xref: /openbmc/linux/drivers/scsi/pm8001/pm8001_sas.h (revision c819e2cf)
1 /*
2  * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
3  *
4  * Copyright (c) 2008-2009 USI Co., Ltd.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions, and the following disclaimer,
12  *    without modification.
13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14  *    substantially similar to the "NO WARRANTY" disclaimer below
15  *    ("Disclaimer") and any redistribution must be conditioned upon
16  *    including a substantially similar Disclaimer requirement for further
17  *    binary redistribution.
18  * 3. Neither the names of the above-listed copyright holders nor the names
19  *    of any contributors may be used to endorse or promote products derived
20  *    from this software without specific prior written permission.
21  *
22  * Alternatively, this software may be distributed under the terms of the
23  * GNU General Public License ("GPL") version 2 as published by the Free
24  * Software Foundation.
25  *
26  * NO WARRANTY
27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37  * POSSIBILITY OF SUCH DAMAGES.
38  *
39  */
40 
41 #ifndef _PM8001_SAS_H_
42 #define _PM8001_SAS_H_
43 
44 #include <linux/kernel.h>
45 #include <linux/module.h>
46 #include <linux/spinlock.h>
47 #include <linux/delay.h>
48 #include <linux/types.h>
49 #include <linux/ctype.h>
50 #include <linux/dma-mapping.h>
51 #include <linux/pci.h>
52 #include <linux/interrupt.h>
53 #include <linux/workqueue.h>
54 #include <scsi/libsas.h>
55 #include <scsi/scsi_tcq.h>
56 #include <scsi/sas_ata.h>
57 #include <linux/atomic.h>
58 #include "pm8001_defs.h"
59 
60 #define DRV_NAME		"pm80xx"
61 #define DRV_VERSION		"0.1.37"
62 #define PM8001_FAIL_LOGGING	0x01 /* Error message logging */
63 #define PM8001_INIT_LOGGING	0x02 /* driver init logging */
64 #define PM8001_DISC_LOGGING	0x04 /* discovery layer logging */
65 #define PM8001_IO_LOGGING	0x08 /* I/O path logging */
66 #define PM8001_EH_LOGGING	0x10 /* libsas EH function logging*/
67 #define PM8001_IOCTL_LOGGING	0x20 /* IOCTL message logging */
68 #define PM8001_MSG_LOGGING	0x40 /* misc message logging */
69 #define pm8001_printk(format, arg...)	printk(KERN_INFO "pm80xx %s %d:" \
70 			format, __func__, __LINE__, ## arg)
71 #define PM8001_CHECK_LOGGING(HBA, LEVEL, CMD)	\
72 do {						\
73 	if (unlikely(HBA->logging_level & LEVEL))	\
74 		do {					\
75 			CMD;				\
76 		} while (0);				\
77 } while (0);
78 
79 #define PM8001_EH_DBG(HBA, CMD)			\
80 	PM8001_CHECK_LOGGING(HBA, PM8001_EH_LOGGING, CMD)
81 
82 #define PM8001_INIT_DBG(HBA, CMD)		\
83 	PM8001_CHECK_LOGGING(HBA, PM8001_INIT_LOGGING, CMD)
84 
85 #define PM8001_DISC_DBG(HBA, CMD)		\
86 	PM8001_CHECK_LOGGING(HBA, PM8001_DISC_LOGGING, CMD)
87 
88 #define PM8001_IO_DBG(HBA, CMD)		\
89 	PM8001_CHECK_LOGGING(HBA, PM8001_IO_LOGGING, CMD)
90 
91 #define PM8001_FAIL_DBG(HBA, CMD)		\
92 	PM8001_CHECK_LOGGING(HBA, PM8001_FAIL_LOGGING, CMD)
93 
94 #define PM8001_IOCTL_DBG(HBA, CMD)		\
95 	PM8001_CHECK_LOGGING(HBA, PM8001_IOCTL_LOGGING, CMD)
96 
97 #define PM8001_MSG_DBG(HBA, CMD)		\
98 	PM8001_CHECK_LOGGING(HBA, PM8001_MSG_LOGGING, CMD)
99 
100 
101 #define PM8001_USE_TASKLET
102 #define PM8001_USE_MSIX
103 #define PM8001_READ_VPD
104 
105 
106 #define DEV_IS_EXPANDER(type)	((type == SAS_EDGE_EXPANDER_DEVICE) || (type == SAS_FANOUT_EXPANDER_DEVICE))
107 #define IS_SPCV_12G(dev)	((dev->device == 0X8074)		\
108 				|| (dev->device == 0X8076)		\
109 				|| (dev->device == 0X8077))
110 
111 #define PM8001_NAME_LENGTH		32/* generic length of strings */
112 extern struct list_head hba_list;
113 extern const struct pm8001_dispatch pm8001_8001_dispatch;
114 extern const struct pm8001_dispatch pm8001_80xx_dispatch;
115 
116 struct pm8001_hba_info;
117 struct pm8001_ccb_info;
118 struct pm8001_device;
119 /* define task management IU */
120 struct pm8001_tmf_task {
121 	u8	tmf;
122 	u32	tag_of_task_to_be_managed;
123 };
124 struct pm8001_ioctl_payload {
125 	u32	signature;
126 	u16	major_function;
127 	u16	minor_function;
128 	u16	length;
129 	u16	status;
130 	u16	offset;
131 	u16	id;
132 	u8	*func_specific;
133 };
134 
135 #define MPI_FATAL_ERROR_TABLE_OFFSET_MASK 0xFFFFFF
136 #define MPI_FATAL_ERROR_TABLE_SIZE(value) ((0xFF000000 & value) >> SHIFT24)
137 #define MPI_FATAL_EDUMP_TABLE_LO_OFFSET            0x00     /* HNFBUFL */
138 #define MPI_FATAL_EDUMP_TABLE_HI_OFFSET            0x04     /* HNFBUFH */
139 #define MPI_FATAL_EDUMP_TABLE_LENGTH               0x08     /* HNFBLEN */
140 #define MPI_FATAL_EDUMP_TABLE_HANDSHAKE            0x0C     /* FDDHSHK */
141 #define MPI_FATAL_EDUMP_TABLE_STATUS               0x10     /* FDDTSTAT */
142 #define MPI_FATAL_EDUMP_TABLE_ACCUM_LEN            0x14     /* ACCDDLEN */
143 #define MPI_FATAL_EDUMP_HANDSHAKE_RDY              0x1
144 #define MPI_FATAL_EDUMP_HANDSHAKE_BUSY             0x0
145 #define MPI_FATAL_EDUMP_TABLE_STAT_RSVD                 0x0
146 #define MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED           0x1
147 #define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA 0x2
148 #define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE      0x3
149 #define TYPE_GSM_SPACE        1
150 #define TYPE_QUEUE            2
151 #define TYPE_FATAL            3
152 #define TYPE_NON_FATAL        4
153 #define TYPE_INBOUND          1
154 #define TYPE_OUTBOUND         2
155 struct forensic_data {
156 	u32  data_type;
157 	union {
158 		struct {
159 			u32  direct_len;
160 			u32  direct_offset;
161 			void  *direct_data;
162 		} gsm_buf;
163 		struct {
164 			u16  queue_type;
165 			u16  queue_index;
166 			u32  direct_len;
167 			void  *direct_data;
168 		} queue_buf;
169 		struct {
170 			u32  direct_len;
171 			u32  direct_offset;
172 			u32  read_len;
173 			void  *direct_data;
174 		} data_buf;
175 	};
176 };
177 
178 /* bit31-26 - mask bar */
179 #define SCRATCH_PAD0_BAR_MASK                    0xFC000000
180 /* bit25-0  - offset mask */
181 #define SCRATCH_PAD0_OFFSET_MASK                 0x03FFFFFF
182 /* if AAP error state */
183 #define SCRATCH_PAD0_AAPERR_MASK                 0xFFFFFFFF
184 /* Inbound doorbell bit7 */
185 #define SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP	 0x80
186 /* Inbound doorbell bit7 SPCV */
187 #define SPCV_MSGU_CFG_TABLE_TRANSFER_DEBUG_INFO  0x80
188 #define MAIN_MERRDCTO_MERRDCES		         0xA0/* DWORD 0x28) */
189 
190 struct pm8001_dispatch {
191 	char *name;
192 	int (*chip_init)(struct pm8001_hba_info *pm8001_ha);
193 	int (*chip_soft_rst)(struct pm8001_hba_info *pm8001_ha);
194 	void (*chip_rst)(struct pm8001_hba_info *pm8001_ha);
195 	int (*chip_ioremap)(struct pm8001_hba_info *pm8001_ha);
196 	void (*chip_iounmap)(struct pm8001_hba_info *pm8001_ha);
197 	irqreturn_t (*isr)(struct pm8001_hba_info *pm8001_ha, u8 vec);
198 	u32 (*is_our_interupt)(struct pm8001_hba_info *pm8001_ha);
199 	int (*isr_process_oq)(struct pm8001_hba_info *pm8001_ha, u8 vec);
200 	void (*interrupt_enable)(struct pm8001_hba_info *pm8001_ha, u8 vec);
201 	void (*interrupt_disable)(struct pm8001_hba_info *pm8001_ha, u8 vec);
202 	void (*make_prd)(struct scatterlist *scatter, int nr, void *prd);
203 	int (*smp_req)(struct pm8001_hba_info *pm8001_ha,
204 		struct pm8001_ccb_info *ccb);
205 	int (*ssp_io_req)(struct pm8001_hba_info *pm8001_ha,
206 		struct pm8001_ccb_info *ccb);
207 	int (*sata_req)(struct pm8001_hba_info *pm8001_ha,
208 		struct pm8001_ccb_info *ccb);
209 	int (*phy_start_req)(struct pm8001_hba_info *pm8001_ha,	u8 phy_id);
210 	int (*phy_stop_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id);
211 	int (*reg_dev_req)(struct pm8001_hba_info *pm8001_ha,
212 		struct pm8001_device *pm8001_dev, u32 flag);
213 	int (*dereg_dev_req)(struct pm8001_hba_info *pm8001_ha, u32 device_id);
214 	int (*phy_ctl_req)(struct pm8001_hba_info *pm8001_ha,
215 		u32 phy_id, u32 phy_op);
216 	int (*task_abort)(struct pm8001_hba_info *pm8001_ha,
217 		struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag,
218 		u32 cmd_tag);
219 	int (*ssp_tm_req)(struct pm8001_hba_info *pm8001_ha,
220 		struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf);
221 	int (*get_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload);
222 	int (*set_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload);
223 	int (*fw_flash_update_req)(struct pm8001_hba_info *pm8001_ha,
224 		void *payload);
225 	int (*set_dev_state_req)(struct pm8001_hba_info *pm8001_ha,
226 		struct pm8001_device *pm8001_dev, u32 state);
227 	int (*sas_diag_start_end_req)(struct pm8001_hba_info *pm8001_ha,
228 		u32 state);
229 	int (*sas_diag_execute_req)(struct pm8001_hba_info *pm8001_ha,
230 		u32 state);
231 	int (*sas_re_init_req)(struct pm8001_hba_info *pm8001_ha);
232 };
233 
234 struct pm8001_chip_info {
235 	u32     encrypt;
236 	u32	n_phy;
237 	const struct pm8001_dispatch	*dispatch;
238 };
239 #define PM8001_CHIP_DISP	(pm8001_ha->chip->dispatch)
240 
241 struct pm8001_port {
242 	struct asd_sas_port	sas_port;
243 	u8			port_attached;
244 	u8			wide_port_phymap;
245 	u8			port_state;
246 	struct list_head	list;
247 };
248 
249 struct pm8001_phy {
250 	struct pm8001_hba_info	*pm8001_ha;
251 	struct pm8001_port	*port;
252 	struct asd_sas_phy	sas_phy;
253 	struct sas_identify	identify;
254 	struct scsi_device	*sdev;
255 	u64			dev_sas_addr;
256 	u32			phy_type;
257 	struct completion	*enable_completion;
258 	u32			frame_rcvd_size;
259 	u8			frame_rcvd[32];
260 	u8			phy_attached;
261 	u8			phy_state;
262 	enum sas_linkrate	minimum_linkrate;
263 	enum sas_linkrate	maximum_linkrate;
264 };
265 
266 struct pm8001_device {
267 	enum sas_device_type	dev_type;
268 	struct domain_device	*sas_device;
269 	u32			attached_phy;
270 	u32			id;
271 	struct completion	*dcompletion;
272 	struct completion	*setds_completion;
273 	u32			device_id;
274 	u32			running_req;
275 };
276 
277 struct pm8001_prd_imt {
278 	__le32			len;
279 	__le32			e;
280 };
281 
282 struct pm8001_prd {
283 	__le64			addr;		/* 64-bit buffer address */
284 	struct pm8001_prd_imt	im_len;		/* 64-bit length */
285 } __attribute__ ((packed));
286 /*
287  * CCB(Command Control Block)
288  */
289 struct pm8001_ccb_info {
290 	struct list_head	entry;
291 	struct sas_task		*task;
292 	u32			n_elem;
293 	u32			ccb_tag;
294 	dma_addr_t		ccb_dma_handle;
295 	struct pm8001_device	*device;
296 	struct pm8001_prd	buf_prd[PM8001_MAX_DMA_SG];
297 	struct fw_control_ex	*fw_control_context;
298 	u8			open_retry;
299 };
300 
301 struct mpi_mem {
302 	void			*virt_ptr;
303 	dma_addr_t		phys_addr;
304 	u32			phys_addr_hi;
305 	u32			phys_addr_lo;
306 	u32			total_len;
307 	u32			num_elements;
308 	u32			element_size;
309 	u32			alignment;
310 };
311 
312 struct mpi_mem_req {
313 	/* The number of element in the  mpiMemory array */
314 	u32			count;
315 	/* The array of structures that define memroy regions*/
316 	struct mpi_mem		region[USI_MAX_MEMCNT];
317 };
318 
319 struct encrypt {
320 	u32	cipher_mode;
321 	u32	sec_mode;
322 	u32	status;
323 	u32	flag;
324 };
325 
326 struct sas_phy_attribute_table {
327 	u32	phystart1_16[16];
328 	u32	outbound_hw_event_pid1_16[16];
329 };
330 
331 union main_cfg_table {
332 	struct {
333 	u32			signature;
334 	u32			interface_rev;
335 	u32			firmware_rev;
336 	u32			max_out_io;
337 	u32			max_sgl;
338 	u32			ctrl_cap_flag;
339 	u32			gst_offset;
340 	u32			inbound_queue_offset;
341 	u32			outbound_queue_offset;
342 	u32			inbound_q_nppd_hppd;
343 	u32			outbound_hw_event_pid0_3;
344 	u32			outbound_hw_event_pid4_7;
345 	u32			outbound_ncq_event_pid0_3;
346 	u32			outbound_ncq_event_pid4_7;
347 	u32			outbound_tgt_ITNexus_event_pid0_3;
348 	u32			outbound_tgt_ITNexus_event_pid4_7;
349 	u32			outbound_tgt_ssp_event_pid0_3;
350 	u32			outbound_tgt_ssp_event_pid4_7;
351 	u32			outbound_tgt_smp_event_pid0_3;
352 	u32			outbound_tgt_smp_event_pid4_7;
353 	u32			upper_event_log_addr;
354 	u32			lower_event_log_addr;
355 	u32			event_log_size;
356 	u32			event_log_option;
357 	u32			upper_iop_event_log_addr;
358 	u32			lower_iop_event_log_addr;
359 	u32			iop_event_log_size;
360 	u32			iop_event_log_option;
361 	u32			fatal_err_interrupt;
362 	u32			fatal_err_dump_offset0;
363 	u32			fatal_err_dump_length0;
364 	u32			fatal_err_dump_offset1;
365 	u32			fatal_err_dump_length1;
366 	u32			hda_mode_flag;
367 	u32			anolog_setup_table_offset;
368 	u32			rsvd[4];
369 	} pm8001_tbl;
370 
371 	struct {
372 	u32			signature;
373 	u32			interface_rev;
374 	u32			firmware_rev;
375 	u32			max_out_io;
376 	u32			max_sgl;
377 	u32			ctrl_cap_flag;
378 	u32			gst_offset;
379 	u32			inbound_queue_offset;
380 	u32			outbound_queue_offset;
381 	u32			inbound_q_nppd_hppd;
382 	u32			rsvd[8];
383 	u32			crc_core_dump;
384 	u32			rsvd1;
385 	u32			upper_event_log_addr;
386 	u32			lower_event_log_addr;
387 	u32			event_log_size;
388 	u32			event_log_severity;
389 	u32			upper_pcs_event_log_addr;
390 	u32			lower_pcs_event_log_addr;
391 	u32			pcs_event_log_size;
392 	u32			pcs_event_log_severity;
393 	u32			fatal_err_interrupt;
394 	u32			fatal_err_dump_offset0;
395 	u32			fatal_err_dump_length0;
396 	u32			fatal_err_dump_offset1;
397 	u32			fatal_err_dump_length1;
398 	u32			gpio_led_mapping;
399 	u32			analog_setup_table_offset;
400 	u32			int_vec_table_offset;
401 	u32			phy_attr_table_offset;
402 	u32			port_recovery_timer;
403 	u32			interrupt_reassertion_delay;
404 	u32			fatal_n_non_fatal_dump;	        /* 0x28 */
405 	} pm80xx_tbl;
406 };
407 
408 union general_status_table {
409 	struct {
410 	u32			gst_len_mpistate;
411 	u32			iq_freeze_state0;
412 	u32			iq_freeze_state1;
413 	u32			msgu_tcnt;
414 	u32			iop_tcnt;
415 	u32			rsvd;
416 	u32			phy_state[8];
417 	u32			gpio_input_val;
418 	u32			rsvd1[2];
419 	u32			recover_err_info[8];
420 	} pm8001_tbl;
421 	struct {
422 	u32			gst_len_mpistate;
423 	u32			iq_freeze_state0;
424 	u32			iq_freeze_state1;
425 	u32			msgu_tcnt;
426 	u32			iop_tcnt;
427 	u32			rsvd[9];
428 	u32			gpio_input_val;
429 	u32			rsvd1[2];
430 	u32			recover_err_info[8];
431 	} pm80xx_tbl;
432 };
433 struct inbound_queue_table {
434 	u32			element_pri_size_cnt;
435 	u32			upper_base_addr;
436 	u32			lower_base_addr;
437 	u32			ci_upper_base_addr;
438 	u32			ci_lower_base_addr;
439 	u32			pi_pci_bar;
440 	u32			pi_offset;
441 	u32			total_length;
442 	void			*base_virt;
443 	void			*ci_virt;
444 	u32			reserved;
445 	__le32			consumer_index;
446 	u32			producer_idx;
447 };
448 struct outbound_queue_table {
449 	u32			element_size_cnt;
450 	u32			upper_base_addr;
451 	u32			lower_base_addr;
452 	void			*base_virt;
453 	u32			pi_upper_base_addr;
454 	u32			pi_lower_base_addr;
455 	u32			ci_pci_bar;
456 	u32			ci_offset;
457 	u32			total_length;
458 	void			*pi_virt;
459 	u32			interrup_vec_cnt_delay;
460 	u32			dinterrup_to_pci_offset;
461 	__le32			producer_index;
462 	u32			consumer_idx;
463 };
464 struct pm8001_hba_memspace {
465 	void __iomem  		*memvirtaddr;
466 	u64			membase;
467 	u32			memsize;
468 };
469 struct isr_param {
470 	struct pm8001_hba_info *drv_inst;
471 	u32 irq_id;
472 };
473 struct pm8001_hba_info {
474 	char			name[PM8001_NAME_LENGTH];
475 	struct list_head	list;
476 	unsigned long		flags;
477 	spinlock_t		lock;/* host-wide lock */
478 	spinlock_t		bitmap_lock;
479 	struct pci_dev		*pdev;/* our device */
480 	struct device		*dev;
481 	struct pm8001_hba_memspace io_mem[6];
482 	struct mpi_mem_req	memoryMap;
483 	struct encrypt		encrypt_info; /* support encryption */
484 	struct forensic_data	forensic_info;
485 	u32			fatal_bar_loc;
486 	u32			forensic_last_offset;
487 	u32			fatal_forensic_shift_offset;
488 	u32			forensic_fatal_step;
489 	u32			evtlog_ib_offset;
490 	u32			evtlog_ob_offset;
491 	void __iomem	*msg_unit_tbl_addr;/*Message Unit Table Addr*/
492 	void __iomem	*main_cfg_tbl_addr;/*Main Config Table Addr*/
493 	void __iomem	*general_stat_tbl_addr;/*General Status Table Addr*/
494 	void __iomem	*inbnd_q_tbl_addr;/*Inbound Queue Config Table Addr*/
495 	void __iomem	*outbnd_q_tbl_addr;/*Outbound Queue Config Table Addr*/
496 	void __iomem	*pspa_q_tbl_addr;
497 			/*MPI SAS PHY attributes Queue Config Table Addr*/
498 	void __iomem	*ivt_tbl_addr; /*MPI IVT Table Addr */
499 	void __iomem	*fatal_tbl_addr; /*MPI IVT Table Addr */
500 	union main_cfg_table	main_cfg_tbl;
501 	union general_status_table	gs_tbl;
502 	struct inbound_queue_table	inbnd_q_tbl[PM8001_MAX_SPCV_INB_NUM];
503 	struct outbound_queue_table	outbnd_q_tbl[PM8001_MAX_SPCV_OUTB_NUM];
504 	struct sas_phy_attribute_table	phy_attr_table;
505 					/* MPI SAS PHY attributes */
506 	u8			sas_addr[SAS_ADDR_SIZE];
507 	struct sas_ha_struct	*sas;/* SCSI/SAS glue */
508 	struct Scsi_Host	*shost;
509 	u32			chip_id;
510 	const struct pm8001_chip_info	*chip;
511 	struct completion	*nvmd_completion;
512 	int			tags_num;
513 	unsigned long		*tags;
514 	struct pm8001_phy	phy[PM8001_MAX_PHYS];
515 	struct pm8001_port	port[PM8001_MAX_PHYS];
516 	u32			id;
517 	u32			irq;
518 	u32			iomb_size; /* SPC and SPCV IOMB size */
519 	struct pm8001_device	*devices;
520 	struct pm8001_ccb_info	*ccb_info;
521 #ifdef PM8001_USE_MSIX
522 	struct msix_entry	msix_entries[PM8001_MAX_MSIX_VEC];
523 					/*for msi-x interrupt*/
524 	int			number_of_intr;/*will be used in remove()*/
525 #endif
526 #ifdef PM8001_USE_TASKLET
527 	struct tasklet_struct	tasklet[PM8001_MAX_MSIX_VEC];
528 #endif
529 	u32			logging_level;
530 	u32			fw_status;
531 	u32			smp_exp_mode;
532 	const struct firmware 	*fw_image;
533 	struct isr_param irq_vector[PM8001_MAX_MSIX_VEC];
534 };
535 
536 struct pm8001_work {
537 	struct work_struct work;
538 	struct pm8001_hba_info *pm8001_ha;
539 	void *data;
540 	int handler;
541 };
542 
543 struct pm8001_fw_image_header {
544 	u8 vender_id[8];
545 	u8 product_id;
546 	u8 hardware_rev;
547 	u8 dest_partition;
548 	u8 reserved;
549 	u8 fw_rev[4];
550 	__be32  image_length;
551 	__be32 image_crc;
552 	__be32 startup_entry;
553 } __attribute__((packed, aligned(4)));
554 
555 
556 /**
557  * FW Flash Update status values
558  */
559 #define FLASH_UPDATE_COMPLETE_PENDING_REBOOT	0x00
560 #define FLASH_UPDATE_IN_PROGRESS		0x01
561 #define FLASH_UPDATE_HDR_ERR			0x02
562 #define FLASH_UPDATE_OFFSET_ERR			0x03
563 #define FLASH_UPDATE_CRC_ERR			0x04
564 #define FLASH_UPDATE_LENGTH_ERR			0x05
565 #define FLASH_UPDATE_HW_ERR			0x06
566 #define FLASH_UPDATE_DNLD_NOT_SUPPORTED		0x10
567 #define FLASH_UPDATE_DISABLED			0x11
568 
569 #define	NCQ_READ_LOG_FLAG			0x80000000
570 #define	NCQ_ABORT_ALL_FLAG			0x40000000
571 #define	NCQ_2ND_RLE_FLAG			0x20000000
572 /**
573  * brief param structure for firmware flash update.
574  */
575 struct fw_flash_updata_info {
576 	u32			cur_image_offset;
577 	u32			cur_image_len;
578 	u32			total_image_len;
579 	struct pm8001_prd	sgl;
580 };
581 
582 struct fw_control_info {
583 	u32			retcode;/*ret code (status)*/
584 	u32			phase;/*ret code phase*/
585 	u32			phaseCmplt;/*percent complete for the current
586 	update phase */
587 	u32			version;/*Hex encoded firmware version number*/
588 	u32			offset;/*Used for downloading firmware	*/
589 	u32			len; /*len of buffer*/
590 	u32			size;/* Used in OS VPD and Trace get size
591 	operations.*/
592 	u32			reserved;/* padding required for 64 bit
593 	alignment */
594 	u8			buffer[1];/* Start of buffer */
595 };
596 struct fw_control_ex {
597 	struct fw_control_info *fw_control;
598 	void			*buffer;/* keep buffer pointer to be
599 	freed when the response comes*/
600 	void			*virtAddr;/* keep virtual address of the data */
601 	void			*usrAddr;/* keep virtual address of the
602 	user data */
603 	dma_addr_t		phys_addr;
604 	u32			len; /* len of buffer  */
605 	void			*payload; /* pointer to IOCTL Payload */
606 	u8			inProgress;/*if 1 - the IOCTL request is in
607 	progress */
608 	void			*param1;
609 	void			*param2;
610 	void			*param3;
611 };
612 
613 /* pm8001 workqueue */
614 extern struct workqueue_struct *pm8001_wq;
615 
616 /******************** function prototype *********************/
617 int pm8001_tag_alloc(struct pm8001_hba_info *pm8001_ha, u32 *tag_out);
618 void pm8001_tag_init(struct pm8001_hba_info *pm8001_ha);
619 u32 pm8001_get_ncq_tag(struct sas_task *task, u32 *tag);
620 void pm8001_ccb_task_free(struct pm8001_hba_info *pm8001_ha,
621 	struct sas_task *task, struct pm8001_ccb_info *ccb, u32 ccb_idx);
622 int pm8001_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
623 	void *funcdata);
624 void pm8001_scan_start(struct Scsi_Host *shost);
625 int pm8001_scan_finished(struct Scsi_Host *shost, unsigned long time);
626 int pm8001_queue_command(struct sas_task *task, gfp_t gfp_flags);
627 int pm8001_abort_task(struct sas_task *task);
628 int pm8001_abort_task_set(struct domain_device *dev, u8 *lun);
629 int pm8001_clear_aca(struct domain_device *dev, u8 *lun);
630 int pm8001_clear_task_set(struct domain_device *dev, u8 *lun);
631 int pm8001_dev_found(struct domain_device *dev);
632 void pm8001_dev_gone(struct domain_device *dev);
633 int pm8001_lu_reset(struct domain_device *dev, u8 *lun);
634 int pm8001_I_T_nexus_reset(struct domain_device *dev);
635 int pm8001_I_T_nexus_event_handler(struct domain_device *dev);
636 int pm8001_query_task(struct sas_task *task);
637 void pm8001_open_reject_retry(
638 	struct pm8001_hba_info *pm8001_ha,
639 	struct sas_task *task_to_close,
640 	struct pm8001_device *device_to_close);
641 int pm8001_mem_alloc(struct pci_dev *pdev, void **virt_addr,
642 	dma_addr_t *pphys_addr, u32 *pphys_addr_hi, u32 *pphys_addr_lo,
643 	u32 mem_size, u32 align);
644 
645 void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha);
646 int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
647 			struct inbound_queue_table *circularQ,
648 			u32 opCode, void *payload, u32 responseQueue);
649 int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ,
650 				u16 messageSize, void **messagePtr);
651 u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
652 			struct outbound_queue_table *circularQ, u8 bc);
653 u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
654 			struct outbound_queue_table *circularQ,
655 			void **messagePtr1, u8 *pBC);
656 int pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
657 			struct pm8001_device *pm8001_dev, u32 state);
658 int pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
659 					void *payload);
660 int pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
661 					void *fw_flash_updata_info, u32 tag);
662 int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha, void *payload);
663 int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha, void *payload);
664 int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
665 				struct pm8001_ccb_info *ccb,
666 				struct pm8001_tmf_task *tmf);
667 int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
668 				struct pm8001_device *pm8001_dev,
669 				u8 flag, u32 task_tag, u32 cmd_tag);
670 int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha, u32 device_id);
671 void pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd);
672 void pm8001_work_fn(struct work_struct *work);
673 int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha,
674 					void *data, int handler);
675 void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha,
676 							void *piomb);
677 void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha,
678 							void *piomb);
679 void pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha,
680 							void *piomb);
681 int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha,
682 							void *piomb);
683 void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate);
684 void pm8001_get_attached_sas_addr(struct pm8001_phy *phy, u8 *sas_addr);
685 void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i);
686 int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
687 int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
688 int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha,
689 							void *piomb);
690 int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb);
691 int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
692 struct sas_task *pm8001_alloc_task(void);
693 void pm8001_task_done(struct sas_task *task);
694 void pm8001_free_task(struct sas_task *task);
695 void pm8001_tag_free(struct pm8001_hba_info *pm8001_ha, u32 tag);
696 struct pm8001_device *pm8001_find_dev(struct pm8001_hba_info *pm8001_ha,
697 					u32 device_id);
698 int pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha);
699 
700 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
701 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
702 	u32 length, u8 *buf);
703 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
704 ssize_t pm80xx_get_fatal_dump(struct device *cdev,
705 		struct device_attribute *attr, char *buf);
706 ssize_t pm8001_get_gsm_dump(struct device *cdev, u32, char *buf);
707 /* ctl shared API */
708 extern struct device_attribute *pm8001_host_attrs[];
709 
710 static inline void
711 pm8001_ccb_task_free_done(struct pm8001_hba_info *pm8001_ha,
712 			struct sas_task *task, struct pm8001_ccb_info *ccb,
713 			u32 ccb_idx)
714 {
715 	pm8001_ccb_task_free(pm8001_ha, task, ccb, ccb_idx);
716 	smp_mb(); /*in order to force CPU ordering*/
717 	spin_unlock(&pm8001_ha->lock);
718 	task->task_done(task);
719 	spin_lock(&pm8001_ha->lock);
720 }
721 
722 #endif
723 
724