1 /* 2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 USI Co., Ltd. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 41 #ifndef _PM8001_SAS_H_ 42 #define _PM8001_SAS_H_ 43 44 #include <linux/kernel.h> 45 #include <linux/module.h> 46 #include <linux/spinlock.h> 47 #include <linux/delay.h> 48 #include <linux/types.h> 49 #include <linux/ctype.h> 50 #include <linux/dma-mapping.h> 51 #include <linux/pci.h> 52 #include <linux/interrupt.h> 53 #include <linux/workqueue.h> 54 #include <scsi/libsas.h> 55 #include <scsi/scsi_tcq.h> 56 #include <scsi/sas_ata.h> 57 #include <linux/atomic.h> 58 #include "pm8001_defs.h" 59 60 #define DRV_NAME "pm80xx" 61 #define DRV_VERSION "0.1.40" 62 #define PM8001_FAIL_LOGGING 0x01 /* Error message logging */ 63 #define PM8001_INIT_LOGGING 0x02 /* driver init logging */ 64 #define PM8001_DISC_LOGGING 0x04 /* discovery layer logging */ 65 #define PM8001_IO_LOGGING 0x08 /* I/O path logging */ 66 #define PM8001_EH_LOGGING 0x10 /* libsas EH function logging*/ 67 #define PM8001_IOCTL_LOGGING 0x20 /* IOCTL message logging */ 68 #define PM8001_MSG_LOGGING 0x40 /* misc message logging */ 69 #define PM8001_DEV_LOGGING 0x80 /* development message logging */ 70 #define PM8001_DEVIO_LOGGING 0x100 /* development io message logging */ 71 #define PM8001_IOERR_LOGGING 0x200 /* development io err message logging */ 72 73 #define pm8001_info(HBA, fmt, ...) \ 74 pr_info("%s:: %s %d:" fmt, \ 75 (HBA)->name, __func__, __LINE__, ##__VA_ARGS__) 76 77 #define pm8001_dbg(HBA, level, fmt, ...) \ 78 do { \ 79 if (unlikely((HBA)->logging_level & PM8001_##level##_LOGGING)) \ 80 pm8001_info(HBA, fmt, ##__VA_ARGS__); \ 81 } while (0) 82 83 #define PM8001_USE_TASKLET 84 #define PM8001_USE_MSIX 85 #define PM8001_READ_VPD 86 87 88 #define IS_SPCV_12G(dev) ((dev->device == 0X8074) \ 89 || (dev->device == 0X8076) \ 90 || (dev->device == 0X8077) \ 91 || (dev->device == 0X8070) \ 92 || (dev->device == 0X8072)) 93 94 #define PM8001_NAME_LENGTH 32/* generic length of strings */ 95 extern struct list_head hba_list; 96 extern const struct pm8001_dispatch pm8001_8001_dispatch; 97 extern const struct pm8001_dispatch pm8001_80xx_dispatch; 98 99 struct pm8001_hba_info; 100 struct pm8001_ccb_info; 101 struct pm8001_device; 102 /* define task management IU */ 103 struct pm8001_tmf_task { 104 u8 tmf; 105 u32 tag_of_task_to_be_managed; 106 }; 107 struct pm8001_ioctl_payload { 108 u32 signature; 109 u16 major_function; 110 u16 minor_function; 111 u16 status; 112 u16 offset; 113 u16 id; 114 u32 wr_length; 115 u32 rd_length; 116 u8 *func_specific; 117 }; 118 119 #define MPI_FATAL_ERROR_TABLE_OFFSET_MASK 0xFFFFFF 120 #define MPI_FATAL_ERROR_TABLE_SIZE(value) ((0xFF000000 & value) >> SHIFT24) 121 #define MPI_FATAL_EDUMP_TABLE_LO_OFFSET 0x00 /* HNFBUFL */ 122 #define MPI_FATAL_EDUMP_TABLE_HI_OFFSET 0x04 /* HNFBUFH */ 123 #define MPI_FATAL_EDUMP_TABLE_LENGTH 0x08 /* HNFBLEN */ 124 #define MPI_FATAL_EDUMP_TABLE_HANDSHAKE 0x0C /* FDDHSHK */ 125 #define MPI_FATAL_EDUMP_TABLE_STATUS 0x10 /* FDDTSTAT */ 126 #define MPI_FATAL_EDUMP_TABLE_ACCUM_LEN 0x14 /* ACCDDLEN */ 127 #define MPI_FATAL_EDUMP_TABLE_TOTAL_LEN 0x18 /* TOTALLEN */ 128 #define MPI_FATAL_EDUMP_TABLE_SIGNATURE 0x1C /* SIGNITURE */ 129 #define MPI_FATAL_EDUMP_HANDSHAKE_RDY 0x1 130 #define MPI_FATAL_EDUMP_HANDSHAKE_BUSY 0x0 131 #define MPI_FATAL_EDUMP_TABLE_STAT_RSVD 0x0 132 #define MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED 0x1 133 #define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA 0x2 134 #define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE 0x3 135 #define TYPE_GSM_SPACE 1 136 #define TYPE_QUEUE 2 137 #define TYPE_FATAL 3 138 #define TYPE_NON_FATAL 4 139 #define TYPE_INBOUND 1 140 #define TYPE_OUTBOUND 2 141 struct forensic_data { 142 u32 data_type; 143 union { 144 struct { 145 u32 direct_len; 146 u32 direct_offset; 147 void *direct_data; 148 } gsm_buf; 149 struct { 150 u16 queue_type; 151 u16 queue_index; 152 u32 direct_len; 153 void *direct_data; 154 } queue_buf; 155 struct { 156 u32 direct_len; 157 u32 direct_offset; 158 u32 read_len; 159 void *direct_data; 160 } data_buf; 161 }; 162 }; 163 164 /* bit31-26 - mask bar */ 165 #define SCRATCH_PAD0_BAR_MASK 0xFC000000 166 /* bit25-0 - offset mask */ 167 #define SCRATCH_PAD0_OFFSET_MASK 0x03FFFFFF 168 /* if AAP error state */ 169 #define SCRATCH_PAD0_AAPERR_MASK 0xFFFFFFFF 170 /* Inbound doorbell bit7 */ 171 #define SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP 0x80 172 /* Inbound doorbell bit7 SPCV */ 173 #define SPCV_MSGU_CFG_TABLE_TRANSFER_DEBUG_INFO 0x80 174 #define MAIN_MERRDCTO_MERRDCES 0xA0/* DWORD 0x28) */ 175 176 struct pm8001_dispatch { 177 char *name; 178 int (*chip_init)(struct pm8001_hba_info *pm8001_ha); 179 int (*chip_soft_rst)(struct pm8001_hba_info *pm8001_ha); 180 void (*chip_rst)(struct pm8001_hba_info *pm8001_ha); 181 int (*chip_ioremap)(struct pm8001_hba_info *pm8001_ha); 182 void (*chip_iounmap)(struct pm8001_hba_info *pm8001_ha); 183 irqreturn_t (*isr)(struct pm8001_hba_info *pm8001_ha, u8 vec); 184 u32 (*is_our_interrupt)(struct pm8001_hba_info *pm8001_ha); 185 int (*isr_process_oq)(struct pm8001_hba_info *pm8001_ha, u8 vec); 186 void (*interrupt_enable)(struct pm8001_hba_info *pm8001_ha, u8 vec); 187 void (*interrupt_disable)(struct pm8001_hba_info *pm8001_ha, u8 vec); 188 void (*make_prd)(struct scatterlist *scatter, int nr, void *prd); 189 int (*smp_req)(struct pm8001_hba_info *pm8001_ha, 190 struct pm8001_ccb_info *ccb); 191 int (*ssp_io_req)(struct pm8001_hba_info *pm8001_ha, 192 struct pm8001_ccb_info *ccb); 193 int (*sata_req)(struct pm8001_hba_info *pm8001_ha, 194 struct pm8001_ccb_info *ccb); 195 int (*phy_start_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id); 196 int (*phy_stop_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id); 197 int (*reg_dev_req)(struct pm8001_hba_info *pm8001_ha, 198 struct pm8001_device *pm8001_dev, u32 flag); 199 int (*dereg_dev_req)(struct pm8001_hba_info *pm8001_ha, u32 device_id); 200 int (*phy_ctl_req)(struct pm8001_hba_info *pm8001_ha, 201 u32 phy_id, u32 phy_op); 202 int (*task_abort)(struct pm8001_hba_info *pm8001_ha, 203 struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, 204 u32 cmd_tag); 205 int (*ssp_tm_req)(struct pm8001_hba_info *pm8001_ha, 206 struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf); 207 int (*get_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload); 208 int (*set_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload); 209 int (*fw_flash_update_req)(struct pm8001_hba_info *pm8001_ha, 210 void *payload); 211 int (*set_dev_state_req)(struct pm8001_hba_info *pm8001_ha, 212 struct pm8001_device *pm8001_dev, u32 state); 213 int (*sas_diag_start_end_req)(struct pm8001_hba_info *pm8001_ha, 214 u32 state); 215 int (*sas_diag_execute_req)(struct pm8001_hba_info *pm8001_ha, 216 u32 state); 217 int (*sas_re_init_req)(struct pm8001_hba_info *pm8001_ha); 218 int (*fatal_errors)(struct pm8001_hba_info *pm8001_ha); 219 }; 220 221 struct pm8001_chip_info { 222 u32 encrypt; 223 u32 n_phy; 224 const struct pm8001_dispatch *dispatch; 225 }; 226 #define PM8001_CHIP_DISP (pm8001_ha->chip->dispatch) 227 228 struct pm8001_port { 229 struct asd_sas_port sas_port; 230 u8 port_attached; 231 u16 wide_port_phymap; 232 u8 port_state; 233 u8 port_id; 234 struct list_head list; 235 }; 236 237 struct pm8001_phy { 238 struct pm8001_hba_info *pm8001_ha; 239 struct pm8001_port *port; 240 struct asd_sas_phy sas_phy; 241 struct sas_identify identify; 242 struct scsi_device *sdev; 243 u64 dev_sas_addr; 244 u32 phy_type; 245 struct completion *enable_completion; 246 u32 frame_rcvd_size; 247 u8 frame_rcvd[32]; 248 u8 phy_attached; 249 u8 phy_state; 250 enum sas_linkrate minimum_linkrate; 251 enum sas_linkrate maximum_linkrate; 252 struct completion *reset_completion; 253 bool port_reset_status; 254 bool reset_success; 255 }; 256 257 /* port reset status */ 258 #define PORT_RESET_SUCCESS 0x00 259 #define PORT_RESET_TMO 0x01 260 261 struct pm8001_device { 262 enum sas_device_type dev_type; 263 struct domain_device *sas_device; 264 u32 attached_phy; 265 u32 id; 266 struct completion *dcompletion; 267 struct completion *setds_completion; 268 u32 device_id; 269 atomic_t running_req; 270 }; 271 272 struct pm8001_prd_imt { 273 __le32 len; 274 __le32 e; 275 }; 276 277 struct pm8001_prd { 278 __le64 addr; /* 64-bit buffer address */ 279 struct pm8001_prd_imt im_len; /* 64-bit length */ 280 } __attribute__ ((packed)); 281 /* 282 * CCB(Command Control Block) 283 */ 284 struct pm8001_ccb_info { 285 struct sas_task *task; 286 u32 n_elem; 287 u32 ccb_tag; 288 dma_addr_t ccb_dma_handle; 289 struct pm8001_device *device; 290 struct pm8001_prd *buf_prd; 291 struct fw_control_ex *fw_control_context; 292 u8 open_retry; 293 }; 294 295 struct mpi_mem { 296 void *virt_ptr; 297 dma_addr_t phys_addr; 298 u32 phys_addr_hi; 299 u32 phys_addr_lo; 300 u32 total_len; 301 u32 num_elements; 302 u32 element_size; 303 u32 alignment; 304 }; 305 306 struct mpi_mem_req { 307 /* The number of element in the mpiMemory array */ 308 u32 count; 309 /* The array of structures that define memroy regions*/ 310 struct mpi_mem region[USI_MAX_MEMCNT]; 311 }; 312 313 struct encrypt { 314 u32 cipher_mode; 315 u32 sec_mode; 316 u32 status; 317 u32 flag; 318 }; 319 320 struct sas_phy_attribute_table { 321 u32 phystart1_16[16]; 322 u32 outbound_hw_event_pid1_16[16]; 323 }; 324 325 union main_cfg_table { 326 struct { 327 u32 signature; 328 u32 interface_rev; 329 u32 firmware_rev; 330 u32 max_out_io; 331 u32 max_sgl; 332 u32 ctrl_cap_flag; 333 u32 gst_offset; 334 u32 inbound_queue_offset; 335 u32 outbound_queue_offset; 336 u32 inbound_q_nppd_hppd; 337 u32 outbound_hw_event_pid0_3; 338 u32 outbound_hw_event_pid4_7; 339 u32 outbound_ncq_event_pid0_3; 340 u32 outbound_ncq_event_pid4_7; 341 u32 outbound_tgt_ITNexus_event_pid0_3; 342 u32 outbound_tgt_ITNexus_event_pid4_7; 343 u32 outbound_tgt_ssp_event_pid0_3; 344 u32 outbound_tgt_ssp_event_pid4_7; 345 u32 outbound_tgt_smp_event_pid0_3; 346 u32 outbound_tgt_smp_event_pid4_7; 347 u32 upper_event_log_addr; 348 u32 lower_event_log_addr; 349 u32 event_log_size; 350 u32 event_log_option; 351 u32 upper_iop_event_log_addr; 352 u32 lower_iop_event_log_addr; 353 u32 iop_event_log_size; 354 u32 iop_event_log_option; 355 u32 fatal_err_interrupt; 356 u32 fatal_err_dump_offset0; 357 u32 fatal_err_dump_length0; 358 u32 fatal_err_dump_offset1; 359 u32 fatal_err_dump_length1; 360 u32 hda_mode_flag; 361 u32 anolog_setup_table_offset; 362 u32 rsvd[4]; 363 } pm8001_tbl; 364 365 struct { 366 u32 signature; 367 u32 interface_rev; 368 u32 firmware_rev; 369 u32 max_out_io; 370 u32 max_sgl; 371 u32 ctrl_cap_flag; 372 u32 gst_offset; 373 u32 inbound_queue_offset; 374 u32 outbound_queue_offset; 375 u32 inbound_q_nppd_hppd; 376 u32 rsvd[8]; 377 u32 crc_core_dump; 378 u32 rsvd1; 379 u32 upper_event_log_addr; 380 u32 lower_event_log_addr; 381 u32 event_log_size; 382 u32 event_log_severity; 383 u32 upper_pcs_event_log_addr; 384 u32 lower_pcs_event_log_addr; 385 u32 pcs_event_log_size; 386 u32 pcs_event_log_severity; 387 u32 fatal_err_interrupt; 388 u32 fatal_err_dump_offset0; 389 u32 fatal_err_dump_length0; 390 u32 fatal_err_dump_offset1; 391 u32 fatal_err_dump_length1; 392 u32 gpio_led_mapping; 393 u32 analog_setup_table_offset; 394 u32 int_vec_table_offset; 395 u32 phy_attr_table_offset; 396 u32 port_recovery_timer; 397 u32 interrupt_reassertion_delay; 398 u32 fatal_n_non_fatal_dump; /* 0x28 */ 399 u32 ila_version; 400 u32 inc_fw_version; 401 } pm80xx_tbl; 402 }; 403 404 union general_status_table { 405 struct { 406 u32 gst_len_mpistate; 407 u32 iq_freeze_state0; 408 u32 iq_freeze_state1; 409 u32 msgu_tcnt; 410 u32 iop_tcnt; 411 u32 rsvd; 412 u32 phy_state[8]; 413 u32 gpio_input_val; 414 u32 rsvd1[2]; 415 u32 recover_err_info[8]; 416 } pm8001_tbl; 417 struct { 418 u32 gst_len_mpistate; 419 u32 iq_freeze_state0; 420 u32 iq_freeze_state1; 421 u32 msgu_tcnt; 422 u32 iop_tcnt; 423 u32 rsvd[9]; 424 u32 gpio_input_val; 425 u32 rsvd1[2]; 426 u32 recover_err_info[8]; 427 } pm80xx_tbl; 428 }; 429 struct inbound_queue_table { 430 u32 element_pri_size_cnt; 431 u32 upper_base_addr; 432 u32 lower_base_addr; 433 u32 ci_upper_base_addr; 434 u32 ci_lower_base_addr; 435 u32 pi_pci_bar; 436 u32 pi_offset; 437 u32 total_length; 438 void *base_virt; 439 void *ci_virt; 440 u32 reserved; 441 __le32 consumer_index; 442 u32 producer_idx; 443 spinlock_t iq_lock; 444 }; 445 struct outbound_queue_table { 446 u32 element_size_cnt; 447 u32 upper_base_addr; 448 u32 lower_base_addr; 449 void *base_virt; 450 u32 pi_upper_base_addr; 451 u32 pi_lower_base_addr; 452 u32 ci_pci_bar; 453 u32 ci_offset; 454 u32 total_length; 455 void *pi_virt; 456 u32 interrup_vec_cnt_delay; 457 u32 dinterrup_to_pci_offset; 458 __le32 producer_index; 459 u32 consumer_idx; 460 spinlock_t oq_lock; 461 unsigned long lock_flags; 462 }; 463 struct pm8001_hba_memspace { 464 void __iomem *memvirtaddr; 465 u64 membase; 466 u32 memsize; 467 }; 468 struct isr_param { 469 struct pm8001_hba_info *drv_inst; 470 u32 irq_id; 471 }; 472 struct pm8001_hba_info { 473 char name[PM8001_NAME_LENGTH]; 474 struct list_head list; 475 unsigned long flags; 476 spinlock_t lock;/* host-wide lock */ 477 spinlock_t bitmap_lock; 478 struct pci_dev *pdev;/* our device */ 479 struct device *dev; 480 struct pm8001_hba_memspace io_mem[6]; 481 struct mpi_mem_req memoryMap; 482 struct encrypt encrypt_info; /* support encryption */ 483 struct forensic_data forensic_info; 484 u32 fatal_bar_loc; 485 u32 forensic_last_offset; 486 u32 fatal_forensic_shift_offset; 487 u32 forensic_fatal_step; 488 u32 forensic_preserved_accumulated_transfer; 489 u32 evtlog_ib_offset; 490 u32 evtlog_ob_offset; 491 void __iomem *msg_unit_tbl_addr;/*Message Unit Table Addr*/ 492 void __iomem *main_cfg_tbl_addr;/*Main Config Table Addr*/ 493 void __iomem *general_stat_tbl_addr;/*General Status Table Addr*/ 494 void __iomem *inbnd_q_tbl_addr;/*Inbound Queue Config Table Addr*/ 495 void __iomem *outbnd_q_tbl_addr;/*Outbound Queue Config Table Addr*/ 496 void __iomem *pspa_q_tbl_addr; 497 /*MPI SAS PHY attributes Queue Config Table Addr*/ 498 void __iomem *ivt_tbl_addr; /*MPI IVT Table Addr */ 499 void __iomem *fatal_tbl_addr; /*MPI IVT Table Addr */ 500 union main_cfg_table main_cfg_tbl; 501 union general_status_table gs_tbl; 502 struct inbound_queue_table inbnd_q_tbl[PM8001_MAX_INB_NUM]; 503 struct outbound_queue_table outbnd_q_tbl[PM8001_MAX_OUTB_NUM]; 504 struct sas_phy_attribute_table phy_attr_table; 505 /* MPI SAS PHY attributes */ 506 u8 sas_addr[SAS_ADDR_SIZE]; 507 struct sas_ha_struct *sas;/* SCSI/SAS glue */ 508 struct Scsi_Host *shost; 509 u32 chip_id; 510 const struct pm8001_chip_info *chip; 511 struct completion *nvmd_completion; 512 int tags_num; 513 unsigned long *tags; 514 struct pm8001_phy phy[PM8001_MAX_PHYS]; 515 struct pm8001_port port[PM8001_MAX_PHYS]; 516 u32 id; 517 u32 irq; 518 u32 iomb_size; /* SPC and SPCV IOMB size */ 519 struct pm8001_device *devices; 520 struct pm8001_ccb_info *ccb_info; 521 u32 ccb_count; 522 #ifdef PM8001_USE_MSIX 523 int number_of_intr;/*will be used in remove()*/ 524 char intr_drvname[PM8001_MAX_MSIX_VEC] 525 [PM8001_NAME_LENGTH+1+3+1]; 526 #endif 527 #ifdef PM8001_USE_TASKLET 528 struct tasklet_struct tasklet[PM8001_MAX_MSIX_VEC]; 529 #endif 530 u32 logging_level; 531 u32 link_rate; 532 u32 fw_status; 533 u32 smp_exp_mode; 534 bool controller_fatal_error; 535 const struct firmware *fw_image; 536 struct isr_param irq_vector[PM8001_MAX_MSIX_VEC]; 537 u32 reset_in_progress; 538 u32 non_fatal_count; 539 u32 non_fatal_read_length; 540 u32 max_q_num; 541 u32 ib_offset; 542 u32 ob_offset; 543 u32 ci_offset; 544 u32 pi_offset; 545 u32 max_memcnt; 546 }; 547 548 struct pm8001_work { 549 struct work_struct work; 550 struct pm8001_hba_info *pm8001_ha; 551 void *data; 552 int handler; 553 }; 554 555 struct pm8001_fw_image_header { 556 u8 vender_id[8]; 557 u8 product_id; 558 u8 hardware_rev; 559 u8 dest_partition; 560 u8 reserved; 561 u8 fw_rev[4]; 562 __be32 image_length; 563 __be32 image_crc; 564 __be32 startup_entry; 565 } __attribute__((packed, aligned(4))); 566 567 568 /** 569 * FW Flash Update status values 570 */ 571 #define FLASH_UPDATE_COMPLETE_PENDING_REBOOT 0x00 572 #define FLASH_UPDATE_IN_PROGRESS 0x01 573 #define FLASH_UPDATE_HDR_ERR 0x02 574 #define FLASH_UPDATE_OFFSET_ERR 0x03 575 #define FLASH_UPDATE_CRC_ERR 0x04 576 #define FLASH_UPDATE_LENGTH_ERR 0x05 577 #define FLASH_UPDATE_HW_ERR 0x06 578 #define FLASH_UPDATE_DNLD_NOT_SUPPORTED 0x10 579 #define FLASH_UPDATE_DISABLED 0x11 580 581 #define NCQ_READ_LOG_FLAG 0x80000000 582 #define NCQ_ABORT_ALL_FLAG 0x40000000 583 #define NCQ_2ND_RLE_FLAG 0x20000000 584 585 /* Device states */ 586 #define DS_OPERATIONAL 0x01 587 #define DS_PORT_IN_RESET 0x02 588 #define DS_IN_RECOVERY 0x03 589 #define DS_IN_ERROR 0x04 590 #define DS_NON_OPERATIONAL 0x07 591 592 /** 593 * brief param structure for firmware flash update. 594 */ 595 struct fw_flash_updata_info { 596 u32 cur_image_offset; 597 u32 cur_image_len; 598 u32 total_image_len; 599 struct pm8001_prd sgl; 600 }; 601 602 struct fw_control_info { 603 u32 retcode;/*ret code (status)*/ 604 u32 phase;/*ret code phase*/ 605 u32 phaseCmplt;/*percent complete for the current 606 update phase */ 607 u32 version;/*Hex encoded firmware version number*/ 608 u32 offset;/*Used for downloading firmware */ 609 u32 len; /*len of buffer*/ 610 u32 size;/* Used in OS VPD and Trace get size 611 operations.*/ 612 u32 reserved;/* padding required for 64 bit 613 alignment */ 614 u8 buffer[1];/* Start of buffer */ 615 }; 616 struct fw_control_ex { 617 struct fw_control_info *fw_control; 618 void *buffer;/* keep buffer pointer to be 619 freed when the response comes*/ 620 void *virtAddr;/* keep virtual address of the data */ 621 void *usrAddr;/* keep virtual address of the 622 user data */ 623 dma_addr_t phys_addr; 624 u32 len; /* len of buffer */ 625 void *payload; /* pointer to IOCTL Payload */ 626 u8 inProgress;/*if 1 - the IOCTL request is in 627 progress */ 628 void *param1; 629 void *param2; 630 void *param3; 631 }; 632 633 /* pm8001 workqueue */ 634 extern struct workqueue_struct *pm8001_wq; 635 636 /******************** function prototype *********************/ 637 int pm8001_tag_alloc(struct pm8001_hba_info *pm8001_ha, u32 *tag_out); 638 void pm8001_tag_init(struct pm8001_hba_info *pm8001_ha); 639 u32 pm8001_get_ncq_tag(struct sas_task *task, u32 *tag); 640 void pm8001_ccb_task_free(struct pm8001_hba_info *pm8001_ha, 641 struct sas_task *task, struct pm8001_ccb_info *ccb, u32 ccb_idx); 642 int pm8001_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func, 643 void *funcdata); 644 void pm8001_scan_start(struct Scsi_Host *shost); 645 int pm8001_scan_finished(struct Scsi_Host *shost, unsigned long time); 646 int pm8001_queue_command(struct sas_task *task, gfp_t gfp_flags); 647 int pm8001_abort_task(struct sas_task *task); 648 int pm8001_abort_task_set(struct domain_device *dev, u8 *lun); 649 int pm8001_clear_aca(struct domain_device *dev, u8 *lun); 650 int pm8001_clear_task_set(struct domain_device *dev, u8 *lun); 651 int pm8001_dev_found(struct domain_device *dev); 652 void pm8001_dev_gone(struct domain_device *dev); 653 int pm8001_lu_reset(struct domain_device *dev, u8 *lun); 654 int pm8001_I_T_nexus_reset(struct domain_device *dev); 655 int pm8001_I_T_nexus_event_handler(struct domain_device *dev); 656 int pm8001_query_task(struct sas_task *task); 657 void pm8001_port_formed(struct asd_sas_phy *sas_phy); 658 void pm8001_open_reject_retry( 659 struct pm8001_hba_info *pm8001_ha, 660 struct sas_task *task_to_close, 661 struct pm8001_device *device_to_close); 662 int pm8001_mem_alloc(struct pci_dev *pdev, void **virt_addr, 663 dma_addr_t *pphys_addr, u32 *pphys_addr_hi, u32 *pphys_addr_lo, 664 u32 mem_size, u32 align); 665 666 void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha); 667 int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha, 668 struct inbound_queue_table *circularQ, 669 u32 opCode, void *payload, size_t nb, 670 u32 responseQueue); 671 int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ, 672 u16 messageSize, void **messagePtr); 673 u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg, 674 struct outbound_queue_table *circularQ, u8 bc); 675 u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha, 676 struct outbound_queue_table *circularQ, 677 void **messagePtr1, u8 *pBC); 678 int pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha, 679 struct pm8001_device *pm8001_dev, u32 state); 680 int pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha, 681 void *payload); 682 int pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha, 683 void *fw_flash_updata_info, u32 tag); 684 int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha, void *payload); 685 int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha, void *payload); 686 int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha, 687 struct pm8001_ccb_info *ccb, 688 struct pm8001_tmf_task *tmf); 689 int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha, 690 struct pm8001_device *pm8001_dev, 691 u8 flag, u32 task_tag, u32 cmd_tag); 692 int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha, u32 device_id); 693 void pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd); 694 void pm8001_work_fn(struct work_struct *work); 695 int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, 696 void *data, int handler); 697 void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha, 698 void *piomb); 699 void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, 700 void *piomb); 701 void pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, 702 void *piomb); 703 int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, 704 void *piomb); 705 void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate); 706 void pm8001_get_attached_sas_addr(struct pm8001_phy *phy, u8 *sas_addr); 707 void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i); 708 int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb); 709 int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb); 710 int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha, 711 void *piomb); 712 int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha, void *piomb); 713 int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb); 714 struct sas_task *pm8001_alloc_task(void); 715 void pm8001_task_done(struct sas_task *task); 716 void pm8001_free_task(struct sas_task *task); 717 void pm8001_tag_free(struct pm8001_hba_info *pm8001_ha, u32 tag); 718 struct pm8001_device *pm8001_find_dev(struct pm8001_hba_info *pm8001_ha, 719 u32 device_id); 720 int pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha); 721 722 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue); 723 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha, 724 u32 length, u8 *buf); 725 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha, 726 u32 phy, u32 length, u32 *buf); 727 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue); 728 ssize_t pm80xx_get_fatal_dump(struct device *cdev, 729 struct device_attribute *attr, char *buf); 730 ssize_t pm80xx_get_non_fatal_dump(struct device *cdev, 731 struct device_attribute *attr, char *buf); 732 ssize_t pm8001_get_gsm_dump(struct device *cdev, u32, char *buf); 733 int pm80xx_fatal_errors(struct pm8001_hba_info *pm8001_ha); 734 void pm8001_free_dev(struct pm8001_device *pm8001_dev); 735 /* ctl shared API */ 736 extern const struct attribute_group *pm8001_host_groups[]; 737 738 static inline void 739 pm8001_ccb_task_free_done(struct pm8001_hba_info *pm8001_ha, 740 struct sas_task *task, struct pm8001_ccb_info *ccb, 741 u32 ccb_idx) 742 { 743 pm8001_ccb_task_free(pm8001_ha, task, ccb, ccb_idx); 744 smp_mb(); /*in order to force CPU ordering*/ 745 task->task_done(task); 746 } 747 748 #endif 749 750