1 /* 2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 USI Co., Ltd. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 41 #ifndef _PM8001_SAS_H_ 42 #define _PM8001_SAS_H_ 43 44 #include <linux/kernel.h> 45 #include <linux/module.h> 46 #include <linux/spinlock.h> 47 #include <linux/delay.h> 48 #include <linux/types.h> 49 #include <linux/ctype.h> 50 #include <linux/dma-mapping.h> 51 #include <linux/pci.h> 52 #include <linux/interrupt.h> 53 #include <linux/workqueue.h> 54 #include <scsi/libsas.h> 55 #include <scsi/scsi_tcq.h> 56 #include <scsi/sas_ata.h> 57 #include <linux/atomic.h> 58 #include "pm8001_defs.h" 59 60 #define DRV_NAME "pm80xx" 61 #define DRV_VERSION "0.1.39" 62 #define PM8001_FAIL_LOGGING 0x01 /* Error message logging */ 63 #define PM8001_INIT_LOGGING 0x02 /* driver init logging */ 64 #define PM8001_DISC_LOGGING 0x04 /* discovery layer logging */ 65 #define PM8001_IO_LOGGING 0x08 /* I/O path logging */ 66 #define PM8001_EH_LOGGING 0x10 /* libsas EH function logging*/ 67 #define PM8001_IOCTL_LOGGING 0x20 /* IOCTL message logging */ 68 #define PM8001_MSG_LOGGING 0x40 /* misc message logging */ 69 #define pm8001_printk(format, arg...) printk(KERN_INFO "pm80xx %s %d:" \ 70 format, __func__, __LINE__, ## arg) 71 #define PM8001_CHECK_LOGGING(HBA, LEVEL, CMD) \ 72 do { \ 73 if (unlikely(HBA->logging_level & LEVEL)) \ 74 do { \ 75 CMD; \ 76 } while (0); \ 77 } while (0); 78 79 #define PM8001_EH_DBG(HBA, CMD) \ 80 PM8001_CHECK_LOGGING(HBA, PM8001_EH_LOGGING, CMD) 81 82 #define PM8001_INIT_DBG(HBA, CMD) \ 83 PM8001_CHECK_LOGGING(HBA, PM8001_INIT_LOGGING, CMD) 84 85 #define PM8001_DISC_DBG(HBA, CMD) \ 86 PM8001_CHECK_LOGGING(HBA, PM8001_DISC_LOGGING, CMD) 87 88 #define PM8001_IO_DBG(HBA, CMD) \ 89 PM8001_CHECK_LOGGING(HBA, PM8001_IO_LOGGING, CMD) 90 91 #define PM8001_FAIL_DBG(HBA, CMD) \ 92 PM8001_CHECK_LOGGING(HBA, PM8001_FAIL_LOGGING, CMD) 93 94 #define PM8001_IOCTL_DBG(HBA, CMD) \ 95 PM8001_CHECK_LOGGING(HBA, PM8001_IOCTL_LOGGING, CMD) 96 97 #define PM8001_MSG_DBG(HBA, CMD) \ 98 PM8001_CHECK_LOGGING(HBA, PM8001_MSG_LOGGING, CMD) 99 100 101 #define PM8001_USE_TASKLET 102 #define PM8001_USE_MSIX 103 #define PM8001_READ_VPD 104 105 106 #define IS_SPCV_12G(dev) ((dev->device == 0X8074) \ 107 || (dev->device == 0X8076) \ 108 || (dev->device == 0X8077) \ 109 || (dev->device == 0X8070) \ 110 || (dev->device == 0X8072)) 111 112 #define PM8001_NAME_LENGTH 32/* generic length of strings */ 113 extern struct list_head hba_list; 114 extern const struct pm8001_dispatch pm8001_8001_dispatch; 115 extern const struct pm8001_dispatch pm8001_80xx_dispatch; 116 117 struct pm8001_hba_info; 118 struct pm8001_ccb_info; 119 struct pm8001_device; 120 /* define task management IU */ 121 struct pm8001_tmf_task { 122 u8 tmf; 123 u32 tag_of_task_to_be_managed; 124 }; 125 struct pm8001_ioctl_payload { 126 u32 signature; 127 u16 major_function; 128 u16 minor_function; 129 u16 length; 130 u16 status; 131 u16 offset; 132 u16 id; 133 u8 *func_specific; 134 }; 135 136 #define MPI_FATAL_ERROR_TABLE_OFFSET_MASK 0xFFFFFF 137 #define MPI_FATAL_ERROR_TABLE_SIZE(value) ((0xFF000000 & value) >> SHIFT24) 138 #define MPI_FATAL_EDUMP_TABLE_LO_OFFSET 0x00 /* HNFBUFL */ 139 #define MPI_FATAL_EDUMP_TABLE_HI_OFFSET 0x04 /* HNFBUFH */ 140 #define MPI_FATAL_EDUMP_TABLE_LENGTH 0x08 /* HNFBLEN */ 141 #define MPI_FATAL_EDUMP_TABLE_HANDSHAKE 0x0C /* FDDHSHK */ 142 #define MPI_FATAL_EDUMP_TABLE_STATUS 0x10 /* FDDTSTAT */ 143 #define MPI_FATAL_EDUMP_TABLE_ACCUM_LEN 0x14 /* ACCDDLEN */ 144 #define MPI_FATAL_EDUMP_HANDSHAKE_RDY 0x1 145 #define MPI_FATAL_EDUMP_HANDSHAKE_BUSY 0x0 146 #define MPI_FATAL_EDUMP_TABLE_STAT_RSVD 0x0 147 #define MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED 0x1 148 #define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA 0x2 149 #define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE 0x3 150 #define TYPE_GSM_SPACE 1 151 #define TYPE_QUEUE 2 152 #define TYPE_FATAL 3 153 #define TYPE_NON_FATAL 4 154 #define TYPE_INBOUND 1 155 #define TYPE_OUTBOUND 2 156 struct forensic_data { 157 u32 data_type; 158 union { 159 struct { 160 u32 direct_len; 161 u32 direct_offset; 162 void *direct_data; 163 } gsm_buf; 164 struct { 165 u16 queue_type; 166 u16 queue_index; 167 u32 direct_len; 168 void *direct_data; 169 } queue_buf; 170 struct { 171 u32 direct_len; 172 u32 direct_offset; 173 u32 read_len; 174 void *direct_data; 175 } data_buf; 176 }; 177 }; 178 179 /* bit31-26 - mask bar */ 180 #define SCRATCH_PAD0_BAR_MASK 0xFC000000 181 /* bit25-0 - offset mask */ 182 #define SCRATCH_PAD0_OFFSET_MASK 0x03FFFFFF 183 /* if AAP error state */ 184 #define SCRATCH_PAD0_AAPERR_MASK 0xFFFFFFFF 185 /* Inbound doorbell bit7 */ 186 #define SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP 0x80 187 /* Inbound doorbell bit7 SPCV */ 188 #define SPCV_MSGU_CFG_TABLE_TRANSFER_DEBUG_INFO 0x80 189 #define MAIN_MERRDCTO_MERRDCES 0xA0/* DWORD 0x28) */ 190 191 struct pm8001_dispatch { 192 char *name; 193 int (*chip_init)(struct pm8001_hba_info *pm8001_ha); 194 int (*chip_soft_rst)(struct pm8001_hba_info *pm8001_ha); 195 void (*chip_rst)(struct pm8001_hba_info *pm8001_ha); 196 int (*chip_ioremap)(struct pm8001_hba_info *pm8001_ha); 197 void (*chip_iounmap)(struct pm8001_hba_info *pm8001_ha); 198 irqreturn_t (*isr)(struct pm8001_hba_info *pm8001_ha, u8 vec); 199 u32 (*is_our_interrupt)(struct pm8001_hba_info *pm8001_ha); 200 int (*isr_process_oq)(struct pm8001_hba_info *pm8001_ha, u8 vec); 201 void (*interrupt_enable)(struct pm8001_hba_info *pm8001_ha, u8 vec); 202 void (*interrupt_disable)(struct pm8001_hba_info *pm8001_ha, u8 vec); 203 void (*make_prd)(struct scatterlist *scatter, int nr, void *prd); 204 int (*smp_req)(struct pm8001_hba_info *pm8001_ha, 205 struct pm8001_ccb_info *ccb); 206 int (*ssp_io_req)(struct pm8001_hba_info *pm8001_ha, 207 struct pm8001_ccb_info *ccb); 208 int (*sata_req)(struct pm8001_hba_info *pm8001_ha, 209 struct pm8001_ccb_info *ccb); 210 int (*phy_start_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id); 211 int (*phy_stop_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id); 212 int (*reg_dev_req)(struct pm8001_hba_info *pm8001_ha, 213 struct pm8001_device *pm8001_dev, u32 flag); 214 int (*dereg_dev_req)(struct pm8001_hba_info *pm8001_ha, u32 device_id); 215 int (*phy_ctl_req)(struct pm8001_hba_info *pm8001_ha, 216 u32 phy_id, u32 phy_op); 217 int (*task_abort)(struct pm8001_hba_info *pm8001_ha, 218 struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, 219 u32 cmd_tag); 220 int (*ssp_tm_req)(struct pm8001_hba_info *pm8001_ha, 221 struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf); 222 int (*get_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload); 223 int (*set_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload); 224 int (*fw_flash_update_req)(struct pm8001_hba_info *pm8001_ha, 225 void *payload); 226 int (*set_dev_state_req)(struct pm8001_hba_info *pm8001_ha, 227 struct pm8001_device *pm8001_dev, u32 state); 228 int (*sas_diag_start_end_req)(struct pm8001_hba_info *pm8001_ha, 229 u32 state); 230 int (*sas_diag_execute_req)(struct pm8001_hba_info *pm8001_ha, 231 u32 state); 232 int (*sas_re_init_req)(struct pm8001_hba_info *pm8001_ha); 233 }; 234 235 struct pm8001_chip_info { 236 u32 encrypt; 237 u32 n_phy; 238 const struct pm8001_dispatch *dispatch; 239 }; 240 #define PM8001_CHIP_DISP (pm8001_ha->chip->dispatch) 241 242 struct pm8001_port { 243 struct asd_sas_port sas_port; 244 u8 port_attached; 245 u16 wide_port_phymap; 246 u8 port_state; 247 struct list_head list; 248 }; 249 250 struct pm8001_phy { 251 struct pm8001_hba_info *pm8001_ha; 252 struct pm8001_port *port; 253 struct asd_sas_phy sas_phy; 254 struct sas_identify identify; 255 struct scsi_device *sdev; 256 u64 dev_sas_addr; 257 u32 phy_type; 258 struct completion *enable_completion; 259 u32 frame_rcvd_size; 260 u8 frame_rcvd[32]; 261 u8 phy_attached; 262 u8 phy_state; 263 enum sas_linkrate minimum_linkrate; 264 enum sas_linkrate maximum_linkrate; 265 struct completion *reset_completion; 266 bool port_reset_status; 267 bool reset_success; 268 }; 269 270 /* port reset status */ 271 #define PORT_RESET_SUCCESS 0x00 272 #define PORT_RESET_TMO 0x01 273 274 struct pm8001_device { 275 enum sas_device_type dev_type; 276 struct domain_device *sas_device; 277 u32 attached_phy; 278 u32 id; 279 struct completion *dcompletion; 280 struct completion *setds_completion; 281 u32 device_id; 282 u32 running_req; 283 }; 284 285 struct pm8001_prd_imt { 286 __le32 len; 287 __le32 e; 288 }; 289 290 struct pm8001_prd { 291 __le64 addr; /* 64-bit buffer address */ 292 struct pm8001_prd_imt im_len; /* 64-bit length */ 293 } __attribute__ ((packed)); 294 /* 295 * CCB(Command Control Block) 296 */ 297 struct pm8001_ccb_info { 298 struct list_head entry; 299 struct sas_task *task; 300 u32 n_elem; 301 u32 ccb_tag; 302 dma_addr_t ccb_dma_handle; 303 struct pm8001_device *device; 304 struct pm8001_prd buf_prd[PM8001_MAX_DMA_SG]; 305 struct fw_control_ex *fw_control_context; 306 u8 open_retry; 307 }; 308 309 struct mpi_mem { 310 void *virt_ptr; 311 dma_addr_t phys_addr; 312 u32 phys_addr_hi; 313 u32 phys_addr_lo; 314 u32 total_len; 315 u32 num_elements; 316 u32 element_size; 317 u32 alignment; 318 }; 319 320 struct mpi_mem_req { 321 /* The number of element in the mpiMemory array */ 322 u32 count; 323 /* The array of structures that define memroy regions*/ 324 struct mpi_mem region[USI_MAX_MEMCNT]; 325 }; 326 327 struct encrypt { 328 u32 cipher_mode; 329 u32 sec_mode; 330 u32 status; 331 u32 flag; 332 }; 333 334 struct sas_phy_attribute_table { 335 u32 phystart1_16[16]; 336 u32 outbound_hw_event_pid1_16[16]; 337 }; 338 339 union main_cfg_table { 340 struct { 341 u32 signature; 342 u32 interface_rev; 343 u32 firmware_rev; 344 u32 max_out_io; 345 u32 max_sgl; 346 u32 ctrl_cap_flag; 347 u32 gst_offset; 348 u32 inbound_queue_offset; 349 u32 outbound_queue_offset; 350 u32 inbound_q_nppd_hppd; 351 u32 outbound_hw_event_pid0_3; 352 u32 outbound_hw_event_pid4_7; 353 u32 outbound_ncq_event_pid0_3; 354 u32 outbound_ncq_event_pid4_7; 355 u32 outbound_tgt_ITNexus_event_pid0_3; 356 u32 outbound_tgt_ITNexus_event_pid4_7; 357 u32 outbound_tgt_ssp_event_pid0_3; 358 u32 outbound_tgt_ssp_event_pid4_7; 359 u32 outbound_tgt_smp_event_pid0_3; 360 u32 outbound_tgt_smp_event_pid4_7; 361 u32 upper_event_log_addr; 362 u32 lower_event_log_addr; 363 u32 event_log_size; 364 u32 event_log_option; 365 u32 upper_iop_event_log_addr; 366 u32 lower_iop_event_log_addr; 367 u32 iop_event_log_size; 368 u32 iop_event_log_option; 369 u32 fatal_err_interrupt; 370 u32 fatal_err_dump_offset0; 371 u32 fatal_err_dump_length0; 372 u32 fatal_err_dump_offset1; 373 u32 fatal_err_dump_length1; 374 u32 hda_mode_flag; 375 u32 anolog_setup_table_offset; 376 u32 rsvd[4]; 377 } pm8001_tbl; 378 379 struct { 380 u32 signature; 381 u32 interface_rev; 382 u32 firmware_rev; 383 u32 max_out_io; 384 u32 max_sgl; 385 u32 ctrl_cap_flag; 386 u32 gst_offset; 387 u32 inbound_queue_offset; 388 u32 outbound_queue_offset; 389 u32 inbound_q_nppd_hppd; 390 u32 rsvd[8]; 391 u32 crc_core_dump; 392 u32 rsvd1; 393 u32 upper_event_log_addr; 394 u32 lower_event_log_addr; 395 u32 event_log_size; 396 u32 event_log_severity; 397 u32 upper_pcs_event_log_addr; 398 u32 lower_pcs_event_log_addr; 399 u32 pcs_event_log_size; 400 u32 pcs_event_log_severity; 401 u32 fatal_err_interrupt; 402 u32 fatal_err_dump_offset0; 403 u32 fatal_err_dump_length0; 404 u32 fatal_err_dump_offset1; 405 u32 fatal_err_dump_length1; 406 u32 gpio_led_mapping; 407 u32 analog_setup_table_offset; 408 u32 int_vec_table_offset; 409 u32 phy_attr_table_offset; 410 u32 port_recovery_timer; 411 u32 interrupt_reassertion_delay; 412 u32 fatal_n_non_fatal_dump; /* 0x28 */ 413 u32 ila_version; 414 u32 inc_fw_version; 415 } pm80xx_tbl; 416 }; 417 418 union general_status_table { 419 struct { 420 u32 gst_len_mpistate; 421 u32 iq_freeze_state0; 422 u32 iq_freeze_state1; 423 u32 msgu_tcnt; 424 u32 iop_tcnt; 425 u32 rsvd; 426 u32 phy_state[8]; 427 u32 gpio_input_val; 428 u32 rsvd1[2]; 429 u32 recover_err_info[8]; 430 } pm8001_tbl; 431 struct { 432 u32 gst_len_mpistate; 433 u32 iq_freeze_state0; 434 u32 iq_freeze_state1; 435 u32 msgu_tcnt; 436 u32 iop_tcnt; 437 u32 rsvd[9]; 438 u32 gpio_input_val; 439 u32 rsvd1[2]; 440 u32 recover_err_info[8]; 441 } pm80xx_tbl; 442 }; 443 struct inbound_queue_table { 444 u32 element_pri_size_cnt; 445 u32 upper_base_addr; 446 u32 lower_base_addr; 447 u32 ci_upper_base_addr; 448 u32 ci_lower_base_addr; 449 u32 pi_pci_bar; 450 u32 pi_offset; 451 u32 total_length; 452 void *base_virt; 453 void *ci_virt; 454 u32 reserved; 455 __le32 consumer_index; 456 u32 producer_idx; 457 }; 458 struct outbound_queue_table { 459 u32 element_size_cnt; 460 u32 upper_base_addr; 461 u32 lower_base_addr; 462 void *base_virt; 463 u32 pi_upper_base_addr; 464 u32 pi_lower_base_addr; 465 u32 ci_pci_bar; 466 u32 ci_offset; 467 u32 total_length; 468 void *pi_virt; 469 u32 interrup_vec_cnt_delay; 470 u32 dinterrup_to_pci_offset; 471 __le32 producer_index; 472 u32 consumer_idx; 473 }; 474 struct pm8001_hba_memspace { 475 void __iomem *memvirtaddr; 476 u64 membase; 477 u32 memsize; 478 }; 479 struct isr_param { 480 struct pm8001_hba_info *drv_inst; 481 u32 irq_id; 482 }; 483 struct pm8001_hba_info { 484 char name[PM8001_NAME_LENGTH]; 485 struct list_head list; 486 unsigned long flags; 487 spinlock_t lock;/* host-wide lock */ 488 spinlock_t bitmap_lock; 489 struct pci_dev *pdev;/* our device */ 490 struct device *dev; 491 struct pm8001_hba_memspace io_mem[6]; 492 struct mpi_mem_req memoryMap; 493 struct encrypt encrypt_info; /* support encryption */ 494 struct forensic_data forensic_info; 495 u32 fatal_bar_loc; 496 u32 forensic_last_offset; 497 u32 fatal_forensic_shift_offset; 498 u32 forensic_fatal_step; 499 u32 evtlog_ib_offset; 500 u32 evtlog_ob_offset; 501 void __iomem *msg_unit_tbl_addr;/*Message Unit Table Addr*/ 502 void __iomem *main_cfg_tbl_addr;/*Main Config Table Addr*/ 503 void __iomem *general_stat_tbl_addr;/*General Status Table Addr*/ 504 void __iomem *inbnd_q_tbl_addr;/*Inbound Queue Config Table Addr*/ 505 void __iomem *outbnd_q_tbl_addr;/*Outbound Queue Config Table Addr*/ 506 void __iomem *pspa_q_tbl_addr; 507 /*MPI SAS PHY attributes Queue Config Table Addr*/ 508 void __iomem *ivt_tbl_addr; /*MPI IVT Table Addr */ 509 void __iomem *fatal_tbl_addr; /*MPI IVT Table Addr */ 510 union main_cfg_table main_cfg_tbl; 511 union general_status_table gs_tbl; 512 struct inbound_queue_table inbnd_q_tbl[PM8001_MAX_SPCV_INB_NUM]; 513 struct outbound_queue_table outbnd_q_tbl[PM8001_MAX_SPCV_OUTB_NUM]; 514 struct sas_phy_attribute_table phy_attr_table; 515 /* MPI SAS PHY attributes */ 516 u8 sas_addr[SAS_ADDR_SIZE]; 517 struct sas_ha_struct *sas;/* SCSI/SAS glue */ 518 struct Scsi_Host *shost; 519 u32 chip_id; 520 const struct pm8001_chip_info *chip; 521 struct completion *nvmd_completion; 522 int tags_num; 523 unsigned long *tags; 524 struct pm8001_phy phy[PM8001_MAX_PHYS]; 525 struct pm8001_port port[PM8001_MAX_PHYS]; 526 u32 id; 527 u32 irq; 528 u32 iomb_size; /* SPC and SPCV IOMB size */ 529 struct pm8001_device *devices; 530 struct pm8001_ccb_info *ccb_info; 531 #ifdef PM8001_USE_MSIX 532 int number_of_intr;/*will be used in remove()*/ 533 #endif 534 #ifdef PM8001_USE_TASKLET 535 struct tasklet_struct tasklet[PM8001_MAX_MSIX_VEC]; 536 #endif 537 u32 logging_level; 538 u32 fw_status; 539 u32 smp_exp_mode; 540 bool controller_fatal_error; 541 const struct firmware *fw_image; 542 struct isr_param irq_vector[PM8001_MAX_MSIX_VEC]; 543 u32 reset_in_progress; 544 }; 545 546 struct pm8001_work { 547 struct work_struct work; 548 struct pm8001_hba_info *pm8001_ha; 549 void *data; 550 int handler; 551 }; 552 553 struct pm8001_fw_image_header { 554 u8 vender_id[8]; 555 u8 product_id; 556 u8 hardware_rev; 557 u8 dest_partition; 558 u8 reserved; 559 u8 fw_rev[4]; 560 __be32 image_length; 561 __be32 image_crc; 562 __be32 startup_entry; 563 } __attribute__((packed, aligned(4))); 564 565 566 /** 567 * FW Flash Update status values 568 */ 569 #define FLASH_UPDATE_COMPLETE_PENDING_REBOOT 0x00 570 #define FLASH_UPDATE_IN_PROGRESS 0x01 571 #define FLASH_UPDATE_HDR_ERR 0x02 572 #define FLASH_UPDATE_OFFSET_ERR 0x03 573 #define FLASH_UPDATE_CRC_ERR 0x04 574 #define FLASH_UPDATE_LENGTH_ERR 0x05 575 #define FLASH_UPDATE_HW_ERR 0x06 576 #define FLASH_UPDATE_DNLD_NOT_SUPPORTED 0x10 577 #define FLASH_UPDATE_DISABLED 0x11 578 579 #define NCQ_READ_LOG_FLAG 0x80000000 580 #define NCQ_ABORT_ALL_FLAG 0x40000000 581 #define NCQ_2ND_RLE_FLAG 0x20000000 582 583 /* Device states */ 584 #define DS_OPERATIONAL 0x01 585 #define DS_PORT_IN_RESET 0x02 586 #define DS_IN_RECOVERY 0x03 587 #define DS_IN_ERROR 0x04 588 #define DS_NON_OPERATIONAL 0x07 589 590 /** 591 * brief param structure for firmware flash update. 592 */ 593 struct fw_flash_updata_info { 594 u32 cur_image_offset; 595 u32 cur_image_len; 596 u32 total_image_len; 597 struct pm8001_prd sgl; 598 }; 599 600 struct fw_control_info { 601 u32 retcode;/*ret code (status)*/ 602 u32 phase;/*ret code phase*/ 603 u32 phaseCmplt;/*percent complete for the current 604 update phase */ 605 u32 version;/*Hex encoded firmware version number*/ 606 u32 offset;/*Used for downloading firmware */ 607 u32 len; /*len of buffer*/ 608 u32 size;/* Used in OS VPD and Trace get size 609 operations.*/ 610 u32 reserved;/* padding required for 64 bit 611 alignment */ 612 u8 buffer[1];/* Start of buffer */ 613 }; 614 struct fw_control_ex { 615 struct fw_control_info *fw_control; 616 void *buffer;/* keep buffer pointer to be 617 freed when the response comes*/ 618 void *virtAddr;/* keep virtual address of the data */ 619 void *usrAddr;/* keep virtual address of the 620 user data */ 621 dma_addr_t phys_addr; 622 u32 len; /* len of buffer */ 623 void *payload; /* pointer to IOCTL Payload */ 624 u8 inProgress;/*if 1 - the IOCTL request is in 625 progress */ 626 void *param1; 627 void *param2; 628 void *param3; 629 }; 630 631 /* pm8001 workqueue */ 632 extern struct workqueue_struct *pm8001_wq; 633 634 /******************** function prototype *********************/ 635 int pm8001_tag_alloc(struct pm8001_hba_info *pm8001_ha, u32 *tag_out); 636 void pm8001_tag_init(struct pm8001_hba_info *pm8001_ha); 637 u32 pm8001_get_ncq_tag(struct sas_task *task, u32 *tag); 638 void pm8001_ccb_task_free(struct pm8001_hba_info *pm8001_ha, 639 struct sas_task *task, struct pm8001_ccb_info *ccb, u32 ccb_idx); 640 int pm8001_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func, 641 void *funcdata); 642 void pm8001_scan_start(struct Scsi_Host *shost); 643 int pm8001_scan_finished(struct Scsi_Host *shost, unsigned long time); 644 int pm8001_queue_command(struct sas_task *task, gfp_t gfp_flags); 645 int pm8001_abort_task(struct sas_task *task); 646 int pm8001_abort_task_set(struct domain_device *dev, u8 *lun); 647 int pm8001_clear_aca(struct domain_device *dev, u8 *lun); 648 int pm8001_clear_task_set(struct domain_device *dev, u8 *lun); 649 int pm8001_dev_found(struct domain_device *dev); 650 void pm8001_dev_gone(struct domain_device *dev); 651 int pm8001_lu_reset(struct domain_device *dev, u8 *lun); 652 int pm8001_I_T_nexus_reset(struct domain_device *dev); 653 int pm8001_I_T_nexus_event_handler(struct domain_device *dev); 654 int pm8001_query_task(struct sas_task *task); 655 void pm8001_open_reject_retry( 656 struct pm8001_hba_info *pm8001_ha, 657 struct sas_task *task_to_close, 658 struct pm8001_device *device_to_close); 659 int pm8001_mem_alloc(struct pci_dev *pdev, void **virt_addr, 660 dma_addr_t *pphys_addr, u32 *pphys_addr_hi, u32 *pphys_addr_lo, 661 u32 mem_size, u32 align); 662 663 void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha); 664 int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha, 665 struct inbound_queue_table *circularQ, 666 u32 opCode, void *payload, u32 responseQueue); 667 int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ, 668 u16 messageSize, void **messagePtr); 669 u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg, 670 struct outbound_queue_table *circularQ, u8 bc); 671 u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha, 672 struct outbound_queue_table *circularQ, 673 void **messagePtr1, u8 *pBC); 674 int pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha, 675 struct pm8001_device *pm8001_dev, u32 state); 676 int pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha, 677 void *payload); 678 int pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha, 679 void *fw_flash_updata_info, u32 tag); 680 int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha, void *payload); 681 int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha, void *payload); 682 int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha, 683 struct pm8001_ccb_info *ccb, 684 struct pm8001_tmf_task *tmf); 685 int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha, 686 struct pm8001_device *pm8001_dev, 687 u8 flag, u32 task_tag, u32 cmd_tag); 688 int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha, u32 device_id); 689 void pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd); 690 void pm8001_work_fn(struct work_struct *work); 691 int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, 692 void *data, int handler); 693 void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha, 694 void *piomb); 695 void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, 696 void *piomb); 697 void pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, 698 void *piomb); 699 int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, 700 void *piomb); 701 void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate); 702 void pm8001_get_attached_sas_addr(struct pm8001_phy *phy, u8 *sas_addr); 703 void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i); 704 int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb); 705 int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb); 706 int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha, 707 void *piomb); 708 int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb); 709 int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb); 710 struct sas_task *pm8001_alloc_task(void); 711 void pm8001_task_done(struct sas_task *task); 712 void pm8001_free_task(struct sas_task *task); 713 void pm8001_tag_free(struct pm8001_hba_info *pm8001_ha, u32 tag); 714 struct pm8001_device *pm8001_find_dev(struct pm8001_hba_info *pm8001_ha, 715 u32 device_id); 716 int pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha); 717 718 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue); 719 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha, 720 u32 length, u8 *buf); 721 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha, 722 u32 phy, u32 length, u32 *buf); 723 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue); 724 ssize_t pm80xx_get_fatal_dump(struct device *cdev, 725 struct device_attribute *attr, char *buf); 726 ssize_t pm8001_get_gsm_dump(struct device *cdev, u32, char *buf); 727 /* ctl shared API */ 728 extern struct device_attribute *pm8001_host_attrs[]; 729 730 static inline void 731 pm8001_ccb_task_free_done(struct pm8001_hba_info *pm8001_ha, 732 struct sas_task *task, struct pm8001_ccb_info *ccb, 733 u32 ccb_idx) 734 { 735 pm8001_ccb_task_free(pm8001_ha, task, ccb, ccb_idx); 736 smp_mb(); /*in order to force CPU ordering*/ 737 spin_unlock(&pm8001_ha->lock); 738 task->task_done(task); 739 spin_lock(&pm8001_ha->lock); 740 } 741 742 #endif 743 744