1 /* 2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 USI Co., Ltd. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 41 #include <linux/slab.h> 42 #include "pm8001_sas.h" 43 #include "pm8001_chips.h" 44 #include "pm80xx_hwi.h" 45 46 static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING | 47 PM8001_EVENT_LOGGING | PM8001_INIT_LOGGING; 48 module_param(logging_level, ulong, 0644); 49 MODULE_PARM_DESC(logging_level, " bits for enabling logging info."); 50 51 static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120; 52 module_param(link_rate, ulong, 0644); 53 MODULE_PARM_DESC(link_rate, "Enable link rate.\n" 54 " 1: Link rate 1.5G\n" 55 " 2: Link rate 3.0G\n" 56 " 4: Link rate 6.0G\n" 57 " 8: Link rate 12.0G\n"); 58 59 static struct scsi_transport_template *pm8001_stt; 60 static int pm8001_init_ccb_tag(struct pm8001_hba_info *); 61 62 /* 63 * chip info structure to identify chip key functionality as 64 * encryption available/not, no of ports, hw specific function ref 65 */ 66 static const struct pm8001_chip_info pm8001_chips[] = { 67 [chip_8001] = {0, 8, &pm8001_8001_dispatch,}, 68 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,}, 69 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,}, 70 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,}, 71 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,}, 72 [chip_8074] = {0, 8, &pm8001_80xx_dispatch,}, 73 [chip_8076] = {0, 16, &pm8001_80xx_dispatch,}, 74 [chip_8077] = {0, 16, &pm8001_80xx_dispatch,}, 75 [chip_8006] = {0, 16, &pm8001_80xx_dispatch,}, 76 [chip_8070] = {0, 8, &pm8001_80xx_dispatch,}, 77 [chip_8072] = {0, 16, &pm8001_80xx_dispatch,}, 78 }; 79 static int pm8001_id; 80 81 LIST_HEAD(hba_list); 82 83 struct workqueue_struct *pm8001_wq; 84 85 static void pm8001_map_queues(struct Scsi_Host *shost) 86 { 87 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 88 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 89 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT]; 90 91 if (pm8001_ha->number_of_intr > 1) 92 blk_mq_pci_map_queues(qmap, pm8001_ha->pdev, 1); 93 94 return blk_mq_map_queues(qmap); 95 } 96 97 /* 98 * The main structure which LLDD must register for scsi core. 99 */ 100 static const struct scsi_host_template pm8001_sht = { 101 .module = THIS_MODULE, 102 .name = DRV_NAME, 103 .proc_name = DRV_NAME, 104 .queuecommand = sas_queuecommand, 105 .dma_need_drain = ata_scsi_dma_need_drain, 106 .target_alloc = sas_target_alloc, 107 .slave_configure = sas_slave_configure, 108 .scan_finished = pm8001_scan_finished, 109 .scan_start = pm8001_scan_start, 110 .change_queue_depth = sas_change_queue_depth, 111 .bios_param = sas_bios_param, 112 .can_queue = 1, 113 .this_id = -1, 114 .sg_tablesize = PM8001_MAX_DMA_SG, 115 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 116 .eh_device_reset_handler = sas_eh_device_reset_handler, 117 .eh_target_reset_handler = sas_eh_target_reset_handler, 118 .slave_alloc = sas_slave_alloc, 119 .target_destroy = sas_target_destroy, 120 .ioctl = sas_ioctl, 121 #ifdef CONFIG_COMPAT 122 .compat_ioctl = sas_ioctl, 123 #endif 124 .shost_groups = pm8001_host_groups, 125 .track_queue_depth = 1, 126 .cmd_per_lun = 32, 127 .map_queues = pm8001_map_queues, 128 }; 129 130 /* 131 * Sas layer call this function to execute specific task. 132 */ 133 static struct sas_domain_function_template pm8001_transport_ops = { 134 .lldd_dev_found = pm8001_dev_found, 135 .lldd_dev_gone = pm8001_dev_gone, 136 137 .lldd_execute_task = pm8001_queue_command, 138 .lldd_control_phy = pm8001_phy_control, 139 140 .lldd_abort_task = pm8001_abort_task, 141 .lldd_abort_task_set = sas_abort_task_set, 142 .lldd_clear_task_set = pm8001_clear_task_set, 143 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset, 144 .lldd_lu_reset = pm8001_lu_reset, 145 .lldd_query_task = pm8001_query_task, 146 .lldd_port_formed = pm8001_port_formed, 147 .lldd_tmf_exec_complete = pm8001_setds_completion, 148 .lldd_tmf_aborted = pm8001_tmf_aborted, 149 }; 150 151 /** 152 * pm8001_phy_init - initiate our adapter phys 153 * @pm8001_ha: our hba structure. 154 * @phy_id: phy id. 155 */ 156 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id) 157 { 158 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 159 struct asd_sas_phy *sas_phy = &phy->sas_phy; 160 phy->phy_state = PHY_LINK_DISABLE; 161 phy->pm8001_ha = pm8001_ha; 162 phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS; 163 phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS; 164 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0; 165 sas_phy->iproto = SAS_PROTOCOL_ALL; 166 sas_phy->tproto = 0; 167 sas_phy->role = PHY_ROLE_INITIATOR; 168 sas_phy->oob_mode = OOB_NOT_CONNECTED; 169 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN; 170 sas_phy->id = phy_id; 171 sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr; 172 sas_phy->frame_rcvd = &phy->frame_rcvd[0]; 173 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata; 174 sas_phy->lldd_phy = phy; 175 } 176 177 /** 178 * pm8001_free - free hba 179 * @pm8001_ha: our hba structure. 180 */ 181 static void pm8001_free(struct pm8001_hba_info *pm8001_ha) 182 { 183 int i; 184 185 if (!pm8001_ha) 186 return; 187 188 for (i = 0; i < USI_MAX_MEMCNT; i++) { 189 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) { 190 dma_free_coherent(&pm8001_ha->pdev->dev, 191 (pm8001_ha->memoryMap.region[i].total_len + 192 pm8001_ha->memoryMap.region[i].alignment), 193 pm8001_ha->memoryMap.region[i].virt_ptr, 194 pm8001_ha->memoryMap.region[i].phys_addr); 195 } 196 } 197 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha); 198 flush_workqueue(pm8001_wq); 199 bitmap_free(pm8001_ha->rsvd_tags); 200 kfree(pm8001_ha); 201 } 202 203 #ifdef PM8001_USE_TASKLET 204 205 /** 206 * pm8001_tasklet() - tasklet for 64 msi-x interrupt handler 207 * @opaque: the passed general host adapter struct 208 * Note: pm8001_tasklet is common for pm8001 & pm80xx 209 */ 210 static void pm8001_tasklet(unsigned long opaque) 211 { 212 struct pm8001_hba_info *pm8001_ha; 213 struct isr_param *irq_vector; 214 215 irq_vector = (struct isr_param *)opaque; 216 pm8001_ha = irq_vector->drv_inst; 217 if (unlikely(!pm8001_ha)) 218 BUG_ON(1); 219 PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id); 220 } 221 #endif 222 223 /** 224 * pm8001_interrupt_handler_msix - main MSIX interrupt handler. 225 * It obtains the vector number and calls the equivalent bottom 226 * half or services directly. 227 * @irq: interrupt number 228 * @opaque: the passed outbound queue/vector. Host structure is 229 * retrieved from the same. 230 */ 231 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque) 232 { 233 struct isr_param *irq_vector; 234 struct pm8001_hba_info *pm8001_ha; 235 irqreturn_t ret = IRQ_HANDLED; 236 irq_vector = (struct isr_param *)opaque; 237 pm8001_ha = irq_vector->drv_inst; 238 239 if (unlikely(!pm8001_ha)) 240 return IRQ_NONE; 241 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha)) 242 return IRQ_NONE; 243 #ifdef PM8001_USE_TASKLET 244 tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]); 245 #else 246 ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id); 247 #endif 248 return ret; 249 } 250 251 /** 252 * pm8001_interrupt_handler_intx - main INTx interrupt handler. 253 * @irq: interrupt number 254 * @dev_id: sas_ha structure. The HBA is retrieved from sas_ha structure. 255 */ 256 257 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id) 258 { 259 struct pm8001_hba_info *pm8001_ha; 260 irqreturn_t ret = IRQ_HANDLED; 261 struct sas_ha_struct *sha = dev_id; 262 pm8001_ha = sha->lldd_ha; 263 if (unlikely(!pm8001_ha)) 264 return IRQ_NONE; 265 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha)) 266 return IRQ_NONE; 267 268 #ifdef PM8001_USE_TASKLET 269 tasklet_schedule(&pm8001_ha->tasklet[0]); 270 #else 271 ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0); 272 #endif 273 return ret; 274 } 275 276 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha); 277 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha); 278 279 /** 280 * pm8001_alloc - initiate our hba structure and 6 DMAs area. 281 * @pm8001_ha: our hba structure. 282 * @ent: PCI device ID structure to match on 283 */ 284 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha, 285 const struct pci_device_id *ent) 286 { 287 int i, count = 0, rc = 0; 288 u32 ci_offset, ib_offset, ob_offset, pi_offset; 289 struct inbound_queue_table *ibq; 290 struct outbound_queue_table *obq; 291 292 spin_lock_init(&pm8001_ha->lock); 293 spin_lock_init(&pm8001_ha->bitmap_lock); 294 pm8001_dbg(pm8001_ha, INIT, "pm8001_alloc: PHY:%x\n", 295 pm8001_ha->chip->n_phy); 296 297 /* Setup Interrupt */ 298 rc = pm8001_setup_irq(pm8001_ha); 299 if (rc) { 300 pm8001_dbg(pm8001_ha, FAIL, 301 "pm8001_setup_irq failed [ret: %d]\n", rc); 302 goto err_out; 303 } 304 /* Request Interrupt */ 305 rc = pm8001_request_irq(pm8001_ha); 306 if (rc) 307 goto err_out; 308 309 count = pm8001_ha->max_q_num; 310 /* Queues are chosen based on the number of cores/msix availability */ 311 ib_offset = pm8001_ha->ib_offset = USI_MAX_MEMCNT_BASE; 312 ci_offset = pm8001_ha->ci_offset = ib_offset + count; 313 ob_offset = pm8001_ha->ob_offset = ci_offset + count; 314 pi_offset = pm8001_ha->pi_offset = ob_offset + count; 315 pm8001_ha->max_memcnt = pi_offset + count; 316 317 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 318 pm8001_phy_init(pm8001_ha, i); 319 pm8001_ha->port[i].wide_port_phymap = 0; 320 pm8001_ha->port[i].port_attached = 0; 321 pm8001_ha->port[i].port_state = 0; 322 INIT_LIST_HEAD(&pm8001_ha->port[i].list); 323 } 324 325 /* MPI Memory region 1 for AAP Event Log for fw */ 326 pm8001_ha->memoryMap.region[AAP1].num_elements = 1; 327 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE; 328 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE; 329 pm8001_ha->memoryMap.region[AAP1].alignment = 32; 330 331 /* MPI Memory region 2 for IOP Event Log for fw */ 332 pm8001_ha->memoryMap.region[IOP].num_elements = 1; 333 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE; 334 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE; 335 pm8001_ha->memoryMap.region[IOP].alignment = 32; 336 337 for (i = 0; i < count; i++) { 338 ibq = &pm8001_ha->inbnd_q_tbl[i]; 339 spin_lock_init(&ibq->iq_lock); 340 /* MPI Memory region 3 for consumer Index of inbound queues */ 341 pm8001_ha->memoryMap.region[ci_offset+i].num_elements = 1; 342 pm8001_ha->memoryMap.region[ci_offset+i].element_size = 4; 343 pm8001_ha->memoryMap.region[ci_offset+i].total_len = 4; 344 pm8001_ha->memoryMap.region[ci_offset+i].alignment = 4; 345 346 if ((ent->driver_data) != chip_8001) { 347 /* MPI Memory region 5 inbound queues */ 348 pm8001_ha->memoryMap.region[ib_offset+i].num_elements = 349 PM8001_MPI_QUEUE; 350 pm8001_ha->memoryMap.region[ib_offset+i].element_size 351 = 128; 352 pm8001_ha->memoryMap.region[ib_offset+i].total_len = 353 PM8001_MPI_QUEUE * 128; 354 pm8001_ha->memoryMap.region[ib_offset+i].alignment 355 = 128; 356 } else { 357 pm8001_ha->memoryMap.region[ib_offset+i].num_elements = 358 PM8001_MPI_QUEUE; 359 pm8001_ha->memoryMap.region[ib_offset+i].element_size 360 = 64; 361 pm8001_ha->memoryMap.region[ib_offset+i].total_len = 362 PM8001_MPI_QUEUE * 64; 363 pm8001_ha->memoryMap.region[ib_offset+i].alignment = 64; 364 } 365 } 366 367 for (i = 0; i < count; i++) { 368 obq = &pm8001_ha->outbnd_q_tbl[i]; 369 spin_lock_init(&obq->oq_lock); 370 /* MPI Memory region 4 for producer Index of outbound queues */ 371 pm8001_ha->memoryMap.region[pi_offset+i].num_elements = 1; 372 pm8001_ha->memoryMap.region[pi_offset+i].element_size = 4; 373 pm8001_ha->memoryMap.region[pi_offset+i].total_len = 4; 374 pm8001_ha->memoryMap.region[pi_offset+i].alignment = 4; 375 376 if (ent->driver_data != chip_8001) { 377 /* MPI Memory region 6 Outbound queues */ 378 pm8001_ha->memoryMap.region[ob_offset+i].num_elements = 379 PM8001_MPI_QUEUE; 380 pm8001_ha->memoryMap.region[ob_offset+i].element_size 381 = 128; 382 pm8001_ha->memoryMap.region[ob_offset+i].total_len = 383 PM8001_MPI_QUEUE * 128; 384 pm8001_ha->memoryMap.region[ob_offset+i].alignment 385 = 128; 386 } else { 387 /* MPI Memory region 6 Outbound queues */ 388 pm8001_ha->memoryMap.region[ob_offset+i].num_elements = 389 PM8001_MPI_QUEUE; 390 pm8001_ha->memoryMap.region[ob_offset+i].element_size 391 = 64; 392 pm8001_ha->memoryMap.region[ob_offset+i].total_len = 393 PM8001_MPI_QUEUE * 64; 394 pm8001_ha->memoryMap.region[ob_offset+i].alignment = 64; 395 } 396 397 } 398 /* Memory region write DMA*/ 399 pm8001_ha->memoryMap.region[NVMD].num_elements = 1; 400 pm8001_ha->memoryMap.region[NVMD].element_size = 4096; 401 pm8001_ha->memoryMap.region[NVMD].total_len = 4096; 402 403 /* Memory region for fw flash */ 404 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096; 405 406 pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1; 407 pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000; 408 pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000; 409 pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000; 410 for (i = 0; i < pm8001_ha->max_memcnt; i++) { 411 struct mpi_mem *region = &pm8001_ha->memoryMap.region[i]; 412 413 if (pm8001_mem_alloc(pm8001_ha->pdev, 414 ®ion->virt_ptr, 415 ®ion->phys_addr, 416 ®ion->phys_addr_hi, 417 ®ion->phys_addr_lo, 418 region->total_len, 419 region->alignment) != 0) { 420 pm8001_dbg(pm8001_ha, FAIL, "Mem%d alloc failed\n", i); 421 goto err_out; 422 } 423 } 424 425 /* Memory region for devices*/ 426 pm8001_ha->devices = kzalloc(PM8001_MAX_DEVICES 427 * sizeof(struct pm8001_device), GFP_KERNEL); 428 if (!pm8001_ha->devices) { 429 rc = -ENOMEM; 430 goto err_out_nodev; 431 } 432 for (i = 0; i < PM8001_MAX_DEVICES; i++) { 433 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED; 434 pm8001_ha->devices[i].id = i; 435 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES; 436 atomic_set(&pm8001_ha->devices[i].running_req, 0); 437 } 438 pm8001_ha->flags = PM8001F_INIT_TIME; 439 return 0; 440 441 err_out_nodev: 442 for (i = 0; i < pm8001_ha->max_memcnt; i++) { 443 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) { 444 dma_free_coherent(&pm8001_ha->pdev->dev, 445 (pm8001_ha->memoryMap.region[i].total_len + 446 pm8001_ha->memoryMap.region[i].alignment), 447 pm8001_ha->memoryMap.region[i].virt_ptr, 448 pm8001_ha->memoryMap.region[i].phys_addr); 449 } 450 } 451 err_out: 452 return 1; 453 } 454 455 /** 456 * pm8001_ioremap - remap the pci high physical address to kernel virtual 457 * address so that we can access them. 458 * @pm8001_ha: our hba structure. 459 */ 460 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha) 461 { 462 u32 bar; 463 u32 logicalBar = 0; 464 struct pci_dev *pdev; 465 466 pdev = pm8001_ha->pdev; 467 /* map pci mem (PMC pci base 0-3)*/ 468 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { 469 /* 470 ** logical BARs for SPC: 471 ** bar 0 and 1 - logical BAR0 472 ** bar 2 and 3 - logical BAR1 473 ** bar4 - logical BAR2 474 ** bar5 - logical BAR3 475 ** Skip the appropriate assignments: 476 */ 477 if ((bar == 1) || (bar == 3)) 478 continue; 479 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { 480 pm8001_ha->io_mem[logicalBar].membase = 481 pci_resource_start(pdev, bar); 482 pm8001_ha->io_mem[logicalBar].memsize = 483 pci_resource_len(pdev, bar); 484 pm8001_ha->io_mem[logicalBar].memvirtaddr = 485 ioremap(pm8001_ha->io_mem[logicalBar].membase, 486 pm8001_ha->io_mem[logicalBar].memsize); 487 if (!pm8001_ha->io_mem[logicalBar].memvirtaddr) { 488 pm8001_dbg(pm8001_ha, INIT, 489 "Failed to ioremap bar %d, logicalBar %d", 490 bar, logicalBar); 491 return -ENOMEM; 492 } 493 pm8001_dbg(pm8001_ha, INIT, 494 "base addr %llx virt_addr=%llx len=%d\n", 495 (u64)pm8001_ha->io_mem[logicalBar].membase, 496 (u64)(unsigned long) 497 pm8001_ha->io_mem[logicalBar].memvirtaddr, 498 pm8001_ha->io_mem[logicalBar].memsize); 499 } else { 500 pm8001_ha->io_mem[logicalBar].membase = 0; 501 pm8001_ha->io_mem[logicalBar].memsize = 0; 502 pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL; 503 } 504 logicalBar++; 505 } 506 return 0; 507 } 508 509 /** 510 * pm8001_pci_alloc - initialize our ha card structure 511 * @pdev: pci device. 512 * @ent: ent 513 * @shost: scsi host struct which has been initialized before. 514 */ 515 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev, 516 const struct pci_device_id *ent, 517 struct Scsi_Host *shost) 518 519 { 520 struct pm8001_hba_info *pm8001_ha; 521 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 522 int j; 523 524 pm8001_ha = sha->lldd_ha; 525 if (!pm8001_ha) 526 return NULL; 527 528 pm8001_ha->pdev = pdev; 529 pm8001_ha->dev = &pdev->dev; 530 pm8001_ha->chip_id = ent->driver_data; 531 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id]; 532 pm8001_ha->irq = pdev->irq; 533 pm8001_ha->sas = sha; 534 pm8001_ha->shost = shost; 535 pm8001_ha->id = pm8001_id++; 536 pm8001_ha->logging_level = logging_level; 537 pm8001_ha->non_fatal_count = 0; 538 if (link_rate >= 1 && link_rate <= 15) 539 pm8001_ha->link_rate = (link_rate << 8); 540 else { 541 pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 | 542 LINKRATE_60 | LINKRATE_120; 543 pm8001_dbg(pm8001_ha, FAIL, 544 "Setting link rate to default value\n"); 545 } 546 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id); 547 /* IOMB size is 128 for 8088/89 controllers */ 548 if (pm8001_ha->chip_id != chip_8001) 549 pm8001_ha->iomb_size = IOMB_SIZE_SPCV; 550 else 551 pm8001_ha->iomb_size = IOMB_SIZE_SPC; 552 553 #ifdef PM8001_USE_TASKLET 554 /* Tasklet for non msi-x interrupt handler */ 555 if ((!pdev->msix_cap || !pci_msi_enabled()) 556 || (pm8001_ha->chip_id == chip_8001)) 557 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet, 558 (unsigned long)&(pm8001_ha->irq_vector[0])); 559 else 560 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 561 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet, 562 (unsigned long)&(pm8001_ha->irq_vector[j])); 563 #endif 564 if (pm8001_ioremap(pm8001_ha)) 565 goto failed_pci_alloc; 566 if (!pm8001_alloc(pm8001_ha, ent)) 567 return pm8001_ha; 568 failed_pci_alloc: 569 pm8001_free(pm8001_ha); 570 return NULL; 571 } 572 573 /** 574 * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit 575 * @pdev: pci device. 576 */ 577 static int pci_go_44(struct pci_dev *pdev) 578 { 579 int rc; 580 581 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44)); 582 if (rc) { 583 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 584 if (rc) 585 dev_printk(KERN_ERR, &pdev->dev, 586 "32-bit DMA enable failed\n"); 587 } 588 return rc; 589 } 590 591 /** 592 * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them. 593 * @shost: scsi host which has been allocated outside. 594 * @chip_info: our ha struct. 595 */ 596 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost, 597 const struct pm8001_chip_info *chip_info) 598 { 599 int phy_nr, port_nr; 600 struct asd_sas_phy **arr_phy; 601 struct asd_sas_port **arr_port; 602 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 603 604 phy_nr = chip_info->n_phy; 605 port_nr = phy_nr; 606 memset(sha, 0x00, sizeof(*sha)); 607 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL); 608 if (!arr_phy) 609 goto exit; 610 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL); 611 if (!arr_port) 612 goto exit_free2; 613 614 sha->sas_phy = arr_phy; 615 sha->sas_port = arr_port; 616 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL); 617 if (!sha->lldd_ha) 618 goto exit_free1; 619 620 shost->transportt = pm8001_stt; 621 shost->max_id = PM8001_MAX_DEVICES; 622 shost->unique_id = pm8001_id; 623 shost->max_cmd_len = 16; 624 return 0; 625 exit_free1: 626 kfree(arr_port); 627 exit_free2: 628 kfree(arr_phy); 629 exit: 630 return -1; 631 } 632 633 /** 634 * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas 635 * @shost: scsi host which has been allocated outside 636 * @chip_info: our ha struct. 637 */ 638 static void pm8001_post_sas_ha_init(struct Scsi_Host *shost, 639 const struct pm8001_chip_info *chip_info) 640 { 641 int i = 0; 642 struct pm8001_hba_info *pm8001_ha; 643 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 644 645 pm8001_ha = sha->lldd_ha; 646 for (i = 0; i < chip_info->n_phy; i++) { 647 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy; 648 sha->sas_port[i] = &pm8001_ha->port[i].sas_port; 649 sha->sas_phy[i]->sas_addr = 650 (u8 *)&pm8001_ha->phy[i].dev_sas_addr; 651 } 652 sha->sas_ha_name = DRV_NAME; 653 sha->dev = pm8001_ha->dev; 654 sha->strict_wide_ports = 1; 655 sha->sas_addr = &pm8001_ha->sas_addr[0]; 656 sha->num_phys = chip_info->n_phy; 657 sha->shost = shost; 658 } 659 660 /** 661 * pm8001_init_sas_add - initialize sas address 662 * @pm8001_ha: our ha struct. 663 * 664 * Currently we just set the fixed SAS address to our HBA, for manufacture, 665 * it should read from the EEPROM 666 */ 667 static int pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha) 668 { 669 u8 i, j; 670 u8 sas_add[8]; 671 #ifdef PM8001_READ_VPD 672 /* For new SPC controllers WWN is stored in flash vpd 673 * For SPC/SPCve controllers WWN is stored in EEPROM 674 * For Older SPC WWN is stored in NVMD 675 */ 676 DECLARE_COMPLETION_ONSTACK(completion); 677 struct pm8001_ioctl_payload payload; 678 u16 deviceid; 679 int rc; 680 unsigned long time_remaining; 681 682 if (PM8001_CHIP_DISP->fatal_errors(pm8001_ha)) { 683 pm8001_dbg(pm8001_ha, FAIL, "controller is in fatal error state\n"); 684 return -EIO; 685 } 686 687 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid); 688 pm8001_ha->nvmd_completion = &completion; 689 690 if (pm8001_ha->chip_id == chip_8001) { 691 if (deviceid == 0x8081 || deviceid == 0x0042) { 692 payload.minor_function = 4; 693 payload.rd_length = 4096; 694 } else { 695 payload.minor_function = 0; 696 payload.rd_length = 128; 697 } 698 } else if ((pm8001_ha->chip_id == chip_8070 || 699 pm8001_ha->chip_id == chip_8072) && 700 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) { 701 payload.minor_function = 4; 702 payload.rd_length = 4096; 703 } else { 704 payload.minor_function = 1; 705 payload.rd_length = 4096; 706 } 707 payload.offset = 0; 708 payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL); 709 if (!payload.func_specific) { 710 pm8001_dbg(pm8001_ha, FAIL, "mem alloc fail\n"); 711 return -ENOMEM; 712 } 713 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload); 714 if (rc) { 715 kfree(payload.func_specific); 716 pm8001_dbg(pm8001_ha, FAIL, "nvmd failed\n"); 717 return -EIO; 718 } 719 time_remaining = wait_for_completion_timeout(&completion, 720 msecs_to_jiffies(60*1000)); // 1 min 721 if (!time_remaining) { 722 kfree(payload.func_specific); 723 pm8001_dbg(pm8001_ha, FAIL, "get_nvmd_req timeout\n"); 724 return -EIO; 725 } 726 727 728 for (i = 0, j = 0; i <= 7; i++, j++) { 729 if (pm8001_ha->chip_id == chip_8001) { 730 if (deviceid == 0x8081) 731 pm8001_ha->sas_addr[j] = 732 payload.func_specific[0x704 + i]; 733 else if (deviceid == 0x0042) 734 pm8001_ha->sas_addr[j] = 735 payload.func_specific[0x010 + i]; 736 } else if ((pm8001_ha->chip_id == chip_8070 || 737 pm8001_ha->chip_id == chip_8072) && 738 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) { 739 pm8001_ha->sas_addr[j] = 740 payload.func_specific[0x010 + i]; 741 } else 742 pm8001_ha->sas_addr[j] = 743 payload.func_specific[0x804 + i]; 744 } 745 memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE); 746 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 747 if (i && ((i % 4) == 0)) 748 sas_add[7] = sas_add[7] + 4; 749 memcpy(&pm8001_ha->phy[i].dev_sas_addr, 750 sas_add, SAS_ADDR_SIZE); 751 pm8001_dbg(pm8001_ha, INIT, "phy %d sas_addr = %016llx\n", i, 752 pm8001_ha->phy[i].dev_sas_addr); 753 } 754 kfree(payload.func_specific); 755 #else 756 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 757 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL; 758 pm8001_ha->phy[i].dev_sas_addr = 759 cpu_to_be64((u64) 760 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr)); 761 } 762 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr, 763 SAS_ADDR_SIZE); 764 #endif 765 return 0; 766 } 767 768 /* 769 * pm8001_get_phy_settings_info : Read phy setting values. 770 * @pm8001_ha : our hba. 771 */ 772 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha) 773 { 774 775 #ifdef PM8001_READ_VPD 776 /*OPTION ROM FLASH read for the SPC cards */ 777 DECLARE_COMPLETION_ONSTACK(completion); 778 struct pm8001_ioctl_payload payload; 779 int rc; 780 781 pm8001_ha->nvmd_completion = &completion; 782 /* SAS ADDRESS read from flash / EEPROM */ 783 payload.minor_function = 6; 784 payload.offset = 0; 785 payload.rd_length = 4096; 786 payload.func_specific = kzalloc(4096, GFP_KERNEL); 787 if (!payload.func_specific) 788 return -ENOMEM; 789 /* Read phy setting values from flash */ 790 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload); 791 if (rc) { 792 kfree(payload.func_specific); 793 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n"); 794 return -ENOMEM; 795 } 796 wait_for_completion(&completion); 797 pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific); 798 kfree(payload.func_specific); 799 #endif 800 return 0; 801 } 802 803 struct pm8001_mpi3_phy_pg_trx_config { 804 u32 LaneLosCfg; 805 u32 LanePgaCfg1; 806 u32 LanePisoCfg1; 807 u32 LanePisoCfg2; 808 u32 LanePisoCfg3; 809 u32 LanePisoCfg4; 810 u32 LanePisoCfg5; 811 u32 LanePisoCfg6; 812 u32 LaneBctCtrl; 813 }; 814 815 /** 816 * pm8001_get_internal_phy_settings - Retrieves the internal PHY settings 817 * @pm8001_ha : our adapter 818 * @phycfg : PHY config page to populate 819 */ 820 static 821 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha, 822 struct pm8001_mpi3_phy_pg_trx_config *phycfg) 823 { 824 phycfg->LaneLosCfg = 0x00000132; 825 phycfg->LanePgaCfg1 = 0x00203949; 826 phycfg->LanePisoCfg1 = 0x000000FF; 827 phycfg->LanePisoCfg2 = 0xFF000001; 828 phycfg->LanePisoCfg3 = 0xE7011300; 829 phycfg->LanePisoCfg4 = 0x631C40C0; 830 phycfg->LanePisoCfg5 = 0xF8102036; 831 phycfg->LanePisoCfg6 = 0xF74A1000; 832 phycfg->LaneBctCtrl = 0x00FB33F8; 833 } 834 835 /** 836 * pm8001_get_external_phy_settings - Retrieves the external PHY settings 837 * @pm8001_ha : our adapter 838 * @phycfg : PHY config page to populate 839 */ 840 static 841 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha, 842 struct pm8001_mpi3_phy_pg_trx_config *phycfg) 843 { 844 phycfg->LaneLosCfg = 0x00000132; 845 phycfg->LanePgaCfg1 = 0x00203949; 846 phycfg->LanePisoCfg1 = 0x000000FF; 847 phycfg->LanePisoCfg2 = 0xFF000001; 848 phycfg->LanePisoCfg3 = 0xE7011300; 849 phycfg->LanePisoCfg4 = 0x63349140; 850 phycfg->LanePisoCfg5 = 0xF8102036; 851 phycfg->LanePisoCfg6 = 0xF80D9300; 852 phycfg->LaneBctCtrl = 0x00FB33F8; 853 } 854 855 /** 856 * pm8001_get_phy_mask - Retrieves the mask that denotes if a PHY is int/ext 857 * @pm8001_ha : our adapter 858 * @phymask : The PHY mask 859 */ 860 static 861 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask) 862 { 863 switch (pm8001_ha->pdev->subsystem_device) { 864 case 0x0070: /* H1280 - 8 external 0 internal */ 865 case 0x0072: /* H12F0 - 16 external 0 internal */ 866 *phymask = 0x0000; 867 break; 868 869 case 0x0071: /* H1208 - 0 external 8 internal */ 870 case 0x0073: /* H120F - 0 external 16 internal */ 871 *phymask = 0xFFFF; 872 break; 873 874 case 0x0080: /* H1244 - 4 external 4 internal */ 875 *phymask = 0x00F0; 876 break; 877 878 case 0x0081: /* H1248 - 4 external 8 internal */ 879 *phymask = 0x0FF0; 880 break; 881 882 case 0x0082: /* H1288 - 8 external 8 internal */ 883 *phymask = 0xFF00; 884 break; 885 886 default: 887 pm8001_dbg(pm8001_ha, INIT, 888 "Unknown subsystem device=0x%.04x\n", 889 pm8001_ha->pdev->subsystem_device); 890 } 891 } 892 893 /** 894 * pm8001_set_phy_settings_ven_117c_12G() - Configure ATTO 12Gb PHY settings 895 * @pm8001_ha : our adapter 896 */ 897 static 898 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha) 899 { 900 struct pm8001_mpi3_phy_pg_trx_config phycfg_int; 901 struct pm8001_mpi3_phy_pg_trx_config phycfg_ext; 902 int phymask = 0; 903 int i = 0; 904 905 memset(&phycfg_int, 0, sizeof(phycfg_int)); 906 memset(&phycfg_ext, 0, sizeof(phycfg_ext)); 907 908 pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int); 909 pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext); 910 pm8001_get_phy_mask(pm8001_ha, &phymask); 911 912 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 913 if (phymask & (1 << i)) {/* Internal PHY */ 914 pm8001_set_phy_profile_single(pm8001_ha, i, 915 sizeof(phycfg_int) / sizeof(u32), 916 (u32 *)&phycfg_int); 917 918 } else { /* External PHY */ 919 pm8001_set_phy_profile_single(pm8001_ha, i, 920 sizeof(phycfg_ext) / sizeof(u32), 921 (u32 *)&phycfg_ext); 922 } 923 } 924 925 return 0; 926 } 927 928 /** 929 * pm8001_configure_phy_settings - Configures PHY settings based on vendor ID. 930 * @pm8001_ha : our hba. 931 */ 932 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha) 933 { 934 switch (pm8001_ha->pdev->subsystem_vendor) { 935 case PCI_VENDOR_ID_ATTO: 936 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */ 937 return 0; 938 else 939 return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha); 940 941 case PCI_VENDOR_ID_ADAPTEC2: 942 case 0: 943 return 0; 944 945 default: 946 return pm8001_get_phy_settings_info(pm8001_ha); 947 } 948 } 949 950 #ifdef PM8001_USE_MSIX 951 /** 952 * pm8001_setup_msix - enable MSI-X interrupt 953 * @pm8001_ha: our ha struct. 954 */ 955 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha) 956 { 957 unsigned int allocated_irq_vectors; 958 int rc; 959 960 /* SPCv controllers supports 64 msi-x */ 961 if (pm8001_ha->chip_id == chip_8001) { 962 rc = pci_alloc_irq_vectors(pm8001_ha->pdev, 1, 1, 963 PCI_IRQ_MSIX); 964 } else { 965 /* 966 * Queue index #0 is used always for housekeeping, so don't 967 * include in the affinity spreading. 968 */ 969 struct irq_affinity desc = { 970 .pre_vectors = 1, 971 }; 972 rc = pci_alloc_irq_vectors_affinity( 973 pm8001_ha->pdev, 2, PM8001_MAX_MSIX_VEC, 974 PCI_IRQ_MSIX | PCI_IRQ_AFFINITY, &desc); 975 } 976 977 allocated_irq_vectors = rc; 978 if (rc < 0) 979 return rc; 980 981 /* Assigns the number of interrupts */ 982 pm8001_ha->number_of_intr = allocated_irq_vectors; 983 984 /* Maximum queue number updating in HBA structure */ 985 pm8001_ha->max_q_num = allocated_irq_vectors; 986 987 pm8001_dbg(pm8001_ha, INIT, 988 "pci_alloc_irq_vectors request ret:%d no of intr %d\n", 989 rc, pm8001_ha->number_of_intr); 990 return 0; 991 } 992 993 static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha) 994 { 995 u32 i = 0, j = 0; 996 int flag = 0, rc = 0; 997 int nr_irqs = pm8001_ha->number_of_intr; 998 999 if (pm8001_ha->chip_id != chip_8001) 1000 flag &= ~IRQF_SHARED; 1001 1002 pm8001_dbg(pm8001_ha, INIT, 1003 "pci_enable_msix request number of intr %d\n", 1004 pm8001_ha->number_of_intr); 1005 1006 if (nr_irqs > ARRAY_SIZE(pm8001_ha->intr_drvname)) 1007 nr_irqs = ARRAY_SIZE(pm8001_ha->intr_drvname); 1008 1009 for (i = 0; i < nr_irqs; i++) { 1010 snprintf(pm8001_ha->intr_drvname[i], 1011 sizeof(pm8001_ha->intr_drvname[0]), 1012 "%s-%d", pm8001_ha->name, i); 1013 pm8001_ha->irq_vector[i].irq_id = i; 1014 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha; 1015 1016 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i), 1017 pm8001_interrupt_handler_msix, flag, 1018 pm8001_ha->intr_drvname[i], 1019 &(pm8001_ha->irq_vector[i])); 1020 if (rc) { 1021 for (j = 0; j < i; j++) { 1022 free_irq(pci_irq_vector(pm8001_ha->pdev, i), 1023 &(pm8001_ha->irq_vector[i])); 1024 } 1025 pci_free_irq_vectors(pm8001_ha->pdev); 1026 break; 1027 } 1028 } 1029 1030 return rc; 1031 } 1032 #endif 1033 1034 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha) 1035 { 1036 struct pci_dev *pdev; 1037 1038 pdev = pm8001_ha->pdev; 1039 1040 #ifdef PM8001_USE_MSIX 1041 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX)) 1042 return pm8001_setup_msix(pm8001_ha); 1043 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n"); 1044 #endif 1045 return 0; 1046 } 1047 1048 /** 1049 * pm8001_request_irq - register interrupt 1050 * @pm8001_ha: our ha struct. 1051 */ 1052 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha) 1053 { 1054 struct pci_dev *pdev; 1055 int rc; 1056 1057 pdev = pm8001_ha->pdev; 1058 1059 #ifdef PM8001_USE_MSIX 1060 if (pdev->msix_cap && pci_msi_enabled()) 1061 return pm8001_request_msix(pm8001_ha); 1062 else { 1063 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n"); 1064 goto intx; 1065 } 1066 #endif 1067 1068 intx: 1069 /* initialize the INT-X interrupt */ 1070 pm8001_ha->irq_vector[0].irq_id = 0; 1071 pm8001_ha->irq_vector[0].drv_inst = pm8001_ha; 1072 rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED, 1073 pm8001_ha->name, SHOST_TO_SAS_HA(pm8001_ha->shost)); 1074 return rc; 1075 } 1076 1077 /** 1078 * pm8001_pci_probe - probe supported device 1079 * @pdev: pci device which kernel has been prepared for. 1080 * @ent: pci device id 1081 * 1082 * This function is the main initialization function, when register a new 1083 * pci driver it is invoked, all struct and hardware initialization should be 1084 * done here, also, register interrupt. 1085 */ 1086 static int pm8001_pci_probe(struct pci_dev *pdev, 1087 const struct pci_device_id *ent) 1088 { 1089 unsigned int rc; 1090 u32 pci_reg; 1091 u8 i = 0; 1092 struct pm8001_hba_info *pm8001_ha; 1093 struct Scsi_Host *shost = NULL; 1094 const struct pm8001_chip_info *chip; 1095 struct sas_ha_struct *sha; 1096 1097 dev_printk(KERN_INFO, &pdev->dev, 1098 "pm80xx: driver version %s\n", DRV_VERSION); 1099 rc = pci_enable_device(pdev); 1100 if (rc) 1101 goto err_out_enable; 1102 pci_set_master(pdev); 1103 /* 1104 * Enable pci slot busmaster by setting pci command register. 1105 * This is required by FW for Cyclone card. 1106 */ 1107 1108 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg); 1109 pci_reg |= 0x157; 1110 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg); 1111 rc = pci_request_regions(pdev, DRV_NAME); 1112 if (rc) 1113 goto err_out_disable; 1114 rc = pci_go_44(pdev); 1115 if (rc) 1116 goto err_out_regions; 1117 1118 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *)); 1119 if (!shost) { 1120 rc = -ENOMEM; 1121 goto err_out_regions; 1122 } 1123 chip = &pm8001_chips[ent->driver_data]; 1124 sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL); 1125 if (!sha) { 1126 rc = -ENOMEM; 1127 goto err_out_free_host; 1128 } 1129 SHOST_TO_SAS_HA(shost) = sha; 1130 1131 rc = pm8001_prep_sas_ha_init(shost, chip); 1132 if (rc) { 1133 rc = -ENOMEM; 1134 goto err_out_free; 1135 } 1136 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost)); 1137 /* ent->driver variable is used to differentiate between controllers */ 1138 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost); 1139 if (!pm8001_ha) { 1140 rc = -ENOMEM; 1141 goto err_out_free; 1142 } 1143 1144 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1145 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); 1146 if (rc) { 1147 pm8001_dbg(pm8001_ha, FAIL, 1148 "chip_init failed [ret: %d]\n", rc); 1149 goto err_out_ha_free; 1150 } 1151 1152 rc = pm8001_init_ccb_tag(pm8001_ha); 1153 if (rc) 1154 goto err_out_enable; 1155 1156 1157 PM8001_CHIP_DISP->chip_post_init(pm8001_ha); 1158 1159 if (pm8001_ha->number_of_intr > 1) { 1160 shost->nr_hw_queues = pm8001_ha->number_of_intr - 1; 1161 /* 1162 * For now, ensure we're not sent too many commands by setting 1163 * host_tagset. This is also required if we start using request 1164 * tag. 1165 */ 1166 shost->host_tagset = 1; 1167 } 1168 1169 rc = scsi_add_host(shost, &pdev->dev); 1170 if (rc) 1171 goto err_out_ha_free; 1172 1173 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0); 1174 if (pm8001_ha->chip_id != chip_8001) { 1175 for (i = 1; i < pm8001_ha->number_of_intr; i++) 1176 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i); 1177 /* setup thermal configuration. */ 1178 pm80xx_set_thermal_config(pm8001_ha); 1179 } 1180 1181 rc = pm8001_init_sas_add(pm8001_ha); 1182 if (rc) 1183 goto err_out_shost; 1184 /* phy setting support for motherboard controller */ 1185 rc = pm8001_configure_phy_settings(pm8001_ha); 1186 if (rc) 1187 goto err_out_shost; 1188 1189 pm8001_post_sas_ha_init(shost, chip); 1190 rc = sas_register_ha(SHOST_TO_SAS_HA(shost)); 1191 if (rc) { 1192 pm8001_dbg(pm8001_ha, FAIL, 1193 "sas_register_ha failed [ret: %d]\n", rc); 1194 goto err_out_shost; 1195 } 1196 list_add_tail(&pm8001_ha->list, &hba_list); 1197 pm8001_ha->flags = PM8001F_RUN_TIME; 1198 scsi_scan_host(pm8001_ha->shost); 1199 return 0; 1200 1201 err_out_shost: 1202 scsi_remove_host(pm8001_ha->shost); 1203 err_out_ha_free: 1204 pm8001_free(pm8001_ha); 1205 err_out_free: 1206 kfree(sha); 1207 err_out_free_host: 1208 scsi_host_put(shost); 1209 err_out_regions: 1210 pci_release_regions(pdev); 1211 err_out_disable: 1212 pci_disable_device(pdev); 1213 err_out_enable: 1214 return rc; 1215 } 1216 1217 /** 1218 * pm8001_init_ccb_tag - allocate memory to CCB and tag. 1219 * @pm8001_ha: our hba card information. 1220 */ 1221 static int pm8001_init_ccb_tag(struct pm8001_hba_info *pm8001_ha) 1222 { 1223 struct Scsi_Host *shost = pm8001_ha->shost; 1224 struct device *dev = pm8001_ha->dev; 1225 u32 max_out_io, ccb_count; 1226 int i; 1227 1228 max_out_io = pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io; 1229 ccb_count = min_t(int, PM8001_MAX_CCB, max_out_io); 1230 1231 shost->can_queue = ccb_count - PM8001_RESERVE_SLOT; 1232 1233 pm8001_ha->rsvd_tags = bitmap_zalloc(PM8001_RESERVE_SLOT, GFP_KERNEL); 1234 if (!pm8001_ha->rsvd_tags) 1235 goto err_out; 1236 1237 /* Memory region for ccb_info*/ 1238 pm8001_ha->ccb_count = ccb_count; 1239 pm8001_ha->ccb_info = 1240 kcalloc(ccb_count, sizeof(struct pm8001_ccb_info), GFP_KERNEL); 1241 if (!pm8001_ha->ccb_info) { 1242 pm8001_dbg(pm8001_ha, FAIL, 1243 "Unable to allocate memory for ccb\n"); 1244 goto err_out_noccb; 1245 } 1246 for (i = 0; i < ccb_count; i++) { 1247 pm8001_ha->ccb_info[i].buf_prd = dma_alloc_coherent(dev, 1248 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG, 1249 &pm8001_ha->ccb_info[i].ccb_dma_handle, 1250 GFP_KERNEL); 1251 if (!pm8001_ha->ccb_info[i].buf_prd) { 1252 pm8001_dbg(pm8001_ha, FAIL, 1253 "ccb prd memory allocation error\n"); 1254 goto err_out; 1255 } 1256 pm8001_ha->ccb_info[i].task = NULL; 1257 pm8001_ha->ccb_info[i].ccb_tag = PM8001_INVALID_TAG; 1258 pm8001_ha->ccb_info[i].device = NULL; 1259 } 1260 1261 return 0; 1262 1263 err_out_noccb: 1264 kfree(pm8001_ha->devices); 1265 err_out: 1266 return -ENOMEM; 1267 } 1268 1269 static void pm8001_pci_remove(struct pci_dev *pdev) 1270 { 1271 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1272 struct pm8001_hba_info *pm8001_ha; 1273 int i, j; 1274 pm8001_ha = sha->lldd_ha; 1275 sas_unregister_ha(sha); 1276 sas_remove_host(pm8001_ha->shost); 1277 list_del(&pm8001_ha->list); 1278 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1279 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1280 1281 #ifdef PM8001_USE_MSIX 1282 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1283 synchronize_irq(pci_irq_vector(pdev, i)); 1284 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1285 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]); 1286 pci_free_irq_vectors(pdev); 1287 #else 1288 free_irq(pm8001_ha->irq, sha); 1289 #endif 1290 #ifdef PM8001_USE_TASKLET 1291 /* For non-msix and msix interrupts */ 1292 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1293 (pm8001_ha->chip_id == chip_8001)) 1294 tasklet_kill(&pm8001_ha->tasklet[0]); 1295 else 1296 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1297 tasklet_kill(&pm8001_ha->tasklet[j]); 1298 #endif 1299 scsi_host_put(pm8001_ha->shost); 1300 1301 for (i = 0; i < pm8001_ha->ccb_count; i++) { 1302 dma_free_coherent(&pm8001_ha->pdev->dev, 1303 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG, 1304 pm8001_ha->ccb_info[i].buf_prd, 1305 pm8001_ha->ccb_info[i].ccb_dma_handle); 1306 } 1307 kfree(pm8001_ha->ccb_info); 1308 kfree(pm8001_ha->devices); 1309 1310 pm8001_free(pm8001_ha); 1311 kfree(sha->sas_phy); 1312 kfree(sha->sas_port); 1313 kfree(sha); 1314 pci_release_regions(pdev); 1315 pci_disable_device(pdev); 1316 } 1317 1318 /** 1319 * pm8001_pci_suspend - power management suspend main entry point 1320 * @dev: Device struct 1321 * 1322 * Return: 0 on success, anything else on error. 1323 */ 1324 static int __maybe_unused pm8001_pci_suspend(struct device *dev) 1325 { 1326 struct pci_dev *pdev = to_pci_dev(dev); 1327 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1328 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 1329 int i, j; 1330 sas_suspend_ha(sha); 1331 flush_workqueue(pm8001_wq); 1332 scsi_block_requests(pm8001_ha->shost); 1333 if (!pdev->pm_cap) { 1334 dev_err(dev, " PCI PM not supported\n"); 1335 return -ENODEV; 1336 } 1337 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1338 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1339 #ifdef PM8001_USE_MSIX 1340 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1341 synchronize_irq(pci_irq_vector(pdev, i)); 1342 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1343 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]); 1344 pci_free_irq_vectors(pdev); 1345 #else 1346 free_irq(pm8001_ha->irq, sha); 1347 #endif 1348 #ifdef PM8001_USE_TASKLET 1349 /* For non-msix and msix interrupts */ 1350 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1351 (pm8001_ha->chip_id == chip_8001)) 1352 tasklet_kill(&pm8001_ha->tasklet[0]); 1353 else 1354 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1355 tasklet_kill(&pm8001_ha->tasklet[j]); 1356 #endif 1357 pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, entering " 1358 "suspended state\n", pdev, 1359 pm8001_ha->name); 1360 return 0; 1361 } 1362 1363 /** 1364 * pm8001_pci_resume - power management resume main entry point 1365 * @dev: Device struct 1366 * 1367 * Return: 0 on success, anything else on error. 1368 */ 1369 static int __maybe_unused pm8001_pci_resume(struct device *dev) 1370 { 1371 struct pci_dev *pdev = to_pci_dev(dev); 1372 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1373 struct pm8001_hba_info *pm8001_ha; 1374 int rc; 1375 u8 i = 0, j; 1376 DECLARE_COMPLETION_ONSTACK(completion); 1377 1378 pm8001_ha = sha->lldd_ha; 1379 1380 pm8001_info(pm8001_ha, 1381 "pdev=0x%p, slot=%s, resuming from previous operating state [D%d]\n", 1382 pdev, pm8001_ha->name, pdev->current_state); 1383 1384 rc = pci_go_44(pdev); 1385 if (rc) 1386 goto err_out_disable; 1387 sas_prep_resume_ha(sha); 1388 /* chip soft rst only for spc */ 1389 if (pm8001_ha->chip_id == chip_8001) { 1390 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1391 pm8001_dbg(pm8001_ha, INIT, "chip soft reset successful\n"); 1392 } 1393 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); 1394 if (rc) 1395 goto err_out_disable; 1396 1397 /* disable all the interrupt bits */ 1398 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1399 1400 rc = pm8001_request_irq(pm8001_ha); 1401 if (rc) 1402 goto err_out_disable; 1403 #ifdef PM8001_USE_TASKLET 1404 /* Tasklet for non msi-x interrupt handler */ 1405 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1406 (pm8001_ha->chip_id == chip_8001)) 1407 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet, 1408 (unsigned long)&(pm8001_ha->irq_vector[0])); 1409 else 1410 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1411 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet, 1412 (unsigned long)&(pm8001_ha->irq_vector[j])); 1413 #endif 1414 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0); 1415 if (pm8001_ha->chip_id != chip_8001) { 1416 for (i = 1; i < pm8001_ha->number_of_intr; i++) 1417 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i); 1418 } 1419 1420 /* Chip documentation for the 8070 and 8072 SPCv */ 1421 /* states that a 500ms minimum delay is required */ 1422 /* before issuing commands. Otherwise, the firmware */ 1423 /* will enter an unrecoverable state. */ 1424 1425 if (pm8001_ha->chip_id == chip_8070 || 1426 pm8001_ha->chip_id == chip_8072) { 1427 mdelay(500); 1428 } 1429 1430 /* Spin up the PHYs */ 1431 1432 pm8001_ha->flags = PM8001F_RUN_TIME; 1433 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 1434 pm8001_ha->phy[i].enable_completion = &completion; 1435 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i); 1436 wait_for_completion(&completion); 1437 } 1438 sas_resume_ha(sha); 1439 return 0; 1440 1441 err_out_disable: 1442 scsi_remove_host(pm8001_ha->shost); 1443 1444 return rc; 1445 } 1446 1447 /* update of pci device, vendor id and driver data with 1448 * unique value for each of the controller 1449 */ 1450 static struct pci_device_id pm8001_pci_table[] = { 1451 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 }, 1452 { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 }, 1453 { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 }, 1454 { PCI_VDEVICE(ATTO, 0x0042), chip_8001 }, 1455 /* Support for SPC/SPCv/SPCve controllers */ 1456 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 }, 1457 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 }, 1458 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 }, 1459 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 }, 1460 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 }, 1461 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 }, 1462 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 }, 1463 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 }, 1464 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 }, 1465 { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 }, 1466 { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 }, 1467 { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 }, 1468 { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 }, 1469 { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 }, 1470 { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 }, 1471 { PCI_VENDOR_ID_ADAPTEC2, 0x8081, 1472 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 }, 1473 { PCI_VENDOR_ID_ADAPTEC2, 0x8081, 1474 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 }, 1475 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1476 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 }, 1477 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1478 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 }, 1479 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1480 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 }, 1481 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1482 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 }, 1483 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1484 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 }, 1485 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1486 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 }, 1487 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1488 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 }, 1489 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1490 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 }, 1491 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1492 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 }, 1493 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1494 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 }, 1495 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1496 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 }, 1497 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1498 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 }, 1499 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1500 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 }, 1501 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1502 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 }, 1503 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1504 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 }, 1505 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1506 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 }, 1507 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1508 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 }, 1509 { PCI_VENDOR_ID_ATTO, 0x8070, 1510 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 }, 1511 { PCI_VENDOR_ID_ATTO, 0x8070, 1512 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 }, 1513 { PCI_VENDOR_ID_ATTO, 0x8072, 1514 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 }, 1515 { PCI_VENDOR_ID_ATTO, 0x8072, 1516 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 }, 1517 { PCI_VENDOR_ID_ATTO, 0x8070, 1518 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 }, 1519 { PCI_VENDOR_ID_ATTO, 0x8072, 1520 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 }, 1521 { PCI_VENDOR_ID_ATTO, 0x8072, 1522 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 }, 1523 {} /* terminate list */ 1524 }; 1525 1526 static SIMPLE_DEV_PM_OPS(pm8001_pci_pm_ops, 1527 pm8001_pci_suspend, 1528 pm8001_pci_resume); 1529 1530 static struct pci_driver pm8001_pci_driver = { 1531 .name = DRV_NAME, 1532 .id_table = pm8001_pci_table, 1533 .probe = pm8001_pci_probe, 1534 .remove = pm8001_pci_remove, 1535 .driver.pm = &pm8001_pci_pm_ops, 1536 }; 1537 1538 /** 1539 * pm8001_init - initialize scsi transport template 1540 */ 1541 static int __init pm8001_init(void) 1542 { 1543 int rc = -ENOMEM; 1544 1545 pm8001_wq = alloc_workqueue("pm80xx", 0, 0); 1546 if (!pm8001_wq) 1547 goto err; 1548 1549 pm8001_id = 0; 1550 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops); 1551 if (!pm8001_stt) 1552 goto err_wq; 1553 rc = pci_register_driver(&pm8001_pci_driver); 1554 if (rc) 1555 goto err_tp; 1556 return 0; 1557 1558 err_tp: 1559 sas_release_transport(pm8001_stt); 1560 err_wq: 1561 destroy_workqueue(pm8001_wq); 1562 err: 1563 return rc; 1564 } 1565 1566 static void __exit pm8001_exit(void) 1567 { 1568 pci_unregister_driver(&pm8001_pci_driver); 1569 sas_release_transport(pm8001_stt); 1570 destroy_workqueue(pm8001_wq); 1571 } 1572 1573 module_init(pm8001_init); 1574 module_exit(pm8001_exit); 1575 1576 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>"); 1577 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>"); 1578 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>"); 1579 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>"); 1580 MODULE_DESCRIPTION( 1581 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 " 1582 "SAS/SATA controller driver"); 1583 MODULE_VERSION(DRV_VERSION); 1584 MODULE_LICENSE("GPL"); 1585 MODULE_DEVICE_TABLE(pci, pm8001_pci_table); 1586 1587