1 /*
2  * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
3  *
4  * Copyright (c) 2008-2009 USI Co., Ltd.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions, and the following disclaimer,
12  *    without modification.
13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14  *    substantially similar to the "NO WARRANTY" disclaimer below
15  *    ("Disclaimer") and any redistribution must be conditioned upon
16  *    including a substantially similar Disclaimer requirement for further
17  *    binary redistribution.
18  * 3. Neither the names of the above-listed copyright holders nor the names
19  *    of any contributors may be used to endorse or promote products derived
20  *    from this software without specific prior written permission.
21  *
22  * Alternatively, this software may be distributed under the terms of the
23  * GNU General Public License ("GPL") version 2 as published by the Free
24  * Software Foundation.
25  *
26  * NO WARRANTY
27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37  * POSSIBILITY OF SUCH DAMAGES.
38  *
39  */
40 
41 #include <linux/slab.h>
42 #include "pm8001_sas.h"
43 #include "pm8001_chips.h"
44 
45 static struct scsi_transport_template *pm8001_stt;
46 
47 /**
48  * chip info structure to identify chip key functionality as
49  * encryption available/not, no of ports, hw specific function ref
50  */
51 static const struct pm8001_chip_info pm8001_chips[] = {
52 	[chip_8001] = {0,  8, &pm8001_8001_dispatch,},
53 	[chip_8008] = {0,  8, &pm8001_80xx_dispatch,},
54 	[chip_8009] = {1,  8, &pm8001_80xx_dispatch,},
55 	[chip_8018] = {0,  16, &pm8001_80xx_dispatch,},
56 	[chip_8019] = {1,  16, &pm8001_80xx_dispatch,},
57 	[chip_8074] = {0,  8, &pm8001_80xx_dispatch,},
58 	[chip_8076] = {0,  16, &pm8001_80xx_dispatch,},
59 	[chip_8077] = {0,  16, &pm8001_80xx_dispatch,},
60 };
61 static int pm8001_id;
62 
63 LIST_HEAD(hba_list);
64 
65 struct workqueue_struct *pm8001_wq;
66 
67 /**
68  * The main structure which LLDD must register for scsi core.
69  */
70 static struct scsi_host_template pm8001_sht = {
71 	.module			= THIS_MODULE,
72 	.name			= DRV_NAME,
73 	.queuecommand		= sas_queuecommand,
74 	.target_alloc		= sas_target_alloc,
75 	.slave_configure	= sas_slave_configure,
76 	.scan_finished		= pm8001_scan_finished,
77 	.scan_start		= pm8001_scan_start,
78 	.change_queue_depth	= sas_change_queue_depth,
79 	.change_queue_type	= sas_change_queue_type,
80 	.bios_param		= sas_bios_param,
81 	.can_queue		= 1,
82 	.cmd_per_lun		= 1,
83 	.this_id		= -1,
84 	.sg_tablesize		= SG_ALL,
85 	.max_sectors		= SCSI_DEFAULT_MAX_SECTORS,
86 	.use_clustering		= ENABLE_CLUSTERING,
87 	.eh_device_reset_handler = sas_eh_device_reset_handler,
88 	.eh_bus_reset_handler	= sas_eh_bus_reset_handler,
89 	.target_destroy		= sas_target_destroy,
90 	.ioctl			= sas_ioctl,
91 	.shost_attrs		= pm8001_host_attrs,
92 };
93 
94 /**
95  * Sas layer call this function to execute specific task.
96  */
97 static struct sas_domain_function_template pm8001_transport_ops = {
98 	.lldd_dev_found		= pm8001_dev_found,
99 	.lldd_dev_gone		= pm8001_dev_gone,
100 
101 	.lldd_execute_task	= pm8001_queue_command,
102 	.lldd_control_phy	= pm8001_phy_control,
103 
104 	.lldd_abort_task	= pm8001_abort_task,
105 	.lldd_abort_task_set	= pm8001_abort_task_set,
106 	.lldd_clear_aca		= pm8001_clear_aca,
107 	.lldd_clear_task_set	= pm8001_clear_task_set,
108 	.lldd_I_T_nexus_reset   = pm8001_I_T_nexus_reset,
109 	.lldd_lu_reset		= pm8001_lu_reset,
110 	.lldd_query_task	= pm8001_query_task,
111 };
112 
113 /**
114  *pm8001_phy_init - initiate our adapter phys
115  *@pm8001_ha: our hba structure.
116  *@phy_id: phy id.
117  */
118 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
119 {
120 	struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
121 	struct asd_sas_phy *sas_phy = &phy->sas_phy;
122 	phy->phy_state = 0;
123 	phy->pm8001_ha = pm8001_ha;
124 	sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
125 	sas_phy->class = SAS;
126 	sas_phy->iproto = SAS_PROTOCOL_ALL;
127 	sas_phy->tproto = 0;
128 	sas_phy->type = PHY_TYPE_PHYSICAL;
129 	sas_phy->role = PHY_ROLE_INITIATOR;
130 	sas_phy->oob_mode = OOB_NOT_CONNECTED;
131 	sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
132 	sas_phy->id = phy_id;
133 	sas_phy->sas_addr = &pm8001_ha->sas_addr[0];
134 	sas_phy->frame_rcvd = &phy->frame_rcvd[0];
135 	sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
136 	sas_phy->lldd_phy = phy;
137 }
138 
139 /**
140  *pm8001_free - free hba
141  *@pm8001_ha:	our hba structure.
142  *
143  */
144 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
145 {
146 	int i;
147 
148 	if (!pm8001_ha)
149 		return;
150 
151 	for (i = 0; i < USI_MAX_MEMCNT; i++) {
152 		if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
153 			pci_free_consistent(pm8001_ha->pdev,
154 				(pm8001_ha->memoryMap.region[i].total_len +
155 				pm8001_ha->memoryMap.region[i].alignment),
156 				pm8001_ha->memoryMap.region[i].virt_ptr,
157 				pm8001_ha->memoryMap.region[i].phys_addr);
158 			}
159 	}
160 	PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
161 	if (pm8001_ha->shost)
162 		scsi_host_put(pm8001_ha->shost);
163 	flush_workqueue(pm8001_wq);
164 	kfree(pm8001_ha->tags);
165 	kfree(pm8001_ha);
166 }
167 
168 #ifdef PM8001_USE_TASKLET
169 
170 /**
171  * tasklet for 64 msi-x interrupt handler
172  * @opaque: the passed general host adapter struct
173  * Note: pm8001_tasklet is common for pm8001 & pm80xx
174  */
175 static void pm8001_tasklet(unsigned long opaque)
176 {
177 	struct pm8001_hba_info *pm8001_ha;
178 	struct isr_param *irq_vector;
179 
180 	irq_vector = (struct isr_param *)opaque;
181 	pm8001_ha = irq_vector->drv_inst;
182 	if (unlikely(!pm8001_ha))
183 		BUG_ON(1);
184 	PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
185 }
186 #endif
187 
188 /**
189  * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
190  * It obtains the vector number and calls the equivalent bottom
191  * half or services directly.
192  * @opaque: the passed outbound queue/vector. Host structure is
193  * retrieved from the same.
194  */
195 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
196 {
197 	struct isr_param *irq_vector;
198 	struct pm8001_hba_info *pm8001_ha;
199 	irqreturn_t ret = IRQ_HANDLED;
200 	irq_vector = (struct isr_param *)opaque;
201 	pm8001_ha = irq_vector->drv_inst;
202 
203 	if (unlikely(!pm8001_ha))
204 		return IRQ_NONE;
205 	if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
206 		return IRQ_NONE;
207 #ifdef PM8001_USE_TASKLET
208 	tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
209 #else
210 	ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
211 #endif
212 	return ret;
213 }
214 
215 /**
216  * pm8001_interrupt_handler_intx - main INTx interrupt handler.
217  * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure.
218  */
219 
220 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
221 {
222 	struct pm8001_hba_info *pm8001_ha;
223 	irqreturn_t ret = IRQ_HANDLED;
224 	struct sas_ha_struct *sha = dev_id;
225 	pm8001_ha = sha->lldd_ha;
226 	if (unlikely(!pm8001_ha))
227 		return IRQ_NONE;
228 	if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
229 		return IRQ_NONE;
230 
231 #ifdef PM8001_USE_TASKLET
232 	tasklet_schedule(&pm8001_ha->tasklet[0]);
233 #else
234 	ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
235 #endif
236 	return ret;
237 }
238 
239 /**
240  * pm8001_alloc - initiate our hba structure and 6 DMAs area.
241  * @pm8001_ha:our hba structure.
242  *
243  */
244 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
245 			const struct pci_device_id *ent)
246 {
247 	int i;
248 	spin_lock_init(&pm8001_ha->lock);
249 	PM8001_INIT_DBG(pm8001_ha,
250 		pm8001_printk("pm8001_alloc: PHY:%x\n",
251 				pm8001_ha->chip->n_phy));
252 	for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
253 		pm8001_phy_init(pm8001_ha, i);
254 		pm8001_ha->port[i].wide_port_phymap = 0;
255 		pm8001_ha->port[i].port_attached = 0;
256 		pm8001_ha->port[i].port_state = 0;
257 		INIT_LIST_HEAD(&pm8001_ha->port[i].list);
258 	}
259 
260 	pm8001_ha->tags = kzalloc(PM8001_MAX_CCB, GFP_KERNEL);
261 	if (!pm8001_ha->tags)
262 		goto err_out;
263 	/* MPI Memory region 1 for AAP Event Log for fw */
264 	pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
265 	pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
266 	pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
267 	pm8001_ha->memoryMap.region[AAP1].alignment = 32;
268 
269 	/* MPI Memory region 2 for IOP Event Log for fw */
270 	pm8001_ha->memoryMap.region[IOP].num_elements = 1;
271 	pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
272 	pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
273 	pm8001_ha->memoryMap.region[IOP].alignment = 32;
274 
275 	for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
276 		/* MPI Memory region 3 for consumer Index of inbound queues */
277 		pm8001_ha->memoryMap.region[CI+i].num_elements = 1;
278 		pm8001_ha->memoryMap.region[CI+i].element_size = 4;
279 		pm8001_ha->memoryMap.region[CI+i].total_len = 4;
280 		pm8001_ha->memoryMap.region[CI+i].alignment = 4;
281 
282 		if ((ent->driver_data) != chip_8001) {
283 			/* MPI Memory region 5 inbound queues */
284 			pm8001_ha->memoryMap.region[IB+i].num_elements =
285 						PM8001_MPI_QUEUE;
286 			pm8001_ha->memoryMap.region[IB+i].element_size = 128;
287 			pm8001_ha->memoryMap.region[IB+i].total_len =
288 						PM8001_MPI_QUEUE * 128;
289 			pm8001_ha->memoryMap.region[IB+i].alignment = 128;
290 		} else {
291 			pm8001_ha->memoryMap.region[IB+i].num_elements =
292 						PM8001_MPI_QUEUE;
293 			pm8001_ha->memoryMap.region[IB+i].element_size = 64;
294 			pm8001_ha->memoryMap.region[IB+i].total_len =
295 						PM8001_MPI_QUEUE * 64;
296 			pm8001_ha->memoryMap.region[IB+i].alignment = 64;
297 		}
298 	}
299 
300 	for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
301 		/* MPI Memory region 4 for producer Index of outbound queues */
302 		pm8001_ha->memoryMap.region[PI+i].num_elements = 1;
303 		pm8001_ha->memoryMap.region[PI+i].element_size = 4;
304 		pm8001_ha->memoryMap.region[PI+i].total_len = 4;
305 		pm8001_ha->memoryMap.region[PI+i].alignment = 4;
306 
307 		if (ent->driver_data != chip_8001) {
308 			/* MPI Memory region 6 Outbound queues */
309 			pm8001_ha->memoryMap.region[OB+i].num_elements =
310 						PM8001_MPI_QUEUE;
311 			pm8001_ha->memoryMap.region[OB+i].element_size = 128;
312 			pm8001_ha->memoryMap.region[OB+i].total_len =
313 						PM8001_MPI_QUEUE * 128;
314 			pm8001_ha->memoryMap.region[OB+i].alignment = 128;
315 		} else {
316 			/* MPI Memory region 6 Outbound queues */
317 			pm8001_ha->memoryMap.region[OB+i].num_elements =
318 						PM8001_MPI_QUEUE;
319 			pm8001_ha->memoryMap.region[OB+i].element_size = 64;
320 			pm8001_ha->memoryMap.region[OB+i].total_len =
321 						PM8001_MPI_QUEUE * 64;
322 			pm8001_ha->memoryMap.region[OB+i].alignment = 64;
323 		}
324 
325 	}
326 	/* Memory region write DMA*/
327 	pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
328 	pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
329 	pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
330 	/* Memory region for devices*/
331 	pm8001_ha->memoryMap.region[DEV_MEM].num_elements = 1;
332 	pm8001_ha->memoryMap.region[DEV_MEM].element_size = PM8001_MAX_DEVICES *
333 		sizeof(struct pm8001_device);
334 	pm8001_ha->memoryMap.region[DEV_MEM].total_len = PM8001_MAX_DEVICES *
335 		sizeof(struct pm8001_device);
336 
337 	/* Memory region for ccb_info*/
338 	pm8001_ha->memoryMap.region[CCB_MEM].num_elements = 1;
339 	pm8001_ha->memoryMap.region[CCB_MEM].element_size = PM8001_MAX_CCB *
340 		sizeof(struct pm8001_ccb_info);
341 	pm8001_ha->memoryMap.region[CCB_MEM].total_len = PM8001_MAX_CCB *
342 		sizeof(struct pm8001_ccb_info);
343 
344 	/* Memory region for fw flash */
345 	pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
346 
347 	pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
348 	pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
349 	pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
350 	pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
351 	for (i = 0; i < USI_MAX_MEMCNT; i++) {
352 		if (pm8001_mem_alloc(pm8001_ha->pdev,
353 			&pm8001_ha->memoryMap.region[i].virt_ptr,
354 			&pm8001_ha->memoryMap.region[i].phys_addr,
355 			&pm8001_ha->memoryMap.region[i].phys_addr_hi,
356 			&pm8001_ha->memoryMap.region[i].phys_addr_lo,
357 			pm8001_ha->memoryMap.region[i].total_len,
358 			pm8001_ha->memoryMap.region[i].alignment) != 0) {
359 				PM8001_FAIL_DBG(pm8001_ha,
360 					pm8001_printk("Mem%d alloc failed\n",
361 					i));
362 				goto err_out;
363 		}
364 	}
365 
366 	pm8001_ha->devices = pm8001_ha->memoryMap.region[DEV_MEM].virt_ptr;
367 	for (i = 0; i < PM8001_MAX_DEVICES; i++) {
368 		pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
369 		pm8001_ha->devices[i].id = i;
370 		pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
371 		pm8001_ha->devices[i].running_req = 0;
372 	}
373 	pm8001_ha->ccb_info = pm8001_ha->memoryMap.region[CCB_MEM].virt_ptr;
374 	for (i = 0; i < PM8001_MAX_CCB; i++) {
375 		pm8001_ha->ccb_info[i].ccb_dma_handle =
376 			pm8001_ha->memoryMap.region[CCB_MEM].phys_addr +
377 			i * sizeof(struct pm8001_ccb_info);
378 		pm8001_ha->ccb_info[i].task = NULL;
379 		pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
380 		pm8001_ha->ccb_info[i].device = NULL;
381 		++pm8001_ha->tags_num;
382 	}
383 	pm8001_ha->flags = PM8001F_INIT_TIME;
384 	/* Initialize tags */
385 	pm8001_tag_init(pm8001_ha);
386 	return 0;
387 err_out:
388 	return 1;
389 }
390 
391 /**
392  * pm8001_ioremap - remap the pci high physical address to kernal virtual
393  * address so that we can access them.
394  * @pm8001_ha:our hba structure.
395  */
396 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
397 {
398 	u32 bar;
399 	u32 logicalBar = 0;
400 	struct pci_dev *pdev;
401 
402 	pdev = pm8001_ha->pdev;
403 	/* map pci mem (PMC pci base 0-3)*/
404 	for (bar = 0; bar < 6; bar++) {
405 		/*
406 		** logical BARs for SPC:
407 		** bar 0 and 1 - logical BAR0
408 		** bar 2 and 3 - logical BAR1
409 		** bar4 - logical BAR2
410 		** bar5 - logical BAR3
411 		** Skip the appropriate assignments:
412 		*/
413 		if ((bar == 1) || (bar == 3))
414 			continue;
415 		if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
416 			pm8001_ha->io_mem[logicalBar].membase =
417 				pci_resource_start(pdev, bar);
418 			pm8001_ha->io_mem[logicalBar].membase &=
419 				(u32)PCI_BASE_ADDRESS_MEM_MASK;
420 			pm8001_ha->io_mem[logicalBar].memsize =
421 				pci_resource_len(pdev, bar);
422 			pm8001_ha->io_mem[logicalBar].memvirtaddr =
423 				ioremap(pm8001_ha->io_mem[logicalBar].membase,
424 				pm8001_ha->io_mem[logicalBar].memsize);
425 			PM8001_INIT_DBG(pm8001_ha,
426 				pm8001_printk("PCI: bar %d, logicalBar %d ",
427 				bar, logicalBar));
428 			PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
429 				"base addr %llx virt_addr=%llx len=%d\n",
430 				(u64)pm8001_ha->io_mem[logicalBar].membase,
431 				(u64)(unsigned long)
432 				pm8001_ha->io_mem[logicalBar].memvirtaddr,
433 				pm8001_ha->io_mem[logicalBar].memsize));
434 		} else {
435 			pm8001_ha->io_mem[logicalBar].membase	= 0;
436 			pm8001_ha->io_mem[logicalBar].memsize	= 0;
437 			pm8001_ha->io_mem[logicalBar].memvirtaddr = 0;
438 		}
439 		logicalBar++;
440 	}
441 	return 0;
442 }
443 
444 /**
445  * pm8001_pci_alloc - initialize our ha card structure
446  * @pdev: pci device.
447  * @ent: ent
448  * @shost: scsi host struct which has been initialized before.
449  */
450 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
451 				 const struct pci_device_id *ent,
452 				struct Scsi_Host *shost)
453 
454 {
455 	struct pm8001_hba_info *pm8001_ha;
456 	struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
457 	int j;
458 
459 	pm8001_ha = sha->lldd_ha;
460 	if (!pm8001_ha)
461 		return NULL;
462 
463 	pm8001_ha->pdev = pdev;
464 	pm8001_ha->dev = &pdev->dev;
465 	pm8001_ha->chip_id = ent->driver_data;
466 	pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
467 	pm8001_ha->irq = pdev->irq;
468 	pm8001_ha->sas = sha;
469 	pm8001_ha->shost = shost;
470 	pm8001_ha->id = pm8001_id++;
471 	pm8001_ha->logging_level = 0x01;
472 	sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
473 	/* IOMB size is 128 for 8088/89 controllers */
474 	if (pm8001_ha->chip_id != chip_8001)
475 		pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
476 	else
477 		pm8001_ha->iomb_size = IOMB_SIZE_SPC;
478 
479 #ifdef PM8001_USE_TASKLET
480 	/* Tasklet for non msi-x interrupt handler */
481 	if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
482 		tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
483 			(unsigned long)&(pm8001_ha->irq_vector[0]));
484 	else
485 		for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
486 			tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
487 				(unsigned long)&(pm8001_ha->irq_vector[j]));
488 #endif
489 	pm8001_ioremap(pm8001_ha);
490 	if (!pm8001_alloc(pm8001_ha, ent))
491 		return pm8001_ha;
492 	pm8001_free(pm8001_ha);
493 	return NULL;
494 }
495 
496 /**
497  * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
498  * @pdev: pci device.
499  */
500 static int pci_go_44(struct pci_dev *pdev)
501 {
502 	int rc;
503 
504 	if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(44))) {
505 		rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(44));
506 		if (rc) {
507 			rc = pci_set_consistent_dma_mask(pdev,
508 				DMA_BIT_MASK(32));
509 			if (rc) {
510 				dev_printk(KERN_ERR, &pdev->dev,
511 					"44-bit DMA enable failed\n");
512 				return rc;
513 			}
514 		}
515 	} else {
516 		rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
517 		if (rc) {
518 			dev_printk(KERN_ERR, &pdev->dev,
519 				"32-bit DMA enable failed\n");
520 			return rc;
521 		}
522 		rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
523 		if (rc) {
524 			dev_printk(KERN_ERR, &pdev->dev,
525 				"32-bit consistent DMA enable failed\n");
526 			return rc;
527 		}
528 	}
529 	return rc;
530 }
531 
532 /**
533  * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
534  * @shost: scsi host which has been allocated outside.
535  * @chip_info: our ha struct.
536  */
537 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
538 				   const struct pm8001_chip_info *chip_info)
539 {
540 	int phy_nr, port_nr;
541 	struct asd_sas_phy **arr_phy;
542 	struct asd_sas_port **arr_port;
543 	struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
544 
545 	phy_nr = chip_info->n_phy;
546 	port_nr = phy_nr;
547 	memset(sha, 0x00, sizeof(*sha));
548 	arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
549 	if (!arr_phy)
550 		goto exit;
551 	arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
552 	if (!arr_port)
553 		goto exit_free2;
554 
555 	sha->sas_phy = arr_phy;
556 	sha->sas_port = arr_port;
557 	sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
558 	if (!sha->lldd_ha)
559 		goto exit_free1;
560 
561 	shost->transportt = pm8001_stt;
562 	shost->max_id = PM8001_MAX_DEVICES;
563 	shost->max_lun = 8;
564 	shost->max_channel = 0;
565 	shost->unique_id = pm8001_id;
566 	shost->max_cmd_len = 16;
567 	shost->can_queue = PM8001_CAN_QUEUE;
568 	shost->cmd_per_lun = 32;
569 	return 0;
570 exit_free1:
571 	kfree(arr_port);
572 exit_free2:
573 	kfree(arr_phy);
574 exit:
575 	return -1;
576 }
577 
578 /**
579  * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
580  * @shost: scsi host which has been allocated outside
581  * @chip_info: our ha struct.
582  */
583 static void  pm8001_post_sas_ha_init(struct Scsi_Host *shost,
584 				     const struct pm8001_chip_info *chip_info)
585 {
586 	int i = 0;
587 	struct pm8001_hba_info *pm8001_ha;
588 	struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
589 
590 	pm8001_ha = sha->lldd_ha;
591 	for (i = 0; i < chip_info->n_phy; i++) {
592 		sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
593 		sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
594 	}
595 	sha->sas_ha_name = DRV_NAME;
596 	sha->dev = pm8001_ha->dev;
597 
598 	sha->lldd_module = THIS_MODULE;
599 	sha->sas_addr = &pm8001_ha->sas_addr[0];
600 	sha->num_phys = chip_info->n_phy;
601 	sha->lldd_max_execute_num = 1;
602 	sha->lldd_queue_size = PM8001_CAN_QUEUE;
603 	sha->core.shost = shost;
604 }
605 
606 /**
607  * pm8001_init_sas_add - initialize sas address
608  * @chip_info: our ha struct.
609  *
610  * Currently we just set the fixed SAS address to our HBA,for manufacture,
611  * it should read from the EEPROM
612  */
613 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
614 {
615 	u8 i, j;
616 #ifdef PM8001_READ_VPD
617 	/* For new SPC controllers WWN is stored in flash vpd
618 	*  For SPC/SPCve controllers WWN is stored in EEPROM
619 	*  For Older SPC WWN is stored in NVMD
620 	*/
621 	DECLARE_COMPLETION_ONSTACK(completion);
622 	struct pm8001_ioctl_payload payload;
623 	u16 deviceid;
624 	pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
625 	pm8001_ha->nvmd_completion = &completion;
626 
627 	if (pm8001_ha->chip_id == chip_8001) {
628 		if (deviceid == 0x8081 || deviceid == 0x0042) {
629 			payload.minor_function = 4;
630 			payload.length = 4096;
631 		} else {
632 			payload.minor_function = 0;
633 			payload.length = 128;
634 		}
635 	} else {
636 		payload.minor_function = 1;
637 		payload.length = 4096;
638 	}
639 	payload.offset = 0;
640 	payload.func_specific = kzalloc(payload.length, GFP_KERNEL);
641 	PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
642 	wait_for_completion(&completion);
643 
644 	for (i = 0, j = 0; i <= 7; i++, j++) {
645 		if (pm8001_ha->chip_id == chip_8001) {
646 			if (deviceid == 0x8081)
647 				pm8001_ha->sas_addr[j] =
648 					payload.func_specific[0x704 + i];
649 			else if (deviceid == 0x0042)
650 				pm8001_ha->sas_addr[j] =
651 					payload.func_specific[0x010 + i];
652 		} else
653 			pm8001_ha->sas_addr[j] =
654 					payload.func_specific[0x804 + i];
655 	}
656 
657 	for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
658 		memcpy(&pm8001_ha->phy[i].dev_sas_addr,
659 			pm8001_ha->sas_addr, SAS_ADDR_SIZE);
660 		PM8001_INIT_DBG(pm8001_ha,
661 			pm8001_printk("phy %d sas_addr = %016llx\n", i,
662 			pm8001_ha->phy[i].dev_sas_addr));
663 	}
664 #else
665 	for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
666 		pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
667 		pm8001_ha->phy[i].dev_sas_addr =
668 			cpu_to_be64((u64)
669 				(*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
670 	}
671 	memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
672 		SAS_ADDR_SIZE);
673 #endif
674 }
675 
676 /*
677  * pm8001_get_phy_settings_info : Read phy setting values.
678  * @pm8001_ha : our hba.
679  */
680 void pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
681 {
682 
683 #ifdef PM8001_READ_VPD
684 	/*OPTION ROM FLASH read for the SPC cards */
685 	DECLARE_COMPLETION_ONSTACK(completion);
686 	struct pm8001_ioctl_payload payload;
687 
688 	pm8001_ha->nvmd_completion = &completion;
689 	/* SAS ADDRESS read from flash / EEPROM */
690 	payload.minor_function = 6;
691 	payload.offset = 0;
692 	payload.length = 4096;
693 	payload.func_specific = kzalloc(4096, GFP_KERNEL);
694 	/* Read phy setting values from flash */
695 	PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
696 	wait_for_completion(&completion);
697 	pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
698 #endif
699 }
700 
701 #ifdef PM8001_USE_MSIX
702 /**
703  * pm8001_setup_msix - enable MSI-X interrupt
704  * @chip_info: our ha struct.
705  * @irq_handler: irq_handler
706  */
707 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
708 {
709 	u32 i = 0, j = 0;
710 	u32 number_of_intr;
711 	int flag = 0;
712 	u32 max_entry;
713 	int rc;
714 	static char intr_drvname[PM8001_MAX_MSIX_VEC][sizeof(DRV_NAME)+3];
715 
716 	/* SPCv controllers supports 64 msi-x */
717 	if (pm8001_ha->chip_id == chip_8001) {
718 		number_of_intr = 1;
719 	} else {
720 		number_of_intr = PM8001_MAX_MSIX_VEC;
721 		flag &= ~IRQF_SHARED;
722 	}
723 
724 	max_entry = sizeof(pm8001_ha->msix_entries) /
725 		sizeof(pm8001_ha->msix_entries[0]);
726 	for (i = 0; i < max_entry ; i++)
727 		pm8001_ha->msix_entries[i].entry = i;
728 	rc = pci_enable_msix(pm8001_ha->pdev, pm8001_ha->msix_entries,
729 		number_of_intr);
730 	pm8001_ha->number_of_intr = number_of_intr;
731 	if (!rc) {
732 		PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
733 			"pci_enable_msix request ret:%d no of intr %d\n",
734 					rc, pm8001_ha->number_of_intr));
735 
736 
737 		for (i = 0; i < number_of_intr; i++) {
738 			snprintf(intr_drvname[i], sizeof(intr_drvname[0]),
739 					DRV_NAME"%d", i);
740 			pm8001_ha->irq_vector[i].irq_id = i;
741 			pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
742 
743 			if (request_irq(pm8001_ha->msix_entries[i].vector,
744 				pm8001_interrupt_handler_msix, flag,
745 				intr_drvname[i], &(pm8001_ha->irq_vector[i]))) {
746 				for (j = 0; j < i; j++)
747 					free_irq(
748 					pm8001_ha->msix_entries[j].vector,
749 					&(pm8001_ha->irq_vector[i]));
750 				pci_disable_msix(pm8001_ha->pdev);
751 				break;
752 			}
753 		}
754 	}
755 	return rc;
756 }
757 #endif
758 
759 /**
760  * pm8001_request_irq - register interrupt
761  * @chip_info: our ha struct.
762  */
763 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
764 {
765 	struct pci_dev *pdev;
766 	int rc;
767 
768 	pdev = pm8001_ha->pdev;
769 
770 #ifdef PM8001_USE_MSIX
771 	if (pdev->msix_cap)
772 		return pm8001_setup_msix(pm8001_ha);
773 	else {
774 		PM8001_INIT_DBG(pm8001_ha,
775 			pm8001_printk("MSIX not supported!!!\n"));
776 		goto intx;
777 	}
778 #endif
779 
780 intx:
781 	/* initialize the INT-X interrupt */
782 	rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
783 		DRV_NAME, SHOST_TO_SAS_HA(pm8001_ha->shost));
784 	return rc;
785 }
786 
787 /**
788  * pm8001_pci_probe - probe supported device
789  * @pdev: pci device which kernel has been prepared for.
790  * @ent: pci device id
791  *
792  * This function is the main initialization function, when register a new
793  * pci driver it is invoked, all struct an hardware initilization should be done
794  * here, also, register interrupt
795  */
796 static int pm8001_pci_probe(struct pci_dev *pdev,
797 			    const struct pci_device_id *ent)
798 {
799 	unsigned int rc;
800 	u32	pci_reg;
801 	u8	i = 0;
802 	struct pm8001_hba_info *pm8001_ha;
803 	struct Scsi_Host *shost = NULL;
804 	const struct pm8001_chip_info *chip;
805 
806 	dev_printk(KERN_INFO, &pdev->dev,
807 		"pm80xx: driver version %s\n", DRV_VERSION);
808 	rc = pci_enable_device(pdev);
809 	if (rc)
810 		goto err_out_enable;
811 	pci_set_master(pdev);
812 	/*
813 	 * Enable pci slot busmaster by setting pci command register.
814 	 * This is required by FW for Cyclone card.
815 	 */
816 
817 	pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
818 	pci_reg |= 0x157;
819 	pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
820 	rc = pci_request_regions(pdev, DRV_NAME);
821 	if (rc)
822 		goto err_out_disable;
823 	rc = pci_go_44(pdev);
824 	if (rc)
825 		goto err_out_regions;
826 
827 	shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
828 	if (!shost) {
829 		rc = -ENOMEM;
830 		goto err_out_regions;
831 	}
832 	chip = &pm8001_chips[ent->driver_data];
833 	SHOST_TO_SAS_HA(shost) =
834 		kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
835 	if (!SHOST_TO_SAS_HA(shost)) {
836 		rc = -ENOMEM;
837 		goto err_out_free_host;
838 	}
839 
840 	rc = pm8001_prep_sas_ha_init(shost, chip);
841 	if (rc) {
842 		rc = -ENOMEM;
843 		goto err_out_free;
844 	}
845 	pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
846 	/* ent->driver variable is used to differentiate between controllers */
847 	pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
848 	if (!pm8001_ha) {
849 		rc = -ENOMEM;
850 		goto err_out_free;
851 	}
852 	list_add_tail(&pm8001_ha->list, &hba_list);
853 	PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
854 	rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
855 	if (rc) {
856 		PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
857 			"chip_init failed [ret: %d]\n", rc));
858 		goto err_out_ha_free;
859 	}
860 
861 	rc = scsi_add_host(shost, &pdev->dev);
862 	if (rc)
863 		goto err_out_ha_free;
864 	rc = pm8001_request_irq(pm8001_ha);
865 	if (rc)	{
866 		PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
867 			"pm8001_request_irq failed [ret: %d]\n", rc));
868 		goto err_out_shost;
869 	}
870 
871 	PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
872 	if (pm8001_ha->chip_id != chip_8001) {
873 		for (i = 1; i < pm8001_ha->number_of_intr; i++)
874 			PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
875 		/* setup thermal configuration. */
876 		pm80xx_set_thermal_config(pm8001_ha);
877 	}
878 
879 	pm8001_init_sas_add(pm8001_ha);
880 	/* phy setting support for motherboard controller */
881 	if (pdev->subsystem_vendor != PCI_VENDOR_ID_ADAPTEC2 &&
882 		pdev->subsystem_vendor != 0)
883 		pm8001_get_phy_settings_info(pm8001_ha);
884 	pm8001_post_sas_ha_init(shost, chip);
885 	rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
886 	if (rc)
887 		goto err_out_shost;
888 	scsi_scan_host(pm8001_ha->shost);
889 	return 0;
890 
891 err_out_shost:
892 	scsi_remove_host(pm8001_ha->shost);
893 err_out_ha_free:
894 	pm8001_free(pm8001_ha);
895 err_out_free:
896 	kfree(SHOST_TO_SAS_HA(shost));
897 err_out_free_host:
898 	kfree(shost);
899 err_out_regions:
900 	pci_release_regions(pdev);
901 err_out_disable:
902 	pci_disable_device(pdev);
903 err_out_enable:
904 	return rc;
905 }
906 
907 static void pm8001_pci_remove(struct pci_dev *pdev)
908 {
909 	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
910 	struct pm8001_hba_info *pm8001_ha;
911 	int i, j;
912 	pm8001_ha = sha->lldd_ha;
913 	sas_unregister_ha(sha);
914 	sas_remove_host(pm8001_ha->shost);
915 	list_del(&pm8001_ha->list);
916 	scsi_remove_host(pm8001_ha->shost);
917 	PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
918 	PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
919 
920 #ifdef PM8001_USE_MSIX
921 	for (i = 0; i < pm8001_ha->number_of_intr; i++)
922 		synchronize_irq(pm8001_ha->msix_entries[i].vector);
923 	for (i = 0; i < pm8001_ha->number_of_intr; i++)
924 		free_irq(pm8001_ha->msix_entries[i].vector,
925 				&(pm8001_ha->irq_vector[i]));
926 	pci_disable_msix(pdev);
927 #else
928 	free_irq(pm8001_ha->irq, sha);
929 #endif
930 #ifdef PM8001_USE_TASKLET
931 	/* For non-msix and msix interrupts */
932 	if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
933 		tasklet_kill(&pm8001_ha->tasklet[0]);
934 	else
935 		for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
936 			tasklet_kill(&pm8001_ha->tasklet[j]);
937 #endif
938 	pm8001_free(pm8001_ha);
939 	kfree(sha->sas_phy);
940 	kfree(sha->sas_port);
941 	kfree(sha);
942 	pci_release_regions(pdev);
943 	pci_disable_device(pdev);
944 }
945 
946 /**
947  * pm8001_pci_suspend - power management suspend main entry point
948  * @pdev: PCI device struct
949  * @state: PM state change to (usually PCI_D3)
950  *
951  * Returns 0 success, anything else error.
952  */
953 static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state)
954 {
955 	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
956 	struct pm8001_hba_info *pm8001_ha;
957 	int  i, j;
958 	u32 device_state;
959 	pm8001_ha = sha->lldd_ha;
960 	flush_workqueue(pm8001_wq);
961 	scsi_block_requests(pm8001_ha->shost);
962 	if (!pdev->pm_cap) {
963 		dev_err(&pdev->dev, " PCI PM not supported\n");
964 		return -ENODEV;
965 	}
966 	PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
967 	PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
968 #ifdef PM8001_USE_MSIX
969 	for (i = 0; i < pm8001_ha->number_of_intr; i++)
970 		synchronize_irq(pm8001_ha->msix_entries[i].vector);
971 	for (i = 0; i < pm8001_ha->number_of_intr; i++)
972 		free_irq(pm8001_ha->msix_entries[i].vector,
973 				&(pm8001_ha->irq_vector[i]));
974 	pci_disable_msix(pdev);
975 #else
976 	free_irq(pm8001_ha->irq, sha);
977 #endif
978 #ifdef PM8001_USE_TASKLET
979 	/* For non-msix and msix interrupts */
980 	if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
981 		tasklet_kill(&pm8001_ha->tasklet[0]);
982 	else
983 		for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
984 			tasklet_kill(&pm8001_ha->tasklet[j]);
985 #endif
986 	device_state = pci_choose_state(pdev, state);
987 	pm8001_printk("pdev=0x%p, slot=%s, entering "
988 		      "operating state [D%d]\n", pdev,
989 		      pm8001_ha->name, device_state);
990 	pci_save_state(pdev);
991 	pci_disable_device(pdev);
992 	pci_set_power_state(pdev, device_state);
993 	return 0;
994 }
995 
996 /**
997  * pm8001_pci_resume - power management resume main entry point
998  * @pdev: PCI device struct
999  *
1000  * Returns 0 success, anything else error.
1001  */
1002 static int pm8001_pci_resume(struct pci_dev *pdev)
1003 {
1004 	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1005 	struct pm8001_hba_info *pm8001_ha;
1006 	int rc;
1007 	u8 i = 0, j;
1008 	u32 device_state;
1009 	pm8001_ha = sha->lldd_ha;
1010 	device_state = pdev->current_state;
1011 
1012 	pm8001_printk("pdev=0x%p, slot=%s, resuming from previous "
1013 		"operating state [D%d]\n", pdev, pm8001_ha->name, device_state);
1014 
1015 	pci_set_power_state(pdev, PCI_D0);
1016 	pci_enable_wake(pdev, PCI_D0, 0);
1017 	pci_restore_state(pdev);
1018 	rc = pci_enable_device(pdev);
1019 	if (rc) {
1020 		pm8001_printk("slot=%s Enable device failed during resume\n",
1021 			      pm8001_ha->name);
1022 		goto err_out_enable;
1023 	}
1024 
1025 	pci_set_master(pdev);
1026 	rc = pci_go_44(pdev);
1027 	if (rc)
1028 		goto err_out_disable;
1029 
1030 	/* chip soft rst only for spc */
1031 	if (pm8001_ha->chip_id == chip_8001) {
1032 		PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1033 		PM8001_INIT_DBG(pm8001_ha,
1034 			pm8001_printk("chip soft reset successful\n"));
1035 	}
1036 	rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1037 	if (rc)
1038 		goto err_out_disable;
1039 
1040 	/* disable all the interrupt bits */
1041 	PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1042 
1043 	rc = pm8001_request_irq(pm8001_ha);
1044 	if (rc)
1045 		goto err_out_disable;
1046 #ifdef PM8001_USE_TASKLET
1047 	/*  Tasklet for non msi-x interrupt handler */
1048 	if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
1049 		tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1050 			(unsigned long)&(pm8001_ha->irq_vector[0]));
1051 	else
1052 		for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1053 			tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1054 				(unsigned long)&(pm8001_ha->irq_vector[j]));
1055 #endif
1056 	PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1057 	if (pm8001_ha->chip_id != chip_8001) {
1058 		for (i = 1; i < pm8001_ha->number_of_intr; i++)
1059 			PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1060 	}
1061 	scsi_unblock_requests(pm8001_ha->shost);
1062 	return 0;
1063 
1064 err_out_disable:
1065 	scsi_remove_host(pm8001_ha->shost);
1066 	pci_disable_device(pdev);
1067 err_out_enable:
1068 	return rc;
1069 }
1070 
1071 /* update of pci device, vendor id and driver data with
1072  * unique value for each of the controller
1073  */
1074 static struct pci_device_id pm8001_pci_table[] = {
1075 	{ PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1076 	{ PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1077 	/* Support for SPC/SPCv/SPCve controllers */
1078 	{ PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1079 	{ PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1080 	{ PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1081 	{ PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1082 	{ PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1083 	{ PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1084 	{ PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1085 	{ PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1086 	{ PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1087 	{ PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1088 	{ PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1089 	{ PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1090 	{ PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1091 	{ PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1092 	{ PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1093 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1094 		PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1095 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1096 		PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1097 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1098 		PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1099 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1100 		PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1101 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1102 		PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1103 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1104 		PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1105 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1106 		PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1107 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1108 		PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1109 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1110 		PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1111 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1112 		PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1113 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1114 		PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1115 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1116 		PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1117 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1118 		PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1119 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1120 		PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1121 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1122 		PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1123 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1124 		PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1125 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1126 		PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1127 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1128 		PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1129 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1130 		PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1131 	{} /* terminate list */
1132 };
1133 
1134 static struct pci_driver pm8001_pci_driver = {
1135 	.name		= DRV_NAME,
1136 	.id_table	= pm8001_pci_table,
1137 	.probe		= pm8001_pci_probe,
1138 	.remove		= pm8001_pci_remove,
1139 	.suspend	= pm8001_pci_suspend,
1140 	.resume		= pm8001_pci_resume,
1141 };
1142 
1143 /**
1144  *	pm8001_init - initialize scsi transport template
1145  */
1146 static int __init pm8001_init(void)
1147 {
1148 	int rc = -ENOMEM;
1149 
1150 	pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1151 	if (!pm8001_wq)
1152 		goto err;
1153 
1154 	pm8001_id = 0;
1155 	pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1156 	if (!pm8001_stt)
1157 		goto err_wq;
1158 	rc = pci_register_driver(&pm8001_pci_driver);
1159 	if (rc)
1160 		goto err_tp;
1161 	return 0;
1162 
1163 err_tp:
1164 	sas_release_transport(pm8001_stt);
1165 err_wq:
1166 	destroy_workqueue(pm8001_wq);
1167 err:
1168 	return rc;
1169 }
1170 
1171 static void __exit pm8001_exit(void)
1172 {
1173 	pci_unregister_driver(&pm8001_pci_driver);
1174 	sas_release_transport(pm8001_stt);
1175 	destroy_workqueue(pm8001_wq);
1176 }
1177 
1178 module_init(pm8001_init);
1179 module_exit(pm8001_exit);
1180 
1181 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1182 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1183 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1184 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1185 MODULE_DESCRIPTION(
1186 		"PMC-Sierra PM8001/8081/8088/8089/8074/8076/8077 "
1187 		"SAS/SATA controller driver");
1188 MODULE_VERSION(DRV_VERSION);
1189 MODULE_LICENSE("GPL");
1190 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1191 
1192