1 /*
2  * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
3  *
4  * Copyright (c) 2008-2009 USI Co., Ltd.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions, and the following disclaimer,
12  *    without modification.
13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14  *    substantially similar to the "NO WARRANTY" disclaimer below
15  *    ("Disclaimer") and any redistribution must be conditioned upon
16  *    including a substantially similar Disclaimer requirement for further
17  *    binary redistribution.
18  * 3. Neither the names of the above-listed copyright holders nor the names
19  *    of any contributors may be used to endorse or promote products derived
20  *    from this software without specific prior written permission.
21  *
22  * Alternatively, this software may be distributed under the terms of the
23  * GNU General Public License ("GPL") version 2 as published by the Free
24  * Software Foundation.
25  *
26  * NO WARRANTY
27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37  * POSSIBILITY OF SUCH DAMAGES.
38  *
39  */
40 
41 #include <linux/slab.h>
42 #include "pm8001_sas.h"
43 #include "pm8001_chips.h"
44 #include "pm80xx_hwi.h"
45 
46 static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING;
47 module_param(logging_level, ulong, 0644);
48 MODULE_PARM_DESC(logging_level, " bits for enabling logging info.");
49 
50 static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120;
51 module_param(link_rate, ulong, 0644);
52 MODULE_PARM_DESC(link_rate, "Enable link rate.\n"
53 		" 1: Link rate 1.5G\n"
54 		" 2: Link rate 3.0G\n"
55 		" 4: Link rate 6.0G\n"
56 		" 8: Link rate 12.0G\n");
57 
58 static struct scsi_transport_template *pm8001_stt;
59 static int pm8001_init_ccb_tag(struct pm8001_hba_info *);
60 
61 /*
62  * chip info structure to identify chip key functionality as
63  * encryption available/not, no of ports, hw specific function ref
64  */
65 static const struct pm8001_chip_info pm8001_chips[] = {
66 	[chip_8001] = {0,  8, &pm8001_8001_dispatch,},
67 	[chip_8008] = {0,  8, &pm8001_80xx_dispatch,},
68 	[chip_8009] = {1,  8, &pm8001_80xx_dispatch,},
69 	[chip_8018] = {0,  16, &pm8001_80xx_dispatch,},
70 	[chip_8019] = {1,  16, &pm8001_80xx_dispatch,},
71 	[chip_8074] = {0,  8, &pm8001_80xx_dispatch,},
72 	[chip_8076] = {0,  16, &pm8001_80xx_dispatch,},
73 	[chip_8077] = {0,  16, &pm8001_80xx_dispatch,},
74 	[chip_8006] = {0,  16, &pm8001_80xx_dispatch,},
75 	[chip_8070] = {0,  8, &pm8001_80xx_dispatch,},
76 	[chip_8072] = {0,  16, &pm8001_80xx_dispatch,},
77 };
78 static int pm8001_id;
79 
80 LIST_HEAD(hba_list);
81 
82 struct workqueue_struct *pm8001_wq;
83 
84 static void pm8001_map_queues(struct Scsi_Host *shost)
85 {
86 	struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
87 	struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
88 	struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
89 
90 	if (pm8001_ha->number_of_intr > 1)
91 		blk_mq_pci_map_queues(qmap, pm8001_ha->pdev, 1);
92 
93 	return blk_mq_map_queues(qmap);
94 }
95 
96 /*
97  * The main structure which LLDD must register for scsi core.
98  */
99 static const struct scsi_host_template pm8001_sht = {
100 	.module			= THIS_MODULE,
101 	.name			= DRV_NAME,
102 	.proc_name		= DRV_NAME,
103 	.queuecommand		= sas_queuecommand,
104 	.dma_need_drain		= ata_scsi_dma_need_drain,
105 	.target_alloc		= sas_target_alloc,
106 	.slave_configure	= sas_slave_configure,
107 	.scan_finished		= pm8001_scan_finished,
108 	.scan_start		= pm8001_scan_start,
109 	.change_queue_depth	= sas_change_queue_depth,
110 	.bios_param		= sas_bios_param,
111 	.can_queue		= 1,
112 	.this_id		= -1,
113 	.sg_tablesize		= PM8001_MAX_DMA_SG,
114 	.max_sectors		= SCSI_DEFAULT_MAX_SECTORS,
115 	.eh_device_reset_handler = sas_eh_device_reset_handler,
116 	.eh_target_reset_handler = sas_eh_target_reset_handler,
117 	.slave_alloc		= sas_slave_alloc,
118 	.target_destroy		= sas_target_destroy,
119 	.ioctl			= sas_ioctl,
120 #ifdef CONFIG_COMPAT
121 	.compat_ioctl		= sas_ioctl,
122 #endif
123 	.shost_groups		= pm8001_host_groups,
124 	.track_queue_depth	= 1,
125 	.cmd_per_lun		= 32,
126 	.map_queues		= pm8001_map_queues,
127 };
128 
129 /*
130  * Sas layer call this function to execute specific task.
131  */
132 static struct sas_domain_function_template pm8001_transport_ops = {
133 	.lldd_dev_found		= pm8001_dev_found,
134 	.lldd_dev_gone		= pm8001_dev_gone,
135 
136 	.lldd_execute_task	= pm8001_queue_command,
137 	.lldd_control_phy	= pm8001_phy_control,
138 
139 	.lldd_abort_task	= pm8001_abort_task,
140 	.lldd_abort_task_set	= sas_abort_task_set,
141 	.lldd_clear_task_set	= pm8001_clear_task_set,
142 	.lldd_I_T_nexus_reset   = pm8001_I_T_nexus_reset,
143 	.lldd_lu_reset		= pm8001_lu_reset,
144 	.lldd_query_task	= pm8001_query_task,
145 	.lldd_port_formed	= pm8001_port_formed,
146 	.lldd_tmf_exec_complete = pm8001_setds_completion,
147 	.lldd_tmf_aborted	= pm8001_tmf_aborted,
148 };
149 
150 /**
151  * pm8001_phy_init - initiate our adapter phys
152  * @pm8001_ha: our hba structure.
153  * @phy_id: phy id.
154  */
155 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
156 {
157 	struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
158 	struct asd_sas_phy *sas_phy = &phy->sas_phy;
159 	phy->phy_state = PHY_LINK_DISABLE;
160 	phy->pm8001_ha = pm8001_ha;
161 	phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
162 	phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
163 	sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
164 	sas_phy->class = SAS;
165 	sas_phy->iproto = SAS_PROTOCOL_ALL;
166 	sas_phy->tproto = 0;
167 	sas_phy->type = PHY_TYPE_PHYSICAL;
168 	sas_phy->role = PHY_ROLE_INITIATOR;
169 	sas_phy->oob_mode = OOB_NOT_CONNECTED;
170 	sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
171 	sas_phy->id = phy_id;
172 	sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr;
173 	sas_phy->frame_rcvd = &phy->frame_rcvd[0];
174 	sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
175 	sas_phy->lldd_phy = phy;
176 }
177 
178 /**
179  * pm8001_free - free hba
180  * @pm8001_ha:	our hba structure.
181  */
182 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
183 {
184 	int i;
185 
186 	if (!pm8001_ha)
187 		return;
188 
189 	for (i = 0; i < USI_MAX_MEMCNT; i++) {
190 		if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
191 			dma_free_coherent(&pm8001_ha->pdev->dev,
192 				(pm8001_ha->memoryMap.region[i].total_len +
193 				pm8001_ha->memoryMap.region[i].alignment),
194 				pm8001_ha->memoryMap.region[i].virt_ptr,
195 				pm8001_ha->memoryMap.region[i].phys_addr);
196 			}
197 	}
198 	PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
199 	flush_workqueue(pm8001_wq);
200 	bitmap_free(pm8001_ha->rsvd_tags);
201 	kfree(pm8001_ha);
202 }
203 
204 #ifdef PM8001_USE_TASKLET
205 
206 /**
207  * pm8001_tasklet() - tasklet for 64 msi-x interrupt handler
208  * @opaque: the passed general host adapter struct
209  * Note: pm8001_tasklet is common for pm8001 & pm80xx
210  */
211 static void pm8001_tasklet(unsigned long opaque)
212 {
213 	struct pm8001_hba_info *pm8001_ha;
214 	struct isr_param *irq_vector;
215 
216 	irq_vector = (struct isr_param *)opaque;
217 	pm8001_ha = irq_vector->drv_inst;
218 	if (unlikely(!pm8001_ha))
219 		BUG_ON(1);
220 	PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
221 }
222 #endif
223 
224 /**
225  * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
226  * It obtains the vector number and calls the equivalent bottom
227  * half or services directly.
228  * @irq: interrupt number
229  * @opaque: the passed outbound queue/vector. Host structure is
230  * retrieved from the same.
231  */
232 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
233 {
234 	struct isr_param *irq_vector;
235 	struct pm8001_hba_info *pm8001_ha;
236 	irqreturn_t ret = IRQ_HANDLED;
237 	irq_vector = (struct isr_param *)opaque;
238 	pm8001_ha = irq_vector->drv_inst;
239 
240 	if (unlikely(!pm8001_ha))
241 		return IRQ_NONE;
242 	if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
243 		return IRQ_NONE;
244 #ifdef PM8001_USE_TASKLET
245 	tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
246 #else
247 	ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
248 #endif
249 	return ret;
250 }
251 
252 /**
253  * pm8001_interrupt_handler_intx - main INTx interrupt handler.
254  * @irq: interrupt number
255  * @dev_id: sas_ha structure. The HBA is retrieved from sas_ha structure.
256  */
257 
258 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
259 {
260 	struct pm8001_hba_info *pm8001_ha;
261 	irqreturn_t ret = IRQ_HANDLED;
262 	struct sas_ha_struct *sha = dev_id;
263 	pm8001_ha = sha->lldd_ha;
264 	if (unlikely(!pm8001_ha))
265 		return IRQ_NONE;
266 	if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
267 		return IRQ_NONE;
268 
269 #ifdef PM8001_USE_TASKLET
270 	tasklet_schedule(&pm8001_ha->tasklet[0]);
271 #else
272 	ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
273 #endif
274 	return ret;
275 }
276 
277 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha);
278 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha);
279 
280 /**
281  * pm8001_alloc - initiate our hba structure and 6 DMAs area.
282  * @pm8001_ha: our hba structure.
283  * @ent: PCI device ID structure to match on
284  */
285 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
286 			const struct pci_device_id *ent)
287 {
288 	int i, count = 0, rc = 0;
289 	u32 ci_offset, ib_offset, ob_offset, pi_offset;
290 	struct inbound_queue_table *ibq;
291 	struct outbound_queue_table *obq;
292 
293 	spin_lock_init(&pm8001_ha->lock);
294 	spin_lock_init(&pm8001_ha->bitmap_lock);
295 	pm8001_dbg(pm8001_ha, INIT, "pm8001_alloc: PHY:%x\n",
296 		   pm8001_ha->chip->n_phy);
297 
298 	/* Setup Interrupt */
299 	rc = pm8001_setup_irq(pm8001_ha);
300 	if (rc) {
301 		pm8001_dbg(pm8001_ha, FAIL,
302 			   "pm8001_setup_irq failed [ret: %d]\n", rc);
303 		goto err_out;
304 	}
305 	/* Request Interrupt */
306 	rc = pm8001_request_irq(pm8001_ha);
307 	if (rc)
308 		goto err_out;
309 
310 	count = pm8001_ha->max_q_num;
311 	/* Queues are chosen based on the number of cores/msix availability */
312 	ib_offset = pm8001_ha->ib_offset  = USI_MAX_MEMCNT_BASE;
313 	ci_offset = pm8001_ha->ci_offset  = ib_offset + count;
314 	ob_offset = pm8001_ha->ob_offset  = ci_offset + count;
315 	pi_offset = pm8001_ha->pi_offset  = ob_offset + count;
316 	pm8001_ha->max_memcnt = pi_offset + count;
317 
318 	for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
319 		pm8001_phy_init(pm8001_ha, i);
320 		pm8001_ha->port[i].wide_port_phymap = 0;
321 		pm8001_ha->port[i].port_attached = 0;
322 		pm8001_ha->port[i].port_state = 0;
323 		INIT_LIST_HEAD(&pm8001_ha->port[i].list);
324 	}
325 
326 	/* MPI Memory region 1 for AAP Event Log for fw */
327 	pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
328 	pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
329 	pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
330 	pm8001_ha->memoryMap.region[AAP1].alignment = 32;
331 
332 	/* MPI Memory region 2 for IOP Event Log for fw */
333 	pm8001_ha->memoryMap.region[IOP].num_elements = 1;
334 	pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
335 	pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
336 	pm8001_ha->memoryMap.region[IOP].alignment = 32;
337 
338 	for (i = 0; i < count; i++) {
339 		ibq = &pm8001_ha->inbnd_q_tbl[i];
340 		spin_lock_init(&ibq->iq_lock);
341 		/* MPI Memory region 3 for consumer Index of inbound queues */
342 		pm8001_ha->memoryMap.region[ci_offset+i].num_elements = 1;
343 		pm8001_ha->memoryMap.region[ci_offset+i].element_size = 4;
344 		pm8001_ha->memoryMap.region[ci_offset+i].total_len = 4;
345 		pm8001_ha->memoryMap.region[ci_offset+i].alignment = 4;
346 
347 		if ((ent->driver_data) != chip_8001) {
348 			/* MPI Memory region 5 inbound queues */
349 			pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
350 						PM8001_MPI_QUEUE;
351 			pm8001_ha->memoryMap.region[ib_offset+i].element_size
352 								= 128;
353 			pm8001_ha->memoryMap.region[ib_offset+i].total_len =
354 						PM8001_MPI_QUEUE * 128;
355 			pm8001_ha->memoryMap.region[ib_offset+i].alignment
356 								= 128;
357 		} else {
358 			pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
359 						PM8001_MPI_QUEUE;
360 			pm8001_ha->memoryMap.region[ib_offset+i].element_size
361 								= 64;
362 			pm8001_ha->memoryMap.region[ib_offset+i].total_len =
363 						PM8001_MPI_QUEUE * 64;
364 			pm8001_ha->memoryMap.region[ib_offset+i].alignment = 64;
365 		}
366 	}
367 
368 	for (i = 0; i < count; i++) {
369 		obq = &pm8001_ha->outbnd_q_tbl[i];
370 		spin_lock_init(&obq->oq_lock);
371 		/* MPI Memory region 4 for producer Index of outbound queues */
372 		pm8001_ha->memoryMap.region[pi_offset+i].num_elements = 1;
373 		pm8001_ha->memoryMap.region[pi_offset+i].element_size = 4;
374 		pm8001_ha->memoryMap.region[pi_offset+i].total_len = 4;
375 		pm8001_ha->memoryMap.region[pi_offset+i].alignment = 4;
376 
377 		if (ent->driver_data != chip_8001) {
378 			/* MPI Memory region 6 Outbound queues */
379 			pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
380 						PM8001_MPI_QUEUE;
381 			pm8001_ha->memoryMap.region[ob_offset+i].element_size
382 								= 128;
383 			pm8001_ha->memoryMap.region[ob_offset+i].total_len =
384 						PM8001_MPI_QUEUE * 128;
385 			pm8001_ha->memoryMap.region[ob_offset+i].alignment
386 								= 128;
387 		} else {
388 			/* MPI Memory region 6 Outbound queues */
389 			pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
390 						PM8001_MPI_QUEUE;
391 			pm8001_ha->memoryMap.region[ob_offset+i].element_size
392 								= 64;
393 			pm8001_ha->memoryMap.region[ob_offset+i].total_len =
394 						PM8001_MPI_QUEUE * 64;
395 			pm8001_ha->memoryMap.region[ob_offset+i].alignment = 64;
396 		}
397 
398 	}
399 	/* Memory region write DMA*/
400 	pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
401 	pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
402 	pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
403 
404 	/* Memory region for fw flash */
405 	pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
406 
407 	pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
408 	pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
409 	pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
410 	pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
411 	for (i = 0; i < pm8001_ha->max_memcnt; i++) {
412 		struct mpi_mem *region = &pm8001_ha->memoryMap.region[i];
413 
414 		if (pm8001_mem_alloc(pm8001_ha->pdev,
415 				     &region->virt_ptr,
416 				     &region->phys_addr,
417 				     &region->phys_addr_hi,
418 				     &region->phys_addr_lo,
419 				     region->total_len,
420 				     region->alignment) != 0) {
421 			pm8001_dbg(pm8001_ha, FAIL, "Mem%d alloc failed\n", i);
422 			goto err_out;
423 		}
424 	}
425 
426 	/* Memory region for devices*/
427 	pm8001_ha->devices = kzalloc(PM8001_MAX_DEVICES
428 				* sizeof(struct pm8001_device), GFP_KERNEL);
429 	if (!pm8001_ha->devices) {
430 		rc = -ENOMEM;
431 		goto err_out_nodev;
432 	}
433 	for (i = 0; i < PM8001_MAX_DEVICES; i++) {
434 		pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
435 		pm8001_ha->devices[i].id = i;
436 		pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
437 		atomic_set(&pm8001_ha->devices[i].running_req, 0);
438 	}
439 	pm8001_ha->flags = PM8001F_INIT_TIME;
440 	return 0;
441 
442 err_out_nodev:
443 	for (i = 0; i < pm8001_ha->max_memcnt; i++) {
444 		if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
445 			dma_free_coherent(&pm8001_ha->pdev->dev,
446 				(pm8001_ha->memoryMap.region[i].total_len +
447 				pm8001_ha->memoryMap.region[i].alignment),
448 				pm8001_ha->memoryMap.region[i].virt_ptr,
449 				pm8001_ha->memoryMap.region[i].phys_addr);
450 		}
451 	}
452 err_out:
453 	return 1;
454 }
455 
456 /**
457  * pm8001_ioremap - remap the pci high physical address to kernel virtual
458  * address so that we can access them.
459  * @pm8001_ha: our hba structure.
460  */
461 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
462 {
463 	u32 bar;
464 	u32 logicalBar = 0;
465 	struct pci_dev *pdev;
466 
467 	pdev = pm8001_ha->pdev;
468 	/* map pci mem (PMC pci base 0-3)*/
469 	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
470 		/*
471 		** logical BARs for SPC:
472 		** bar 0 and 1 - logical BAR0
473 		** bar 2 and 3 - logical BAR1
474 		** bar4 - logical BAR2
475 		** bar5 - logical BAR3
476 		** Skip the appropriate assignments:
477 		*/
478 		if ((bar == 1) || (bar == 3))
479 			continue;
480 		if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
481 			pm8001_ha->io_mem[logicalBar].membase =
482 				pci_resource_start(pdev, bar);
483 			pm8001_ha->io_mem[logicalBar].memsize =
484 				pci_resource_len(pdev, bar);
485 			pm8001_ha->io_mem[logicalBar].memvirtaddr =
486 				ioremap(pm8001_ha->io_mem[logicalBar].membase,
487 				pm8001_ha->io_mem[logicalBar].memsize);
488 			if (!pm8001_ha->io_mem[logicalBar].memvirtaddr) {
489 				pm8001_dbg(pm8001_ha, INIT,
490 					"Failed to ioremap bar %d, logicalBar %d",
491 				   bar, logicalBar);
492 				return -ENOMEM;
493 			}
494 			pm8001_dbg(pm8001_ha, INIT,
495 				   "base addr %llx virt_addr=%llx len=%d\n",
496 				   (u64)pm8001_ha->io_mem[logicalBar].membase,
497 				   (u64)(unsigned long)
498 				   pm8001_ha->io_mem[logicalBar].memvirtaddr,
499 				   pm8001_ha->io_mem[logicalBar].memsize);
500 		} else {
501 			pm8001_ha->io_mem[logicalBar].membase	= 0;
502 			pm8001_ha->io_mem[logicalBar].memsize	= 0;
503 			pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL;
504 		}
505 		logicalBar++;
506 	}
507 	return 0;
508 }
509 
510 /**
511  * pm8001_pci_alloc - initialize our ha card structure
512  * @pdev: pci device.
513  * @ent: ent
514  * @shost: scsi host struct which has been initialized before.
515  */
516 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
517 				 const struct pci_device_id *ent,
518 				struct Scsi_Host *shost)
519 
520 {
521 	struct pm8001_hba_info *pm8001_ha;
522 	struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
523 	int j;
524 
525 	pm8001_ha = sha->lldd_ha;
526 	if (!pm8001_ha)
527 		return NULL;
528 
529 	pm8001_ha->pdev = pdev;
530 	pm8001_ha->dev = &pdev->dev;
531 	pm8001_ha->chip_id = ent->driver_data;
532 	pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
533 	pm8001_ha->irq = pdev->irq;
534 	pm8001_ha->sas = sha;
535 	pm8001_ha->shost = shost;
536 	pm8001_ha->id = pm8001_id++;
537 	pm8001_ha->logging_level = logging_level;
538 	pm8001_ha->non_fatal_count = 0;
539 	if (link_rate >= 1 && link_rate <= 15)
540 		pm8001_ha->link_rate = (link_rate << 8);
541 	else {
542 		pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 |
543 			LINKRATE_60 | LINKRATE_120;
544 		pm8001_dbg(pm8001_ha, FAIL,
545 			   "Setting link rate to default value\n");
546 	}
547 	sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
548 	/* IOMB size is 128 for 8088/89 controllers */
549 	if (pm8001_ha->chip_id != chip_8001)
550 		pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
551 	else
552 		pm8001_ha->iomb_size = IOMB_SIZE_SPC;
553 
554 #ifdef PM8001_USE_TASKLET
555 	/* Tasklet for non msi-x interrupt handler */
556 	if ((!pdev->msix_cap || !pci_msi_enabled())
557 	    || (pm8001_ha->chip_id == chip_8001))
558 		tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
559 			(unsigned long)&(pm8001_ha->irq_vector[0]));
560 	else
561 		for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
562 			tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
563 				(unsigned long)&(pm8001_ha->irq_vector[j]));
564 #endif
565 	if (pm8001_ioremap(pm8001_ha))
566 		goto failed_pci_alloc;
567 	if (!pm8001_alloc(pm8001_ha, ent))
568 		return pm8001_ha;
569 failed_pci_alloc:
570 	pm8001_free(pm8001_ha);
571 	return NULL;
572 }
573 
574 /**
575  * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
576  * @pdev: pci device.
577  */
578 static int pci_go_44(struct pci_dev *pdev)
579 {
580 	int rc;
581 
582 	rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
583 	if (rc) {
584 		rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
585 		if (rc)
586 			dev_printk(KERN_ERR, &pdev->dev,
587 				"32-bit DMA enable failed\n");
588 	}
589 	return rc;
590 }
591 
592 /**
593  * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
594  * @shost: scsi host which has been allocated outside.
595  * @chip_info: our ha struct.
596  */
597 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
598 				   const struct pm8001_chip_info *chip_info)
599 {
600 	int phy_nr, port_nr;
601 	struct asd_sas_phy **arr_phy;
602 	struct asd_sas_port **arr_port;
603 	struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
604 
605 	phy_nr = chip_info->n_phy;
606 	port_nr = phy_nr;
607 	memset(sha, 0x00, sizeof(*sha));
608 	arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
609 	if (!arr_phy)
610 		goto exit;
611 	arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
612 	if (!arr_port)
613 		goto exit_free2;
614 
615 	sha->sas_phy = arr_phy;
616 	sha->sas_port = arr_port;
617 	sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
618 	if (!sha->lldd_ha)
619 		goto exit_free1;
620 
621 	shost->transportt = pm8001_stt;
622 	shost->max_id = PM8001_MAX_DEVICES;
623 	shost->unique_id = pm8001_id;
624 	shost->max_cmd_len = 16;
625 	return 0;
626 exit_free1:
627 	kfree(arr_port);
628 exit_free2:
629 	kfree(arr_phy);
630 exit:
631 	return -1;
632 }
633 
634 /**
635  * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
636  * @shost: scsi host which has been allocated outside
637  * @chip_info: our ha struct.
638  */
639 static void  pm8001_post_sas_ha_init(struct Scsi_Host *shost,
640 				     const struct pm8001_chip_info *chip_info)
641 {
642 	int i = 0;
643 	struct pm8001_hba_info *pm8001_ha;
644 	struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
645 
646 	pm8001_ha = sha->lldd_ha;
647 	for (i = 0; i < chip_info->n_phy; i++) {
648 		sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
649 		sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
650 		sha->sas_phy[i]->sas_addr =
651 			(u8 *)&pm8001_ha->phy[i].dev_sas_addr;
652 	}
653 	sha->sas_ha_name = DRV_NAME;
654 	sha->dev = pm8001_ha->dev;
655 	sha->strict_wide_ports = 1;
656 	sha->lldd_module = THIS_MODULE;
657 	sha->sas_addr = &pm8001_ha->sas_addr[0];
658 	sha->num_phys = chip_info->n_phy;
659 	sha->core.shost = shost;
660 }
661 
662 /**
663  * pm8001_init_sas_add - initialize sas address
664  * @pm8001_ha: our ha struct.
665  *
666  * Currently we just set the fixed SAS address to our HBA, for manufacture,
667  * it should read from the EEPROM
668  */
669 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
670 {
671 	u8 i, j;
672 	u8 sas_add[8];
673 #ifdef PM8001_READ_VPD
674 	/* For new SPC controllers WWN is stored in flash vpd
675 	*  For SPC/SPCve controllers WWN is stored in EEPROM
676 	*  For Older SPC WWN is stored in NVMD
677 	*/
678 	DECLARE_COMPLETION_ONSTACK(completion);
679 	struct pm8001_ioctl_payload payload;
680 	u16 deviceid;
681 	int rc;
682 
683 	pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
684 	pm8001_ha->nvmd_completion = &completion;
685 
686 	if (pm8001_ha->chip_id == chip_8001) {
687 		if (deviceid == 0x8081 || deviceid == 0x0042) {
688 			payload.minor_function = 4;
689 			payload.rd_length = 4096;
690 		} else {
691 			payload.minor_function = 0;
692 			payload.rd_length = 128;
693 		}
694 	} else if ((pm8001_ha->chip_id == chip_8070 ||
695 			pm8001_ha->chip_id == chip_8072) &&
696 			pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
697 		payload.minor_function = 4;
698 		payload.rd_length = 4096;
699 	} else {
700 		payload.minor_function = 1;
701 		payload.rd_length = 4096;
702 	}
703 	payload.offset = 0;
704 	payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL);
705 	if (!payload.func_specific) {
706 		pm8001_dbg(pm8001_ha, INIT, "mem alloc fail\n");
707 		return;
708 	}
709 	rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
710 	if (rc) {
711 		kfree(payload.func_specific);
712 		pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
713 		return;
714 	}
715 	wait_for_completion(&completion);
716 
717 	for (i = 0, j = 0; i <= 7; i++, j++) {
718 		if (pm8001_ha->chip_id == chip_8001) {
719 			if (deviceid == 0x8081)
720 				pm8001_ha->sas_addr[j] =
721 					payload.func_specific[0x704 + i];
722 			else if (deviceid == 0x0042)
723 				pm8001_ha->sas_addr[j] =
724 					payload.func_specific[0x010 + i];
725 		} else if ((pm8001_ha->chip_id == chip_8070 ||
726 				pm8001_ha->chip_id == chip_8072) &&
727 				pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
728 			pm8001_ha->sas_addr[j] =
729 					payload.func_specific[0x010 + i];
730 		} else
731 			pm8001_ha->sas_addr[j] =
732 					payload.func_specific[0x804 + i];
733 	}
734 	memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE);
735 	for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
736 		if (i && ((i % 4) == 0))
737 			sas_add[7] = sas_add[7] + 4;
738 		memcpy(&pm8001_ha->phy[i].dev_sas_addr,
739 			sas_add, SAS_ADDR_SIZE);
740 		pm8001_dbg(pm8001_ha, INIT, "phy %d sas_addr = %016llx\n", i,
741 			   pm8001_ha->phy[i].dev_sas_addr);
742 	}
743 	kfree(payload.func_specific);
744 #else
745 	for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
746 		pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
747 		pm8001_ha->phy[i].dev_sas_addr =
748 			cpu_to_be64((u64)
749 				(*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
750 	}
751 	memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
752 		SAS_ADDR_SIZE);
753 #endif
754 }
755 
756 /*
757  * pm8001_get_phy_settings_info : Read phy setting values.
758  * @pm8001_ha : our hba.
759  */
760 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
761 {
762 
763 #ifdef PM8001_READ_VPD
764 	/*OPTION ROM FLASH read for the SPC cards */
765 	DECLARE_COMPLETION_ONSTACK(completion);
766 	struct pm8001_ioctl_payload payload;
767 	int rc;
768 
769 	pm8001_ha->nvmd_completion = &completion;
770 	/* SAS ADDRESS read from flash / EEPROM */
771 	payload.minor_function = 6;
772 	payload.offset = 0;
773 	payload.rd_length = 4096;
774 	payload.func_specific = kzalloc(4096, GFP_KERNEL);
775 	if (!payload.func_specific)
776 		return -ENOMEM;
777 	/* Read phy setting values from flash */
778 	rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
779 	if (rc) {
780 		kfree(payload.func_specific);
781 		pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
782 		return -ENOMEM;
783 	}
784 	wait_for_completion(&completion);
785 	pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
786 	kfree(payload.func_specific);
787 #endif
788 	return 0;
789 }
790 
791 struct pm8001_mpi3_phy_pg_trx_config {
792 	u32 LaneLosCfg;
793 	u32 LanePgaCfg1;
794 	u32 LanePisoCfg1;
795 	u32 LanePisoCfg2;
796 	u32 LanePisoCfg3;
797 	u32 LanePisoCfg4;
798 	u32 LanePisoCfg5;
799 	u32 LanePisoCfg6;
800 	u32 LaneBctCtrl;
801 };
802 
803 /**
804  * pm8001_get_internal_phy_settings - Retrieves the internal PHY settings
805  * @pm8001_ha : our adapter
806  * @phycfg : PHY config page to populate
807  */
808 static
809 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
810 		struct pm8001_mpi3_phy_pg_trx_config *phycfg)
811 {
812 	phycfg->LaneLosCfg   = 0x00000132;
813 	phycfg->LanePgaCfg1  = 0x00203949;
814 	phycfg->LanePisoCfg1 = 0x000000FF;
815 	phycfg->LanePisoCfg2 = 0xFF000001;
816 	phycfg->LanePisoCfg3 = 0xE7011300;
817 	phycfg->LanePisoCfg4 = 0x631C40C0;
818 	phycfg->LanePisoCfg5 = 0xF8102036;
819 	phycfg->LanePisoCfg6 = 0xF74A1000;
820 	phycfg->LaneBctCtrl  = 0x00FB33F8;
821 }
822 
823 /**
824  * pm8001_get_external_phy_settings - Retrieves the external PHY settings
825  * @pm8001_ha : our adapter
826  * @phycfg : PHY config page to populate
827  */
828 static
829 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
830 		struct pm8001_mpi3_phy_pg_trx_config *phycfg)
831 {
832 	phycfg->LaneLosCfg   = 0x00000132;
833 	phycfg->LanePgaCfg1  = 0x00203949;
834 	phycfg->LanePisoCfg1 = 0x000000FF;
835 	phycfg->LanePisoCfg2 = 0xFF000001;
836 	phycfg->LanePisoCfg3 = 0xE7011300;
837 	phycfg->LanePisoCfg4 = 0x63349140;
838 	phycfg->LanePisoCfg5 = 0xF8102036;
839 	phycfg->LanePisoCfg6 = 0xF80D9300;
840 	phycfg->LaneBctCtrl  = 0x00FB33F8;
841 }
842 
843 /**
844  * pm8001_get_phy_mask - Retrieves the mask that denotes if a PHY is int/ext
845  * @pm8001_ha : our adapter
846  * @phymask : The PHY mask
847  */
848 static
849 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
850 {
851 	switch (pm8001_ha->pdev->subsystem_device) {
852 	case 0x0070: /* H1280 - 8 external 0 internal */
853 	case 0x0072: /* H12F0 - 16 external 0 internal */
854 		*phymask = 0x0000;
855 		break;
856 
857 	case 0x0071: /* H1208 - 0 external 8 internal */
858 	case 0x0073: /* H120F - 0 external 16 internal */
859 		*phymask = 0xFFFF;
860 		break;
861 
862 	case 0x0080: /* H1244 - 4 external 4 internal */
863 		*phymask = 0x00F0;
864 		break;
865 
866 	case 0x0081: /* H1248 - 4 external 8 internal */
867 		*phymask = 0x0FF0;
868 		break;
869 
870 	case 0x0082: /* H1288 - 8 external 8 internal */
871 		*phymask = 0xFF00;
872 		break;
873 
874 	default:
875 		pm8001_dbg(pm8001_ha, INIT,
876 			   "Unknown subsystem device=0x%.04x\n",
877 			   pm8001_ha->pdev->subsystem_device);
878 	}
879 }
880 
881 /**
882  * pm8001_set_phy_settings_ven_117c_12G() - Configure ATTO 12Gb PHY settings
883  * @pm8001_ha : our adapter
884  */
885 static
886 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
887 {
888 	struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
889 	struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
890 	int phymask = 0;
891 	int i = 0;
892 
893 	memset(&phycfg_int, 0, sizeof(phycfg_int));
894 	memset(&phycfg_ext, 0, sizeof(phycfg_ext));
895 
896 	pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
897 	pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
898 	pm8001_get_phy_mask(pm8001_ha, &phymask);
899 
900 	for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
901 		if (phymask & (1 << i)) {/* Internal PHY */
902 			pm8001_set_phy_profile_single(pm8001_ha, i,
903 					sizeof(phycfg_int) / sizeof(u32),
904 					(u32 *)&phycfg_int);
905 
906 		} else { /* External PHY */
907 			pm8001_set_phy_profile_single(pm8001_ha, i,
908 					sizeof(phycfg_ext) / sizeof(u32),
909 					(u32 *)&phycfg_ext);
910 		}
911 	}
912 
913 	return 0;
914 }
915 
916 /**
917  * pm8001_configure_phy_settings - Configures PHY settings based on vendor ID.
918  * @pm8001_ha : our hba.
919  */
920 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
921 {
922 	switch (pm8001_ha->pdev->subsystem_vendor) {
923 	case PCI_VENDOR_ID_ATTO:
924 		if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */
925 			return 0;
926 		else
927 			return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
928 
929 	case PCI_VENDOR_ID_ADAPTEC2:
930 	case 0:
931 		return 0;
932 
933 	default:
934 		return pm8001_get_phy_settings_info(pm8001_ha);
935 	}
936 }
937 
938 #ifdef PM8001_USE_MSIX
939 /**
940  * pm8001_setup_msix - enable MSI-X interrupt
941  * @pm8001_ha: our ha struct.
942  */
943 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
944 {
945 	unsigned int allocated_irq_vectors;
946 	int rc;
947 
948 	/* SPCv controllers supports 64 msi-x */
949 	if (pm8001_ha->chip_id == chip_8001) {
950 		rc = pci_alloc_irq_vectors(pm8001_ha->pdev, 1, 1,
951 					   PCI_IRQ_MSIX);
952 	} else {
953 		/*
954 		 * Queue index #0 is used always for housekeeping, so don't
955 		 * include in the affinity spreading.
956 		 */
957 		struct irq_affinity desc = {
958 			.pre_vectors = 1,
959 		};
960 		rc = pci_alloc_irq_vectors_affinity(
961 				pm8001_ha->pdev, 2, PM8001_MAX_MSIX_VEC,
962 				PCI_IRQ_MSIX | PCI_IRQ_AFFINITY, &desc);
963 	}
964 
965 	allocated_irq_vectors = rc;
966 	if (rc < 0)
967 		return rc;
968 
969 	/* Assigns the number of interrupts */
970 	pm8001_ha->number_of_intr = allocated_irq_vectors;
971 
972 	/* Maximum queue number updating in HBA structure */
973 	pm8001_ha->max_q_num = allocated_irq_vectors;
974 
975 	pm8001_dbg(pm8001_ha, INIT,
976 		   "pci_alloc_irq_vectors request ret:%d no of intr %d\n",
977 		   rc, pm8001_ha->number_of_intr);
978 	return 0;
979 }
980 
981 static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha)
982 {
983 	u32 i = 0, j = 0;
984 	int flag = 0, rc = 0;
985 	int nr_irqs = pm8001_ha->number_of_intr;
986 
987 	if (pm8001_ha->chip_id != chip_8001)
988 		flag &= ~IRQF_SHARED;
989 
990 	pm8001_dbg(pm8001_ha, INIT,
991 		   "pci_enable_msix request number of intr %d\n",
992 		   pm8001_ha->number_of_intr);
993 
994 	if (nr_irqs > ARRAY_SIZE(pm8001_ha->intr_drvname))
995 		nr_irqs = ARRAY_SIZE(pm8001_ha->intr_drvname);
996 
997 	for (i = 0; i < nr_irqs; i++) {
998 		snprintf(pm8001_ha->intr_drvname[i],
999 			sizeof(pm8001_ha->intr_drvname[0]),
1000 			"%s-%d", pm8001_ha->name, i);
1001 		pm8001_ha->irq_vector[i].irq_id = i;
1002 		pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
1003 
1004 		rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i),
1005 			pm8001_interrupt_handler_msix, flag,
1006 			pm8001_ha->intr_drvname[i],
1007 			&(pm8001_ha->irq_vector[i]));
1008 		if (rc) {
1009 			for (j = 0; j < i; j++) {
1010 				free_irq(pci_irq_vector(pm8001_ha->pdev, i),
1011 					&(pm8001_ha->irq_vector[i]));
1012 			}
1013 			pci_free_irq_vectors(pm8001_ha->pdev);
1014 			break;
1015 		}
1016 	}
1017 
1018 	return rc;
1019 }
1020 #endif
1021 
1022 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha)
1023 {
1024 	struct pci_dev *pdev;
1025 
1026 	pdev = pm8001_ha->pdev;
1027 
1028 #ifdef PM8001_USE_MSIX
1029 	if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
1030 		return pm8001_setup_msix(pm8001_ha);
1031 	pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1032 #endif
1033 	return 0;
1034 }
1035 
1036 /**
1037  * pm8001_request_irq - register interrupt
1038  * @pm8001_ha: our ha struct.
1039  */
1040 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
1041 {
1042 	struct pci_dev *pdev;
1043 	int rc;
1044 
1045 	pdev = pm8001_ha->pdev;
1046 
1047 #ifdef PM8001_USE_MSIX
1048 	if (pdev->msix_cap && pci_msi_enabled())
1049 		return pm8001_request_msix(pm8001_ha);
1050 	else {
1051 		pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1052 		goto intx;
1053 	}
1054 #endif
1055 
1056 intx:
1057 	/* initialize the INT-X interrupt */
1058 	pm8001_ha->irq_vector[0].irq_id = 0;
1059 	pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
1060 	rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
1061 		pm8001_ha->name, SHOST_TO_SAS_HA(pm8001_ha->shost));
1062 	return rc;
1063 }
1064 
1065 /**
1066  * pm8001_pci_probe - probe supported device
1067  * @pdev: pci device which kernel has been prepared for.
1068  * @ent: pci device id
1069  *
1070  * This function is the main initialization function, when register a new
1071  * pci driver it is invoked, all struct and hardware initialization should be
1072  * done here, also, register interrupt.
1073  */
1074 static int pm8001_pci_probe(struct pci_dev *pdev,
1075 			    const struct pci_device_id *ent)
1076 {
1077 	unsigned int rc;
1078 	u32	pci_reg;
1079 	u8	i = 0;
1080 	struct pm8001_hba_info *pm8001_ha;
1081 	struct Scsi_Host *shost = NULL;
1082 	const struct pm8001_chip_info *chip;
1083 	struct sas_ha_struct *sha;
1084 
1085 	dev_printk(KERN_INFO, &pdev->dev,
1086 		"pm80xx: driver version %s\n", DRV_VERSION);
1087 	rc = pci_enable_device(pdev);
1088 	if (rc)
1089 		goto err_out_enable;
1090 	pci_set_master(pdev);
1091 	/*
1092 	 * Enable pci slot busmaster by setting pci command register.
1093 	 * This is required by FW for Cyclone card.
1094 	 */
1095 
1096 	pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
1097 	pci_reg |= 0x157;
1098 	pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
1099 	rc = pci_request_regions(pdev, DRV_NAME);
1100 	if (rc)
1101 		goto err_out_disable;
1102 	rc = pci_go_44(pdev);
1103 	if (rc)
1104 		goto err_out_regions;
1105 
1106 	shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
1107 	if (!shost) {
1108 		rc = -ENOMEM;
1109 		goto err_out_regions;
1110 	}
1111 	chip = &pm8001_chips[ent->driver_data];
1112 	sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
1113 	if (!sha) {
1114 		rc = -ENOMEM;
1115 		goto err_out_free_host;
1116 	}
1117 	SHOST_TO_SAS_HA(shost) = sha;
1118 
1119 	rc = pm8001_prep_sas_ha_init(shost, chip);
1120 	if (rc) {
1121 		rc = -ENOMEM;
1122 		goto err_out_free;
1123 	}
1124 	pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
1125 	/* ent->driver variable is used to differentiate between controllers */
1126 	pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
1127 	if (!pm8001_ha) {
1128 		rc = -ENOMEM;
1129 		goto err_out_free;
1130 	}
1131 
1132 	PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1133 	rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1134 	if (rc) {
1135 		pm8001_dbg(pm8001_ha, FAIL,
1136 			   "chip_init failed [ret: %d]\n", rc);
1137 		goto err_out_ha_free;
1138 	}
1139 
1140 	rc = pm8001_init_ccb_tag(pm8001_ha);
1141 	if (rc)
1142 		goto err_out_enable;
1143 
1144 
1145 	PM8001_CHIP_DISP->chip_post_init(pm8001_ha);
1146 
1147 	if (pm8001_ha->number_of_intr > 1) {
1148 		shost->nr_hw_queues = pm8001_ha->number_of_intr - 1;
1149 		/*
1150 		 * For now, ensure we're not sent too many commands by setting
1151 		 * host_tagset. This is also required if we start using request
1152 		 * tag.
1153 		 */
1154 		shost->host_tagset = 1;
1155 	}
1156 
1157 	rc = scsi_add_host(shost, &pdev->dev);
1158 	if (rc)
1159 		goto err_out_ha_free;
1160 
1161 	PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1162 	if (pm8001_ha->chip_id != chip_8001) {
1163 		for (i = 1; i < pm8001_ha->number_of_intr; i++)
1164 			PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1165 		/* setup thermal configuration. */
1166 		pm80xx_set_thermal_config(pm8001_ha);
1167 	}
1168 
1169 	pm8001_init_sas_add(pm8001_ha);
1170 	/* phy setting support for motherboard controller */
1171 	rc = pm8001_configure_phy_settings(pm8001_ha);
1172 	if (rc)
1173 		goto err_out_shost;
1174 
1175 	pm8001_post_sas_ha_init(shost, chip);
1176 	rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
1177 	if (rc) {
1178 		pm8001_dbg(pm8001_ha, FAIL,
1179 			   "sas_register_ha failed [ret: %d]\n", rc);
1180 		goto err_out_shost;
1181 	}
1182 	list_add_tail(&pm8001_ha->list, &hba_list);
1183 	pm8001_ha->flags = PM8001F_RUN_TIME;
1184 	scsi_scan_host(pm8001_ha->shost);
1185 	return 0;
1186 
1187 err_out_shost:
1188 	scsi_remove_host(pm8001_ha->shost);
1189 err_out_ha_free:
1190 	pm8001_free(pm8001_ha);
1191 err_out_free:
1192 	kfree(sha);
1193 err_out_free_host:
1194 	scsi_host_put(shost);
1195 err_out_regions:
1196 	pci_release_regions(pdev);
1197 err_out_disable:
1198 	pci_disable_device(pdev);
1199 err_out_enable:
1200 	return rc;
1201 }
1202 
1203 /**
1204  * pm8001_init_ccb_tag - allocate memory to CCB and tag.
1205  * @pm8001_ha: our hba card information.
1206  */
1207 static int pm8001_init_ccb_tag(struct pm8001_hba_info *pm8001_ha)
1208 {
1209 	struct Scsi_Host *shost = pm8001_ha->shost;
1210 	struct device *dev = pm8001_ha->dev;
1211 	u32 max_out_io, ccb_count;
1212 	int i;
1213 
1214 	max_out_io = pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io;
1215 	ccb_count = min_t(int, PM8001_MAX_CCB, max_out_io);
1216 
1217 	shost->can_queue = ccb_count - PM8001_RESERVE_SLOT;
1218 
1219 	pm8001_ha->rsvd_tags = bitmap_zalloc(PM8001_RESERVE_SLOT, GFP_KERNEL);
1220 	if (!pm8001_ha->rsvd_tags)
1221 		goto err_out;
1222 
1223 	/* Memory region for ccb_info*/
1224 	pm8001_ha->ccb_count = ccb_count;
1225 	pm8001_ha->ccb_info =
1226 		kcalloc(ccb_count, sizeof(struct pm8001_ccb_info), GFP_KERNEL);
1227 	if (!pm8001_ha->ccb_info) {
1228 		pm8001_dbg(pm8001_ha, FAIL,
1229 			   "Unable to allocate memory for ccb\n");
1230 		goto err_out_noccb;
1231 	}
1232 	for (i = 0; i < ccb_count; i++) {
1233 		pm8001_ha->ccb_info[i].buf_prd = dma_alloc_coherent(dev,
1234 				sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1235 				&pm8001_ha->ccb_info[i].ccb_dma_handle,
1236 				GFP_KERNEL);
1237 		if (!pm8001_ha->ccb_info[i].buf_prd) {
1238 			pm8001_dbg(pm8001_ha, FAIL,
1239 				   "ccb prd memory allocation error\n");
1240 			goto err_out;
1241 		}
1242 		pm8001_ha->ccb_info[i].task = NULL;
1243 		pm8001_ha->ccb_info[i].ccb_tag = PM8001_INVALID_TAG;
1244 		pm8001_ha->ccb_info[i].device = NULL;
1245 	}
1246 
1247 	return 0;
1248 
1249 err_out_noccb:
1250 	kfree(pm8001_ha->devices);
1251 err_out:
1252 	return -ENOMEM;
1253 }
1254 
1255 static void pm8001_pci_remove(struct pci_dev *pdev)
1256 {
1257 	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1258 	struct pm8001_hba_info *pm8001_ha;
1259 	int i, j;
1260 	pm8001_ha = sha->lldd_ha;
1261 	sas_unregister_ha(sha);
1262 	sas_remove_host(pm8001_ha->shost);
1263 	list_del(&pm8001_ha->list);
1264 	PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1265 	PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1266 
1267 #ifdef PM8001_USE_MSIX
1268 	for (i = 0; i < pm8001_ha->number_of_intr; i++)
1269 		synchronize_irq(pci_irq_vector(pdev, i));
1270 	for (i = 0; i < pm8001_ha->number_of_intr; i++)
1271 		free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1272 	pci_free_irq_vectors(pdev);
1273 #else
1274 	free_irq(pm8001_ha->irq, sha);
1275 #endif
1276 #ifdef PM8001_USE_TASKLET
1277 	/* For non-msix and msix interrupts */
1278 	if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1279 	    (pm8001_ha->chip_id == chip_8001))
1280 		tasklet_kill(&pm8001_ha->tasklet[0]);
1281 	else
1282 		for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1283 			tasklet_kill(&pm8001_ha->tasklet[j]);
1284 #endif
1285 	scsi_host_put(pm8001_ha->shost);
1286 
1287 	for (i = 0; i < pm8001_ha->ccb_count; i++) {
1288 		dma_free_coherent(&pm8001_ha->pdev->dev,
1289 			sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1290 			pm8001_ha->ccb_info[i].buf_prd,
1291 			pm8001_ha->ccb_info[i].ccb_dma_handle);
1292 	}
1293 	kfree(pm8001_ha->ccb_info);
1294 	kfree(pm8001_ha->devices);
1295 
1296 	pm8001_free(pm8001_ha);
1297 	kfree(sha->sas_phy);
1298 	kfree(sha->sas_port);
1299 	kfree(sha);
1300 	pci_release_regions(pdev);
1301 	pci_disable_device(pdev);
1302 }
1303 
1304 /**
1305  * pm8001_pci_suspend - power management suspend main entry point
1306  * @dev: Device struct
1307  *
1308  * Return: 0 on success, anything else on error.
1309  */
1310 static int __maybe_unused pm8001_pci_suspend(struct device *dev)
1311 {
1312 	struct pci_dev *pdev = to_pci_dev(dev);
1313 	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1314 	struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
1315 	int  i, j;
1316 	sas_suspend_ha(sha);
1317 	flush_workqueue(pm8001_wq);
1318 	scsi_block_requests(pm8001_ha->shost);
1319 	if (!pdev->pm_cap) {
1320 		dev_err(dev, " PCI PM not supported\n");
1321 		return -ENODEV;
1322 	}
1323 	PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1324 	PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1325 #ifdef PM8001_USE_MSIX
1326 	for (i = 0; i < pm8001_ha->number_of_intr; i++)
1327 		synchronize_irq(pci_irq_vector(pdev, i));
1328 	for (i = 0; i < pm8001_ha->number_of_intr; i++)
1329 		free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1330 	pci_free_irq_vectors(pdev);
1331 #else
1332 	free_irq(pm8001_ha->irq, sha);
1333 #endif
1334 #ifdef PM8001_USE_TASKLET
1335 	/* For non-msix and msix interrupts */
1336 	if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1337 	    (pm8001_ha->chip_id == chip_8001))
1338 		tasklet_kill(&pm8001_ha->tasklet[0]);
1339 	else
1340 		for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1341 			tasklet_kill(&pm8001_ha->tasklet[j]);
1342 #endif
1343 	pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, entering "
1344 		      "suspended state\n", pdev,
1345 		      pm8001_ha->name);
1346 	return 0;
1347 }
1348 
1349 /**
1350  * pm8001_pci_resume - power management resume main entry point
1351  * @dev: Device struct
1352  *
1353  * Return: 0 on success, anything else on error.
1354  */
1355 static int __maybe_unused pm8001_pci_resume(struct device *dev)
1356 {
1357 	struct pci_dev *pdev = to_pci_dev(dev);
1358 	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1359 	struct pm8001_hba_info *pm8001_ha;
1360 	int rc;
1361 	u8 i = 0, j;
1362 	DECLARE_COMPLETION_ONSTACK(completion);
1363 
1364 	pm8001_ha = sha->lldd_ha;
1365 
1366 	pm8001_info(pm8001_ha,
1367 		    "pdev=0x%p, slot=%s, resuming from previous operating state [D%d]\n",
1368 		    pdev, pm8001_ha->name, pdev->current_state);
1369 
1370 	rc = pci_go_44(pdev);
1371 	if (rc)
1372 		goto err_out_disable;
1373 	sas_prep_resume_ha(sha);
1374 	/* chip soft rst only for spc */
1375 	if (pm8001_ha->chip_id == chip_8001) {
1376 		PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1377 		pm8001_dbg(pm8001_ha, INIT, "chip soft reset successful\n");
1378 	}
1379 	rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1380 	if (rc)
1381 		goto err_out_disable;
1382 
1383 	/* disable all the interrupt bits */
1384 	PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1385 
1386 	rc = pm8001_request_irq(pm8001_ha);
1387 	if (rc)
1388 		goto err_out_disable;
1389 #ifdef PM8001_USE_TASKLET
1390 	/*  Tasklet for non msi-x interrupt handler */
1391 	if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1392 	    (pm8001_ha->chip_id == chip_8001))
1393 		tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1394 			(unsigned long)&(pm8001_ha->irq_vector[0]));
1395 	else
1396 		for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1397 			tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1398 				(unsigned long)&(pm8001_ha->irq_vector[j]));
1399 #endif
1400 	PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1401 	if (pm8001_ha->chip_id != chip_8001) {
1402 		for (i = 1; i < pm8001_ha->number_of_intr; i++)
1403 			PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1404 	}
1405 
1406 	/* Chip documentation for the 8070 and 8072 SPCv    */
1407 	/* states that a 500ms minimum delay is required    */
1408 	/* before issuing commands. Otherwise, the firmware */
1409 	/* will enter an unrecoverable state.               */
1410 
1411 	if (pm8001_ha->chip_id == chip_8070 ||
1412 		pm8001_ha->chip_id == chip_8072) {
1413 		mdelay(500);
1414 	}
1415 
1416 	/* Spin up the PHYs */
1417 
1418 	pm8001_ha->flags = PM8001F_RUN_TIME;
1419 	for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1420 		pm8001_ha->phy[i].enable_completion = &completion;
1421 		PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1422 		wait_for_completion(&completion);
1423 	}
1424 	sas_resume_ha(sha);
1425 	return 0;
1426 
1427 err_out_disable:
1428 	scsi_remove_host(pm8001_ha->shost);
1429 
1430 	return rc;
1431 }
1432 
1433 /* update of pci device, vendor id and driver data with
1434  * unique value for each of the controller
1435  */
1436 static struct pci_device_id pm8001_pci_table[] = {
1437 	{ PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1438 	{ PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1439 	{ PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1440 	{ PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1441 	/* Support for SPC/SPCv/SPCve controllers */
1442 	{ PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1443 	{ PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1444 	{ PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1445 	{ PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1446 	{ PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1447 	{ PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1448 	{ PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1449 	{ PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1450 	{ PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1451 	{ PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1452 	{ PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1453 	{ PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1454 	{ PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1455 	{ PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1456 	{ PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1457 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1458 		PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1459 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1460 		PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1461 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1462 		PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1463 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1464 		PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1465 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1466 		PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1467 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1468 		PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1469 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1470 		PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1471 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1472 		PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1473 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1474 		PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1475 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1476 		PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1477 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1478 		PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1479 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1480 		PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1481 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1482 		PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1483 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1484 		PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1485 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1486 		PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1487 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1488 		PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1489 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1490 		PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1491 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1492 		PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1493 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1494 		PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1495 	{ PCI_VENDOR_ID_ATTO, 0x8070,
1496 		PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1497 	{ PCI_VENDOR_ID_ATTO, 0x8070,
1498 		PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1499 	{ PCI_VENDOR_ID_ATTO, 0x8072,
1500 		PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1501 	{ PCI_VENDOR_ID_ATTO, 0x8072,
1502 		PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1503 	{ PCI_VENDOR_ID_ATTO, 0x8070,
1504 		PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1505 	{ PCI_VENDOR_ID_ATTO, 0x8072,
1506 		PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1507 	{ PCI_VENDOR_ID_ATTO, 0x8072,
1508 		PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1509 	{} /* terminate list */
1510 };
1511 
1512 static SIMPLE_DEV_PM_OPS(pm8001_pci_pm_ops,
1513 			 pm8001_pci_suspend,
1514 			 pm8001_pci_resume);
1515 
1516 static struct pci_driver pm8001_pci_driver = {
1517 	.name		= DRV_NAME,
1518 	.id_table	= pm8001_pci_table,
1519 	.probe		= pm8001_pci_probe,
1520 	.remove		= pm8001_pci_remove,
1521 	.driver.pm	= &pm8001_pci_pm_ops,
1522 };
1523 
1524 /**
1525  *	pm8001_init - initialize scsi transport template
1526  */
1527 static int __init pm8001_init(void)
1528 {
1529 	int rc = -ENOMEM;
1530 
1531 	pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1532 	if (!pm8001_wq)
1533 		goto err;
1534 
1535 	pm8001_id = 0;
1536 	pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1537 	if (!pm8001_stt)
1538 		goto err_wq;
1539 	rc = pci_register_driver(&pm8001_pci_driver);
1540 	if (rc)
1541 		goto err_tp;
1542 	return 0;
1543 
1544 err_tp:
1545 	sas_release_transport(pm8001_stt);
1546 err_wq:
1547 	destroy_workqueue(pm8001_wq);
1548 err:
1549 	return rc;
1550 }
1551 
1552 static void __exit pm8001_exit(void)
1553 {
1554 	pci_unregister_driver(&pm8001_pci_driver);
1555 	sas_release_transport(pm8001_stt);
1556 	destroy_workqueue(pm8001_wq);
1557 }
1558 
1559 module_init(pm8001_init);
1560 module_exit(pm8001_exit);
1561 
1562 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1563 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1564 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1565 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1566 MODULE_DESCRIPTION(
1567 		"PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1568 		"SAS/SATA controller driver");
1569 MODULE_VERSION(DRV_VERSION);
1570 MODULE_LICENSE("GPL");
1571 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1572 
1573