1 /* 2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 USI Co., Ltd. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 41 #include <linux/slab.h> 42 #include "pm8001_sas.h" 43 #include "pm8001_chips.h" 44 #include "pm80xx_hwi.h" 45 46 static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING; 47 module_param(logging_level, ulong, 0644); 48 MODULE_PARM_DESC(logging_level, " bits for enabling logging info."); 49 50 static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120; 51 module_param(link_rate, ulong, 0644); 52 MODULE_PARM_DESC(link_rate, "Enable link rate.\n" 53 " 1: Link rate 1.5G\n" 54 " 2: Link rate 3.0G\n" 55 " 4: Link rate 6.0G\n" 56 " 8: Link rate 12.0G\n"); 57 58 static struct scsi_transport_template *pm8001_stt; 59 static int pm8001_init_ccb_tag(struct pm8001_hba_info *, struct Scsi_Host *, struct pci_dev *); 60 61 /* 62 * chip info structure to identify chip key functionality as 63 * encryption available/not, no of ports, hw specific function ref 64 */ 65 static const struct pm8001_chip_info pm8001_chips[] = { 66 [chip_8001] = {0, 8, &pm8001_8001_dispatch,}, 67 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,}, 68 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,}, 69 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,}, 70 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,}, 71 [chip_8074] = {0, 8, &pm8001_80xx_dispatch,}, 72 [chip_8076] = {0, 16, &pm8001_80xx_dispatch,}, 73 [chip_8077] = {0, 16, &pm8001_80xx_dispatch,}, 74 [chip_8006] = {0, 16, &pm8001_80xx_dispatch,}, 75 [chip_8070] = {0, 8, &pm8001_80xx_dispatch,}, 76 [chip_8072] = {0, 16, &pm8001_80xx_dispatch,}, 77 }; 78 static int pm8001_id; 79 80 LIST_HEAD(hba_list); 81 82 struct workqueue_struct *pm8001_wq; 83 84 /* 85 * The main structure which LLDD must register for scsi core. 86 */ 87 static struct scsi_host_template pm8001_sht = { 88 .module = THIS_MODULE, 89 .name = DRV_NAME, 90 .queuecommand = sas_queuecommand, 91 .dma_need_drain = ata_scsi_dma_need_drain, 92 .target_alloc = sas_target_alloc, 93 .slave_configure = sas_slave_configure, 94 .scan_finished = pm8001_scan_finished, 95 .scan_start = pm8001_scan_start, 96 .change_queue_depth = sas_change_queue_depth, 97 .bios_param = sas_bios_param, 98 .can_queue = 1, 99 .this_id = -1, 100 .sg_tablesize = PM8001_MAX_DMA_SG, 101 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 102 .eh_device_reset_handler = sas_eh_device_reset_handler, 103 .eh_target_reset_handler = sas_eh_target_reset_handler, 104 .slave_alloc = sas_slave_alloc, 105 .target_destroy = sas_target_destroy, 106 .ioctl = sas_ioctl, 107 #ifdef CONFIG_COMPAT 108 .compat_ioctl = sas_ioctl, 109 #endif 110 .shost_groups = pm8001_host_groups, 111 .track_queue_depth = 1, 112 }; 113 114 /* 115 * Sas layer call this function to execute specific task. 116 */ 117 static struct sas_domain_function_template pm8001_transport_ops = { 118 .lldd_dev_found = pm8001_dev_found, 119 .lldd_dev_gone = pm8001_dev_gone, 120 121 .lldd_execute_task = pm8001_queue_command, 122 .lldd_control_phy = pm8001_phy_control, 123 124 .lldd_abort_task = pm8001_abort_task, 125 .lldd_abort_task_set = pm8001_abort_task_set, 126 .lldd_clear_aca = pm8001_clear_aca, 127 .lldd_clear_task_set = pm8001_clear_task_set, 128 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset, 129 .lldd_lu_reset = pm8001_lu_reset, 130 .lldd_query_task = pm8001_query_task, 131 .lldd_port_formed = pm8001_port_formed, 132 }; 133 134 /** 135 * pm8001_phy_init - initiate our adapter phys 136 * @pm8001_ha: our hba structure. 137 * @phy_id: phy id. 138 */ 139 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id) 140 { 141 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 142 struct asd_sas_phy *sas_phy = &phy->sas_phy; 143 phy->phy_state = PHY_LINK_DISABLE; 144 phy->pm8001_ha = pm8001_ha; 145 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0; 146 sas_phy->class = SAS; 147 sas_phy->iproto = SAS_PROTOCOL_ALL; 148 sas_phy->tproto = 0; 149 sas_phy->type = PHY_TYPE_PHYSICAL; 150 sas_phy->role = PHY_ROLE_INITIATOR; 151 sas_phy->oob_mode = OOB_NOT_CONNECTED; 152 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN; 153 sas_phy->id = phy_id; 154 sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr; 155 sas_phy->frame_rcvd = &phy->frame_rcvd[0]; 156 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata; 157 sas_phy->lldd_phy = phy; 158 } 159 160 /** 161 * pm8001_free - free hba 162 * @pm8001_ha: our hba structure. 163 */ 164 static void pm8001_free(struct pm8001_hba_info *pm8001_ha) 165 { 166 int i; 167 168 if (!pm8001_ha) 169 return; 170 171 for (i = 0; i < USI_MAX_MEMCNT; i++) { 172 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) { 173 dma_free_coherent(&pm8001_ha->pdev->dev, 174 (pm8001_ha->memoryMap.region[i].total_len + 175 pm8001_ha->memoryMap.region[i].alignment), 176 pm8001_ha->memoryMap.region[i].virt_ptr, 177 pm8001_ha->memoryMap.region[i].phys_addr); 178 } 179 } 180 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha); 181 flush_workqueue(pm8001_wq); 182 kfree(pm8001_ha->tags); 183 kfree(pm8001_ha); 184 } 185 186 #ifdef PM8001_USE_TASKLET 187 188 /** 189 * pm8001_tasklet() - tasklet for 64 msi-x interrupt handler 190 * @opaque: the passed general host adapter struct 191 * Note: pm8001_tasklet is common for pm8001 & pm80xx 192 */ 193 static void pm8001_tasklet(unsigned long opaque) 194 { 195 struct pm8001_hba_info *pm8001_ha; 196 struct isr_param *irq_vector; 197 198 irq_vector = (struct isr_param *)opaque; 199 pm8001_ha = irq_vector->drv_inst; 200 if (unlikely(!pm8001_ha)) 201 BUG_ON(1); 202 PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id); 203 } 204 #endif 205 206 /** 207 * pm8001_interrupt_handler_msix - main MSIX interrupt handler. 208 * It obtains the vector number and calls the equivalent bottom 209 * half or services directly. 210 * @irq: interrupt number 211 * @opaque: the passed outbound queue/vector. Host structure is 212 * retrieved from the same. 213 */ 214 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque) 215 { 216 struct isr_param *irq_vector; 217 struct pm8001_hba_info *pm8001_ha; 218 irqreturn_t ret = IRQ_HANDLED; 219 irq_vector = (struct isr_param *)opaque; 220 pm8001_ha = irq_vector->drv_inst; 221 222 if (unlikely(!pm8001_ha)) 223 return IRQ_NONE; 224 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha)) 225 return IRQ_NONE; 226 #ifdef PM8001_USE_TASKLET 227 tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]); 228 #else 229 ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id); 230 #endif 231 return ret; 232 } 233 234 /** 235 * pm8001_interrupt_handler_intx - main INTx interrupt handler. 236 * @irq: interrupt number 237 * @dev_id: sas_ha structure. The HBA is retrieved from sas_ha structure. 238 */ 239 240 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id) 241 { 242 struct pm8001_hba_info *pm8001_ha; 243 irqreturn_t ret = IRQ_HANDLED; 244 struct sas_ha_struct *sha = dev_id; 245 pm8001_ha = sha->lldd_ha; 246 if (unlikely(!pm8001_ha)) 247 return IRQ_NONE; 248 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha)) 249 return IRQ_NONE; 250 251 #ifdef PM8001_USE_TASKLET 252 tasklet_schedule(&pm8001_ha->tasklet[0]); 253 #else 254 ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0); 255 #endif 256 return ret; 257 } 258 259 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha); 260 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha); 261 262 /** 263 * pm8001_alloc - initiate our hba structure and 6 DMAs area. 264 * @pm8001_ha: our hba structure. 265 * @ent: PCI device ID structure to match on 266 */ 267 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha, 268 const struct pci_device_id *ent) 269 { 270 int i, count = 0, rc = 0; 271 u32 ci_offset, ib_offset, ob_offset, pi_offset; 272 struct inbound_queue_table *ibq; 273 struct outbound_queue_table *obq; 274 275 spin_lock_init(&pm8001_ha->lock); 276 spin_lock_init(&pm8001_ha->bitmap_lock); 277 pm8001_dbg(pm8001_ha, INIT, "pm8001_alloc: PHY:%x\n", 278 pm8001_ha->chip->n_phy); 279 280 /* Setup Interrupt */ 281 rc = pm8001_setup_irq(pm8001_ha); 282 if (rc) { 283 pm8001_dbg(pm8001_ha, FAIL, 284 "pm8001_setup_irq failed [ret: %d]\n", rc); 285 goto err_out_shost; 286 } 287 /* Request Interrupt */ 288 rc = pm8001_request_irq(pm8001_ha); 289 if (rc) 290 goto err_out_shost; 291 292 count = pm8001_ha->max_q_num; 293 /* Queues are chosen based on the number of cores/msix availability */ 294 ib_offset = pm8001_ha->ib_offset = USI_MAX_MEMCNT_BASE; 295 ci_offset = pm8001_ha->ci_offset = ib_offset + count; 296 ob_offset = pm8001_ha->ob_offset = ci_offset + count; 297 pi_offset = pm8001_ha->pi_offset = ob_offset + count; 298 pm8001_ha->max_memcnt = pi_offset + count; 299 300 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 301 pm8001_phy_init(pm8001_ha, i); 302 pm8001_ha->port[i].wide_port_phymap = 0; 303 pm8001_ha->port[i].port_attached = 0; 304 pm8001_ha->port[i].port_state = 0; 305 INIT_LIST_HEAD(&pm8001_ha->port[i].list); 306 } 307 308 /* MPI Memory region 1 for AAP Event Log for fw */ 309 pm8001_ha->memoryMap.region[AAP1].num_elements = 1; 310 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE; 311 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE; 312 pm8001_ha->memoryMap.region[AAP1].alignment = 32; 313 314 /* MPI Memory region 2 for IOP Event Log for fw */ 315 pm8001_ha->memoryMap.region[IOP].num_elements = 1; 316 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE; 317 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE; 318 pm8001_ha->memoryMap.region[IOP].alignment = 32; 319 320 for (i = 0; i < count; i++) { 321 ibq = &pm8001_ha->inbnd_q_tbl[i]; 322 spin_lock_init(&ibq->iq_lock); 323 /* MPI Memory region 3 for consumer Index of inbound queues */ 324 pm8001_ha->memoryMap.region[ci_offset+i].num_elements = 1; 325 pm8001_ha->memoryMap.region[ci_offset+i].element_size = 4; 326 pm8001_ha->memoryMap.region[ci_offset+i].total_len = 4; 327 pm8001_ha->memoryMap.region[ci_offset+i].alignment = 4; 328 329 if ((ent->driver_data) != chip_8001) { 330 /* MPI Memory region 5 inbound queues */ 331 pm8001_ha->memoryMap.region[ib_offset+i].num_elements = 332 PM8001_MPI_QUEUE; 333 pm8001_ha->memoryMap.region[ib_offset+i].element_size 334 = 128; 335 pm8001_ha->memoryMap.region[ib_offset+i].total_len = 336 PM8001_MPI_QUEUE * 128; 337 pm8001_ha->memoryMap.region[ib_offset+i].alignment 338 = 128; 339 } else { 340 pm8001_ha->memoryMap.region[ib_offset+i].num_elements = 341 PM8001_MPI_QUEUE; 342 pm8001_ha->memoryMap.region[ib_offset+i].element_size 343 = 64; 344 pm8001_ha->memoryMap.region[ib_offset+i].total_len = 345 PM8001_MPI_QUEUE * 64; 346 pm8001_ha->memoryMap.region[ib_offset+i].alignment = 64; 347 } 348 } 349 350 for (i = 0; i < count; i++) { 351 obq = &pm8001_ha->outbnd_q_tbl[i]; 352 spin_lock_init(&obq->oq_lock); 353 /* MPI Memory region 4 for producer Index of outbound queues */ 354 pm8001_ha->memoryMap.region[pi_offset+i].num_elements = 1; 355 pm8001_ha->memoryMap.region[pi_offset+i].element_size = 4; 356 pm8001_ha->memoryMap.region[pi_offset+i].total_len = 4; 357 pm8001_ha->memoryMap.region[pi_offset+i].alignment = 4; 358 359 if (ent->driver_data != chip_8001) { 360 /* MPI Memory region 6 Outbound queues */ 361 pm8001_ha->memoryMap.region[ob_offset+i].num_elements = 362 PM8001_MPI_QUEUE; 363 pm8001_ha->memoryMap.region[ob_offset+i].element_size 364 = 128; 365 pm8001_ha->memoryMap.region[ob_offset+i].total_len = 366 PM8001_MPI_QUEUE * 128; 367 pm8001_ha->memoryMap.region[ob_offset+i].alignment 368 = 128; 369 } else { 370 /* MPI Memory region 6 Outbound queues */ 371 pm8001_ha->memoryMap.region[ob_offset+i].num_elements = 372 PM8001_MPI_QUEUE; 373 pm8001_ha->memoryMap.region[ob_offset+i].element_size 374 = 64; 375 pm8001_ha->memoryMap.region[ob_offset+i].total_len = 376 PM8001_MPI_QUEUE * 64; 377 pm8001_ha->memoryMap.region[ob_offset+i].alignment = 64; 378 } 379 380 } 381 /* Memory region write DMA*/ 382 pm8001_ha->memoryMap.region[NVMD].num_elements = 1; 383 pm8001_ha->memoryMap.region[NVMD].element_size = 4096; 384 pm8001_ha->memoryMap.region[NVMD].total_len = 4096; 385 386 /* Memory region for fw flash */ 387 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096; 388 389 pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1; 390 pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000; 391 pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000; 392 pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000; 393 for (i = 0; i < pm8001_ha->max_memcnt; i++) { 394 struct mpi_mem *region = &pm8001_ha->memoryMap.region[i]; 395 396 if (pm8001_mem_alloc(pm8001_ha->pdev, 397 ®ion->virt_ptr, 398 ®ion->phys_addr, 399 ®ion->phys_addr_hi, 400 ®ion->phys_addr_lo, 401 region->total_len, 402 region->alignment) != 0) { 403 pm8001_dbg(pm8001_ha, FAIL, "Mem%d alloc failed\n", i); 404 goto err_out; 405 } 406 } 407 408 /* Memory region for devices*/ 409 pm8001_ha->devices = kzalloc(PM8001_MAX_DEVICES 410 * sizeof(struct pm8001_device), GFP_KERNEL); 411 if (!pm8001_ha->devices) { 412 rc = -ENOMEM; 413 goto err_out_nodev; 414 } 415 for (i = 0; i < PM8001_MAX_DEVICES; i++) { 416 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED; 417 pm8001_ha->devices[i].id = i; 418 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES; 419 atomic_set(&pm8001_ha->devices[i].running_req, 0); 420 } 421 pm8001_ha->flags = PM8001F_INIT_TIME; 422 /* Initialize tags */ 423 pm8001_tag_init(pm8001_ha); 424 return 0; 425 426 err_out_shost: 427 scsi_remove_host(pm8001_ha->shost); 428 err_out_nodev: 429 for (i = 0; i < pm8001_ha->max_memcnt; i++) { 430 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) { 431 dma_free_coherent(&pm8001_ha->pdev->dev, 432 (pm8001_ha->memoryMap.region[i].total_len + 433 pm8001_ha->memoryMap.region[i].alignment), 434 pm8001_ha->memoryMap.region[i].virt_ptr, 435 pm8001_ha->memoryMap.region[i].phys_addr); 436 } 437 } 438 err_out: 439 return 1; 440 } 441 442 /** 443 * pm8001_ioremap - remap the pci high physical address to kernel virtual 444 * address so that we can access them. 445 * @pm8001_ha: our hba structure. 446 */ 447 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha) 448 { 449 u32 bar; 450 u32 logicalBar = 0; 451 struct pci_dev *pdev; 452 453 pdev = pm8001_ha->pdev; 454 /* map pci mem (PMC pci base 0-3)*/ 455 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { 456 /* 457 ** logical BARs for SPC: 458 ** bar 0 and 1 - logical BAR0 459 ** bar 2 and 3 - logical BAR1 460 ** bar4 - logical BAR2 461 ** bar5 - logical BAR3 462 ** Skip the appropriate assignments: 463 */ 464 if ((bar == 1) || (bar == 3)) 465 continue; 466 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { 467 pm8001_ha->io_mem[logicalBar].membase = 468 pci_resource_start(pdev, bar); 469 pm8001_ha->io_mem[logicalBar].memsize = 470 pci_resource_len(pdev, bar); 471 pm8001_ha->io_mem[logicalBar].memvirtaddr = 472 ioremap(pm8001_ha->io_mem[logicalBar].membase, 473 pm8001_ha->io_mem[logicalBar].memsize); 474 if (!pm8001_ha->io_mem[logicalBar].memvirtaddr) { 475 pm8001_dbg(pm8001_ha, INIT, 476 "Failed to ioremap bar %d, logicalBar %d", 477 bar, logicalBar); 478 return -ENOMEM; 479 } 480 pm8001_dbg(pm8001_ha, INIT, 481 "base addr %llx virt_addr=%llx len=%d\n", 482 (u64)pm8001_ha->io_mem[logicalBar].membase, 483 (u64)(unsigned long) 484 pm8001_ha->io_mem[logicalBar].memvirtaddr, 485 pm8001_ha->io_mem[logicalBar].memsize); 486 } else { 487 pm8001_ha->io_mem[logicalBar].membase = 0; 488 pm8001_ha->io_mem[logicalBar].memsize = 0; 489 pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL; 490 } 491 logicalBar++; 492 } 493 return 0; 494 } 495 496 /** 497 * pm8001_pci_alloc - initialize our ha card structure 498 * @pdev: pci device. 499 * @ent: ent 500 * @shost: scsi host struct which has been initialized before. 501 */ 502 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev, 503 const struct pci_device_id *ent, 504 struct Scsi_Host *shost) 505 506 { 507 struct pm8001_hba_info *pm8001_ha; 508 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 509 int j; 510 511 pm8001_ha = sha->lldd_ha; 512 if (!pm8001_ha) 513 return NULL; 514 515 pm8001_ha->pdev = pdev; 516 pm8001_ha->dev = &pdev->dev; 517 pm8001_ha->chip_id = ent->driver_data; 518 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id]; 519 pm8001_ha->irq = pdev->irq; 520 pm8001_ha->sas = sha; 521 pm8001_ha->shost = shost; 522 pm8001_ha->id = pm8001_id++; 523 pm8001_ha->logging_level = logging_level; 524 pm8001_ha->non_fatal_count = 0; 525 if (link_rate >= 1 && link_rate <= 15) 526 pm8001_ha->link_rate = (link_rate << 8); 527 else { 528 pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 | 529 LINKRATE_60 | LINKRATE_120; 530 pm8001_dbg(pm8001_ha, FAIL, 531 "Setting link rate to default value\n"); 532 } 533 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id); 534 /* IOMB size is 128 for 8088/89 controllers */ 535 if (pm8001_ha->chip_id != chip_8001) 536 pm8001_ha->iomb_size = IOMB_SIZE_SPCV; 537 else 538 pm8001_ha->iomb_size = IOMB_SIZE_SPC; 539 540 #ifdef PM8001_USE_TASKLET 541 /* Tasklet for non msi-x interrupt handler */ 542 if ((!pdev->msix_cap || !pci_msi_enabled()) 543 || (pm8001_ha->chip_id == chip_8001)) 544 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet, 545 (unsigned long)&(pm8001_ha->irq_vector[0])); 546 else 547 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 548 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet, 549 (unsigned long)&(pm8001_ha->irq_vector[j])); 550 #endif 551 if (pm8001_ioremap(pm8001_ha)) 552 goto failed_pci_alloc; 553 if (!pm8001_alloc(pm8001_ha, ent)) 554 return pm8001_ha; 555 failed_pci_alloc: 556 pm8001_free(pm8001_ha); 557 return NULL; 558 } 559 560 /** 561 * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit 562 * @pdev: pci device. 563 */ 564 static int pci_go_44(struct pci_dev *pdev) 565 { 566 int rc; 567 568 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44)); 569 if (rc) { 570 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 571 if (rc) 572 dev_printk(KERN_ERR, &pdev->dev, 573 "32-bit DMA enable failed\n"); 574 } 575 return rc; 576 } 577 578 /** 579 * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them. 580 * @shost: scsi host which has been allocated outside. 581 * @chip_info: our ha struct. 582 */ 583 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost, 584 const struct pm8001_chip_info *chip_info) 585 { 586 int phy_nr, port_nr; 587 struct asd_sas_phy **arr_phy; 588 struct asd_sas_port **arr_port; 589 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 590 591 phy_nr = chip_info->n_phy; 592 port_nr = phy_nr; 593 memset(sha, 0x00, sizeof(*sha)); 594 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL); 595 if (!arr_phy) 596 goto exit; 597 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL); 598 if (!arr_port) 599 goto exit_free2; 600 601 sha->sas_phy = arr_phy; 602 sha->sas_port = arr_port; 603 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL); 604 if (!sha->lldd_ha) 605 goto exit_free1; 606 607 shost->transportt = pm8001_stt; 608 shost->max_id = PM8001_MAX_DEVICES; 609 shost->max_lun = 8; 610 shost->max_channel = 0; 611 shost->unique_id = pm8001_id; 612 shost->max_cmd_len = 16; 613 shost->can_queue = PM8001_CAN_QUEUE; 614 shost->cmd_per_lun = 32; 615 return 0; 616 exit_free1: 617 kfree(arr_port); 618 exit_free2: 619 kfree(arr_phy); 620 exit: 621 return -1; 622 } 623 624 /** 625 * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas 626 * @shost: scsi host which has been allocated outside 627 * @chip_info: our ha struct. 628 */ 629 static void pm8001_post_sas_ha_init(struct Scsi_Host *shost, 630 const struct pm8001_chip_info *chip_info) 631 { 632 int i = 0; 633 struct pm8001_hba_info *pm8001_ha; 634 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 635 636 pm8001_ha = sha->lldd_ha; 637 for (i = 0; i < chip_info->n_phy; i++) { 638 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy; 639 sha->sas_port[i] = &pm8001_ha->port[i].sas_port; 640 sha->sas_phy[i]->sas_addr = 641 (u8 *)&pm8001_ha->phy[i].dev_sas_addr; 642 } 643 sha->sas_ha_name = DRV_NAME; 644 sha->dev = pm8001_ha->dev; 645 sha->strict_wide_ports = 1; 646 sha->lldd_module = THIS_MODULE; 647 sha->sas_addr = &pm8001_ha->sas_addr[0]; 648 sha->num_phys = chip_info->n_phy; 649 sha->core.shost = shost; 650 } 651 652 /** 653 * pm8001_init_sas_add - initialize sas address 654 * @pm8001_ha: our ha struct. 655 * 656 * Currently we just set the fixed SAS address to our HBA, for manufacture, 657 * it should read from the EEPROM 658 */ 659 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha) 660 { 661 u8 i, j; 662 u8 sas_add[8]; 663 #ifdef PM8001_READ_VPD 664 /* For new SPC controllers WWN is stored in flash vpd 665 * For SPC/SPCve controllers WWN is stored in EEPROM 666 * For Older SPC WWN is stored in NVMD 667 */ 668 DECLARE_COMPLETION_ONSTACK(completion); 669 struct pm8001_ioctl_payload payload; 670 u16 deviceid; 671 int rc; 672 673 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid); 674 pm8001_ha->nvmd_completion = &completion; 675 676 if (pm8001_ha->chip_id == chip_8001) { 677 if (deviceid == 0x8081 || deviceid == 0x0042) { 678 payload.minor_function = 4; 679 payload.rd_length = 4096; 680 } else { 681 payload.minor_function = 0; 682 payload.rd_length = 128; 683 } 684 } else if ((pm8001_ha->chip_id == chip_8070 || 685 pm8001_ha->chip_id == chip_8072) && 686 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) { 687 payload.minor_function = 4; 688 payload.rd_length = 4096; 689 } else { 690 payload.minor_function = 1; 691 payload.rd_length = 4096; 692 } 693 payload.offset = 0; 694 payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL); 695 if (!payload.func_specific) { 696 pm8001_dbg(pm8001_ha, INIT, "mem alloc fail\n"); 697 return; 698 } 699 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload); 700 if (rc) { 701 kfree(payload.func_specific); 702 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n"); 703 return; 704 } 705 wait_for_completion(&completion); 706 707 for (i = 0, j = 0; i <= 7; i++, j++) { 708 if (pm8001_ha->chip_id == chip_8001) { 709 if (deviceid == 0x8081) 710 pm8001_ha->sas_addr[j] = 711 payload.func_specific[0x704 + i]; 712 else if (deviceid == 0x0042) 713 pm8001_ha->sas_addr[j] = 714 payload.func_specific[0x010 + i]; 715 } else if ((pm8001_ha->chip_id == chip_8070 || 716 pm8001_ha->chip_id == chip_8072) && 717 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) { 718 pm8001_ha->sas_addr[j] = 719 payload.func_specific[0x010 + i]; 720 } else 721 pm8001_ha->sas_addr[j] = 722 payload.func_specific[0x804 + i]; 723 } 724 memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE); 725 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 726 if (i && ((i % 4) == 0)) 727 sas_add[7] = sas_add[7] + 4; 728 memcpy(&pm8001_ha->phy[i].dev_sas_addr, 729 sas_add, SAS_ADDR_SIZE); 730 pm8001_dbg(pm8001_ha, INIT, "phy %d sas_addr = %016llx\n", i, 731 pm8001_ha->phy[i].dev_sas_addr); 732 } 733 kfree(payload.func_specific); 734 #else 735 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 736 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL; 737 pm8001_ha->phy[i].dev_sas_addr = 738 cpu_to_be64((u64) 739 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr)); 740 } 741 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr, 742 SAS_ADDR_SIZE); 743 #endif 744 } 745 746 /* 747 * pm8001_get_phy_settings_info : Read phy setting values. 748 * @pm8001_ha : our hba. 749 */ 750 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha) 751 { 752 753 #ifdef PM8001_READ_VPD 754 /*OPTION ROM FLASH read for the SPC cards */ 755 DECLARE_COMPLETION_ONSTACK(completion); 756 struct pm8001_ioctl_payload payload; 757 int rc; 758 759 pm8001_ha->nvmd_completion = &completion; 760 /* SAS ADDRESS read from flash / EEPROM */ 761 payload.minor_function = 6; 762 payload.offset = 0; 763 payload.rd_length = 4096; 764 payload.func_specific = kzalloc(4096, GFP_KERNEL); 765 if (!payload.func_specific) 766 return -ENOMEM; 767 /* Read phy setting values from flash */ 768 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload); 769 if (rc) { 770 kfree(payload.func_specific); 771 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n"); 772 return -ENOMEM; 773 } 774 wait_for_completion(&completion); 775 pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific); 776 kfree(payload.func_specific); 777 #endif 778 return 0; 779 } 780 781 struct pm8001_mpi3_phy_pg_trx_config { 782 u32 LaneLosCfg; 783 u32 LanePgaCfg1; 784 u32 LanePisoCfg1; 785 u32 LanePisoCfg2; 786 u32 LanePisoCfg3; 787 u32 LanePisoCfg4; 788 u32 LanePisoCfg5; 789 u32 LanePisoCfg6; 790 u32 LaneBctCtrl; 791 }; 792 793 /** 794 * pm8001_get_internal_phy_settings - Retrieves the internal PHY settings 795 * @pm8001_ha : our adapter 796 * @phycfg : PHY config page to populate 797 */ 798 static 799 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha, 800 struct pm8001_mpi3_phy_pg_trx_config *phycfg) 801 { 802 phycfg->LaneLosCfg = 0x00000132; 803 phycfg->LanePgaCfg1 = 0x00203949; 804 phycfg->LanePisoCfg1 = 0x000000FF; 805 phycfg->LanePisoCfg2 = 0xFF000001; 806 phycfg->LanePisoCfg3 = 0xE7011300; 807 phycfg->LanePisoCfg4 = 0x631C40C0; 808 phycfg->LanePisoCfg5 = 0xF8102036; 809 phycfg->LanePisoCfg6 = 0xF74A1000; 810 phycfg->LaneBctCtrl = 0x00FB33F8; 811 } 812 813 /** 814 * pm8001_get_external_phy_settings - Retrieves the external PHY settings 815 * @pm8001_ha : our adapter 816 * @phycfg : PHY config page to populate 817 */ 818 static 819 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha, 820 struct pm8001_mpi3_phy_pg_trx_config *phycfg) 821 { 822 phycfg->LaneLosCfg = 0x00000132; 823 phycfg->LanePgaCfg1 = 0x00203949; 824 phycfg->LanePisoCfg1 = 0x000000FF; 825 phycfg->LanePisoCfg2 = 0xFF000001; 826 phycfg->LanePisoCfg3 = 0xE7011300; 827 phycfg->LanePisoCfg4 = 0x63349140; 828 phycfg->LanePisoCfg5 = 0xF8102036; 829 phycfg->LanePisoCfg6 = 0xF80D9300; 830 phycfg->LaneBctCtrl = 0x00FB33F8; 831 } 832 833 /** 834 * pm8001_get_phy_mask - Retrieves the mask that denotes if a PHY is int/ext 835 * @pm8001_ha : our adapter 836 * @phymask : The PHY mask 837 */ 838 static 839 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask) 840 { 841 switch (pm8001_ha->pdev->subsystem_device) { 842 case 0x0070: /* H1280 - 8 external 0 internal */ 843 case 0x0072: /* H12F0 - 16 external 0 internal */ 844 *phymask = 0x0000; 845 break; 846 847 case 0x0071: /* H1208 - 0 external 8 internal */ 848 case 0x0073: /* H120F - 0 external 16 internal */ 849 *phymask = 0xFFFF; 850 break; 851 852 case 0x0080: /* H1244 - 4 external 4 internal */ 853 *phymask = 0x00F0; 854 break; 855 856 case 0x0081: /* H1248 - 4 external 8 internal */ 857 *phymask = 0x0FF0; 858 break; 859 860 case 0x0082: /* H1288 - 8 external 8 internal */ 861 *phymask = 0xFF00; 862 break; 863 864 default: 865 pm8001_dbg(pm8001_ha, INIT, 866 "Unknown subsystem device=0x%.04x\n", 867 pm8001_ha->pdev->subsystem_device); 868 } 869 } 870 871 /** 872 * pm8001_set_phy_settings_ven_117c_12G() - Configure ATTO 12Gb PHY settings 873 * @pm8001_ha : our adapter 874 */ 875 static 876 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha) 877 { 878 struct pm8001_mpi3_phy_pg_trx_config phycfg_int; 879 struct pm8001_mpi3_phy_pg_trx_config phycfg_ext; 880 int phymask = 0; 881 int i = 0; 882 883 memset(&phycfg_int, 0, sizeof(phycfg_int)); 884 memset(&phycfg_ext, 0, sizeof(phycfg_ext)); 885 886 pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int); 887 pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext); 888 pm8001_get_phy_mask(pm8001_ha, &phymask); 889 890 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 891 if (phymask & (1 << i)) {/* Internal PHY */ 892 pm8001_set_phy_profile_single(pm8001_ha, i, 893 sizeof(phycfg_int) / sizeof(u32), 894 (u32 *)&phycfg_int); 895 896 } else { /* External PHY */ 897 pm8001_set_phy_profile_single(pm8001_ha, i, 898 sizeof(phycfg_ext) / sizeof(u32), 899 (u32 *)&phycfg_ext); 900 } 901 } 902 903 return 0; 904 } 905 906 /** 907 * pm8001_configure_phy_settings - Configures PHY settings based on vendor ID. 908 * @pm8001_ha : our hba. 909 */ 910 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha) 911 { 912 switch (pm8001_ha->pdev->subsystem_vendor) { 913 case PCI_VENDOR_ID_ATTO: 914 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */ 915 return 0; 916 else 917 return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha); 918 919 case PCI_VENDOR_ID_ADAPTEC2: 920 case 0: 921 return 0; 922 923 default: 924 return pm8001_get_phy_settings_info(pm8001_ha); 925 } 926 } 927 928 #ifdef PM8001_USE_MSIX 929 /** 930 * pm8001_setup_msix - enable MSI-X interrupt 931 * @pm8001_ha: our ha struct. 932 */ 933 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha) 934 { 935 u32 number_of_intr; 936 int rc, cpu_online_count; 937 unsigned int allocated_irq_vectors; 938 939 /* SPCv controllers supports 64 msi-x */ 940 if (pm8001_ha->chip_id == chip_8001) { 941 number_of_intr = 1; 942 } else { 943 number_of_intr = PM8001_MAX_MSIX_VEC; 944 } 945 946 cpu_online_count = num_online_cpus(); 947 number_of_intr = min_t(int, cpu_online_count, number_of_intr); 948 rc = pci_alloc_irq_vectors(pm8001_ha->pdev, number_of_intr, 949 number_of_intr, PCI_IRQ_MSIX); 950 allocated_irq_vectors = rc; 951 if (rc < 0) 952 return rc; 953 954 /* Assigns the number of interrupts */ 955 number_of_intr = min_t(int, allocated_irq_vectors, number_of_intr); 956 pm8001_ha->number_of_intr = number_of_intr; 957 958 /* Maximum queue number updating in HBA structure */ 959 pm8001_ha->max_q_num = number_of_intr; 960 961 pm8001_dbg(pm8001_ha, INIT, 962 "pci_alloc_irq_vectors request ret:%d no of intr %d\n", 963 rc, pm8001_ha->number_of_intr); 964 return 0; 965 } 966 967 static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha) 968 { 969 u32 i = 0, j = 0; 970 int flag = 0, rc = 0; 971 int nr_irqs = pm8001_ha->number_of_intr; 972 973 if (pm8001_ha->chip_id != chip_8001) 974 flag &= ~IRQF_SHARED; 975 976 pm8001_dbg(pm8001_ha, INIT, 977 "pci_enable_msix request number of intr %d\n", 978 pm8001_ha->number_of_intr); 979 980 if (nr_irqs > ARRAY_SIZE(pm8001_ha->intr_drvname)) 981 nr_irqs = ARRAY_SIZE(pm8001_ha->intr_drvname); 982 983 for (i = 0; i < nr_irqs; i++) { 984 snprintf(pm8001_ha->intr_drvname[i], 985 sizeof(pm8001_ha->intr_drvname[0]), 986 "%s-%d", pm8001_ha->name, i); 987 pm8001_ha->irq_vector[i].irq_id = i; 988 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha; 989 990 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i), 991 pm8001_interrupt_handler_msix, flag, 992 pm8001_ha->intr_drvname[i], 993 &(pm8001_ha->irq_vector[i])); 994 if (rc) { 995 for (j = 0; j < i; j++) { 996 free_irq(pci_irq_vector(pm8001_ha->pdev, i), 997 &(pm8001_ha->irq_vector[i])); 998 } 999 pci_free_irq_vectors(pm8001_ha->pdev); 1000 break; 1001 } 1002 } 1003 1004 return rc; 1005 } 1006 #endif 1007 1008 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha) 1009 { 1010 struct pci_dev *pdev; 1011 1012 pdev = pm8001_ha->pdev; 1013 1014 #ifdef PM8001_USE_MSIX 1015 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX)) 1016 return pm8001_setup_msix(pm8001_ha); 1017 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n"); 1018 #endif 1019 return 0; 1020 } 1021 1022 /** 1023 * pm8001_request_irq - register interrupt 1024 * @pm8001_ha: our ha struct. 1025 */ 1026 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha) 1027 { 1028 struct pci_dev *pdev; 1029 int rc; 1030 1031 pdev = pm8001_ha->pdev; 1032 1033 #ifdef PM8001_USE_MSIX 1034 if (pdev->msix_cap && pci_msi_enabled()) 1035 return pm8001_request_msix(pm8001_ha); 1036 else { 1037 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n"); 1038 goto intx; 1039 } 1040 #endif 1041 1042 intx: 1043 /* initialize the INT-X interrupt */ 1044 pm8001_ha->irq_vector[0].irq_id = 0; 1045 pm8001_ha->irq_vector[0].drv_inst = pm8001_ha; 1046 rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED, 1047 pm8001_ha->name, SHOST_TO_SAS_HA(pm8001_ha->shost)); 1048 return rc; 1049 } 1050 1051 /** 1052 * pm8001_pci_probe - probe supported device 1053 * @pdev: pci device which kernel has been prepared for. 1054 * @ent: pci device id 1055 * 1056 * This function is the main initialization function, when register a new 1057 * pci driver it is invoked, all struct and hardware initialization should be 1058 * done here, also, register interrupt. 1059 */ 1060 static int pm8001_pci_probe(struct pci_dev *pdev, 1061 const struct pci_device_id *ent) 1062 { 1063 unsigned int rc; 1064 u32 pci_reg; 1065 u8 i = 0; 1066 struct pm8001_hba_info *pm8001_ha; 1067 struct Scsi_Host *shost = NULL; 1068 const struct pm8001_chip_info *chip; 1069 struct sas_ha_struct *sha; 1070 1071 dev_printk(KERN_INFO, &pdev->dev, 1072 "pm80xx: driver version %s\n", DRV_VERSION); 1073 rc = pci_enable_device(pdev); 1074 if (rc) 1075 goto err_out_enable; 1076 pci_set_master(pdev); 1077 /* 1078 * Enable pci slot busmaster by setting pci command register. 1079 * This is required by FW for Cyclone card. 1080 */ 1081 1082 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg); 1083 pci_reg |= 0x157; 1084 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg); 1085 rc = pci_request_regions(pdev, DRV_NAME); 1086 if (rc) 1087 goto err_out_disable; 1088 rc = pci_go_44(pdev); 1089 if (rc) 1090 goto err_out_regions; 1091 1092 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *)); 1093 if (!shost) { 1094 rc = -ENOMEM; 1095 goto err_out_regions; 1096 } 1097 chip = &pm8001_chips[ent->driver_data]; 1098 sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL); 1099 if (!sha) { 1100 rc = -ENOMEM; 1101 goto err_out_free_host; 1102 } 1103 SHOST_TO_SAS_HA(shost) = sha; 1104 1105 rc = pm8001_prep_sas_ha_init(shost, chip); 1106 if (rc) { 1107 rc = -ENOMEM; 1108 goto err_out_free; 1109 } 1110 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost)); 1111 /* ent->driver variable is used to differentiate between controllers */ 1112 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost); 1113 if (!pm8001_ha) { 1114 rc = -ENOMEM; 1115 goto err_out_free; 1116 } 1117 1118 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1119 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); 1120 if (rc) { 1121 pm8001_dbg(pm8001_ha, FAIL, 1122 "chip_init failed [ret: %d]\n", rc); 1123 goto err_out_ha_free; 1124 } 1125 1126 rc = pm8001_init_ccb_tag(pm8001_ha, shost, pdev); 1127 if (rc) 1128 goto err_out_enable; 1129 1130 rc = scsi_add_host(shost, &pdev->dev); 1131 if (rc) 1132 goto err_out_ha_free; 1133 1134 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0); 1135 if (pm8001_ha->chip_id != chip_8001) { 1136 for (i = 1; i < pm8001_ha->number_of_intr; i++) 1137 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i); 1138 /* setup thermal configuration. */ 1139 pm80xx_set_thermal_config(pm8001_ha); 1140 } 1141 1142 pm8001_init_sas_add(pm8001_ha); 1143 /* phy setting support for motherboard controller */ 1144 rc = pm8001_configure_phy_settings(pm8001_ha); 1145 if (rc) 1146 goto err_out_shost; 1147 1148 pm8001_post_sas_ha_init(shost, chip); 1149 rc = sas_register_ha(SHOST_TO_SAS_HA(shost)); 1150 if (rc) { 1151 pm8001_dbg(pm8001_ha, FAIL, 1152 "sas_register_ha failed [ret: %d]\n", rc); 1153 goto err_out_shost; 1154 } 1155 list_add_tail(&pm8001_ha->list, &hba_list); 1156 pm8001_ha->flags = PM8001F_RUN_TIME; 1157 scsi_scan_host(pm8001_ha->shost); 1158 return 0; 1159 1160 err_out_shost: 1161 scsi_remove_host(pm8001_ha->shost); 1162 err_out_ha_free: 1163 pm8001_free(pm8001_ha); 1164 err_out_free: 1165 kfree(sha); 1166 err_out_free_host: 1167 scsi_host_put(shost); 1168 err_out_regions: 1169 pci_release_regions(pdev); 1170 err_out_disable: 1171 pci_disable_device(pdev); 1172 err_out_enable: 1173 return rc; 1174 } 1175 1176 /** 1177 * pm8001_init_ccb_tag - allocate memory to CCB and tag. 1178 * @pm8001_ha: our hba card information. 1179 * @shost: scsi host which has been allocated outside. 1180 * @pdev: pci device. 1181 */ 1182 static int 1183 pm8001_init_ccb_tag(struct pm8001_hba_info *pm8001_ha, struct Scsi_Host *shost, 1184 struct pci_dev *pdev) 1185 { 1186 int i = 0; 1187 u32 max_out_io, ccb_count; 1188 u32 can_queue; 1189 1190 max_out_io = pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io; 1191 ccb_count = min_t(int, PM8001_MAX_CCB, max_out_io); 1192 1193 /* Update to the scsi host*/ 1194 can_queue = ccb_count - PM8001_RESERVE_SLOT; 1195 shost->can_queue = can_queue; 1196 1197 pm8001_ha->tags = kzalloc(ccb_count, GFP_KERNEL); 1198 if (!pm8001_ha->tags) 1199 goto err_out; 1200 1201 /* Memory region for ccb_info*/ 1202 pm8001_ha->ccb_count = ccb_count; 1203 pm8001_ha->ccb_info = 1204 kcalloc(ccb_count, sizeof(struct pm8001_ccb_info), GFP_KERNEL); 1205 if (!pm8001_ha->ccb_info) { 1206 pm8001_dbg(pm8001_ha, FAIL, 1207 "Unable to allocate memory for ccb\n"); 1208 goto err_out_noccb; 1209 } 1210 for (i = 0; i < ccb_count; i++) { 1211 pm8001_ha->ccb_info[i].buf_prd = dma_alloc_coherent(&pdev->dev, 1212 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG, 1213 &pm8001_ha->ccb_info[i].ccb_dma_handle, 1214 GFP_KERNEL); 1215 if (!pm8001_ha->ccb_info[i].buf_prd) { 1216 pm8001_dbg(pm8001_ha, FAIL, 1217 "ccb prd memory allocation error\n"); 1218 goto err_out; 1219 } 1220 pm8001_ha->ccb_info[i].task = NULL; 1221 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff; 1222 pm8001_ha->ccb_info[i].device = NULL; 1223 ++pm8001_ha->tags_num; 1224 } 1225 return 0; 1226 1227 err_out_noccb: 1228 kfree(pm8001_ha->devices); 1229 err_out: 1230 return -ENOMEM; 1231 } 1232 1233 static void pm8001_pci_remove(struct pci_dev *pdev) 1234 { 1235 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1236 struct pm8001_hba_info *pm8001_ha; 1237 int i, j; 1238 pm8001_ha = sha->lldd_ha; 1239 sas_unregister_ha(sha); 1240 sas_remove_host(pm8001_ha->shost); 1241 list_del(&pm8001_ha->list); 1242 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1243 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1244 1245 #ifdef PM8001_USE_MSIX 1246 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1247 synchronize_irq(pci_irq_vector(pdev, i)); 1248 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1249 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]); 1250 pci_free_irq_vectors(pdev); 1251 #else 1252 free_irq(pm8001_ha->irq, sha); 1253 #endif 1254 #ifdef PM8001_USE_TASKLET 1255 /* For non-msix and msix interrupts */ 1256 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1257 (pm8001_ha->chip_id == chip_8001)) 1258 tasklet_kill(&pm8001_ha->tasklet[0]); 1259 else 1260 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1261 tasklet_kill(&pm8001_ha->tasklet[j]); 1262 #endif 1263 scsi_host_put(pm8001_ha->shost); 1264 1265 for (i = 0; i < pm8001_ha->ccb_count; i++) { 1266 dma_free_coherent(&pm8001_ha->pdev->dev, 1267 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG, 1268 pm8001_ha->ccb_info[i].buf_prd, 1269 pm8001_ha->ccb_info[i].ccb_dma_handle); 1270 } 1271 kfree(pm8001_ha->ccb_info); 1272 kfree(pm8001_ha->devices); 1273 1274 pm8001_free(pm8001_ha); 1275 kfree(sha->sas_phy); 1276 kfree(sha->sas_port); 1277 kfree(sha); 1278 pci_release_regions(pdev); 1279 pci_disable_device(pdev); 1280 } 1281 1282 /** 1283 * pm8001_pci_suspend - power management suspend main entry point 1284 * @dev: Device struct 1285 * 1286 * Return: 0 on success, anything else on error. 1287 */ 1288 static int __maybe_unused pm8001_pci_suspend(struct device *dev) 1289 { 1290 struct pci_dev *pdev = to_pci_dev(dev); 1291 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1292 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 1293 int i, j; 1294 sas_suspend_ha(sha); 1295 flush_workqueue(pm8001_wq); 1296 scsi_block_requests(pm8001_ha->shost); 1297 if (!pdev->pm_cap) { 1298 dev_err(dev, " PCI PM not supported\n"); 1299 return -ENODEV; 1300 } 1301 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1302 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1303 #ifdef PM8001_USE_MSIX 1304 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1305 synchronize_irq(pci_irq_vector(pdev, i)); 1306 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1307 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]); 1308 pci_free_irq_vectors(pdev); 1309 #else 1310 free_irq(pm8001_ha->irq, sha); 1311 #endif 1312 #ifdef PM8001_USE_TASKLET 1313 /* For non-msix and msix interrupts */ 1314 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1315 (pm8001_ha->chip_id == chip_8001)) 1316 tasklet_kill(&pm8001_ha->tasklet[0]); 1317 else 1318 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1319 tasklet_kill(&pm8001_ha->tasklet[j]); 1320 #endif 1321 pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, entering " 1322 "suspended state\n", pdev, 1323 pm8001_ha->name); 1324 return 0; 1325 } 1326 1327 /** 1328 * pm8001_pci_resume - power management resume main entry point 1329 * @dev: Device struct 1330 * 1331 * Return: 0 on success, anything else on error. 1332 */ 1333 static int __maybe_unused pm8001_pci_resume(struct device *dev) 1334 { 1335 struct pci_dev *pdev = to_pci_dev(dev); 1336 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1337 struct pm8001_hba_info *pm8001_ha; 1338 int rc; 1339 u8 i = 0, j; 1340 u32 device_state; 1341 DECLARE_COMPLETION_ONSTACK(completion); 1342 pm8001_ha = sha->lldd_ha; 1343 device_state = pdev->current_state; 1344 1345 pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, resuming from previous operating state [D%d]\n", 1346 pdev, pm8001_ha->name, device_state); 1347 1348 rc = pci_go_44(pdev); 1349 if (rc) 1350 goto err_out_disable; 1351 sas_prep_resume_ha(sha); 1352 /* chip soft rst only for spc */ 1353 if (pm8001_ha->chip_id == chip_8001) { 1354 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1355 pm8001_dbg(pm8001_ha, INIT, "chip soft reset successful\n"); 1356 } 1357 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); 1358 if (rc) 1359 goto err_out_disable; 1360 1361 /* disable all the interrupt bits */ 1362 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1363 1364 rc = pm8001_request_irq(pm8001_ha); 1365 if (rc) 1366 goto err_out_disable; 1367 #ifdef PM8001_USE_TASKLET 1368 /* Tasklet for non msi-x interrupt handler */ 1369 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1370 (pm8001_ha->chip_id == chip_8001)) 1371 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet, 1372 (unsigned long)&(pm8001_ha->irq_vector[0])); 1373 else 1374 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1375 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet, 1376 (unsigned long)&(pm8001_ha->irq_vector[j])); 1377 #endif 1378 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0); 1379 if (pm8001_ha->chip_id != chip_8001) { 1380 for (i = 1; i < pm8001_ha->number_of_intr; i++) 1381 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i); 1382 } 1383 1384 /* Chip documentation for the 8070 and 8072 SPCv */ 1385 /* states that a 500ms minimum delay is required */ 1386 /* before issuing commands. Otherwise, the firmware */ 1387 /* will enter an unrecoverable state. */ 1388 1389 if (pm8001_ha->chip_id == chip_8070 || 1390 pm8001_ha->chip_id == chip_8072) { 1391 mdelay(500); 1392 } 1393 1394 /* Spin up the PHYs */ 1395 1396 pm8001_ha->flags = PM8001F_RUN_TIME; 1397 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 1398 pm8001_ha->phy[i].enable_completion = &completion; 1399 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i); 1400 wait_for_completion(&completion); 1401 } 1402 sas_resume_ha(sha); 1403 return 0; 1404 1405 err_out_disable: 1406 scsi_remove_host(pm8001_ha->shost); 1407 1408 return rc; 1409 } 1410 1411 /* update of pci device, vendor id and driver data with 1412 * unique value for each of the controller 1413 */ 1414 static struct pci_device_id pm8001_pci_table[] = { 1415 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 }, 1416 { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 }, 1417 { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 }, 1418 { PCI_VDEVICE(ATTO, 0x0042), chip_8001 }, 1419 /* Support for SPC/SPCv/SPCve controllers */ 1420 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 }, 1421 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 }, 1422 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 }, 1423 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 }, 1424 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 }, 1425 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 }, 1426 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 }, 1427 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 }, 1428 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 }, 1429 { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 }, 1430 { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 }, 1431 { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 }, 1432 { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 }, 1433 { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 }, 1434 { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 }, 1435 { PCI_VENDOR_ID_ADAPTEC2, 0x8081, 1436 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 }, 1437 { PCI_VENDOR_ID_ADAPTEC2, 0x8081, 1438 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 }, 1439 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1440 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 }, 1441 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1442 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 }, 1443 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1444 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 }, 1445 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1446 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 }, 1447 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1448 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 }, 1449 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1450 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 }, 1451 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1452 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 }, 1453 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1454 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 }, 1455 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1456 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 }, 1457 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1458 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 }, 1459 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1460 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 }, 1461 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1462 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 }, 1463 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1464 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 }, 1465 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1466 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 }, 1467 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1468 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 }, 1469 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1470 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 }, 1471 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1472 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 }, 1473 { PCI_VENDOR_ID_ATTO, 0x8070, 1474 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 }, 1475 { PCI_VENDOR_ID_ATTO, 0x8070, 1476 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 }, 1477 { PCI_VENDOR_ID_ATTO, 0x8072, 1478 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 }, 1479 { PCI_VENDOR_ID_ATTO, 0x8072, 1480 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 }, 1481 { PCI_VENDOR_ID_ATTO, 0x8070, 1482 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 }, 1483 { PCI_VENDOR_ID_ATTO, 0x8072, 1484 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 }, 1485 { PCI_VENDOR_ID_ATTO, 0x8072, 1486 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 }, 1487 {} /* terminate list */ 1488 }; 1489 1490 static SIMPLE_DEV_PM_OPS(pm8001_pci_pm_ops, 1491 pm8001_pci_suspend, 1492 pm8001_pci_resume); 1493 1494 static struct pci_driver pm8001_pci_driver = { 1495 .name = DRV_NAME, 1496 .id_table = pm8001_pci_table, 1497 .probe = pm8001_pci_probe, 1498 .remove = pm8001_pci_remove, 1499 .driver.pm = &pm8001_pci_pm_ops, 1500 }; 1501 1502 /** 1503 * pm8001_init - initialize scsi transport template 1504 */ 1505 static int __init pm8001_init(void) 1506 { 1507 int rc = -ENOMEM; 1508 1509 pm8001_wq = alloc_workqueue("pm80xx", 0, 0); 1510 if (!pm8001_wq) 1511 goto err; 1512 1513 pm8001_id = 0; 1514 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops); 1515 if (!pm8001_stt) 1516 goto err_wq; 1517 rc = pci_register_driver(&pm8001_pci_driver); 1518 if (rc) 1519 goto err_tp; 1520 return 0; 1521 1522 err_tp: 1523 sas_release_transport(pm8001_stt); 1524 err_wq: 1525 destroy_workqueue(pm8001_wq); 1526 err: 1527 return rc; 1528 } 1529 1530 static void __exit pm8001_exit(void) 1531 { 1532 pci_unregister_driver(&pm8001_pci_driver); 1533 sas_release_transport(pm8001_stt); 1534 destroy_workqueue(pm8001_wq); 1535 } 1536 1537 module_init(pm8001_init); 1538 module_exit(pm8001_exit); 1539 1540 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>"); 1541 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>"); 1542 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>"); 1543 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>"); 1544 MODULE_DESCRIPTION( 1545 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 " 1546 "SAS/SATA controller driver"); 1547 MODULE_VERSION(DRV_VERSION); 1548 MODULE_LICENSE("GPL"); 1549 MODULE_DEVICE_TABLE(pci, pm8001_pci_table); 1550 1551