1 /* 2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 USI Co., Ltd. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 41 #include <linux/slab.h> 42 #include "pm8001_sas.h" 43 #include "pm8001_chips.h" 44 #include "pm80xx_hwi.h" 45 46 static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING | 47 PM8001_EVENT_LOGGING | PM8001_INIT_LOGGING; 48 module_param(logging_level, ulong, 0644); 49 MODULE_PARM_DESC(logging_level, " bits for enabling logging info."); 50 51 static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120; 52 module_param(link_rate, ulong, 0644); 53 MODULE_PARM_DESC(link_rate, "Enable link rate.\n" 54 " 1: Link rate 1.5G\n" 55 " 2: Link rate 3.0G\n" 56 " 4: Link rate 6.0G\n" 57 " 8: Link rate 12.0G\n"); 58 59 static struct scsi_transport_template *pm8001_stt; 60 static int pm8001_init_ccb_tag(struct pm8001_hba_info *); 61 62 /* 63 * chip info structure to identify chip key functionality as 64 * encryption available/not, no of ports, hw specific function ref 65 */ 66 static const struct pm8001_chip_info pm8001_chips[] = { 67 [chip_8001] = {0, 8, &pm8001_8001_dispatch,}, 68 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,}, 69 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,}, 70 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,}, 71 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,}, 72 [chip_8074] = {0, 8, &pm8001_80xx_dispatch,}, 73 [chip_8076] = {0, 16, &pm8001_80xx_dispatch,}, 74 [chip_8077] = {0, 16, &pm8001_80xx_dispatch,}, 75 [chip_8006] = {0, 16, &pm8001_80xx_dispatch,}, 76 [chip_8070] = {0, 8, &pm8001_80xx_dispatch,}, 77 [chip_8072] = {0, 16, &pm8001_80xx_dispatch,}, 78 }; 79 static int pm8001_id; 80 81 LIST_HEAD(hba_list); 82 83 struct workqueue_struct *pm8001_wq; 84 85 static void pm8001_map_queues(struct Scsi_Host *shost) 86 { 87 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 88 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 89 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT]; 90 91 if (pm8001_ha->number_of_intr > 1) { 92 blk_mq_pci_map_queues(qmap, pm8001_ha->pdev, 1); 93 return; 94 } 95 96 blk_mq_map_queues(qmap); 97 } 98 99 /* 100 * The main structure which LLDD must register for scsi core. 101 */ 102 static const struct scsi_host_template pm8001_sht = { 103 .module = THIS_MODULE, 104 .name = DRV_NAME, 105 .proc_name = DRV_NAME, 106 .queuecommand = sas_queuecommand, 107 .dma_need_drain = ata_scsi_dma_need_drain, 108 .target_alloc = sas_target_alloc, 109 .slave_configure = sas_slave_configure, 110 .scan_finished = pm8001_scan_finished, 111 .scan_start = pm8001_scan_start, 112 .change_queue_depth = sas_change_queue_depth, 113 .bios_param = sas_bios_param, 114 .can_queue = 1, 115 .this_id = -1, 116 .sg_tablesize = PM8001_MAX_DMA_SG, 117 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 118 .eh_device_reset_handler = sas_eh_device_reset_handler, 119 .eh_target_reset_handler = sas_eh_target_reset_handler, 120 .slave_alloc = sas_slave_alloc, 121 .target_destroy = sas_target_destroy, 122 .ioctl = sas_ioctl, 123 #ifdef CONFIG_COMPAT 124 .compat_ioctl = sas_ioctl, 125 #endif 126 .shost_groups = pm8001_host_groups, 127 .track_queue_depth = 1, 128 .cmd_per_lun = 32, 129 .map_queues = pm8001_map_queues, 130 }; 131 132 /* 133 * Sas layer call this function to execute specific task. 134 */ 135 static struct sas_domain_function_template pm8001_transport_ops = { 136 .lldd_dev_found = pm8001_dev_found, 137 .lldd_dev_gone = pm8001_dev_gone, 138 139 .lldd_execute_task = pm8001_queue_command, 140 .lldd_control_phy = pm8001_phy_control, 141 142 .lldd_abort_task = pm8001_abort_task, 143 .lldd_abort_task_set = sas_abort_task_set, 144 .lldd_clear_task_set = pm8001_clear_task_set, 145 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset, 146 .lldd_lu_reset = pm8001_lu_reset, 147 .lldd_query_task = pm8001_query_task, 148 .lldd_port_formed = pm8001_port_formed, 149 .lldd_tmf_exec_complete = pm8001_setds_completion, 150 .lldd_tmf_aborted = pm8001_tmf_aborted, 151 }; 152 153 /** 154 * pm8001_phy_init - initiate our adapter phys 155 * @pm8001_ha: our hba structure. 156 * @phy_id: phy id. 157 */ 158 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id) 159 { 160 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 161 struct asd_sas_phy *sas_phy = &phy->sas_phy; 162 phy->phy_state = PHY_LINK_DISABLE; 163 phy->pm8001_ha = pm8001_ha; 164 phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS; 165 phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS; 166 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0; 167 sas_phy->iproto = SAS_PROTOCOL_ALL; 168 sas_phy->tproto = 0; 169 sas_phy->role = PHY_ROLE_INITIATOR; 170 sas_phy->oob_mode = OOB_NOT_CONNECTED; 171 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN; 172 sas_phy->id = phy_id; 173 sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr; 174 sas_phy->frame_rcvd = &phy->frame_rcvd[0]; 175 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata; 176 sas_phy->lldd_phy = phy; 177 } 178 179 /** 180 * pm8001_free - free hba 181 * @pm8001_ha: our hba structure. 182 */ 183 static void pm8001_free(struct pm8001_hba_info *pm8001_ha) 184 { 185 int i; 186 187 if (!pm8001_ha) 188 return; 189 190 for (i = 0; i < USI_MAX_MEMCNT; i++) { 191 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) { 192 dma_free_coherent(&pm8001_ha->pdev->dev, 193 (pm8001_ha->memoryMap.region[i].total_len + 194 pm8001_ha->memoryMap.region[i].alignment), 195 pm8001_ha->memoryMap.region[i].virt_ptr, 196 pm8001_ha->memoryMap.region[i].phys_addr); 197 } 198 } 199 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha); 200 flush_workqueue(pm8001_wq); 201 bitmap_free(pm8001_ha->rsvd_tags); 202 kfree(pm8001_ha); 203 } 204 205 #ifdef PM8001_USE_TASKLET 206 207 /** 208 * pm8001_tasklet() - tasklet for 64 msi-x interrupt handler 209 * @opaque: the passed general host adapter struct 210 * Note: pm8001_tasklet is common for pm8001 & pm80xx 211 */ 212 static void pm8001_tasklet(unsigned long opaque) 213 { 214 struct pm8001_hba_info *pm8001_ha; 215 struct isr_param *irq_vector; 216 217 irq_vector = (struct isr_param *)opaque; 218 pm8001_ha = irq_vector->drv_inst; 219 if (unlikely(!pm8001_ha)) 220 BUG_ON(1); 221 PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id); 222 } 223 #endif 224 225 /** 226 * pm8001_interrupt_handler_msix - main MSIX interrupt handler. 227 * It obtains the vector number and calls the equivalent bottom 228 * half or services directly. 229 * @irq: interrupt number 230 * @opaque: the passed outbound queue/vector. Host structure is 231 * retrieved from the same. 232 */ 233 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque) 234 { 235 struct isr_param *irq_vector; 236 struct pm8001_hba_info *pm8001_ha; 237 irqreturn_t ret = IRQ_HANDLED; 238 irq_vector = (struct isr_param *)opaque; 239 pm8001_ha = irq_vector->drv_inst; 240 241 if (unlikely(!pm8001_ha)) 242 return IRQ_NONE; 243 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha)) 244 return IRQ_NONE; 245 #ifdef PM8001_USE_TASKLET 246 tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]); 247 #else 248 ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id); 249 #endif 250 return ret; 251 } 252 253 /** 254 * pm8001_interrupt_handler_intx - main INTx interrupt handler. 255 * @irq: interrupt number 256 * @dev_id: sas_ha structure. The HBA is retrieved from sas_ha structure. 257 */ 258 259 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id) 260 { 261 struct pm8001_hba_info *pm8001_ha; 262 irqreturn_t ret = IRQ_HANDLED; 263 struct sas_ha_struct *sha = dev_id; 264 pm8001_ha = sha->lldd_ha; 265 if (unlikely(!pm8001_ha)) 266 return IRQ_NONE; 267 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha)) 268 return IRQ_NONE; 269 270 #ifdef PM8001_USE_TASKLET 271 tasklet_schedule(&pm8001_ha->tasklet[0]); 272 #else 273 ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0); 274 #endif 275 return ret; 276 } 277 278 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha); 279 280 /** 281 * pm8001_alloc - initiate our hba structure and 6 DMAs area. 282 * @pm8001_ha: our hba structure. 283 * @ent: PCI device ID structure to match on 284 */ 285 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha, 286 const struct pci_device_id *ent) 287 { 288 int i, count = 0, rc = 0; 289 u32 ci_offset, ib_offset, ob_offset, pi_offset; 290 struct inbound_queue_table *ibq; 291 struct outbound_queue_table *obq; 292 293 spin_lock_init(&pm8001_ha->lock); 294 spin_lock_init(&pm8001_ha->bitmap_lock); 295 pm8001_dbg(pm8001_ha, INIT, "pm8001_alloc: PHY:%x\n", 296 pm8001_ha->chip->n_phy); 297 298 /* Request Interrupt */ 299 rc = pm8001_request_irq(pm8001_ha); 300 if (rc) 301 goto err_out; 302 303 count = pm8001_ha->max_q_num; 304 /* Queues are chosen based on the number of cores/msix availability */ 305 ib_offset = pm8001_ha->ib_offset = USI_MAX_MEMCNT_BASE; 306 ci_offset = pm8001_ha->ci_offset = ib_offset + count; 307 ob_offset = pm8001_ha->ob_offset = ci_offset + count; 308 pi_offset = pm8001_ha->pi_offset = ob_offset + count; 309 pm8001_ha->max_memcnt = pi_offset + count; 310 311 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 312 pm8001_phy_init(pm8001_ha, i); 313 pm8001_ha->port[i].wide_port_phymap = 0; 314 pm8001_ha->port[i].port_attached = 0; 315 pm8001_ha->port[i].port_state = 0; 316 INIT_LIST_HEAD(&pm8001_ha->port[i].list); 317 } 318 319 /* MPI Memory region 1 for AAP Event Log for fw */ 320 pm8001_ha->memoryMap.region[AAP1].num_elements = 1; 321 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE; 322 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE; 323 pm8001_ha->memoryMap.region[AAP1].alignment = 32; 324 325 /* MPI Memory region 2 for IOP Event Log for fw */ 326 pm8001_ha->memoryMap.region[IOP].num_elements = 1; 327 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE; 328 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE; 329 pm8001_ha->memoryMap.region[IOP].alignment = 32; 330 331 for (i = 0; i < count; i++) { 332 ibq = &pm8001_ha->inbnd_q_tbl[i]; 333 spin_lock_init(&ibq->iq_lock); 334 /* MPI Memory region 3 for consumer Index of inbound queues */ 335 pm8001_ha->memoryMap.region[ci_offset+i].num_elements = 1; 336 pm8001_ha->memoryMap.region[ci_offset+i].element_size = 4; 337 pm8001_ha->memoryMap.region[ci_offset+i].total_len = 4; 338 pm8001_ha->memoryMap.region[ci_offset+i].alignment = 4; 339 340 if ((ent->driver_data) != chip_8001) { 341 /* MPI Memory region 5 inbound queues */ 342 pm8001_ha->memoryMap.region[ib_offset+i].num_elements = 343 PM8001_MPI_QUEUE; 344 pm8001_ha->memoryMap.region[ib_offset+i].element_size 345 = 128; 346 pm8001_ha->memoryMap.region[ib_offset+i].total_len = 347 PM8001_MPI_QUEUE * 128; 348 pm8001_ha->memoryMap.region[ib_offset+i].alignment 349 = 128; 350 } else { 351 pm8001_ha->memoryMap.region[ib_offset+i].num_elements = 352 PM8001_MPI_QUEUE; 353 pm8001_ha->memoryMap.region[ib_offset+i].element_size 354 = 64; 355 pm8001_ha->memoryMap.region[ib_offset+i].total_len = 356 PM8001_MPI_QUEUE * 64; 357 pm8001_ha->memoryMap.region[ib_offset+i].alignment = 64; 358 } 359 } 360 361 for (i = 0; i < count; i++) { 362 obq = &pm8001_ha->outbnd_q_tbl[i]; 363 spin_lock_init(&obq->oq_lock); 364 /* MPI Memory region 4 for producer Index of outbound queues */ 365 pm8001_ha->memoryMap.region[pi_offset+i].num_elements = 1; 366 pm8001_ha->memoryMap.region[pi_offset+i].element_size = 4; 367 pm8001_ha->memoryMap.region[pi_offset+i].total_len = 4; 368 pm8001_ha->memoryMap.region[pi_offset+i].alignment = 4; 369 370 if (ent->driver_data != chip_8001) { 371 /* MPI Memory region 6 Outbound queues */ 372 pm8001_ha->memoryMap.region[ob_offset+i].num_elements = 373 PM8001_MPI_QUEUE; 374 pm8001_ha->memoryMap.region[ob_offset+i].element_size 375 = 128; 376 pm8001_ha->memoryMap.region[ob_offset+i].total_len = 377 PM8001_MPI_QUEUE * 128; 378 pm8001_ha->memoryMap.region[ob_offset+i].alignment 379 = 128; 380 } else { 381 /* MPI Memory region 6 Outbound queues */ 382 pm8001_ha->memoryMap.region[ob_offset+i].num_elements = 383 PM8001_MPI_QUEUE; 384 pm8001_ha->memoryMap.region[ob_offset+i].element_size 385 = 64; 386 pm8001_ha->memoryMap.region[ob_offset+i].total_len = 387 PM8001_MPI_QUEUE * 64; 388 pm8001_ha->memoryMap.region[ob_offset+i].alignment = 64; 389 } 390 391 } 392 /* Memory region write DMA*/ 393 pm8001_ha->memoryMap.region[NVMD].num_elements = 1; 394 pm8001_ha->memoryMap.region[NVMD].element_size = 4096; 395 pm8001_ha->memoryMap.region[NVMD].total_len = 4096; 396 397 /* Memory region for fw flash */ 398 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096; 399 400 pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1; 401 pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000; 402 pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000; 403 pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000; 404 for (i = 0; i < pm8001_ha->max_memcnt; i++) { 405 struct mpi_mem *region = &pm8001_ha->memoryMap.region[i]; 406 407 if (pm8001_mem_alloc(pm8001_ha->pdev, 408 ®ion->virt_ptr, 409 ®ion->phys_addr, 410 ®ion->phys_addr_hi, 411 ®ion->phys_addr_lo, 412 region->total_len, 413 region->alignment) != 0) { 414 pm8001_dbg(pm8001_ha, FAIL, "Mem%d alloc failed\n", i); 415 goto err_out; 416 } 417 } 418 419 /* Memory region for devices*/ 420 pm8001_ha->devices = kzalloc(PM8001_MAX_DEVICES 421 * sizeof(struct pm8001_device), GFP_KERNEL); 422 if (!pm8001_ha->devices) { 423 rc = -ENOMEM; 424 goto err_out_nodev; 425 } 426 for (i = 0; i < PM8001_MAX_DEVICES; i++) { 427 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED; 428 pm8001_ha->devices[i].id = i; 429 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES; 430 atomic_set(&pm8001_ha->devices[i].running_req, 0); 431 } 432 pm8001_ha->flags = PM8001F_INIT_TIME; 433 return 0; 434 435 err_out_nodev: 436 for (i = 0; i < pm8001_ha->max_memcnt; i++) { 437 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) { 438 dma_free_coherent(&pm8001_ha->pdev->dev, 439 (pm8001_ha->memoryMap.region[i].total_len + 440 pm8001_ha->memoryMap.region[i].alignment), 441 pm8001_ha->memoryMap.region[i].virt_ptr, 442 pm8001_ha->memoryMap.region[i].phys_addr); 443 } 444 } 445 err_out: 446 return 1; 447 } 448 449 /** 450 * pm8001_ioremap - remap the pci high physical address to kernel virtual 451 * address so that we can access them. 452 * @pm8001_ha: our hba structure. 453 */ 454 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha) 455 { 456 u32 bar; 457 u32 logicalBar = 0; 458 struct pci_dev *pdev; 459 460 pdev = pm8001_ha->pdev; 461 /* map pci mem (PMC pci base 0-3)*/ 462 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { 463 /* 464 ** logical BARs for SPC: 465 ** bar 0 and 1 - logical BAR0 466 ** bar 2 and 3 - logical BAR1 467 ** bar4 - logical BAR2 468 ** bar5 - logical BAR3 469 ** Skip the appropriate assignments: 470 */ 471 if ((bar == 1) || (bar == 3)) 472 continue; 473 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { 474 pm8001_ha->io_mem[logicalBar].membase = 475 pci_resource_start(pdev, bar); 476 pm8001_ha->io_mem[logicalBar].memsize = 477 pci_resource_len(pdev, bar); 478 pm8001_ha->io_mem[logicalBar].memvirtaddr = 479 ioremap(pm8001_ha->io_mem[logicalBar].membase, 480 pm8001_ha->io_mem[logicalBar].memsize); 481 if (!pm8001_ha->io_mem[logicalBar].memvirtaddr) { 482 pm8001_dbg(pm8001_ha, INIT, 483 "Failed to ioremap bar %d, logicalBar %d", 484 bar, logicalBar); 485 return -ENOMEM; 486 } 487 pm8001_dbg(pm8001_ha, INIT, 488 "base addr %llx virt_addr=%llx len=%d\n", 489 (u64)pm8001_ha->io_mem[logicalBar].membase, 490 (u64)(unsigned long) 491 pm8001_ha->io_mem[logicalBar].memvirtaddr, 492 pm8001_ha->io_mem[logicalBar].memsize); 493 } else { 494 pm8001_ha->io_mem[logicalBar].membase = 0; 495 pm8001_ha->io_mem[logicalBar].memsize = 0; 496 pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL; 497 } 498 logicalBar++; 499 } 500 return 0; 501 } 502 503 /** 504 * pm8001_pci_alloc - initialize our ha card structure 505 * @pdev: pci device. 506 * @ent: ent 507 * @shost: scsi host struct which has been initialized before. 508 */ 509 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev, 510 const struct pci_device_id *ent, 511 struct Scsi_Host *shost) 512 513 { 514 struct pm8001_hba_info *pm8001_ha; 515 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 516 int j; 517 518 pm8001_ha = sha->lldd_ha; 519 if (!pm8001_ha) 520 return NULL; 521 522 pm8001_ha->pdev = pdev; 523 pm8001_ha->dev = &pdev->dev; 524 pm8001_ha->chip_id = ent->driver_data; 525 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id]; 526 pm8001_ha->irq = pdev->irq; 527 pm8001_ha->sas = sha; 528 pm8001_ha->shost = shost; 529 pm8001_ha->id = pm8001_id++; 530 pm8001_ha->logging_level = logging_level; 531 pm8001_ha->non_fatal_count = 0; 532 if (link_rate >= 1 && link_rate <= 15) 533 pm8001_ha->link_rate = (link_rate << 8); 534 else { 535 pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 | 536 LINKRATE_60 | LINKRATE_120; 537 pm8001_dbg(pm8001_ha, FAIL, 538 "Setting link rate to default value\n"); 539 } 540 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id); 541 /* IOMB size is 128 for 8088/89 controllers */ 542 if (pm8001_ha->chip_id != chip_8001) 543 pm8001_ha->iomb_size = IOMB_SIZE_SPCV; 544 else 545 pm8001_ha->iomb_size = IOMB_SIZE_SPC; 546 547 #ifdef PM8001_USE_TASKLET 548 /* Tasklet for non msi-x interrupt handler */ 549 if ((!pdev->msix_cap || !pci_msi_enabled()) 550 || (pm8001_ha->chip_id == chip_8001)) 551 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet, 552 (unsigned long)&(pm8001_ha->irq_vector[0])); 553 else 554 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 555 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet, 556 (unsigned long)&(pm8001_ha->irq_vector[j])); 557 #endif 558 if (pm8001_ioremap(pm8001_ha)) 559 goto failed_pci_alloc; 560 if (!pm8001_alloc(pm8001_ha, ent)) 561 return pm8001_ha; 562 failed_pci_alloc: 563 pm8001_free(pm8001_ha); 564 return NULL; 565 } 566 567 /** 568 * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit 569 * @pdev: pci device. 570 */ 571 static int pci_go_44(struct pci_dev *pdev) 572 { 573 int rc; 574 575 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44)); 576 if (rc) { 577 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 578 if (rc) 579 dev_printk(KERN_ERR, &pdev->dev, 580 "32-bit DMA enable failed\n"); 581 } 582 return rc; 583 } 584 585 /** 586 * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them. 587 * @shost: scsi host which has been allocated outside. 588 * @chip_info: our ha struct. 589 */ 590 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost, 591 const struct pm8001_chip_info *chip_info) 592 { 593 int phy_nr, port_nr; 594 struct asd_sas_phy **arr_phy; 595 struct asd_sas_port **arr_port; 596 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 597 598 phy_nr = chip_info->n_phy; 599 port_nr = phy_nr; 600 memset(sha, 0x00, sizeof(*sha)); 601 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL); 602 if (!arr_phy) 603 goto exit; 604 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL); 605 if (!arr_port) 606 goto exit_free2; 607 608 sha->sas_phy = arr_phy; 609 sha->sas_port = arr_port; 610 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL); 611 if (!sha->lldd_ha) 612 goto exit_free1; 613 614 shost->transportt = pm8001_stt; 615 shost->max_id = PM8001_MAX_DEVICES; 616 shost->unique_id = pm8001_id; 617 shost->max_cmd_len = 16; 618 return 0; 619 exit_free1: 620 kfree(arr_port); 621 exit_free2: 622 kfree(arr_phy); 623 exit: 624 return -1; 625 } 626 627 /** 628 * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas 629 * @shost: scsi host which has been allocated outside 630 * @chip_info: our ha struct. 631 */ 632 static void pm8001_post_sas_ha_init(struct Scsi_Host *shost, 633 const struct pm8001_chip_info *chip_info) 634 { 635 int i = 0; 636 struct pm8001_hba_info *pm8001_ha; 637 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 638 639 pm8001_ha = sha->lldd_ha; 640 for (i = 0; i < chip_info->n_phy; i++) { 641 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy; 642 sha->sas_port[i] = &pm8001_ha->port[i].sas_port; 643 sha->sas_phy[i]->sas_addr = 644 (u8 *)&pm8001_ha->phy[i].dev_sas_addr; 645 } 646 sha->sas_ha_name = DRV_NAME; 647 sha->dev = pm8001_ha->dev; 648 sha->strict_wide_ports = 1; 649 sha->sas_addr = &pm8001_ha->sas_addr[0]; 650 sha->num_phys = chip_info->n_phy; 651 sha->shost = shost; 652 } 653 654 /** 655 * pm8001_init_sas_add - initialize sas address 656 * @pm8001_ha: our ha struct. 657 * 658 * Currently we just set the fixed SAS address to our HBA, for manufacture, 659 * it should read from the EEPROM 660 */ 661 static int pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha) 662 { 663 u8 i, j; 664 u8 sas_add[8]; 665 #ifdef PM8001_READ_VPD 666 /* For new SPC controllers WWN is stored in flash vpd 667 * For SPC/SPCve controllers WWN is stored in EEPROM 668 * For Older SPC WWN is stored in NVMD 669 */ 670 DECLARE_COMPLETION_ONSTACK(completion); 671 struct pm8001_ioctl_payload payload; 672 u16 deviceid; 673 int rc; 674 unsigned long time_remaining; 675 676 if (PM8001_CHIP_DISP->fatal_errors(pm8001_ha)) { 677 pm8001_dbg(pm8001_ha, FAIL, "controller is in fatal error state\n"); 678 return -EIO; 679 } 680 681 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid); 682 pm8001_ha->nvmd_completion = &completion; 683 684 if (pm8001_ha->chip_id == chip_8001) { 685 if (deviceid == 0x8081 || deviceid == 0x0042) { 686 payload.minor_function = 4; 687 payload.rd_length = 4096; 688 } else { 689 payload.minor_function = 0; 690 payload.rd_length = 128; 691 } 692 } else if ((pm8001_ha->chip_id == chip_8070 || 693 pm8001_ha->chip_id == chip_8072) && 694 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) { 695 payload.minor_function = 4; 696 payload.rd_length = 4096; 697 } else { 698 payload.minor_function = 1; 699 payload.rd_length = 4096; 700 } 701 payload.offset = 0; 702 payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL); 703 if (!payload.func_specific) { 704 pm8001_dbg(pm8001_ha, FAIL, "mem alloc fail\n"); 705 return -ENOMEM; 706 } 707 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload); 708 if (rc) { 709 kfree(payload.func_specific); 710 pm8001_dbg(pm8001_ha, FAIL, "nvmd failed\n"); 711 return -EIO; 712 } 713 time_remaining = wait_for_completion_timeout(&completion, 714 msecs_to_jiffies(60*1000)); // 1 min 715 if (!time_remaining) { 716 kfree(payload.func_specific); 717 pm8001_dbg(pm8001_ha, FAIL, "get_nvmd_req timeout\n"); 718 return -EIO; 719 } 720 721 722 for (i = 0, j = 0; i <= 7; i++, j++) { 723 if (pm8001_ha->chip_id == chip_8001) { 724 if (deviceid == 0x8081) 725 pm8001_ha->sas_addr[j] = 726 payload.func_specific[0x704 + i]; 727 else if (deviceid == 0x0042) 728 pm8001_ha->sas_addr[j] = 729 payload.func_specific[0x010 + i]; 730 } else if ((pm8001_ha->chip_id == chip_8070 || 731 pm8001_ha->chip_id == chip_8072) && 732 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) { 733 pm8001_ha->sas_addr[j] = 734 payload.func_specific[0x010 + i]; 735 } else 736 pm8001_ha->sas_addr[j] = 737 payload.func_specific[0x804 + i]; 738 } 739 memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE); 740 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 741 if (i && ((i % 4) == 0)) 742 sas_add[7] = sas_add[7] + 4; 743 memcpy(&pm8001_ha->phy[i].dev_sas_addr, 744 sas_add, SAS_ADDR_SIZE); 745 pm8001_dbg(pm8001_ha, INIT, "phy %d sas_addr = %016llx\n", i, 746 pm8001_ha->phy[i].dev_sas_addr); 747 } 748 kfree(payload.func_specific); 749 #else 750 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 751 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL; 752 pm8001_ha->phy[i].dev_sas_addr = 753 cpu_to_be64((u64) 754 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr)); 755 } 756 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr, 757 SAS_ADDR_SIZE); 758 #endif 759 return 0; 760 } 761 762 /* 763 * pm8001_get_phy_settings_info : Read phy setting values. 764 * @pm8001_ha : our hba. 765 */ 766 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha) 767 { 768 769 #ifdef PM8001_READ_VPD 770 /*OPTION ROM FLASH read for the SPC cards */ 771 DECLARE_COMPLETION_ONSTACK(completion); 772 struct pm8001_ioctl_payload payload; 773 int rc; 774 775 pm8001_ha->nvmd_completion = &completion; 776 /* SAS ADDRESS read from flash / EEPROM */ 777 payload.minor_function = 6; 778 payload.offset = 0; 779 payload.rd_length = 4096; 780 payload.func_specific = kzalloc(4096, GFP_KERNEL); 781 if (!payload.func_specific) 782 return -ENOMEM; 783 /* Read phy setting values from flash */ 784 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload); 785 if (rc) { 786 kfree(payload.func_specific); 787 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n"); 788 return -ENOMEM; 789 } 790 wait_for_completion(&completion); 791 pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific); 792 kfree(payload.func_specific); 793 #endif 794 return 0; 795 } 796 797 struct pm8001_mpi3_phy_pg_trx_config { 798 u32 LaneLosCfg; 799 u32 LanePgaCfg1; 800 u32 LanePisoCfg1; 801 u32 LanePisoCfg2; 802 u32 LanePisoCfg3; 803 u32 LanePisoCfg4; 804 u32 LanePisoCfg5; 805 u32 LanePisoCfg6; 806 u32 LaneBctCtrl; 807 }; 808 809 /** 810 * pm8001_get_internal_phy_settings - Retrieves the internal PHY settings 811 * @pm8001_ha : our adapter 812 * @phycfg : PHY config page to populate 813 */ 814 static 815 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha, 816 struct pm8001_mpi3_phy_pg_trx_config *phycfg) 817 { 818 phycfg->LaneLosCfg = 0x00000132; 819 phycfg->LanePgaCfg1 = 0x00203949; 820 phycfg->LanePisoCfg1 = 0x000000FF; 821 phycfg->LanePisoCfg2 = 0xFF000001; 822 phycfg->LanePisoCfg3 = 0xE7011300; 823 phycfg->LanePisoCfg4 = 0x631C40C0; 824 phycfg->LanePisoCfg5 = 0xF8102036; 825 phycfg->LanePisoCfg6 = 0xF74A1000; 826 phycfg->LaneBctCtrl = 0x00FB33F8; 827 } 828 829 /** 830 * pm8001_get_external_phy_settings - Retrieves the external PHY settings 831 * @pm8001_ha : our adapter 832 * @phycfg : PHY config page to populate 833 */ 834 static 835 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha, 836 struct pm8001_mpi3_phy_pg_trx_config *phycfg) 837 { 838 phycfg->LaneLosCfg = 0x00000132; 839 phycfg->LanePgaCfg1 = 0x00203949; 840 phycfg->LanePisoCfg1 = 0x000000FF; 841 phycfg->LanePisoCfg2 = 0xFF000001; 842 phycfg->LanePisoCfg3 = 0xE7011300; 843 phycfg->LanePisoCfg4 = 0x63349140; 844 phycfg->LanePisoCfg5 = 0xF8102036; 845 phycfg->LanePisoCfg6 = 0xF80D9300; 846 phycfg->LaneBctCtrl = 0x00FB33F8; 847 } 848 849 /** 850 * pm8001_get_phy_mask - Retrieves the mask that denotes if a PHY is int/ext 851 * @pm8001_ha : our adapter 852 * @phymask : The PHY mask 853 */ 854 static 855 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask) 856 { 857 switch (pm8001_ha->pdev->subsystem_device) { 858 case 0x0070: /* H1280 - 8 external 0 internal */ 859 case 0x0072: /* H12F0 - 16 external 0 internal */ 860 *phymask = 0x0000; 861 break; 862 863 case 0x0071: /* H1208 - 0 external 8 internal */ 864 case 0x0073: /* H120F - 0 external 16 internal */ 865 *phymask = 0xFFFF; 866 break; 867 868 case 0x0080: /* H1244 - 4 external 4 internal */ 869 *phymask = 0x00F0; 870 break; 871 872 case 0x0081: /* H1248 - 4 external 8 internal */ 873 *phymask = 0x0FF0; 874 break; 875 876 case 0x0082: /* H1288 - 8 external 8 internal */ 877 *phymask = 0xFF00; 878 break; 879 880 default: 881 pm8001_dbg(pm8001_ha, INIT, 882 "Unknown subsystem device=0x%.04x\n", 883 pm8001_ha->pdev->subsystem_device); 884 } 885 } 886 887 /** 888 * pm8001_set_phy_settings_ven_117c_12G() - Configure ATTO 12Gb PHY settings 889 * @pm8001_ha : our adapter 890 */ 891 static 892 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha) 893 { 894 struct pm8001_mpi3_phy_pg_trx_config phycfg_int; 895 struct pm8001_mpi3_phy_pg_trx_config phycfg_ext; 896 int phymask = 0; 897 int i = 0; 898 899 memset(&phycfg_int, 0, sizeof(phycfg_int)); 900 memset(&phycfg_ext, 0, sizeof(phycfg_ext)); 901 902 pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int); 903 pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext); 904 pm8001_get_phy_mask(pm8001_ha, &phymask); 905 906 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 907 if (phymask & (1 << i)) {/* Internal PHY */ 908 pm8001_set_phy_profile_single(pm8001_ha, i, 909 sizeof(phycfg_int) / sizeof(u32), 910 (u32 *)&phycfg_int); 911 912 } else { /* External PHY */ 913 pm8001_set_phy_profile_single(pm8001_ha, i, 914 sizeof(phycfg_ext) / sizeof(u32), 915 (u32 *)&phycfg_ext); 916 } 917 } 918 919 return 0; 920 } 921 922 /** 923 * pm8001_configure_phy_settings - Configures PHY settings based on vendor ID. 924 * @pm8001_ha : our hba. 925 */ 926 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha) 927 { 928 switch (pm8001_ha->pdev->subsystem_vendor) { 929 case PCI_VENDOR_ID_ATTO: 930 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */ 931 return 0; 932 else 933 return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha); 934 935 case PCI_VENDOR_ID_ADAPTEC2: 936 case 0: 937 return 0; 938 939 default: 940 return pm8001_get_phy_settings_info(pm8001_ha); 941 } 942 } 943 944 #ifdef PM8001_USE_MSIX 945 /** 946 * pm8001_setup_msix - enable MSI-X interrupt 947 * @pm8001_ha: our ha struct. 948 */ 949 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha) 950 { 951 unsigned int allocated_irq_vectors; 952 int rc; 953 954 /* SPCv controllers supports 64 msi-x */ 955 if (pm8001_ha->chip_id == chip_8001) { 956 rc = pci_alloc_irq_vectors(pm8001_ha->pdev, 1, 1, 957 PCI_IRQ_MSIX); 958 } else { 959 /* 960 * Queue index #0 is used always for housekeeping, so don't 961 * include in the affinity spreading. 962 */ 963 struct irq_affinity desc = { 964 .pre_vectors = 1, 965 }; 966 rc = pci_alloc_irq_vectors_affinity( 967 pm8001_ha->pdev, 2, PM8001_MAX_MSIX_VEC, 968 PCI_IRQ_MSIX | PCI_IRQ_AFFINITY, &desc); 969 } 970 971 allocated_irq_vectors = rc; 972 if (rc < 0) 973 return rc; 974 975 /* Assigns the number of interrupts */ 976 pm8001_ha->number_of_intr = allocated_irq_vectors; 977 978 /* Maximum queue number updating in HBA structure */ 979 pm8001_ha->max_q_num = allocated_irq_vectors; 980 981 pm8001_dbg(pm8001_ha, INIT, 982 "pci_alloc_irq_vectors request ret:%d no of intr %d\n", 983 rc, pm8001_ha->number_of_intr); 984 return 0; 985 } 986 987 static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha) 988 { 989 u32 i = 0, j = 0; 990 int flag = 0, rc = 0; 991 int nr_irqs = pm8001_ha->number_of_intr; 992 993 if (pm8001_ha->chip_id != chip_8001) 994 flag &= ~IRQF_SHARED; 995 996 pm8001_dbg(pm8001_ha, INIT, 997 "pci_enable_msix request number of intr %d\n", 998 pm8001_ha->number_of_intr); 999 1000 if (nr_irqs > ARRAY_SIZE(pm8001_ha->intr_drvname)) 1001 nr_irqs = ARRAY_SIZE(pm8001_ha->intr_drvname); 1002 1003 for (i = 0; i < nr_irqs; i++) { 1004 snprintf(pm8001_ha->intr_drvname[i], 1005 sizeof(pm8001_ha->intr_drvname[0]), 1006 "%s-%d", pm8001_ha->name, i); 1007 pm8001_ha->irq_vector[i].irq_id = i; 1008 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha; 1009 1010 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i), 1011 pm8001_interrupt_handler_msix, flag, 1012 pm8001_ha->intr_drvname[i], 1013 &(pm8001_ha->irq_vector[i])); 1014 if (rc) { 1015 for (j = 0; j < i; j++) { 1016 free_irq(pci_irq_vector(pm8001_ha->pdev, i), 1017 &(pm8001_ha->irq_vector[i])); 1018 } 1019 pci_free_irq_vectors(pm8001_ha->pdev); 1020 break; 1021 } 1022 } 1023 1024 return rc; 1025 } 1026 #endif 1027 1028 /** 1029 * pm8001_request_irq - register interrupt 1030 * @pm8001_ha: our ha struct. 1031 */ 1032 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha) 1033 { 1034 struct pci_dev *pdev = pm8001_ha->pdev; 1035 #ifdef PM8001_USE_MSIX 1036 int rc; 1037 1038 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX)) { 1039 rc = pm8001_setup_msix(pm8001_ha); 1040 if (rc) { 1041 pm8001_dbg(pm8001_ha, FAIL, 1042 "pm8001_setup_irq failed [ret: %d]\n", rc); 1043 return rc; 1044 } 1045 1046 if (pdev->msix_cap && pci_msi_enabled()) 1047 return pm8001_request_msix(pm8001_ha); 1048 } 1049 1050 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n"); 1051 #endif 1052 1053 /* initialize the INT-X interrupt */ 1054 pm8001_ha->irq_vector[0].irq_id = 0; 1055 pm8001_ha->irq_vector[0].drv_inst = pm8001_ha; 1056 1057 return request_irq(pdev->irq, pm8001_interrupt_handler_intx, 1058 IRQF_SHARED, pm8001_ha->name, 1059 SHOST_TO_SAS_HA(pm8001_ha->shost)); 1060 } 1061 1062 /** 1063 * pm8001_pci_probe - probe supported device 1064 * @pdev: pci device which kernel has been prepared for. 1065 * @ent: pci device id 1066 * 1067 * This function is the main initialization function, when register a new 1068 * pci driver it is invoked, all struct and hardware initialization should be 1069 * done here, also, register interrupt. 1070 */ 1071 static int pm8001_pci_probe(struct pci_dev *pdev, 1072 const struct pci_device_id *ent) 1073 { 1074 unsigned int rc; 1075 u32 pci_reg; 1076 u8 i = 0; 1077 struct pm8001_hba_info *pm8001_ha; 1078 struct Scsi_Host *shost = NULL; 1079 const struct pm8001_chip_info *chip; 1080 struct sas_ha_struct *sha; 1081 1082 dev_printk(KERN_INFO, &pdev->dev, 1083 "pm80xx: driver version %s\n", DRV_VERSION); 1084 rc = pci_enable_device(pdev); 1085 if (rc) 1086 goto err_out_enable; 1087 pci_set_master(pdev); 1088 /* 1089 * Enable pci slot busmaster by setting pci command register. 1090 * This is required by FW for Cyclone card. 1091 */ 1092 1093 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg); 1094 pci_reg |= 0x157; 1095 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg); 1096 rc = pci_request_regions(pdev, DRV_NAME); 1097 if (rc) 1098 goto err_out_disable; 1099 rc = pci_go_44(pdev); 1100 if (rc) 1101 goto err_out_regions; 1102 1103 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *)); 1104 if (!shost) { 1105 rc = -ENOMEM; 1106 goto err_out_regions; 1107 } 1108 chip = &pm8001_chips[ent->driver_data]; 1109 sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL); 1110 if (!sha) { 1111 rc = -ENOMEM; 1112 goto err_out_free_host; 1113 } 1114 SHOST_TO_SAS_HA(shost) = sha; 1115 1116 rc = pm8001_prep_sas_ha_init(shost, chip); 1117 if (rc) { 1118 rc = -ENOMEM; 1119 goto err_out_free; 1120 } 1121 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost)); 1122 /* ent->driver variable is used to differentiate between controllers */ 1123 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost); 1124 if (!pm8001_ha) { 1125 rc = -ENOMEM; 1126 goto err_out_free; 1127 } 1128 1129 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1130 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); 1131 if (rc) { 1132 pm8001_dbg(pm8001_ha, FAIL, 1133 "chip_init failed [ret: %d]\n", rc); 1134 goto err_out_ha_free; 1135 } 1136 1137 rc = pm8001_init_ccb_tag(pm8001_ha); 1138 if (rc) 1139 goto err_out_enable; 1140 1141 1142 PM8001_CHIP_DISP->chip_post_init(pm8001_ha); 1143 1144 if (pm8001_ha->number_of_intr > 1) { 1145 shost->nr_hw_queues = pm8001_ha->number_of_intr - 1; 1146 /* 1147 * For now, ensure we're not sent too many commands by setting 1148 * host_tagset. This is also required if we start using request 1149 * tag. 1150 */ 1151 shost->host_tagset = 1; 1152 } 1153 1154 rc = scsi_add_host(shost, &pdev->dev); 1155 if (rc) 1156 goto err_out_ha_free; 1157 1158 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0); 1159 if (pm8001_ha->chip_id != chip_8001) { 1160 for (i = 1; i < pm8001_ha->number_of_intr; i++) 1161 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i); 1162 /* setup thermal configuration. */ 1163 pm80xx_set_thermal_config(pm8001_ha); 1164 } 1165 1166 rc = pm8001_init_sas_add(pm8001_ha); 1167 if (rc) 1168 goto err_out_shost; 1169 /* phy setting support for motherboard controller */ 1170 rc = pm8001_configure_phy_settings(pm8001_ha); 1171 if (rc) 1172 goto err_out_shost; 1173 1174 pm8001_post_sas_ha_init(shost, chip); 1175 rc = sas_register_ha(SHOST_TO_SAS_HA(shost)); 1176 if (rc) { 1177 pm8001_dbg(pm8001_ha, FAIL, 1178 "sas_register_ha failed [ret: %d]\n", rc); 1179 goto err_out_shost; 1180 } 1181 list_add_tail(&pm8001_ha->list, &hba_list); 1182 pm8001_ha->flags = PM8001F_RUN_TIME; 1183 scsi_scan_host(pm8001_ha->shost); 1184 return 0; 1185 1186 err_out_shost: 1187 scsi_remove_host(pm8001_ha->shost); 1188 err_out_ha_free: 1189 pm8001_free(pm8001_ha); 1190 err_out_free: 1191 kfree(sha); 1192 err_out_free_host: 1193 scsi_host_put(shost); 1194 err_out_regions: 1195 pci_release_regions(pdev); 1196 err_out_disable: 1197 pci_disable_device(pdev); 1198 err_out_enable: 1199 return rc; 1200 } 1201 1202 /** 1203 * pm8001_init_ccb_tag - allocate memory to CCB and tag. 1204 * @pm8001_ha: our hba card information. 1205 */ 1206 static int pm8001_init_ccb_tag(struct pm8001_hba_info *pm8001_ha) 1207 { 1208 struct Scsi_Host *shost = pm8001_ha->shost; 1209 struct device *dev = pm8001_ha->dev; 1210 u32 max_out_io, ccb_count; 1211 int i; 1212 1213 max_out_io = pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io; 1214 ccb_count = min_t(int, PM8001_MAX_CCB, max_out_io); 1215 1216 shost->can_queue = ccb_count - PM8001_RESERVE_SLOT; 1217 1218 pm8001_ha->rsvd_tags = bitmap_zalloc(PM8001_RESERVE_SLOT, GFP_KERNEL); 1219 if (!pm8001_ha->rsvd_tags) 1220 goto err_out; 1221 1222 /* Memory region for ccb_info*/ 1223 pm8001_ha->ccb_count = ccb_count; 1224 pm8001_ha->ccb_info = 1225 kcalloc(ccb_count, sizeof(struct pm8001_ccb_info), GFP_KERNEL); 1226 if (!pm8001_ha->ccb_info) { 1227 pm8001_dbg(pm8001_ha, FAIL, 1228 "Unable to allocate memory for ccb\n"); 1229 goto err_out_noccb; 1230 } 1231 for (i = 0; i < ccb_count; i++) { 1232 pm8001_ha->ccb_info[i].buf_prd = dma_alloc_coherent(dev, 1233 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG, 1234 &pm8001_ha->ccb_info[i].ccb_dma_handle, 1235 GFP_KERNEL); 1236 if (!pm8001_ha->ccb_info[i].buf_prd) { 1237 pm8001_dbg(pm8001_ha, FAIL, 1238 "ccb prd memory allocation error\n"); 1239 goto err_out; 1240 } 1241 pm8001_ha->ccb_info[i].task = NULL; 1242 pm8001_ha->ccb_info[i].ccb_tag = PM8001_INVALID_TAG; 1243 pm8001_ha->ccb_info[i].device = NULL; 1244 } 1245 1246 return 0; 1247 1248 err_out_noccb: 1249 kfree(pm8001_ha->devices); 1250 err_out: 1251 return -ENOMEM; 1252 } 1253 1254 static void pm8001_pci_remove(struct pci_dev *pdev) 1255 { 1256 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1257 struct pm8001_hba_info *pm8001_ha; 1258 int i, j; 1259 pm8001_ha = sha->lldd_ha; 1260 sas_unregister_ha(sha); 1261 sas_remove_host(pm8001_ha->shost); 1262 list_del(&pm8001_ha->list); 1263 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1264 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1265 1266 #ifdef PM8001_USE_MSIX 1267 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1268 synchronize_irq(pci_irq_vector(pdev, i)); 1269 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1270 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]); 1271 pci_free_irq_vectors(pdev); 1272 #else 1273 free_irq(pm8001_ha->irq, sha); 1274 #endif 1275 #ifdef PM8001_USE_TASKLET 1276 /* For non-msix and msix interrupts */ 1277 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1278 (pm8001_ha->chip_id == chip_8001)) 1279 tasklet_kill(&pm8001_ha->tasklet[0]); 1280 else 1281 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1282 tasklet_kill(&pm8001_ha->tasklet[j]); 1283 #endif 1284 scsi_host_put(pm8001_ha->shost); 1285 1286 for (i = 0; i < pm8001_ha->ccb_count; i++) { 1287 dma_free_coherent(&pm8001_ha->pdev->dev, 1288 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG, 1289 pm8001_ha->ccb_info[i].buf_prd, 1290 pm8001_ha->ccb_info[i].ccb_dma_handle); 1291 } 1292 kfree(pm8001_ha->ccb_info); 1293 kfree(pm8001_ha->devices); 1294 1295 pm8001_free(pm8001_ha); 1296 kfree(sha->sas_phy); 1297 kfree(sha->sas_port); 1298 kfree(sha); 1299 pci_release_regions(pdev); 1300 pci_disable_device(pdev); 1301 } 1302 1303 /** 1304 * pm8001_pci_suspend - power management suspend main entry point 1305 * @dev: Device struct 1306 * 1307 * Return: 0 on success, anything else on error. 1308 */ 1309 static int __maybe_unused pm8001_pci_suspend(struct device *dev) 1310 { 1311 struct pci_dev *pdev = to_pci_dev(dev); 1312 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1313 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 1314 int i, j; 1315 sas_suspend_ha(sha); 1316 flush_workqueue(pm8001_wq); 1317 scsi_block_requests(pm8001_ha->shost); 1318 if (!pdev->pm_cap) { 1319 dev_err(dev, " PCI PM not supported\n"); 1320 return -ENODEV; 1321 } 1322 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1323 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1324 #ifdef PM8001_USE_MSIX 1325 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1326 synchronize_irq(pci_irq_vector(pdev, i)); 1327 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1328 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]); 1329 pci_free_irq_vectors(pdev); 1330 #else 1331 free_irq(pm8001_ha->irq, sha); 1332 #endif 1333 #ifdef PM8001_USE_TASKLET 1334 /* For non-msix and msix interrupts */ 1335 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1336 (pm8001_ha->chip_id == chip_8001)) 1337 tasklet_kill(&pm8001_ha->tasklet[0]); 1338 else 1339 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1340 tasklet_kill(&pm8001_ha->tasklet[j]); 1341 #endif 1342 pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, entering " 1343 "suspended state\n", pdev, 1344 pm8001_ha->name); 1345 return 0; 1346 } 1347 1348 /** 1349 * pm8001_pci_resume - power management resume main entry point 1350 * @dev: Device struct 1351 * 1352 * Return: 0 on success, anything else on error. 1353 */ 1354 static int __maybe_unused pm8001_pci_resume(struct device *dev) 1355 { 1356 struct pci_dev *pdev = to_pci_dev(dev); 1357 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1358 struct pm8001_hba_info *pm8001_ha; 1359 int rc; 1360 u8 i = 0, j; 1361 DECLARE_COMPLETION_ONSTACK(completion); 1362 1363 pm8001_ha = sha->lldd_ha; 1364 1365 pm8001_info(pm8001_ha, 1366 "pdev=0x%p, slot=%s, resuming from previous operating state [D%d]\n", 1367 pdev, pm8001_ha->name, pdev->current_state); 1368 1369 rc = pci_go_44(pdev); 1370 if (rc) 1371 goto err_out_disable; 1372 sas_prep_resume_ha(sha); 1373 /* chip soft rst only for spc */ 1374 if (pm8001_ha->chip_id == chip_8001) { 1375 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1376 pm8001_dbg(pm8001_ha, INIT, "chip soft reset successful\n"); 1377 } 1378 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); 1379 if (rc) 1380 goto err_out_disable; 1381 1382 /* disable all the interrupt bits */ 1383 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1384 1385 rc = pm8001_request_irq(pm8001_ha); 1386 if (rc) 1387 goto err_out_disable; 1388 #ifdef PM8001_USE_TASKLET 1389 /* Tasklet for non msi-x interrupt handler */ 1390 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1391 (pm8001_ha->chip_id == chip_8001)) 1392 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet, 1393 (unsigned long)&(pm8001_ha->irq_vector[0])); 1394 else 1395 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1396 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet, 1397 (unsigned long)&(pm8001_ha->irq_vector[j])); 1398 #endif 1399 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0); 1400 if (pm8001_ha->chip_id != chip_8001) { 1401 for (i = 1; i < pm8001_ha->number_of_intr; i++) 1402 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i); 1403 } 1404 1405 /* Chip documentation for the 8070 and 8072 SPCv */ 1406 /* states that a 500ms minimum delay is required */ 1407 /* before issuing commands. Otherwise, the firmware */ 1408 /* will enter an unrecoverable state. */ 1409 1410 if (pm8001_ha->chip_id == chip_8070 || 1411 pm8001_ha->chip_id == chip_8072) { 1412 mdelay(500); 1413 } 1414 1415 /* Spin up the PHYs */ 1416 1417 pm8001_ha->flags = PM8001F_RUN_TIME; 1418 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 1419 pm8001_ha->phy[i].enable_completion = &completion; 1420 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i); 1421 wait_for_completion(&completion); 1422 } 1423 sas_resume_ha(sha); 1424 return 0; 1425 1426 err_out_disable: 1427 scsi_remove_host(pm8001_ha->shost); 1428 1429 return rc; 1430 } 1431 1432 /* update of pci device, vendor id and driver data with 1433 * unique value for each of the controller 1434 */ 1435 static struct pci_device_id pm8001_pci_table[] = { 1436 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 }, 1437 { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 }, 1438 { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 }, 1439 { PCI_VDEVICE(ATTO, 0x0042), chip_8001 }, 1440 /* Support for SPC/SPCv/SPCve controllers */ 1441 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 }, 1442 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 }, 1443 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 }, 1444 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 }, 1445 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 }, 1446 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 }, 1447 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 }, 1448 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 }, 1449 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 }, 1450 { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 }, 1451 { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 }, 1452 { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 }, 1453 { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 }, 1454 { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 }, 1455 { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 }, 1456 { PCI_VENDOR_ID_ADAPTEC2, 0x8081, 1457 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 }, 1458 { PCI_VENDOR_ID_ADAPTEC2, 0x8081, 1459 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 }, 1460 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1461 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 }, 1462 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1463 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 }, 1464 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1465 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 }, 1466 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1467 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 }, 1468 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1469 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 }, 1470 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1471 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 }, 1472 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1473 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 }, 1474 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1475 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 }, 1476 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1477 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 }, 1478 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1479 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 }, 1480 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1481 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 }, 1482 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1483 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 }, 1484 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1485 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 }, 1486 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1487 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 }, 1488 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1489 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 }, 1490 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1491 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 }, 1492 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1493 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 }, 1494 { PCI_VENDOR_ID_ATTO, 0x8070, 1495 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 }, 1496 { PCI_VENDOR_ID_ATTO, 0x8070, 1497 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 }, 1498 { PCI_VENDOR_ID_ATTO, 0x8072, 1499 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 }, 1500 { PCI_VENDOR_ID_ATTO, 0x8072, 1501 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 }, 1502 { PCI_VENDOR_ID_ATTO, 0x8070, 1503 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 }, 1504 { PCI_VENDOR_ID_ATTO, 0x8072, 1505 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 }, 1506 { PCI_VENDOR_ID_ATTO, 0x8072, 1507 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 }, 1508 {} /* terminate list */ 1509 }; 1510 1511 static SIMPLE_DEV_PM_OPS(pm8001_pci_pm_ops, 1512 pm8001_pci_suspend, 1513 pm8001_pci_resume); 1514 1515 static struct pci_driver pm8001_pci_driver = { 1516 .name = DRV_NAME, 1517 .id_table = pm8001_pci_table, 1518 .probe = pm8001_pci_probe, 1519 .remove = pm8001_pci_remove, 1520 .driver.pm = &pm8001_pci_pm_ops, 1521 }; 1522 1523 /** 1524 * pm8001_init - initialize scsi transport template 1525 */ 1526 static int __init pm8001_init(void) 1527 { 1528 int rc = -ENOMEM; 1529 1530 pm8001_wq = alloc_workqueue("pm80xx", 0, 0); 1531 if (!pm8001_wq) 1532 goto err; 1533 1534 pm8001_id = 0; 1535 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops); 1536 if (!pm8001_stt) 1537 goto err_wq; 1538 rc = pci_register_driver(&pm8001_pci_driver); 1539 if (rc) 1540 goto err_tp; 1541 return 0; 1542 1543 err_tp: 1544 sas_release_transport(pm8001_stt); 1545 err_wq: 1546 destroy_workqueue(pm8001_wq); 1547 err: 1548 return rc; 1549 } 1550 1551 static void __exit pm8001_exit(void) 1552 { 1553 pci_unregister_driver(&pm8001_pci_driver); 1554 sas_release_transport(pm8001_stt); 1555 destroy_workqueue(pm8001_wq); 1556 } 1557 1558 module_init(pm8001_init); 1559 module_exit(pm8001_exit); 1560 1561 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>"); 1562 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>"); 1563 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>"); 1564 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>"); 1565 MODULE_DESCRIPTION( 1566 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 " 1567 "SAS/SATA controller driver"); 1568 MODULE_VERSION(DRV_VERSION); 1569 MODULE_LICENSE("GPL"); 1570 MODULE_DEVICE_TABLE(pci, pm8001_pci_table); 1571 1572