1 /* 2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 USI Co., Ltd. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 41 #include <linux/slab.h> 42 #include "pm8001_sas.h" 43 #include "pm8001_chips.h" 44 45 static struct scsi_transport_template *pm8001_stt; 46 47 /** 48 * chip info structure to identify chip key functionality as 49 * encryption available/not, no of ports, hw specific function ref 50 */ 51 static const struct pm8001_chip_info pm8001_chips[] = { 52 [chip_8001] = {0, 8, &pm8001_8001_dispatch,}, 53 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,}, 54 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,}, 55 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,}, 56 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,}, 57 [chip_8074] = {0, 8, &pm8001_80xx_dispatch,}, 58 [chip_8076] = {0, 16, &pm8001_80xx_dispatch,}, 59 [chip_8077] = {0, 16, &pm8001_80xx_dispatch,}, 60 }; 61 static int pm8001_id; 62 63 LIST_HEAD(hba_list); 64 65 struct workqueue_struct *pm8001_wq; 66 67 /** 68 * The main structure which LLDD must register for scsi core. 69 */ 70 static struct scsi_host_template pm8001_sht = { 71 .module = THIS_MODULE, 72 .name = DRV_NAME, 73 .queuecommand = sas_queuecommand, 74 .target_alloc = sas_target_alloc, 75 .slave_configure = sas_slave_configure, 76 .scan_finished = pm8001_scan_finished, 77 .scan_start = pm8001_scan_start, 78 .change_queue_depth = sas_change_queue_depth, 79 .change_queue_type = sas_change_queue_type, 80 .bios_param = sas_bios_param, 81 .can_queue = 1, 82 .cmd_per_lun = 1, 83 .this_id = -1, 84 .sg_tablesize = SG_ALL, 85 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 86 .use_clustering = ENABLE_CLUSTERING, 87 .eh_device_reset_handler = sas_eh_device_reset_handler, 88 .eh_bus_reset_handler = sas_eh_bus_reset_handler, 89 .target_destroy = sas_target_destroy, 90 .ioctl = sas_ioctl, 91 .shost_attrs = pm8001_host_attrs, 92 }; 93 94 /** 95 * Sas layer call this function to execute specific task. 96 */ 97 static struct sas_domain_function_template pm8001_transport_ops = { 98 .lldd_dev_found = pm8001_dev_found, 99 .lldd_dev_gone = pm8001_dev_gone, 100 101 .lldd_execute_task = pm8001_queue_command, 102 .lldd_control_phy = pm8001_phy_control, 103 104 .lldd_abort_task = pm8001_abort_task, 105 .lldd_abort_task_set = pm8001_abort_task_set, 106 .lldd_clear_aca = pm8001_clear_aca, 107 .lldd_clear_task_set = pm8001_clear_task_set, 108 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset, 109 .lldd_lu_reset = pm8001_lu_reset, 110 .lldd_query_task = pm8001_query_task, 111 }; 112 113 /** 114 *pm8001_phy_init - initiate our adapter phys 115 *@pm8001_ha: our hba structure. 116 *@phy_id: phy id. 117 */ 118 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id) 119 { 120 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 121 struct asd_sas_phy *sas_phy = &phy->sas_phy; 122 phy->phy_state = 0; 123 phy->pm8001_ha = pm8001_ha; 124 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0; 125 sas_phy->class = SAS; 126 sas_phy->iproto = SAS_PROTOCOL_ALL; 127 sas_phy->tproto = 0; 128 sas_phy->type = PHY_TYPE_PHYSICAL; 129 sas_phy->role = PHY_ROLE_INITIATOR; 130 sas_phy->oob_mode = OOB_NOT_CONNECTED; 131 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN; 132 sas_phy->id = phy_id; 133 sas_phy->sas_addr = &pm8001_ha->sas_addr[0]; 134 sas_phy->frame_rcvd = &phy->frame_rcvd[0]; 135 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata; 136 sas_phy->lldd_phy = phy; 137 } 138 139 /** 140 *pm8001_free - free hba 141 *@pm8001_ha: our hba structure. 142 * 143 */ 144 static void pm8001_free(struct pm8001_hba_info *pm8001_ha) 145 { 146 int i; 147 148 if (!pm8001_ha) 149 return; 150 151 for (i = 0; i < USI_MAX_MEMCNT; i++) { 152 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) { 153 pci_free_consistent(pm8001_ha->pdev, 154 (pm8001_ha->memoryMap.region[i].total_len + 155 pm8001_ha->memoryMap.region[i].alignment), 156 pm8001_ha->memoryMap.region[i].virt_ptr, 157 pm8001_ha->memoryMap.region[i].phys_addr); 158 } 159 } 160 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha); 161 if (pm8001_ha->shost) 162 scsi_host_put(pm8001_ha->shost); 163 flush_workqueue(pm8001_wq); 164 kfree(pm8001_ha->tags); 165 kfree(pm8001_ha); 166 } 167 168 #ifdef PM8001_USE_TASKLET 169 170 /** 171 * tasklet for 64 msi-x interrupt handler 172 * @opaque: the passed general host adapter struct 173 * Note: pm8001_tasklet is common for pm8001 & pm80xx 174 */ 175 static void pm8001_tasklet(unsigned long opaque) 176 { 177 struct pm8001_hba_info *pm8001_ha; 178 u32 vec; 179 pm8001_ha = (struct pm8001_hba_info *)opaque; 180 if (unlikely(!pm8001_ha)) 181 BUG_ON(1); 182 vec = pm8001_ha->int_vector; 183 PM8001_CHIP_DISP->isr(pm8001_ha, vec); 184 } 185 #endif 186 187 static struct pm8001_hba_info *outq_to_hba(u8 *outq) 188 { 189 return container_of((outq - *outq), struct pm8001_hba_info, outq[0]); 190 } 191 192 /** 193 * pm8001_interrupt_handler_msix - main MSIX interrupt handler. 194 * It obtains the vector number and calls the equivalent bottom 195 * half or services directly. 196 * @opaque: the passed outbound queue/vector. Host structure is 197 * retrieved from the same. 198 */ 199 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque) 200 { 201 struct pm8001_hba_info *pm8001_ha = outq_to_hba(opaque); 202 u8 outq = *(u8 *)opaque; 203 irqreturn_t ret = IRQ_HANDLED; 204 if (unlikely(!pm8001_ha)) 205 return IRQ_NONE; 206 if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha)) 207 return IRQ_NONE; 208 pm8001_ha->int_vector = outq; 209 #ifdef PM8001_USE_TASKLET 210 tasklet_schedule(&pm8001_ha->tasklet); 211 #else 212 ret = PM8001_CHIP_DISP->isr(pm8001_ha, outq); 213 #endif 214 return ret; 215 } 216 217 /** 218 * pm8001_interrupt_handler_intx - main INTx interrupt handler. 219 * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure. 220 */ 221 222 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id) 223 { 224 struct pm8001_hba_info *pm8001_ha; 225 irqreturn_t ret = IRQ_HANDLED; 226 struct sas_ha_struct *sha = dev_id; 227 pm8001_ha = sha->lldd_ha; 228 if (unlikely(!pm8001_ha)) 229 return IRQ_NONE; 230 if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha)) 231 return IRQ_NONE; 232 233 pm8001_ha->int_vector = 0; 234 #ifdef PM8001_USE_TASKLET 235 tasklet_schedule(&pm8001_ha->tasklet); 236 #else 237 ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0); 238 #endif 239 return ret; 240 } 241 242 /** 243 * pm8001_alloc - initiate our hba structure and 6 DMAs area. 244 * @pm8001_ha:our hba structure. 245 * 246 */ 247 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha, 248 const struct pci_device_id *ent) 249 { 250 int i; 251 spin_lock_init(&pm8001_ha->lock); 252 PM8001_INIT_DBG(pm8001_ha, 253 pm8001_printk("pm8001_alloc: PHY:%x\n", 254 pm8001_ha->chip->n_phy)); 255 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 256 pm8001_phy_init(pm8001_ha, i); 257 pm8001_ha->port[i].wide_port_phymap = 0; 258 pm8001_ha->port[i].port_attached = 0; 259 pm8001_ha->port[i].port_state = 0; 260 INIT_LIST_HEAD(&pm8001_ha->port[i].list); 261 } 262 263 pm8001_ha->tags = kzalloc(PM8001_MAX_CCB, GFP_KERNEL); 264 if (!pm8001_ha->tags) 265 goto err_out; 266 /* MPI Memory region 1 for AAP Event Log for fw */ 267 pm8001_ha->memoryMap.region[AAP1].num_elements = 1; 268 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE; 269 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE; 270 pm8001_ha->memoryMap.region[AAP1].alignment = 32; 271 272 /* MPI Memory region 2 for IOP Event Log for fw */ 273 pm8001_ha->memoryMap.region[IOP].num_elements = 1; 274 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE; 275 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE; 276 pm8001_ha->memoryMap.region[IOP].alignment = 32; 277 278 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) { 279 /* MPI Memory region 3 for consumer Index of inbound queues */ 280 pm8001_ha->memoryMap.region[CI+i].num_elements = 1; 281 pm8001_ha->memoryMap.region[CI+i].element_size = 4; 282 pm8001_ha->memoryMap.region[CI+i].total_len = 4; 283 pm8001_ha->memoryMap.region[CI+i].alignment = 4; 284 285 if ((ent->driver_data) != chip_8001) { 286 /* MPI Memory region 5 inbound queues */ 287 pm8001_ha->memoryMap.region[IB+i].num_elements = 288 PM8001_MPI_QUEUE; 289 pm8001_ha->memoryMap.region[IB+i].element_size = 128; 290 pm8001_ha->memoryMap.region[IB+i].total_len = 291 PM8001_MPI_QUEUE * 128; 292 pm8001_ha->memoryMap.region[IB+i].alignment = 128; 293 } else { 294 pm8001_ha->memoryMap.region[IB+i].num_elements = 295 PM8001_MPI_QUEUE; 296 pm8001_ha->memoryMap.region[IB+i].element_size = 64; 297 pm8001_ha->memoryMap.region[IB+i].total_len = 298 PM8001_MPI_QUEUE * 64; 299 pm8001_ha->memoryMap.region[IB+i].alignment = 64; 300 } 301 } 302 303 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) { 304 /* MPI Memory region 4 for producer Index of outbound queues */ 305 pm8001_ha->memoryMap.region[PI+i].num_elements = 1; 306 pm8001_ha->memoryMap.region[PI+i].element_size = 4; 307 pm8001_ha->memoryMap.region[PI+i].total_len = 4; 308 pm8001_ha->memoryMap.region[PI+i].alignment = 4; 309 310 if (ent->driver_data != chip_8001) { 311 /* MPI Memory region 6 Outbound queues */ 312 pm8001_ha->memoryMap.region[OB+i].num_elements = 313 PM8001_MPI_QUEUE; 314 pm8001_ha->memoryMap.region[OB+i].element_size = 128; 315 pm8001_ha->memoryMap.region[OB+i].total_len = 316 PM8001_MPI_QUEUE * 128; 317 pm8001_ha->memoryMap.region[OB+i].alignment = 128; 318 } else { 319 /* MPI Memory region 6 Outbound queues */ 320 pm8001_ha->memoryMap.region[OB+i].num_elements = 321 PM8001_MPI_QUEUE; 322 pm8001_ha->memoryMap.region[OB+i].element_size = 64; 323 pm8001_ha->memoryMap.region[OB+i].total_len = 324 PM8001_MPI_QUEUE * 64; 325 pm8001_ha->memoryMap.region[OB+i].alignment = 64; 326 } 327 328 } 329 /* Memory region write DMA*/ 330 pm8001_ha->memoryMap.region[NVMD].num_elements = 1; 331 pm8001_ha->memoryMap.region[NVMD].element_size = 4096; 332 pm8001_ha->memoryMap.region[NVMD].total_len = 4096; 333 /* Memory region for devices*/ 334 pm8001_ha->memoryMap.region[DEV_MEM].num_elements = 1; 335 pm8001_ha->memoryMap.region[DEV_MEM].element_size = PM8001_MAX_DEVICES * 336 sizeof(struct pm8001_device); 337 pm8001_ha->memoryMap.region[DEV_MEM].total_len = PM8001_MAX_DEVICES * 338 sizeof(struct pm8001_device); 339 340 /* Memory region for ccb_info*/ 341 pm8001_ha->memoryMap.region[CCB_MEM].num_elements = 1; 342 pm8001_ha->memoryMap.region[CCB_MEM].element_size = PM8001_MAX_CCB * 343 sizeof(struct pm8001_ccb_info); 344 pm8001_ha->memoryMap.region[CCB_MEM].total_len = PM8001_MAX_CCB * 345 sizeof(struct pm8001_ccb_info); 346 347 /* Memory region for fw flash */ 348 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096; 349 350 pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1; 351 pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000; 352 pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000; 353 pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000; 354 for (i = 0; i < USI_MAX_MEMCNT; i++) { 355 if (pm8001_mem_alloc(pm8001_ha->pdev, 356 &pm8001_ha->memoryMap.region[i].virt_ptr, 357 &pm8001_ha->memoryMap.region[i].phys_addr, 358 &pm8001_ha->memoryMap.region[i].phys_addr_hi, 359 &pm8001_ha->memoryMap.region[i].phys_addr_lo, 360 pm8001_ha->memoryMap.region[i].total_len, 361 pm8001_ha->memoryMap.region[i].alignment) != 0) { 362 PM8001_FAIL_DBG(pm8001_ha, 363 pm8001_printk("Mem%d alloc failed\n", 364 i)); 365 goto err_out; 366 } 367 } 368 369 pm8001_ha->devices = pm8001_ha->memoryMap.region[DEV_MEM].virt_ptr; 370 for (i = 0; i < PM8001_MAX_DEVICES; i++) { 371 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED; 372 pm8001_ha->devices[i].id = i; 373 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES; 374 pm8001_ha->devices[i].running_req = 0; 375 } 376 pm8001_ha->ccb_info = pm8001_ha->memoryMap.region[CCB_MEM].virt_ptr; 377 for (i = 0; i < PM8001_MAX_CCB; i++) { 378 pm8001_ha->ccb_info[i].ccb_dma_handle = 379 pm8001_ha->memoryMap.region[CCB_MEM].phys_addr + 380 i * sizeof(struct pm8001_ccb_info); 381 pm8001_ha->ccb_info[i].task = NULL; 382 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff; 383 pm8001_ha->ccb_info[i].device = NULL; 384 ++pm8001_ha->tags_num; 385 } 386 pm8001_ha->flags = PM8001F_INIT_TIME; 387 /* Initialize tags */ 388 pm8001_tag_init(pm8001_ha); 389 return 0; 390 err_out: 391 return 1; 392 } 393 394 /** 395 * pm8001_ioremap - remap the pci high physical address to kernal virtual 396 * address so that we can access them. 397 * @pm8001_ha:our hba structure. 398 */ 399 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha) 400 { 401 u32 bar; 402 u32 logicalBar = 0; 403 struct pci_dev *pdev; 404 405 pdev = pm8001_ha->pdev; 406 /* map pci mem (PMC pci base 0-3)*/ 407 for (bar = 0; bar < 6; bar++) { 408 /* 409 ** logical BARs for SPC: 410 ** bar 0 and 1 - logical BAR0 411 ** bar 2 and 3 - logical BAR1 412 ** bar4 - logical BAR2 413 ** bar5 - logical BAR3 414 ** Skip the appropriate assignments: 415 */ 416 if ((bar == 1) || (bar == 3)) 417 continue; 418 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { 419 pm8001_ha->io_mem[logicalBar].membase = 420 pci_resource_start(pdev, bar); 421 pm8001_ha->io_mem[logicalBar].membase &= 422 (u32)PCI_BASE_ADDRESS_MEM_MASK; 423 pm8001_ha->io_mem[logicalBar].memsize = 424 pci_resource_len(pdev, bar); 425 pm8001_ha->io_mem[logicalBar].memvirtaddr = 426 ioremap(pm8001_ha->io_mem[logicalBar].membase, 427 pm8001_ha->io_mem[logicalBar].memsize); 428 PM8001_INIT_DBG(pm8001_ha, 429 pm8001_printk("PCI: bar %d, logicalBar %d ", 430 bar, logicalBar)); 431 PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 432 "base addr %llx virt_addr=%llx len=%d\n", 433 (u64)pm8001_ha->io_mem[logicalBar].membase, 434 (u64)(unsigned long) 435 pm8001_ha->io_mem[logicalBar].memvirtaddr, 436 pm8001_ha->io_mem[logicalBar].memsize)); 437 } else { 438 pm8001_ha->io_mem[logicalBar].membase = 0; 439 pm8001_ha->io_mem[logicalBar].memsize = 0; 440 pm8001_ha->io_mem[logicalBar].memvirtaddr = 0; 441 } 442 logicalBar++; 443 } 444 return 0; 445 } 446 447 /** 448 * pm8001_pci_alloc - initialize our ha card structure 449 * @pdev: pci device. 450 * @ent: ent 451 * @shost: scsi host struct which has been initialized before. 452 */ 453 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev, 454 const struct pci_device_id *ent, 455 struct Scsi_Host *shost) 456 457 { 458 struct pm8001_hba_info *pm8001_ha; 459 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 460 461 462 pm8001_ha = sha->lldd_ha; 463 if (!pm8001_ha) 464 return NULL; 465 466 pm8001_ha->pdev = pdev; 467 pm8001_ha->dev = &pdev->dev; 468 pm8001_ha->chip_id = ent->driver_data; 469 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id]; 470 pm8001_ha->irq = pdev->irq; 471 pm8001_ha->sas = sha; 472 pm8001_ha->shost = shost; 473 pm8001_ha->id = pm8001_id++; 474 pm8001_ha->logging_level = 0x01; 475 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id); 476 /* IOMB size is 128 for 8088/89 controllers */ 477 if (pm8001_ha->chip_id != chip_8001) 478 pm8001_ha->iomb_size = IOMB_SIZE_SPCV; 479 else 480 pm8001_ha->iomb_size = IOMB_SIZE_SPC; 481 482 #ifdef PM8001_USE_TASKLET 483 /** 484 * default tasklet for non msi-x interrupt handler/first msi-x 485 * interrupt handler 486 **/ 487 tasklet_init(&pm8001_ha->tasklet, pm8001_tasklet, 488 (unsigned long)pm8001_ha); 489 #endif 490 pm8001_ioremap(pm8001_ha); 491 if (!pm8001_alloc(pm8001_ha, ent)) 492 return pm8001_ha; 493 pm8001_free(pm8001_ha); 494 return NULL; 495 } 496 497 /** 498 * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit 499 * @pdev: pci device. 500 */ 501 static int pci_go_44(struct pci_dev *pdev) 502 { 503 int rc; 504 505 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(44))) { 506 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(44)); 507 if (rc) { 508 rc = pci_set_consistent_dma_mask(pdev, 509 DMA_BIT_MASK(32)); 510 if (rc) { 511 dev_printk(KERN_ERR, &pdev->dev, 512 "44-bit DMA enable failed\n"); 513 return rc; 514 } 515 } 516 } else { 517 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 518 if (rc) { 519 dev_printk(KERN_ERR, &pdev->dev, 520 "32-bit DMA enable failed\n"); 521 return rc; 522 } 523 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 524 if (rc) { 525 dev_printk(KERN_ERR, &pdev->dev, 526 "32-bit consistent DMA enable failed\n"); 527 return rc; 528 } 529 } 530 return rc; 531 } 532 533 /** 534 * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them. 535 * @shost: scsi host which has been allocated outside. 536 * @chip_info: our ha struct. 537 */ 538 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost, 539 const struct pm8001_chip_info *chip_info) 540 { 541 int phy_nr, port_nr; 542 struct asd_sas_phy **arr_phy; 543 struct asd_sas_port **arr_port; 544 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 545 546 phy_nr = chip_info->n_phy; 547 port_nr = phy_nr; 548 memset(sha, 0x00, sizeof(*sha)); 549 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL); 550 if (!arr_phy) 551 goto exit; 552 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL); 553 if (!arr_port) 554 goto exit_free2; 555 556 sha->sas_phy = arr_phy; 557 sha->sas_port = arr_port; 558 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL); 559 if (!sha->lldd_ha) 560 goto exit_free1; 561 562 shost->transportt = pm8001_stt; 563 shost->max_id = PM8001_MAX_DEVICES; 564 shost->max_lun = 8; 565 shost->max_channel = 0; 566 shost->unique_id = pm8001_id; 567 shost->max_cmd_len = 16; 568 shost->can_queue = PM8001_CAN_QUEUE; 569 shost->cmd_per_lun = 32; 570 return 0; 571 exit_free1: 572 kfree(arr_port); 573 exit_free2: 574 kfree(arr_phy); 575 exit: 576 return -1; 577 } 578 579 /** 580 * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas 581 * @shost: scsi host which has been allocated outside 582 * @chip_info: our ha struct. 583 */ 584 static void pm8001_post_sas_ha_init(struct Scsi_Host *shost, 585 const struct pm8001_chip_info *chip_info) 586 { 587 int i = 0; 588 struct pm8001_hba_info *pm8001_ha; 589 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 590 591 pm8001_ha = sha->lldd_ha; 592 for (i = 0; i < chip_info->n_phy; i++) { 593 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy; 594 sha->sas_port[i] = &pm8001_ha->port[i].sas_port; 595 } 596 sha->sas_ha_name = DRV_NAME; 597 sha->dev = pm8001_ha->dev; 598 599 sha->lldd_module = THIS_MODULE; 600 sha->sas_addr = &pm8001_ha->sas_addr[0]; 601 sha->num_phys = chip_info->n_phy; 602 sha->lldd_max_execute_num = 1; 603 sha->lldd_queue_size = PM8001_CAN_QUEUE; 604 sha->core.shost = shost; 605 } 606 607 /** 608 * pm8001_init_sas_add - initialize sas address 609 * @chip_info: our ha struct. 610 * 611 * Currently we just set the fixed SAS address to our HBA,for manufacture, 612 * it should read from the EEPROM 613 */ 614 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha) 615 { 616 u8 i, j; 617 #ifdef PM8001_READ_VPD 618 /* For new SPC controllers WWN is stored in flash vpd 619 * For SPC/SPCve controllers WWN is stored in EEPROM 620 * For Older SPC WWN is stored in NVMD 621 */ 622 DECLARE_COMPLETION_ONSTACK(completion); 623 struct pm8001_ioctl_payload payload; 624 u16 deviceid; 625 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid); 626 pm8001_ha->nvmd_completion = &completion; 627 628 if (pm8001_ha->chip_id == chip_8001) { 629 if (deviceid == 0x8081) { 630 payload.minor_function = 4; 631 payload.length = 4096; 632 } else { 633 payload.minor_function = 0; 634 payload.length = 128; 635 } 636 } else { 637 payload.minor_function = 1; 638 payload.length = 4096; 639 } 640 payload.offset = 0; 641 payload.func_specific = kzalloc(payload.length, GFP_KERNEL); 642 PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload); 643 wait_for_completion(&completion); 644 645 for (i = 0, j = 0; i <= 7; i++, j++) { 646 if (pm8001_ha->chip_id == chip_8001) { 647 if (deviceid == 0x8081) 648 pm8001_ha->sas_addr[j] = 649 payload.func_specific[0x704 + i]; 650 } else 651 pm8001_ha->sas_addr[j] = 652 payload.func_specific[0x804 + i]; 653 } 654 655 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 656 memcpy(&pm8001_ha->phy[i].dev_sas_addr, 657 pm8001_ha->sas_addr, SAS_ADDR_SIZE); 658 PM8001_INIT_DBG(pm8001_ha, 659 pm8001_printk("phy %d sas_addr = %016llx\n", i, 660 pm8001_ha->phy[i].dev_sas_addr)); 661 } 662 #else 663 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 664 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL; 665 pm8001_ha->phy[i].dev_sas_addr = 666 cpu_to_be64((u64) 667 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr)); 668 } 669 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr, 670 SAS_ADDR_SIZE); 671 #endif 672 } 673 674 /* 675 * pm8001_get_phy_settings_info : Read phy setting values. 676 * @pm8001_ha : our hba. 677 */ 678 void pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha) 679 { 680 681 #ifdef PM8001_READ_VPD 682 /*OPTION ROM FLASH read for the SPC cards */ 683 DECLARE_COMPLETION_ONSTACK(completion); 684 struct pm8001_ioctl_payload payload; 685 686 pm8001_ha->nvmd_completion = &completion; 687 /* SAS ADDRESS read from flash / EEPROM */ 688 payload.minor_function = 6; 689 payload.offset = 0; 690 payload.length = 4096; 691 payload.func_specific = kzalloc(4096, GFP_KERNEL); 692 /* Read phy setting values from flash */ 693 PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload); 694 wait_for_completion(&completion); 695 pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific); 696 #endif 697 } 698 699 #ifdef PM8001_USE_MSIX 700 /** 701 * pm8001_setup_msix - enable MSI-X interrupt 702 * @chip_info: our ha struct. 703 * @irq_handler: irq_handler 704 */ 705 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha) 706 { 707 u32 i = 0, j = 0; 708 u32 number_of_intr; 709 int flag = 0; 710 u32 max_entry; 711 int rc; 712 static char intr_drvname[PM8001_MAX_MSIX_VEC][sizeof(DRV_NAME)+3]; 713 714 /* SPCv controllers supports 64 msi-x */ 715 if (pm8001_ha->chip_id == chip_8001) { 716 number_of_intr = 1; 717 flag |= IRQF_DISABLED; 718 } else { 719 number_of_intr = PM8001_MAX_MSIX_VEC; 720 flag &= ~IRQF_SHARED; 721 flag |= IRQF_DISABLED; 722 } 723 724 max_entry = sizeof(pm8001_ha->msix_entries) / 725 sizeof(pm8001_ha->msix_entries[0]); 726 for (i = 0; i < max_entry ; i++) 727 pm8001_ha->msix_entries[i].entry = i; 728 rc = pci_enable_msix(pm8001_ha->pdev, pm8001_ha->msix_entries, 729 number_of_intr); 730 pm8001_ha->number_of_intr = number_of_intr; 731 if (!rc) { 732 PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 733 "pci_enable_msix request ret:%d no of intr %d\n", 734 rc, pm8001_ha->number_of_intr)); 735 736 for (i = 0; i < number_of_intr; i++) 737 pm8001_ha->outq[i] = i; 738 739 for (i = 0; i < number_of_intr; i++) { 740 snprintf(intr_drvname[i], sizeof(intr_drvname[0]), 741 DRV_NAME"%d", i); 742 if (request_irq(pm8001_ha->msix_entries[i].vector, 743 pm8001_interrupt_handler_msix, flag, 744 intr_drvname[i], &pm8001_ha->outq[i])) { 745 for (j = 0; j < i; j++) 746 free_irq( 747 pm8001_ha->msix_entries[j].vector, 748 &pm8001_ha->outq[j]); 749 pci_disable_msix(pm8001_ha->pdev); 750 break; 751 } 752 } 753 } 754 return rc; 755 } 756 #endif 757 758 /** 759 * pm8001_request_irq - register interrupt 760 * @chip_info: our ha struct. 761 */ 762 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha) 763 { 764 struct pci_dev *pdev; 765 int rc; 766 767 pdev = pm8001_ha->pdev; 768 769 #ifdef PM8001_USE_MSIX 770 if (pdev->msix_cap) 771 return pm8001_setup_msix(pm8001_ha); 772 else { 773 PM8001_INIT_DBG(pm8001_ha, 774 pm8001_printk("MSIX not supported!!!\n")); 775 goto intx; 776 } 777 #endif 778 779 intx: 780 /* initialize the INT-X interrupt */ 781 rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED, 782 DRV_NAME, SHOST_TO_SAS_HA(pm8001_ha->shost)); 783 return rc; 784 } 785 786 /** 787 * pm8001_pci_probe - probe supported device 788 * @pdev: pci device which kernel has been prepared for. 789 * @ent: pci device id 790 * 791 * This function is the main initialization function, when register a new 792 * pci driver it is invoked, all struct an hardware initilization should be done 793 * here, also, register interrupt 794 */ 795 static int pm8001_pci_probe(struct pci_dev *pdev, 796 const struct pci_device_id *ent) 797 { 798 unsigned int rc; 799 u32 pci_reg; 800 u8 i = 0; 801 struct pm8001_hba_info *pm8001_ha; 802 struct Scsi_Host *shost = NULL; 803 const struct pm8001_chip_info *chip; 804 805 dev_printk(KERN_INFO, &pdev->dev, 806 "pm80xx: driver version %s\n", DRV_VERSION); 807 rc = pci_enable_device(pdev); 808 if (rc) 809 goto err_out_enable; 810 pci_set_master(pdev); 811 /* 812 * Enable pci slot busmaster by setting pci command register. 813 * This is required by FW for Cyclone card. 814 */ 815 816 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg); 817 pci_reg |= 0x157; 818 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg); 819 rc = pci_request_regions(pdev, DRV_NAME); 820 if (rc) 821 goto err_out_disable; 822 rc = pci_go_44(pdev); 823 if (rc) 824 goto err_out_regions; 825 826 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *)); 827 if (!shost) { 828 rc = -ENOMEM; 829 goto err_out_regions; 830 } 831 chip = &pm8001_chips[ent->driver_data]; 832 SHOST_TO_SAS_HA(shost) = 833 kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL); 834 if (!SHOST_TO_SAS_HA(shost)) { 835 rc = -ENOMEM; 836 goto err_out_free_host; 837 } 838 839 rc = pm8001_prep_sas_ha_init(shost, chip); 840 if (rc) { 841 rc = -ENOMEM; 842 goto err_out_free; 843 } 844 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost)); 845 /* ent->driver variable is used to differentiate between controllers */ 846 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost); 847 if (!pm8001_ha) { 848 rc = -ENOMEM; 849 goto err_out_free; 850 } 851 list_add_tail(&pm8001_ha->list, &hba_list); 852 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 853 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); 854 if (rc) { 855 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 856 "chip_init failed [ret: %d]\n", rc)); 857 goto err_out_ha_free; 858 } 859 860 rc = scsi_add_host(shost, &pdev->dev); 861 if (rc) 862 goto err_out_ha_free; 863 rc = pm8001_request_irq(pm8001_ha); 864 if (rc) { 865 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 866 "pm8001_request_irq failed [ret: %d]\n", rc)); 867 goto err_out_shost; 868 } 869 870 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0); 871 if (pm8001_ha->chip_id != chip_8001) { 872 for (i = 1; i < pm8001_ha->number_of_intr; i++) 873 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i); 874 /* setup thermal configuration. */ 875 pm80xx_set_thermal_config(pm8001_ha); 876 } 877 878 pm8001_init_sas_add(pm8001_ha); 879 /* phy setting support for motherboard controller */ 880 if (pdev->subsystem_vendor != PCI_VENDOR_ID_ADAPTEC2 && 881 pdev->subsystem_vendor != 0) 882 pm8001_get_phy_settings_info(pm8001_ha); 883 pm8001_post_sas_ha_init(shost, chip); 884 rc = sas_register_ha(SHOST_TO_SAS_HA(shost)); 885 if (rc) 886 goto err_out_shost; 887 scsi_scan_host(pm8001_ha->shost); 888 return 0; 889 890 err_out_shost: 891 scsi_remove_host(pm8001_ha->shost); 892 err_out_ha_free: 893 pm8001_free(pm8001_ha); 894 err_out_free: 895 kfree(SHOST_TO_SAS_HA(shost)); 896 err_out_free_host: 897 kfree(shost); 898 err_out_regions: 899 pci_release_regions(pdev); 900 err_out_disable: 901 pci_disable_device(pdev); 902 err_out_enable: 903 return rc; 904 } 905 906 static void pm8001_pci_remove(struct pci_dev *pdev) 907 { 908 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 909 struct pm8001_hba_info *pm8001_ha; 910 int i; 911 pm8001_ha = sha->lldd_ha; 912 sas_unregister_ha(sha); 913 sas_remove_host(pm8001_ha->shost); 914 list_del(&pm8001_ha->list); 915 scsi_remove_host(pm8001_ha->shost); 916 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 917 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 918 919 #ifdef PM8001_USE_MSIX 920 for (i = 0; i < pm8001_ha->number_of_intr; i++) 921 synchronize_irq(pm8001_ha->msix_entries[i].vector); 922 for (i = 0; i < pm8001_ha->number_of_intr; i++) 923 free_irq(pm8001_ha->msix_entries[i].vector, 924 &pm8001_ha->outq[i]); 925 pci_disable_msix(pdev); 926 #else 927 free_irq(pm8001_ha->irq, sha); 928 #endif 929 #ifdef PM8001_USE_TASKLET 930 tasklet_kill(&pm8001_ha->tasklet); 931 #endif 932 pm8001_free(pm8001_ha); 933 kfree(sha->sas_phy); 934 kfree(sha->sas_port); 935 kfree(sha); 936 pci_release_regions(pdev); 937 pci_disable_device(pdev); 938 } 939 940 /** 941 * pm8001_pci_suspend - power management suspend main entry point 942 * @pdev: PCI device struct 943 * @state: PM state change to (usually PCI_D3) 944 * 945 * Returns 0 success, anything else error. 946 */ 947 static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state) 948 { 949 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 950 struct pm8001_hba_info *pm8001_ha; 951 int i; 952 u32 device_state; 953 pm8001_ha = sha->lldd_ha; 954 flush_workqueue(pm8001_wq); 955 scsi_block_requests(pm8001_ha->shost); 956 if (!pdev->pm_cap) { 957 dev_err(&pdev->dev, " PCI PM not supported\n"); 958 return -ENODEV; 959 } 960 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 961 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 962 #ifdef PM8001_USE_MSIX 963 for (i = 0; i < pm8001_ha->number_of_intr; i++) 964 synchronize_irq(pm8001_ha->msix_entries[i].vector); 965 for (i = 0; i < pm8001_ha->number_of_intr; i++) 966 free_irq(pm8001_ha->msix_entries[i].vector, 967 &pm8001_ha->outq[i]); 968 pci_disable_msix(pdev); 969 #else 970 free_irq(pm8001_ha->irq, sha); 971 #endif 972 #ifdef PM8001_USE_TASKLET 973 tasklet_kill(&pm8001_ha->tasklet); 974 #endif 975 device_state = pci_choose_state(pdev, state); 976 pm8001_printk("pdev=0x%p, slot=%s, entering " 977 "operating state [D%d]\n", pdev, 978 pm8001_ha->name, device_state); 979 pci_save_state(pdev); 980 pci_disable_device(pdev); 981 pci_set_power_state(pdev, device_state); 982 return 0; 983 } 984 985 /** 986 * pm8001_pci_resume - power management resume main entry point 987 * @pdev: PCI device struct 988 * 989 * Returns 0 success, anything else error. 990 */ 991 static int pm8001_pci_resume(struct pci_dev *pdev) 992 { 993 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 994 struct pm8001_hba_info *pm8001_ha; 995 int rc; 996 u8 i = 0; 997 u32 device_state; 998 pm8001_ha = sha->lldd_ha; 999 device_state = pdev->current_state; 1000 1001 pm8001_printk("pdev=0x%p, slot=%s, resuming from previous " 1002 "operating state [D%d]\n", pdev, pm8001_ha->name, device_state); 1003 1004 pci_set_power_state(pdev, PCI_D0); 1005 pci_enable_wake(pdev, PCI_D0, 0); 1006 pci_restore_state(pdev); 1007 rc = pci_enable_device(pdev); 1008 if (rc) { 1009 pm8001_printk("slot=%s Enable device failed during resume\n", 1010 pm8001_ha->name); 1011 goto err_out_enable; 1012 } 1013 1014 pci_set_master(pdev); 1015 rc = pci_go_44(pdev); 1016 if (rc) 1017 goto err_out_disable; 1018 1019 /* chip soft rst only for spc */ 1020 if (pm8001_ha->chip_id == chip_8001) { 1021 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1022 PM8001_INIT_DBG(pm8001_ha, 1023 pm8001_printk("chip soft reset successful\n")); 1024 } 1025 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); 1026 if (rc) 1027 goto err_out_disable; 1028 1029 /* disable all the interrupt bits */ 1030 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1031 1032 rc = pm8001_request_irq(pm8001_ha); 1033 if (rc) 1034 goto err_out_disable; 1035 #ifdef PM8001_USE_TASKLET 1036 /* default tasklet for non msi-x interrupt handler/first msi-x 1037 * interrupt handler */ 1038 tasklet_init(&pm8001_ha->tasklet, pm8001_tasklet, 1039 (unsigned long)pm8001_ha); 1040 #endif 1041 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0); 1042 if (pm8001_ha->chip_id != chip_8001) { 1043 for (i = 1; i < pm8001_ha->number_of_intr; i++) 1044 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i); 1045 } 1046 scsi_unblock_requests(pm8001_ha->shost); 1047 return 0; 1048 1049 err_out_disable: 1050 scsi_remove_host(pm8001_ha->shost); 1051 pci_disable_device(pdev); 1052 err_out_enable: 1053 return rc; 1054 } 1055 1056 /* update of pci device, vendor id and driver data with 1057 * unique value for each of the controller 1058 */ 1059 static struct pci_device_id pm8001_pci_table[] = { 1060 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 }, 1061 { 1062 PCI_DEVICE(0x117c, 0x0042), 1063 .driver_data = chip_8001 1064 }, 1065 /* Support for SPC/SPCv/SPCve controllers */ 1066 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 }, 1067 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 }, 1068 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 }, 1069 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 }, 1070 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 }, 1071 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 }, 1072 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 }, 1073 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 }, 1074 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 }, 1075 { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 }, 1076 { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 }, 1077 { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 }, 1078 { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 }, 1079 { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 }, 1080 { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 }, 1081 { PCI_VENDOR_ID_ADAPTEC2, 0x8081, 1082 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 }, 1083 { PCI_VENDOR_ID_ADAPTEC2, 0x8081, 1084 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 }, 1085 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1086 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 }, 1087 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1088 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 }, 1089 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1090 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 }, 1091 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1092 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 }, 1093 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1094 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 }, 1095 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1096 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 }, 1097 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1098 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 }, 1099 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1100 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 }, 1101 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1102 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 }, 1103 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1104 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 }, 1105 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1106 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 }, 1107 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1108 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 }, 1109 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1110 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 }, 1111 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1112 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 }, 1113 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1114 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 }, 1115 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1116 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 }, 1117 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1118 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 }, 1119 {} /* terminate list */ 1120 }; 1121 1122 static struct pci_driver pm8001_pci_driver = { 1123 .name = DRV_NAME, 1124 .id_table = pm8001_pci_table, 1125 .probe = pm8001_pci_probe, 1126 .remove = pm8001_pci_remove, 1127 .suspend = pm8001_pci_suspend, 1128 .resume = pm8001_pci_resume, 1129 }; 1130 1131 /** 1132 * pm8001_init - initialize scsi transport template 1133 */ 1134 static int __init pm8001_init(void) 1135 { 1136 int rc = -ENOMEM; 1137 1138 pm8001_wq = alloc_workqueue("pm80xx", 0, 0); 1139 if (!pm8001_wq) 1140 goto err; 1141 1142 pm8001_id = 0; 1143 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops); 1144 if (!pm8001_stt) 1145 goto err_wq; 1146 rc = pci_register_driver(&pm8001_pci_driver); 1147 if (rc) 1148 goto err_tp; 1149 return 0; 1150 1151 err_tp: 1152 sas_release_transport(pm8001_stt); 1153 err_wq: 1154 destroy_workqueue(pm8001_wq); 1155 err: 1156 return rc; 1157 } 1158 1159 static void __exit pm8001_exit(void) 1160 { 1161 pci_unregister_driver(&pm8001_pci_driver); 1162 sas_release_transport(pm8001_stt); 1163 destroy_workqueue(pm8001_wq); 1164 } 1165 1166 module_init(pm8001_init); 1167 module_exit(pm8001_exit); 1168 1169 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>"); 1170 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>"); 1171 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>"); 1172 MODULE_DESCRIPTION( 1173 "PMC-Sierra PM8001/8081/8088/8089/8074/8076/8077 " 1174 "SAS/SATA controller driver"); 1175 MODULE_VERSION(DRV_VERSION); 1176 MODULE_LICENSE("GPL"); 1177 MODULE_DEVICE_TABLE(pci, pm8001_pci_table); 1178 1179