1 /* 2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 USI Co., Ltd. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 41 #include <linux/slab.h> 42 #include "pm8001_sas.h" 43 #include "pm8001_chips.h" 44 #include "pm80xx_hwi.h" 45 46 static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING; 47 module_param(logging_level, ulong, 0644); 48 MODULE_PARM_DESC(logging_level, " bits for enabling logging info."); 49 50 static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120; 51 module_param(link_rate, ulong, 0644); 52 MODULE_PARM_DESC(link_rate, "Enable link rate.\n" 53 " 1: Link rate 1.5G\n" 54 " 2: Link rate 3.0G\n" 55 " 4: Link rate 6.0G\n" 56 " 8: Link rate 12.0G\n"); 57 58 static struct scsi_transport_template *pm8001_stt; 59 static int pm8001_init_ccb_tag(struct pm8001_hba_info *); 60 61 /* 62 * chip info structure to identify chip key functionality as 63 * encryption available/not, no of ports, hw specific function ref 64 */ 65 static const struct pm8001_chip_info pm8001_chips[] = { 66 [chip_8001] = {0, 8, &pm8001_8001_dispatch,}, 67 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,}, 68 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,}, 69 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,}, 70 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,}, 71 [chip_8074] = {0, 8, &pm8001_80xx_dispatch,}, 72 [chip_8076] = {0, 16, &pm8001_80xx_dispatch,}, 73 [chip_8077] = {0, 16, &pm8001_80xx_dispatch,}, 74 [chip_8006] = {0, 16, &pm8001_80xx_dispatch,}, 75 [chip_8070] = {0, 8, &pm8001_80xx_dispatch,}, 76 [chip_8072] = {0, 16, &pm8001_80xx_dispatch,}, 77 }; 78 static int pm8001_id; 79 80 LIST_HEAD(hba_list); 81 82 struct workqueue_struct *pm8001_wq; 83 84 static void pm8001_map_queues(struct Scsi_Host *shost) 85 { 86 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 87 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 88 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT]; 89 90 if (pm8001_ha->number_of_intr > 1) 91 blk_mq_pci_map_queues(qmap, pm8001_ha->pdev, 1); 92 93 return blk_mq_map_queues(qmap); 94 } 95 96 /* 97 * The main structure which LLDD must register for scsi core. 98 */ 99 static struct scsi_host_template pm8001_sht = { 100 .module = THIS_MODULE, 101 .name = DRV_NAME, 102 .proc_name = DRV_NAME, 103 .queuecommand = sas_queuecommand, 104 .dma_need_drain = ata_scsi_dma_need_drain, 105 .target_alloc = sas_target_alloc, 106 .slave_configure = sas_slave_configure, 107 .scan_finished = pm8001_scan_finished, 108 .scan_start = pm8001_scan_start, 109 .change_queue_depth = sas_change_queue_depth, 110 .bios_param = sas_bios_param, 111 .can_queue = 1, 112 .this_id = -1, 113 .sg_tablesize = PM8001_MAX_DMA_SG, 114 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 115 .eh_device_reset_handler = sas_eh_device_reset_handler, 116 .eh_target_reset_handler = sas_eh_target_reset_handler, 117 .slave_alloc = sas_slave_alloc, 118 .target_destroy = sas_target_destroy, 119 .ioctl = sas_ioctl, 120 #ifdef CONFIG_COMPAT 121 .compat_ioctl = sas_ioctl, 122 #endif 123 .shost_groups = pm8001_host_groups, 124 .track_queue_depth = 1, 125 .cmd_per_lun = 32, 126 .map_queues = pm8001_map_queues, 127 }; 128 129 /* 130 * Sas layer call this function to execute specific task. 131 */ 132 static struct sas_domain_function_template pm8001_transport_ops = { 133 .lldd_dev_found = pm8001_dev_found, 134 .lldd_dev_gone = pm8001_dev_gone, 135 136 .lldd_execute_task = pm8001_queue_command, 137 .lldd_control_phy = pm8001_phy_control, 138 139 .lldd_abort_task = pm8001_abort_task, 140 .lldd_abort_task_set = sas_abort_task_set, 141 .lldd_clear_task_set = pm8001_clear_task_set, 142 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset, 143 .lldd_lu_reset = pm8001_lu_reset, 144 .lldd_query_task = pm8001_query_task, 145 .lldd_port_formed = pm8001_port_formed, 146 .lldd_tmf_exec_complete = pm8001_setds_completion, 147 .lldd_tmf_aborted = pm8001_tmf_aborted, 148 }; 149 150 /** 151 * pm8001_phy_init - initiate our adapter phys 152 * @pm8001_ha: our hba structure. 153 * @phy_id: phy id. 154 */ 155 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id) 156 { 157 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 158 struct asd_sas_phy *sas_phy = &phy->sas_phy; 159 phy->phy_state = PHY_LINK_DISABLE; 160 phy->pm8001_ha = pm8001_ha; 161 phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS; 162 phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS; 163 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0; 164 sas_phy->class = SAS; 165 sas_phy->iproto = SAS_PROTOCOL_ALL; 166 sas_phy->tproto = 0; 167 sas_phy->type = PHY_TYPE_PHYSICAL; 168 sas_phy->role = PHY_ROLE_INITIATOR; 169 sas_phy->oob_mode = OOB_NOT_CONNECTED; 170 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN; 171 sas_phy->id = phy_id; 172 sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr; 173 sas_phy->frame_rcvd = &phy->frame_rcvd[0]; 174 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata; 175 sas_phy->lldd_phy = phy; 176 } 177 178 /** 179 * pm8001_free - free hba 180 * @pm8001_ha: our hba structure. 181 */ 182 static void pm8001_free(struct pm8001_hba_info *pm8001_ha) 183 { 184 int i; 185 186 if (!pm8001_ha) 187 return; 188 189 for (i = 0; i < USI_MAX_MEMCNT; i++) { 190 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) { 191 dma_free_coherent(&pm8001_ha->pdev->dev, 192 (pm8001_ha->memoryMap.region[i].total_len + 193 pm8001_ha->memoryMap.region[i].alignment), 194 pm8001_ha->memoryMap.region[i].virt_ptr, 195 pm8001_ha->memoryMap.region[i].phys_addr); 196 } 197 } 198 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha); 199 flush_workqueue(pm8001_wq); 200 bitmap_free(pm8001_ha->tags); 201 kfree(pm8001_ha); 202 } 203 204 #ifdef PM8001_USE_TASKLET 205 206 /** 207 * pm8001_tasklet() - tasklet for 64 msi-x interrupt handler 208 * @opaque: the passed general host adapter struct 209 * Note: pm8001_tasklet is common for pm8001 & pm80xx 210 */ 211 static void pm8001_tasklet(unsigned long opaque) 212 { 213 struct pm8001_hba_info *pm8001_ha; 214 struct isr_param *irq_vector; 215 216 irq_vector = (struct isr_param *)opaque; 217 pm8001_ha = irq_vector->drv_inst; 218 if (unlikely(!pm8001_ha)) 219 BUG_ON(1); 220 PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id); 221 } 222 #endif 223 224 /** 225 * pm8001_interrupt_handler_msix - main MSIX interrupt handler. 226 * It obtains the vector number and calls the equivalent bottom 227 * half or services directly. 228 * @irq: interrupt number 229 * @opaque: the passed outbound queue/vector. Host structure is 230 * retrieved from the same. 231 */ 232 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque) 233 { 234 struct isr_param *irq_vector; 235 struct pm8001_hba_info *pm8001_ha; 236 irqreturn_t ret = IRQ_HANDLED; 237 irq_vector = (struct isr_param *)opaque; 238 pm8001_ha = irq_vector->drv_inst; 239 240 if (unlikely(!pm8001_ha)) 241 return IRQ_NONE; 242 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha)) 243 return IRQ_NONE; 244 #ifdef PM8001_USE_TASKLET 245 tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]); 246 #else 247 ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id); 248 #endif 249 return ret; 250 } 251 252 /** 253 * pm8001_interrupt_handler_intx - main INTx interrupt handler. 254 * @irq: interrupt number 255 * @dev_id: sas_ha structure. The HBA is retrieved from sas_ha structure. 256 */ 257 258 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id) 259 { 260 struct pm8001_hba_info *pm8001_ha; 261 irqreturn_t ret = IRQ_HANDLED; 262 struct sas_ha_struct *sha = dev_id; 263 pm8001_ha = sha->lldd_ha; 264 if (unlikely(!pm8001_ha)) 265 return IRQ_NONE; 266 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha)) 267 return IRQ_NONE; 268 269 #ifdef PM8001_USE_TASKLET 270 tasklet_schedule(&pm8001_ha->tasklet[0]); 271 #else 272 ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0); 273 #endif 274 return ret; 275 } 276 277 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha); 278 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha); 279 280 /** 281 * pm8001_alloc - initiate our hba structure and 6 DMAs area. 282 * @pm8001_ha: our hba structure. 283 * @ent: PCI device ID structure to match on 284 */ 285 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha, 286 const struct pci_device_id *ent) 287 { 288 int i, count = 0, rc = 0; 289 u32 ci_offset, ib_offset, ob_offset, pi_offset; 290 struct inbound_queue_table *ibq; 291 struct outbound_queue_table *obq; 292 293 spin_lock_init(&pm8001_ha->lock); 294 spin_lock_init(&pm8001_ha->bitmap_lock); 295 pm8001_dbg(pm8001_ha, INIT, "pm8001_alloc: PHY:%x\n", 296 pm8001_ha->chip->n_phy); 297 298 /* Setup Interrupt */ 299 rc = pm8001_setup_irq(pm8001_ha); 300 if (rc) { 301 pm8001_dbg(pm8001_ha, FAIL, 302 "pm8001_setup_irq failed [ret: %d]\n", rc); 303 goto err_out; 304 } 305 /* Request Interrupt */ 306 rc = pm8001_request_irq(pm8001_ha); 307 if (rc) 308 goto err_out; 309 310 count = pm8001_ha->max_q_num; 311 /* Queues are chosen based on the number of cores/msix availability */ 312 ib_offset = pm8001_ha->ib_offset = USI_MAX_MEMCNT_BASE; 313 ci_offset = pm8001_ha->ci_offset = ib_offset + count; 314 ob_offset = pm8001_ha->ob_offset = ci_offset + count; 315 pi_offset = pm8001_ha->pi_offset = ob_offset + count; 316 pm8001_ha->max_memcnt = pi_offset + count; 317 318 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 319 pm8001_phy_init(pm8001_ha, i); 320 pm8001_ha->port[i].wide_port_phymap = 0; 321 pm8001_ha->port[i].port_attached = 0; 322 pm8001_ha->port[i].port_state = 0; 323 INIT_LIST_HEAD(&pm8001_ha->port[i].list); 324 } 325 326 /* MPI Memory region 1 for AAP Event Log for fw */ 327 pm8001_ha->memoryMap.region[AAP1].num_elements = 1; 328 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE; 329 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE; 330 pm8001_ha->memoryMap.region[AAP1].alignment = 32; 331 332 /* MPI Memory region 2 for IOP Event Log for fw */ 333 pm8001_ha->memoryMap.region[IOP].num_elements = 1; 334 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE; 335 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE; 336 pm8001_ha->memoryMap.region[IOP].alignment = 32; 337 338 for (i = 0; i < count; i++) { 339 ibq = &pm8001_ha->inbnd_q_tbl[i]; 340 spin_lock_init(&ibq->iq_lock); 341 /* MPI Memory region 3 for consumer Index of inbound queues */ 342 pm8001_ha->memoryMap.region[ci_offset+i].num_elements = 1; 343 pm8001_ha->memoryMap.region[ci_offset+i].element_size = 4; 344 pm8001_ha->memoryMap.region[ci_offset+i].total_len = 4; 345 pm8001_ha->memoryMap.region[ci_offset+i].alignment = 4; 346 347 if ((ent->driver_data) != chip_8001) { 348 /* MPI Memory region 5 inbound queues */ 349 pm8001_ha->memoryMap.region[ib_offset+i].num_elements = 350 PM8001_MPI_QUEUE; 351 pm8001_ha->memoryMap.region[ib_offset+i].element_size 352 = 128; 353 pm8001_ha->memoryMap.region[ib_offset+i].total_len = 354 PM8001_MPI_QUEUE * 128; 355 pm8001_ha->memoryMap.region[ib_offset+i].alignment 356 = 128; 357 } else { 358 pm8001_ha->memoryMap.region[ib_offset+i].num_elements = 359 PM8001_MPI_QUEUE; 360 pm8001_ha->memoryMap.region[ib_offset+i].element_size 361 = 64; 362 pm8001_ha->memoryMap.region[ib_offset+i].total_len = 363 PM8001_MPI_QUEUE * 64; 364 pm8001_ha->memoryMap.region[ib_offset+i].alignment = 64; 365 } 366 } 367 368 for (i = 0; i < count; i++) { 369 obq = &pm8001_ha->outbnd_q_tbl[i]; 370 spin_lock_init(&obq->oq_lock); 371 /* MPI Memory region 4 for producer Index of outbound queues */ 372 pm8001_ha->memoryMap.region[pi_offset+i].num_elements = 1; 373 pm8001_ha->memoryMap.region[pi_offset+i].element_size = 4; 374 pm8001_ha->memoryMap.region[pi_offset+i].total_len = 4; 375 pm8001_ha->memoryMap.region[pi_offset+i].alignment = 4; 376 377 if (ent->driver_data != chip_8001) { 378 /* MPI Memory region 6 Outbound queues */ 379 pm8001_ha->memoryMap.region[ob_offset+i].num_elements = 380 PM8001_MPI_QUEUE; 381 pm8001_ha->memoryMap.region[ob_offset+i].element_size 382 = 128; 383 pm8001_ha->memoryMap.region[ob_offset+i].total_len = 384 PM8001_MPI_QUEUE * 128; 385 pm8001_ha->memoryMap.region[ob_offset+i].alignment 386 = 128; 387 } else { 388 /* MPI Memory region 6 Outbound queues */ 389 pm8001_ha->memoryMap.region[ob_offset+i].num_elements = 390 PM8001_MPI_QUEUE; 391 pm8001_ha->memoryMap.region[ob_offset+i].element_size 392 = 64; 393 pm8001_ha->memoryMap.region[ob_offset+i].total_len = 394 PM8001_MPI_QUEUE * 64; 395 pm8001_ha->memoryMap.region[ob_offset+i].alignment = 64; 396 } 397 398 } 399 /* Memory region write DMA*/ 400 pm8001_ha->memoryMap.region[NVMD].num_elements = 1; 401 pm8001_ha->memoryMap.region[NVMD].element_size = 4096; 402 pm8001_ha->memoryMap.region[NVMD].total_len = 4096; 403 404 /* Memory region for fw flash */ 405 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096; 406 407 pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1; 408 pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000; 409 pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000; 410 pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000; 411 for (i = 0; i < pm8001_ha->max_memcnt; i++) { 412 struct mpi_mem *region = &pm8001_ha->memoryMap.region[i]; 413 414 if (pm8001_mem_alloc(pm8001_ha->pdev, 415 ®ion->virt_ptr, 416 ®ion->phys_addr, 417 ®ion->phys_addr_hi, 418 ®ion->phys_addr_lo, 419 region->total_len, 420 region->alignment) != 0) { 421 pm8001_dbg(pm8001_ha, FAIL, "Mem%d alloc failed\n", i); 422 goto err_out; 423 } 424 } 425 426 /* Memory region for devices*/ 427 pm8001_ha->devices = kzalloc(PM8001_MAX_DEVICES 428 * sizeof(struct pm8001_device), GFP_KERNEL); 429 if (!pm8001_ha->devices) { 430 rc = -ENOMEM; 431 goto err_out_nodev; 432 } 433 for (i = 0; i < PM8001_MAX_DEVICES; i++) { 434 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED; 435 pm8001_ha->devices[i].id = i; 436 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES; 437 atomic_set(&pm8001_ha->devices[i].running_req, 0); 438 } 439 pm8001_ha->flags = PM8001F_INIT_TIME; 440 /* Initialize tags */ 441 pm8001_tag_init(pm8001_ha); 442 return 0; 443 444 err_out_nodev: 445 for (i = 0; i < pm8001_ha->max_memcnt; i++) { 446 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) { 447 dma_free_coherent(&pm8001_ha->pdev->dev, 448 (pm8001_ha->memoryMap.region[i].total_len + 449 pm8001_ha->memoryMap.region[i].alignment), 450 pm8001_ha->memoryMap.region[i].virt_ptr, 451 pm8001_ha->memoryMap.region[i].phys_addr); 452 } 453 } 454 err_out: 455 return 1; 456 } 457 458 /** 459 * pm8001_ioremap - remap the pci high physical address to kernel virtual 460 * address so that we can access them. 461 * @pm8001_ha: our hba structure. 462 */ 463 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha) 464 { 465 u32 bar; 466 u32 logicalBar = 0; 467 struct pci_dev *pdev; 468 469 pdev = pm8001_ha->pdev; 470 /* map pci mem (PMC pci base 0-3)*/ 471 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { 472 /* 473 ** logical BARs for SPC: 474 ** bar 0 and 1 - logical BAR0 475 ** bar 2 and 3 - logical BAR1 476 ** bar4 - logical BAR2 477 ** bar5 - logical BAR3 478 ** Skip the appropriate assignments: 479 */ 480 if ((bar == 1) || (bar == 3)) 481 continue; 482 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { 483 pm8001_ha->io_mem[logicalBar].membase = 484 pci_resource_start(pdev, bar); 485 pm8001_ha->io_mem[logicalBar].memsize = 486 pci_resource_len(pdev, bar); 487 pm8001_ha->io_mem[logicalBar].memvirtaddr = 488 ioremap(pm8001_ha->io_mem[logicalBar].membase, 489 pm8001_ha->io_mem[logicalBar].memsize); 490 if (!pm8001_ha->io_mem[logicalBar].memvirtaddr) { 491 pm8001_dbg(pm8001_ha, INIT, 492 "Failed to ioremap bar %d, logicalBar %d", 493 bar, logicalBar); 494 return -ENOMEM; 495 } 496 pm8001_dbg(pm8001_ha, INIT, 497 "base addr %llx virt_addr=%llx len=%d\n", 498 (u64)pm8001_ha->io_mem[logicalBar].membase, 499 (u64)(unsigned long) 500 pm8001_ha->io_mem[logicalBar].memvirtaddr, 501 pm8001_ha->io_mem[logicalBar].memsize); 502 } else { 503 pm8001_ha->io_mem[logicalBar].membase = 0; 504 pm8001_ha->io_mem[logicalBar].memsize = 0; 505 pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL; 506 } 507 logicalBar++; 508 } 509 return 0; 510 } 511 512 /** 513 * pm8001_pci_alloc - initialize our ha card structure 514 * @pdev: pci device. 515 * @ent: ent 516 * @shost: scsi host struct which has been initialized before. 517 */ 518 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev, 519 const struct pci_device_id *ent, 520 struct Scsi_Host *shost) 521 522 { 523 struct pm8001_hba_info *pm8001_ha; 524 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 525 int j; 526 527 pm8001_ha = sha->lldd_ha; 528 if (!pm8001_ha) 529 return NULL; 530 531 pm8001_ha->pdev = pdev; 532 pm8001_ha->dev = &pdev->dev; 533 pm8001_ha->chip_id = ent->driver_data; 534 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id]; 535 pm8001_ha->irq = pdev->irq; 536 pm8001_ha->sas = sha; 537 pm8001_ha->shost = shost; 538 pm8001_ha->id = pm8001_id++; 539 pm8001_ha->logging_level = logging_level; 540 pm8001_ha->non_fatal_count = 0; 541 if (link_rate >= 1 && link_rate <= 15) 542 pm8001_ha->link_rate = (link_rate << 8); 543 else { 544 pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 | 545 LINKRATE_60 | LINKRATE_120; 546 pm8001_dbg(pm8001_ha, FAIL, 547 "Setting link rate to default value\n"); 548 } 549 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id); 550 /* IOMB size is 128 for 8088/89 controllers */ 551 if (pm8001_ha->chip_id != chip_8001) 552 pm8001_ha->iomb_size = IOMB_SIZE_SPCV; 553 else 554 pm8001_ha->iomb_size = IOMB_SIZE_SPC; 555 556 #ifdef PM8001_USE_TASKLET 557 /* Tasklet for non msi-x interrupt handler */ 558 if ((!pdev->msix_cap || !pci_msi_enabled()) 559 || (pm8001_ha->chip_id == chip_8001)) 560 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet, 561 (unsigned long)&(pm8001_ha->irq_vector[0])); 562 else 563 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 564 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet, 565 (unsigned long)&(pm8001_ha->irq_vector[j])); 566 #endif 567 if (pm8001_ioremap(pm8001_ha)) 568 goto failed_pci_alloc; 569 if (!pm8001_alloc(pm8001_ha, ent)) 570 return pm8001_ha; 571 failed_pci_alloc: 572 pm8001_free(pm8001_ha); 573 return NULL; 574 } 575 576 /** 577 * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit 578 * @pdev: pci device. 579 */ 580 static int pci_go_44(struct pci_dev *pdev) 581 { 582 int rc; 583 584 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44)); 585 if (rc) { 586 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 587 if (rc) 588 dev_printk(KERN_ERR, &pdev->dev, 589 "32-bit DMA enable failed\n"); 590 } 591 return rc; 592 } 593 594 /** 595 * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them. 596 * @shost: scsi host which has been allocated outside. 597 * @chip_info: our ha struct. 598 */ 599 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost, 600 const struct pm8001_chip_info *chip_info) 601 { 602 int phy_nr, port_nr; 603 struct asd_sas_phy **arr_phy; 604 struct asd_sas_port **arr_port; 605 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 606 607 phy_nr = chip_info->n_phy; 608 port_nr = phy_nr; 609 memset(sha, 0x00, sizeof(*sha)); 610 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL); 611 if (!arr_phy) 612 goto exit; 613 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL); 614 if (!arr_port) 615 goto exit_free2; 616 617 sha->sas_phy = arr_phy; 618 sha->sas_port = arr_port; 619 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL); 620 if (!sha->lldd_ha) 621 goto exit_free1; 622 623 shost->transportt = pm8001_stt; 624 shost->max_id = PM8001_MAX_DEVICES; 625 shost->unique_id = pm8001_id; 626 shost->max_cmd_len = 16; 627 return 0; 628 exit_free1: 629 kfree(arr_port); 630 exit_free2: 631 kfree(arr_phy); 632 exit: 633 return -1; 634 } 635 636 /** 637 * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas 638 * @shost: scsi host which has been allocated outside 639 * @chip_info: our ha struct. 640 */ 641 static void pm8001_post_sas_ha_init(struct Scsi_Host *shost, 642 const struct pm8001_chip_info *chip_info) 643 { 644 int i = 0; 645 struct pm8001_hba_info *pm8001_ha; 646 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 647 648 pm8001_ha = sha->lldd_ha; 649 for (i = 0; i < chip_info->n_phy; i++) { 650 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy; 651 sha->sas_port[i] = &pm8001_ha->port[i].sas_port; 652 sha->sas_phy[i]->sas_addr = 653 (u8 *)&pm8001_ha->phy[i].dev_sas_addr; 654 } 655 sha->sas_ha_name = DRV_NAME; 656 sha->dev = pm8001_ha->dev; 657 sha->strict_wide_ports = 1; 658 sha->lldd_module = THIS_MODULE; 659 sha->sas_addr = &pm8001_ha->sas_addr[0]; 660 sha->num_phys = chip_info->n_phy; 661 sha->core.shost = shost; 662 } 663 664 /** 665 * pm8001_init_sas_add - initialize sas address 666 * @pm8001_ha: our ha struct. 667 * 668 * Currently we just set the fixed SAS address to our HBA, for manufacture, 669 * it should read from the EEPROM 670 */ 671 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha) 672 { 673 u8 i, j; 674 u8 sas_add[8]; 675 #ifdef PM8001_READ_VPD 676 /* For new SPC controllers WWN is stored in flash vpd 677 * For SPC/SPCve controllers WWN is stored in EEPROM 678 * For Older SPC WWN is stored in NVMD 679 */ 680 DECLARE_COMPLETION_ONSTACK(completion); 681 struct pm8001_ioctl_payload payload; 682 u16 deviceid; 683 int rc; 684 685 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid); 686 pm8001_ha->nvmd_completion = &completion; 687 688 if (pm8001_ha->chip_id == chip_8001) { 689 if (deviceid == 0x8081 || deviceid == 0x0042) { 690 payload.minor_function = 4; 691 payload.rd_length = 4096; 692 } else { 693 payload.minor_function = 0; 694 payload.rd_length = 128; 695 } 696 } else if ((pm8001_ha->chip_id == chip_8070 || 697 pm8001_ha->chip_id == chip_8072) && 698 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) { 699 payload.minor_function = 4; 700 payload.rd_length = 4096; 701 } else { 702 payload.minor_function = 1; 703 payload.rd_length = 4096; 704 } 705 payload.offset = 0; 706 payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL); 707 if (!payload.func_specific) { 708 pm8001_dbg(pm8001_ha, INIT, "mem alloc fail\n"); 709 return; 710 } 711 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload); 712 if (rc) { 713 kfree(payload.func_specific); 714 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n"); 715 return; 716 } 717 wait_for_completion(&completion); 718 719 for (i = 0, j = 0; i <= 7; i++, j++) { 720 if (pm8001_ha->chip_id == chip_8001) { 721 if (deviceid == 0x8081) 722 pm8001_ha->sas_addr[j] = 723 payload.func_specific[0x704 + i]; 724 else if (deviceid == 0x0042) 725 pm8001_ha->sas_addr[j] = 726 payload.func_specific[0x010 + i]; 727 } else if ((pm8001_ha->chip_id == chip_8070 || 728 pm8001_ha->chip_id == chip_8072) && 729 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) { 730 pm8001_ha->sas_addr[j] = 731 payload.func_specific[0x010 + i]; 732 } else 733 pm8001_ha->sas_addr[j] = 734 payload.func_specific[0x804 + i]; 735 } 736 memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE); 737 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 738 if (i && ((i % 4) == 0)) 739 sas_add[7] = sas_add[7] + 4; 740 memcpy(&pm8001_ha->phy[i].dev_sas_addr, 741 sas_add, SAS_ADDR_SIZE); 742 pm8001_dbg(pm8001_ha, INIT, "phy %d sas_addr = %016llx\n", i, 743 pm8001_ha->phy[i].dev_sas_addr); 744 } 745 kfree(payload.func_specific); 746 #else 747 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 748 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL; 749 pm8001_ha->phy[i].dev_sas_addr = 750 cpu_to_be64((u64) 751 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr)); 752 } 753 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr, 754 SAS_ADDR_SIZE); 755 #endif 756 } 757 758 /* 759 * pm8001_get_phy_settings_info : Read phy setting values. 760 * @pm8001_ha : our hba. 761 */ 762 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha) 763 { 764 765 #ifdef PM8001_READ_VPD 766 /*OPTION ROM FLASH read for the SPC cards */ 767 DECLARE_COMPLETION_ONSTACK(completion); 768 struct pm8001_ioctl_payload payload; 769 int rc; 770 771 pm8001_ha->nvmd_completion = &completion; 772 /* SAS ADDRESS read from flash / EEPROM */ 773 payload.minor_function = 6; 774 payload.offset = 0; 775 payload.rd_length = 4096; 776 payload.func_specific = kzalloc(4096, GFP_KERNEL); 777 if (!payload.func_specific) 778 return -ENOMEM; 779 /* Read phy setting values from flash */ 780 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload); 781 if (rc) { 782 kfree(payload.func_specific); 783 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n"); 784 return -ENOMEM; 785 } 786 wait_for_completion(&completion); 787 pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific); 788 kfree(payload.func_specific); 789 #endif 790 return 0; 791 } 792 793 struct pm8001_mpi3_phy_pg_trx_config { 794 u32 LaneLosCfg; 795 u32 LanePgaCfg1; 796 u32 LanePisoCfg1; 797 u32 LanePisoCfg2; 798 u32 LanePisoCfg3; 799 u32 LanePisoCfg4; 800 u32 LanePisoCfg5; 801 u32 LanePisoCfg6; 802 u32 LaneBctCtrl; 803 }; 804 805 /** 806 * pm8001_get_internal_phy_settings - Retrieves the internal PHY settings 807 * @pm8001_ha : our adapter 808 * @phycfg : PHY config page to populate 809 */ 810 static 811 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha, 812 struct pm8001_mpi3_phy_pg_trx_config *phycfg) 813 { 814 phycfg->LaneLosCfg = 0x00000132; 815 phycfg->LanePgaCfg1 = 0x00203949; 816 phycfg->LanePisoCfg1 = 0x000000FF; 817 phycfg->LanePisoCfg2 = 0xFF000001; 818 phycfg->LanePisoCfg3 = 0xE7011300; 819 phycfg->LanePisoCfg4 = 0x631C40C0; 820 phycfg->LanePisoCfg5 = 0xF8102036; 821 phycfg->LanePisoCfg6 = 0xF74A1000; 822 phycfg->LaneBctCtrl = 0x00FB33F8; 823 } 824 825 /** 826 * pm8001_get_external_phy_settings - Retrieves the external PHY settings 827 * @pm8001_ha : our adapter 828 * @phycfg : PHY config page to populate 829 */ 830 static 831 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha, 832 struct pm8001_mpi3_phy_pg_trx_config *phycfg) 833 { 834 phycfg->LaneLosCfg = 0x00000132; 835 phycfg->LanePgaCfg1 = 0x00203949; 836 phycfg->LanePisoCfg1 = 0x000000FF; 837 phycfg->LanePisoCfg2 = 0xFF000001; 838 phycfg->LanePisoCfg3 = 0xE7011300; 839 phycfg->LanePisoCfg4 = 0x63349140; 840 phycfg->LanePisoCfg5 = 0xF8102036; 841 phycfg->LanePisoCfg6 = 0xF80D9300; 842 phycfg->LaneBctCtrl = 0x00FB33F8; 843 } 844 845 /** 846 * pm8001_get_phy_mask - Retrieves the mask that denotes if a PHY is int/ext 847 * @pm8001_ha : our adapter 848 * @phymask : The PHY mask 849 */ 850 static 851 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask) 852 { 853 switch (pm8001_ha->pdev->subsystem_device) { 854 case 0x0070: /* H1280 - 8 external 0 internal */ 855 case 0x0072: /* H12F0 - 16 external 0 internal */ 856 *phymask = 0x0000; 857 break; 858 859 case 0x0071: /* H1208 - 0 external 8 internal */ 860 case 0x0073: /* H120F - 0 external 16 internal */ 861 *phymask = 0xFFFF; 862 break; 863 864 case 0x0080: /* H1244 - 4 external 4 internal */ 865 *phymask = 0x00F0; 866 break; 867 868 case 0x0081: /* H1248 - 4 external 8 internal */ 869 *phymask = 0x0FF0; 870 break; 871 872 case 0x0082: /* H1288 - 8 external 8 internal */ 873 *phymask = 0xFF00; 874 break; 875 876 default: 877 pm8001_dbg(pm8001_ha, INIT, 878 "Unknown subsystem device=0x%.04x\n", 879 pm8001_ha->pdev->subsystem_device); 880 } 881 } 882 883 /** 884 * pm8001_set_phy_settings_ven_117c_12G() - Configure ATTO 12Gb PHY settings 885 * @pm8001_ha : our adapter 886 */ 887 static 888 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha) 889 { 890 struct pm8001_mpi3_phy_pg_trx_config phycfg_int; 891 struct pm8001_mpi3_phy_pg_trx_config phycfg_ext; 892 int phymask = 0; 893 int i = 0; 894 895 memset(&phycfg_int, 0, sizeof(phycfg_int)); 896 memset(&phycfg_ext, 0, sizeof(phycfg_ext)); 897 898 pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int); 899 pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext); 900 pm8001_get_phy_mask(pm8001_ha, &phymask); 901 902 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 903 if (phymask & (1 << i)) {/* Internal PHY */ 904 pm8001_set_phy_profile_single(pm8001_ha, i, 905 sizeof(phycfg_int) / sizeof(u32), 906 (u32 *)&phycfg_int); 907 908 } else { /* External PHY */ 909 pm8001_set_phy_profile_single(pm8001_ha, i, 910 sizeof(phycfg_ext) / sizeof(u32), 911 (u32 *)&phycfg_ext); 912 } 913 } 914 915 return 0; 916 } 917 918 /** 919 * pm8001_configure_phy_settings - Configures PHY settings based on vendor ID. 920 * @pm8001_ha : our hba. 921 */ 922 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha) 923 { 924 switch (pm8001_ha->pdev->subsystem_vendor) { 925 case PCI_VENDOR_ID_ATTO: 926 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */ 927 return 0; 928 else 929 return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha); 930 931 case PCI_VENDOR_ID_ADAPTEC2: 932 case 0: 933 return 0; 934 935 default: 936 return pm8001_get_phy_settings_info(pm8001_ha); 937 } 938 } 939 940 #ifdef PM8001_USE_MSIX 941 /** 942 * pm8001_setup_msix - enable MSI-X interrupt 943 * @pm8001_ha: our ha struct. 944 */ 945 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha) 946 { 947 unsigned int allocated_irq_vectors; 948 int rc; 949 950 /* SPCv controllers supports 64 msi-x */ 951 if (pm8001_ha->chip_id == chip_8001) { 952 rc = pci_alloc_irq_vectors(pm8001_ha->pdev, 1, 1, 953 PCI_IRQ_MSIX); 954 } else { 955 /* 956 * Queue index #0 is used always for housekeeping, so don't 957 * include in the affinity spreading. 958 */ 959 struct irq_affinity desc = { 960 .pre_vectors = 1, 961 }; 962 rc = pci_alloc_irq_vectors_affinity( 963 pm8001_ha->pdev, 2, PM8001_MAX_MSIX_VEC, 964 PCI_IRQ_MSIX | PCI_IRQ_AFFINITY, &desc); 965 } 966 967 allocated_irq_vectors = rc; 968 if (rc < 0) 969 return rc; 970 971 /* Assigns the number of interrupts */ 972 pm8001_ha->number_of_intr = allocated_irq_vectors; 973 974 /* Maximum queue number updating in HBA structure */ 975 pm8001_ha->max_q_num = allocated_irq_vectors; 976 977 pm8001_dbg(pm8001_ha, INIT, 978 "pci_alloc_irq_vectors request ret:%d no of intr %d\n", 979 rc, pm8001_ha->number_of_intr); 980 return 0; 981 } 982 983 static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha) 984 { 985 u32 i = 0, j = 0; 986 int flag = 0, rc = 0; 987 int nr_irqs = pm8001_ha->number_of_intr; 988 989 if (pm8001_ha->chip_id != chip_8001) 990 flag &= ~IRQF_SHARED; 991 992 pm8001_dbg(pm8001_ha, INIT, 993 "pci_enable_msix request number of intr %d\n", 994 pm8001_ha->number_of_intr); 995 996 if (nr_irqs > ARRAY_SIZE(pm8001_ha->intr_drvname)) 997 nr_irqs = ARRAY_SIZE(pm8001_ha->intr_drvname); 998 999 for (i = 0; i < nr_irqs; i++) { 1000 snprintf(pm8001_ha->intr_drvname[i], 1001 sizeof(pm8001_ha->intr_drvname[0]), 1002 "%s-%d", pm8001_ha->name, i); 1003 pm8001_ha->irq_vector[i].irq_id = i; 1004 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha; 1005 1006 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i), 1007 pm8001_interrupt_handler_msix, flag, 1008 pm8001_ha->intr_drvname[i], 1009 &(pm8001_ha->irq_vector[i])); 1010 if (rc) { 1011 for (j = 0; j < i; j++) { 1012 free_irq(pci_irq_vector(pm8001_ha->pdev, i), 1013 &(pm8001_ha->irq_vector[i])); 1014 } 1015 pci_free_irq_vectors(pm8001_ha->pdev); 1016 break; 1017 } 1018 } 1019 1020 return rc; 1021 } 1022 #endif 1023 1024 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha) 1025 { 1026 struct pci_dev *pdev; 1027 1028 pdev = pm8001_ha->pdev; 1029 1030 #ifdef PM8001_USE_MSIX 1031 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX)) 1032 return pm8001_setup_msix(pm8001_ha); 1033 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n"); 1034 #endif 1035 return 0; 1036 } 1037 1038 /** 1039 * pm8001_request_irq - register interrupt 1040 * @pm8001_ha: our ha struct. 1041 */ 1042 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha) 1043 { 1044 struct pci_dev *pdev; 1045 int rc; 1046 1047 pdev = pm8001_ha->pdev; 1048 1049 #ifdef PM8001_USE_MSIX 1050 if (pdev->msix_cap && pci_msi_enabled()) 1051 return pm8001_request_msix(pm8001_ha); 1052 else { 1053 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n"); 1054 goto intx; 1055 } 1056 #endif 1057 1058 intx: 1059 /* initialize the INT-X interrupt */ 1060 pm8001_ha->irq_vector[0].irq_id = 0; 1061 pm8001_ha->irq_vector[0].drv_inst = pm8001_ha; 1062 rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED, 1063 pm8001_ha->name, SHOST_TO_SAS_HA(pm8001_ha->shost)); 1064 return rc; 1065 } 1066 1067 /** 1068 * pm8001_pci_probe - probe supported device 1069 * @pdev: pci device which kernel has been prepared for. 1070 * @ent: pci device id 1071 * 1072 * This function is the main initialization function, when register a new 1073 * pci driver it is invoked, all struct and hardware initialization should be 1074 * done here, also, register interrupt. 1075 */ 1076 static int pm8001_pci_probe(struct pci_dev *pdev, 1077 const struct pci_device_id *ent) 1078 { 1079 unsigned int rc; 1080 u32 pci_reg; 1081 u8 i = 0; 1082 struct pm8001_hba_info *pm8001_ha; 1083 struct Scsi_Host *shost = NULL; 1084 const struct pm8001_chip_info *chip; 1085 struct sas_ha_struct *sha; 1086 1087 dev_printk(KERN_INFO, &pdev->dev, 1088 "pm80xx: driver version %s\n", DRV_VERSION); 1089 rc = pci_enable_device(pdev); 1090 if (rc) 1091 goto err_out_enable; 1092 pci_set_master(pdev); 1093 /* 1094 * Enable pci slot busmaster by setting pci command register. 1095 * This is required by FW for Cyclone card. 1096 */ 1097 1098 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg); 1099 pci_reg |= 0x157; 1100 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg); 1101 rc = pci_request_regions(pdev, DRV_NAME); 1102 if (rc) 1103 goto err_out_disable; 1104 rc = pci_go_44(pdev); 1105 if (rc) 1106 goto err_out_regions; 1107 1108 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *)); 1109 if (!shost) { 1110 rc = -ENOMEM; 1111 goto err_out_regions; 1112 } 1113 chip = &pm8001_chips[ent->driver_data]; 1114 sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL); 1115 if (!sha) { 1116 rc = -ENOMEM; 1117 goto err_out_free_host; 1118 } 1119 SHOST_TO_SAS_HA(shost) = sha; 1120 1121 rc = pm8001_prep_sas_ha_init(shost, chip); 1122 if (rc) { 1123 rc = -ENOMEM; 1124 goto err_out_free; 1125 } 1126 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost)); 1127 /* ent->driver variable is used to differentiate between controllers */ 1128 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost); 1129 if (!pm8001_ha) { 1130 rc = -ENOMEM; 1131 goto err_out_free; 1132 } 1133 1134 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1135 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); 1136 if (rc) { 1137 pm8001_dbg(pm8001_ha, FAIL, 1138 "chip_init failed [ret: %d]\n", rc); 1139 goto err_out_ha_free; 1140 } 1141 1142 rc = pm8001_init_ccb_tag(pm8001_ha); 1143 if (rc) 1144 goto err_out_enable; 1145 1146 1147 PM8001_CHIP_DISP->chip_post_init(pm8001_ha); 1148 1149 if (pm8001_ha->number_of_intr > 1) { 1150 shost->nr_hw_queues = pm8001_ha->number_of_intr - 1; 1151 /* 1152 * For now, ensure we're not sent too many commands by setting 1153 * host_tagset. This is also required if we start using request 1154 * tag. 1155 */ 1156 shost->host_tagset = 1; 1157 } 1158 1159 rc = scsi_add_host(shost, &pdev->dev); 1160 if (rc) 1161 goto err_out_ha_free; 1162 1163 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0); 1164 if (pm8001_ha->chip_id != chip_8001) { 1165 for (i = 1; i < pm8001_ha->number_of_intr; i++) 1166 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i); 1167 /* setup thermal configuration. */ 1168 pm80xx_set_thermal_config(pm8001_ha); 1169 } 1170 1171 pm8001_init_sas_add(pm8001_ha); 1172 /* phy setting support for motherboard controller */ 1173 rc = pm8001_configure_phy_settings(pm8001_ha); 1174 if (rc) 1175 goto err_out_shost; 1176 1177 pm8001_post_sas_ha_init(shost, chip); 1178 rc = sas_register_ha(SHOST_TO_SAS_HA(shost)); 1179 if (rc) { 1180 pm8001_dbg(pm8001_ha, FAIL, 1181 "sas_register_ha failed [ret: %d]\n", rc); 1182 goto err_out_shost; 1183 } 1184 list_add_tail(&pm8001_ha->list, &hba_list); 1185 pm8001_ha->flags = PM8001F_RUN_TIME; 1186 scsi_scan_host(pm8001_ha->shost); 1187 return 0; 1188 1189 err_out_shost: 1190 scsi_remove_host(pm8001_ha->shost); 1191 err_out_ha_free: 1192 pm8001_free(pm8001_ha); 1193 err_out_free: 1194 kfree(sha); 1195 err_out_free_host: 1196 scsi_host_put(shost); 1197 err_out_regions: 1198 pci_release_regions(pdev); 1199 err_out_disable: 1200 pci_disable_device(pdev); 1201 err_out_enable: 1202 return rc; 1203 } 1204 1205 /** 1206 * pm8001_init_ccb_tag - allocate memory to CCB and tag. 1207 * @pm8001_ha: our hba card information. 1208 */ 1209 static int pm8001_init_ccb_tag(struct pm8001_hba_info *pm8001_ha) 1210 { 1211 struct Scsi_Host *shost = pm8001_ha->shost; 1212 struct device *dev = pm8001_ha->dev; 1213 u32 max_out_io, ccb_count; 1214 u32 can_queue; 1215 int i; 1216 1217 max_out_io = pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io; 1218 ccb_count = min_t(int, PM8001_MAX_CCB, max_out_io); 1219 1220 /* Update to the scsi host*/ 1221 can_queue = ccb_count - PM8001_RESERVE_SLOT; 1222 shost->can_queue = can_queue; 1223 1224 pm8001_ha->tags = bitmap_zalloc(ccb_count, GFP_KERNEL); 1225 if (!pm8001_ha->tags) 1226 goto err_out; 1227 1228 /* Memory region for ccb_info*/ 1229 pm8001_ha->ccb_count = ccb_count; 1230 pm8001_ha->ccb_info = 1231 kcalloc(ccb_count, sizeof(struct pm8001_ccb_info), GFP_KERNEL); 1232 if (!pm8001_ha->ccb_info) { 1233 pm8001_dbg(pm8001_ha, FAIL, 1234 "Unable to allocate memory for ccb\n"); 1235 goto err_out_noccb; 1236 } 1237 for (i = 0; i < ccb_count; i++) { 1238 pm8001_ha->ccb_info[i].buf_prd = dma_alloc_coherent(dev, 1239 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG, 1240 &pm8001_ha->ccb_info[i].ccb_dma_handle, 1241 GFP_KERNEL); 1242 if (!pm8001_ha->ccb_info[i].buf_prd) { 1243 pm8001_dbg(pm8001_ha, FAIL, 1244 "ccb prd memory allocation error\n"); 1245 goto err_out; 1246 } 1247 pm8001_ha->ccb_info[i].task = NULL; 1248 pm8001_ha->ccb_info[i].ccb_tag = PM8001_INVALID_TAG; 1249 pm8001_ha->ccb_info[i].device = NULL; 1250 ++pm8001_ha->tags_num; 1251 } 1252 1253 return 0; 1254 1255 err_out_noccb: 1256 kfree(pm8001_ha->devices); 1257 err_out: 1258 return -ENOMEM; 1259 } 1260 1261 static void pm8001_pci_remove(struct pci_dev *pdev) 1262 { 1263 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1264 struct pm8001_hba_info *pm8001_ha; 1265 int i, j; 1266 pm8001_ha = sha->lldd_ha; 1267 sas_unregister_ha(sha); 1268 sas_remove_host(pm8001_ha->shost); 1269 list_del(&pm8001_ha->list); 1270 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1271 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1272 1273 #ifdef PM8001_USE_MSIX 1274 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1275 synchronize_irq(pci_irq_vector(pdev, i)); 1276 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1277 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]); 1278 pci_free_irq_vectors(pdev); 1279 #else 1280 free_irq(pm8001_ha->irq, sha); 1281 #endif 1282 #ifdef PM8001_USE_TASKLET 1283 /* For non-msix and msix interrupts */ 1284 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1285 (pm8001_ha->chip_id == chip_8001)) 1286 tasklet_kill(&pm8001_ha->tasklet[0]); 1287 else 1288 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1289 tasklet_kill(&pm8001_ha->tasklet[j]); 1290 #endif 1291 scsi_host_put(pm8001_ha->shost); 1292 1293 for (i = 0; i < pm8001_ha->ccb_count; i++) { 1294 dma_free_coherent(&pm8001_ha->pdev->dev, 1295 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG, 1296 pm8001_ha->ccb_info[i].buf_prd, 1297 pm8001_ha->ccb_info[i].ccb_dma_handle); 1298 } 1299 kfree(pm8001_ha->ccb_info); 1300 kfree(pm8001_ha->devices); 1301 1302 pm8001_free(pm8001_ha); 1303 kfree(sha->sas_phy); 1304 kfree(sha->sas_port); 1305 kfree(sha); 1306 pci_release_regions(pdev); 1307 pci_disable_device(pdev); 1308 } 1309 1310 /** 1311 * pm8001_pci_suspend - power management suspend main entry point 1312 * @dev: Device struct 1313 * 1314 * Return: 0 on success, anything else on error. 1315 */ 1316 static int __maybe_unused pm8001_pci_suspend(struct device *dev) 1317 { 1318 struct pci_dev *pdev = to_pci_dev(dev); 1319 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1320 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 1321 int i, j; 1322 sas_suspend_ha(sha); 1323 flush_workqueue(pm8001_wq); 1324 scsi_block_requests(pm8001_ha->shost); 1325 if (!pdev->pm_cap) { 1326 dev_err(dev, " PCI PM not supported\n"); 1327 return -ENODEV; 1328 } 1329 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1330 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1331 #ifdef PM8001_USE_MSIX 1332 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1333 synchronize_irq(pci_irq_vector(pdev, i)); 1334 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1335 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]); 1336 pci_free_irq_vectors(pdev); 1337 #else 1338 free_irq(pm8001_ha->irq, sha); 1339 #endif 1340 #ifdef PM8001_USE_TASKLET 1341 /* For non-msix and msix interrupts */ 1342 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1343 (pm8001_ha->chip_id == chip_8001)) 1344 tasklet_kill(&pm8001_ha->tasklet[0]); 1345 else 1346 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1347 tasklet_kill(&pm8001_ha->tasklet[j]); 1348 #endif 1349 pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, entering " 1350 "suspended state\n", pdev, 1351 pm8001_ha->name); 1352 return 0; 1353 } 1354 1355 /** 1356 * pm8001_pci_resume - power management resume main entry point 1357 * @dev: Device struct 1358 * 1359 * Return: 0 on success, anything else on error. 1360 */ 1361 static int __maybe_unused pm8001_pci_resume(struct device *dev) 1362 { 1363 struct pci_dev *pdev = to_pci_dev(dev); 1364 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1365 struct pm8001_hba_info *pm8001_ha; 1366 int rc; 1367 u8 i = 0, j; 1368 DECLARE_COMPLETION_ONSTACK(completion); 1369 1370 pm8001_ha = sha->lldd_ha; 1371 1372 pm8001_info(pm8001_ha, 1373 "pdev=0x%p, slot=%s, resuming from previous operating state [D%d]\n", 1374 pdev, pm8001_ha->name, pdev->current_state); 1375 1376 rc = pci_go_44(pdev); 1377 if (rc) 1378 goto err_out_disable; 1379 sas_prep_resume_ha(sha); 1380 /* chip soft rst only for spc */ 1381 if (pm8001_ha->chip_id == chip_8001) { 1382 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1383 pm8001_dbg(pm8001_ha, INIT, "chip soft reset successful\n"); 1384 } 1385 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); 1386 if (rc) 1387 goto err_out_disable; 1388 1389 /* disable all the interrupt bits */ 1390 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1391 1392 rc = pm8001_request_irq(pm8001_ha); 1393 if (rc) 1394 goto err_out_disable; 1395 #ifdef PM8001_USE_TASKLET 1396 /* Tasklet for non msi-x interrupt handler */ 1397 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1398 (pm8001_ha->chip_id == chip_8001)) 1399 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet, 1400 (unsigned long)&(pm8001_ha->irq_vector[0])); 1401 else 1402 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1403 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet, 1404 (unsigned long)&(pm8001_ha->irq_vector[j])); 1405 #endif 1406 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0); 1407 if (pm8001_ha->chip_id != chip_8001) { 1408 for (i = 1; i < pm8001_ha->number_of_intr; i++) 1409 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i); 1410 } 1411 1412 /* Chip documentation for the 8070 and 8072 SPCv */ 1413 /* states that a 500ms minimum delay is required */ 1414 /* before issuing commands. Otherwise, the firmware */ 1415 /* will enter an unrecoverable state. */ 1416 1417 if (pm8001_ha->chip_id == chip_8070 || 1418 pm8001_ha->chip_id == chip_8072) { 1419 mdelay(500); 1420 } 1421 1422 /* Spin up the PHYs */ 1423 1424 pm8001_ha->flags = PM8001F_RUN_TIME; 1425 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 1426 pm8001_ha->phy[i].enable_completion = &completion; 1427 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i); 1428 wait_for_completion(&completion); 1429 } 1430 sas_resume_ha(sha); 1431 return 0; 1432 1433 err_out_disable: 1434 scsi_remove_host(pm8001_ha->shost); 1435 1436 return rc; 1437 } 1438 1439 /* update of pci device, vendor id and driver data with 1440 * unique value for each of the controller 1441 */ 1442 static struct pci_device_id pm8001_pci_table[] = { 1443 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 }, 1444 { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 }, 1445 { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 }, 1446 { PCI_VDEVICE(ATTO, 0x0042), chip_8001 }, 1447 /* Support for SPC/SPCv/SPCve controllers */ 1448 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 }, 1449 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 }, 1450 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 }, 1451 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 }, 1452 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 }, 1453 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 }, 1454 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 }, 1455 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 }, 1456 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 }, 1457 { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 }, 1458 { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 }, 1459 { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 }, 1460 { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 }, 1461 { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 }, 1462 { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 }, 1463 { PCI_VENDOR_ID_ADAPTEC2, 0x8081, 1464 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 }, 1465 { PCI_VENDOR_ID_ADAPTEC2, 0x8081, 1466 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 }, 1467 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1468 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 }, 1469 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1470 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 }, 1471 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1472 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 }, 1473 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1474 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 }, 1475 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1476 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 }, 1477 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1478 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 }, 1479 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1480 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 }, 1481 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1482 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 }, 1483 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1484 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 }, 1485 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1486 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 }, 1487 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1488 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 }, 1489 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1490 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 }, 1491 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1492 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 }, 1493 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1494 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 }, 1495 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1496 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 }, 1497 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1498 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 }, 1499 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1500 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 }, 1501 { PCI_VENDOR_ID_ATTO, 0x8070, 1502 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 }, 1503 { PCI_VENDOR_ID_ATTO, 0x8070, 1504 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 }, 1505 { PCI_VENDOR_ID_ATTO, 0x8072, 1506 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 }, 1507 { PCI_VENDOR_ID_ATTO, 0x8072, 1508 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 }, 1509 { PCI_VENDOR_ID_ATTO, 0x8070, 1510 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 }, 1511 { PCI_VENDOR_ID_ATTO, 0x8072, 1512 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 }, 1513 { PCI_VENDOR_ID_ATTO, 0x8072, 1514 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 }, 1515 {} /* terminate list */ 1516 }; 1517 1518 static SIMPLE_DEV_PM_OPS(pm8001_pci_pm_ops, 1519 pm8001_pci_suspend, 1520 pm8001_pci_resume); 1521 1522 static struct pci_driver pm8001_pci_driver = { 1523 .name = DRV_NAME, 1524 .id_table = pm8001_pci_table, 1525 .probe = pm8001_pci_probe, 1526 .remove = pm8001_pci_remove, 1527 .driver.pm = &pm8001_pci_pm_ops, 1528 }; 1529 1530 /** 1531 * pm8001_init - initialize scsi transport template 1532 */ 1533 static int __init pm8001_init(void) 1534 { 1535 int rc = -ENOMEM; 1536 1537 pm8001_wq = alloc_workqueue("pm80xx", 0, 0); 1538 if (!pm8001_wq) 1539 goto err; 1540 1541 pm8001_id = 0; 1542 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops); 1543 if (!pm8001_stt) 1544 goto err_wq; 1545 rc = pci_register_driver(&pm8001_pci_driver); 1546 if (rc) 1547 goto err_tp; 1548 return 0; 1549 1550 err_tp: 1551 sas_release_transport(pm8001_stt); 1552 err_wq: 1553 destroy_workqueue(pm8001_wq); 1554 err: 1555 return rc; 1556 } 1557 1558 static void __exit pm8001_exit(void) 1559 { 1560 pci_unregister_driver(&pm8001_pci_driver); 1561 sas_release_transport(pm8001_stt); 1562 destroy_workqueue(pm8001_wq); 1563 } 1564 1565 module_init(pm8001_init); 1566 module_exit(pm8001_exit); 1567 1568 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>"); 1569 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>"); 1570 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>"); 1571 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>"); 1572 MODULE_DESCRIPTION( 1573 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 " 1574 "SAS/SATA controller driver"); 1575 MODULE_VERSION(DRV_VERSION); 1576 MODULE_LICENSE("GPL"); 1577 MODULE_DEVICE_TABLE(pci, pm8001_pci_table); 1578 1579