1 /*
2  * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
3  *
4  * Copyright (c) 2008-2009 USI Co., Ltd.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions, and the following disclaimer,
12  *    without modification.
13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14  *    substantially similar to the "NO WARRANTY" disclaimer below
15  *    ("Disclaimer") and any redistribution must be conditioned upon
16  *    including a substantially similar Disclaimer requirement for further
17  *    binary redistribution.
18  * 3. Neither the names of the above-listed copyright holders nor the names
19  *    of any contributors may be used to endorse or promote products derived
20  *    from this software without specific prior written permission.
21  *
22  * Alternatively, this software may be distributed under the terms of the
23  * GNU General Public License ("GPL") version 2 as published by the Free
24  * Software Foundation.
25  *
26  * NO WARRANTY
27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37  * POSSIBILITY OF SUCH DAMAGES.
38  *
39  */
40 
41 #include <linux/slab.h>
42 #include "pm8001_sas.h"
43 #include "pm8001_chips.h"
44 #include "pm80xx_hwi.h"
45 
46 static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING;
47 module_param(logging_level, ulong, 0644);
48 MODULE_PARM_DESC(logging_level, " bits for enabling logging info.");
49 
50 static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120;
51 module_param(link_rate, ulong, 0644);
52 MODULE_PARM_DESC(link_rate, "Enable link rate.\n"
53 		" 1: Link rate 1.5G\n"
54 		" 2: Link rate 3.0G\n"
55 		" 4: Link rate 6.0G\n"
56 		" 8: Link rate 12.0G\n");
57 
58 static struct scsi_transport_template *pm8001_stt;
59 static int pm8001_init_ccb_tag(struct pm8001_hba_info *);
60 
61 /*
62  * chip info structure to identify chip key functionality as
63  * encryption available/not, no of ports, hw specific function ref
64  */
65 static const struct pm8001_chip_info pm8001_chips[] = {
66 	[chip_8001] = {0,  8, &pm8001_8001_dispatch,},
67 	[chip_8008] = {0,  8, &pm8001_80xx_dispatch,},
68 	[chip_8009] = {1,  8, &pm8001_80xx_dispatch,},
69 	[chip_8018] = {0,  16, &pm8001_80xx_dispatch,},
70 	[chip_8019] = {1,  16, &pm8001_80xx_dispatch,},
71 	[chip_8074] = {0,  8, &pm8001_80xx_dispatch,},
72 	[chip_8076] = {0,  16, &pm8001_80xx_dispatch,},
73 	[chip_8077] = {0,  16, &pm8001_80xx_dispatch,},
74 	[chip_8006] = {0,  16, &pm8001_80xx_dispatch,},
75 	[chip_8070] = {0,  8, &pm8001_80xx_dispatch,},
76 	[chip_8072] = {0,  16, &pm8001_80xx_dispatch,},
77 };
78 static int pm8001_id;
79 
80 LIST_HEAD(hba_list);
81 
82 struct workqueue_struct *pm8001_wq;
83 
84 static int pm8001_map_queues(struct Scsi_Host *shost)
85 {
86 	struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
87 	struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
88 	struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
89 
90 	if (pm8001_ha->number_of_intr > 1)
91 		blk_mq_pci_map_queues(qmap, pm8001_ha->pdev, 1);
92 
93 	return blk_mq_map_queues(qmap);
94 }
95 
96 /*
97  * The main structure which LLDD must register for scsi core.
98  */
99 static struct scsi_host_template pm8001_sht = {
100 	.module			= THIS_MODULE,
101 	.name			= DRV_NAME,
102 	.queuecommand		= sas_queuecommand,
103 	.dma_need_drain		= ata_scsi_dma_need_drain,
104 	.target_alloc		= sas_target_alloc,
105 	.slave_configure	= sas_slave_configure,
106 	.scan_finished		= pm8001_scan_finished,
107 	.scan_start		= pm8001_scan_start,
108 	.change_queue_depth	= sas_change_queue_depth,
109 	.bios_param		= sas_bios_param,
110 	.can_queue		= 1,
111 	.this_id		= -1,
112 	.sg_tablesize		= PM8001_MAX_DMA_SG,
113 	.max_sectors		= SCSI_DEFAULT_MAX_SECTORS,
114 	.eh_device_reset_handler = sas_eh_device_reset_handler,
115 	.eh_target_reset_handler = sas_eh_target_reset_handler,
116 	.slave_alloc		= sas_slave_alloc,
117 	.target_destroy		= sas_target_destroy,
118 	.ioctl			= sas_ioctl,
119 #ifdef CONFIG_COMPAT
120 	.compat_ioctl		= sas_ioctl,
121 #endif
122 	.shost_groups		= pm8001_host_groups,
123 	.track_queue_depth	= 1,
124 	.cmd_per_lun		= 32,
125 	.map_queues		= pm8001_map_queues,
126 };
127 
128 /*
129  * Sas layer call this function to execute specific task.
130  */
131 static struct sas_domain_function_template pm8001_transport_ops = {
132 	.lldd_dev_found		= pm8001_dev_found,
133 	.lldd_dev_gone		= pm8001_dev_gone,
134 
135 	.lldd_execute_task	= pm8001_queue_command,
136 	.lldd_control_phy	= pm8001_phy_control,
137 
138 	.lldd_abort_task	= pm8001_abort_task,
139 	.lldd_abort_task_set	= sas_abort_task_set,
140 	.lldd_clear_task_set	= pm8001_clear_task_set,
141 	.lldd_I_T_nexus_reset   = pm8001_I_T_nexus_reset,
142 	.lldd_lu_reset		= pm8001_lu_reset,
143 	.lldd_query_task	= pm8001_query_task,
144 	.lldd_port_formed	= pm8001_port_formed,
145 	.lldd_tmf_exec_complete = pm8001_setds_completion,
146 	.lldd_tmf_aborted	= pm8001_tmf_aborted,
147 };
148 
149 /**
150  * pm8001_phy_init - initiate our adapter phys
151  * @pm8001_ha: our hba structure.
152  * @phy_id: phy id.
153  */
154 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
155 {
156 	struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
157 	struct asd_sas_phy *sas_phy = &phy->sas_phy;
158 	phy->phy_state = PHY_LINK_DISABLE;
159 	phy->pm8001_ha = pm8001_ha;
160 	sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
161 	sas_phy->class = SAS;
162 	sas_phy->iproto = SAS_PROTOCOL_ALL;
163 	sas_phy->tproto = 0;
164 	sas_phy->type = PHY_TYPE_PHYSICAL;
165 	sas_phy->role = PHY_ROLE_INITIATOR;
166 	sas_phy->oob_mode = OOB_NOT_CONNECTED;
167 	sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
168 	sas_phy->id = phy_id;
169 	sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr;
170 	sas_phy->frame_rcvd = &phy->frame_rcvd[0];
171 	sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
172 	sas_phy->lldd_phy = phy;
173 }
174 
175 /**
176  * pm8001_free - free hba
177  * @pm8001_ha:	our hba structure.
178  */
179 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
180 {
181 	int i;
182 
183 	if (!pm8001_ha)
184 		return;
185 
186 	for (i = 0; i < USI_MAX_MEMCNT; i++) {
187 		if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
188 			dma_free_coherent(&pm8001_ha->pdev->dev,
189 				(pm8001_ha->memoryMap.region[i].total_len +
190 				pm8001_ha->memoryMap.region[i].alignment),
191 				pm8001_ha->memoryMap.region[i].virt_ptr,
192 				pm8001_ha->memoryMap.region[i].phys_addr);
193 			}
194 	}
195 	PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
196 	flush_workqueue(pm8001_wq);
197 	bitmap_free(pm8001_ha->tags);
198 	kfree(pm8001_ha);
199 }
200 
201 #ifdef PM8001_USE_TASKLET
202 
203 /**
204  * pm8001_tasklet() - tasklet for 64 msi-x interrupt handler
205  * @opaque: the passed general host adapter struct
206  * Note: pm8001_tasklet is common for pm8001 & pm80xx
207  */
208 static void pm8001_tasklet(unsigned long opaque)
209 {
210 	struct pm8001_hba_info *pm8001_ha;
211 	struct isr_param *irq_vector;
212 
213 	irq_vector = (struct isr_param *)opaque;
214 	pm8001_ha = irq_vector->drv_inst;
215 	if (unlikely(!pm8001_ha))
216 		BUG_ON(1);
217 	PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
218 }
219 #endif
220 
221 /**
222  * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
223  * It obtains the vector number and calls the equivalent bottom
224  * half or services directly.
225  * @irq: interrupt number
226  * @opaque: the passed outbound queue/vector. Host structure is
227  * retrieved from the same.
228  */
229 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
230 {
231 	struct isr_param *irq_vector;
232 	struct pm8001_hba_info *pm8001_ha;
233 	irqreturn_t ret = IRQ_HANDLED;
234 	irq_vector = (struct isr_param *)opaque;
235 	pm8001_ha = irq_vector->drv_inst;
236 
237 	if (unlikely(!pm8001_ha))
238 		return IRQ_NONE;
239 	if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
240 		return IRQ_NONE;
241 #ifdef PM8001_USE_TASKLET
242 	tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
243 #else
244 	ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
245 #endif
246 	return ret;
247 }
248 
249 /**
250  * pm8001_interrupt_handler_intx - main INTx interrupt handler.
251  * @irq: interrupt number
252  * @dev_id: sas_ha structure. The HBA is retrieved from sas_ha structure.
253  */
254 
255 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
256 {
257 	struct pm8001_hba_info *pm8001_ha;
258 	irqreturn_t ret = IRQ_HANDLED;
259 	struct sas_ha_struct *sha = dev_id;
260 	pm8001_ha = sha->lldd_ha;
261 	if (unlikely(!pm8001_ha))
262 		return IRQ_NONE;
263 	if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
264 		return IRQ_NONE;
265 
266 #ifdef PM8001_USE_TASKLET
267 	tasklet_schedule(&pm8001_ha->tasklet[0]);
268 #else
269 	ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
270 #endif
271 	return ret;
272 }
273 
274 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha);
275 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha);
276 
277 /**
278  * pm8001_alloc - initiate our hba structure and 6 DMAs area.
279  * @pm8001_ha: our hba structure.
280  * @ent: PCI device ID structure to match on
281  */
282 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
283 			const struct pci_device_id *ent)
284 {
285 	int i, count = 0, rc = 0;
286 	u32 ci_offset, ib_offset, ob_offset, pi_offset;
287 	struct inbound_queue_table *ibq;
288 	struct outbound_queue_table *obq;
289 
290 	spin_lock_init(&pm8001_ha->lock);
291 	spin_lock_init(&pm8001_ha->bitmap_lock);
292 	pm8001_dbg(pm8001_ha, INIT, "pm8001_alloc: PHY:%x\n",
293 		   pm8001_ha->chip->n_phy);
294 
295 	/* Setup Interrupt */
296 	rc = pm8001_setup_irq(pm8001_ha);
297 	if (rc) {
298 		pm8001_dbg(pm8001_ha, FAIL,
299 			   "pm8001_setup_irq failed [ret: %d]\n", rc);
300 		goto err_out;
301 	}
302 	/* Request Interrupt */
303 	rc = pm8001_request_irq(pm8001_ha);
304 	if (rc)
305 		goto err_out;
306 
307 	count = pm8001_ha->max_q_num;
308 	/* Queues are chosen based on the number of cores/msix availability */
309 	ib_offset = pm8001_ha->ib_offset  = USI_MAX_MEMCNT_BASE;
310 	ci_offset = pm8001_ha->ci_offset  = ib_offset + count;
311 	ob_offset = pm8001_ha->ob_offset  = ci_offset + count;
312 	pi_offset = pm8001_ha->pi_offset  = ob_offset + count;
313 	pm8001_ha->max_memcnt = pi_offset + count;
314 
315 	for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
316 		pm8001_phy_init(pm8001_ha, i);
317 		pm8001_ha->port[i].wide_port_phymap = 0;
318 		pm8001_ha->port[i].port_attached = 0;
319 		pm8001_ha->port[i].port_state = 0;
320 		INIT_LIST_HEAD(&pm8001_ha->port[i].list);
321 	}
322 
323 	/* MPI Memory region 1 for AAP Event Log for fw */
324 	pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
325 	pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
326 	pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
327 	pm8001_ha->memoryMap.region[AAP1].alignment = 32;
328 
329 	/* MPI Memory region 2 for IOP Event Log for fw */
330 	pm8001_ha->memoryMap.region[IOP].num_elements = 1;
331 	pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
332 	pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
333 	pm8001_ha->memoryMap.region[IOP].alignment = 32;
334 
335 	for (i = 0; i < count; i++) {
336 		ibq = &pm8001_ha->inbnd_q_tbl[i];
337 		spin_lock_init(&ibq->iq_lock);
338 		/* MPI Memory region 3 for consumer Index of inbound queues */
339 		pm8001_ha->memoryMap.region[ci_offset+i].num_elements = 1;
340 		pm8001_ha->memoryMap.region[ci_offset+i].element_size = 4;
341 		pm8001_ha->memoryMap.region[ci_offset+i].total_len = 4;
342 		pm8001_ha->memoryMap.region[ci_offset+i].alignment = 4;
343 
344 		if ((ent->driver_data) != chip_8001) {
345 			/* MPI Memory region 5 inbound queues */
346 			pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
347 						PM8001_MPI_QUEUE;
348 			pm8001_ha->memoryMap.region[ib_offset+i].element_size
349 								= 128;
350 			pm8001_ha->memoryMap.region[ib_offset+i].total_len =
351 						PM8001_MPI_QUEUE * 128;
352 			pm8001_ha->memoryMap.region[ib_offset+i].alignment
353 								= 128;
354 		} else {
355 			pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
356 						PM8001_MPI_QUEUE;
357 			pm8001_ha->memoryMap.region[ib_offset+i].element_size
358 								= 64;
359 			pm8001_ha->memoryMap.region[ib_offset+i].total_len =
360 						PM8001_MPI_QUEUE * 64;
361 			pm8001_ha->memoryMap.region[ib_offset+i].alignment = 64;
362 		}
363 	}
364 
365 	for (i = 0; i < count; i++) {
366 		obq = &pm8001_ha->outbnd_q_tbl[i];
367 		spin_lock_init(&obq->oq_lock);
368 		/* MPI Memory region 4 for producer Index of outbound queues */
369 		pm8001_ha->memoryMap.region[pi_offset+i].num_elements = 1;
370 		pm8001_ha->memoryMap.region[pi_offset+i].element_size = 4;
371 		pm8001_ha->memoryMap.region[pi_offset+i].total_len = 4;
372 		pm8001_ha->memoryMap.region[pi_offset+i].alignment = 4;
373 
374 		if (ent->driver_data != chip_8001) {
375 			/* MPI Memory region 6 Outbound queues */
376 			pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
377 						PM8001_MPI_QUEUE;
378 			pm8001_ha->memoryMap.region[ob_offset+i].element_size
379 								= 128;
380 			pm8001_ha->memoryMap.region[ob_offset+i].total_len =
381 						PM8001_MPI_QUEUE * 128;
382 			pm8001_ha->memoryMap.region[ob_offset+i].alignment
383 								= 128;
384 		} else {
385 			/* MPI Memory region 6 Outbound queues */
386 			pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
387 						PM8001_MPI_QUEUE;
388 			pm8001_ha->memoryMap.region[ob_offset+i].element_size
389 								= 64;
390 			pm8001_ha->memoryMap.region[ob_offset+i].total_len =
391 						PM8001_MPI_QUEUE * 64;
392 			pm8001_ha->memoryMap.region[ob_offset+i].alignment = 64;
393 		}
394 
395 	}
396 	/* Memory region write DMA*/
397 	pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
398 	pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
399 	pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
400 
401 	/* Memory region for fw flash */
402 	pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
403 
404 	pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
405 	pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
406 	pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
407 	pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
408 	for (i = 0; i < pm8001_ha->max_memcnt; i++) {
409 		struct mpi_mem *region = &pm8001_ha->memoryMap.region[i];
410 
411 		if (pm8001_mem_alloc(pm8001_ha->pdev,
412 				     &region->virt_ptr,
413 				     &region->phys_addr,
414 				     &region->phys_addr_hi,
415 				     &region->phys_addr_lo,
416 				     region->total_len,
417 				     region->alignment) != 0) {
418 			pm8001_dbg(pm8001_ha, FAIL, "Mem%d alloc failed\n", i);
419 			goto err_out;
420 		}
421 	}
422 
423 	/* Memory region for devices*/
424 	pm8001_ha->devices = kzalloc(PM8001_MAX_DEVICES
425 				* sizeof(struct pm8001_device), GFP_KERNEL);
426 	if (!pm8001_ha->devices) {
427 		rc = -ENOMEM;
428 		goto err_out_nodev;
429 	}
430 	for (i = 0; i < PM8001_MAX_DEVICES; i++) {
431 		pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
432 		pm8001_ha->devices[i].id = i;
433 		pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
434 		atomic_set(&pm8001_ha->devices[i].running_req, 0);
435 	}
436 	pm8001_ha->flags = PM8001F_INIT_TIME;
437 	/* Initialize tags */
438 	pm8001_tag_init(pm8001_ha);
439 	return 0;
440 
441 err_out_nodev:
442 	for (i = 0; i < pm8001_ha->max_memcnt; i++) {
443 		if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
444 			dma_free_coherent(&pm8001_ha->pdev->dev,
445 				(pm8001_ha->memoryMap.region[i].total_len +
446 				pm8001_ha->memoryMap.region[i].alignment),
447 				pm8001_ha->memoryMap.region[i].virt_ptr,
448 				pm8001_ha->memoryMap.region[i].phys_addr);
449 		}
450 	}
451 err_out:
452 	return 1;
453 }
454 
455 /**
456  * pm8001_ioremap - remap the pci high physical address to kernel virtual
457  * address so that we can access them.
458  * @pm8001_ha: our hba structure.
459  */
460 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
461 {
462 	u32 bar;
463 	u32 logicalBar = 0;
464 	struct pci_dev *pdev;
465 
466 	pdev = pm8001_ha->pdev;
467 	/* map pci mem (PMC pci base 0-3)*/
468 	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
469 		/*
470 		** logical BARs for SPC:
471 		** bar 0 and 1 - logical BAR0
472 		** bar 2 and 3 - logical BAR1
473 		** bar4 - logical BAR2
474 		** bar5 - logical BAR3
475 		** Skip the appropriate assignments:
476 		*/
477 		if ((bar == 1) || (bar == 3))
478 			continue;
479 		if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
480 			pm8001_ha->io_mem[logicalBar].membase =
481 				pci_resource_start(pdev, bar);
482 			pm8001_ha->io_mem[logicalBar].memsize =
483 				pci_resource_len(pdev, bar);
484 			pm8001_ha->io_mem[logicalBar].memvirtaddr =
485 				ioremap(pm8001_ha->io_mem[logicalBar].membase,
486 				pm8001_ha->io_mem[logicalBar].memsize);
487 			if (!pm8001_ha->io_mem[logicalBar].memvirtaddr) {
488 				pm8001_dbg(pm8001_ha, INIT,
489 					"Failed to ioremap bar %d, logicalBar %d",
490 				   bar, logicalBar);
491 				return -ENOMEM;
492 			}
493 			pm8001_dbg(pm8001_ha, INIT,
494 				   "base addr %llx virt_addr=%llx len=%d\n",
495 				   (u64)pm8001_ha->io_mem[logicalBar].membase,
496 				   (u64)(unsigned long)
497 				   pm8001_ha->io_mem[logicalBar].memvirtaddr,
498 				   pm8001_ha->io_mem[logicalBar].memsize);
499 		} else {
500 			pm8001_ha->io_mem[logicalBar].membase	= 0;
501 			pm8001_ha->io_mem[logicalBar].memsize	= 0;
502 			pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL;
503 		}
504 		logicalBar++;
505 	}
506 	return 0;
507 }
508 
509 /**
510  * pm8001_pci_alloc - initialize our ha card structure
511  * @pdev: pci device.
512  * @ent: ent
513  * @shost: scsi host struct which has been initialized before.
514  */
515 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
516 				 const struct pci_device_id *ent,
517 				struct Scsi_Host *shost)
518 
519 {
520 	struct pm8001_hba_info *pm8001_ha;
521 	struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
522 	int j;
523 
524 	pm8001_ha = sha->lldd_ha;
525 	if (!pm8001_ha)
526 		return NULL;
527 
528 	pm8001_ha->pdev = pdev;
529 	pm8001_ha->dev = &pdev->dev;
530 	pm8001_ha->chip_id = ent->driver_data;
531 	pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
532 	pm8001_ha->irq = pdev->irq;
533 	pm8001_ha->sas = sha;
534 	pm8001_ha->shost = shost;
535 	pm8001_ha->id = pm8001_id++;
536 	pm8001_ha->logging_level = logging_level;
537 	pm8001_ha->non_fatal_count = 0;
538 	if (link_rate >= 1 && link_rate <= 15)
539 		pm8001_ha->link_rate = (link_rate << 8);
540 	else {
541 		pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 |
542 			LINKRATE_60 | LINKRATE_120;
543 		pm8001_dbg(pm8001_ha, FAIL,
544 			   "Setting link rate to default value\n");
545 	}
546 	sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
547 	/* IOMB size is 128 for 8088/89 controllers */
548 	if (pm8001_ha->chip_id != chip_8001)
549 		pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
550 	else
551 		pm8001_ha->iomb_size = IOMB_SIZE_SPC;
552 
553 #ifdef PM8001_USE_TASKLET
554 	/* Tasklet for non msi-x interrupt handler */
555 	if ((!pdev->msix_cap || !pci_msi_enabled())
556 	    || (pm8001_ha->chip_id == chip_8001))
557 		tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
558 			(unsigned long)&(pm8001_ha->irq_vector[0]));
559 	else
560 		for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
561 			tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
562 				(unsigned long)&(pm8001_ha->irq_vector[j]));
563 #endif
564 	if (pm8001_ioremap(pm8001_ha))
565 		goto failed_pci_alloc;
566 	if (!pm8001_alloc(pm8001_ha, ent))
567 		return pm8001_ha;
568 failed_pci_alloc:
569 	pm8001_free(pm8001_ha);
570 	return NULL;
571 }
572 
573 /**
574  * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
575  * @pdev: pci device.
576  */
577 static int pci_go_44(struct pci_dev *pdev)
578 {
579 	int rc;
580 
581 	rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
582 	if (rc) {
583 		rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
584 		if (rc)
585 			dev_printk(KERN_ERR, &pdev->dev,
586 				"32-bit DMA enable failed\n");
587 	}
588 	return rc;
589 }
590 
591 /**
592  * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
593  * @shost: scsi host which has been allocated outside.
594  * @chip_info: our ha struct.
595  */
596 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
597 				   const struct pm8001_chip_info *chip_info)
598 {
599 	int phy_nr, port_nr;
600 	struct asd_sas_phy **arr_phy;
601 	struct asd_sas_port **arr_port;
602 	struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
603 
604 	phy_nr = chip_info->n_phy;
605 	port_nr = phy_nr;
606 	memset(sha, 0x00, sizeof(*sha));
607 	arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
608 	if (!arr_phy)
609 		goto exit;
610 	arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
611 	if (!arr_port)
612 		goto exit_free2;
613 
614 	sha->sas_phy = arr_phy;
615 	sha->sas_port = arr_port;
616 	sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
617 	if (!sha->lldd_ha)
618 		goto exit_free1;
619 
620 	shost->transportt = pm8001_stt;
621 	shost->max_id = PM8001_MAX_DEVICES;
622 	shost->unique_id = pm8001_id;
623 	shost->max_cmd_len = 16;
624 	return 0;
625 exit_free1:
626 	kfree(arr_port);
627 exit_free2:
628 	kfree(arr_phy);
629 exit:
630 	return -1;
631 }
632 
633 /**
634  * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
635  * @shost: scsi host which has been allocated outside
636  * @chip_info: our ha struct.
637  */
638 static void  pm8001_post_sas_ha_init(struct Scsi_Host *shost,
639 				     const struct pm8001_chip_info *chip_info)
640 {
641 	int i = 0;
642 	struct pm8001_hba_info *pm8001_ha;
643 	struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
644 
645 	pm8001_ha = sha->lldd_ha;
646 	for (i = 0; i < chip_info->n_phy; i++) {
647 		sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
648 		sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
649 		sha->sas_phy[i]->sas_addr =
650 			(u8 *)&pm8001_ha->phy[i].dev_sas_addr;
651 	}
652 	sha->sas_ha_name = DRV_NAME;
653 	sha->dev = pm8001_ha->dev;
654 	sha->strict_wide_ports = 1;
655 	sha->lldd_module = THIS_MODULE;
656 	sha->sas_addr = &pm8001_ha->sas_addr[0];
657 	sha->num_phys = chip_info->n_phy;
658 	sha->core.shost = shost;
659 }
660 
661 /**
662  * pm8001_init_sas_add - initialize sas address
663  * @pm8001_ha: our ha struct.
664  *
665  * Currently we just set the fixed SAS address to our HBA, for manufacture,
666  * it should read from the EEPROM
667  */
668 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
669 {
670 	u8 i, j;
671 	u8 sas_add[8];
672 #ifdef PM8001_READ_VPD
673 	/* For new SPC controllers WWN is stored in flash vpd
674 	*  For SPC/SPCve controllers WWN is stored in EEPROM
675 	*  For Older SPC WWN is stored in NVMD
676 	*/
677 	DECLARE_COMPLETION_ONSTACK(completion);
678 	struct pm8001_ioctl_payload payload;
679 	u16 deviceid;
680 	int rc;
681 
682 	pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
683 	pm8001_ha->nvmd_completion = &completion;
684 
685 	if (pm8001_ha->chip_id == chip_8001) {
686 		if (deviceid == 0x8081 || deviceid == 0x0042) {
687 			payload.minor_function = 4;
688 			payload.rd_length = 4096;
689 		} else {
690 			payload.minor_function = 0;
691 			payload.rd_length = 128;
692 		}
693 	} else if ((pm8001_ha->chip_id == chip_8070 ||
694 			pm8001_ha->chip_id == chip_8072) &&
695 			pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
696 		payload.minor_function = 4;
697 		payload.rd_length = 4096;
698 	} else {
699 		payload.minor_function = 1;
700 		payload.rd_length = 4096;
701 	}
702 	payload.offset = 0;
703 	payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL);
704 	if (!payload.func_specific) {
705 		pm8001_dbg(pm8001_ha, INIT, "mem alloc fail\n");
706 		return;
707 	}
708 	rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
709 	if (rc) {
710 		kfree(payload.func_specific);
711 		pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
712 		return;
713 	}
714 	wait_for_completion(&completion);
715 
716 	for (i = 0, j = 0; i <= 7; i++, j++) {
717 		if (pm8001_ha->chip_id == chip_8001) {
718 			if (deviceid == 0x8081)
719 				pm8001_ha->sas_addr[j] =
720 					payload.func_specific[0x704 + i];
721 			else if (deviceid == 0x0042)
722 				pm8001_ha->sas_addr[j] =
723 					payload.func_specific[0x010 + i];
724 		} else if ((pm8001_ha->chip_id == chip_8070 ||
725 				pm8001_ha->chip_id == chip_8072) &&
726 				pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
727 			pm8001_ha->sas_addr[j] =
728 					payload.func_specific[0x010 + i];
729 		} else
730 			pm8001_ha->sas_addr[j] =
731 					payload.func_specific[0x804 + i];
732 	}
733 	memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE);
734 	for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
735 		if (i && ((i % 4) == 0))
736 			sas_add[7] = sas_add[7] + 4;
737 		memcpy(&pm8001_ha->phy[i].dev_sas_addr,
738 			sas_add, SAS_ADDR_SIZE);
739 		pm8001_dbg(pm8001_ha, INIT, "phy %d sas_addr = %016llx\n", i,
740 			   pm8001_ha->phy[i].dev_sas_addr);
741 	}
742 	kfree(payload.func_specific);
743 #else
744 	for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
745 		pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
746 		pm8001_ha->phy[i].dev_sas_addr =
747 			cpu_to_be64((u64)
748 				(*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
749 	}
750 	memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
751 		SAS_ADDR_SIZE);
752 #endif
753 }
754 
755 /*
756  * pm8001_get_phy_settings_info : Read phy setting values.
757  * @pm8001_ha : our hba.
758  */
759 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
760 {
761 
762 #ifdef PM8001_READ_VPD
763 	/*OPTION ROM FLASH read for the SPC cards */
764 	DECLARE_COMPLETION_ONSTACK(completion);
765 	struct pm8001_ioctl_payload payload;
766 	int rc;
767 
768 	pm8001_ha->nvmd_completion = &completion;
769 	/* SAS ADDRESS read from flash / EEPROM */
770 	payload.minor_function = 6;
771 	payload.offset = 0;
772 	payload.rd_length = 4096;
773 	payload.func_specific = kzalloc(4096, GFP_KERNEL);
774 	if (!payload.func_specific)
775 		return -ENOMEM;
776 	/* Read phy setting values from flash */
777 	rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
778 	if (rc) {
779 		kfree(payload.func_specific);
780 		pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
781 		return -ENOMEM;
782 	}
783 	wait_for_completion(&completion);
784 	pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
785 	kfree(payload.func_specific);
786 #endif
787 	return 0;
788 }
789 
790 struct pm8001_mpi3_phy_pg_trx_config {
791 	u32 LaneLosCfg;
792 	u32 LanePgaCfg1;
793 	u32 LanePisoCfg1;
794 	u32 LanePisoCfg2;
795 	u32 LanePisoCfg3;
796 	u32 LanePisoCfg4;
797 	u32 LanePisoCfg5;
798 	u32 LanePisoCfg6;
799 	u32 LaneBctCtrl;
800 };
801 
802 /**
803  * pm8001_get_internal_phy_settings - Retrieves the internal PHY settings
804  * @pm8001_ha : our adapter
805  * @phycfg : PHY config page to populate
806  */
807 static
808 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
809 		struct pm8001_mpi3_phy_pg_trx_config *phycfg)
810 {
811 	phycfg->LaneLosCfg   = 0x00000132;
812 	phycfg->LanePgaCfg1  = 0x00203949;
813 	phycfg->LanePisoCfg1 = 0x000000FF;
814 	phycfg->LanePisoCfg2 = 0xFF000001;
815 	phycfg->LanePisoCfg3 = 0xE7011300;
816 	phycfg->LanePisoCfg4 = 0x631C40C0;
817 	phycfg->LanePisoCfg5 = 0xF8102036;
818 	phycfg->LanePisoCfg6 = 0xF74A1000;
819 	phycfg->LaneBctCtrl  = 0x00FB33F8;
820 }
821 
822 /**
823  * pm8001_get_external_phy_settings - Retrieves the external PHY settings
824  * @pm8001_ha : our adapter
825  * @phycfg : PHY config page to populate
826  */
827 static
828 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
829 		struct pm8001_mpi3_phy_pg_trx_config *phycfg)
830 {
831 	phycfg->LaneLosCfg   = 0x00000132;
832 	phycfg->LanePgaCfg1  = 0x00203949;
833 	phycfg->LanePisoCfg1 = 0x000000FF;
834 	phycfg->LanePisoCfg2 = 0xFF000001;
835 	phycfg->LanePisoCfg3 = 0xE7011300;
836 	phycfg->LanePisoCfg4 = 0x63349140;
837 	phycfg->LanePisoCfg5 = 0xF8102036;
838 	phycfg->LanePisoCfg6 = 0xF80D9300;
839 	phycfg->LaneBctCtrl  = 0x00FB33F8;
840 }
841 
842 /**
843  * pm8001_get_phy_mask - Retrieves the mask that denotes if a PHY is int/ext
844  * @pm8001_ha : our adapter
845  * @phymask : The PHY mask
846  */
847 static
848 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
849 {
850 	switch (pm8001_ha->pdev->subsystem_device) {
851 	case 0x0070: /* H1280 - 8 external 0 internal */
852 	case 0x0072: /* H12F0 - 16 external 0 internal */
853 		*phymask = 0x0000;
854 		break;
855 
856 	case 0x0071: /* H1208 - 0 external 8 internal */
857 	case 0x0073: /* H120F - 0 external 16 internal */
858 		*phymask = 0xFFFF;
859 		break;
860 
861 	case 0x0080: /* H1244 - 4 external 4 internal */
862 		*phymask = 0x00F0;
863 		break;
864 
865 	case 0x0081: /* H1248 - 4 external 8 internal */
866 		*phymask = 0x0FF0;
867 		break;
868 
869 	case 0x0082: /* H1288 - 8 external 8 internal */
870 		*phymask = 0xFF00;
871 		break;
872 
873 	default:
874 		pm8001_dbg(pm8001_ha, INIT,
875 			   "Unknown subsystem device=0x%.04x\n",
876 			   pm8001_ha->pdev->subsystem_device);
877 	}
878 }
879 
880 /**
881  * pm8001_set_phy_settings_ven_117c_12G() - Configure ATTO 12Gb PHY settings
882  * @pm8001_ha : our adapter
883  */
884 static
885 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
886 {
887 	struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
888 	struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
889 	int phymask = 0;
890 	int i = 0;
891 
892 	memset(&phycfg_int, 0, sizeof(phycfg_int));
893 	memset(&phycfg_ext, 0, sizeof(phycfg_ext));
894 
895 	pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
896 	pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
897 	pm8001_get_phy_mask(pm8001_ha, &phymask);
898 
899 	for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
900 		if (phymask & (1 << i)) {/* Internal PHY */
901 			pm8001_set_phy_profile_single(pm8001_ha, i,
902 					sizeof(phycfg_int) / sizeof(u32),
903 					(u32 *)&phycfg_int);
904 
905 		} else { /* External PHY */
906 			pm8001_set_phy_profile_single(pm8001_ha, i,
907 					sizeof(phycfg_ext) / sizeof(u32),
908 					(u32 *)&phycfg_ext);
909 		}
910 	}
911 
912 	return 0;
913 }
914 
915 /**
916  * pm8001_configure_phy_settings - Configures PHY settings based on vendor ID.
917  * @pm8001_ha : our hba.
918  */
919 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
920 {
921 	switch (pm8001_ha->pdev->subsystem_vendor) {
922 	case PCI_VENDOR_ID_ATTO:
923 		if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */
924 			return 0;
925 		else
926 			return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
927 
928 	case PCI_VENDOR_ID_ADAPTEC2:
929 	case 0:
930 		return 0;
931 
932 	default:
933 		return pm8001_get_phy_settings_info(pm8001_ha);
934 	}
935 }
936 
937 #ifdef PM8001_USE_MSIX
938 /**
939  * pm8001_setup_msix - enable MSI-X interrupt
940  * @pm8001_ha: our ha struct.
941  */
942 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
943 {
944 	unsigned int allocated_irq_vectors;
945 	int rc;
946 
947 	/* SPCv controllers supports 64 msi-x */
948 	if (pm8001_ha->chip_id == chip_8001) {
949 		rc = pci_alloc_irq_vectors(pm8001_ha->pdev, 1, 1,
950 					   PCI_IRQ_MSIX);
951 	} else {
952 		/*
953 		 * Queue index #0 is used always for housekeeping, so don't
954 		 * include in the affinity spreading.
955 		 */
956 		struct irq_affinity desc = {
957 			.pre_vectors = 1,
958 		};
959 		rc = pci_alloc_irq_vectors_affinity(
960 				pm8001_ha->pdev, 2, PM8001_MAX_MSIX_VEC,
961 				PCI_IRQ_MSIX | PCI_IRQ_AFFINITY, &desc);
962 	}
963 
964 	allocated_irq_vectors = rc;
965 	if (rc < 0)
966 		return rc;
967 
968 	/* Assigns the number of interrupts */
969 	pm8001_ha->number_of_intr = allocated_irq_vectors;
970 
971 	/* Maximum queue number updating in HBA structure */
972 	pm8001_ha->max_q_num = allocated_irq_vectors;
973 
974 	pm8001_dbg(pm8001_ha, INIT,
975 		   "pci_alloc_irq_vectors request ret:%d no of intr %d\n",
976 		   rc, pm8001_ha->number_of_intr);
977 	return 0;
978 }
979 
980 static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha)
981 {
982 	u32 i = 0, j = 0;
983 	int flag = 0, rc = 0;
984 	int nr_irqs = pm8001_ha->number_of_intr;
985 
986 	if (pm8001_ha->chip_id != chip_8001)
987 		flag &= ~IRQF_SHARED;
988 
989 	pm8001_dbg(pm8001_ha, INIT,
990 		   "pci_enable_msix request number of intr %d\n",
991 		   pm8001_ha->number_of_intr);
992 
993 	if (nr_irqs > ARRAY_SIZE(pm8001_ha->intr_drvname))
994 		nr_irqs = ARRAY_SIZE(pm8001_ha->intr_drvname);
995 
996 	for (i = 0; i < nr_irqs; i++) {
997 		snprintf(pm8001_ha->intr_drvname[i],
998 			sizeof(pm8001_ha->intr_drvname[0]),
999 			"%s-%d", pm8001_ha->name, i);
1000 		pm8001_ha->irq_vector[i].irq_id = i;
1001 		pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
1002 
1003 		rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i),
1004 			pm8001_interrupt_handler_msix, flag,
1005 			pm8001_ha->intr_drvname[i],
1006 			&(pm8001_ha->irq_vector[i]));
1007 		if (rc) {
1008 			for (j = 0; j < i; j++) {
1009 				free_irq(pci_irq_vector(pm8001_ha->pdev, i),
1010 					&(pm8001_ha->irq_vector[i]));
1011 			}
1012 			pci_free_irq_vectors(pm8001_ha->pdev);
1013 			break;
1014 		}
1015 	}
1016 
1017 	return rc;
1018 }
1019 #endif
1020 
1021 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha)
1022 {
1023 	struct pci_dev *pdev;
1024 
1025 	pdev = pm8001_ha->pdev;
1026 
1027 #ifdef PM8001_USE_MSIX
1028 	if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
1029 		return pm8001_setup_msix(pm8001_ha);
1030 	pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1031 #endif
1032 	return 0;
1033 }
1034 
1035 /**
1036  * pm8001_request_irq - register interrupt
1037  * @pm8001_ha: our ha struct.
1038  */
1039 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
1040 {
1041 	struct pci_dev *pdev;
1042 	int rc;
1043 
1044 	pdev = pm8001_ha->pdev;
1045 
1046 #ifdef PM8001_USE_MSIX
1047 	if (pdev->msix_cap && pci_msi_enabled())
1048 		return pm8001_request_msix(pm8001_ha);
1049 	else {
1050 		pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1051 		goto intx;
1052 	}
1053 #endif
1054 
1055 intx:
1056 	/* initialize the INT-X interrupt */
1057 	pm8001_ha->irq_vector[0].irq_id = 0;
1058 	pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
1059 	rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
1060 		pm8001_ha->name, SHOST_TO_SAS_HA(pm8001_ha->shost));
1061 	return rc;
1062 }
1063 
1064 /**
1065  * pm8001_pci_probe - probe supported device
1066  * @pdev: pci device which kernel has been prepared for.
1067  * @ent: pci device id
1068  *
1069  * This function is the main initialization function, when register a new
1070  * pci driver it is invoked, all struct and hardware initialization should be
1071  * done here, also, register interrupt.
1072  */
1073 static int pm8001_pci_probe(struct pci_dev *pdev,
1074 			    const struct pci_device_id *ent)
1075 {
1076 	unsigned int rc;
1077 	u32	pci_reg;
1078 	u8	i = 0;
1079 	struct pm8001_hba_info *pm8001_ha;
1080 	struct Scsi_Host *shost = NULL;
1081 	const struct pm8001_chip_info *chip;
1082 	struct sas_ha_struct *sha;
1083 
1084 	dev_printk(KERN_INFO, &pdev->dev,
1085 		"pm80xx: driver version %s\n", DRV_VERSION);
1086 	rc = pci_enable_device(pdev);
1087 	if (rc)
1088 		goto err_out_enable;
1089 	pci_set_master(pdev);
1090 	/*
1091 	 * Enable pci slot busmaster by setting pci command register.
1092 	 * This is required by FW for Cyclone card.
1093 	 */
1094 
1095 	pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
1096 	pci_reg |= 0x157;
1097 	pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
1098 	rc = pci_request_regions(pdev, DRV_NAME);
1099 	if (rc)
1100 		goto err_out_disable;
1101 	rc = pci_go_44(pdev);
1102 	if (rc)
1103 		goto err_out_regions;
1104 
1105 	shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
1106 	if (!shost) {
1107 		rc = -ENOMEM;
1108 		goto err_out_regions;
1109 	}
1110 	chip = &pm8001_chips[ent->driver_data];
1111 	sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
1112 	if (!sha) {
1113 		rc = -ENOMEM;
1114 		goto err_out_free_host;
1115 	}
1116 	SHOST_TO_SAS_HA(shost) = sha;
1117 
1118 	rc = pm8001_prep_sas_ha_init(shost, chip);
1119 	if (rc) {
1120 		rc = -ENOMEM;
1121 		goto err_out_free;
1122 	}
1123 	pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
1124 	/* ent->driver variable is used to differentiate between controllers */
1125 	pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
1126 	if (!pm8001_ha) {
1127 		rc = -ENOMEM;
1128 		goto err_out_free;
1129 	}
1130 
1131 	PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1132 	rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1133 	if (rc) {
1134 		pm8001_dbg(pm8001_ha, FAIL,
1135 			   "chip_init failed [ret: %d]\n", rc);
1136 		goto err_out_ha_free;
1137 	}
1138 
1139 	rc = pm8001_init_ccb_tag(pm8001_ha);
1140 	if (rc)
1141 		goto err_out_enable;
1142 
1143 
1144 	PM8001_CHIP_DISP->chip_post_init(pm8001_ha);
1145 
1146 	if (pm8001_ha->number_of_intr > 1) {
1147 		shost->nr_hw_queues = pm8001_ha->number_of_intr - 1;
1148 		/*
1149 		 * For now, ensure we're not sent too many commands by setting
1150 		 * host_tagset. This is also required if we start using request
1151 		 * tag.
1152 		 */
1153 		shost->host_tagset = 1;
1154 	}
1155 
1156 	rc = scsi_add_host(shost, &pdev->dev);
1157 	if (rc)
1158 		goto err_out_ha_free;
1159 
1160 	PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1161 	if (pm8001_ha->chip_id != chip_8001) {
1162 		for (i = 1; i < pm8001_ha->number_of_intr; i++)
1163 			PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1164 		/* setup thermal configuration. */
1165 		pm80xx_set_thermal_config(pm8001_ha);
1166 	}
1167 
1168 	pm8001_init_sas_add(pm8001_ha);
1169 	/* phy setting support for motherboard controller */
1170 	rc = pm8001_configure_phy_settings(pm8001_ha);
1171 	if (rc)
1172 		goto err_out_shost;
1173 
1174 	pm8001_post_sas_ha_init(shost, chip);
1175 	rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
1176 	if (rc) {
1177 		pm8001_dbg(pm8001_ha, FAIL,
1178 			   "sas_register_ha failed [ret: %d]\n", rc);
1179 		goto err_out_shost;
1180 	}
1181 	list_add_tail(&pm8001_ha->list, &hba_list);
1182 	pm8001_ha->flags = PM8001F_RUN_TIME;
1183 	scsi_scan_host(pm8001_ha->shost);
1184 	return 0;
1185 
1186 err_out_shost:
1187 	scsi_remove_host(pm8001_ha->shost);
1188 err_out_ha_free:
1189 	pm8001_free(pm8001_ha);
1190 err_out_free:
1191 	kfree(sha);
1192 err_out_free_host:
1193 	scsi_host_put(shost);
1194 err_out_regions:
1195 	pci_release_regions(pdev);
1196 err_out_disable:
1197 	pci_disable_device(pdev);
1198 err_out_enable:
1199 	return rc;
1200 }
1201 
1202 /**
1203  * pm8001_init_ccb_tag - allocate memory to CCB and tag.
1204  * @pm8001_ha: our hba card information.
1205  */
1206 static int pm8001_init_ccb_tag(struct pm8001_hba_info *pm8001_ha)
1207 {
1208 	struct Scsi_Host *shost = pm8001_ha->shost;
1209 	struct device *dev = pm8001_ha->dev;
1210 	u32 max_out_io, ccb_count;
1211 	u32 can_queue;
1212 	int i;
1213 
1214 	max_out_io = pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io;
1215 	ccb_count = min_t(int, PM8001_MAX_CCB, max_out_io);
1216 
1217 	/* Update to the scsi host*/
1218 	can_queue = ccb_count - PM8001_RESERVE_SLOT;
1219 	shost->can_queue = can_queue;
1220 
1221 	pm8001_ha->tags = bitmap_zalloc(ccb_count, GFP_KERNEL);
1222 	if (!pm8001_ha->tags)
1223 		goto err_out;
1224 
1225 	/* Memory region for ccb_info*/
1226 	pm8001_ha->ccb_count = ccb_count;
1227 	pm8001_ha->ccb_info =
1228 		kcalloc(ccb_count, sizeof(struct pm8001_ccb_info), GFP_KERNEL);
1229 	if (!pm8001_ha->ccb_info) {
1230 		pm8001_dbg(pm8001_ha, FAIL,
1231 			   "Unable to allocate memory for ccb\n");
1232 		goto err_out_noccb;
1233 	}
1234 	for (i = 0; i < ccb_count; i++) {
1235 		pm8001_ha->ccb_info[i].buf_prd = dma_alloc_coherent(dev,
1236 				sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1237 				&pm8001_ha->ccb_info[i].ccb_dma_handle,
1238 				GFP_KERNEL);
1239 		if (!pm8001_ha->ccb_info[i].buf_prd) {
1240 			pm8001_dbg(pm8001_ha, FAIL,
1241 				   "ccb prd memory allocation error\n");
1242 			goto err_out;
1243 		}
1244 		pm8001_ha->ccb_info[i].task = NULL;
1245 		pm8001_ha->ccb_info[i].ccb_tag = PM8001_INVALID_TAG;
1246 		pm8001_ha->ccb_info[i].device = NULL;
1247 		++pm8001_ha->tags_num;
1248 	}
1249 
1250 	return 0;
1251 
1252 err_out_noccb:
1253 	kfree(pm8001_ha->devices);
1254 err_out:
1255 	return -ENOMEM;
1256 }
1257 
1258 static void pm8001_pci_remove(struct pci_dev *pdev)
1259 {
1260 	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1261 	struct pm8001_hba_info *pm8001_ha;
1262 	int i, j;
1263 	pm8001_ha = sha->lldd_ha;
1264 	sas_unregister_ha(sha);
1265 	sas_remove_host(pm8001_ha->shost);
1266 	list_del(&pm8001_ha->list);
1267 	PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1268 	PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1269 
1270 #ifdef PM8001_USE_MSIX
1271 	for (i = 0; i < pm8001_ha->number_of_intr; i++)
1272 		synchronize_irq(pci_irq_vector(pdev, i));
1273 	for (i = 0; i < pm8001_ha->number_of_intr; i++)
1274 		free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1275 	pci_free_irq_vectors(pdev);
1276 #else
1277 	free_irq(pm8001_ha->irq, sha);
1278 #endif
1279 #ifdef PM8001_USE_TASKLET
1280 	/* For non-msix and msix interrupts */
1281 	if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1282 	    (pm8001_ha->chip_id == chip_8001))
1283 		tasklet_kill(&pm8001_ha->tasklet[0]);
1284 	else
1285 		for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1286 			tasklet_kill(&pm8001_ha->tasklet[j]);
1287 #endif
1288 	scsi_host_put(pm8001_ha->shost);
1289 
1290 	for (i = 0; i < pm8001_ha->ccb_count; i++) {
1291 		dma_free_coherent(&pm8001_ha->pdev->dev,
1292 			sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1293 			pm8001_ha->ccb_info[i].buf_prd,
1294 			pm8001_ha->ccb_info[i].ccb_dma_handle);
1295 	}
1296 	kfree(pm8001_ha->ccb_info);
1297 	kfree(pm8001_ha->devices);
1298 
1299 	pm8001_free(pm8001_ha);
1300 	kfree(sha->sas_phy);
1301 	kfree(sha->sas_port);
1302 	kfree(sha);
1303 	pci_release_regions(pdev);
1304 	pci_disable_device(pdev);
1305 }
1306 
1307 /**
1308  * pm8001_pci_suspend - power management suspend main entry point
1309  * @dev: Device struct
1310  *
1311  * Return: 0 on success, anything else on error.
1312  */
1313 static int __maybe_unused pm8001_pci_suspend(struct device *dev)
1314 {
1315 	struct pci_dev *pdev = to_pci_dev(dev);
1316 	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1317 	struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
1318 	int  i, j;
1319 	sas_suspend_ha(sha);
1320 	flush_workqueue(pm8001_wq);
1321 	scsi_block_requests(pm8001_ha->shost);
1322 	if (!pdev->pm_cap) {
1323 		dev_err(dev, " PCI PM not supported\n");
1324 		return -ENODEV;
1325 	}
1326 	PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1327 	PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1328 #ifdef PM8001_USE_MSIX
1329 	for (i = 0; i < pm8001_ha->number_of_intr; i++)
1330 		synchronize_irq(pci_irq_vector(pdev, i));
1331 	for (i = 0; i < pm8001_ha->number_of_intr; i++)
1332 		free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1333 	pci_free_irq_vectors(pdev);
1334 #else
1335 	free_irq(pm8001_ha->irq, sha);
1336 #endif
1337 #ifdef PM8001_USE_TASKLET
1338 	/* For non-msix and msix interrupts */
1339 	if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1340 	    (pm8001_ha->chip_id == chip_8001))
1341 		tasklet_kill(&pm8001_ha->tasklet[0]);
1342 	else
1343 		for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1344 			tasklet_kill(&pm8001_ha->tasklet[j]);
1345 #endif
1346 	pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, entering "
1347 		      "suspended state\n", pdev,
1348 		      pm8001_ha->name);
1349 	return 0;
1350 }
1351 
1352 /**
1353  * pm8001_pci_resume - power management resume main entry point
1354  * @dev: Device struct
1355  *
1356  * Return: 0 on success, anything else on error.
1357  */
1358 static int __maybe_unused pm8001_pci_resume(struct device *dev)
1359 {
1360 	struct pci_dev *pdev = to_pci_dev(dev);
1361 	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1362 	struct pm8001_hba_info *pm8001_ha;
1363 	int rc;
1364 	u8 i = 0, j;
1365 	DECLARE_COMPLETION_ONSTACK(completion);
1366 
1367 	pm8001_ha = sha->lldd_ha;
1368 
1369 	pm8001_info(pm8001_ha,
1370 		    "pdev=0x%p, slot=%s, resuming from previous operating state [D%d]\n",
1371 		    pdev, pm8001_ha->name, pdev->current_state);
1372 
1373 	rc = pci_go_44(pdev);
1374 	if (rc)
1375 		goto err_out_disable;
1376 	sas_prep_resume_ha(sha);
1377 	/* chip soft rst only for spc */
1378 	if (pm8001_ha->chip_id == chip_8001) {
1379 		PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1380 		pm8001_dbg(pm8001_ha, INIT, "chip soft reset successful\n");
1381 	}
1382 	rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1383 	if (rc)
1384 		goto err_out_disable;
1385 
1386 	/* disable all the interrupt bits */
1387 	PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1388 
1389 	rc = pm8001_request_irq(pm8001_ha);
1390 	if (rc)
1391 		goto err_out_disable;
1392 #ifdef PM8001_USE_TASKLET
1393 	/*  Tasklet for non msi-x interrupt handler */
1394 	if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1395 	    (pm8001_ha->chip_id == chip_8001))
1396 		tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1397 			(unsigned long)&(pm8001_ha->irq_vector[0]));
1398 	else
1399 		for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1400 			tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1401 				(unsigned long)&(pm8001_ha->irq_vector[j]));
1402 #endif
1403 	PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1404 	if (pm8001_ha->chip_id != chip_8001) {
1405 		for (i = 1; i < pm8001_ha->number_of_intr; i++)
1406 			PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1407 	}
1408 
1409 	/* Chip documentation for the 8070 and 8072 SPCv    */
1410 	/* states that a 500ms minimum delay is required    */
1411 	/* before issuing commands. Otherwise, the firmware */
1412 	/* will enter an unrecoverable state.               */
1413 
1414 	if (pm8001_ha->chip_id == chip_8070 ||
1415 		pm8001_ha->chip_id == chip_8072) {
1416 		mdelay(500);
1417 	}
1418 
1419 	/* Spin up the PHYs */
1420 
1421 	pm8001_ha->flags = PM8001F_RUN_TIME;
1422 	for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1423 		pm8001_ha->phy[i].enable_completion = &completion;
1424 		PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1425 		wait_for_completion(&completion);
1426 	}
1427 	sas_resume_ha(sha);
1428 	return 0;
1429 
1430 err_out_disable:
1431 	scsi_remove_host(pm8001_ha->shost);
1432 
1433 	return rc;
1434 }
1435 
1436 /* update of pci device, vendor id and driver data with
1437  * unique value for each of the controller
1438  */
1439 static struct pci_device_id pm8001_pci_table[] = {
1440 	{ PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1441 	{ PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1442 	{ PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1443 	{ PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1444 	/* Support for SPC/SPCv/SPCve controllers */
1445 	{ PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1446 	{ PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1447 	{ PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1448 	{ PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1449 	{ PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1450 	{ PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1451 	{ PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1452 	{ PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1453 	{ PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1454 	{ PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1455 	{ PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1456 	{ PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1457 	{ PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1458 	{ PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1459 	{ PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1460 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1461 		PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1462 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1463 		PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1464 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1465 		PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1466 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1467 		PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1468 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1469 		PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1470 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1471 		PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1472 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1473 		PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1474 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1475 		PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1476 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1477 		PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1478 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1479 		PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1480 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1481 		PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1482 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1483 		PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1484 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1485 		PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1486 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1487 		PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1488 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1489 		PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1490 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1491 		PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1492 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1493 		PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1494 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1495 		PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1496 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1497 		PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1498 	{ PCI_VENDOR_ID_ATTO, 0x8070,
1499 		PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1500 	{ PCI_VENDOR_ID_ATTO, 0x8070,
1501 		PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1502 	{ PCI_VENDOR_ID_ATTO, 0x8072,
1503 		PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1504 	{ PCI_VENDOR_ID_ATTO, 0x8072,
1505 		PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1506 	{ PCI_VENDOR_ID_ATTO, 0x8070,
1507 		PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1508 	{ PCI_VENDOR_ID_ATTO, 0x8072,
1509 		PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1510 	{ PCI_VENDOR_ID_ATTO, 0x8072,
1511 		PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1512 	{} /* terminate list */
1513 };
1514 
1515 static SIMPLE_DEV_PM_OPS(pm8001_pci_pm_ops,
1516 			 pm8001_pci_suspend,
1517 			 pm8001_pci_resume);
1518 
1519 static struct pci_driver pm8001_pci_driver = {
1520 	.name		= DRV_NAME,
1521 	.id_table	= pm8001_pci_table,
1522 	.probe		= pm8001_pci_probe,
1523 	.remove		= pm8001_pci_remove,
1524 	.driver.pm	= &pm8001_pci_pm_ops,
1525 };
1526 
1527 /**
1528  *	pm8001_init - initialize scsi transport template
1529  */
1530 static int __init pm8001_init(void)
1531 {
1532 	int rc = -ENOMEM;
1533 
1534 	pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1535 	if (!pm8001_wq)
1536 		goto err;
1537 
1538 	pm8001_id = 0;
1539 	pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1540 	if (!pm8001_stt)
1541 		goto err_wq;
1542 	rc = pci_register_driver(&pm8001_pci_driver);
1543 	if (rc)
1544 		goto err_tp;
1545 	return 0;
1546 
1547 err_tp:
1548 	sas_release_transport(pm8001_stt);
1549 err_wq:
1550 	destroy_workqueue(pm8001_wq);
1551 err:
1552 	return rc;
1553 }
1554 
1555 static void __exit pm8001_exit(void)
1556 {
1557 	pci_unregister_driver(&pm8001_pci_driver);
1558 	sas_release_transport(pm8001_stt);
1559 	destroy_workqueue(pm8001_wq);
1560 }
1561 
1562 module_init(pm8001_init);
1563 module_exit(pm8001_exit);
1564 
1565 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1566 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1567 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1568 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1569 MODULE_DESCRIPTION(
1570 		"PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1571 		"SAS/SATA controller driver");
1572 MODULE_VERSION(DRV_VERSION);
1573 MODULE_LICENSE("GPL");
1574 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1575 
1576