1 /* 2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 USI Co., Ltd. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 41 #include <linux/slab.h> 42 #include "pm8001_sas.h" 43 #include "pm8001_chips.h" 44 #include "pm80xx_hwi.h" 45 46 static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING; 47 module_param(logging_level, ulong, 0644); 48 MODULE_PARM_DESC(logging_level, " bits for enabling logging info."); 49 50 static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120; 51 module_param(link_rate, ulong, 0644); 52 MODULE_PARM_DESC(link_rate, "Enable link rate.\n" 53 " 1: Link rate 1.5G\n" 54 " 2: Link rate 3.0G\n" 55 " 4: Link rate 6.0G\n" 56 " 8: Link rate 12.0G\n"); 57 58 static struct scsi_transport_template *pm8001_stt; 59 60 /** 61 * chip info structure to identify chip key functionality as 62 * encryption available/not, no of ports, hw specific function ref 63 */ 64 static const struct pm8001_chip_info pm8001_chips[] = { 65 [chip_8001] = {0, 8, &pm8001_8001_dispatch,}, 66 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,}, 67 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,}, 68 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,}, 69 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,}, 70 [chip_8074] = {0, 8, &pm8001_80xx_dispatch,}, 71 [chip_8076] = {0, 16, &pm8001_80xx_dispatch,}, 72 [chip_8077] = {0, 16, &pm8001_80xx_dispatch,}, 73 [chip_8006] = {0, 16, &pm8001_80xx_dispatch,}, 74 [chip_8070] = {0, 8, &pm8001_80xx_dispatch,}, 75 [chip_8072] = {0, 16, &pm8001_80xx_dispatch,}, 76 }; 77 static int pm8001_id; 78 79 LIST_HEAD(hba_list); 80 81 struct workqueue_struct *pm8001_wq; 82 83 /** 84 * The main structure which LLDD must register for scsi core. 85 */ 86 static struct scsi_host_template pm8001_sht = { 87 .module = THIS_MODULE, 88 .name = DRV_NAME, 89 .queuecommand = sas_queuecommand, 90 .target_alloc = sas_target_alloc, 91 .slave_configure = sas_slave_configure, 92 .scan_finished = pm8001_scan_finished, 93 .scan_start = pm8001_scan_start, 94 .change_queue_depth = sas_change_queue_depth, 95 .bios_param = sas_bios_param, 96 .can_queue = 1, 97 .this_id = -1, 98 .sg_tablesize = PM8001_MAX_DMA_SG, 99 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 100 .eh_device_reset_handler = sas_eh_device_reset_handler, 101 .eh_target_reset_handler = sas_eh_target_reset_handler, 102 .target_destroy = sas_target_destroy, 103 .ioctl = sas_ioctl, 104 #ifdef CONFIG_COMPAT 105 .compat_ioctl = sas_ioctl, 106 #endif 107 .shost_attrs = pm8001_host_attrs, 108 .track_queue_depth = 1, 109 }; 110 111 /** 112 * Sas layer call this function to execute specific task. 113 */ 114 static struct sas_domain_function_template pm8001_transport_ops = { 115 .lldd_dev_found = pm8001_dev_found, 116 .lldd_dev_gone = pm8001_dev_gone, 117 118 .lldd_execute_task = pm8001_queue_command, 119 .lldd_control_phy = pm8001_phy_control, 120 121 .lldd_abort_task = pm8001_abort_task, 122 .lldd_abort_task_set = pm8001_abort_task_set, 123 .lldd_clear_aca = pm8001_clear_aca, 124 .lldd_clear_task_set = pm8001_clear_task_set, 125 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset, 126 .lldd_lu_reset = pm8001_lu_reset, 127 .lldd_query_task = pm8001_query_task, 128 }; 129 130 /** 131 *pm8001_phy_init - initiate our adapter phys 132 *@pm8001_ha: our hba structure. 133 *@phy_id: phy id. 134 */ 135 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id) 136 { 137 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 138 struct asd_sas_phy *sas_phy = &phy->sas_phy; 139 phy->phy_state = PHY_LINK_DISABLE; 140 phy->pm8001_ha = pm8001_ha; 141 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0; 142 sas_phy->class = SAS; 143 sas_phy->iproto = SAS_PROTOCOL_ALL; 144 sas_phy->tproto = 0; 145 sas_phy->type = PHY_TYPE_PHYSICAL; 146 sas_phy->role = PHY_ROLE_INITIATOR; 147 sas_phy->oob_mode = OOB_NOT_CONNECTED; 148 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN; 149 sas_phy->id = phy_id; 150 sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr; 151 sas_phy->frame_rcvd = &phy->frame_rcvd[0]; 152 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata; 153 sas_phy->lldd_phy = phy; 154 } 155 156 /** 157 *pm8001_free - free hba 158 *@pm8001_ha: our hba structure. 159 * 160 */ 161 static void pm8001_free(struct pm8001_hba_info *pm8001_ha) 162 { 163 int i; 164 165 if (!pm8001_ha) 166 return; 167 168 for (i = 0; i < USI_MAX_MEMCNT; i++) { 169 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) { 170 dma_free_coherent(&pm8001_ha->pdev->dev, 171 (pm8001_ha->memoryMap.region[i].total_len + 172 pm8001_ha->memoryMap.region[i].alignment), 173 pm8001_ha->memoryMap.region[i].virt_ptr, 174 pm8001_ha->memoryMap.region[i].phys_addr); 175 } 176 } 177 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha); 178 flush_workqueue(pm8001_wq); 179 kfree(pm8001_ha->tags); 180 kfree(pm8001_ha); 181 } 182 183 #ifdef PM8001_USE_TASKLET 184 185 /** 186 * tasklet for 64 msi-x interrupt handler 187 * @opaque: the passed general host adapter struct 188 * Note: pm8001_tasklet is common for pm8001 & pm80xx 189 */ 190 static void pm8001_tasklet(unsigned long opaque) 191 { 192 struct pm8001_hba_info *pm8001_ha; 193 struct isr_param *irq_vector; 194 195 irq_vector = (struct isr_param *)opaque; 196 pm8001_ha = irq_vector->drv_inst; 197 if (unlikely(!pm8001_ha)) 198 BUG_ON(1); 199 PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id); 200 } 201 #endif 202 203 /** 204 * pm8001_interrupt_handler_msix - main MSIX interrupt handler. 205 * It obtains the vector number and calls the equivalent bottom 206 * half or services directly. 207 * @opaque: the passed outbound queue/vector. Host structure is 208 * retrieved from the same. 209 */ 210 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque) 211 { 212 struct isr_param *irq_vector; 213 struct pm8001_hba_info *pm8001_ha; 214 irqreturn_t ret = IRQ_HANDLED; 215 irq_vector = (struct isr_param *)opaque; 216 pm8001_ha = irq_vector->drv_inst; 217 218 if (unlikely(!pm8001_ha)) 219 return IRQ_NONE; 220 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha)) 221 return IRQ_NONE; 222 #ifdef PM8001_USE_TASKLET 223 tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]); 224 #else 225 ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id); 226 #endif 227 return ret; 228 } 229 230 /** 231 * pm8001_interrupt_handler_intx - main INTx interrupt handler. 232 * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure. 233 */ 234 235 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id) 236 { 237 struct pm8001_hba_info *pm8001_ha; 238 irqreturn_t ret = IRQ_HANDLED; 239 struct sas_ha_struct *sha = dev_id; 240 pm8001_ha = sha->lldd_ha; 241 if (unlikely(!pm8001_ha)) 242 return IRQ_NONE; 243 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha)) 244 return IRQ_NONE; 245 246 #ifdef PM8001_USE_TASKLET 247 tasklet_schedule(&pm8001_ha->tasklet[0]); 248 #else 249 ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0); 250 #endif 251 return ret; 252 } 253 254 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha); 255 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha); 256 257 /** 258 * pm8001_alloc - initiate our hba structure and 6 DMAs area. 259 * @pm8001_ha:our hba structure. 260 * 261 */ 262 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha, 263 const struct pci_device_id *ent) 264 { 265 int i; 266 spin_lock_init(&pm8001_ha->lock); 267 spin_lock_init(&pm8001_ha->bitmap_lock); 268 PM8001_INIT_DBG(pm8001_ha, 269 pm8001_printk("pm8001_alloc: PHY:%x\n", 270 pm8001_ha->chip->n_phy)); 271 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 272 pm8001_phy_init(pm8001_ha, i); 273 pm8001_ha->port[i].wide_port_phymap = 0; 274 pm8001_ha->port[i].port_attached = 0; 275 pm8001_ha->port[i].port_state = 0; 276 INIT_LIST_HEAD(&pm8001_ha->port[i].list); 277 } 278 279 pm8001_ha->tags = kzalloc(PM8001_MAX_CCB, GFP_KERNEL); 280 if (!pm8001_ha->tags) 281 goto err_out; 282 /* MPI Memory region 1 for AAP Event Log for fw */ 283 pm8001_ha->memoryMap.region[AAP1].num_elements = 1; 284 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE; 285 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE; 286 pm8001_ha->memoryMap.region[AAP1].alignment = 32; 287 288 /* MPI Memory region 2 for IOP Event Log for fw */ 289 pm8001_ha->memoryMap.region[IOP].num_elements = 1; 290 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE; 291 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE; 292 pm8001_ha->memoryMap.region[IOP].alignment = 32; 293 294 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) { 295 /* MPI Memory region 3 for consumer Index of inbound queues */ 296 pm8001_ha->memoryMap.region[CI+i].num_elements = 1; 297 pm8001_ha->memoryMap.region[CI+i].element_size = 4; 298 pm8001_ha->memoryMap.region[CI+i].total_len = 4; 299 pm8001_ha->memoryMap.region[CI+i].alignment = 4; 300 301 if ((ent->driver_data) != chip_8001) { 302 /* MPI Memory region 5 inbound queues */ 303 pm8001_ha->memoryMap.region[IB+i].num_elements = 304 PM8001_MPI_QUEUE; 305 pm8001_ha->memoryMap.region[IB+i].element_size = 128; 306 pm8001_ha->memoryMap.region[IB+i].total_len = 307 PM8001_MPI_QUEUE * 128; 308 pm8001_ha->memoryMap.region[IB+i].alignment = 128; 309 } else { 310 pm8001_ha->memoryMap.region[IB+i].num_elements = 311 PM8001_MPI_QUEUE; 312 pm8001_ha->memoryMap.region[IB+i].element_size = 64; 313 pm8001_ha->memoryMap.region[IB+i].total_len = 314 PM8001_MPI_QUEUE * 64; 315 pm8001_ha->memoryMap.region[IB+i].alignment = 64; 316 } 317 } 318 319 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) { 320 /* MPI Memory region 4 for producer Index of outbound queues */ 321 pm8001_ha->memoryMap.region[PI+i].num_elements = 1; 322 pm8001_ha->memoryMap.region[PI+i].element_size = 4; 323 pm8001_ha->memoryMap.region[PI+i].total_len = 4; 324 pm8001_ha->memoryMap.region[PI+i].alignment = 4; 325 326 if (ent->driver_data != chip_8001) { 327 /* MPI Memory region 6 Outbound queues */ 328 pm8001_ha->memoryMap.region[OB+i].num_elements = 329 PM8001_MPI_QUEUE; 330 pm8001_ha->memoryMap.region[OB+i].element_size = 128; 331 pm8001_ha->memoryMap.region[OB+i].total_len = 332 PM8001_MPI_QUEUE * 128; 333 pm8001_ha->memoryMap.region[OB+i].alignment = 128; 334 } else { 335 /* MPI Memory region 6 Outbound queues */ 336 pm8001_ha->memoryMap.region[OB+i].num_elements = 337 PM8001_MPI_QUEUE; 338 pm8001_ha->memoryMap.region[OB+i].element_size = 64; 339 pm8001_ha->memoryMap.region[OB+i].total_len = 340 PM8001_MPI_QUEUE * 64; 341 pm8001_ha->memoryMap.region[OB+i].alignment = 64; 342 } 343 344 } 345 /* Memory region write DMA*/ 346 pm8001_ha->memoryMap.region[NVMD].num_elements = 1; 347 pm8001_ha->memoryMap.region[NVMD].element_size = 4096; 348 pm8001_ha->memoryMap.region[NVMD].total_len = 4096; 349 /* Memory region for devices*/ 350 pm8001_ha->memoryMap.region[DEV_MEM].num_elements = 1; 351 pm8001_ha->memoryMap.region[DEV_MEM].element_size = PM8001_MAX_DEVICES * 352 sizeof(struct pm8001_device); 353 pm8001_ha->memoryMap.region[DEV_MEM].total_len = PM8001_MAX_DEVICES * 354 sizeof(struct pm8001_device); 355 356 /* Memory region for ccb_info*/ 357 pm8001_ha->memoryMap.region[CCB_MEM].num_elements = 1; 358 pm8001_ha->memoryMap.region[CCB_MEM].element_size = PM8001_MAX_CCB * 359 sizeof(struct pm8001_ccb_info); 360 pm8001_ha->memoryMap.region[CCB_MEM].total_len = PM8001_MAX_CCB * 361 sizeof(struct pm8001_ccb_info); 362 363 /* Memory region for fw flash */ 364 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096; 365 366 pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1; 367 pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000; 368 pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000; 369 pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000; 370 for (i = 0; i < USI_MAX_MEMCNT; i++) { 371 if (pm8001_mem_alloc(pm8001_ha->pdev, 372 &pm8001_ha->memoryMap.region[i].virt_ptr, 373 &pm8001_ha->memoryMap.region[i].phys_addr, 374 &pm8001_ha->memoryMap.region[i].phys_addr_hi, 375 &pm8001_ha->memoryMap.region[i].phys_addr_lo, 376 pm8001_ha->memoryMap.region[i].total_len, 377 pm8001_ha->memoryMap.region[i].alignment) != 0) { 378 PM8001_FAIL_DBG(pm8001_ha, 379 pm8001_printk("Mem%d alloc failed\n", 380 i)); 381 goto err_out; 382 } 383 } 384 385 pm8001_ha->devices = pm8001_ha->memoryMap.region[DEV_MEM].virt_ptr; 386 for (i = 0; i < PM8001_MAX_DEVICES; i++) { 387 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED; 388 pm8001_ha->devices[i].id = i; 389 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES; 390 pm8001_ha->devices[i].running_req = 0; 391 } 392 pm8001_ha->ccb_info = pm8001_ha->memoryMap.region[CCB_MEM].virt_ptr; 393 for (i = 0; i < PM8001_MAX_CCB; i++) { 394 pm8001_ha->ccb_info[i].ccb_dma_handle = 395 pm8001_ha->memoryMap.region[CCB_MEM].phys_addr + 396 i * sizeof(struct pm8001_ccb_info); 397 pm8001_ha->ccb_info[i].task = NULL; 398 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff; 399 pm8001_ha->ccb_info[i].device = NULL; 400 ++pm8001_ha->tags_num; 401 } 402 pm8001_ha->flags = PM8001F_INIT_TIME; 403 /* Initialize tags */ 404 pm8001_tag_init(pm8001_ha); 405 return 0; 406 err_out: 407 return 1; 408 } 409 410 /** 411 * pm8001_ioremap - remap the pci high physical address to kernal virtual 412 * address so that we can access them. 413 * @pm8001_ha:our hba structure. 414 */ 415 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha) 416 { 417 u32 bar; 418 u32 logicalBar = 0; 419 struct pci_dev *pdev; 420 421 pdev = pm8001_ha->pdev; 422 /* map pci mem (PMC pci base 0-3)*/ 423 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { 424 /* 425 ** logical BARs for SPC: 426 ** bar 0 and 1 - logical BAR0 427 ** bar 2 and 3 - logical BAR1 428 ** bar4 - logical BAR2 429 ** bar5 - logical BAR3 430 ** Skip the appropriate assignments: 431 */ 432 if ((bar == 1) || (bar == 3)) 433 continue; 434 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { 435 pm8001_ha->io_mem[logicalBar].membase = 436 pci_resource_start(pdev, bar); 437 pm8001_ha->io_mem[logicalBar].memsize = 438 pci_resource_len(pdev, bar); 439 pm8001_ha->io_mem[logicalBar].memvirtaddr = 440 ioremap(pm8001_ha->io_mem[logicalBar].membase, 441 pm8001_ha->io_mem[logicalBar].memsize); 442 PM8001_INIT_DBG(pm8001_ha, 443 pm8001_printk("PCI: bar %d, logicalBar %d ", 444 bar, logicalBar)); 445 PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 446 "base addr %llx virt_addr=%llx len=%d\n", 447 (u64)pm8001_ha->io_mem[logicalBar].membase, 448 (u64)(unsigned long) 449 pm8001_ha->io_mem[logicalBar].memvirtaddr, 450 pm8001_ha->io_mem[logicalBar].memsize)); 451 } else { 452 pm8001_ha->io_mem[logicalBar].membase = 0; 453 pm8001_ha->io_mem[logicalBar].memsize = 0; 454 pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL; 455 } 456 logicalBar++; 457 } 458 return 0; 459 } 460 461 /** 462 * pm8001_pci_alloc - initialize our ha card structure 463 * @pdev: pci device. 464 * @ent: ent 465 * @shost: scsi host struct which has been initialized before. 466 */ 467 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev, 468 const struct pci_device_id *ent, 469 struct Scsi_Host *shost) 470 471 { 472 struct pm8001_hba_info *pm8001_ha; 473 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 474 int j; 475 476 pm8001_ha = sha->lldd_ha; 477 if (!pm8001_ha) 478 return NULL; 479 480 pm8001_ha->pdev = pdev; 481 pm8001_ha->dev = &pdev->dev; 482 pm8001_ha->chip_id = ent->driver_data; 483 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id]; 484 pm8001_ha->irq = pdev->irq; 485 pm8001_ha->sas = sha; 486 pm8001_ha->shost = shost; 487 pm8001_ha->id = pm8001_id++; 488 pm8001_ha->logging_level = logging_level; 489 pm8001_ha->non_fatal_count = 0; 490 if (link_rate >= 1 && link_rate <= 15) 491 pm8001_ha->link_rate = (link_rate << 8); 492 else { 493 pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 | 494 LINKRATE_60 | LINKRATE_120; 495 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 496 "Setting link rate to default value\n")); 497 } 498 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id); 499 /* IOMB size is 128 for 8088/89 controllers */ 500 if (pm8001_ha->chip_id != chip_8001) 501 pm8001_ha->iomb_size = IOMB_SIZE_SPCV; 502 else 503 pm8001_ha->iomb_size = IOMB_SIZE_SPC; 504 505 #ifdef PM8001_USE_TASKLET 506 /* Tasklet for non msi-x interrupt handler */ 507 if ((!pdev->msix_cap || !pci_msi_enabled()) 508 || (pm8001_ha->chip_id == chip_8001)) 509 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet, 510 (unsigned long)&(pm8001_ha->irq_vector[0])); 511 else 512 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 513 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet, 514 (unsigned long)&(pm8001_ha->irq_vector[j])); 515 #endif 516 pm8001_ioremap(pm8001_ha); 517 if (!pm8001_alloc(pm8001_ha, ent)) 518 return pm8001_ha; 519 pm8001_free(pm8001_ha); 520 return NULL; 521 } 522 523 /** 524 * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit 525 * @pdev: pci device. 526 */ 527 static int pci_go_44(struct pci_dev *pdev) 528 { 529 int rc; 530 531 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44)); 532 if (rc) { 533 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 534 if (rc) 535 dev_printk(KERN_ERR, &pdev->dev, 536 "32-bit DMA enable failed\n"); 537 } 538 return rc; 539 } 540 541 /** 542 * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them. 543 * @shost: scsi host which has been allocated outside. 544 * @chip_info: our ha struct. 545 */ 546 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost, 547 const struct pm8001_chip_info *chip_info) 548 { 549 int phy_nr, port_nr; 550 struct asd_sas_phy **arr_phy; 551 struct asd_sas_port **arr_port; 552 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 553 554 phy_nr = chip_info->n_phy; 555 port_nr = phy_nr; 556 memset(sha, 0x00, sizeof(*sha)); 557 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL); 558 if (!arr_phy) 559 goto exit; 560 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL); 561 if (!arr_port) 562 goto exit_free2; 563 564 sha->sas_phy = arr_phy; 565 sha->sas_port = arr_port; 566 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL); 567 if (!sha->lldd_ha) 568 goto exit_free1; 569 570 shost->transportt = pm8001_stt; 571 shost->max_id = PM8001_MAX_DEVICES; 572 shost->max_lun = 8; 573 shost->max_channel = 0; 574 shost->unique_id = pm8001_id; 575 shost->max_cmd_len = 16; 576 shost->can_queue = PM8001_CAN_QUEUE; 577 shost->cmd_per_lun = 32; 578 return 0; 579 exit_free1: 580 kfree(arr_port); 581 exit_free2: 582 kfree(arr_phy); 583 exit: 584 return -1; 585 } 586 587 /** 588 * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas 589 * @shost: scsi host which has been allocated outside 590 * @chip_info: our ha struct. 591 */ 592 static void pm8001_post_sas_ha_init(struct Scsi_Host *shost, 593 const struct pm8001_chip_info *chip_info) 594 { 595 int i = 0; 596 struct pm8001_hba_info *pm8001_ha; 597 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 598 599 pm8001_ha = sha->lldd_ha; 600 for (i = 0; i < chip_info->n_phy; i++) { 601 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy; 602 sha->sas_port[i] = &pm8001_ha->port[i].sas_port; 603 sha->sas_phy[i]->sas_addr = 604 (u8 *)&pm8001_ha->phy[i].dev_sas_addr; 605 } 606 sha->sas_ha_name = DRV_NAME; 607 sha->dev = pm8001_ha->dev; 608 sha->strict_wide_ports = 1; 609 sha->lldd_module = THIS_MODULE; 610 sha->sas_addr = &pm8001_ha->sas_addr[0]; 611 sha->num_phys = chip_info->n_phy; 612 sha->core.shost = shost; 613 } 614 615 /** 616 * pm8001_init_sas_add - initialize sas address 617 * @chip_info: our ha struct. 618 * 619 * Currently we just set the fixed SAS address to our HBA,for manufacture, 620 * it should read from the EEPROM 621 */ 622 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha) 623 { 624 u8 i, j; 625 u8 sas_add[8]; 626 #ifdef PM8001_READ_VPD 627 /* For new SPC controllers WWN is stored in flash vpd 628 * For SPC/SPCve controllers WWN is stored in EEPROM 629 * For Older SPC WWN is stored in NVMD 630 */ 631 DECLARE_COMPLETION_ONSTACK(completion); 632 struct pm8001_ioctl_payload payload; 633 u16 deviceid; 634 int rc; 635 636 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid); 637 pm8001_ha->nvmd_completion = &completion; 638 639 if (pm8001_ha->chip_id == chip_8001) { 640 if (deviceid == 0x8081 || deviceid == 0x0042) { 641 payload.minor_function = 4; 642 payload.rd_length = 4096; 643 } else { 644 payload.minor_function = 0; 645 payload.rd_length = 128; 646 } 647 } else if ((pm8001_ha->chip_id == chip_8070 || 648 pm8001_ha->chip_id == chip_8072) && 649 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) { 650 payload.minor_function = 4; 651 payload.rd_length = 4096; 652 } else { 653 payload.minor_function = 1; 654 payload.rd_length = 4096; 655 } 656 payload.offset = 0; 657 payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL); 658 if (!payload.func_specific) { 659 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("mem alloc fail\n")); 660 return; 661 } 662 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload); 663 if (rc) { 664 kfree(payload.func_specific); 665 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n")); 666 return; 667 } 668 wait_for_completion(&completion); 669 670 for (i = 0, j = 0; i <= 7; i++, j++) { 671 if (pm8001_ha->chip_id == chip_8001) { 672 if (deviceid == 0x8081) 673 pm8001_ha->sas_addr[j] = 674 payload.func_specific[0x704 + i]; 675 else if (deviceid == 0x0042) 676 pm8001_ha->sas_addr[j] = 677 payload.func_specific[0x010 + i]; 678 } else if ((pm8001_ha->chip_id == chip_8070 || 679 pm8001_ha->chip_id == chip_8072) && 680 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) { 681 pm8001_ha->sas_addr[j] = 682 payload.func_specific[0x010 + i]; 683 } else 684 pm8001_ha->sas_addr[j] = 685 payload.func_specific[0x804 + i]; 686 } 687 memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE); 688 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 689 if (i && ((i % 4) == 0)) 690 sas_add[7] = sas_add[7] + 4; 691 memcpy(&pm8001_ha->phy[i].dev_sas_addr, 692 sas_add, SAS_ADDR_SIZE); 693 PM8001_INIT_DBG(pm8001_ha, 694 pm8001_printk("phy %d sas_addr = %016llx\n", i, 695 pm8001_ha->phy[i].dev_sas_addr)); 696 } 697 kfree(payload.func_specific); 698 #else 699 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 700 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL; 701 pm8001_ha->phy[i].dev_sas_addr = 702 cpu_to_be64((u64) 703 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr)); 704 } 705 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr, 706 SAS_ADDR_SIZE); 707 #endif 708 } 709 710 /* 711 * pm8001_get_phy_settings_info : Read phy setting values. 712 * @pm8001_ha : our hba. 713 */ 714 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha) 715 { 716 717 #ifdef PM8001_READ_VPD 718 /*OPTION ROM FLASH read for the SPC cards */ 719 DECLARE_COMPLETION_ONSTACK(completion); 720 struct pm8001_ioctl_payload payload; 721 int rc; 722 723 pm8001_ha->nvmd_completion = &completion; 724 /* SAS ADDRESS read from flash / EEPROM */ 725 payload.minor_function = 6; 726 payload.offset = 0; 727 payload.rd_length = 4096; 728 payload.func_specific = kzalloc(4096, GFP_KERNEL); 729 if (!payload.func_specific) 730 return -ENOMEM; 731 /* Read phy setting values from flash */ 732 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload); 733 if (rc) { 734 kfree(payload.func_specific); 735 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n")); 736 return -ENOMEM; 737 } 738 wait_for_completion(&completion); 739 pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific); 740 kfree(payload.func_specific); 741 #endif 742 return 0; 743 } 744 745 struct pm8001_mpi3_phy_pg_trx_config { 746 u32 LaneLosCfg; 747 u32 LanePgaCfg1; 748 u32 LanePisoCfg1; 749 u32 LanePisoCfg2; 750 u32 LanePisoCfg3; 751 u32 LanePisoCfg4; 752 u32 LanePisoCfg5; 753 u32 LanePisoCfg6; 754 u32 LaneBctCtrl; 755 }; 756 757 /** 758 * pm8001_get_internal_phy_settings : Retrieves the internal PHY settings 759 * @pm8001_ha : our adapter 760 * @phycfg : PHY config page to populate 761 */ 762 static 763 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha, 764 struct pm8001_mpi3_phy_pg_trx_config *phycfg) 765 { 766 phycfg->LaneLosCfg = 0x00000132; 767 phycfg->LanePgaCfg1 = 0x00203949; 768 phycfg->LanePisoCfg1 = 0x000000FF; 769 phycfg->LanePisoCfg2 = 0xFF000001; 770 phycfg->LanePisoCfg3 = 0xE7011300; 771 phycfg->LanePisoCfg4 = 0x631C40C0; 772 phycfg->LanePisoCfg5 = 0xF8102036; 773 phycfg->LanePisoCfg6 = 0xF74A1000; 774 phycfg->LaneBctCtrl = 0x00FB33F8; 775 } 776 777 /** 778 * pm8001_get_external_phy_settings : Retrieves the external PHY settings 779 * @pm8001_ha : our adapter 780 * @phycfg : PHY config page to populate 781 */ 782 static 783 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha, 784 struct pm8001_mpi3_phy_pg_trx_config *phycfg) 785 { 786 phycfg->LaneLosCfg = 0x00000132; 787 phycfg->LanePgaCfg1 = 0x00203949; 788 phycfg->LanePisoCfg1 = 0x000000FF; 789 phycfg->LanePisoCfg2 = 0xFF000001; 790 phycfg->LanePisoCfg3 = 0xE7011300; 791 phycfg->LanePisoCfg4 = 0x63349140; 792 phycfg->LanePisoCfg5 = 0xF8102036; 793 phycfg->LanePisoCfg6 = 0xF80D9300; 794 phycfg->LaneBctCtrl = 0x00FB33F8; 795 } 796 797 /** 798 * pm8001_get_phy_mask : Retrieves the mask that denotes if a PHY is int/ext 799 * @pm8001_ha : our adapter 800 * @phymask : The PHY mask 801 */ 802 static 803 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask) 804 { 805 switch (pm8001_ha->pdev->subsystem_device) { 806 case 0x0070: /* H1280 - 8 external 0 internal */ 807 case 0x0072: /* H12F0 - 16 external 0 internal */ 808 *phymask = 0x0000; 809 break; 810 811 case 0x0071: /* H1208 - 0 external 8 internal */ 812 case 0x0073: /* H120F - 0 external 16 internal */ 813 *phymask = 0xFFFF; 814 break; 815 816 case 0x0080: /* H1244 - 4 external 4 internal */ 817 *phymask = 0x00F0; 818 break; 819 820 case 0x0081: /* H1248 - 4 external 8 internal */ 821 *phymask = 0x0FF0; 822 break; 823 824 case 0x0082: /* H1288 - 8 external 8 internal */ 825 *phymask = 0xFF00; 826 break; 827 828 default: 829 PM8001_INIT_DBG(pm8001_ha, 830 pm8001_printk("Unknown subsystem device=0x%.04x", 831 pm8001_ha->pdev->subsystem_device)); 832 } 833 } 834 835 /** 836 * pm8001_set_phy_settings_ven_117c_12Gb : Configure ATTO 12Gb PHY settings 837 * @pm8001_ha : our adapter 838 */ 839 static 840 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha) 841 { 842 struct pm8001_mpi3_phy_pg_trx_config phycfg_int; 843 struct pm8001_mpi3_phy_pg_trx_config phycfg_ext; 844 int phymask = 0; 845 int i = 0; 846 847 memset(&phycfg_int, 0, sizeof(phycfg_int)); 848 memset(&phycfg_ext, 0, sizeof(phycfg_ext)); 849 850 pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int); 851 pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext); 852 pm8001_get_phy_mask(pm8001_ha, &phymask); 853 854 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 855 if (phymask & (1 << i)) {/* Internal PHY */ 856 pm8001_set_phy_profile_single(pm8001_ha, i, 857 sizeof(phycfg_int) / sizeof(u32), 858 (u32 *)&phycfg_int); 859 860 } else { /* External PHY */ 861 pm8001_set_phy_profile_single(pm8001_ha, i, 862 sizeof(phycfg_ext) / sizeof(u32), 863 (u32 *)&phycfg_ext); 864 } 865 } 866 867 return 0; 868 } 869 870 /** 871 * pm8001_configure_phy_settings : Configures PHY settings based on vendor ID. 872 * @pm8001_ha : our hba. 873 */ 874 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha) 875 { 876 switch (pm8001_ha->pdev->subsystem_vendor) { 877 case PCI_VENDOR_ID_ATTO: 878 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */ 879 return 0; 880 else 881 return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha); 882 883 case PCI_VENDOR_ID_ADAPTEC2: 884 case 0: 885 return 0; 886 887 default: 888 return pm8001_get_phy_settings_info(pm8001_ha); 889 } 890 } 891 892 #ifdef PM8001_USE_MSIX 893 /** 894 * pm8001_setup_msix - enable MSI-X interrupt 895 * @chip_info: our ha struct. 896 * @irq_handler: irq_handler 897 */ 898 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha) 899 { 900 u32 number_of_intr; 901 int rc; 902 903 /* SPCv controllers supports 64 msi-x */ 904 if (pm8001_ha->chip_id == chip_8001) { 905 number_of_intr = 1; 906 } else { 907 number_of_intr = PM8001_MAX_MSIX_VEC; 908 } 909 910 rc = pci_alloc_irq_vectors(pm8001_ha->pdev, number_of_intr, 911 number_of_intr, PCI_IRQ_MSIX); 912 number_of_intr = rc; 913 if (rc < 0) 914 return rc; 915 pm8001_ha->number_of_intr = number_of_intr; 916 917 PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 918 "pci_alloc_irq_vectors request ret:%d no of intr %d\n", 919 rc, pm8001_ha->number_of_intr)); 920 return 0; 921 } 922 923 static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha) 924 { 925 u32 i = 0, j = 0; 926 int flag = 0, rc = 0; 927 928 if (pm8001_ha->chip_id != chip_8001) 929 flag &= ~IRQF_SHARED; 930 931 PM8001_INIT_DBG(pm8001_ha, 932 pm8001_printk("pci_enable_msix request number of intr %d\n", 933 pm8001_ha->number_of_intr)); 934 935 for (i = 0; i < pm8001_ha->number_of_intr; i++) { 936 snprintf(pm8001_ha->intr_drvname[i], 937 sizeof(pm8001_ha->intr_drvname[0]), 938 "%s-%d", pm8001_ha->name, i); 939 pm8001_ha->irq_vector[i].irq_id = i; 940 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha; 941 942 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i), 943 pm8001_interrupt_handler_msix, flag, 944 pm8001_ha->intr_drvname[i], 945 &(pm8001_ha->irq_vector[i])); 946 if (rc) { 947 for (j = 0; j < i; j++) { 948 free_irq(pci_irq_vector(pm8001_ha->pdev, i), 949 &(pm8001_ha->irq_vector[i])); 950 } 951 pci_free_irq_vectors(pm8001_ha->pdev); 952 break; 953 } 954 } 955 956 return rc; 957 } 958 #endif 959 960 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha) 961 { 962 struct pci_dev *pdev; 963 964 pdev = pm8001_ha->pdev; 965 966 #ifdef PM8001_USE_MSIX 967 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX)) 968 return pm8001_setup_msix(pm8001_ha); 969 PM8001_INIT_DBG(pm8001_ha, 970 pm8001_printk("MSIX not supported!!!\n")); 971 #endif 972 return 0; 973 } 974 975 /** 976 * pm8001_request_irq - register interrupt 977 * @chip_info: our ha struct. 978 */ 979 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha) 980 { 981 struct pci_dev *pdev; 982 int rc; 983 984 pdev = pm8001_ha->pdev; 985 986 #ifdef PM8001_USE_MSIX 987 if (pdev->msix_cap && pci_msi_enabled()) 988 return pm8001_request_msix(pm8001_ha); 989 else { 990 PM8001_INIT_DBG(pm8001_ha, 991 pm8001_printk("MSIX not supported!!!\n")); 992 goto intx; 993 } 994 #endif 995 996 intx: 997 /* initialize the INT-X interrupt */ 998 pm8001_ha->irq_vector[0].irq_id = 0; 999 pm8001_ha->irq_vector[0].drv_inst = pm8001_ha; 1000 rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED, 1001 pm8001_ha->name, SHOST_TO_SAS_HA(pm8001_ha->shost)); 1002 return rc; 1003 } 1004 1005 /** 1006 * pm8001_pci_probe - probe supported device 1007 * @pdev: pci device which kernel has been prepared for. 1008 * @ent: pci device id 1009 * 1010 * This function is the main initialization function, when register a new 1011 * pci driver it is invoked, all struct an hardware initilization should be done 1012 * here, also, register interrupt 1013 */ 1014 static int pm8001_pci_probe(struct pci_dev *pdev, 1015 const struct pci_device_id *ent) 1016 { 1017 unsigned int rc; 1018 u32 pci_reg; 1019 u8 i = 0; 1020 struct pm8001_hba_info *pm8001_ha; 1021 struct Scsi_Host *shost = NULL; 1022 const struct pm8001_chip_info *chip; 1023 struct sas_ha_struct *sha; 1024 1025 dev_printk(KERN_INFO, &pdev->dev, 1026 "pm80xx: driver version %s\n", DRV_VERSION); 1027 rc = pci_enable_device(pdev); 1028 if (rc) 1029 goto err_out_enable; 1030 pci_set_master(pdev); 1031 /* 1032 * Enable pci slot busmaster by setting pci command register. 1033 * This is required by FW for Cyclone card. 1034 */ 1035 1036 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg); 1037 pci_reg |= 0x157; 1038 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg); 1039 rc = pci_request_regions(pdev, DRV_NAME); 1040 if (rc) 1041 goto err_out_disable; 1042 rc = pci_go_44(pdev); 1043 if (rc) 1044 goto err_out_regions; 1045 1046 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *)); 1047 if (!shost) { 1048 rc = -ENOMEM; 1049 goto err_out_regions; 1050 } 1051 chip = &pm8001_chips[ent->driver_data]; 1052 sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL); 1053 if (!sha) { 1054 rc = -ENOMEM; 1055 goto err_out_free_host; 1056 } 1057 SHOST_TO_SAS_HA(shost) = sha; 1058 1059 rc = pm8001_prep_sas_ha_init(shost, chip); 1060 if (rc) { 1061 rc = -ENOMEM; 1062 goto err_out_free; 1063 } 1064 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost)); 1065 /* ent->driver variable is used to differentiate between controllers */ 1066 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost); 1067 if (!pm8001_ha) { 1068 rc = -ENOMEM; 1069 goto err_out_free; 1070 } 1071 /* Setup Interrupt */ 1072 rc = pm8001_setup_irq(pm8001_ha); 1073 if (rc) { 1074 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 1075 "pm8001_setup_irq failed [ret: %d]\n", rc)); 1076 goto err_out_shost; 1077 } 1078 1079 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1080 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); 1081 if (rc) { 1082 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 1083 "chip_init failed [ret: %d]\n", rc)); 1084 goto err_out_ha_free; 1085 } 1086 1087 rc = scsi_add_host(shost, &pdev->dev); 1088 if (rc) 1089 goto err_out_ha_free; 1090 /* Request Interrupt */ 1091 rc = pm8001_request_irq(pm8001_ha); 1092 if (rc) { 1093 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 1094 "pm8001_request_irq failed [ret: %d]\n", rc)); 1095 goto err_out_shost; 1096 } 1097 1098 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0); 1099 if (pm8001_ha->chip_id != chip_8001) { 1100 for (i = 1; i < pm8001_ha->number_of_intr; i++) 1101 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i); 1102 /* setup thermal configuration. */ 1103 pm80xx_set_thermal_config(pm8001_ha); 1104 } 1105 1106 pm8001_init_sas_add(pm8001_ha); 1107 /* phy setting support for motherboard controller */ 1108 if (pm8001_configure_phy_settings(pm8001_ha)) 1109 goto err_out_shost; 1110 1111 pm8001_post_sas_ha_init(shost, chip); 1112 rc = sas_register_ha(SHOST_TO_SAS_HA(shost)); 1113 if (rc) { 1114 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 1115 "sas_register_ha failed [ret: %d]\n", rc)); 1116 goto err_out_shost; 1117 } 1118 list_add_tail(&pm8001_ha->list, &hba_list); 1119 scsi_scan_host(pm8001_ha->shost); 1120 pm8001_ha->flags = PM8001F_RUN_TIME; 1121 return 0; 1122 1123 err_out_shost: 1124 scsi_remove_host(pm8001_ha->shost); 1125 err_out_ha_free: 1126 pm8001_free(pm8001_ha); 1127 err_out_free: 1128 kfree(sha); 1129 err_out_free_host: 1130 scsi_host_put(shost); 1131 err_out_regions: 1132 pci_release_regions(pdev); 1133 err_out_disable: 1134 pci_disable_device(pdev); 1135 err_out_enable: 1136 return rc; 1137 } 1138 1139 static void pm8001_pci_remove(struct pci_dev *pdev) 1140 { 1141 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1142 struct pm8001_hba_info *pm8001_ha; 1143 int i, j; 1144 pm8001_ha = sha->lldd_ha; 1145 sas_unregister_ha(sha); 1146 sas_remove_host(pm8001_ha->shost); 1147 list_del(&pm8001_ha->list); 1148 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1149 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1150 1151 #ifdef PM8001_USE_MSIX 1152 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1153 synchronize_irq(pci_irq_vector(pdev, i)); 1154 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1155 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]); 1156 pci_free_irq_vectors(pdev); 1157 #else 1158 free_irq(pm8001_ha->irq, sha); 1159 #endif 1160 #ifdef PM8001_USE_TASKLET 1161 /* For non-msix and msix interrupts */ 1162 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1163 (pm8001_ha->chip_id == chip_8001)) 1164 tasklet_kill(&pm8001_ha->tasklet[0]); 1165 else 1166 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1167 tasklet_kill(&pm8001_ha->tasklet[j]); 1168 #endif 1169 scsi_host_put(pm8001_ha->shost); 1170 pm8001_free(pm8001_ha); 1171 kfree(sha->sas_phy); 1172 kfree(sha->sas_port); 1173 kfree(sha); 1174 pci_release_regions(pdev); 1175 pci_disable_device(pdev); 1176 } 1177 1178 /** 1179 * pm8001_pci_suspend - power management suspend main entry point 1180 * @pdev: PCI device struct 1181 * @state: PM state change to (usually PCI_D3) 1182 * 1183 * Returns 0 success, anything else error. 1184 */ 1185 static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1186 { 1187 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1188 struct pm8001_hba_info *pm8001_ha; 1189 int i, j; 1190 u32 device_state; 1191 pm8001_ha = sha->lldd_ha; 1192 sas_suspend_ha(sha); 1193 flush_workqueue(pm8001_wq); 1194 scsi_block_requests(pm8001_ha->shost); 1195 if (!pdev->pm_cap) { 1196 dev_err(&pdev->dev, " PCI PM not supported\n"); 1197 return -ENODEV; 1198 } 1199 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1200 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1201 #ifdef PM8001_USE_MSIX 1202 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1203 synchronize_irq(pci_irq_vector(pdev, i)); 1204 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1205 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]); 1206 pci_free_irq_vectors(pdev); 1207 #else 1208 free_irq(pm8001_ha->irq, sha); 1209 #endif 1210 #ifdef PM8001_USE_TASKLET 1211 /* For non-msix and msix interrupts */ 1212 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1213 (pm8001_ha->chip_id == chip_8001)) 1214 tasklet_kill(&pm8001_ha->tasklet[0]); 1215 else 1216 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1217 tasklet_kill(&pm8001_ha->tasklet[j]); 1218 #endif 1219 device_state = pci_choose_state(pdev, state); 1220 pm8001_printk("pdev=0x%p, slot=%s, entering " 1221 "operating state [D%d]\n", pdev, 1222 pm8001_ha->name, device_state); 1223 pci_save_state(pdev); 1224 pci_disable_device(pdev); 1225 pci_set_power_state(pdev, device_state); 1226 return 0; 1227 } 1228 1229 /** 1230 * pm8001_pci_resume - power management resume main entry point 1231 * @pdev: PCI device struct 1232 * 1233 * Returns 0 success, anything else error. 1234 */ 1235 static int pm8001_pci_resume(struct pci_dev *pdev) 1236 { 1237 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1238 struct pm8001_hba_info *pm8001_ha; 1239 int rc; 1240 u8 i = 0, j; 1241 u32 device_state; 1242 DECLARE_COMPLETION_ONSTACK(completion); 1243 pm8001_ha = sha->lldd_ha; 1244 device_state = pdev->current_state; 1245 1246 pm8001_printk("pdev=0x%p, slot=%s, resuming from previous " 1247 "operating state [D%d]\n", pdev, pm8001_ha->name, device_state); 1248 1249 pci_set_power_state(pdev, PCI_D0); 1250 pci_enable_wake(pdev, PCI_D0, 0); 1251 pci_restore_state(pdev); 1252 rc = pci_enable_device(pdev); 1253 if (rc) { 1254 pm8001_printk("slot=%s Enable device failed during resume\n", 1255 pm8001_ha->name); 1256 goto err_out_enable; 1257 } 1258 1259 pci_set_master(pdev); 1260 rc = pci_go_44(pdev); 1261 if (rc) 1262 goto err_out_disable; 1263 sas_prep_resume_ha(sha); 1264 /* chip soft rst only for spc */ 1265 if (pm8001_ha->chip_id == chip_8001) { 1266 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1267 PM8001_INIT_DBG(pm8001_ha, 1268 pm8001_printk("chip soft reset successful\n")); 1269 } 1270 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); 1271 if (rc) 1272 goto err_out_disable; 1273 1274 /* disable all the interrupt bits */ 1275 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1276 1277 rc = pm8001_request_irq(pm8001_ha); 1278 if (rc) 1279 goto err_out_disable; 1280 #ifdef PM8001_USE_TASKLET 1281 /* Tasklet for non msi-x interrupt handler */ 1282 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1283 (pm8001_ha->chip_id == chip_8001)) 1284 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet, 1285 (unsigned long)&(pm8001_ha->irq_vector[0])); 1286 else 1287 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1288 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet, 1289 (unsigned long)&(pm8001_ha->irq_vector[j])); 1290 #endif 1291 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0); 1292 if (pm8001_ha->chip_id != chip_8001) { 1293 for (i = 1; i < pm8001_ha->number_of_intr; i++) 1294 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i); 1295 } 1296 1297 /* Chip documentation for the 8070 and 8072 SPCv */ 1298 /* states that a 500ms minimum delay is required */ 1299 /* before issuing commands. Otherwise, the firmware */ 1300 /* will enter an unrecoverable state. */ 1301 1302 if (pm8001_ha->chip_id == chip_8070 || 1303 pm8001_ha->chip_id == chip_8072) { 1304 mdelay(500); 1305 } 1306 1307 /* Spin up the PHYs */ 1308 1309 pm8001_ha->flags = PM8001F_RUN_TIME; 1310 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 1311 pm8001_ha->phy[i].enable_completion = &completion; 1312 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i); 1313 wait_for_completion(&completion); 1314 } 1315 sas_resume_ha(sha); 1316 return 0; 1317 1318 err_out_disable: 1319 scsi_remove_host(pm8001_ha->shost); 1320 pci_disable_device(pdev); 1321 err_out_enable: 1322 return rc; 1323 } 1324 1325 /* update of pci device, vendor id and driver data with 1326 * unique value for each of the controller 1327 */ 1328 static struct pci_device_id pm8001_pci_table[] = { 1329 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 }, 1330 { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 }, 1331 { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 }, 1332 { PCI_VDEVICE(ATTO, 0x0042), chip_8001 }, 1333 /* Support for SPC/SPCv/SPCve controllers */ 1334 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 }, 1335 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 }, 1336 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 }, 1337 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 }, 1338 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 }, 1339 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 }, 1340 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 }, 1341 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 }, 1342 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 }, 1343 { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 }, 1344 { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 }, 1345 { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 }, 1346 { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 }, 1347 { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 }, 1348 { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 }, 1349 { PCI_VENDOR_ID_ADAPTEC2, 0x8081, 1350 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 }, 1351 { PCI_VENDOR_ID_ADAPTEC2, 0x8081, 1352 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 }, 1353 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1354 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 }, 1355 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1356 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 }, 1357 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1358 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 }, 1359 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1360 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 }, 1361 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1362 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 }, 1363 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1364 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 }, 1365 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1366 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 }, 1367 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1368 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 }, 1369 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1370 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 }, 1371 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1372 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 }, 1373 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1374 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 }, 1375 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1376 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 }, 1377 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1378 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 }, 1379 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1380 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 }, 1381 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1382 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 }, 1383 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1384 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 }, 1385 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1386 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 }, 1387 { PCI_VENDOR_ID_ATTO, 0x8070, 1388 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 }, 1389 { PCI_VENDOR_ID_ATTO, 0x8070, 1390 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 }, 1391 { PCI_VENDOR_ID_ATTO, 0x8072, 1392 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 }, 1393 { PCI_VENDOR_ID_ATTO, 0x8072, 1394 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 }, 1395 { PCI_VENDOR_ID_ATTO, 0x8070, 1396 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 }, 1397 { PCI_VENDOR_ID_ATTO, 0x8072, 1398 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 }, 1399 { PCI_VENDOR_ID_ATTO, 0x8072, 1400 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 }, 1401 {} /* terminate list */ 1402 }; 1403 1404 static struct pci_driver pm8001_pci_driver = { 1405 .name = DRV_NAME, 1406 .id_table = pm8001_pci_table, 1407 .probe = pm8001_pci_probe, 1408 .remove = pm8001_pci_remove, 1409 .suspend = pm8001_pci_suspend, 1410 .resume = pm8001_pci_resume, 1411 }; 1412 1413 /** 1414 * pm8001_init - initialize scsi transport template 1415 */ 1416 static int __init pm8001_init(void) 1417 { 1418 int rc = -ENOMEM; 1419 1420 pm8001_wq = alloc_workqueue("pm80xx", 0, 0); 1421 if (!pm8001_wq) 1422 goto err; 1423 1424 pm8001_id = 0; 1425 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops); 1426 if (!pm8001_stt) 1427 goto err_wq; 1428 rc = pci_register_driver(&pm8001_pci_driver); 1429 if (rc) 1430 goto err_tp; 1431 return 0; 1432 1433 err_tp: 1434 sas_release_transport(pm8001_stt); 1435 err_wq: 1436 destroy_workqueue(pm8001_wq); 1437 err: 1438 return rc; 1439 } 1440 1441 static void __exit pm8001_exit(void) 1442 { 1443 pci_unregister_driver(&pm8001_pci_driver); 1444 sas_release_transport(pm8001_stt); 1445 destroy_workqueue(pm8001_wq); 1446 } 1447 1448 module_init(pm8001_init); 1449 module_exit(pm8001_exit); 1450 1451 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>"); 1452 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>"); 1453 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>"); 1454 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>"); 1455 MODULE_DESCRIPTION( 1456 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 " 1457 "SAS/SATA controller driver"); 1458 MODULE_VERSION(DRV_VERSION); 1459 MODULE_LICENSE("GPL"); 1460 MODULE_DEVICE_TABLE(pci, pm8001_pci_table); 1461 1462