1 /*
2  * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
3  *
4  * Copyright (c) 2008-2009 USI Co., Ltd.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions, and the following disclaimer,
12  *    without modification.
13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14  *    substantially similar to the "NO WARRANTY" disclaimer below
15  *    ("Disclaimer") and any redistribution must be conditioned upon
16  *    including a substantially similar Disclaimer requirement for further
17  *    binary redistribution.
18  * 3. Neither the names of the above-listed copyright holders nor the names
19  *    of any contributors may be used to endorse or promote products derived
20  *    from this software without specific prior written permission.
21  *
22  * Alternatively, this software may be distributed under the terms of the
23  * GNU General Public License ("GPL") version 2 as published by the Free
24  * Software Foundation.
25  *
26  * NO WARRANTY
27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37  * POSSIBILITY OF SUCH DAMAGES.
38  *
39  */
40 
41 #include <linux/slab.h>
42 #include "pm8001_sas.h"
43 #include "pm8001_chips.h"
44 #include "pm80xx_hwi.h"
45 
46 static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING |
47 				PM8001_EVENT_LOGGING | PM8001_INIT_LOGGING;
48 module_param(logging_level, ulong, 0644);
49 MODULE_PARM_DESC(logging_level, " bits for enabling logging info.");
50 
51 static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120;
52 module_param(link_rate, ulong, 0644);
53 MODULE_PARM_DESC(link_rate, "Enable link rate.\n"
54 		" 1: Link rate 1.5G\n"
55 		" 2: Link rate 3.0G\n"
56 		" 4: Link rate 6.0G\n"
57 		" 8: Link rate 12.0G\n");
58 
59 static struct scsi_transport_template *pm8001_stt;
60 static int pm8001_init_ccb_tag(struct pm8001_hba_info *);
61 
62 /*
63  * chip info structure to identify chip key functionality as
64  * encryption available/not, no of ports, hw specific function ref
65  */
66 static const struct pm8001_chip_info pm8001_chips[] = {
67 	[chip_8001] = {0,  8, &pm8001_8001_dispatch,},
68 	[chip_8008] = {0,  8, &pm8001_80xx_dispatch,},
69 	[chip_8009] = {1,  8, &pm8001_80xx_dispatch,},
70 	[chip_8018] = {0,  16, &pm8001_80xx_dispatch,},
71 	[chip_8019] = {1,  16, &pm8001_80xx_dispatch,},
72 	[chip_8074] = {0,  8, &pm8001_80xx_dispatch,},
73 	[chip_8076] = {0,  16, &pm8001_80xx_dispatch,},
74 	[chip_8077] = {0,  16, &pm8001_80xx_dispatch,},
75 	[chip_8006] = {0,  16, &pm8001_80xx_dispatch,},
76 	[chip_8070] = {0,  8, &pm8001_80xx_dispatch,},
77 	[chip_8072] = {0,  16, &pm8001_80xx_dispatch,},
78 };
79 static int pm8001_id;
80 
81 LIST_HEAD(hba_list);
82 
83 struct workqueue_struct *pm8001_wq;
84 
85 static void pm8001_map_queues(struct Scsi_Host *shost)
86 {
87 	struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
88 	struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
89 	struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
90 
91 	if (pm8001_ha->number_of_intr > 1)
92 		blk_mq_pci_map_queues(qmap, pm8001_ha->pdev, 1);
93 
94 	return blk_mq_map_queues(qmap);
95 }
96 
97 /*
98  * The main structure which LLDD must register for scsi core.
99  */
100 static const struct scsi_host_template pm8001_sht = {
101 	.module			= THIS_MODULE,
102 	.name			= DRV_NAME,
103 	.proc_name		= DRV_NAME,
104 	.queuecommand		= sas_queuecommand,
105 	.dma_need_drain		= ata_scsi_dma_need_drain,
106 	.target_alloc		= sas_target_alloc,
107 	.slave_configure	= sas_slave_configure,
108 	.scan_finished		= pm8001_scan_finished,
109 	.scan_start		= pm8001_scan_start,
110 	.change_queue_depth	= sas_change_queue_depth,
111 	.bios_param		= sas_bios_param,
112 	.can_queue		= 1,
113 	.this_id		= -1,
114 	.sg_tablesize		= PM8001_MAX_DMA_SG,
115 	.max_sectors		= SCSI_DEFAULT_MAX_SECTORS,
116 	.eh_device_reset_handler = sas_eh_device_reset_handler,
117 	.eh_target_reset_handler = sas_eh_target_reset_handler,
118 	.slave_alloc		= sas_slave_alloc,
119 	.target_destroy		= sas_target_destroy,
120 	.ioctl			= sas_ioctl,
121 #ifdef CONFIG_COMPAT
122 	.compat_ioctl		= sas_ioctl,
123 #endif
124 	.shost_groups		= pm8001_host_groups,
125 	.track_queue_depth	= 1,
126 	.cmd_per_lun		= 32,
127 	.map_queues		= pm8001_map_queues,
128 };
129 
130 /*
131  * Sas layer call this function to execute specific task.
132  */
133 static struct sas_domain_function_template pm8001_transport_ops = {
134 	.lldd_dev_found		= pm8001_dev_found,
135 	.lldd_dev_gone		= pm8001_dev_gone,
136 
137 	.lldd_execute_task	= pm8001_queue_command,
138 	.lldd_control_phy	= pm8001_phy_control,
139 
140 	.lldd_abort_task	= pm8001_abort_task,
141 	.lldd_abort_task_set	= sas_abort_task_set,
142 	.lldd_clear_task_set	= pm8001_clear_task_set,
143 	.lldd_I_T_nexus_reset   = pm8001_I_T_nexus_reset,
144 	.lldd_lu_reset		= pm8001_lu_reset,
145 	.lldd_query_task	= pm8001_query_task,
146 	.lldd_port_formed	= pm8001_port_formed,
147 	.lldd_tmf_exec_complete = pm8001_setds_completion,
148 	.lldd_tmf_aborted	= pm8001_tmf_aborted,
149 };
150 
151 /**
152  * pm8001_phy_init - initiate our adapter phys
153  * @pm8001_ha: our hba structure.
154  * @phy_id: phy id.
155  */
156 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
157 {
158 	struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
159 	struct asd_sas_phy *sas_phy = &phy->sas_phy;
160 	phy->phy_state = PHY_LINK_DISABLE;
161 	phy->pm8001_ha = pm8001_ha;
162 	phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
163 	phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
164 	sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
165 	sas_phy->iproto = SAS_PROTOCOL_ALL;
166 	sas_phy->tproto = 0;
167 	sas_phy->role = PHY_ROLE_INITIATOR;
168 	sas_phy->oob_mode = OOB_NOT_CONNECTED;
169 	sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
170 	sas_phy->id = phy_id;
171 	sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr;
172 	sas_phy->frame_rcvd = &phy->frame_rcvd[0];
173 	sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
174 	sas_phy->lldd_phy = phy;
175 }
176 
177 /**
178  * pm8001_free - free hba
179  * @pm8001_ha:	our hba structure.
180  */
181 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
182 {
183 	int i;
184 
185 	if (!pm8001_ha)
186 		return;
187 
188 	for (i = 0; i < USI_MAX_MEMCNT; i++) {
189 		if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
190 			dma_free_coherent(&pm8001_ha->pdev->dev,
191 				(pm8001_ha->memoryMap.region[i].total_len +
192 				pm8001_ha->memoryMap.region[i].alignment),
193 				pm8001_ha->memoryMap.region[i].virt_ptr,
194 				pm8001_ha->memoryMap.region[i].phys_addr);
195 			}
196 	}
197 	PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
198 	flush_workqueue(pm8001_wq);
199 	bitmap_free(pm8001_ha->rsvd_tags);
200 	kfree(pm8001_ha);
201 }
202 
203 #ifdef PM8001_USE_TASKLET
204 
205 /**
206  * pm8001_tasklet() - tasklet for 64 msi-x interrupt handler
207  * @opaque: the passed general host adapter struct
208  * Note: pm8001_tasklet is common for pm8001 & pm80xx
209  */
210 static void pm8001_tasklet(unsigned long opaque)
211 {
212 	struct pm8001_hba_info *pm8001_ha;
213 	struct isr_param *irq_vector;
214 
215 	irq_vector = (struct isr_param *)opaque;
216 	pm8001_ha = irq_vector->drv_inst;
217 	if (unlikely(!pm8001_ha))
218 		BUG_ON(1);
219 	PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
220 }
221 #endif
222 
223 /**
224  * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
225  * It obtains the vector number and calls the equivalent bottom
226  * half or services directly.
227  * @irq: interrupt number
228  * @opaque: the passed outbound queue/vector. Host structure is
229  * retrieved from the same.
230  */
231 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
232 {
233 	struct isr_param *irq_vector;
234 	struct pm8001_hba_info *pm8001_ha;
235 	irqreturn_t ret = IRQ_HANDLED;
236 	irq_vector = (struct isr_param *)opaque;
237 	pm8001_ha = irq_vector->drv_inst;
238 
239 	if (unlikely(!pm8001_ha))
240 		return IRQ_NONE;
241 	if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
242 		return IRQ_NONE;
243 #ifdef PM8001_USE_TASKLET
244 	tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
245 #else
246 	ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
247 #endif
248 	return ret;
249 }
250 
251 /**
252  * pm8001_interrupt_handler_intx - main INTx interrupt handler.
253  * @irq: interrupt number
254  * @dev_id: sas_ha structure. The HBA is retrieved from sas_ha structure.
255  */
256 
257 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
258 {
259 	struct pm8001_hba_info *pm8001_ha;
260 	irqreturn_t ret = IRQ_HANDLED;
261 	struct sas_ha_struct *sha = dev_id;
262 	pm8001_ha = sha->lldd_ha;
263 	if (unlikely(!pm8001_ha))
264 		return IRQ_NONE;
265 	if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
266 		return IRQ_NONE;
267 
268 #ifdef PM8001_USE_TASKLET
269 	tasklet_schedule(&pm8001_ha->tasklet[0]);
270 #else
271 	ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
272 #endif
273 	return ret;
274 }
275 
276 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha);
277 
278 /**
279  * pm8001_alloc - initiate our hba structure and 6 DMAs area.
280  * @pm8001_ha: our hba structure.
281  * @ent: PCI device ID structure to match on
282  */
283 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
284 			const struct pci_device_id *ent)
285 {
286 	int i, count = 0, rc = 0;
287 	u32 ci_offset, ib_offset, ob_offset, pi_offset;
288 	struct inbound_queue_table *ibq;
289 	struct outbound_queue_table *obq;
290 
291 	spin_lock_init(&pm8001_ha->lock);
292 	spin_lock_init(&pm8001_ha->bitmap_lock);
293 	pm8001_dbg(pm8001_ha, INIT, "pm8001_alloc: PHY:%x\n",
294 		   pm8001_ha->chip->n_phy);
295 
296 	/* Request Interrupt */
297 	rc = pm8001_request_irq(pm8001_ha);
298 	if (rc)
299 		goto err_out;
300 
301 	count = pm8001_ha->max_q_num;
302 	/* Queues are chosen based on the number of cores/msix availability */
303 	ib_offset = pm8001_ha->ib_offset  = USI_MAX_MEMCNT_BASE;
304 	ci_offset = pm8001_ha->ci_offset  = ib_offset + count;
305 	ob_offset = pm8001_ha->ob_offset  = ci_offset + count;
306 	pi_offset = pm8001_ha->pi_offset  = ob_offset + count;
307 	pm8001_ha->max_memcnt = pi_offset + count;
308 
309 	for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
310 		pm8001_phy_init(pm8001_ha, i);
311 		pm8001_ha->port[i].wide_port_phymap = 0;
312 		pm8001_ha->port[i].port_attached = 0;
313 		pm8001_ha->port[i].port_state = 0;
314 		INIT_LIST_HEAD(&pm8001_ha->port[i].list);
315 	}
316 
317 	/* MPI Memory region 1 for AAP Event Log for fw */
318 	pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
319 	pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
320 	pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
321 	pm8001_ha->memoryMap.region[AAP1].alignment = 32;
322 
323 	/* MPI Memory region 2 for IOP Event Log for fw */
324 	pm8001_ha->memoryMap.region[IOP].num_elements = 1;
325 	pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
326 	pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
327 	pm8001_ha->memoryMap.region[IOP].alignment = 32;
328 
329 	for (i = 0; i < count; i++) {
330 		ibq = &pm8001_ha->inbnd_q_tbl[i];
331 		spin_lock_init(&ibq->iq_lock);
332 		/* MPI Memory region 3 for consumer Index of inbound queues */
333 		pm8001_ha->memoryMap.region[ci_offset+i].num_elements = 1;
334 		pm8001_ha->memoryMap.region[ci_offset+i].element_size = 4;
335 		pm8001_ha->memoryMap.region[ci_offset+i].total_len = 4;
336 		pm8001_ha->memoryMap.region[ci_offset+i].alignment = 4;
337 
338 		if ((ent->driver_data) != chip_8001) {
339 			/* MPI Memory region 5 inbound queues */
340 			pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
341 						PM8001_MPI_QUEUE;
342 			pm8001_ha->memoryMap.region[ib_offset+i].element_size
343 								= 128;
344 			pm8001_ha->memoryMap.region[ib_offset+i].total_len =
345 						PM8001_MPI_QUEUE * 128;
346 			pm8001_ha->memoryMap.region[ib_offset+i].alignment
347 								= 128;
348 		} else {
349 			pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
350 						PM8001_MPI_QUEUE;
351 			pm8001_ha->memoryMap.region[ib_offset+i].element_size
352 								= 64;
353 			pm8001_ha->memoryMap.region[ib_offset+i].total_len =
354 						PM8001_MPI_QUEUE * 64;
355 			pm8001_ha->memoryMap.region[ib_offset+i].alignment = 64;
356 		}
357 	}
358 
359 	for (i = 0; i < count; i++) {
360 		obq = &pm8001_ha->outbnd_q_tbl[i];
361 		spin_lock_init(&obq->oq_lock);
362 		/* MPI Memory region 4 for producer Index of outbound queues */
363 		pm8001_ha->memoryMap.region[pi_offset+i].num_elements = 1;
364 		pm8001_ha->memoryMap.region[pi_offset+i].element_size = 4;
365 		pm8001_ha->memoryMap.region[pi_offset+i].total_len = 4;
366 		pm8001_ha->memoryMap.region[pi_offset+i].alignment = 4;
367 
368 		if (ent->driver_data != chip_8001) {
369 			/* MPI Memory region 6 Outbound queues */
370 			pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
371 						PM8001_MPI_QUEUE;
372 			pm8001_ha->memoryMap.region[ob_offset+i].element_size
373 								= 128;
374 			pm8001_ha->memoryMap.region[ob_offset+i].total_len =
375 						PM8001_MPI_QUEUE * 128;
376 			pm8001_ha->memoryMap.region[ob_offset+i].alignment
377 								= 128;
378 		} else {
379 			/* MPI Memory region 6 Outbound queues */
380 			pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
381 						PM8001_MPI_QUEUE;
382 			pm8001_ha->memoryMap.region[ob_offset+i].element_size
383 								= 64;
384 			pm8001_ha->memoryMap.region[ob_offset+i].total_len =
385 						PM8001_MPI_QUEUE * 64;
386 			pm8001_ha->memoryMap.region[ob_offset+i].alignment = 64;
387 		}
388 
389 	}
390 	/* Memory region write DMA*/
391 	pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
392 	pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
393 	pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
394 
395 	/* Memory region for fw flash */
396 	pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
397 
398 	pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
399 	pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
400 	pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
401 	pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
402 	for (i = 0; i < pm8001_ha->max_memcnt; i++) {
403 		struct mpi_mem *region = &pm8001_ha->memoryMap.region[i];
404 
405 		if (pm8001_mem_alloc(pm8001_ha->pdev,
406 				     &region->virt_ptr,
407 				     &region->phys_addr,
408 				     &region->phys_addr_hi,
409 				     &region->phys_addr_lo,
410 				     region->total_len,
411 				     region->alignment) != 0) {
412 			pm8001_dbg(pm8001_ha, FAIL, "Mem%d alloc failed\n", i);
413 			goto err_out;
414 		}
415 	}
416 
417 	/* Memory region for devices*/
418 	pm8001_ha->devices = kzalloc(PM8001_MAX_DEVICES
419 				* sizeof(struct pm8001_device), GFP_KERNEL);
420 	if (!pm8001_ha->devices) {
421 		rc = -ENOMEM;
422 		goto err_out_nodev;
423 	}
424 	for (i = 0; i < PM8001_MAX_DEVICES; i++) {
425 		pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
426 		pm8001_ha->devices[i].id = i;
427 		pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
428 		atomic_set(&pm8001_ha->devices[i].running_req, 0);
429 	}
430 	pm8001_ha->flags = PM8001F_INIT_TIME;
431 	return 0;
432 
433 err_out_nodev:
434 	for (i = 0; i < pm8001_ha->max_memcnt; i++) {
435 		if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
436 			dma_free_coherent(&pm8001_ha->pdev->dev,
437 				(pm8001_ha->memoryMap.region[i].total_len +
438 				pm8001_ha->memoryMap.region[i].alignment),
439 				pm8001_ha->memoryMap.region[i].virt_ptr,
440 				pm8001_ha->memoryMap.region[i].phys_addr);
441 		}
442 	}
443 err_out:
444 	return 1;
445 }
446 
447 /**
448  * pm8001_ioremap - remap the pci high physical address to kernel virtual
449  * address so that we can access them.
450  * @pm8001_ha: our hba structure.
451  */
452 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
453 {
454 	u32 bar;
455 	u32 logicalBar = 0;
456 	struct pci_dev *pdev;
457 
458 	pdev = pm8001_ha->pdev;
459 	/* map pci mem (PMC pci base 0-3)*/
460 	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
461 		/*
462 		** logical BARs for SPC:
463 		** bar 0 and 1 - logical BAR0
464 		** bar 2 and 3 - logical BAR1
465 		** bar4 - logical BAR2
466 		** bar5 - logical BAR3
467 		** Skip the appropriate assignments:
468 		*/
469 		if ((bar == 1) || (bar == 3))
470 			continue;
471 		if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
472 			pm8001_ha->io_mem[logicalBar].membase =
473 				pci_resource_start(pdev, bar);
474 			pm8001_ha->io_mem[logicalBar].memsize =
475 				pci_resource_len(pdev, bar);
476 			pm8001_ha->io_mem[logicalBar].memvirtaddr =
477 				ioremap(pm8001_ha->io_mem[logicalBar].membase,
478 				pm8001_ha->io_mem[logicalBar].memsize);
479 			if (!pm8001_ha->io_mem[logicalBar].memvirtaddr) {
480 				pm8001_dbg(pm8001_ha, INIT,
481 					"Failed to ioremap bar %d, logicalBar %d",
482 				   bar, logicalBar);
483 				return -ENOMEM;
484 			}
485 			pm8001_dbg(pm8001_ha, INIT,
486 				   "base addr %llx virt_addr=%llx len=%d\n",
487 				   (u64)pm8001_ha->io_mem[logicalBar].membase,
488 				   (u64)(unsigned long)
489 				   pm8001_ha->io_mem[logicalBar].memvirtaddr,
490 				   pm8001_ha->io_mem[logicalBar].memsize);
491 		} else {
492 			pm8001_ha->io_mem[logicalBar].membase	= 0;
493 			pm8001_ha->io_mem[logicalBar].memsize	= 0;
494 			pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL;
495 		}
496 		logicalBar++;
497 	}
498 	return 0;
499 }
500 
501 /**
502  * pm8001_pci_alloc - initialize our ha card structure
503  * @pdev: pci device.
504  * @ent: ent
505  * @shost: scsi host struct which has been initialized before.
506  */
507 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
508 				 const struct pci_device_id *ent,
509 				struct Scsi_Host *shost)
510 
511 {
512 	struct pm8001_hba_info *pm8001_ha;
513 	struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
514 	int j;
515 
516 	pm8001_ha = sha->lldd_ha;
517 	if (!pm8001_ha)
518 		return NULL;
519 
520 	pm8001_ha->pdev = pdev;
521 	pm8001_ha->dev = &pdev->dev;
522 	pm8001_ha->chip_id = ent->driver_data;
523 	pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
524 	pm8001_ha->irq = pdev->irq;
525 	pm8001_ha->sas = sha;
526 	pm8001_ha->shost = shost;
527 	pm8001_ha->id = pm8001_id++;
528 	pm8001_ha->logging_level = logging_level;
529 	pm8001_ha->non_fatal_count = 0;
530 	if (link_rate >= 1 && link_rate <= 15)
531 		pm8001_ha->link_rate = (link_rate << 8);
532 	else {
533 		pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 |
534 			LINKRATE_60 | LINKRATE_120;
535 		pm8001_dbg(pm8001_ha, FAIL,
536 			   "Setting link rate to default value\n");
537 	}
538 	sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
539 	/* IOMB size is 128 for 8088/89 controllers */
540 	if (pm8001_ha->chip_id != chip_8001)
541 		pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
542 	else
543 		pm8001_ha->iomb_size = IOMB_SIZE_SPC;
544 
545 #ifdef PM8001_USE_TASKLET
546 	/* Tasklet for non msi-x interrupt handler */
547 	if ((!pdev->msix_cap || !pci_msi_enabled())
548 	    || (pm8001_ha->chip_id == chip_8001))
549 		tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
550 			(unsigned long)&(pm8001_ha->irq_vector[0]));
551 	else
552 		for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
553 			tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
554 				(unsigned long)&(pm8001_ha->irq_vector[j]));
555 #endif
556 	if (pm8001_ioremap(pm8001_ha))
557 		goto failed_pci_alloc;
558 	if (!pm8001_alloc(pm8001_ha, ent))
559 		return pm8001_ha;
560 failed_pci_alloc:
561 	pm8001_free(pm8001_ha);
562 	return NULL;
563 }
564 
565 /**
566  * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
567  * @pdev: pci device.
568  */
569 static int pci_go_44(struct pci_dev *pdev)
570 {
571 	int rc;
572 
573 	rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
574 	if (rc) {
575 		rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
576 		if (rc)
577 			dev_printk(KERN_ERR, &pdev->dev,
578 				"32-bit DMA enable failed\n");
579 	}
580 	return rc;
581 }
582 
583 /**
584  * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
585  * @shost: scsi host which has been allocated outside.
586  * @chip_info: our ha struct.
587  */
588 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
589 				   const struct pm8001_chip_info *chip_info)
590 {
591 	int phy_nr, port_nr;
592 	struct asd_sas_phy **arr_phy;
593 	struct asd_sas_port **arr_port;
594 	struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
595 
596 	phy_nr = chip_info->n_phy;
597 	port_nr = phy_nr;
598 	memset(sha, 0x00, sizeof(*sha));
599 	arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
600 	if (!arr_phy)
601 		goto exit;
602 	arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
603 	if (!arr_port)
604 		goto exit_free2;
605 
606 	sha->sas_phy = arr_phy;
607 	sha->sas_port = arr_port;
608 	sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
609 	if (!sha->lldd_ha)
610 		goto exit_free1;
611 
612 	shost->transportt = pm8001_stt;
613 	shost->max_id = PM8001_MAX_DEVICES;
614 	shost->unique_id = pm8001_id;
615 	shost->max_cmd_len = 16;
616 	return 0;
617 exit_free1:
618 	kfree(arr_port);
619 exit_free2:
620 	kfree(arr_phy);
621 exit:
622 	return -1;
623 }
624 
625 /**
626  * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
627  * @shost: scsi host which has been allocated outside
628  * @chip_info: our ha struct.
629  */
630 static void  pm8001_post_sas_ha_init(struct Scsi_Host *shost,
631 				     const struct pm8001_chip_info *chip_info)
632 {
633 	int i = 0;
634 	struct pm8001_hba_info *pm8001_ha;
635 	struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
636 
637 	pm8001_ha = sha->lldd_ha;
638 	for (i = 0; i < chip_info->n_phy; i++) {
639 		sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
640 		sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
641 		sha->sas_phy[i]->sas_addr =
642 			(u8 *)&pm8001_ha->phy[i].dev_sas_addr;
643 	}
644 	sha->sas_ha_name = DRV_NAME;
645 	sha->dev = pm8001_ha->dev;
646 	sha->strict_wide_ports = 1;
647 	sha->sas_addr = &pm8001_ha->sas_addr[0];
648 	sha->num_phys = chip_info->n_phy;
649 	sha->shost = shost;
650 }
651 
652 /**
653  * pm8001_init_sas_add - initialize sas address
654  * @pm8001_ha: our ha struct.
655  *
656  * Currently we just set the fixed SAS address to our HBA, for manufacture,
657  * it should read from the EEPROM
658  */
659 static int pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
660 {
661 	u8 i, j;
662 	u8 sas_add[8];
663 #ifdef PM8001_READ_VPD
664 	/* For new SPC controllers WWN is stored in flash vpd
665 	*  For SPC/SPCve controllers WWN is stored in EEPROM
666 	*  For Older SPC WWN is stored in NVMD
667 	*/
668 	DECLARE_COMPLETION_ONSTACK(completion);
669 	struct pm8001_ioctl_payload payload;
670 	u16 deviceid;
671 	int rc;
672 	unsigned long time_remaining;
673 
674 	if (PM8001_CHIP_DISP->fatal_errors(pm8001_ha)) {
675 		pm8001_dbg(pm8001_ha, FAIL, "controller is in fatal error state\n");
676 		return -EIO;
677 	}
678 
679 	pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
680 	pm8001_ha->nvmd_completion = &completion;
681 
682 	if (pm8001_ha->chip_id == chip_8001) {
683 		if (deviceid == 0x8081 || deviceid == 0x0042) {
684 			payload.minor_function = 4;
685 			payload.rd_length = 4096;
686 		} else {
687 			payload.minor_function = 0;
688 			payload.rd_length = 128;
689 		}
690 	} else if ((pm8001_ha->chip_id == chip_8070 ||
691 			pm8001_ha->chip_id == chip_8072) &&
692 			pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
693 		payload.minor_function = 4;
694 		payload.rd_length = 4096;
695 	} else {
696 		payload.minor_function = 1;
697 		payload.rd_length = 4096;
698 	}
699 	payload.offset = 0;
700 	payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL);
701 	if (!payload.func_specific) {
702 		pm8001_dbg(pm8001_ha, FAIL, "mem alloc fail\n");
703 		return -ENOMEM;
704 	}
705 	rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
706 	if (rc) {
707 		kfree(payload.func_specific);
708 		pm8001_dbg(pm8001_ha, FAIL, "nvmd failed\n");
709 		return -EIO;
710 	}
711 	time_remaining = wait_for_completion_timeout(&completion,
712 				msecs_to_jiffies(60*1000)); // 1 min
713 	if (!time_remaining) {
714 		kfree(payload.func_specific);
715 		pm8001_dbg(pm8001_ha, FAIL, "get_nvmd_req timeout\n");
716 		return -EIO;
717 	}
718 
719 
720 	for (i = 0, j = 0; i <= 7; i++, j++) {
721 		if (pm8001_ha->chip_id == chip_8001) {
722 			if (deviceid == 0x8081)
723 				pm8001_ha->sas_addr[j] =
724 					payload.func_specific[0x704 + i];
725 			else if (deviceid == 0x0042)
726 				pm8001_ha->sas_addr[j] =
727 					payload.func_specific[0x010 + i];
728 		} else if ((pm8001_ha->chip_id == chip_8070 ||
729 				pm8001_ha->chip_id == chip_8072) &&
730 				pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
731 			pm8001_ha->sas_addr[j] =
732 					payload.func_specific[0x010 + i];
733 		} else
734 			pm8001_ha->sas_addr[j] =
735 					payload.func_specific[0x804 + i];
736 	}
737 	memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE);
738 	for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
739 		if (i && ((i % 4) == 0))
740 			sas_add[7] = sas_add[7] + 4;
741 		memcpy(&pm8001_ha->phy[i].dev_sas_addr,
742 			sas_add, SAS_ADDR_SIZE);
743 		pm8001_dbg(pm8001_ha, INIT, "phy %d sas_addr = %016llx\n", i,
744 			   pm8001_ha->phy[i].dev_sas_addr);
745 	}
746 	kfree(payload.func_specific);
747 #else
748 	for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
749 		pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
750 		pm8001_ha->phy[i].dev_sas_addr =
751 			cpu_to_be64((u64)
752 				(*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
753 	}
754 	memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
755 		SAS_ADDR_SIZE);
756 #endif
757 	return 0;
758 }
759 
760 /*
761  * pm8001_get_phy_settings_info : Read phy setting values.
762  * @pm8001_ha : our hba.
763  */
764 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
765 {
766 
767 #ifdef PM8001_READ_VPD
768 	/*OPTION ROM FLASH read for the SPC cards */
769 	DECLARE_COMPLETION_ONSTACK(completion);
770 	struct pm8001_ioctl_payload payload;
771 	int rc;
772 
773 	pm8001_ha->nvmd_completion = &completion;
774 	/* SAS ADDRESS read from flash / EEPROM */
775 	payload.minor_function = 6;
776 	payload.offset = 0;
777 	payload.rd_length = 4096;
778 	payload.func_specific = kzalloc(4096, GFP_KERNEL);
779 	if (!payload.func_specific)
780 		return -ENOMEM;
781 	/* Read phy setting values from flash */
782 	rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
783 	if (rc) {
784 		kfree(payload.func_specific);
785 		pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
786 		return -ENOMEM;
787 	}
788 	wait_for_completion(&completion);
789 	pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
790 	kfree(payload.func_specific);
791 #endif
792 	return 0;
793 }
794 
795 struct pm8001_mpi3_phy_pg_trx_config {
796 	u32 LaneLosCfg;
797 	u32 LanePgaCfg1;
798 	u32 LanePisoCfg1;
799 	u32 LanePisoCfg2;
800 	u32 LanePisoCfg3;
801 	u32 LanePisoCfg4;
802 	u32 LanePisoCfg5;
803 	u32 LanePisoCfg6;
804 	u32 LaneBctCtrl;
805 };
806 
807 /**
808  * pm8001_get_internal_phy_settings - Retrieves the internal PHY settings
809  * @pm8001_ha : our adapter
810  * @phycfg : PHY config page to populate
811  */
812 static
813 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
814 		struct pm8001_mpi3_phy_pg_trx_config *phycfg)
815 {
816 	phycfg->LaneLosCfg   = 0x00000132;
817 	phycfg->LanePgaCfg1  = 0x00203949;
818 	phycfg->LanePisoCfg1 = 0x000000FF;
819 	phycfg->LanePisoCfg2 = 0xFF000001;
820 	phycfg->LanePisoCfg3 = 0xE7011300;
821 	phycfg->LanePisoCfg4 = 0x631C40C0;
822 	phycfg->LanePisoCfg5 = 0xF8102036;
823 	phycfg->LanePisoCfg6 = 0xF74A1000;
824 	phycfg->LaneBctCtrl  = 0x00FB33F8;
825 }
826 
827 /**
828  * pm8001_get_external_phy_settings - Retrieves the external PHY settings
829  * @pm8001_ha : our adapter
830  * @phycfg : PHY config page to populate
831  */
832 static
833 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
834 		struct pm8001_mpi3_phy_pg_trx_config *phycfg)
835 {
836 	phycfg->LaneLosCfg   = 0x00000132;
837 	phycfg->LanePgaCfg1  = 0x00203949;
838 	phycfg->LanePisoCfg1 = 0x000000FF;
839 	phycfg->LanePisoCfg2 = 0xFF000001;
840 	phycfg->LanePisoCfg3 = 0xE7011300;
841 	phycfg->LanePisoCfg4 = 0x63349140;
842 	phycfg->LanePisoCfg5 = 0xF8102036;
843 	phycfg->LanePisoCfg6 = 0xF80D9300;
844 	phycfg->LaneBctCtrl  = 0x00FB33F8;
845 }
846 
847 /**
848  * pm8001_get_phy_mask - Retrieves the mask that denotes if a PHY is int/ext
849  * @pm8001_ha : our adapter
850  * @phymask : The PHY mask
851  */
852 static
853 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
854 {
855 	switch (pm8001_ha->pdev->subsystem_device) {
856 	case 0x0070: /* H1280 - 8 external 0 internal */
857 	case 0x0072: /* H12F0 - 16 external 0 internal */
858 		*phymask = 0x0000;
859 		break;
860 
861 	case 0x0071: /* H1208 - 0 external 8 internal */
862 	case 0x0073: /* H120F - 0 external 16 internal */
863 		*phymask = 0xFFFF;
864 		break;
865 
866 	case 0x0080: /* H1244 - 4 external 4 internal */
867 		*phymask = 0x00F0;
868 		break;
869 
870 	case 0x0081: /* H1248 - 4 external 8 internal */
871 		*phymask = 0x0FF0;
872 		break;
873 
874 	case 0x0082: /* H1288 - 8 external 8 internal */
875 		*phymask = 0xFF00;
876 		break;
877 
878 	default:
879 		pm8001_dbg(pm8001_ha, INIT,
880 			   "Unknown subsystem device=0x%.04x\n",
881 			   pm8001_ha->pdev->subsystem_device);
882 	}
883 }
884 
885 /**
886  * pm8001_set_phy_settings_ven_117c_12G() - Configure ATTO 12Gb PHY settings
887  * @pm8001_ha : our adapter
888  */
889 static
890 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
891 {
892 	struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
893 	struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
894 	int phymask = 0;
895 	int i = 0;
896 
897 	memset(&phycfg_int, 0, sizeof(phycfg_int));
898 	memset(&phycfg_ext, 0, sizeof(phycfg_ext));
899 
900 	pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
901 	pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
902 	pm8001_get_phy_mask(pm8001_ha, &phymask);
903 
904 	for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
905 		if (phymask & (1 << i)) {/* Internal PHY */
906 			pm8001_set_phy_profile_single(pm8001_ha, i,
907 					sizeof(phycfg_int) / sizeof(u32),
908 					(u32 *)&phycfg_int);
909 
910 		} else { /* External PHY */
911 			pm8001_set_phy_profile_single(pm8001_ha, i,
912 					sizeof(phycfg_ext) / sizeof(u32),
913 					(u32 *)&phycfg_ext);
914 		}
915 	}
916 
917 	return 0;
918 }
919 
920 /**
921  * pm8001_configure_phy_settings - Configures PHY settings based on vendor ID.
922  * @pm8001_ha : our hba.
923  */
924 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
925 {
926 	switch (pm8001_ha->pdev->subsystem_vendor) {
927 	case PCI_VENDOR_ID_ATTO:
928 		if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */
929 			return 0;
930 		else
931 			return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
932 
933 	case PCI_VENDOR_ID_ADAPTEC2:
934 	case 0:
935 		return 0;
936 
937 	default:
938 		return pm8001_get_phy_settings_info(pm8001_ha);
939 	}
940 }
941 
942 #ifdef PM8001_USE_MSIX
943 /**
944  * pm8001_setup_msix - enable MSI-X interrupt
945  * @pm8001_ha: our ha struct.
946  */
947 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
948 {
949 	unsigned int allocated_irq_vectors;
950 	int rc;
951 
952 	/* SPCv controllers supports 64 msi-x */
953 	if (pm8001_ha->chip_id == chip_8001) {
954 		rc = pci_alloc_irq_vectors(pm8001_ha->pdev, 1, 1,
955 					   PCI_IRQ_MSIX);
956 	} else {
957 		/*
958 		 * Queue index #0 is used always for housekeeping, so don't
959 		 * include in the affinity spreading.
960 		 */
961 		struct irq_affinity desc = {
962 			.pre_vectors = 1,
963 		};
964 		rc = pci_alloc_irq_vectors_affinity(
965 				pm8001_ha->pdev, 2, PM8001_MAX_MSIX_VEC,
966 				PCI_IRQ_MSIX | PCI_IRQ_AFFINITY, &desc);
967 	}
968 
969 	allocated_irq_vectors = rc;
970 	if (rc < 0)
971 		return rc;
972 
973 	/* Assigns the number of interrupts */
974 	pm8001_ha->number_of_intr = allocated_irq_vectors;
975 
976 	/* Maximum queue number updating in HBA structure */
977 	pm8001_ha->max_q_num = allocated_irq_vectors;
978 
979 	pm8001_dbg(pm8001_ha, INIT,
980 		   "pci_alloc_irq_vectors request ret:%d no of intr %d\n",
981 		   rc, pm8001_ha->number_of_intr);
982 	return 0;
983 }
984 
985 static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha)
986 {
987 	u32 i = 0, j = 0;
988 	int flag = 0, rc = 0;
989 	int nr_irqs = pm8001_ha->number_of_intr;
990 
991 	if (pm8001_ha->chip_id != chip_8001)
992 		flag &= ~IRQF_SHARED;
993 
994 	pm8001_dbg(pm8001_ha, INIT,
995 		   "pci_enable_msix request number of intr %d\n",
996 		   pm8001_ha->number_of_intr);
997 
998 	if (nr_irqs > ARRAY_SIZE(pm8001_ha->intr_drvname))
999 		nr_irqs = ARRAY_SIZE(pm8001_ha->intr_drvname);
1000 
1001 	for (i = 0; i < nr_irqs; i++) {
1002 		snprintf(pm8001_ha->intr_drvname[i],
1003 			sizeof(pm8001_ha->intr_drvname[0]),
1004 			"%s-%d", pm8001_ha->name, i);
1005 		pm8001_ha->irq_vector[i].irq_id = i;
1006 		pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
1007 
1008 		rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i),
1009 			pm8001_interrupt_handler_msix, flag,
1010 			pm8001_ha->intr_drvname[i],
1011 			&(pm8001_ha->irq_vector[i]));
1012 		if (rc) {
1013 			for (j = 0; j < i; j++) {
1014 				free_irq(pci_irq_vector(pm8001_ha->pdev, i),
1015 					&(pm8001_ha->irq_vector[i]));
1016 			}
1017 			pci_free_irq_vectors(pm8001_ha->pdev);
1018 			break;
1019 		}
1020 	}
1021 
1022 	return rc;
1023 }
1024 #endif
1025 
1026 /**
1027  * pm8001_request_irq - register interrupt
1028  * @pm8001_ha: our ha struct.
1029  */
1030 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
1031 {
1032 	struct pci_dev *pdev = pm8001_ha->pdev;
1033 #ifdef PM8001_USE_MSIX
1034 	int rc;
1035 
1036 	if (pci_find_capability(pdev, PCI_CAP_ID_MSIX)) {
1037 		rc = pm8001_setup_msix(pm8001_ha);
1038 		if (rc) {
1039 			pm8001_dbg(pm8001_ha, FAIL,
1040 				   "pm8001_setup_irq failed [ret: %d]\n", rc);
1041 			return rc;
1042 		}
1043 
1044 		if (pdev->msix_cap && pci_msi_enabled())
1045 			return pm8001_request_msix(pm8001_ha);
1046 	}
1047 
1048 	pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1049 #endif
1050 
1051 	/* initialize the INT-X interrupt */
1052 	pm8001_ha->irq_vector[0].irq_id = 0;
1053 	pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
1054 
1055 	return request_irq(pdev->irq, pm8001_interrupt_handler_intx,
1056 			   IRQF_SHARED, pm8001_ha->name,
1057 			   SHOST_TO_SAS_HA(pm8001_ha->shost));
1058 }
1059 
1060 /**
1061  * pm8001_pci_probe - probe supported device
1062  * @pdev: pci device which kernel has been prepared for.
1063  * @ent: pci device id
1064  *
1065  * This function is the main initialization function, when register a new
1066  * pci driver it is invoked, all struct and hardware initialization should be
1067  * done here, also, register interrupt.
1068  */
1069 static int pm8001_pci_probe(struct pci_dev *pdev,
1070 			    const struct pci_device_id *ent)
1071 {
1072 	unsigned int rc;
1073 	u32	pci_reg;
1074 	u8	i = 0;
1075 	struct pm8001_hba_info *pm8001_ha;
1076 	struct Scsi_Host *shost = NULL;
1077 	const struct pm8001_chip_info *chip;
1078 	struct sas_ha_struct *sha;
1079 
1080 	dev_printk(KERN_INFO, &pdev->dev,
1081 		"pm80xx: driver version %s\n", DRV_VERSION);
1082 	rc = pci_enable_device(pdev);
1083 	if (rc)
1084 		goto err_out_enable;
1085 	pci_set_master(pdev);
1086 	/*
1087 	 * Enable pci slot busmaster by setting pci command register.
1088 	 * This is required by FW for Cyclone card.
1089 	 */
1090 
1091 	pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
1092 	pci_reg |= 0x157;
1093 	pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
1094 	rc = pci_request_regions(pdev, DRV_NAME);
1095 	if (rc)
1096 		goto err_out_disable;
1097 	rc = pci_go_44(pdev);
1098 	if (rc)
1099 		goto err_out_regions;
1100 
1101 	shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
1102 	if (!shost) {
1103 		rc = -ENOMEM;
1104 		goto err_out_regions;
1105 	}
1106 	chip = &pm8001_chips[ent->driver_data];
1107 	sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
1108 	if (!sha) {
1109 		rc = -ENOMEM;
1110 		goto err_out_free_host;
1111 	}
1112 	SHOST_TO_SAS_HA(shost) = sha;
1113 
1114 	rc = pm8001_prep_sas_ha_init(shost, chip);
1115 	if (rc) {
1116 		rc = -ENOMEM;
1117 		goto err_out_free;
1118 	}
1119 	pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
1120 	/* ent->driver variable is used to differentiate between controllers */
1121 	pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
1122 	if (!pm8001_ha) {
1123 		rc = -ENOMEM;
1124 		goto err_out_free;
1125 	}
1126 
1127 	PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1128 	rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1129 	if (rc) {
1130 		pm8001_dbg(pm8001_ha, FAIL,
1131 			   "chip_init failed [ret: %d]\n", rc);
1132 		goto err_out_ha_free;
1133 	}
1134 
1135 	rc = pm8001_init_ccb_tag(pm8001_ha);
1136 	if (rc)
1137 		goto err_out_enable;
1138 
1139 
1140 	PM8001_CHIP_DISP->chip_post_init(pm8001_ha);
1141 
1142 	if (pm8001_ha->number_of_intr > 1) {
1143 		shost->nr_hw_queues = pm8001_ha->number_of_intr - 1;
1144 		/*
1145 		 * For now, ensure we're not sent too many commands by setting
1146 		 * host_tagset. This is also required if we start using request
1147 		 * tag.
1148 		 */
1149 		shost->host_tagset = 1;
1150 	}
1151 
1152 	rc = scsi_add_host(shost, &pdev->dev);
1153 	if (rc)
1154 		goto err_out_ha_free;
1155 
1156 	PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1157 	if (pm8001_ha->chip_id != chip_8001) {
1158 		for (i = 1; i < pm8001_ha->number_of_intr; i++)
1159 			PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1160 		/* setup thermal configuration. */
1161 		pm80xx_set_thermal_config(pm8001_ha);
1162 	}
1163 
1164 	rc = pm8001_init_sas_add(pm8001_ha);
1165 	if (rc)
1166 		goto err_out_shost;
1167 	/* phy setting support for motherboard controller */
1168 	rc = pm8001_configure_phy_settings(pm8001_ha);
1169 	if (rc)
1170 		goto err_out_shost;
1171 
1172 	pm8001_post_sas_ha_init(shost, chip);
1173 	rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
1174 	if (rc) {
1175 		pm8001_dbg(pm8001_ha, FAIL,
1176 			   "sas_register_ha failed [ret: %d]\n", rc);
1177 		goto err_out_shost;
1178 	}
1179 	list_add_tail(&pm8001_ha->list, &hba_list);
1180 	pm8001_ha->flags = PM8001F_RUN_TIME;
1181 	scsi_scan_host(pm8001_ha->shost);
1182 	return 0;
1183 
1184 err_out_shost:
1185 	scsi_remove_host(pm8001_ha->shost);
1186 err_out_ha_free:
1187 	pm8001_free(pm8001_ha);
1188 err_out_free:
1189 	kfree(sha);
1190 err_out_free_host:
1191 	scsi_host_put(shost);
1192 err_out_regions:
1193 	pci_release_regions(pdev);
1194 err_out_disable:
1195 	pci_disable_device(pdev);
1196 err_out_enable:
1197 	return rc;
1198 }
1199 
1200 /**
1201  * pm8001_init_ccb_tag - allocate memory to CCB and tag.
1202  * @pm8001_ha: our hba card information.
1203  */
1204 static int pm8001_init_ccb_tag(struct pm8001_hba_info *pm8001_ha)
1205 {
1206 	struct Scsi_Host *shost = pm8001_ha->shost;
1207 	struct device *dev = pm8001_ha->dev;
1208 	u32 max_out_io, ccb_count;
1209 	int i;
1210 
1211 	max_out_io = pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io;
1212 	ccb_count = min_t(int, PM8001_MAX_CCB, max_out_io);
1213 
1214 	shost->can_queue = ccb_count - PM8001_RESERVE_SLOT;
1215 
1216 	pm8001_ha->rsvd_tags = bitmap_zalloc(PM8001_RESERVE_SLOT, GFP_KERNEL);
1217 	if (!pm8001_ha->rsvd_tags)
1218 		goto err_out;
1219 
1220 	/* Memory region for ccb_info*/
1221 	pm8001_ha->ccb_count = ccb_count;
1222 	pm8001_ha->ccb_info =
1223 		kcalloc(ccb_count, sizeof(struct pm8001_ccb_info), GFP_KERNEL);
1224 	if (!pm8001_ha->ccb_info) {
1225 		pm8001_dbg(pm8001_ha, FAIL,
1226 			   "Unable to allocate memory for ccb\n");
1227 		goto err_out_noccb;
1228 	}
1229 	for (i = 0; i < ccb_count; i++) {
1230 		pm8001_ha->ccb_info[i].buf_prd = dma_alloc_coherent(dev,
1231 				sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1232 				&pm8001_ha->ccb_info[i].ccb_dma_handle,
1233 				GFP_KERNEL);
1234 		if (!pm8001_ha->ccb_info[i].buf_prd) {
1235 			pm8001_dbg(pm8001_ha, FAIL,
1236 				   "ccb prd memory allocation error\n");
1237 			goto err_out;
1238 		}
1239 		pm8001_ha->ccb_info[i].task = NULL;
1240 		pm8001_ha->ccb_info[i].ccb_tag = PM8001_INVALID_TAG;
1241 		pm8001_ha->ccb_info[i].device = NULL;
1242 	}
1243 
1244 	return 0;
1245 
1246 err_out_noccb:
1247 	kfree(pm8001_ha->devices);
1248 err_out:
1249 	return -ENOMEM;
1250 }
1251 
1252 static void pm8001_pci_remove(struct pci_dev *pdev)
1253 {
1254 	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1255 	struct pm8001_hba_info *pm8001_ha;
1256 	int i, j;
1257 	pm8001_ha = sha->lldd_ha;
1258 	sas_unregister_ha(sha);
1259 	sas_remove_host(pm8001_ha->shost);
1260 	list_del(&pm8001_ha->list);
1261 	PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1262 	PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1263 
1264 #ifdef PM8001_USE_MSIX
1265 	for (i = 0; i < pm8001_ha->number_of_intr; i++)
1266 		synchronize_irq(pci_irq_vector(pdev, i));
1267 	for (i = 0; i < pm8001_ha->number_of_intr; i++)
1268 		free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1269 	pci_free_irq_vectors(pdev);
1270 #else
1271 	free_irq(pm8001_ha->irq, sha);
1272 #endif
1273 #ifdef PM8001_USE_TASKLET
1274 	/* For non-msix and msix interrupts */
1275 	if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1276 	    (pm8001_ha->chip_id == chip_8001))
1277 		tasklet_kill(&pm8001_ha->tasklet[0]);
1278 	else
1279 		for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1280 			tasklet_kill(&pm8001_ha->tasklet[j]);
1281 #endif
1282 	scsi_host_put(pm8001_ha->shost);
1283 
1284 	for (i = 0; i < pm8001_ha->ccb_count; i++) {
1285 		dma_free_coherent(&pm8001_ha->pdev->dev,
1286 			sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1287 			pm8001_ha->ccb_info[i].buf_prd,
1288 			pm8001_ha->ccb_info[i].ccb_dma_handle);
1289 	}
1290 	kfree(pm8001_ha->ccb_info);
1291 	kfree(pm8001_ha->devices);
1292 
1293 	pm8001_free(pm8001_ha);
1294 	kfree(sha->sas_phy);
1295 	kfree(sha->sas_port);
1296 	kfree(sha);
1297 	pci_release_regions(pdev);
1298 	pci_disable_device(pdev);
1299 }
1300 
1301 /**
1302  * pm8001_pci_suspend - power management suspend main entry point
1303  * @dev: Device struct
1304  *
1305  * Return: 0 on success, anything else on error.
1306  */
1307 static int __maybe_unused pm8001_pci_suspend(struct device *dev)
1308 {
1309 	struct pci_dev *pdev = to_pci_dev(dev);
1310 	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1311 	struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
1312 	int  i, j;
1313 	sas_suspend_ha(sha);
1314 	flush_workqueue(pm8001_wq);
1315 	scsi_block_requests(pm8001_ha->shost);
1316 	if (!pdev->pm_cap) {
1317 		dev_err(dev, " PCI PM not supported\n");
1318 		return -ENODEV;
1319 	}
1320 	PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1321 	PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1322 #ifdef PM8001_USE_MSIX
1323 	for (i = 0; i < pm8001_ha->number_of_intr; i++)
1324 		synchronize_irq(pci_irq_vector(pdev, i));
1325 	for (i = 0; i < pm8001_ha->number_of_intr; i++)
1326 		free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1327 	pci_free_irq_vectors(pdev);
1328 #else
1329 	free_irq(pm8001_ha->irq, sha);
1330 #endif
1331 #ifdef PM8001_USE_TASKLET
1332 	/* For non-msix and msix interrupts */
1333 	if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1334 	    (pm8001_ha->chip_id == chip_8001))
1335 		tasklet_kill(&pm8001_ha->tasklet[0]);
1336 	else
1337 		for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1338 			tasklet_kill(&pm8001_ha->tasklet[j]);
1339 #endif
1340 	pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, entering "
1341 		      "suspended state\n", pdev,
1342 		      pm8001_ha->name);
1343 	return 0;
1344 }
1345 
1346 /**
1347  * pm8001_pci_resume - power management resume main entry point
1348  * @dev: Device struct
1349  *
1350  * Return: 0 on success, anything else on error.
1351  */
1352 static int __maybe_unused pm8001_pci_resume(struct device *dev)
1353 {
1354 	struct pci_dev *pdev = to_pci_dev(dev);
1355 	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1356 	struct pm8001_hba_info *pm8001_ha;
1357 	int rc;
1358 	u8 i = 0, j;
1359 	DECLARE_COMPLETION_ONSTACK(completion);
1360 
1361 	pm8001_ha = sha->lldd_ha;
1362 
1363 	pm8001_info(pm8001_ha,
1364 		    "pdev=0x%p, slot=%s, resuming from previous operating state [D%d]\n",
1365 		    pdev, pm8001_ha->name, pdev->current_state);
1366 
1367 	rc = pci_go_44(pdev);
1368 	if (rc)
1369 		goto err_out_disable;
1370 	sas_prep_resume_ha(sha);
1371 	/* chip soft rst only for spc */
1372 	if (pm8001_ha->chip_id == chip_8001) {
1373 		PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1374 		pm8001_dbg(pm8001_ha, INIT, "chip soft reset successful\n");
1375 	}
1376 	rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1377 	if (rc)
1378 		goto err_out_disable;
1379 
1380 	/* disable all the interrupt bits */
1381 	PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1382 
1383 	rc = pm8001_request_irq(pm8001_ha);
1384 	if (rc)
1385 		goto err_out_disable;
1386 #ifdef PM8001_USE_TASKLET
1387 	/*  Tasklet for non msi-x interrupt handler */
1388 	if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1389 	    (pm8001_ha->chip_id == chip_8001))
1390 		tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1391 			(unsigned long)&(pm8001_ha->irq_vector[0]));
1392 	else
1393 		for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1394 			tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1395 				(unsigned long)&(pm8001_ha->irq_vector[j]));
1396 #endif
1397 	PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1398 	if (pm8001_ha->chip_id != chip_8001) {
1399 		for (i = 1; i < pm8001_ha->number_of_intr; i++)
1400 			PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1401 	}
1402 
1403 	/* Chip documentation for the 8070 and 8072 SPCv    */
1404 	/* states that a 500ms minimum delay is required    */
1405 	/* before issuing commands. Otherwise, the firmware */
1406 	/* will enter an unrecoverable state.               */
1407 
1408 	if (pm8001_ha->chip_id == chip_8070 ||
1409 		pm8001_ha->chip_id == chip_8072) {
1410 		mdelay(500);
1411 	}
1412 
1413 	/* Spin up the PHYs */
1414 
1415 	pm8001_ha->flags = PM8001F_RUN_TIME;
1416 	for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1417 		pm8001_ha->phy[i].enable_completion = &completion;
1418 		PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1419 		wait_for_completion(&completion);
1420 	}
1421 	sas_resume_ha(sha);
1422 	return 0;
1423 
1424 err_out_disable:
1425 	scsi_remove_host(pm8001_ha->shost);
1426 
1427 	return rc;
1428 }
1429 
1430 /* update of pci device, vendor id and driver data with
1431  * unique value for each of the controller
1432  */
1433 static struct pci_device_id pm8001_pci_table[] = {
1434 	{ PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1435 	{ PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1436 	{ PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1437 	{ PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1438 	/* Support for SPC/SPCv/SPCve controllers */
1439 	{ PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1440 	{ PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1441 	{ PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1442 	{ PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1443 	{ PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1444 	{ PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1445 	{ PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1446 	{ PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1447 	{ PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1448 	{ PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1449 	{ PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1450 	{ PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1451 	{ PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1452 	{ PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1453 	{ PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1454 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1455 		PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1456 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1457 		PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1458 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1459 		PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1460 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1461 		PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1462 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1463 		PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1464 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1465 		PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1466 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1467 		PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1468 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1469 		PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1470 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1471 		PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1472 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1473 		PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1474 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1475 		PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1476 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1477 		PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1478 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1479 		PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1480 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1481 		PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1482 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1483 		PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1484 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1485 		PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1486 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1487 		PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1488 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1489 		PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1490 	{ PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1491 		PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1492 	{ PCI_VENDOR_ID_ATTO, 0x8070,
1493 		PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1494 	{ PCI_VENDOR_ID_ATTO, 0x8070,
1495 		PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1496 	{ PCI_VENDOR_ID_ATTO, 0x8072,
1497 		PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1498 	{ PCI_VENDOR_ID_ATTO, 0x8072,
1499 		PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1500 	{ PCI_VENDOR_ID_ATTO, 0x8070,
1501 		PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1502 	{ PCI_VENDOR_ID_ATTO, 0x8072,
1503 		PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1504 	{ PCI_VENDOR_ID_ATTO, 0x8072,
1505 		PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1506 	{} /* terminate list */
1507 };
1508 
1509 static SIMPLE_DEV_PM_OPS(pm8001_pci_pm_ops,
1510 			 pm8001_pci_suspend,
1511 			 pm8001_pci_resume);
1512 
1513 static struct pci_driver pm8001_pci_driver = {
1514 	.name		= DRV_NAME,
1515 	.id_table	= pm8001_pci_table,
1516 	.probe		= pm8001_pci_probe,
1517 	.remove		= pm8001_pci_remove,
1518 	.driver.pm	= &pm8001_pci_pm_ops,
1519 };
1520 
1521 /**
1522  *	pm8001_init - initialize scsi transport template
1523  */
1524 static int __init pm8001_init(void)
1525 {
1526 	int rc = -ENOMEM;
1527 
1528 	pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1529 	if (!pm8001_wq)
1530 		goto err;
1531 
1532 	pm8001_id = 0;
1533 	pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1534 	if (!pm8001_stt)
1535 		goto err_wq;
1536 	rc = pci_register_driver(&pm8001_pci_driver);
1537 	if (rc)
1538 		goto err_tp;
1539 	return 0;
1540 
1541 err_tp:
1542 	sas_release_transport(pm8001_stt);
1543 err_wq:
1544 	destroy_workqueue(pm8001_wq);
1545 err:
1546 	return rc;
1547 }
1548 
1549 static void __exit pm8001_exit(void)
1550 {
1551 	pci_unregister_driver(&pm8001_pci_driver);
1552 	sas_release_transport(pm8001_stt);
1553 	destroy_workqueue(pm8001_wq);
1554 }
1555 
1556 module_init(pm8001_init);
1557 module_exit(pm8001_exit);
1558 
1559 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1560 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1561 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1562 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1563 MODULE_DESCRIPTION(
1564 		"PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1565 		"SAS/SATA controller driver");
1566 MODULE_VERSION(DRV_VERSION);
1567 MODULE_LICENSE("GPL");
1568 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1569 
1570