1 /* 2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 USI Co., Ltd. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 41 #include <linux/slab.h> 42 #include "pm8001_sas.h" 43 #include "pm8001_chips.h" 44 45 static struct scsi_transport_template *pm8001_stt; 46 47 /** 48 * chip info structure to identify chip key functionality as 49 * encryption available/not, no of ports, hw specific function ref 50 */ 51 static const struct pm8001_chip_info pm8001_chips[] = { 52 [chip_8001] = {0, 8, &pm8001_8001_dispatch,}, 53 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,}, 54 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,}, 55 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,}, 56 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,}, 57 [chip_8074] = {0, 8, &pm8001_80xx_dispatch,}, 58 [chip_8076] = {0, 16, &pm8001_80xx_dispatch,}, 59 [chip_8077] = {0, 16, &pm8001_80xx_dispatch,}, 60 [chip_8006] = {0, 16, &pm8001_80xx_dispatch,}, 61 [chip_8070] = {0, 8, &pm8001_80xx_dispatch,}, 62 [chip_8072] = {0, 16, &pm8001_80xx_dispatch,}, 63 }; 64 static int pm8001_id; 65 66 LIST_HEAD(hba_list); 67 68 struct workqueue_struct *pm8001_wq; 69 70 /** 71 * The main structure which LLDD must register for scsi core. 72 */ 73 static struct scsi_host_template pm8001_sht = { 74 .module = THIS_MODULE, 75 .name = DRV_NAME, 76 .queuecommand = sas_queuecommand, 77 .target_alloc = sas_target_alloc, 78 .slave_configure = sas_slave_configure, 79 .scan_finished = pm8001_scan_finished, 80 .scan_start = pm8001_scan_start, 81 .change_queue_depth = sas_change_queue_depth, 82 .bios_param = sas_bios_param, 83 .can_queue = 1, 84 .this_id = -1, 85 .sg_tablesize = SG_ALL, 86 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 87 .use_clustering = ENABLE_CLUSTERING, 88 .eh_device_reset_handler = sas_eh_device_reset_handler, 89 .eh_target_reset_handler = sas_eh_target_reset_handler, 90 .target_destroy = sas_target_destroy, 91 .ioctl = sas_ioctl, 92 .shost_attrs = pm8001_host_attrs, 93 .track_queue_depth = 1, 94 }; 95 96 /** 97 * Sas layer call this function to execute specific task. 98 */ 99 static struct sas_domain_function_template pm8001_transport_ops = { 100 .lldd_dev_found = pm8001_dev_found, 101 .lldd_dev_gone = pm8001_dev_gone, 102 103 .lldd_execute_task = pm8001_queue_command, 104 .lldd_control_phy = pm8001_phy_control, 105 106 .lldd_abort_task = pm8001_abort_task, 107 .lldd_abort_task_set = pm8001_abort_task_set, 108 .lldd_clear_aca = pm8001_clear_aca, 109 .lldd_clear_task_set = pm8001_clear_task_set, 110 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset, 111 .lldd_lu_reset = pm8001_lu_reset, 112 .lldd_query_task = pm8001_query_task, 113 }; 114 115 /** 116 *pm8001_phy_init - initiate our adapter phys 117 *@pm8001_ha: our hba structure. 118 *@phy_id: phy id. 119 */ 120 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id) 121 { 122 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 123 struct asd_sas_phy *sas_phy = &phy->sas_phy; 124 phy->phy_state = 0; 125 phy->pm8001_ha = pm8001_ha; 126 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0; 127 sas_phy->class = SAS; 128 sas_phy->iproto = SAS_PROTOCOL_ALL; 129 sas_phy->tproto = 0; 130 sas_phy->type = PHY_TYPE_PHYSICAL; 131 sas_phy->role = PHY_ROLE_INITIATOR; 132 sas_phy->oob_mode = OOB_NOT_CONNECTED; 133 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN; 134 sas_phy->id = phy_id; 135 sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr; 136 sas_phy->frame_rcvd = &phy->frame_rcvd[0]; 137 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata; 138 sas_phy->lldd_phy = phy; 139 } 140 141 /** 142 *pm8001_free - free hba 143 *@pm8001_ha: our hba structure. 144 * 145 */ 146 static void pm8001_free(struct pm8001_hba_info *pm8001_ha) 147 { 148 int i; 149 150 if (!pm8001_ha) 151 return; 152 153 for (i = 0; i < USI_MAX_MEMCNT; i++) { 154 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) { 155 pci_free_consistent(pm8001_ha->pdev, 156 (pm8001_ha->memoryMap.region[i].total_len + 157 pm8001_ha->memoryMap.region[i].alignment), 158 pm8001_ha->memoryMap.region[i].virt_ptr, 159 pm8001_ha->memoryMap.region[i].phys_addr); 160 } 161 } 162 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha); 163 flush_workqueue(pm8001_wq); 164 kfree(pm8001_ha->tags); 165 kfree(pm8001_ha); 166 } 167 168 #ifdef PM8001_USE_TASKLET 169 170 /** 171 * tasklet for 64 msi-x interrupt handler 172 * @opaque: the passed general host adapter struct 173 * Note: pm8001_tasklet is common for pm8001 & pm80xx 174 */ 175 static void pm8001_tasklet(unsigned long opaque) 176 { 177 struct pm8001_hba_info *pm8001_ha; 178 struct isr_param *irq_vector; 179 180 irq_vector = (struct isr_param *)opaque; 181 pm8001_ha = irq_vector->drv_inst; 182 if (unlikely(!pm8001_ha)) 183 BUG_ON(1); 184 PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id); 185 } 186 #endif 187 188 /** 189 * pm8001_interrupt_handler_msix - main MSIX interrupt handler. 190 * It obtains the vector number and calls the equivalent bottom 191 * half or services directly. 192 * @opaque: the passed outbound queue/vector. Host structure is 193 * retrieved from the same. 194 */ 195 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque) 196 { 197 struct isr_param *irq_vector; 198 struct pm8001_hba_info *pm8001_ha; 199 irqreturn_t ret = IRQ_HANDLED; 200 irq_vector = (struct isr_param *)opaque; 201 pm8001_ha = irq_vector->drv_inst; 202 203 if (unlikely(!pm8001_ha)) 204 return IRQ_NONE; 205 if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha)) 206 return IRQ_NONE; 207 #ifdef PM8001_USE_TASKLET 208 tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]); 209 #else 210 ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id); 211 #endif 212 return ret; 213 } 214 215 /** 216 * pm8001_interrupt_handler_intx - main INTx interrupt handler. 217 * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure. 218 */ 219 220 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id) 221 { 222 struct pm8001_hba_info *pm8001_ha; 223 irqreturn_t ret = IRQ_HANDLED; 224 struct sas_ha_struct *sha = dev_id; 225 pm8001_ha = sha->lldd_ha; 226 if (unlikely(!pm8001_ha)) 227 return IRQ_NONE; 228 if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha)) 229 return IRQ_NONE; 230 231 #ifdef PM8001_USE_TASKLET 232 tasklet_schedule(&pm8001_ha->tasklet[0]); 233 #else 234 ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0); 235 #endif 236 return ret; 237 } 238 239 /** 240 * pm8001_alloc - initiate our hba structure and 6 DMAs area. 241 * @pm8001_ha:our hba structure. 242 * 243 */ 244 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha, 245 const struct pci_device_id *ent) 246 { 247 int i; 248 spin_lock_init(&pm8001_ha->lock); 249 spin_lock_init(&pm8001_ha->bitmap_lock); 250 PM8001_INIT_DBG(pm8001_ha, 251 pm8001_printk("pm8001_alloc: PHY:%x\n", 252 pm8001_ha->chip->n_phy)); 253 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 254 pm8001_phy_init(pm8001_ha, i); 255 pm8001_ha->port[i].wide_port_phymap = 0; 256 pm8001_ha->port[i].port_attached = 0; 257 pm8001_ha->port[i].port_state = 0; 258 INIT_LIST_HEAD(&pm8001_ha->port[i].list); 259 } 260 261 pm8001_ha->tags = kzalloc(PM8001_MAX_CCB, GFP_KERNEL); 262 if (!pm8001_ha->tags) 263 goto err_out; 264 /* MPI Memory region 1 for AAP Event Log for fw */ 265 pm8001_ha->memoryMap.region[AAP1].num_elements = 1; 266 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE; 267 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE; 268 pm8001_ha->memoryMap.region[AAP1].alignment = 32; 269 270 /* MPI Memory region 2 for IOP Event Log for fw */ 271 pm8001_ha->memoryMap.region[IOP].num_elements = 1; 272 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE; 273 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE; 274 pm8001_ha->memoryMap.region[IOP].alignment = 32; 275 276 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) { 277 /* MPI Memory region 3 for consumer Index of inbound queues */ 278 pm8001_ha->memoryMap.region[CI+i].num_elements = 1; 279 pm8001_ha->memoryMap.region[CI+i].element_size = 4; 280 pm8001_ha->memoryMap.region[CI+i].total_len = 4; 281 pm8001_ha->memoryMap.region[CI+i].alignment = 4; 282 283 if ((ent->driver_data) != chip_8001) { 284 /* MPI Memory region 5 inbound queues */ 285 pm8001_ha->memoryMap.region[IB+i].num_elements = 286 PM8001_MPI_QUEUE; 287 pm8001_ha->memoryMap.region[IB+i].element_size = 128; 288 pm8001_ha->memoryMap.region[IB+i].total_len = 289 PM8001_MPI_QUEUE * 128; 290 pm8001_ha->memoryMap.region[IB+i].alignment = 128; 291 } else { 292 pm8001_ha->memoryMap.region[IB+i].num_elements = 293 PM8001_MPI_QUEUE; 294 pm8001_ha->memoryMap.region[IB+i].element_size = 64; 295 pm8001_ha->memoryMap.region[IB+i].total_len = 296 PM8001_MPI_QUEUE * 64; 297 pm8001_ha->memoryMap.region[IB+i].alignment = 64; 298 } 299 } 300 301 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) { 302 /* MPI Memory region 4 for producer Index of outbound queues */ 303 pm8001_ha->memoryMap.region[PI+i].num_elements = 1; 304 pm8001_ha->memoryMap.region[PI+i].element_size = 4; 305 pm8001_ha->memoryMap.region[PI+i].total_len = 4; 306 pm8001_ha->memoryMap.region[PI+i].alignment = 4; 307 308 if (ent->driver_data != chip_8001) { 309 /* MPI Memory region 6 Outbound queues */ 310 pm8001_ha->memoryMap.region[OB+i].num_elements = 311 PM8001_MPI_QUEUE; 312 pm8001_ha->memoryMap.region[OB+i].element_size = 128; 313 pm8001_ha->memoryMap.region[OB+i].total_len = 314 PM8001_MPI_QUEUE * 128; 315 pm8001_ha->memoryMap.region[OB+i].alignment = 128; 316 } else { 317 /* MPI Memory region 6 Outbound queues */ 318 pm8001_ha->memoryMap.region[OB+i].num_elements = 319 PM8001_MPI_QUEUE; 320 pm8001_ha->memoryMap.region[OB+i].element_size = 64; 321 pm8001_ha->memoryMap.region[OB+i].total_len = 322 PM8001_MPI_QUEUE * 64; 323 pm8001_ha->memoryMap.region[OB+i].alignment = 64; 324 } 325 326 } 327 /* Memory region write DMA*/ 328 pm8001_ha->memoryMap.region[NVMD].num_elements = 1; 329 pm8001_ha->memoryMap.region[NVMD].element_size = 4096; 330 pm8001_ha->memoryMap.region[NVMD].total_len = 4096; 331 /* Memory region for devices*/ 332 pm8001_ha->memoryMap.region[DEV_MEM].num_elements = 1; 333 pm8001_ha->memoryMap.region[DEV_MEM].element_size = PM8001_MAX_DEVICES * 334 sizeof(struct pm8001_device); 335 pm8001_ha->memoryMap.region[DEV_MEM].total_len = PM8001_MAX_DEVICES * 336 sizeof(struct pm8001_device); 337 338 /* Memory region for ccb_info*/ 339 pm8001_ha->memoryMap.region[CCB_MEM].num_elements = 1; 340 pm8001_ha->memoryMap.region[CCB_MEM].element_size = PM8001_MAX_CCB * 341 sizeof(struct pm8001_ccb_info); 342 pm8001_ha->memoryMap.region[CCB_MEM].total_len = PM8001_MAX_CCB * 343 sizeof(struct pm8001_ccb_info); 344 345 /* Memory region for fw flash */ 346 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096; 347 348 pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1; 349 pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000; 350 pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000; 351 pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000; 352 for (i = 0; i < USI_MAX_MEMCNT; i++) { 353 if (pm8001_mem_alloc(pm8001_ha->pdev, 354 &pm8001_ha->memoryMap.region[i].virt_ptr, 355 &pm8001_ha->memoryMap.region[i].phys_addr, 356 &pm8001_ha->memoryMap.region[i].phys_addr_hi, 357 &pm8001_ha->memoryMap.region[i].phys_addr_lo, 358 pm8001_ha->memoryMap.region[i].total_len, 359 pm8001_ha->memoryMap.region[i].alignment) != 0) { 360 PM8001_FAIL_DBG(pm8001_ha, 361 pm8001_printk("Mem%d alloc failed\n", 362 i)); 363 goto err_out; 364 } 365 } 366 367 pm8001_ha->devices = pm8001_ha->memoryMap.region[DEV_MEM].virt_ptr; 368 for (i = 0; i < PM8001_MAX_DEVICES; i++) { 369 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED; 370 pm8001_ha->devices[i].id = i; 371 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES; 372 pm8001_ha->devices[i].running_req = 0; 373 } 374 pm8001_ha->ccb_info = pm8001_ha->memoryMap.region[CCB_MEM].virt_ptr; 375 for (i = 0; i < PM8001_MAX_CCB; i++) { 376 pm8001_ha->ccb_info[i].ccb_dma_handle = 377 pm8001_ha->memoryMap.region[CCB_MEM].phys_addr + 378 i * sizeof(struct pm8001_ccb_info); 379 pm8001_ha->ccb_info[i].task = NULL; 380 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff; 381 pm8001_ha->ccb_info[i].device = NULL; 382 ++pm8001_ha->tags_num; 383 } 384 pm8001_ha->flags = PM8001F_INIT_TIME; 385 /* Initialize tags */ 386 pm8001_tag_init(pm8001_ha); 387 return 0; 388 err_out: 389 return 1; 390 } 391 392 /** 393 * pm8001_ioremap - remap the pci high physical address to kernal virtual 394 * address so that we can access them. 395 * @pm8001_ha:our hba structure. 396 */ 397 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha) 398 { 399 u32 bar; 400 u32 logicalBar = 0; 401 struct pci_dev *pdev; 402 403 pdev = pm8001_ha->pdev; 404 /* map pci mem (PMC pci base 0-3)*/ 405 for (bar = 0; bar < 6; bar++) { 406 /* 407 ** logical BARs for SPC: 408 ** bar 0 and 1 - logical BAR0 409 ** bar 2 and 3 - logical BAR1 410 ** bar4 - logical BAR2 411 ** bar5 - logical BAR3 412 ** Skip the appropriate assignments: 413 */ 414 if ((bar == 1) || (bar == 3)) 415 continue; 416 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { 417 pm8001_ha->io_mem[logicalBar].membase = 418 pci_resource_start(pdev, bar); 419 pm8001_ha->io_mem[logicalBar].memsize = 420 pci_resource_len(pdev, bar); 421 pm8001_ha->io_mem[logicalBar].memvirtaddr = 422 ioremap(pm8001_ha->io_mem[logicalBar].membase, 423 pm8001_ha->io_mem[logicalBar].memsize); 424 PM8001_INIT_DBG(pm8001_ha, 425 pm8001_printk("PCI: bar %d, logicalBar %d ", 426 bar, logicalBar)); 427 PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 428 "base addr %llx virt_addr=%llx len=%d\n", 429 (u64)pm8001_ha->io_mem[logicalBar].membase, 430 (u64)(unsigned long) 431 pm8001_ha->io_mem[logicalBar].memvirtaddr, 432 pm8001_ha->io_mem[logicalBar].memsize)); 433 } else { 434 pm8001_ha->io_mem[logicalBar].membase = 0; 435 pm8001_ha->io_mem[logicalBar].memsize = 0; 436 pm8001_ha->io_mem[logicalBar].memvirtaddr = 0; 437 } 438 logicalBar++; 439 } 440 return 0; 441 } 442 443 /** 444 * pm8001_pci_alloc - initialize our ha card structure 445 * @pdev: pci device. 446 * @ent: ent 447 * @shost: scsi host struct which has been initialized before. 448 */ 449 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev, 450 const struct pci_device_id *ent, 451 struct Scsi_Host *shost) 452 453 { 454 struct pm8001_hba_info *pm8001_ha; 455 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 456 int j; 457 458 pm8001_ha = sha->lldd_ha; 459 if (!pm8001_ha) 460 return NULL; 461 462 pm8001_ha->pdev = pdev; 463 pm8001_ha->dev = &pdev->dev; 464 pm8001_ha->chip_id = ent->driver_data; 465 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id]; 466 pm8001_ha->irq = pdev->irq; 467 pm8001_ha->sas = sha; 468 pm8001_ha->shost = shost; 469 pm8001_ha->id = pm8001_id++; 470 pm8001_ha->logging_level = 0x01; 471 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id); 472 /* IOMB size is 128 for 8088/89 controllers */ 473 if (pm8001_ha->chip_id != chip_8001) 474 pm8001_ha->iomb_size = IOMB_SIZE_SPCV; 475 else 476 pm8001_ha->iomb_size = IOMB_SIZE_SPC; 477 478 #ifdef PM8001_USE_TASKLET 479 /* Tasklet for non msi-x interrupt handler */ 480 if ((!pdev->msix_cap || !pci_msi_enabled()) 481 || (pm8001_ha->chip_id == chip_8001)) 482 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet, 483 (unsigned long)&(pm8001_ha->irq_vector[0])); 484 else 485 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 486 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet, 487 (unsigned long)&(pm8001_ha->irq_vector[j])); 488 #endif 489 pm8001_ioremap(pm8001_ha); 490 if (!pm8001_alloc(pm8001_ha, ent)) 491 return pm8001_ha; 492 pm8001_free(pm8001_ha); 493 return NULL; 494 } 495 496 /** 497 * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit 498 * @pdev: pci device. 499 */ 500 static int pci_go_44(struct pci_dev *pdev) 501 { 502 int rc; 503 504 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(44))) { 505 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(44)); 506 if (rc) { 507 rc = pci_set_consistent_dma_mask(pdev, 508 DMA_BIT_MASK(32)); 509 if (rc) { 510 dev_printk(KERN_ERR, &pdev->dev, 511 "44-bit DMA enable failed\n"); 512 return rc; 513 } 514 } 515 } else { 516 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 517 if (rc) { 518 dev_printk(KERN_ERR, &pdev->dev, 519 "32-bit DMA enable failed\n"); 520 return rc; 521 } 522 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 523 if (rc) { 524 dev_printk(KERN_ERR, &pdev->dev, 525 "32-bit consistent DMA enable failed\n"); 526 return rc; 527 } 528 } 529 return rc; 530 } 531 532 /** 533 * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them. 534 * @shost: scsi host which has been allocated outside. 535 * @chip_info: our ha struct. 536 */ 537 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost, 538 const struct pm8001_chip_info *chip_info) 539 { 540 int phy_nr, port_nr; 541 struct asd_sas_phy **arr_phy; 542 struct asd_sas_port **arr_port; 543 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 544 545 phy_nr = chip_info->n_phy; 546 port_nr = phy_nr; 547 memset(sha, 0x00, sizeof(*sha)); 548 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL); 549 if (!arr_phy) 550 goto exit; 551 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL); 552 if (!arr_port) 553 goto exit_free2; 554 555 sha->sas_phy = arr_phy; 556 sha->sas_port = arr_port; 557 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL); 558 if (!sha->lldd_ha) 559 goto exit_free1; 560 561 shost->transportt = pm8001_stt; 562 shost->max_id = PM8001_MAX_DEVICES; 563 shost->max_lun = 8; 564 shost->max_channel = 0; 565 shost->unique_id = pm8001_id; 566 shost->max_cmd_len = 16; 567 shost->can_queue = PM8001_CAN_QUEUE; 568 shost->cmd_per_lun = 32; 569 return 0; 570 exit_free1: 571 kfree(arr_port); 572 exit_free2: 573 kfree(arr_phy); 574 exit: 575 return -1; 576 } 577 578 /** 579 * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas 580 * @shost: scsi host which has been allocated outside 581 * @chip_info: our ha struct. 582 */ 583 static void pm8001_post_sas_ha_init(struct Scsi_Host *shost, 584 const struct pm8001_chip_info *chip_info) 585 { 586 int i = 0; 587 struct pm8001_hba_info *pm8001_ha; 588 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 589 590 pm8001_ha = sha->lldd_ha; 591 for (i = 0; i < chip_info->n_phy; i++) { 592 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy; 593 sha->sas_port[i] = &pm8001_ha->port[i].sas_port; 594 sha->sas_phy[i]->sas_addr = 595 (u8 *)&pm8001_ha->phy[i].dev_sas_addr; 596 } 597 sha->sas_ha_name = DRV_NAME; 598 sha->dev = pm8001_ha->dev; 599 sha->strict_wide_ports = 1; 600 sha->lldd_module = THIS_MODULE; 601 sha->sas_addr = &pm8001_ha->sas_addr[0]; 602 sha->num_phys = chip_info->n_phy; 603 sha->core.shost = shost; 604 } 605 606 /** 607 * pm8001_init_sas_add - initialize sas address 608 * @chip_info: our ha struct. 609 * 610 * Currently we just set the fixed SAS address to our HBA,for manufacture, 611 * it should read from the EEPROM 612 */ 613 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha) 614 { 615 u8 i, j; 616 u8 sas_add[8]; 617 #ifdef PM8001_READ_VPD 618 /* For new SPC controllers WWN is stored in flash vpd 619 * For SPC/SPCve controllers WWN is stored in EEPROM 620 * For Older SPC WWN is stored in NVMD 621 */ 622 DECLARE_COMPLETION_ONSTACK(completion); 623 struct pm8001_ioctl_payload payload; 624 u16 deviceid; 625 int rc; 626 627 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid); 628 pm8001_ha->nvmd_completion = &completion; 629 630 if (pm8001_ha->chip_id == chip_8001) { 631 if (deviceid == 0x8081 || deviceid == 0x0042) { 632 payload.minor_function = 4; 633 payload.length = 4096; 634 } else { 635 payload.minor_function = 0; 636 payload.length = 128; 637 } 638 } else if ((pm8001_ha->chip_id == chip_8070 || 639 pm8001_ha->chip_id == chip_8072) && 640 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) { 641 payload.minor_function = 4; 642 payload.length = 4096; 643 } else { 644 payload.minor_function = 1; 645 payload.length = 4096; 646 } 647 payload.offset = 0; 648 payload.func_specific = kzalloc(payload.length, GFP_KERNEL); 649 if (!payload.func_specific) { 650 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("mem alloc fail\n")); 651 return; 652 } 653 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload); 654 if (rc) { 655 kfree(payload.func_specific); 656 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n")); 657 return; 658 } 659 wait_for_completion(&completion); 660 661 for (i = 0, j = 0; i <= 7; i++, j++) { 662 if (pm8001_ha->chip_id == chip_8001) { 663 if (deviceid == 0x8081) 664 pm8001_ha->sas_addr[j] = 665 payload.func_specific[0x704 + i]; 666 else if (deviceid == 0x0042) 667 pm8001_ha->sas_addr[j] = 668 payload.func_specific[0x010 + i]; 669 } else if ((pm8001_ha->chip_id == chip_8070 || 670 pm8001_ha->chip_id == chip_8072) && 671 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) { 672 pm8001_ha->sas_addr[j] = 673 payload.func_specific[0x010 + i]; 674 } else 675 pm8001_ha->sas_addr[j] = 676 payload.func_specific[0x804 + i]; 677 } 678 memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE); 679 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 680 if (i && ((i % 4) == 0)) 681 sas_add[7] = sas_add[7] + 4; 682 memcpy(&pm8001_ha->phy[i].dev_sas_addr, 683 sas_add, SAS_ADDR_SIZE); 684 PM8001_INIT_DBG(pm8001_ha, 685 pm8001_printk("phy %d sas_addr = %016llx\n", i, 686 pm8001_ha->phy[i].dev_sas_addr)); 687 } 688 kfree(payload.func_specific); 689 #else 690 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 691 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL; 692 pm8001_ha->phy[i].dev_sas_addr = 693 cpu_to_be64((u64) 694 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr)); 695 } 696 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr, 697 SAS_ADDR_SIZE); 698 #endif 699 } 700 701 /* 702 * pm8001_get_phy_settings_info : Read phy setting values. 703 * @pm8001_ha : our hba. 704 */ 705 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha) 706 { 707 708 #ifdef PM8001_READ_VPD 709 /*OPTION ROM FLASH read for the SPC cards */ 710 DECLARE_COMPLETION_ONSTACK(completion); 711 struct pm8001_ioctl_payload payload; 712 int rc; 713 714 pm8001_ha->nvmd_completion = &completion; 715 /* SAS ADDRESS read from flash / EEPROM */ 716 payload.minor_function = 6; 717 payload.offset = 0; 718 payload.length = 4096; 719 payload.func_specific = kzalloc(4096, GFP_KERNEL); 720 if (!payload.func_specific) 721 return -ENOMEM; 722 /* Read phy setting values from flash */ 723 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload); 724 if (rc) { 725 kfree(payload.func_specific); 726 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n")); 727 return -ENOMEM; 728 } 729 wait_for_completion(&completion); 730 pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific); 731 kfree(payload.func_specific); 732 #endif 733 return 0; 734 } 735 736 struct pm8001_mpi3_phy_pg_trx_config { 737 u32 LaneLosCfg; 738 u32 LanePgaCfg1; 739 u32 LanePisoCfg1; 740 u32 LanePisoCfg2; 741 u32 LanePisoCfg3; 742 u32 LanePisoCfg4; 743 u32 LanePisoCfg5; 744 u32 LanePisoCfg6; 745 u32 LaneBctCtrl; 746 }; 747 748 /** 749 * pm8001_get_internal_phy_settings : Retrieves the internal PHY settings 750 * @pm8001_ha : our adapter 751 * @phycfg : PHY config page to populate 752 */ 753 static 754 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha, 755 struct pm8001_mpi3_phy_pg_trx_config *phycfg) 756 { 757 phycfg->LaneLosCfg = 0x00000132; 758 phycfg->LanePgaCfg1 = 0x00203949; 759 phycfg->LanePisoCfg1 = 0x000000FF; 760 phycfg->LanePisoCfg2 = 0xFF000001; 761 phycfg->LanePisoCfg3 = 0xE7011300; 762 phycfg->LanePisoCfg4 = 0x631C40C0; 763 phycfg->LanePisoCfg5 = 0xF8102036; 764 phycfg->LanePisoCfg6 = 0xF74A1000; 765 phycfg->LaneBctCtrl = 0x00FB33F8; 766 } 767 768 /** 769 * pm8001_get_external_phy_settings : Retrieves the external PHY settings 770 * @pm8001_ha : our adapter 771 * @phycfg : PHY config page to populate 772 */ 773 static 774 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha, 775 struct pm8001_mpi3_phy_pg_trx_config *phycfg) 776 { 777 phycfg->LaneLosCfg = 0x00000132; 778 phycfg->LanePgaCfg1 = 0x00203949; 779 phycfg->LanePisoCfg1 = 0x000000FF; 780 phycfg->LanePisoCfg2 = 0xFF000001; 781 phycfg->LanePisoCfg3 = 0xE7011300; 782 phycfg->LanePisoCfg4 = 0x63349140; 783 phycfg->LanePisoCfg5 = 0xF8102036; 784 phycfg->LanePisoCfg6 = 0xF80D9300; 785 phycfg->LaneBctCtrl = 0x00FB33F8; 786 } 787 788 /** 789 * pm8001_get_phy_mask : Retrieves the mask that denotes if a PHY is int/ext 790 * @pm8001_ha : our adapter 791 * @phymask : The PHY mask 792 */ 793 static 794 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask) 795 { 796 switch (pm8001_ha->pdev->subsystem_device) { 797 case 0x0070: /* H1280 - 8 external 0 internal */ 798 case 0x0072: /* H12F0 - 16 external 0 internal */ 799 *phymask = 0x0000; 800 break; 801 802 case 0x0071: /* H1208 - 0 external 8 internal */ 803 case 0x0073: /* H120F - 0 external 16 internal */ 804 *phymask = 0xFFFF; 805 break; 806 807 case 0x0080: /* H1244 - 4 external 4 internal */ 808 *phymask = 0x00F0; 809 break; 810 811 case 0x0081: /* H1248 - 4 external 8 internal */ 812 *phymask = 0x0FF0; 813 break; 814 815 case 0x0082: /* H1288 - 8 external 8 internal */ 816 *phymask = 0xFF00; 817 break; 818 819 default: 820 PM8001_INIT_DBG(pm8001_ha, 821 pm8001_printk("Unknown subsystem device=0x%.04x", 822 pm8001_ha->pdev->subsystem_device)); 823 } 824 } 825 826 /** 827 * pm8001_set_phy_settings_ven_117c_12Gb : Configure ATTO 12Gb PHY settings 828 * @pm8001_ha : our adapter 829 */ 830 static 831 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha) 832 { 833 struct pm8001_mpi3_phy_pg_trx_config phycfg_int; 834 struct pm8001_mpi3_phy_pg_trx_config phycfg_ext; 835 int phymask = 0; 836 int i = 0; 837 838 memset(&phycfg_int, 0, sizeof(phycfg_int)); 839 memset(&phycfg_ext, 0, sizeof(phycfg_ext)); 840 841 pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int); 842 pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext); 843 pm8001_get_phy_mask(pm8001_ha, &phymask); 844 845 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 846 if (phymask & (1 << i)) {/* Internal PHY */ 847 pm8001_set_phy_profile_single(pm8001_ha, i, 848 sizeof(phycfg_int) / sizeof(u32), 849 (u32 *)&phycfg_int); 850 851 } else { /* External PHY */ 852 pm8001_set_phy_profile_single(pm8001_ha, i, 853 sizeof(phycfg_ext) / sizeof(u32), 854 (u32 *)&phycfg_ext); 855 } 856 } 857 858 return 0; 859 } 860 861 /** 862 * pm8001_configure_phy_settings : Configures PHY settings based on vendor ID. 863 * @pm8001_ha : our hba. 864 */ 865 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha) 866 { 867 switch (pm8001_ha->pdev->subsystem_vendor) { 868 case PCI_VENDOR_ID_ATTO: 869 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */ 870 return 0; 871 else 872 return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha); 873 874 case PCI_VENDOR_ID_ADAPTEC2: 875 case 0: 876 return 0; 877 878 default: 879 return pm8001_get_phy_settings_info(pm8001_ha); 880 } 881 } 882 883 #ifdef PM8001_USE_MSIX 884 /** 885 * pm8001_setup_msix - enable MSI-X interrupt 886 * @chip_info: our ha struct. 887 * @irq_handler: irq_handler 888 */ 889 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha) 890 { 891 u32 i = 0, j = 0; 892 u32 number_of_intr; 893 int flag = 0; 894 int rc; 895 static char intr_drvname[PM8001_MAX_MSIX_VEC][sizeof(DRV_NAME)+3]; 896 897 /* SPCv controllers supports 64 msi-x */ 898 if (pm8001_ha->chip_id == chip_8001) { 899 number_of_intr = 1; 900 } else { 901 number_of_intr = PM8001_MAX_MSIX_VEC; 902 flag &= ~IRQF_SHARED; 903 } 904 905 rc = pci_alloc_irq_vectors(pm8001_ha->pdev, number_of_intr, 906 number_of_intr, PCI_IRQ_MSIX); 907 if (rc < 0) 908 return rc; 909 pm8001_ha->number_of_intr = number_of_intr; 910 911 PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 912 "pci_alloc_irq_vectors request ret:%d no of intr %d\n", 913 rc, pm8001_ha->number_of_intr)); 914 915 for (i = 0; i < number_of_intr; i++) { 916 snprintf(intr_drvname[i], sizeof(intr_drvname[0]), 917 DRV_NAME"%d", i); 918 pm8001_ha->irq_vector[i].irq_id = i; 919 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha; 920 921 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i), 922 pm8001_interrupt_handler_msix, flag, 923 intr_drvname[i], &(pm8001_ha->irq_vector[i])); 924 if (rc) { 925 for (j = 0; j < i; j++) { 926 free_irq(pci_irq_vector(pm8001_ha->pdev, i), 927 &(pm8001_ha->irq_vector[i])); 928 } 929 pci_free_irq_vectors(pm8001_ha->pdev); 930 break; 931 } 932 } 933 934 return rc; 935 } 936 #endif 937 938 /** 939 * pm8001_request_irq - register interrupt 940 * @chip_info: our ha struct. 941 */ 942 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha) 943 { 944 struct pci_dev *pdev; 945 int rc; 946 947 pdev = pm8001_ha->pdev; 948 949 #ifdef PM8001_USE_MSIX 950 if (pdev->msix_cap && pci_msi_enabled()) 951 return pm8001_setup_msix(pm8001_ha); 952 else { 953 PM8001_INIT_DBG(pm8001_ha, 954 pm8001_printk("MSIX not supported!!!\n")); 955 goto intx; 956 } 957 #endif 958 959 intx: 960 /* initialize the INT-X interrupt */ 961 pm8001_ha->irq_vector[0].irq_id = 0; 962 pm8001_ha->irq_vector[0].drv_inst = pm8001_ha; 963 rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED, 964 DRV_NAME, SHOST_TO_SAS_HA(pm8001_ha->shost)); 965 return rc; 966 } 967 968 /** 969 * pm8001_pci_probe - probe supported device 970 * @pdev: pci device which kernel has been prepared for. 971 * @ent: pci device id 972 * 973 * This function is the main initialization function, when register a new 974 * pci driver it is invoked, all struct an hardware initilization should be done 975 * here, also, register interrupt 976 */ 977 static int pm8001_pci_probe(struct pci_dev *pdev, 978 const struct pci_device_id *ent) 979 { 980 unsigned int rc; 981 u32 pci_reg; 982 u8 i = 0; 983 struct pm8001_hba_info *pm8001_ha; 984 struct Scsi_Host *shost = NULL; 985 const struct pm8001_chip_info *chip; 986 987 dev_printk(KERN_INFO, &pdev->dev, 988 "pm80xx: driver version %s\n", DRV_VERSION); 989 rc = pci_enable_device(pdev); 990 if (rc) 991 goto err_out_enable; 992 pci_set_master(pdev); 993 /* 994 * Enable pci slot busmaster by setting pci command register. 995 * This is required by FW for Cyclone card. 996 */ 997 998 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg); 999 pci_reg |= 0x157; 1000 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg); 1001 rc = pci_request_regions(pdev, DRV_NAME); 1002 if (rc) 1003 goto err_out_disable; 1004 rc = pci_go_44(pdev); 1005 if (rc) 1006 goto err_out_regions; 1007 1008 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *)); 1009 if (!shost) { 1010 rc = -ENOMEM; 1011 goto err_out_regions; 1012 } 1013 chip = &pm8001_chips[ent->driver_data]; 1014 SHOST_TO_SAS_HA(shost) = 1015 kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL); 1016 if (!SHOST_TO_SAS_HA(shost)) { 1017 rc = -ENOMEM; 1018 goto err_out_free_host; 1019 } 1020 1021 rc = pm8001_prep_sas_ha_init(shost, chip); 1022 if (rc) { 1023 rc = -ENOMEM; 1024 goto err_out_free; 1025 } 1026 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost)); 1027 /* ent->driver variable is used to differentiate between controllers */ 1028 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost); 1029 if (!pm8001_ha) { 1030 rc = -ENOMEM; 1031 goto err_out_free; 1032 } 1033 list_add_tail(&pm8001_ha->list, &hba_list); 1034 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1035 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); 1036 if (rc) { 1037 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 1038 "chip_init failed [ret: %d]\n", rc)); 1039 goto err_out_ha_free; 1040 } 1041 1042 rc = scsi_add_host(shost, &pdev->dev); 1043 if (rc) 1044 goto err_out_ha_free; 1045 rc = pm8001_request_irq(pm8001_ha); 1046 if (rc) { 1047 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 1048 "pm8001_request_irq failed [ret: %d]\n", rc)); 1049 goto err_out_shost; 1050 } 1051 1052 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0); 1053 if (pm8001_ha->chip_id != chip_8001) { 1054 for (i = 1; i < pm8001_ha->number_of_intr; i++) 1055 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i); 1056 /* setup thermal configuration. */ 1057 pm80xx_set_thermal_config(pm8001_ha); 1058 } 1059 1060 pm8001_init_sas_add(pm8001_ha); 1061 /* phy setting support for motherboard controller */ 1062 if (pm8001_configure_phy_settings(pm8001_ha)) 1063 goto err_out_shost; 1064 1065 pm8001_post_sas_ha_init(shost, chip); 1066 rc = sas_register_ha(SHOST_TO_SAS_HA(shost)); 1067 if (rc) 1068 goto err_out_shost; 1069 scsi_scan_host(pm8001_ha->shost); 1070 return 0; 1071 1072 err_out_shost: 1073 scsi_remove_host(pm8001_ha->shost); 1074 err_out_ha_free: 1075 pm8001_free(pm8001_ha); 1076 err_out_free: 1077 kfree(SHOST_TO_SAS_HA(shost)); 1078 err_out_free_host: 1079 scsi_host_put(shost); 1080 err_out_regions: 1081 pci_release_regions(pdev); 1082 err_out_disable: 1083 pci_disable_device(pdev); 1084 err_out_enable: 1085 return rc; 1086 } 1087 1088 static void pm8001_pci_remove(struct pci_dev *pdev) 1089 { 1090 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1091 struct pm8001_hba_info *pm8001_ha; 1092 int i, j; 1093 pm8001_ha = sha->lldd_ha; 1094 sas_unregister_ha(sha); 1095 sas_remove_host(pm8001_ha->shost); 1096 list_del(&pm8001_ha->list); 1097 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1098 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1099 1100 #ifdef PM8001_USE_MSIX 1101 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1102 synchronize_irq(pci_irq_vector(pdev, i)); 1103 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1104 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]); 1105 pci_free_irq_vectors(pdev); 1106 #else 1107 free_irq(pm8001_ha->irq, sha); 1108 #endif 1109 #ifdef PM8001_USE_TASKLET 1110 /* For non-msix and msix interrupts */ 1111 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1112 (pm8001_ha->chip_id == chip_8001)) 1113 tasklet_kill(&pm8001_ha->tasklet[0]); 1114 else 1115 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1116 tasklet_kill(&pm8001_ha->tasklet[j]); 1117 #endif 1118 scsi_host_put(pm8001_ha->shost); 1119 pm8001_free(pm8001_ha); 1120 kfree(sha->sas_phy); 1121 kfree(sha->sas_port); 1122 kfree(sha); 1123 pci_release_regions(pdev); 1124 pci_disable_device(pdev); 1125 } 1126 1127 /** 1128 * pm8001_pci_suspend - power management suspend main entry point 1129 * @pdev: PCI device struct 1130 * @state: PM state change to (usually PCI_D3) 1131 * 1132 * Returns 0 success, anything else error. 1133 */ 1134 static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1135 { 1136 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1137 struct pm8001_hba_info *pm8001_ha; 1138 int i, j; 1139 u32 device_state; 1140 pm8001_ha = sha->lldd_ha; 1141 sas_suspend_ha(sha); 1142 flush_workqueue(pm8001_wq); 1143 scsi_block_requests(pm8001_ha->shost); 1144 if (!pdev->pm_cap) { 1145 dev_err(&pdev->dev, " PCI PM not supported\n"); 1146 return -ENODEV; 1147 } 1148 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1149 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1150 #ifdef PM8001_USE_MSIX 1151 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1152 synchronize_irq(pci_irq_vector(pdev, i)); 1153 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1154 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]); 1155 pci_free_irq_vectors(pdev); 1156 #else 1157 free_irq(pm8001_ha->irq, sha); 1158 #endif 1159 #ifdef PM8001_USE_TASKLET 1160 /* For non-msix and msix interrupts */ 1161 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1162 (pm8001_ha->chip_id == chip_8001)) 1163 tasklet_kill(&pm8001_ha->tasklet[0]); 1164 else 1165 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1166 tasklet_kill(&pm8001_ha->tasklet[j]); 1167 #endif 1168 device_state = pci_choose_state(pdev, state); 1169 pm8001_printk("pdev=0x%p, slot=%s, entering " 1170 "operating state [D%d]\n", pdev, 1171 pm8001_ha->name, device_state); 1172 pci_save_state(pdev); 1173 pci_disable_device(pdev); 1174 pci_set_power_state(pdev, device_state); 1175 return 0; 1176 } 1177 1178 /** 1179 * pm8001_pci_resume - power management resume main entry point 1180 * @pdev: PCI device struct 1181 * 1182 * Returns 0 success, anything else error. 1183 */ 1184 static int pm8001_pci_resume(struct pci_dev *pdev) 1185 { 1186 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1187 struct pm8001_hba_info *pm8001_ha; 1188 int rc; 1189 u8 i = 0, j; 1190 u32 device_state; 1191 DECLARE_COMPLETION_ONSTACK(completion); 1192 pm8001_ha = sha->lldd_ha; 1193 device_state = pdev->current_state; 1194 1195 pm8001_printk("pdev=0x%p, slot=%s, resuming from previous " 1196 "operating state [D%d]\n", pdev, pm8001_ha->name, device_state); 1197 1198 pci_set_power_state(pdev, PCI_D0); 1199 pci_enable_wake(pdev, PCI_D0, 0); 1200 pci_restore_state(pdev); 1201 rc = pci_enable_device(pdev); 1202 if (rc) { 1203 pm8001_printk("slot=%s Enable device failed during resume\n", 1204 pm8001_ha->name); 1205 goto err_out_enable; 1206 } 1207 1208 pci_set_master(pdev); 1209 rc = pci_go_44(pdev); 1210 if (rc) 1211 goto err_out_disable; 1212 sas_prep_resume_ha(sha); 1213 /* chip soft rst only for spc */ 1214 if (pm8001_ha->chip_id == chip_8001) { 1215 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1216 PM8001_INIT_DBG(pm8001_ha, 1217 pm8001_printk("chip soft reset successful\n")); 1218 } 1219 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); 1220 if (rc) 1221 goto err_out_disable; 1222 1223 /* disable all the interrupt bits */ 1224 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1225 1226 rc = pm8001_request_irq(pm8001_ha); 1227 if (rc) 1228 goto err_out_disable; 1229 #ifdef PM8001_USE_TASKLET 1230 /* Tasklet for non msi-x interrupt handler */ 1231 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1232 (pm8001_ha->chip_id == chip_8001)) 1233 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet, 1234 (unsigned long)&(pm8001_ha->irq_vector[0])); 1235 else 1236 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1237 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet, 1238 (unsigned long)&(pm8001_ha->irq_vector[j])); 1239 #endif 1240 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0); 1241 if (pm8001_ha->chip_id != chip_8001) { 1242 for (i = 1; i < pm8001_ha->number_of_intr; i++) 1243 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i); 1244 } 1245 1246 /* Chip documentation for the 8070 and 8072 SPCv */ 1247 /* states that a 500ms minimum delay is required */ 1248 /* before issuing commands. Otherwise, the firmware */ 1249 /* will enter an unrecoverable state. */ 1250 1251 if (pm8001_ha->chip_id == chip_8070 || 1252 pm8001_ha->chip_id == chip_8072) { 1253 mdelay(500); 1254 } 1255 1256 /* Spin up the PHYs */ 1257 1258 pm8001_ha->flags = PM8001F_RUN_TIME; 1259 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 1260 pm8001_ha->phy[i].enable_completion = &completion; 1261 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i); 1262 wait_for_completion(&completion); 1263 } 1264 sas_resume_ha(sha); 1265 return 0; 1266 1267 err_out_disable: 1268 scsi_remove_host(pm8001_ha->shost); 1269 pci_disable_device(pdev); 1270 err_out_enable: 1271 return rc; 1272 } 1273 1274 /* update of pci device, vendor id and driver data with 1275 * unique value for each of the controller 1276 */ 1277 static struct pci_device_id pm8001_pci_table[] = { 1278 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 }, 1279 { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 }, 1280 { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 }, 1281 { PCI_VDEVICE(ATTO, 0x0042), chip_8001 }, 1282 /* Support for SPC/SPCv/SPCve controllers */ 1283 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 }, 1284 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 }, 1285 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 }, 1286 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 }, 1287 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 }, 1288 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 }, 1289 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 }, 1290 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 }, 1291 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 }, 1292 { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 }, 1293 { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 }, 1294 { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 }, 1295 { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 }, 1296 { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 }, 1297 { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 }, 1298 { PCI_VENDOR_ID_ADAPTEC2, 0x8081, 1299 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 }, 1300 { PCI_VENDOR_ID_ADAPTEC2, 0x8081, 1301 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 }, 1302 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1303 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 }, 1304 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1305 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 }, 1306 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1307 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 }, 1308 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1309 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 }, 1310 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1311 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 }, 1312 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1313 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 }, 1314 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1315 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 }, 1316 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1317 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 }, 1318 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1319 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 }, 1320 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1321 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 }, 1322 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1323 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 }, 1324 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1325 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 }, 1326 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1327 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 }, 1328 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1329 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 }, 1330 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1331 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 }, 1332 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1333 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 }, 1334 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1335 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 }, 1336 { PCI_VENDOR_ID_ATTO, 0x8070, 1337 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 }, 1338 { PCI_VENDOR_ID_ATTO, 0x8070, 1339 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 }, 1340 { PCI_VENDOR_ID_ATTO, 0x8072, 1341 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 }, 1342 { PCI_VENDOR_ID_ATTO, 0x8072, 1343 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 }, 1344 { PCI_VENDOR_ID_ATTO, 0x8070, 1345 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 }, 1346 { PCI_VENDOR_ID_ATTO, 0x8072, 1347 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 }, 1348 { PCI_VENDOR_ID_ATTO, 0x8072, 1349 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 }, 1350 {} /* terminate list */ 1351 }; 1352 1353 static struct pci_driver pm8001_pci_driver = { 1354 .name = DRV_NAME, 1355 .id_table = pm8001_pci_table, 1356 .probe = pm8001_pci_probe, 1357 .remove = pm8001_pci_remove, 1358 .suspend = pm8001_pci_suspend, 1359 .resume = pm8001_pci_resume, 1360 }; 1361 1362 /** 1363 * pm8001_init - initialize scsi transport template 1364 */ 1365 static int __init pm8001_init(void) 1366 { 1367 int rc = -ENOMEM; 1368 1369 pm8001_wq = alloc_workqueue("pm80xx", 0, 0); 1370 if (!pm8001_wq) 1371 goto err; 1372 1373 pm8001_id = 0; 1374 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops); 1375 if (!pm8001_stt) 1376 goto err_wq; 1377 rc = pci_register_driver(&pm8001_pci_driver); 1378 if (rc) 1379 goto err_tp; 1380 return 0; 1381 1382 err_tp: 1383 sas_release_transport(pm8001_stt); 1384 err_wq: 1385 destroy_workqueue(pm8001_wq); 1386 err: 1387 return rc; 1388 } 1389 1390 static void __exit pm8001_exit(void) 1391 { 1392 pci_unregister_driver(&pm8001_pci_driver); 1393 sas_release_transport(pm8001_stt); 1394 destroy_workqueue(pm8001_wq); 1395 } 1396 1397 module_init(pm8001_init); 1398 module_exit(pm8001_exit); 1399 1400 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>"); 1401 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>"); 1402 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>"); 1403 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>"); 1404 MODULE_DESCRIPTION( 1405 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 " 1406 "SAS/SATA controller driver"); 1407 MODULE_VERSION(DRV_VERSION); 1408 MODULE_LICENSE("GPL"); 1409 MODULE_DEVICE_TABLE(pci, pm8001_pci_table); 1410 1411