1dbf9bfe6Sjack wang /* 2e5742101SSakthivel K * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver 3dbf9bfe6Sjack wang * 4dbf9bfe6Sjack wang * Copyright (c) 2008-2009 USI Co., Ltd. 5dbf9bfe6Sjack wang * All rights reserved. 6dbf9bfe6Sjack wang * 7dbf9bfe6Sjack wang * Redistribution and use in source and binary forms, with or without 8dbf9bfe6Sjack wang * modification, are permitted provided that the following conditions 9dbf9bfe6Sjack wang * are met: 10dbf9bfe6Sjack wang * 1. Redistributions of source code must retain the above copyright 11dbf9bfe6Sjack wang * notice, this list of conditions, and the following disclaimer, 12dbf9bfe6Sjack wang * without modification. 13dbf9bfe6Sjack wang * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14dbf9bfe6Sjack wang * substantially similar to the "NO WARRANTY" disclaimer below 15dbf9bfe6Sjack wang * ("Disclaimer") and any redistribution must be conditioned upon 16dbf9bfe6Sjack wang * including a substantially similar Disclaimer requirement for further 17dbf9bfe6Sjack wang * binary redistribution. 18dbf9bfe6Sjack wang * 3. Neither the names of the above-listed copyright holders nor the names 19dbf9bfe6Sjack wang * of any contributors may be used to endorse or promote products derived 20dbf9bfe6Sjack wang * from this software without specific prior written permission. 21dbf9bfe6Sjack wang * 22dbf9bfe6Sjack wang * Alternatively, this software may be distributed under the terms of the 23dbf9bfe6Sjack wang * GNU General Public License ("GPL") version 2 as published by the Free 24dbf9bfe6Sjack wang * Software Foundation. 25dbf9bfe6Sjack wang * 26dbf9bfe6Sjack wang * NO WARRANTY 27dbf9bfe6Sjack wang * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28dbf9bfe6Sjack wang * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29dbf9bfe6Sjack wang * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30dbf9bfe6Sjack wang * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31dbf9bfe6Sjack wang * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32dbf9bfe6Sjack wang * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33dbf9bfe6Sjack wang * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34dbf9bfe6Sjack wang * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35dbf9bfe6Sjack wang * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36dbf9bfe6Sjack wang * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37dbf9bfe6Sjack wang * POSSIBILITY OF SUCH DAMAGES. 38dbf9bfe6Sjack wang * 39dbf9bfe6Sjack wang */ 40dbf9bfe6Sjack wang 415a0e3ad6STejun Heo #include <linux/slab.h> 42dbf9bfe6Sjack wang #include "pm8001_sas.h" 43dbf9bfe6Sjack wang #include "pm8001_chips.h" 443e253d96Speter chang #include "pm80xx_hwi.h" 45dbf9bfe6Sjack wang 467370672dSpeter chang static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING; 477370672dSpeter chang module_param(logging_level, ulong, 0644); 487370672dSpeter chang MODULE_PARM_DESC(logging_level, " bits for enabling logging info."); 497370672dSpeter chang 503e253d96Speter chang static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120; 513e253d96Speter chang module_param(link_rate, ulong, 0644); 523e253d96Speter chang MODULE_PARM_DESC(link_rate, "Enable link rate.\n" 533e253d96Speter chang " 1: Link rate 1.5G\n" 543e253d96Speter chang " 2: Link rate 3.0G\n" 553e253d96Speter chang " 4: Link rate 6.0G\n" 563e253d96Speter chang " 8: Link rate 12.0G\n"); 573e253d96Speter chang 58dbf9bfe6Sjack wang static struct scsi_transport_template *pm8001_stt; 59dbf9bfe6Sjack wang 60e802fc43SLee Jones /* 61e5742101SSakthivel K * chip info structure to identify chip key functionality as 62e5742101SSakthivel K * encryption available/not, no of ports, hw specific function ref 63e5742101SSakthivel K */ 64dbf9bfe6Sjack wang static const struct pm8001_chip_info pm8001_chips[] = { 65e5742101SSakthivel K [chip_8001] = {0, 8, &pm8001_8001_dispatch,}, 66f5860992SSakthivel K [chip_8008] = {0, 8, &pm8001_80xx_dispatch,}, 67f5860992SSakthivel K [chip_8009] = {1, 8, &pm8001_80xx_dispatch,}, 68f5860992SSakthivel K [chip_8018] = {0, 16, &pm8001_80xx_dispatch,}, 69f5860992SSakthivel K [chip_8019] = {1, 16, &pm8001_80xx_dispatch,}, 70a9a923e5SAnand Kumar Santhanam [chip_8074] = {0, 8, &pm8001_80xx_dispatch,}, 71a9a923e5SAnand Kumar Santhanam [chip_8076] = {0, 16, &pm8001_80xx_dispatch,}, 72a9a923e5SAnand Kumar Santhanam [chip_8077] = {0, 16, &pm8001_80xx_dispatch,}, 73d8571b1eSSuresh Thiagarajan [chip_8006] = {0, 16, &pm8001_80xx_dispatch,}, 74db9d4034SBenjamin Rood [chip_8070] = {0, 8, &pm8001_80xx_dispatch,}, 75db9d4034SBenjamin Rood [chip_8072] = {0, 16, &pm8001_80xx_dispatch,}, 76dbf9bfe6Sjack wang }; 77dbf9bfe6Sjack wang static int pm8001_id; 78dbf9bfe6Sjack wang 79dbf9bfe6Sjack wang LIST_HEAD(hba_list); 80dbf9bfe6Sjack wang 81429305e4STejun Heo struct workqueue_struct *pm8001_wq; 82429305e4STejun Heo 83e802fc43SLee Jones /* 84dbf9bfe6Sjack wang * The main structure which LLDD must register for scsi core. 85dbf9bfe6Sjack wang */ 86dbf9bfe6Sjack wang static struct scsi_host_template pm8001_sht = { 87dbf9bfe6Sjack wang .module = THIS_MODULE, 88dbf9bfe6Sjack wang .name = DRV_NAME, 89dbf9bfe6Sjack wang .queuecommand = sas_queuecommand, 90dbf9bfe6Sjack wang .target_alloc = sas_target_alloc, 9111e16364SDan Williams .slave_configure = sas_slave_configure, 92dbf9bfe6Sjack wang .scan_finished = pm8001_scan_finished, 93dbf9bfe6Sjack wang .scan_start = pm8001_scan_start, 94dbf9bfe6Sjack wang .change_queue_depth = sas_change_queue_depth, 95dbf9bfe6Sjack wang .bios_param = sas_bios_param, 96dbf9bfe6Sjack wang .can_queue = 1, 97dbf9bfe6Sjack wang .this_id = -1, 9858bf14c1SPeter Chang .sg_tablesize = PM8001_MAX_DMA_SG, 99dbf9bfe6Sjack wang .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 100dbf9bfe6Sjack wang .eh_device_reset_handler = sas_eh_device_reset_handler, 101cc199e78SHannes Reinecke .eh_target_reset_handler = sas_eh_target_reset_handler, 102dbf9bfe6Sjack wang .target_destroy = sas_target_destroy, 103dbf9bfe6Sjack wang .ioctl = sas_ioctl, 10475c0b0e1SArnd Bergmann #ifdef CONFIG_COMPAT 10575c0b0e1SArnd Bergmann .compat_ioctl = sas_ioctl, 10675c0b0e1SArnd Bergmann #endif 107dbf9bfe6Sjack wang .shost_attrs = pm8001_host_attrs, 108c40ecc12SChristoph Hellwig .track_queue_depth = 1, 109dbf9bfe6Sjack wang }; 110dbf9bfe6Sjack wang 111e802fc43SLee Jones /* 112dbf9bfe6Sjack wang * Sas layer call this function to execute specific task. 113dbf9bfe6Sjack wang */ 114dbf9bfe6Sjack wang static struct sas_domain_function_template pm8001_transport_ops = { 115dbf9bfe6Sjack wang .lldd_dev_found = pm8001_dev_found, 116dbf9bfe6Sjack wang .lldd_dev_gone = pm8001_dev_gone, 117dbf9bfe6Sjack wang 118dbf9bfe6Sjack wang .lldd_execute_task = pm8001_queue_command, 119dbf9bfe6Sjack wang .lldd_control_phy = pm8001_phy_control, 120dbf9bfe6Sjack wang 121dbf9bfe6Sjack wang .lldd_abort_task = pm8001_abort_task, 122dbf9bfe6Sjack wang .lldd_abort_task_set = pm8001_abort_task_set, 123dbf9bfe6Sjack wang .lldd_clear_aca = pm8001_clear_aca, 124dbf9bfe6Sjack wang .lldd_clear_task_set = pm8001_clear_task_set, 125dbf9bfe6Sjack wang .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset, 126dbf9bfe6Sjack wang .lldd_lu_reset = pm8001_lu_reset, 127dbf9bfe6Sjack wang .lldd_query_task = pm8001_query_task, 128dbf9bfe6Sjack wang }; 129dbf9bfe6Sjack wang 130dbf9bfe6Sjack wang /** 131dbf9bfe6Sjack wang * pm8001_phy_init - initiate our adapter phys 132dbf9bfe6Sjack wang * @pm8001_ha: our hba structure. 133dbf9bfe6Sjack wang * @phy_id: phy id. 134dbf9bfe6Sjack wang */ 1356f039790SGreg Kroah-Hartman static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id) 136dbf9bfe6Sjack wang { 137dbf9bfe6Sjack wang struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 138dbf9bfe6Sjack wang struct asd_sas_phy *sas_phy = &phy->sas_phy; 139cd135754SDeepak Ukey phy->phy_state = PHY_LINK_DISABLE; 140dbf9bfe6Sjack wang phy->pm8001_ha = pm8001_ha; 141dbf9bfe6Sjack wang sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0; 142dbf9bfe6Sjack wang sas_phy->class = SAS; 143dbf9bfe6Sjack wang sas_phy->iproto = SAS_PROTOCOL_ALL; 144dbf9bfe6Sjack wang sas_phy->tproto = 0; 145dbf9bfe6Sjack wang sas_phy->type = PHY_TYPE_PHYSICAL; 146dbf9bfe6Sjack wang sas_phy->role = PHY_ROLE_INITIATOR; 147dbf9bfe6Sjack wang sas_phy->oob_mode = OOB_NOT_CONNECTED; 148dbf9bfe6Sjack wang sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN; 149dbf9bfe6Sjack wang sas_phy->id = phy_id; 1506c85e4bcSViswas G sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr; 151dbf9bfe6Sjack wang sas_phy->frame_rcvd = &phy->frame_rcvd[0]; 152dbf9bfe6Sjack wang sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata; 153dbf9bfe6Sjack wang sas_phy->lldd_phy = phy; 154dbf9bfe6Sjack wang } 155dbf9bfe6Sjack wang 156dbf9bfe6Sjack wang /** 157dbf9bfe6Sjack wang * pm8001_free - free hba 158dbf9bfe6Sjack wang * @pm8001_ha: our hba structure. 159dbf9bfe6Sjack wang */ 160dbf9bfe6Sjack wang static void pm8001_free(struct pm8001_hba_info *pm8001_ha) 161dbf9bfe6Sjack wang { 162dbf9bfe6Sjack wang int i; 163dbf9bfe6Sjack wang 164dbf9bfe6Sjack wang if (!pm8001_ha) 165dbf9bfe6Sjack wang return; 166dbf9bfe6Sjack wang 167dbf9bfe6Sjack wang for (i = 0; i < USI_MAX_MEMCNT; i++) { 168dbf9bfe6Sjack wang if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) { 169f73bdebdSChristoph Hellwig dma_free_coherent(&pm8001_ha->pdev->dev, 170bfb4809fSSakthivel K (pm8001_ha->memoryMap.region[i].total_len + 171bfb4809fSSakthivel K pm8001_ha->memoryMap.region[i].alignment), 172dbf9bfe6Sjack wang pm8001_ha->memoryMap.region[i].virt_ptr, 173dbf9bfe6Sjack wang pm8001_ha->memoryMap.region[i].phys_addr); 174dbf9bfe6Sjack wang } 175dbf9bfe6Sjack wang } 176dbf9bfe6Sjack wang PM8001_CHIP_DISP->chip_iounmap(pm8001_ha); 177429305e4STejun Heo flush_workqueue(pm8001_wq); 178dbf9bfe6Sjack wang kfree(pm8001_ha->tags); 179dbf9bfe6Sjack wang kfree(pm8001_ha); 180dbf9bfe6Sjack wang } 181dbf9bfe6Sjack wang 182dbf9bfe6Sjack wang #ifdef PM8001_USE_TASKLET 1831245ee59SSakthivel K 1841245ee59SSakthivel K /** 1851245ee59SSakthivel K * tasklet for 64 msi-x interrupt handler 1861245ee59SSakthivel K * @opaque: the passed general host adapter struct 1871245ee59SSakthivel K * Note: pm8001_tasklet is common for pm8001 & pm80xx 1881245ee59SSakthivel K */ 189dbf9bfe6Sjack wang static void pm8001_tasklet(unsigned long opaque) 190dbf9bfe6Sjack wang { 191dbf9bfe6Sjack wang struct pm8001_hba_info *pm8001_ha; 1926cd60b37SNikith Ganigarakoppal struct isr_param *irq_vector; 1936cd60b37SNikith Ganigarakoppal 1946cd60b37SNikith Ganigarakoppal irq_vector = (struct isr_param *)opaque; 1956cd60b37SNikith Ganigarakoppal pm8001_ha = irq_vector->drv_inst; 196dbf9bfe6Sjack wang if (unlikely(!pm8001_ha)) 197dbf9bfe6Sjack wang BUG_ON(1); 1986cd60b37SNikith Ganigarakoppal PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id); 199dbf9bfe6Sjack wang } 200dbf9bfe6Sjack wang #endif 201dbf9bfe6Sjack wang 202dbf9bfe6Sjack wang /** 2031245ee59SSakthivel K * pm8001_interrupt_handler_msix - main MSIX interrupt handler. 2041245ee59SSakthivel K * It obtains the vector number and calls the equivalent bottom 2051245ee59SSakthivel K * half or services directly. 206e802fc43SLee Jones * @irq: interrupt number 2071245ee59SSakthivel K * @opaque: the passed outbound queue/vector. Host structure is 2081245ee59SSakthivel K * retrieved from the same. 209dbf9bfe6Sjack wang */ 2101245ee59SSakthivel K static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque) 2111245ee59SSakthivel K { 2126cd60b37SNikith Ganigarakoppal struct isr_param *irq_vector; 2136cd60b37SNikith Ganigarakoppal struct pm8001_hba_info *pm8001_ha; 2141245ee59SSakthivel K irqreturn_t ret = IRQ_HANDLED; 2156cd60b37SNikith Ganigarakoppal irq_vector = (struct isr_param *)opaque; 2166cd60b37SNikith Ganigarakoppal pm8001_ha = irq_vector->drv_inst; 2176cd60b37SNikith Ganigarakoppal 2181245ee59SSakthivel K if (unlikely(!pm8001_ha)) 2191245ee59SSakthivel K return IRQ_NONE; 220f310a4eaSColin Ian King if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha)) 2211245ee59SSakthivel K return IRQ_NONE; 2221245ee59SSakthivel K #ifdef PM8001_USE_TASKLET 2236cd60b37SNikith Ganigarakoppal tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]); 2241245ee59SSakthivel K #else 2256cd60b37SNikith Ganigarakoppal ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id); 2261245ee59SSakthivel K #endif 2271245ee59SSakthivel K return ret; 2281245ee59SSakthivel K } 2291245ee59SSakthivel K 2301245ee59SSakthivel K /** 2311245ee59SSakthivel K * pm8001_interrupt_handler_intx - main INTx interrupt handler. 232e802fc43SLee Jones * @irq: interrupt number 2331245ee59SSakthivel K * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure. 2341245ee59SSakthivel K */ 2351245ee59SSakthivel K 2361245ee59SSakthivel K static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id) 237dbf9bfe6Sjack wang { 238dbf9bfe6Sjack wang struct pm8001_hba_info *pm8001_ha; 239dbf9bfe6Sjack wang irqreturn_t ret = IRQ_HANDLED; 2401245ee59SSakthivel K struct sas_ha_struct *sha = dev_id; 241dbf9bfe6Sjack wang pm8001_ha = sha->lldd_ha; 242dbf9bfe6Sjack wang if (unlikely(!pm8001_ha)) 243dbf9bfe6Sjack wang return IRQ_NONE; 244f310a4eaSColin Ian King if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha)) 245dbf9bfe6Sjack wang return IRQ_NONE; 2461245ee59SSakthivel K 247dbf9bfe6Sjack wang #ifdef PM8001_USE_TASKLET 2486cd60b37SNikith Ganigarakoppal tasklet_schedule(&pm8001_ha->tasklet[0]); 249dbf9bfe6Sjack wang #else 250f74cf271SSakthivel K ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0); 251dbf9bfe6Sjack wang #endif 252dbf9bfe6Sjack wang return ret; 253dbf9bfe6Sjack wang } 254dbf9bfe6Sjack wang 255d384be6eSVikram Auradkar static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha); 256d384be6eSVikram Auradkar static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha); 257d384be6eSVikram Auradkar 258dbf9bfe6Sjack wang /** 259dbf9bfe6Sjack wang * pm8001_alloc - initiate our hba structure and 6 DMAs area. 260dbf9bfe6Sjack wang * @pm8001_ha: our hba structure. 261e802fc43SLee Jones * @ent: PCI device ID structure to match on 262dbf9bfe6Sjack wang */ 263e590adfdSSakthivel K static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha, 264e590adfdSSakthivel K const struct pci_device_id *ent) 265dbf9bfe6Sjack wang { 266dbf9bfe6Sjack wang int i; 267dbf9bfe6Sjack wang spin_lock_init(&pm8001_ha->lock); 268646cdf00STomas Henzl spin_lock_init(&pm8001_ha->bitmap_lock); 269e590adfdSSakthivel K PM8001_INIT_DBG(pm8001_ha, 270e590adfdSSakthivel K pm8001_printk("pm8001_alloc: PHY:%x\n", 271e590adfdSSakthivel K pm8001_ha->chip->n_phy)); 2721cc943aeSjack wang for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 273dbf9bfe6Sjack wang pm8001_phy_init(pm8001_ha, i); 2741cc943aeSjack wang pm8001_ha->port[i].wide_port_phymap = 0; 2751cc943aeSjack wang pm8001_ha->port[i].port_attached = 0; 2761cc943aeSjack wang pm8001_ha->port[i].port_state = 0; 2771cc943aeSjack wang INIT_LIST_HEAD(&pm8001_ha->port[i].list); 2781cc943aeSjack wang } 279dbf9bfe6Sjack wang 28097ee2088Sjack_wang pm8001_ha->tags = kzalloc(PM8001_MAX_CCB, GFP_KERNEL); 28197ee2088Sjack_wang if (!pm8001_ha->tags) 28297ee2088Sjack_wang goto err_out; 283dbf9bfe6Sjack wang /* MPI Memory region 1 for AAP Event Log for fw */ 284dbf9bfe6Sjack wang pm8001_ha->memoryMap.region[AAP1].num_elements = 1; 285dbf9bfe6Sjack wang pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE; 286dbf9bfe6Sjack wang pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE; 287dbf9bfe6Sjack wang pm8001_ha->memoryMap.region[AAP1].alignment = 32; 288dbf9bfe6Sjack wang 289dbf9bfe6Sjack wang /* MPI Memory region 2 for IOP Event Log for fw */ 290dbf9bfe6Sjack wang pm8001_ha->memoryMap.region[IOP].num_elements = 1; 291dbf9bfe6Sjack wang pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE; 292dbf9bfe6Sjack wang pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE; 293dbf9bfe6Sjack wang pm8001_ha->memoryMap.region[IOP].alignment = 32; 294dbf9bfe6Sjack wang 295e590adfdSSakthivel K for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) { 296dbf9bfe6Sjack wang /* MPI Memory region 3 for consumer Index of inbound queues */ 297e590adfdSSakthivel K pm8001_ha->memoryMap.region[CI+i].num_elements = 1; 298e590adfdSSakthivel K pm8001_ha->memoryMap.region[CI+i].element_size = 4; 299e590adfdSSakthivel K pm8001_ha->memoryMap.region[CI+i].total_len = 4; 300e590adfdSSakthivel K pm8001_ha->memoryMap.region[CI+i].alignment = 4; 301dbf9bfe6Sjack wang 302e590adfdSSakthivel K if ((ent->driver_data) != chip_8001) { 303dbf9bfe6Sjack wang /* MPI Memory region 5 inbound queues */ 304e590adfdSSakthivel K pm8001_ha->memoryMap.region[IB+i].num_elements = 305e590adfdSSakthivel K PM8001_MPI_QUEUE; 306e590adfdSSakthivel K pm8001_ha->memoryMap.region[IB+i].element_size = 128; 307e590adfdSSakthivel K pm8001_ha->memoryMap.region[IB+i].total_len = 308e590adfdSSakthivel K PM8001_MPI_QUEUE * 128; 309e590adfdSSakthivel K pm8001_ha->memoryMap.region[IB+i].alignment = 128; 310e590adfdSSakthivel K } else { 311e590adfdSSakthivel K pm8001_ha->memoryMap.region[IB+i].num_elements = 312e590adfdSSakthivel K PM8001_MPI_QUEUE; 313e590adfdSSakthivel K pm8001_ha->memoryMap.region[IB+i].element_size = 64; 314e590adfdSSakthivel K pm8001_ha->memoryMap.region[IB+i].total_len = 315e590adfdSSakthivel K PM8001_MPI_QUEUE * 64; 316e590adfdSSakthivel K pm8001_ha->memoryMap.region[IB+i].alignment = 64; 317e590adfdSSakthivel K } 318e590adfdSSakthivel K } 319dbf9bfe6Sjack wang 320e590adfdSSakthivel K for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) { 321e590adfdSSakthivel K /* MPI Memory region 4 for producer Index of outbound queues */ 322e590adfdSSakthivel K pm8001_ha->memoryMap.region[PI+i].num_elements = 1; 323e590adfdSSakthivel K pm8001_ha->memoryMap.region[PI+i].element_size = 4; 324e590adfdSSakthivel K pm8001_ha->memoryMap.region[PI+i].total_len = 4; 325e590adfdSSakthivel K pm8001_ha->memoryMap.region[PI+i].alignment = 4; 326dbf9bfe6Sjack wang 327e590adfdSSakthivel K if (ent->driver_data != chip_8001) { 328e590adfdSSakthivel K /* MPI Memory region 6 Outbound queues */ 329e590adfdSSakthivel K pm8001_ha->memoryMap.region[OB+i].num_elements = 330e590adfdSSakthivel K PM8001_MPI_QUEUE; 331e590adfdSSakthivel K pm8001_ha->memoryMap.region[OB+i].element_size = 128; 332e590adfdSSakthivel K pm8001_ha->memoryMap.region[OB+i].total_len = 333e590adfdSSakthivel K PM8001_MPI_QUEUE * 128; 334e590adfdSSakthivel K pm8001_ha->memoryMap.region[OB+i].alignment = 128; 335e590adfdSSakthivel K } else { 336e590adfdSSakthivel K /* MPI Memory region 6 Outbound queues */ 337e590adfdSSakthivel K pm8001_ha->memoryMap.region[OB+i].num_elements = 338e590adfdSSakthivel K PM8001_MPI_QUEUE; 339e590adfdSSakthivel K pm8001_ha->memoryMap.region[OB+i].element_size = 64; 340e590adfdSSakthivel K pm8001_ha->memoryMap.region[OB+i].total_len = 341e590adfdSSakthivel K PM8001_MPI_QUEUE * 64; 342e590adfdSSakthivel K pm8001_ha->memoryMap.region[OB+i].alignment = 64; 343e590adfdSSakthivel K } 344e590adfdSSakthivel K 345e590adfdSSakthivel K } 346dbf9bfe6Sjack wang /* Memory region write DMA*/ 347dbf9bfe6Sjack wang pm8001_ha->memoryMap.region[NVMD].num_elements = 1; 348dbf9bfe6Sjack wang pm8001_ha->memoryMap.region[NVMD].element_size = 4096; 349dbf9bfe6Sjack wang pm8001_ha->memoryMap.region[NVMD].total_len = 4096; 350dbf9bfe6Sjack wang /* Memory region for devices*/ 351dbf9bfe6Sjack wang pm8001_ha->memoryMap.region[DEV_MEM].num_elements = 1; 352dbf9bfe6Sjack wang pm8001_ha->memoryMap.region[DEV_MEM].element_size = PM8001_MAX_DEVICES * 353dbf9bfe6Sjack wang sizeof(struct pm8001_device); 354dbf9bfe6Sjack wang pm8001_ha->memoryMap.region[DEV_MEM].total_len = PM8001_MAX_DEVICES * 355dbf9bfe6Sjack wang sizeof(struct pm8001_device); 356dbf9bfe6Sjack wang 357dbf9bfe6Sjack wang /* Memory region for ccb_info*/ 358dbf9bfe6Sjack wang pm8001_ha->memoryMap.region[CCB_MEM].num_elements = 1; 359dbf9bfe6Sjack wang pm8001_ha->memoryMap.region[CCB_MEM].element_size = PM8001_MAX_CCB * 360dbf9bfe6Sjack wang sizeof(struct pm8001_ccb_info); 361dbf9bfe6Sjack wang pm8001_ha->memoryMap.region[CCB_MEM].total_len = PM8001_MAX_CCB * 362dbf9bfe6Sjack wang sizeof(struct pm8001_ccb_info); 363dbf9bfe6Sjack wang 3641c75a679SSakthivel K /* Memory region for fw flash */ 3651c75a679SSakthivel K pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096; 3661c75a679SSakthivel K 367d078b511SAnand Kumar Santhanam pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1; 368d078b511SAnand Kumar Santhanam pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000; 369d078b511SAnand Kumar Santhanam pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000; 370d078b511SAnand Kumar Santhanam pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000; 371dbf9bfe6Sjack wang for (i = 0; i < USI_MAX_MEMCNT; i++) { 372dbf9bfe6Sjack wang if (pm8001_mem_alloc(pm8001_ha->pdev, 373dbf9bfe6Sjack wang &pm8001_ha->memoryMap.region[i].virt_ptr, 374dbf9bfe6Sjack wang &pm8001_ha->memoryMap.region[i].phys_addr, 375dbf9bfe6Sjack wang &pm8001_ha->memoryMap.region[i].phys_addr_hi, 376dbf9bfe6Sjack wang &pm8001_ha->memoryMap.region[i].phys_addr_lo, 377dbf9bfe6Sjack wang pm8001_ha->memoryMap.region[i].total_len, 378dbf9bfe6Sjack wang pm8001_ha->memoryMap.region[i].alignment) != 0) { 379dbf9bfe6Sjack wang PM8001_FAIL_DBG(pm8001_ha, 380dbf9bfe6Sjack wang pm8001_printk("Mem%d alloc failed\n", 381dbf9bfe6Sjack wang i)); 382dbf9bfe6Sjack wang goto err_out; 383dbf9bfe6Sjack wang } 384dbf9bfe6Sjack wang } 385dbf9bfe6Sjack wang 386dbf9bfe6Sjack wang pm8001_ha->devices = pm8001_ha->memoryMap.region[DEV_MEM].virt_ptr; 387dbf9bfe6Sjack wang for (i = 0; i < PM8001_MAX_DEVICES; i++) { 388aa9f8328SJames Bottomley pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED; 389dbf9bfe6Sjack wang pm8001_ha->devices[i].id = i; 390dbf9bfe6Sjack wang pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES; 391dbf9bfe6Sjack wang pm8001_ha->devices[i].running_req = 0; 392dbf9bfe6Sjack wang } 393dbf9bfe6Sjack wang pm8001_ha->ccb_info = pm8001_ha->memoryMap.region[CCB_MEM].virt_ptr; 394dbf9bfe6Sjack wang for (i = 0; i < PM8001_MAX_CCB; i++) { 395dbf9bfe6Sjack wang pm8001_ha->ccb_info[i].ccb_dma_handle = 396dbf9bfe6Sjack wang pm8001_ha->memoryMap.region[CCB_MEM].phys_addr + 397dbf9bfe6Sjack wang i * sizeof(struct pm8001_ccb_info); 39897ee2088Sjack_wang pm8001_ha->ccb_info[i].task = NULL; 39997ee2088Sjack_wang pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff; 40097ee2088Sjack_wang pm8001_ha->ccb_info[i].device = NULL; 401dbf9bfe6Sjack wang ++pm8001_ha->tags_num; 402dbf9bfe6Sjack wang } 403dbf9bfe6Sjack wang pm8001_ha->flags = PM8001F_INIT_TIME; 404dbf9bfe6Sjack wang /* Initialize tags */ 405dbf9bfe6Sjack wang pm8001_tag_init(pm8001_ha); 406dbf9bfe6Sjack wang return 0; 407dbf9bfe6Sjack wang err_out: 408dbf9bfe6Sjack wang return 1; 409dbf9bfe6Sjack wang } 410dbf9bfe6Sjack wang 411dbf9bfe6Sjack wang /** 412dbf9bfe6Sjack wang * pm8001_ioremap - remap the pci high physical address to kernal virtual 413dbf9bfe6Sjack wang * address so that we can access them. 414dbf9bfe6Sjack wang * @pm8001_ha:our hba structure. 415dbf9bfe6Sjack wang */ 416dbf9bfe6Sjack wang static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha) 417dbf9bfe6Sjack wang { 418dbf9bfe6Sjack wang u32 bar; 419dbf9bfe6Sjack wang u32 logicalBar = 0; 420dbf9bfe6Sjack wang struct pci_dev *pdev; 421dbf9bfe6Sjack wang 422dbf9bfe6Sjack wang pdev = pm8001_ha->pdev; 423dbf9bfe6Sjack wang /* map pci mem (PMC pci base 0-3)*/ 424c9c13ba4SDenis Efremov for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { 425dbf9bfe6Sjack wang /* 426dbf9bfe6Sjack wang ** logical BARs for SPC: 427dbf9bfe6Sjack wang ** bar 0 and 1 - logical BAR0 428dbf9bfe6Sjack wang ** bar 2 and 3 - logical BAR1 429dbf9bfe6Sjack wang ** bar4 - logical BAR2 430dbf9bfe6Sjack wang ** bar5 - logical BAR3 431dbf9bfe6Sjack wang ** Skip the appropriate assignments: 432dbf9bfe6Sjack wang */ 433dbf9bfe6Sjack wang if ((bar == 1) || (bar == 3)) 434dbf9bfe6Sjack wang continue; 435dbf9bfe6Sjack wang if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { 436dbf9bfe6Sjack wang pm8001_ha->io_mem[logicalBar].membase = 437dbf9bfe6Sjack wang pci_resource_start(pdev, bar); 438dbf9bfe6Sjack wang pm8001_ha->io_mem[logicalBar].memsize = 439dbf9bfe6Sjack wang pci_resource_len(pdev, bar); 440dbf9bfe6Sjack wang pm8001_ha->io_mem[logicalBar].memvirtaddr = 441dbf9bfe6Sjack wang ioremap(pm8001_ha->io_mem[logicalBar].membase, 442dbf9bfe6Sjack wang pm8001_ha->io_mem[logicalBar].memsize); 443dbf9bfe6Sjack wang PM8001_INIT_DBG(pm8001_ha, 444e590adfdSSakthivel K pm8001_printk("PCI: bar %d, logicalBar %d ", 445e590adfdSSakthivel K bar, logicalBar)); 446e590adfdSSakthivel K PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 447e590adfdSSakthivel K "base addr %llx virt_addr=%llx len=%d\n", 448e590adfdSSakthivel K (u64)pm8001_ha->io_mem[logicalBar].membase, 449da1dccceSAnand Kumar Santhanam (u64)(unsigned long) 450da1dccceSAnand Kumar Santhanam pm8001_ha->io_mem[logicalBar].memvirtaddr, 451dbf9bfe6Sjack wang pm8001_ha->io_mem[logicalBar].memsize)); 452dbf9bfe6Sjack wang } else { 453dbf9bfe6Sjack wang pm8001_ha->io_mem[logicalBar].membase = 0; 454dbf9bfe6Sjack wang pm8001_ha->io_mem[logicalBar].memsize = 0; 45562fb8b34SSaurav Girepunje pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL; 456dbf9bfe6Sjack wang } 457dbf9bfe6Sjack wang logicalBar++; 458dbf9bfe6Sjack wang } 459dbf9bfe6Sjack wang return 0; 460dbf9bfe6Sjack wang } 461dbf9bfe6Sjack wang 462dbf9bfe6Sjack wang /** 463dbf9bfe6Sjack wang * pm8001_pci_alloc - initialize our ha card structure 464dbf9bfe6Sjack wang * @pdev: pci device. 465dbf9bfe6Sjack wang * @ent: ent 466dbf9bfe6Sjack wang * @shost: scsi host struct which has been initialized before. 467dbf9bfe6Sjack wang */ 4686f039790SGreg Kroah-Hartman static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev, 469e590adfdSSakthivel K const struct pci_device_id *ent, 4706f039790SGreg Kroah-Hartman struct Scsi_Host *shost) 471e590adfdSSakthivel K 472dbf9bfe6Sjack wang { 473dbf9bfe6Sjack wang struct pm8001_hba_info *pm8001_ha; 474dbf9bfe6Sjack wang struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 4756cd60b37SNikith Ganigarakoppal int j; 476dbf9bfe6Sjack wang 477dbf9bfe6Sjack wang pm8001_ha = sha->lldd_ha; 478dbf9bfe6Sjack wang if (!pm8001_ha) 479dbf9bfe6Sjack wang return NULL; 480dbf9bfe6Sjack wang 481dbf9bfe6Sjack wang pm8001_ha->pdev = pdev; 482dbf9bfe6Sjack wang pm8001_ha->dev = &pdev->dev; 483e590adfdSSakthivel K pm8001_ha->chip_id = ent->driver_data; 484dbf9bfe6Sjack wang pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id]; 485dbf9bfe6Sjack wang pm8001_ha->irq = pdev->irq; 486dbf9bfe6Sjack wang pm8001_ha->sas = sha; 487dbf9bfe6Sjack wang pm8001_ha->shost = shost; 488dbf9bfe6Sjack wang pm8001_ha->id = pm8001_id++; 4897370672dSpeter chang pm8001_ha->logging_level = logging_level; 490dba2cc03SDeepak Ukey pm8001_ha->non_fatal_count = 0; 4913e253d96Speter chang if (link_rate >= 1 && link_rate <= 15) 4923e253d96Speter chang pm8001_ha->link_rate = (link_rate << 8); 4933e253d96Speter chang else { 4943e253d96Speter chang pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 | 4953e253d96Speter chang LINKRATE_60 | LINKRATE_120; 4963e253d96Speter chang PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 4973e253d96Speter chang "Setting link rate to default value\n")); 4983e253d96Speter chang } 499dbf9bfe6Sjack wang sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id); 500f74cf271SSakthivel K /* IOMB size is 128 for 8088/89 controllers */ 501f74cf271SSakthivel K if (pm8001_ha->chip_id != chip_8001) 502f74cf271SSakthivel K pm8001_ha->iomb_size = IOMB_SIZE_SPCV; 503f74cf271SSakthivel K else 504f74cf271SSakthivel K pm8001_ha->iomb_size = IOMB_SIZE_SPC; 505f74cf271SSakthivel K 506dbf9bfe6Sjack wang #ifdef PM8001_USE_TASKLET 5076cd60b37SNikith Ganigarakoppal /* Tasklet for non msi-x interrupt handler */ 508c913df3fSBenjamin Rood if ((!pdev->msix_cap || !pci_msi_enabled()) 509c913df3fSBenjamin Rood || (pm8001_ha->chip_id == chip_8001)) 5106cd60b37SNikith Ganigarakoppal tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet, 5116cd60b37SNikith Ganigarakoppal (unsigned long)&(pm8001_ha->irq_vector[0])); 5126cd60b37SNikith Ganigarakoppal else 5136cd60b37SNikith Ganigarakoppal for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 5146cd60b37SNikith Ganigarakoppal tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet, 5156cd60b37SNikith Ganigarakoppal (unsigned long)&(pm8001_ha->irq_vector[j])); 516dbf9bfe6Sjack wang #endif 517dbf9bfe6Sjack wang pm8001_ioremap(pm8001_ha); 518e590adfdSSakthivel K if (!pm8001_alloc(pm8001_ha, ent)) 519dbf9bfe6Sjack wang return pm8001_ha; 520dbf9bfe6Sjack wang pm8001_free(pm8001_ha); 521dbf9bfe6Sjack wang return NULL; 522dbf9bfe6Sjack wang } 523dbf9bfe6Sjack wang 524dbf9bfe6Sjack wang /** 525dbf9bfe6Sjack wang * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit 526dbf9bfe6Sjack wang * @pdev: pci device. 527dbf9bfe6Sjack wang */ 528dbf9bfe6Sjack wang static int pci_go_44(struct pci_dev *pdev) 529dbf9bfe6Sjack wang { 530dbf9bfe6Sjack wang int rc; 531dbf9bfe6Sjack wang 532f73bdebdSChristoph Hellwig rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44)); 533dbf9bfe6Sjack wang if (rc) { 534f73bdebdSChristoph Hellwig rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 535f73bdebdSChristoph Hellwig if (rc) 536dbf9bfe6Sjack wang dev_printk(KERN_ERR, &pdev->dev, 537dbf9bfe6Sjack wang "32-bit DMA enable failed\n"); 538dbf9bfe6Sjack wang } 539dbf9bfe6Sjack wang return rc; 540dbf9bfe6Sjack wang } 541dbf9bfe6Sjack wang 542dbf9bfe6Sjack wang /** 543dbf9bfe6Sjack wang * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them. 544dbf9bfe6Sjack wang * @shost: scsi host which has been allocated outside. 545dbf9bfe6Sjack wang * @chip_info: our ha struct. 546dbf9bfe6Sjack wang */ 5476f039790SGreg Kroah-Hartman static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost, 548dbf9bfe6Sjack wang const struct pm8001_chip_info *chip_info) 549dbf9bfe6Sjack wang { 550dbf9bfe6Sjack wang int phy_nr, port_nr; 551dbf9bfe6Sjack wang struct asd_sas_phy **arr_phy; 552dbf9bfe6Sjack wang struct asd_sas_port **arr_port; 553dbf9bfe6Sjack wang struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 554dbf9bfe6Sjack wang 555dbf9bfe6Sjack wang phy_nr = chip_info->n_phy; 556dbf9bfe6Sjack wang port_nr = phy_nr; 557dbf9bfe6Sjack wang memset(sha, 0x00, sizeof(*sha)); 558dbf9bfe6Sjack wang arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL); 559dbf9bfe6Sjack wang if (!arr_phy) 560dbf9bfe6Sjack wang goto exit; 561dbf9bfe6Sjack wang arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL); 562dbf9bfe6Sjack wang if (!arr_port) 563dbf9bfe6Sjack wang goto exit_free2; 564dbf9bfe6Sjack wang 565dbf9bfe6Sjack wang sha->sas_phy = arr_phy; 566dbf9bfe6Sjack wang sha->sas_port = arr_port; 567dbf9bfe6Sjack wang sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL); 568dbf9bfe6Sjack wang if (!sha->lldd_ha) 569dbf9bfe6Sjack wang goto exit_free1; 570dbf9bfe6Sjack wang 571dbf9bfe6Sjack wang shost->transportt = pm8001_stt; 572dbf9bfe6Sjack wang shost->max_id = PM8001_MAX_DEVICES; 573dbf9bfe6Sjack wang shost->max_lun = 8; 574dbf9bfe6Sjack wang shost->max_channel = 0; 575dbf9bfe6Sjack wang shost->unique_id = pm8001_id; 576dbf9bfe6Sjack wang shost->max_cmd_len = 16; 577dbf9bfe6Sjack wang shost->can_queue = PM8001_CAN_QUEUE; 578dbf9bfe6Sjack wang shost->cmd_per_lun = 32; 579dbf9bfe6Sjack wang return 0; 580dbf9bfe6Sjack wang exit_free1: 581dbf9bfe6Sjack wang kfree(arr_port); 582dbf9bfe6Sjack wang exit_free2: 583dbf9bfe6Sjack wang kfree(arr_phy); 584dbf9bfe6Sjack wang exit: 585dbf9bfe6Sjack wang return -1; 586dbf9bfe6Sjack wang } 587dbf9bfe6Sjack wang 588dbf9bfe6Sjack wang /** 589dbf9bfe6Sjack wang * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas 590dbf9bfe6Sjack wang * @shost: scsi host which has been allocated outside 591dbf9bfe6Sjack wang * @chip_info: our ha struct. 592dbf9bfe6Sjack wang */ 5936f039790SGreg Kroah-Hartman static void pm8001_post_sas_ha_init(struct Scsi_Host *shost, 594dbf9bfe6Sjack wang const struct pm8001_chip_info *chip_info) 595dbf9bfe6Sjack wang { 596dbf9bfe6Sjack wang int i = 0; 597dbf9bfe6Sjack wang struct pm8001_hba_info *pm8001_ha; 598dbf9bfe6Sjack wang struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 599dbf9bfe6Sjack wang 600dbf9bfe6Sjack wang pm8001_ha = sha->lldd_ha; 601dbf9bfe6Sjack wang for (i = 0; i < chip_info->n_phy; i++) { 602dbf9bfe6Sjack wang sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy; 603dbf9bfe6Sjack wang sha->sas_port[i] = &pm8001_ha->port[i].sas_port; 6046c85e4bcSViswas G sha->sas_phy[i]->sas_addr = 6056c85e4bcSViswas G (u8 *)&pm8001_ha->phy[i].dev_sas_addr; 606dbf9bfe6Sjack wang } 607dbf9bfe6Sjack wang sha->sas_ha_name = DRV_NAME; 608dbf9bfe6Sjack wang sha->dev = pm8001_ha->dev; 6096c85e4bcSViswas G sha->strict_wide_ports = 1; 610dbf9bfe6Sjack wang sha->lldd_module = THIS_MODULE; 611dbf9bfe6Sjack wang sha->sas_addr = &pm8001_ha->sas_addr[0]; 612dbf9bfe6Sjack wang sha->num_phys = chip_info->n_phy; 613dbf9bfe6Sjack wang sha->core.shost = shost; 614dbf9bfe6Sjack wang } 615dbf9bfe6Sjack wang 616dbf9bfe6Sjack wang /** 617dbf9bfe6Sjack wang * pm8001_init_sas_add - initialize sas address 618e802fc43SLee Jones * @pm8001_ha: our ha struct. 619dbf9bfe6Sjack wang * 620dbf9bfe6Sjack wang * Currently we just set the fixed SAS address to our HBA,for manufacture, 621dbf9bfe6Sjack wang * it should read from the EEPROM 622dbf9bfe6Sjack wang */ 623dbf9bfe6Sjack wang static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha) 624dbf9bfe6Sjack wang { 625a33a0155SSakthivel K u8 i, j; 6266c85e4bcSViswas G u8 sas_add[8]; 627dbf9bfe6Sjack wang #ifdef PM8001_READ_VPD 628a33a0155SSakthivel K /* For new SPC controllers WWN is stored in flash vpd 629a33a0155SSakthivel K * For SPC/SPCve controllers WWN is stored in EEPROM 630a33a0155SSakthivel K * For Older SPC WWN is stored in NVMD 631a33a0155SSakthivel K */ 632dbf9bfe6Sjack wang DECLARE_COMPLETION_ONSTACK(completion); 6337c8356d9Sjack wang struct pm8001_ioctl_payload payload; 634a33a0155SSakthivel K u16 deviceid; 6355b4ce882STomas Henzl int rc; 6365b4ce882STomas Henzl 637a33a0155SSakthivel K pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid); 638dbf9bfe6Sjack wang pm8001_ha->nvmd_completion = &completion; 639a33a0155SSakthivel K 640a33a0155SSakthivel K if (pm8001_ha->chip_id == chip_8001) { 641f49d2132SBradley Grove if (deviceid == 0x8081 || deviceid == 0x0042) { 642a33a0155SSakthivel K payload.minor_function = 4; 6439b889846SViswas G payload.rd_length = 4096; 644a33a0155SSakthivel K } else { 6457c8356d9Sjack wang payload.minor_function = 0; 6469b889846SViswas G payload.rd_length = 128; 647a33a0155SSakthivel K } 64810efa460SBenjamin Rood } else if ((pm8001_ha->chip_id == chip_8070 || 64910efa460SBenjamin Rood pm8001_ha->chip_id == chip_8072) && 65010efa460SBenjamin Rood pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) { 65110efa460SBenjamin Rood payload.minor_function = 4; 6529b889846SViswas G payload.rd_length = 4096; 653a33a0155SSakthivel K } else { 654a33a0155SSakthivel K payload.minor_function = 1; 6559b889846SViswas G payload.rd_length = 4096; 656a33a0155SSakthivel K } 657a33a0155SSakthivel K payload.offset = 0; 6589b889846SViswas G payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL); 6595b4ce882STomas Henzl if (!payload.func_specific) { 6605b4ce882STomas Henzl PM8001_INIT_DBG(pm8001_ha, pm8001_printk("mem alloc fail\n")); 6615b4ce882STomas Henzl return; 6625b4ce882STomas Henzl } 6635b4ce882STomas Henzl rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload); 6645b4ce882STomas Henzl if (rc) { 6655b4ce882STomas Henzl kfree(payload.func_specific); 6665b4ce882STomas Henzl PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n")); 6675b4ce882STomas Henzl return; 6685b4ce882STomas Henzl } 669dbf9bfe6Sjack wang wait_for_completion(&completion); 670a33a0155SSakthivel K 671a33a0155SSakthivel K for (i = 0, j = 0; i <= 7; i++, j++) { 672a33a0155SSakthivel K if (pm8001_ha->chip_id == chip_8001) { 673a33a0155SSakthivel K if (deviceid == 0x8081) 674a33a0155SSakthivel K pm8001_ha->sas_addr[j] = 675a33a0155SSakthivel K payload.func_specific[0x704 + i]; 676f49d2132SBradley Grove else if (deviceid == 0x0042) 677f49d2132SBradley Grove pm8001_ha->sas_addr[j] = 678f49d2132SBradley Grove payload.func_specific[0x010 + i]; 67910efa460SBenjamin Rood } else if ((pm8001_ha->chip_id == chip_8070 || 68010efa460SBenjamin Rood pm8001_ha->chip_id == chip_8072) && 68110efa460SBenjamin Rood pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) { 68210efa460SBenjamin Rood pm8001_ha->sas_addr[j] = 68310efa460SBenjamin Rood payload.func_specific[0x010 + i]; 684a33a0155SSakthivel K } else 685a33a0155SSakthivel K pm8001_ha->sas_addr[j] = 686a33a0155SSakthivel K payload.func_specific[0x804 + i]; 687a33a0155SSakthivel K } 6886c85e4bcSViswas G memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE); 689dbf9bfe6Sjack wang for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 6906c85e4bcSViswas G if (i && ((i % 4) == 0)) 6916c85e4bcSViswas G sas_add[7] = sas_add[7] + 4; 692a33a0155SSakthivel K memcpy(&pm8001_ha->phy[i].dev_sas_addr, 6936c85e4bcSViswas G sas_add, SAS_ADDR_SIZE); 694dbf9bfe6Sjack wang PM8001_INIT_DBG(pm8001_ha, 6957c8356d9Sjack wang pm8001_printk("phy %d sas_addr = %016llx\n", i, 6967c8356d9Sjack wang pm8001_ha->phy[i].dev_sas_addr)); 697dbf9bfe6Sjack wang } 6985b4ce882STomas Henzl kfree(payload.func_specific); 699dbf9bfe6Sjack wang #else 700dbf9bfe6Sjack wang for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 7017c8356d9Sjack wang pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL; 702dbf9bfe6Sjack wang pm8001_ha->phy[i].dev_sas_addr = 703dbf9bfe6Sjack wang cpu_to_be64((u64) 704dbf9bfe6Sjack wang (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr)); 705dbf9bfe6Sjack wang } 706dbf9bfe6Sjack wang memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr, 707dbf9bfe6Sjack wang SAS_ADDR_SIZE); 708dbf9bfe6Sjack wang #endif 709dbf9bfe6Sjack wang } 710dbf9bfe6Sjack wang 71127909407SAnand Kumar Santhanam /* 71227909407SAnand Kumar Santhanam * pm8001_get_phy_settings_info : Read phy setting values. 71327909407SAnand Kumar Santhanam * @pm8001_ha : our hba. 71427909407SAnand Kumar Santhanam */ 715f2c6f180SMaurizio Lombardi static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha) 71627909407SAnand Kumar Santhanam { 71727909407SAnand Kumar Santhanam 71827909407SAnand Kumar Santhanam #ifdef PM8001_READ_VPD 71927909407SAnand Kumar Santhanam /*OPTION ROM FLASH read for the SPC cards */ 72027909407SAnand Kumar Santhanam DECLARE_COMPLETION_ONSTACK(completion); 72127909407SAnand Kumar Santhanam struct pm8001_ioctl_payload payload; 7225b4ce882STomas Henzl int rc; 72327909407SAnand Kumar Santhanam 72427909407SAnand Kumar Santhanam pm8001_ha->nvmd_completion = &completion; 72527909407SAnand Kumar Santhanam /* SAS ADDRESS read from flash / EEPROM */ 72627909407SAnand Kumar Santhanam payload.minor_function = 6; 72727909407SAnand Kumar Santhanam payload.offset = 0; 7289b889846SViswas G payload.rd_length = 4096; 72927909407SAnand Kumar Santhanam payload.func_specific = kzalloc(4096, GFP_KERNEL); 730f2c6f180SMaurizio Lombardi if (!payload.func_specific) 731f2c6f180SMaurizio Lombardi return -ENOMEM; 73227909407SAnand Kumar Santhanam /* Read phy setting values from flash */ 7335b4ce882STomas Henzl rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload); 7345b4ce882STomas Henzl if (rc) { 7355b4ce882STomas Henzl kfree(payload.func_specific); 7365b4ce882STomas Henzl PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n")); 7375b4ce882STomas Henzl return -ENOMEM; 7385b4ce882STomas Henzl } 73927909407SAnand Kumar Santhanam wait_for_completion(&completion); 74027909407SAnand Kumar Santhanam pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific); 741f2c6f180SMaurizio Lombardi kfree(payload.func_specific); 74227909407SAnand Kumar Santhanam #endif 743f2c6f180SMaurizio Lombardi return 0; 74427909407SAnand Kumar Santhanam } 74527909407SAnand Kumar Santhanam 746c5614df7SBenjamin Rood struct pm8001_mpi3_phy_pg_trx_config { 747c5614df7SBenjamin Rood u32 LaneLosCfg; 748c5614df7SBenjamin Rood u32 LanePgaCfg1; 749c5614df7SBenjamin Rood u32 LanePisoCfg1; 750c5614df7SBenjamin Rood u32 LanePisoCfg2; 751c5614df7SBenjamin Rood u32 LanePisoCfg3; 752c5614df7SBenjamin Rood u32 LanePisoCfg4; 753c5614df7SBenjamin Rood u32 LanePisoCfg5; 754c5614df7SBenjamin Rood u32 LanePisoCfg6; 755c5614df7SBenjamin Rood u32 LaneBctCtrl; 756c5614df7SBenjamin Rood }; 757c5614df7SBenjamin Rood 758c5614df7SBenjamin Rood /** 759c5614df7SBenjamin Rood * pm8001_get_internal_phy_settings : Retrieves the internal PHY settings 760c5614df7SBenjamin Rood * @pm8001_ha : our adapter 761c5614df7SBenjamin Rood * @phycfg : PHY config page to populate 762c5614df7SBenjamin Rood */ 763c5614df7SBenjamin Rood static 764c5614df7SBenjamin Rood void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha, 765c5614df7SBenjamin Rood struct pm8001_mpi3_phy_pg_trx_config *phycfg) 766c5614df7SBenjamin Rood { 767c5614df7SBenjamin Rood phycfg->LaneLosCfg = 0x00000132; 768c5614df7SBenjamin Rood phycfg->LanePgaCfg1 = 0x00203949; 769c5614df7SBenjamin Rood phycfg->LanePisoCfg1 = 0x000000FF; 770c5614df7SBenjamin Rood phycfg->LanePisoCfg2 = 0xFF000001; 771c5614df7SBenjamin Rood phycfg->LanePisoCfg3 = 0xE7011300; 772c5614df7SBenjamin Rood phycfg->LanePisoCfg4 = 0x631C40C0; 773c5614df7SBenjamin Rood phycfg->LanePisoCfg5 = 0xF8102036; 774c5614df7SBenjamin Rood phycfg->LanePisoCfg6 = 0xF74A1000; 775c5614df7SBenjamin Rood phycfg->LaneBctCtrl = 0x00FB33F8; 776c5614df7SBenjamin Rood } 777c5614df7SBenjamin Rood 778c5614df7SBenjamin Rood /** 779c5614df7SBenjamin Rood * pm8001_get_external_phy_settings : Retrieves the external PHY settings 780c5614df7SBenjamin Rood * @pm8001_ha : our adapter 781c5614df7SBenjamin Rood * @phycfg : PHY config page to populate 782c5614df7SBenjamin Rood */ 783c5614df7SBenjamin Rood static 784c5614df7SBenjamin Rood void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha, 785c5614df7SBenjamin Rood struct pm8001_mpi3_phy_pg_trx_config *phycfg) 786c5614df7SBenjamin Rood { 787c5614df7SBenjamin Rood phycfg->LaneLosCfg = 0x00000132; 788c5614df7SBenjamin Rood phycfg->LanePgaCfg1 = 0x00203949; 789c5614df7SBenjamin Rood phycfg->LanePisoCfg1 = 0x000000FF; 790c5614df7SBenjamin Rood phycfg->LanePisoCfg2 = 0xFF000001; 791c5614df7SBenjamin Rood phycfg->LanePisoCfg3 = 0xE7011300; 792c5614df7SBenjamin Rood phycfg->LanePisoCfg4 = 0x63349140; 793c5614df7SBenjamin Rood phycfg->LanePisoCfg5 = 0xF8102036; 794c5614df7SBenjamin Rood phycfg->LanePisoCfg6 = 0xF80D9300; 795c5614df7SBenjamin Rood phycfg->LaneBctCtrl = 0x00FB33F8; 796c5614df7SBenjamin Rood } 797c5614df7SBenjamin Rood 798c5614df7SBenjamin Rood /** 799c5614df7SBenjamin Rood * pm8001_get_phy_mask : Retrieves the mask that denotes if a PHY is int/ext 800c5614df7SBenjamin Rood * @pm8001_ha : our adapter 801c5614df7SBenjamin Rood * @phymask : The PHY mask 802c5614df7SBenjamin Rood */ 803c5614df7SBenjamin Rood static 804c5614df7SBenjamin Rood void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask) 805c5614df7SBenjamin Rood { 806c5614df7SBenjamin Rood switch (pm8001_ha->pdev->subsystem_device) { 807c5614df7SBenjamin Rood case 0x0070: /* H1280 - 8 external 0 internal */ 808c5614df7SBenjamin Rood case 0x0072: /* H12F0 - 16 external 0 internal */ 809c5614df7SBenjamin Rood *phymask = 0x0000; 810c5614df7SBenjamin Rood break; 811c5614df7SBenjamin Rood 812c5614df7SBenjamin Rood case 0x0071: /* H1208 - 0 external 8 internal */ 813c5614df7SBenjamin Rood case 0x0073: /* H120F - 0 external 16 internal */ 814c5614df7SBenjamin Rood *phymask = 0xFFFF; 815c5614df7SBenjamin Rood break; 816c5614df7SBenjamin Rood 817c5614df7SBenjamin Rood case 0x0080: /* H1244 - 4 external 4 internal */ 818c5614df7SBenjamin Rood *phymask = 0x00F0; 819c5614df7SBenjamin Rood break; 820c5614df7SBenjamin Rood 821c5614df7SBenjamin Rood case 0x0081: /* H1248 - 4 external 8 internal */ 822c5614df7SBenjamin Rood *phymask = 0x0FF0; 823c5614df7SBenjamin Rood break; 824c5614df7SBenjamin Rood 825c5614df7SBenjamin Rood case 0x0082: /* H1288 - 8 external 8 internal */ 826c5614df7SBenjamin Rood *phymask = 0xFF00; 827c5614df7SBenjamin Rood break; 828c5614df7SBenjamin Rood 829c5614df7SBenjamin Rood default: 830c5614df7SBenjamin Rood PM8001_INIT_DBG(pm8001_ha, 831c5614df7SBenjamin Rood pm8001_printk("Unknown subsystem device=0x%.04x", 832c5614df7SBenjamin Rood pm8001_ha->pdev->subsystem_device)); 833c5614df7SBenjamin Rood } 834c5614df7SBenjamin Rood } 835c5614df7SBenjamin Rood 836c5614df7SBenjamin Rood /** 837c5614df7SBenjamin Rood * pm8001_set_phy_settings_ven_117c_12Gb : Configure ATTO 12Gb PHY settings 838c5614df7SBenjamin Rood * @pm8001_ha : our adapter 839c5614df7SBenjamin Rood */ 840c5614df7SBenjamin Rood static 841c5614df7SBenjamin Rood int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha) 842c5614df7SBenjamin Rood { 843c5614df7SBenjamin Rood struct pm8001_mpi3_phy_pg_trx_config phycfg_int; 844c5614df7SBenjamin Rood struct pm8001_mpi3_phy_pg_trx_config phycfg_ext; 845c5614df7SBenjamin Rood int phymask = 0; 846c5614df7SBenjamin Rood int i = 0; 847c5614df7SBenjamin Rood 848c5614df7SBenjamin Rood memset(&phycfg_int, 0, sizeof(phycfg_int)); 849c5614df7SBenjamin Rood memset(&phycfg_ext, 0, sizeof(phycfg_ext)); 850c5614df7SBenjamin Rood 851c5614df7SBenjamin Rood pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int); 852c5614df7SBenjamin Rood pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext); 853c5614df7SBenjamin Rood pm8001_get_phy_mask(pm8001_ha, &phymask); 854c5614df7SBenjamin Rood 855c5614df7SBenjamin Rood for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 856c5614df7SBenjamin Rood if (phymask & (1 << i)) {/* Internal PHY */ 857c5614df7SBenjamin Rood pm8001_set_phy_profile_single(pm8001_ha, i, 858c5614df7SBenjamin Rood sizeof(phycfg_int) / sizeof(u32), 859c5614df7SBenjamin Rood (u32 *)&phycfg_int); 860c5614df7SBenjamin Rood 861c5614df7SBenjamin Rood } else { /* External PHY */ 862c5614df7SBenjamin Rood pm8001_set_phy_profile_single(pm8001_ha, i, 863c5614df7SBenjamin Rood sizeof(phycfg_ext) / sizeof(u32), 864c5614df7SBenjamin Rood (u32 *)&phycfg_ext); 865c5614df7SBenjamin Rood } 866c5614df7SBenjamin Rood } 867c5614df7SBenjamin Rood 868c5614df7SBenjamin Rood return 0; 869c5614df7SBenjamin Rood } 870c5614df7SBenjamin Rood 871da2dd618SBenjamin Rood /** 872da2dd618SBenjamin Rood * pm8001_configure_phy_settings : Configures PHY settings based on vendor ID. 873da2dd618SBenjamin Rood * @pm8001_ha : our hba. 874da2dd618SBenjamin Rood */ 875da2dd618SBenjamin Rood static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha) 876da2dd618SBenjamin Rood { 877da2dd618SBenjamin Rood switch (pm8001_ha->pdev->subsystem_vendor) { 878da2dd618SBenjamin Rood case PCI_VENDOR_ID_ATTO: 879c5614df7SBenjamin Rood if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */ 880c5614df7SBenjamin Rood return 0; 881c5614df7SBenjamin Rood else 882c5614df7SBenjamin Rood return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha); 883c5614df7SBenjamin Rood 884da2dd618SBenjamin Rood case PCI_VENDOR_ID_ADAPTEC2: 885da2dd618SBenjamin Rood case 0: 886da2dd618SBenjamin Rood return 0; 887da2dd618SBenjamin Rood 888da2dd618SBenjamin Rood default: 889da2dd618SBenjamin Rood return pm8001_get_phy_settings_info(pm8001_ha); 890da2dd618SBenjamin Rood } 891da2dd618SBenjamin Rood } 892da2dd618SBenjamin Rood 893dbf9bfe6Sjack wang #ifdef PM8001_USE_MSIX 894dbf9bfe6Sjack wang /** 895dbf9bfe6Sjack wang * pm8001_setup_msix - enable MSI-X interrupt 896e802fc43SLee Jones * @pm8001_ha: our ha struct. 897dbf9bfe6Sjack wang */ 8981245ee59SSakthivel K static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha) 899dbf9bfe6Sjack wang { 9001245ee59SSakthivel K u32 number_of_intr; 901dbf9bfe6Sjack wang int rc; 9021245ee59SSakthivel K 9031245ee59SSakthivel K /* SPCv controllers supports 64 msi-x */ 9041245ee59SSakthivel K if (pm8001_ha->chip_id == chip_8001) { 9051245ee59SSakthivel K number_of_intr = 1; 9061245ee59SSakthivel K } else { 9071245ee59SSakthivel K number_of_intr = PM8001_MAX_MSIX_VEC; 9081245ee59SSakthivel K } 9091245ee59SSakthivel K 910a76037ffSChristoph Hellwig rc = pci_alloc_irq_vectors(pm8001_ha->pdev, number_of_intr, 911a76037ffSChristoph Hellwig number_of_intr, PCI_IRQ_MSIX); 912d384be6eSVikram Auradkar number_of_intr = rc; 913a76037ffSChristoph Hellwig if (rc < 0) 914b4d511e5SAlexander Gordeev return rc; 915a76037ffSChristoph Hellwig pm8001_ha->number_of_intr = number_of_intr; 9161245ee59SSakthivel K 917b4d511e5SAlexander Gordeev PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 918a76037ffSChristoph Hellwig "pci_alloc_irq_vectors request ret:%d no of intr %d\n", 919b4d511e5SAlexander Gordeev rc, pm8001_ha->number_of_intr)); 920d384be6eSVikram Auradkar return 0; 921d384be6eSVikram Auradkar } 9221245ee59SSakthivel K 923d384be6eSVikram Auradkar static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha) 924d384be6eSVikram Auradkar { 925d384be6eSVikram Auradkar u32 i = 0, j = 0; 926d384be6eSVikram Auradkar int flag = 0, rc = 0; 927d384be6eSVikram Auradkar 928d384be6eSVikram Auradkar if (pm8001_ha->chip_id != chip_8001) 929d384be6eSVikram Auradkar flag &= ~IRQF_SHARED; 930d384be6eSVikram Auradkar 931d384be6eSVikram Auradkar PM8001_INIT_DBG(pm8001_ha, 932d384be6eSVikram Auradkar pm8001_printk("pci_enable_msix request number of intr %d\n", 933d384be6eSVikram Auradkar pm8001_ha->number_of_intr)); 934d384be6eSVikram Auradkar 935d384be6eSVikram Auradkar for (i = 0; i < pm8001_ha->number_of_intr; i++) { 93672954936SVikram Auradkar snprintf(pm8001_ha->intr_drvname[i], 93772954936SVikram Auradkar sizeof(pm8001_ha->intr_drvname[0]), 93872954936SVikram Auradkar "%s-%d", pm8001_ha->name, i); 9396cd60b37SNikith Ganigarakoppal pm8001_ha->irq_vector[i].irq_id = i; 9406cd60b37SNikith Ganigarakoppal pm8001_ha->irq_vector[i].drv_inst = pm8001_ha; 9416cd60b37SNikith Ganigarakoppal 942a76037ffSChristoph Hellwig rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i), 9431245ee59SSakthivel K pm8001_interrupt_handler_msix, flag, 94472954936SVikram Auradkar pm8001_ha->intr_drvname[i], 94572954936SVikram Auradkar &(pm8001_ha->irq_vector[i])); 9465607de73SAlexander Gordeev if (rc) { 947b4d511e5SAlexander Gordeev for (j = 0; j < i; j++) { 948a76037ffSChristoph Hellwig free_irq(pci_irq_vector(pm8001_ha->pdev, i), 9496cd60b37SNikith Ganigarakoppal &(pm8001_ha->irq_vector[i])); 950b4d511e5SAlexander Gordeev } 951a76037ffSChristoph Hellwig pci_free_irq_vectors(pm8001_ha->pdev); 952dbf9bfe6Sjack wang break; 953dbf9bfe6Sjack wang } 954dbf9bfe6Sjack wang } 955b4d511e5SAlexander Gordeev 956dbf9bfe6Sjack wang return rc; 957dbf9bfe6Sjack wang } 958dbf9bfe6Sjack wang #endif 959dbf9bfe6Sjack wang 960d384be6eSVikram Auradkar static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha) 961d384be6eSVikram Auradkar { 962d384be6eSVikram Auradkar struct pci_dev *pdev; 963d384be6eSVikram Auradkar 964d384be6eSVikram Auradkar pdev = pm8001_ha->pdev; 965d384be6eSVikram Auradkar 966d384be6eSVikram Auradkar #ifdef PM8001_USE_MSIX 967d384be6eSVikram Auradkar if (pci_find_capability(pdev, PCI_CAP_ID_MSIX)) 968d384be6eSVikram Auradkar return pm8001_setup_msix(pm8001_ha); 969d384be6eSVikram Auradkar PM8001_INIT_DBG(pm8001_ha, 970d384be6eSVikram Auradkar pm8001_printk("MSIX not supported!!!\n")); 971d384be6eSVikram Auradkar #endif 972d384be6eSVikram Auradkar return 0; 973d384be6eSVikram Auradkar } 974d384be6eSVikram Auradkar 975dbf9bfe6Sjack wang /** 976dbf9bfe6Sjack wang * pm8001_request_irq - register interrupt 977e802fc43SLee Jones * @pm8001_ha: our ha struct. 978dbf9bfe6Sjack wang */ 979dbf9bfe6Sjack wang static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha) 980dbf9bfe6Sjack wang { 981dbf9bfe6Sjack wang struct pci_dev *pdev; 98297ee2088Sjack_wang int rc; 983dbf9bfe6Sjack wang 984dbf9bfe6Sjack wang pdev = pm8001_ha->pdev; 985dbf9bfe6Sjack wang 986dbf9bfe6Sjack wang #ifdef PM8001_USE_MSIX 987c913df3fSBenjamin Rood if (pdev->msix_cap && pci_msi_enabled()) 988d384be6eSVikram Auradkar return pm8001_request_msix(pm8001_ha); 9891245ee59SSakthivel K else { 9901245ee59SSakthivel K PM8001_INIT_DBG(pm8001_ha, 9911245ee59SSakthivel K pm8001_printk("MSIX not supported!!!\n")); 992dbf9bfe6Sjack wang goto intx; 9931245ee59SSakthivel K } 994dbf9bfe6Sjack wang #endif 995dbf9bfe6Sjack wang 996dbf9bfe6Sjack wang intx: 997b595076aSUwe Kleine-König /* initialize the INT-X interrupt */ 998c913df3fSBenjamin Rood pm8001_ha->irq_vector[0].irq_id = 0; 999c913df3fSBenjamin Rood pm8001_ha->irq_vector[0].drv_inst = pm8001_ha; 10001245ee59SSakthivel K rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED, 100172954936SVikram Auradkar pm8001_ha->name, SHOST_TO_SAS_HA(pm8001_ha->shost)); 1002dbf9bfe6Sjack wang return rc; 1003dbf9bfe6Sjack wang } 1004dbf9bfe6Sjack wang 1005dbf9bfe6Sjack wang /** 1006dbf9bfe6Sjack wang * pm8001_pci_probe - probe supported device 1007dbf9bfe6Sjack wang * @pdev: pci device which kernel has been prepared for. 1008dbf9bfe6Sjack wang * @ent: pci device id 1009dbf9bfe6Sjack wang * 1010dbf9bfe6Sjack wang * This function is the main initialization function, when register a new 1011dbf9bfe6Sjack wang * pci driver it is invoked, all struct an hardware initilization should be done 1012dbf9bfe6Sjack wang * here, also, register interrupt 1013dbf9bfe6Sjack wang */ 10146f039790SGreg Kroah-Hartman static int pm8001_pci_probe(struct pci_dev *pdev, 1015dbf9bfe6Sjack wang const struct pci_device_id *ent) 1016dbf9bfe6Sjack wang { 1017dbf9bfe6Sjack wang unsigned int rc; 1018dbf9bfe6Sjack wang u32 pci_reg; 10191245ee59SSakthivel K u8 i = 0; 1020dbf9bfe6Sjack wang struct pm8001_hba_info *pm8001_ha; 1021dbf9bfe6Sjack wang struct Scsi_Host *shost = NULL; 1022dbf9bfe6Sjack wang const struct pm8001_chip_info *chip; 1023b40f2882SPeter Chang struct sas_ha_struct *sha; 1024dbf9bfe6Sjack wang 1025dbf9bfe6Sjack wang dev_printk(KERN_INFO, &pdev->dev, 1026a70b8fc3SSakthivel K "pm80xx: driver version %s\n", DRV_VERSION); 1027dbf9bfe6Sjack wang rc = pci_enable_device(pdev); 1028dbf9bfe6Sjack wang if (rc) 1029dbf9bfe6Sjack wang goto err_out_enable; 1030dbf9bfe6Sjack wang pci_set_master(pdev); 1031dbf9bfe6Sjack wang /* 1032dbf9bfe6Sjack wang * Enable pci slot busmaster by setting pci command register. 1033dbf9bfe6Sjack wang * This is required by FW for Cyclone card. 1034dbf9bfe6Sjack wang */ 1035dbf9bfe6Sjack wang 1036dbf9bfe6Sjack wang pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg); 1037dbf9bfe6Sjack wang pci_reg |= 0x157; 1038dbf9bfe6Sjack wang pci_write_config_dword(pdev, PCI_COMMAND, pci_reg); 1039dbf9bfe6Sjack wang rc = pci_request_regions(pdev, DRV_NAME); 1040dbf9bfe6Sjack wang if (rc) 1041dbf9bfe6Sjack wang goto err_out_disable; 1042dbf9bfe6Sjack wang rc = pci_go_44(pdev); 1043dbf9bfe6Sjack wang if (rc) 1044dbf9bfe6Sjack wang goto err_out_regions; 1045dbf9bfe6Sjack wang 1046dbf9bfe6Sjack wang shost = scsi_host_alloc(&pm8001_sht, sizeof(void *)); 1047dbf9bfe6Sjack wang if (!shost) { 1048dbf9bfe6Sjack wang rc = -ENOMEM; 1049dbf9bfe6Sjack wang goto err_out_regions; 1050dbf9bfe6Sjack wang } 1051dbf9bfe6Sjack wang chip = &pm8001_chips[ent->driver_data]; 1052b40f2882SPeter Chang sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL); 1053b40f2882SPeter Chang if (!sha) { 1054dbf9bfe6Sjack wang rc = -ENOMEM; 1055dbf9bfe6Sjack wang goto err_out_free_host; 1056dbf9bfe6Sjack wang } 1057b40f2882SPeter Chang SHOST_TO_SAS_HA(shost) = sha; 1058dbf9bfe6Sjack wang 1059dbf9bfe6Sjack wang rc = pm8001_prep_sas_ha_init(shost, chip); 1060dbf9bfe6Sjack wang if (rc) { 1061dbf9bfe6Sjack wang rc = -ENOMEM; 1062dbf9bfe6Sjack wang goto err_out_free; 1063dbf9bfe6Sjack wang } 1064dbf9bfe6Sjack wang pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost)); 1065e590adfdSSakthivel K /* ent->driver variable is used to differentiate between controllers */ 1066e590adfdSSakthivel K pm8001_ha = pm8001_pci_alloc(pdev, ent, shost); 1067dbf9bfe6Sjack wang if (!pm8001_ha) { 1068dbf9bfe6Sjack wang rc = -ENOMEM; 1069dbf9bfe6Sjack wang goto err_out_free; 1070dbf9bfe6Sjack wang } 1071d384be6eSVikram Auradkar /* Setup Interrupt */ 1072d384be6eSVikram Auradkar rc = pm8001_setup_irq(pm8001_ha); 1073d384be6eSVikram Auradkar if (rc) { 1074d384be6eSVikram Auradkar PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 1075d384be6eSVikram Auradkar "pm8001_setup_irq failed [ret: %d]\n", rc)); 1076d384be6eSVikram Auradkar goto err_out_shost; 1077d384be6eSVikram Auradkar } 1078b40f2882SPeter Chang 1079f5860992SSakthivel K PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1080dbf9bfe6Sjack wang rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); 1081a70b8fc3SSakthivel K if (rc) { 1082a70b8fc3SSakthivel K PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 1083a70b8fc3SSakthivel K "chip_init failed [ret: %d]\n", rc)); 1084dbf9bfe6Sjack wang goto err_out_ha_free; 1085a70b8fc3SSakthivel K } 1086dbf9bfe6Sjack wang 1087dbf9bfe6Sjack wang rc = scsi_add_host(shost, &pdev->dev); 1088dbf9bfe6Sjack wang if (rc) 1089dbf9bfe6Sjack wang goto err_out_ha_free; 1090d384be6eSVikram Auradkar /* Request Interrupt */ 1091dbf9bfe6Sjack wang rc = pm8001_request_irq(pm8001_ha); 1092a70b8fc3SSakthivel K if (rc) { 1093a70b8fc3SSakthivel K PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 1094a70b8fc3SSakthivel K "pm8001_request_irq failed [ret: %d]\n", rc)); 1095dbf9bfe6Sjack wang goto err_out_shost; 1096a70b8fc3SSakthivel K } 1097dbf9bfe6Sjack wang 1098f74cf271SSakthivel K PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0); 10991245ee59SSakthivel K if (pm8001_ha->chip_id != chip_8001) { 11001245ee59SSakthivel K for (i = 1; i < pm8001_ha->number_of_intr; i++) 11011245ee59SSakthivel K PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i); 1102a6cb3d01SSakthivel K /* setup thermal configuration. */ 1103a6cb3d01SSakthivel K pm80xx_set_thermal_config(pm8001_ha); 11041245ee59SSakthivel K } 11051245ee59SSakthivel K 1106dbf9bfe6Sjack wang pm8001_init_sas_add(pm8001_ha); 110727909407SAnand Kumar Santhanam /* phy setting support for motherboard controller */ 1108da2dd618SBenjamin Rood if (pm8001_configure_phy_settings(pm8001_ha)) 1109f2c6f180SMaurizio Lombardi goto err_out_shost; 1110da2dd618SBenjamin Rood 1111dbf9bfe6Sjack wang pm8001_post_sas_ha_init(shost, chip); 1112dbf9bfe6Sjack wang rc = sas_register_ha(SHOST_TO_SAS_HA(shost)); 1113b40f2882SPeter Chang if (rc) { 1114b40f2882SPeter Chang PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 1115b40f2882SPeter Chang "sas_register_ha failed [ret: %d]\n", rc)); 1116dbf9bfe6Sjack wang goto err_out_shost; 1117b40f2882SPeter Chang } 1118b40f2882SPeter Chang list_add_tail(&pm8001_ha->list, &hba_list); 1119dbf9bfe6Sjack wang scsi_scan_host(pm8001_ha->shost); 1120cd135754SDeepak Ukey pm8001_ha->flags = PM8001F_RUN_TIME; 1121dbf9bfe6Sjack wang return 0; 1122dbf9bfe6Sjack wang 1123dbf9bfe6Sjack wang err_out_shost: 1124dbf9bfe6Sjack wang scsi_remove_host(pm8001_ha->shost); 1125dbf9bfe6Sjack wang err_out_ha_free: 1126dbf9bfe6Sjack wang pm8001_free(pm8001_ha); 1127dbf9bfe6Sjack wang err_out_free: 1128b40f2882SPeter Chang kfree(sha); 1129dbf9bfe6Sjack wang err_out_free_host: 1130bc1371c1SPan Bian scsi_host_put(shost); 1131dbf9bfe6Sjack wang err_out_regions: 1132dbf9bfe6Sjack wang pci_release_regions(pdev); 1133dbf9bfe6Sjack wang err_out_disable: 1134dbf9bfe6Sjack wang pci_disable_device(pdev); 1135dbf9bfe6Sjack wang err_out_enable: 1136dbf9bfe6Sjack wang return rc; 1137dbf9bfe6Sjack wang } 1138dbf9bfe6Sjack wang 11396f039790SGreg Kroah-Hartman static void pm8001_pci_remove(struct pci_dev *pdev) 1140dbf9bfe6Sjack wang { 1141dbf9bfe6Sjack wang struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1142dbf9bfe6Sjack wang struct pm8001_hba_info *pm8001_ha; 11436cd60b37SNikith Ganigarakoppal int i, j; 1144dbf9bfe6Sjack wang pm8001_ha = sha->lldd_ha; 1145dbf9bfe6Sjack wang sas_unregister_ha(sha); 1146dbf9bfe6Sjack wang sas_remove_host(pm8001_ha->shost); 1147dbf9bfe6Sjack wang list_del(&pm8001_ha->list); 11481245ee59SSakthivel K PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1149f5860992SSakthivel K PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1150dbf9bfe6Sjack wang 1151dbf9bfe6Sjack wang #ifdef PM8001_USE_MSIX 1152dbf9bfe6Sjack wang for (i = 0; i < pm8001_ha->number_of_intr; i++) 1153a76037ffSChristoph Hellwig synchronize_irq(pci_irq_vector(pdev, i)); 1154dbf9bfe6Sjack wang for (i = 0; i < pm8001_ha->number_of_intr; i++) 1155a76037ffSChristoph Hellwig free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]); 1156a76037ffSChristoph Hellwig pci_free_irq_vectors(pdev); 1157dbf9bfe6Sjack wang #else 1158dbf9bfe6Sjack wang free_irq(pm8001_ha->irq, sha); 1159dbf9bfe6Sjack wang #endif 1160dbf9bfe6Sjack wang #ifdef PM8001_USE_TASKLET 11616cd60b37SNikith Ganigarakoppal /* For non-msix and msix interrupts */ 1162c913df3fSBenjamin Rood if ((!pdev->msix_cap || !pci_msi_enabled()) || 1163c913df3fSBenjamin Rood (pm8001_ha->chip_id == chip_8001)) 11646cd60b37SNikith Ganigarakoppal tasklet_kill(&pm8001_ha->tasklet[0]); 11656cd60b37SNikith Ganigarakoppal else 11666cd60b37SNikith Ganigarakoppal for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 11676cd60b37SNikith Ganigarakoppal tasklet_kill(&pm8001_ha->tasklet[j]); 1168dbf9bfe6Sjack wang #endif 1169bc1371c1SPan Bian scsi_host_put(pm8001_ha->shost); 1170dbf9bfe6Sjack wang pm8001_free(pm8001_ha); 1171dbf9bfe6Sjack wang kfree(sha->sas_phy); 1172dbf9bfe6Sjack wang kfree(sha->sas_port); 1173dbf9bfe6Sjack wang kfree(sha); 1174dbf9bfe6Sjack wang pci_release_regions(pdev); 1175dbf9bfe6Sjack wang pci_disable_device(pdev); 1176dbf9bfe6Sjack wang } 1177dbf9bfe6Sjack wang 1178dbf9bfe6Sjack wang /** 1179dbf9bfe6Sjack wang * pm8001_pci_suspend - power management suspend main entry point 1180dbf9bfe6Sjack wang * @pdev: PCI device struct 1181dbf9bfe6Sjack wang * @state: PM state change to (usually PCI_D3) 1182dbf9bfe6Sjack wang * 1183dbf9bfe6Sjack wang * Returns 0 success, anything else error. 1184dbf9bfe6Sjack wang */ 1185dbf9bfe6Sjack wang static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1186dbf9bfe6Sjack wang { 1187dbf9bfe6Sjack wang struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1188dbf9bfe6Sjack wang struct pm8001_hba_info *pm8001_ha; 11896cd60b37SNikith Ganigarakoppal int i, j; 1190dbf9bfe6Sjack wang u32 device_state; 1191dbf9bfe6Sjack wang pm8001_ha = sha->lldd_ha; 11929f176099SBradley Grove sas_suspend_ha(sha); 1193429305e4STejun Heo flush_workqueue(pm8001_wq); 1194dbf9bfe6Sjack wang scsi_block_requests(pm8001_ha->shost); 1195c8a2ba3fSYijing Wang if (!pdev->pm_cap) { 1196c8a2ba3fSYijing Wang dev_err(&pdev->dev, " PCI PM not supported\n"); 1197dbf9bfe6Sjack wang return -ENODEV; 1198dbf9bfe6Sjack wang } 11991245ee59SSakthivel K PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1200f5860992SSakthivel K PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1201dbf9bfe6Sjack wang #ifdef PM8001_USE_MSIX 1202dbf9bfe6Sjack wang for (i = 0; i < pm8001_ha->number_of_intr; i++) 1203a76037ffSChristoph Hellwig synchronize_irq(pci_irq_vector(pdev, i)); 1204dbf9bfe6Sjack wang for (i = 0; i < pm8001_ha->number_of_intr; i++) 1205a76037ffSChristoph Hellwig free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]); 1206a76037ffSChristoph Hellwig pci_free_irq_vectors(pdev); 1207dbf9bfe6Sjack wang #else 1208dbf9bfe6Sjack wang free_irq(pm8001_ha->irq, sha); 1209dbf9bfe6Sjack wang #endif 1210dbf9bfe6Sjack wang #ifdef PM8001_USE_TASKLET 12116cd60b37SNikith Ganigarakoppal /* For non-msix and msix interrupts */ 1212c913df3fSBenjamin Rood if ((!pdev->msix_cap || !pci_msi_enabled()) || 1213c913df3fSBenjamin Rood (pm8001_ha->chip_id == chip_8001)) 12146cd60b37SNikith Ganigarakoppal tasklet_kill(&pm8001_ha->tasklet[0]); 12156cd60b37SNikith Ganigarakoppal else 12166cd60b37SNikith Ganigarakoppal for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 12176cd60b37SNikith Ganigarakoppal tasklet_kill(&pm8001_ha->tasklet[j]); 1218dbf9bfe6Sjack wang #endif 1219dbf9bfe6Sjack wang device_state = pci_choose_state(pdev, state); 1220dbf9bfe6Sjack wang pm8001_printk("pdev=0x%p, slot=%s, entering " 1221dbf9bfe6Sjack wang "operating state [D%d]\n", pdev, 1222dbf9bfe6Sjack wang pm8001_ha->name, device_state); 1223dbf9bfe6Sjack wang pci_save_state(pdev); 1224dbf9bfe6Sjack wang pci_disable_device(pdev); 1225dbf9bfe6Sjack wang pci_set_power_state(pdev, device_state); 1226dbf9bfe6Sjack wang return 0; 1227dbf9bfe6Sjack wang } 1228dbf9bfe6Sjack wang 1229dbf9bfe6Sjack wang /** 1230dbf9bfe6Sjack wang * pm8001_pci_resume - power management resume main entry point 1231dbf9bfe6Sjack wang * @pdev: PCI device struct 1232dbf9bfe6Sjack wang * 1233dbf9bfe6Sjack wang * Returns 0 success, anything else error. 1234dbf9bfe6Sjack wang */ 1235dbf9bfe6Sjack wang static int pm8001_pci_resume(struct pci_dev *pdev) 1236dbf9bfe6Sjack wang { 1237dbf9bfe6Sjack wang struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1238dbf9bfe6Sjack wang struct pm8001_hba_info *pm8001_ha; 1239dbf9bfe6Sjack wang int rc; 12406cd60b37SNikith Ganigarakoppal u8 i = 0, j; 1241dbf9bfe6Sjack wang u32 device_state; 12429f176099SBradley Grove DECLARE_COMPLETION_ONSTACK(completion); 1243dbf9bfe6Sjack wang pm8001_ha = sha->lldd_ha; 1244dbf9bfe6Sjack wang device_state = pdev->current_state; 1245dbf9bfe6Sjack wang 1246dbf9bfe6Sjack wang pm8001_printk("pdev=0x%p, slot=%s, resuming from previous " 1247dbf9bfe6Sjack wang "operating state [D%d]\n", pdev, pm8001_ha->name, device_state); 1248dbf9bfe6Sjack wang 1249dbf9bfe6Sjack wang pci_set_power_state(pdev, PCI_D0); 1250dbf9bfe6Sjack wang pci_enable_wake(pdev, PCI_D0, 0); 1251dbf9bfe6Sjack wang pci_restore_state(pdev); 1252dbf9bfe6Sjack wang rc = pci_enable_device(pdev); 1253dbf9bfe6Sjack wang if (rc) { 1254dbf9bfe6Sjack wang pm8001_printk("slot=%s Enable device failed during resume\n", 1255dbf9bfe6Sjack wang pm8001_ha->name); 1256dbf9bfe6Sjack wang goto err_out_enable; 1257dbf9bfe6Sjack wang } 1258dbf9bfe6Sjack wang 1259dbf9bfe6Sjack wang pci_set_master(pdev); 1260dbf9bfe6Sjack wang rc = pci_go_44(pdev); 1261dbf9bfe6Sjack wang if (rc) 1262dbf9bfe6Sjack wang goto err_out_disable; 12639f176099SBradley Grove sas_prep_resume_ha(sha); 1264f5860992SSakthivel K /* chip soft rst only for spc */ 1265f5860992SSakthivel K if (pm8001_ha->chip_id == chip_8001) { 1266f5860992SSakthivel K PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1267f5860992SSakthivel K PM8001_INIT_DBG(pm8001_ha, 1268f5860992SSakthivel K pm8001_printk("chip soft reset successful\n")); 1269f5860992SSakthivel K } 1270dbf9bfe6Sjack wang rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); 1271dbf9bfe6Sjack wang if (rc) 1272dbf9bfe6Sjack wang goto err_out_disable; 12731245ee59SSakthivel K 12741245ee59SSakthivel K /* disable all the interrupt bits */ 12751245ee59SSakthivel K PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 12761245ee59SSakthivel K 1277dbf9bfe6Sjack wang rc = pm8001_request_irq(pm8001_ha); 1278dbf9bfe6Sjack wang if (rc) 1279dbf9bfe6Sjack wang goto err_out_disable; 1280dbf9bfe6Sjack wang #ifdef PM8001_USE_TASKLET 12816cd60b37SNikith Ganigarakoppal /* Tasklet for non msi-x interrupt handler */ 1282c913df3fSBenjamin Rood if ((!pdev->msix_cap || !pci_msi_enabled()) || 1283c913df3fSBenjamin Rood (pm8001_ha->chip_id == chip_8001)) 12846cd60b37SNikith Ganigarakoppal tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet, 12856cd60b37SNikith Ganigarakoppal (unsigned long)&(pm8001_ha->irq_vector[0])); 12866cd60b37SNikith Ganigarakoppal else 12876cd60b37SNikith Ganigarakoppal for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 12886cd60b37SNikith Ganigarakoppal tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet, 12896cd60b37SNikith Ganigarakoppal (unsigned long)&(pm8001_ha->irq_vector[j])); 1290dbf9bfe6Sjack wang #endif 1291f74cf271SSakthivel K PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0); 12921245ee59SSakthivel K if (pm8001_ha->chip_id != chip_8001) { 12931245ee59SSakthivel K for (i = 1; i < pm8001_ha->number_of_intr; i++) 12941245ee59SSakthivel K PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i); 12951245ee59SSakthivel K } 1296b650a880SBenjamin Rood 1297b650a880SBenjamin Rood /* Chip documentation for the 8070 and 8072 SPCv */ 1298b650a880SBenjamin Rood /* states that a 500ms minimum delay is required */ 1299014e8ba7SJulia Lawall /* before issuing commands. Otherwise, the firmware */ 1300b650a880SBenjamin Rood /* will enter an unrecoverable state. */ 1301b650a880SBenjamin Rood 1302b650a880SBenjamin Rood if (pm8001_ha->chip_id == chip_8070 || 1303b650a880SBenjamin Rood pm8001_ha->chip_id == chip_8072) { 1304b650a880SBenjamin Rood mdelay(500); 1305b650a880SBenjamin Rood } 1306b650a880SBenjamin Rood 1307b650a880SBenjamin Rood /* Spin up the PHYs */ 1308b650a880SBenjamin Rood 13099f176099SBradley Grove pm8001_ha->flags = PM8001F_RUN_TIME; 13109f176099SBradley Grove for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 13119f176099SBradley Grove pm8001_ha->phy[i].enable_completion = &completion; 13129f176099SBradley Grove PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i); 13139f176099SBradley Grove wait_for_completion(&completion); 13149f176099SBradley Grove } 13159f176099SBradley Grove sas_resume_ha(sha); 1316dbf9bfe6Sjack wang return 0; 1317dbf9bfe6Sjack wang 1318dbf9bfe6Sjack wang err_out_disable: 1319dbf9bfe6Sjack wang scsi_remove_host(pm8001_ha->shost); 1320dbf9bfe6Sjack wang pci_disable_device(pdev); 1321dbf9bfe6Sjack wang err_out_enable: 1322dbf9bfe6Sjack wang return rc; 1323dbf9bfe6Sjack wang } 1324dbf9bfe6Sjack wang 1325e5742101SSakthivel K /* update of pci device, vendor id and driver data with 1326e5742101SSakthivel K * unique value for each of the controller 1327e5742101SSakthivel K */ 13286f039790SGreg Kroah-Hartman static struct pci_device_id pm8001_pci_table[] = { 1329e5742101SSakthivel K { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 }, 1330d8571b1eSSuresh Thiagarajan { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 }, 1331d8571b1eSSuresh Thiagarajan { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 }, 1332f49d2132SBradley Grove { PCI_VDEVICE(ATTO, 0x0042), chip_8001 }, 1333e5742101SSakthivel K /* Support for SPC/SPCv/SPCve controllers */ 1334e5742101SSakthivel K { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 }, 1335e5742101SSakthivel K { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 }, 1336e5742101SSakthivel K { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 }, 1337e5742101SSakthivel K { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 }, 1338e5742101SSakthivel K { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 }, 1339e5742101SSakthivel K { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 }, 1340e5742101SSakthivel K { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 }, 1341e5742101SSakthivel K { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 }, 1342e5742101SSakthivel K { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 }, 1343a9a923e5SAnand Kumar Santhanam { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 }, 1344a9a923e5SAnand Kumar Santhanam { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 }, 1345a9a923e5SAnand Kumar Santhanam { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 }, 1346a9a923e5SAnand Kumar Santhanam { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 }, 1347a9a923e5SAnand Kumar Santhanam { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 }, 1348a9a923e5SAnand Kumar Santhanam { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 }, 1349e5742101SSakthivel K { PCI_VENDOR_ID_ADAPTEC2, 0x8081, 1350e5742101SSakthivel K PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 }, 1351e5742101SSakthivel K { PCI_VENDOR_ID_ADAPTEC2, 0x8081, 1352e5742101SSakthivel K PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 }, 1353e5742101SSakthivel K { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1354e5742101SSakthivel K PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 }, 1355e5742101SSakthivel K { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1356e5742101SSakthivel K PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 }, 1357e5742101SSakthivel K { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1358e5742101SSakthivel K PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 }, 1359e5742101SSakthivel K { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1360e5742101SSakthivel K PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 }, 1361e5742101SSakthivel K { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1362e5742101SSakthivel K PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 }, 1363e5742101SSakthivel K { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1364e5742101SSakthivel K PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 }, 1365e5742101SSakthivel K { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1366e5742101SSakthivel K PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 }, 1367e5742101SSakthivel K { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1368e5742101SSakthivel K PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 }, 1369a9a923e5SAnand Kumar Santhanam { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1370a9a923e5SAnand Kumar Santhanam PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 }, 1371a9a923e5SAnand Kumar Santhanam { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1372a9a923e5SAnand Kumar Santhanam PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 }, 1373a9a923e5SAnand Kumar Santhanam { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1374a9a923e5SAnand Kumar Santhanam PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 }, 1375a9a923e5SAnand Kumar Santhanam { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1376a9a923e5SAnand Kumar Santhanam PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 }, 1377a9a923e5SAnand Kumar Santhanam { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1378a9a923e5SAnand Kumar Santhanam PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 }, 1379a9a923e5SAnand Kumar Santhanam { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1380a9a923e5SAnand Kumar Santhanam PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 }, 1381a9a923e5SAnand Kumar Santhanam { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1382a9a923e5SAnand Kumar Santhanam PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 }, 1383a9a923e5SAnand Kumar Santhanam { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1384a9a923e5SAnand Kumar Santhanam PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 }, 1385a9a923e5SAnand Kumar Santhanam { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1386a9a923e5SAnand Kumar Santhanam PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 }, 1387b2dece48SBenjamin Rood { PCI_VENDOR_ID_ATTO, 0x8070, 1388b2dece48SBenjamin Rood PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 }, 1389b2dece48SBenjamin Rood { PCI_VENDOR_ID_ATTO, 0x8070, 1390b2dece48SBenjamin Rood PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 }, 1391b2dece48SBenjamin Rood { PCI_VENDOR_ID_ATTO, 0x8072, 1392b2dece48SBenjamin Rood PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 }, 1393b2dece48SBenjamin Rood { PCI_VENDOR_ID_ATTO, 0x8072, 1394b2dece48SBenjamin Rood PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 }, 1395b2dece48SBenjamin Rood { PCI_VENDOR_ID_ATTO, 0x8070, 1396b2dece48SBenjamin Rood PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 }, 1397b2dece48SBenjamin Rood { PCI_VENDOR_ID_ATTO, 0x8072, 1398b2dece48SBenjamin Rood PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 }, 1399b2dece48SBenjamin Rood { PCI_VENDOR_ID_ATTO, 0x8072, 1400b2dece48SBenjamin Rood PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 }, 1401dbf9bfe6Sjack wang {} /* terminate list */ 1402dbf9bfe6Sjack wang }; 1403dbf9bfe6Sjack wang 1404dbf9bfe6Sjack wang static struct pci_driver pm8001_pci_driver = { 1405dbf9bfe6Sjack wang .name = DRV_NAME, 1406dbf9bfe6Sjack wang .id_table = pm8001_pci_table, 1407dbf9bfe6Sjack wang .probe = pm8001_pci_probe, 14086f039790SGreg Kroah-Hartman .remove = pm8001_pci_remove, 1409dbf9bfe6Sjack wang .suspend = pm8001_pci_suspend, 1410dbf9bfe6Sjack wang .resume = pm8001_pci_resume, 1411dbf9bfe6Sjack wang }; 1412dbf9bfe6Sjack wang 1413dbf9bfe6Sjack wang /** 1414dbf9bfe6Sjack wang * pm8001_init - initialize scsi transport template 1415dbf9bfe6Sjack wang */ 1416dbf9bfe6Sjack wang static int __init pm8001_init(void) 1417dbf9bfe6Sjack wang { 1418429305e4STejun Heo int rc = -ENOMEM; 1419429305e4STejun Heo 1420a70b8fc3SSakthivel K pm8001_wq = alloc_workqueue("pm80xx", 0, 0); 1421429305e4STejun Heo if (!pm8001_wq) 1422429305e4STejun Heo goto err; 1423429305e4STejun Heo 1424dbf9bfe6Sjack wang pm8001_id = 0; 1425dbf9bfe6Sjack wang pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops); 1426dbf9bfe6Sjack wang if (!pm8001_stt) 1427429305e4STejun Heo goto err_wq; 1428dbf9bfe6Sjack wang rc = pci_register_driver(&pm8001_pci_driver); 1429dbf9bfe6Sjack wang if (rc) 1430429305e4STejun Heo goto err_tp; 1431dbf9bfe6Sjack wang return 0; 1432429305e4STejun Heo 1433429305e4STejun Heo err_tp: 1434dbf9bfe6Sjack wang sas_release_transport(pm8001_stt); 1435429305e4STejun Heo err_wq: 1436429305e4STejun Heo destroy_workqueue(pm8001_wq); 1437429305e4STejun Heo err: 1438dbf9bfe6Sjack wang return rc; 1439dbf9bfe6Sjack wang } 1440dbf9bfe6Sjack wang 1441dbf9bfe6Sjack wang static void __exit pm8001_exit(void) 1442dbf9bfe6Sjack wang { 1443dbf9bfe6Sjack wang pci_unregister_driver(&pm8001_pci_driver); 1444dbf9bfe6Sjack wang sas_release_transport(pm8001_stt); 1445429305e4STejun Heo destroy_workqueue(pm8001_wq); 1446dbf9bfe6Sjack wang } 1447dbf9bfe6Sjack wang 1448dbf9bfe6Sjack wang module_init(pm8001_init); 1449dbf9bfe6Sjack wang module_exit(pm8001_exit); 1450dbf9bfe6Sjack wang 1451dbf9bfe6Sjack wang MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>"); 1452a9a923e5SAnand Kumar Santhanam MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>"); 1453a9a923e5SAnand Kumar Santhanam MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>"); 145494f33c16SNikith Ganigarakoppal MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>"); 1455e5742101SSakthivel K MODULE_DESCRIPTION( 1456db9d4034SBenjamin Rood "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 " 1457a9a923e5SAnand Kumar Santhanam "SAS/SATA controller driver"); 1458dbf9bfe6Sjack wang MODULE_VERSION(DRV_VERSION); 1459dbf9bfe6Sjack wang MODULE_LICENSE("GPL"); 1460dbf9bfe6Sjack wang MODULE_DEVICE_TABLE(pci, pm8001_pci_table); 1461dbf9bfe6Sjack wang 1462