1 /* 2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 USI Co., Ltd. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 #ifndef _PMC8001_REG_H_ 41 #define _PMC8001_REG_H_ 42 43 #include <linux/types.h> 44 #include <scsi/libsas.h> 45 46 47 /* for Request Opcode of IOMB */ 48 #define OPC_INB_ECHO 1 /* 0x000 */ 49 #define OPC_INB_PHYSTART 4 /* 0x004 */ 50 #define OPC_INB_PHYSTOP 5 /* 0x005 */ 51 #define OPC_INB_SSPINIIOSTART 6 /* 0x006 */ 52 #define OPC_INB_SSPINITMSTART 7 /* 0x007 */ 53 #define OPC_INB_SSPINIEXTIOSTART 8 /* 0x008 */ 54 #define OPC_INB_DEV_HANDLE_ACCEPT 9 /* 0x009 */ 55 #define OPC_INB_SSPTGTIOSTART 10 /* 0x00A */ 56 #define OPC_INB_SSPTGTRSPSTART 11 /* 0x00B */ 57 #define OPC_INB_SSPINIEDCIOSTART 12 /* 0x00C */ 58 #define OPC_INB_SSPINIEXTEDCIOSTART 13 /* 0x00D */ 59 #define OPC_INB_SSPTGTEDCIOSTART 14 /* 0x00E */ 60 #define OPC_INB_SSP_ABORT 15 /* 0x00F */ 61 #define OPC_INB_DEREG_DEV_HANDLE 16 /* 0x010 */ 62 #define OPC_INB_GET_DEV_HANDLE 17 /* 0x011 */ 63 #define OPC_INB_SMP_REQUEST 18 /* 0x012 */ 64 /* SMP_RESPONSE is removed */ 65 #define OPC_INB_SMP_RESPONSE 19 /* 0x013 */ 66 #define OPC_INB_SMP_ABORT 20 /* 0x014 */ 67 #define OPC_INB_REG_DEV 22 /* 0x016 */ 68 #define OPC_INB_SATA_HOST_OPSTART 23 /* 0x017 */ 69 #define OPC_INB_SATA_ABORT 24 /* 0x018 */ 70 #define OPC_INB_LOCAL_PHY_CONTROL 25 /* 0x019 */ 71 #define OPC_INB_GET_DEV_INFO 26 /* 0x01A */ 72 #define OPC_INB_FW_FLASH_UPDATE 32 /* 0x020 */ 73 #define OPC_INB_GPIO 34 /* 0x022 */ 74 #define OPC_INB_SAS_DIAG_MODE_START_END 35 /* 0x023 */ 75 #define OPC_INB_SAS_DIAG_EXECUTE 36 /* 0x024 */ 76 #define OPC_INB_SAS_HW_EVENT_ACK 37 /* 0x025 */ 77 #define OPC_INB_GET_TIME_STAMP 38 /* 0x026 */ 78 #define OPC_INB_PORT_CONTROL 39 /* 0x027 */ 79 #define OPC_INB_GET_NVMD_DATA 40 /* 0x028 */ 80 #define OPC_INB_SET_NVMD_DATA 41 /* 0x029 */ 81 #define OPC_INB_SET_DEVICE_STATE 42 /* 0x02A */ 82 #define OPC_INB_GET_DEVICE_STATE 43 /* 0x02B */ 83 #define OPC_INB_SET_DEV_INFO 44 /* 0x02C */ 84 #define OPC_INB_SAS_RE_INITIALIZE 45 /* 0x02D */ 85 86 /* for Response Opcode of IOMB */ 87 #define OPC_OUB_ECHO 1 /* 0x001 */ 88 #define OPC_OUB_HW_EVENT 4 /* 0x004 */ 89 #define OPC_OUB_SSP_COMP 5 /* 0x005 */ 90 #define OPC_OUB_SMP_COMP 6 /* 0x006 */ 91 #define OPC_OUB_LOCAL_PHY_CNTRL 7 /* 0x007 */ 92 #define OPC_OUB_DEV_REGIST 10 /* 0x00A */ 93 #define OPC_OUB_DEREG_DEV 11 /* 0x00B */ 94 #define OPC_OUB_GET_DEV_HANDLE 12 /* 0x00C */ 95 #define OPC_OUB_SATA_COMP 13 /* 0x00D */ 96 #define OPC_OUB_SATA_EVENT 14 /* 0x00E */ 97 #define OPC_OUB_SSP_EVENT 15 /* 0x00F */ 98 #define OPC_OUB_DEV_HANDLE_ARRIV 16 /* 0x010 */ 99 /* SMP_RECEIVED Notification is removed */ 100 #define OPC_OUB_SMP_RECV_EVENT 17 /* 0x011 */ 101 #define OPC_OUB_SSP_RECV_EVENT 18 /* 0x012 */ 102 #define OPC_OUB_DEV_INFO 19 /* 0x013 */ 103 #define OPC_OUB_FW_FLASH_UPDATE 20 /* 0x014 */ 104 #define OPC_OUB_GPIO_RESPONSE 22 /* 0x016 */ 105 #define OPC_OUB_GPIO_EVENT 23 /* 0x017 */ 106 #define OPC_OUB_GENERAL_EVENT 24 /* 0x018 */ 107 #define OPC_OUB_SSP_ABORT_RSP 26 /* 0x01A */ 108 #define OPC_OUB_SATA_ABORT_RSP 27 /* 0x01B */ 109 #define OPC_OUB_SAS_DIAG_MODE_START_END 28 /* 0x01C */ 110 #define OPC_OUB_SAS_DIAG_EXECUTE 29 /* 0x01D */ 111 #define OPC_OUB_GET_TIME_STAMP 30 /* 0x01E */ 112 #define OPC_OUB_SAS_HW_EVENT_ACK 31 /* 0x01F */ 113 #define OPC_OUB_PORT_CONTROL 32 /* 0x020 */ 114 #define OPC_OUB_SKIP_ENTRY 33 /* 0x021 */ 115 #define OPC_OUB_SMP_ABORT_RSP 34 /* 0x022 */ 116 #define OPC_OUB_GET_NVMD_DATA 35 /* 0x023 */ 117 #define OPC_OUB_SET_NVMD_DATA 36 /* 0x024 */ 118 #define OPC_OUB_DEVICE_HANDLE_REMOVAL 37 /* 0x025 */ 119 #define OPC_OUB_SET_DEVICE_STATE 38 /* 0x026 */ 120 #define OPC_OUB_GET_DEVICE_STATE 39 /* 0x027 */ 121 #define OPC_OUB_SET_DEV_INFO 40 /* 0x028 */ 122 #define OPC_OUB_SAS_RE_INITIALIZE 41 /* 0x029 */ 123 124 /* for phy start*/ 125 #define SPINHOLD_DISABLE (0x00 << 14) 126 #define SPINHOLD_ENABLE (0x01 << 14) 127 #define LINKMODE_SAS (0x01 << 12) 128 #define LINKMODE_DSATA (0x02 << 12) 129 #define LINKMODE_AUTO (0x03 << 12) 130 #define LINKRATE_15 (0x01 << 8) 131 #define LINKRATE_30 (0x02 << 8) 132 #define LINKRATE_60 (0x04 << 8) 133 134 struct mpi_msg_hdr{ 135 __le32 header; /* Bits [11:0] - Message operation code */ 136 /* Bits [15:12] - Message Category */ 137 /* Bits [21:16] - Outboundqueue ID for the 138 operation completion message */ 139 /* Bits [23:22] - Reserved */ 140 /* Bits [28:24] - Buffer Count, indicates how 141 many buffer are allocated for the massage */ 142 /* Bits [30:29] - Reserved */ 143 /* Bits [31] - Message Valid bit */ 144 } __attribute__((packed, aligned(4))); 145 146 147 /* 148 * brief the data structure of PHY Start Command 149 * use to describe enable the phy (64 bytes) 150 */ 151 struct phy_start_req { 152 __le32 tag; 153 __le32 ase_sh_lm_slr_phyid; 154 struct sas_identify_frame sas_identify; 155 u32 reserved[5]; 156 } __attribute__((packed, aligned(4))); 157 158 159 /* 160 * brief the data structure of PHY Start Command 161 * use to disable the phy (64 bytes) 162 */ 163 struct phy_stop_req { 164 __le32 tag; 165 __le32 phy_id; 166 u32 reserved[13]; 167 } __attribute__((packed, aligned(4))); 168 169 170 /* set device bits fis - device to host */ 171 struct set_dev_bits_fis { 172 u8 fis_type; /* 0xA1*/ 173 u8 n_i_pmport; 174 /* b7 : n Bit. Notification bit. If set device needs attention. */ 175 /* b6 : i Bit. Interrupt Bit */ 176 /* b5-b4: reserved2 */ 177 /* b3-b0: PM Port */ 178 u8 status; 179 u8 error; 180 u32 _r_a; 181 } __attribute__ ((packed)); 182 /* PIO setup FIS - device to host */ 183 struct pio_setup_fis { 184 u8 fis_type; /* 0x5f */ 185 u8 i_d_pmPort; 186 /* b7 : reserved */ 187 /* b6 : i bit. Interrupt bit */ 188 /* b5 : d bit. data transfer direction. set to 1 for device to host 189 xfer */ 190 /* b4 : reserved */ 191 /* b3-b0: PM Port */ 192 u8 status; 193 u8 error; 194 u8 lbal; 195 u8 lbam; 196 u8 lbah; 197 u8 device; 198 u8 lbal_exp; 199 u8 lbam_exp; 200 u8 lbah_exp; 201 u8 _r_a; 202 u8 sector_count; 203 u8 sector_count_exp; 204 u8 _r_b; 205 u8 e_status; 206 u8 _r_c[2]; 207 u8 transfer_count; 208 } __attribute__ ((packed)); 209 210 /* 211 * brief the data structure of SATA Completion Response 212 * use to describe the sata task response (64 bytes) 213 */ 214 struct sata_completion_resp { 215 __le32 tag; 216 __le32 status; 217 __le32 param; 218 u32 sata_resp[12]; 219 } __attribute__((packed, aligned(4))); 220 221 222 /* 223 * brief the data structure of SAS HW Event Notification 224 * use to alert the host about the hardware event(64 bytes) 225 */ 226 struct hw_event_resp { 227 __le32 lr_evt_status_phyid_portid; 228 __le32 evt_param; 229 __le32 npip_portstate; 230 struct sas_identify_frame sas_identify; 231 struct dev_to_host_fis sata_fis; 232 } __attribute__((packed, aligned(4))); 233 234 235 /* 236 * brief the data structure of REGISTER DEVICE Command 237 * use to describe MPI REGISTER DEVICE Command (64 bytes) 238 */ 239 240 struct reg_dev_req { 241 __le32 tag; 242 __le32 phyid_portid; 243 __le32 dtype_dlr_retry; 244 __le32 firstburstsize_ITNexustimeout; 245 u8 sas_addr[SAS_ADDR_SIZE]; 246 __le32 upper_device_id; 247 u32 reserved[8]; 248 } __attribute__((packed, aligned(4))); 249 250 251 /* 252 * brief the data structure of DEREGISTER DEVICE Command 253 * use to request spc to remove all internal resources associated 254 * with the device id (64 bytes) 255 */ 256 257 struct dereg_dev_req { 258 __le32 tag; 259 __le32 device_id; 260 u32 reserved[13]; 261 } __attribute__((packed, aligned(4))); 262 263 264 /* 265 * brief the data structure of DEVICE_REGISTRATION Response 266 * use to notify the completion of the device registration (64 bytes) 267 */ 268 269 struct dev_reg_resp { 270 __le32 tag; 271 __le32 status; 272 __le32 device_id; 273 u32 reserved[12]; 274 } __attribute__((packed, aligned(4))); 275 276 277 /* 278 * brief the data structure of Local PHY Control Command 279 * use to issue PHY CONTROL to local phy (64 bytes) 280 */ 281 struct local_phy_ctl_req { 282 __le32 tag; 283 __le32 phyop_phyid; 284 u32 reserved1[13]; 285 } __attribute__((packed, aligned(4))); 286 287 288 /** 289 * brief the data structure of Local Phy Control Response 290 * use to describe MPI Local Phy Control Response (64 bytes) 291 */ 292 struct local_phy_ctl_resp { 293 __le32 tag; 294 __le32 phyop_phyid; 295 __le32 status; 296 u32 reserved[12]; 297 } __attribute__((packed, aligned(4))); 298 299 300 #define OP_BITS 0x0000FF00 301 #define ID_BITS 0x0000000F 302 303 /* 304 * brief the data structure of PORT Control Command 305 * use to control port properties (64 bytes) 306 */ 307 308 struct port_ctl_req { 309 __le32 tag; 310 __le32 portop_portid; 311 __le32 param0; 312 __le32 param1; 313 u32 reserved1[11]; 314 } __attribute__((packed, aligned(4))); 315 316 317 /* 318 * brief the data structure of HW Event Ack Command 319 * use to acknowledge receive HW event (64 bytes) 320 */ 321 322 struct hw_event_ack_req { 323 __le32 tag; 324 __le32 sea_phyid_portid; 325 __le32 param0; 326 __le32 param1; 327 u32 reserved1[11]; 328 } __attribute__((packed, aligned(4))); 329 330 331 /* 332 * brief the data structure of SSP Completion Response 333 * use to indicate a SSP Completion (n bytes) 334 */ 335 struct ssp_completion_resp { 336 __le32 tag; 337 __le32 status; 338 __le32 param; 339 __le32 ssptag_rescv_rescpad; 340 struct ssp_response_iu ssp_resp_iu; 341 __le32 residual_count; 342 } __attribute__((packed, aligned(4))); 343 344 345 #define SSP_RESCV_BIT 0x00010000 346 347 /* 348 * brief the data structure of SATA EVNET esponse 349 * use to indicate a SATA Completion (64 bytes) 350 */ 351 352 struct sata_event_resp { 353 __le32 tag; 354 __le32 event; 355 __le32 port_id; 356 __le32 device_id; 357 u32 reserved[11]; 358 } __attribute__((packed, aligned(4))); 359 360 /* 361 * brief the data structure of SSP EVNET esponse 362 * use to indicate a SSP Completion (64 bytes) 363 */ 364 365 struct ssp_event_resp { 366 __le32 tag; 367 __le32 event; 368 __le32 port_id; 369 __le32 device_id; 370 u32 reserved[11]; 371 } __attribute__((packed, aligned(4))); 372 373 /** 374 * brief the data structure of General Event Notification Response 375 * use to describe MPI General Event Notification Response (64 bytes) 376 */ 377 struct general_event_resp { 378 __le32 status; 379 __le32 inb_IOMB_payload[14]; 380 } __attribute__((packed, aligned(4))); 381 382 383 #define GENERAL_EVENT_PAYLOAD 14 384 #define OPCODE_BITS 0x00000fff 385 386 /* 387 * brief the data structure of SMP Request Command 388 * use to describe MPI SMP REQUEST Command (64 bytes) 389 */ 390 struct smp_req { 391 __le32 tag; 392 __le32 device_id; 393 __le32 len_ip_ir; 394 /* Bits [0] - Indirect response */ 395 /* Bits [1] - Indirect Payload */ 396 /* Bits [15:2] - Reserved */ 397 /* Bits [23:16] - direct payload Len */ 398 /* Bits [31:24] - Reserved */ 399 u8 smp_req16[16]; 400 union { 401 u8 smp_req[32]; 402 struct { 403 __le64 long_req_addr;/* sg dma address, LE */ 404 __le32 long_req_size;/* LE */ 405 u32 _r_a; 406 __le64 long_resp_addr;/* sg dma address, LE */ 407 __le32 long_resp_size;/* LE */ 408 u32 _r_b; 409 } long_smp_req;/* sequencer extension */ 410 }; 411 } __attribute__((packed, aligned(4))); 412 /* 413 * brief the data structure of SMP Completion Response 414 * use to describe MPI SMP Completion Response (64 bytes) 415 */ 416 struct smp_completion_resp { 417 __le32 tag; 418 __le32 status; 419 __le32 param; 420 __le32 _r_a[12]; 421 } __attribute__((packed, aligned(4))); 422 423 /* 424 *brief the data structure of SSP SMP SATA Abort Command 425 * use to describe MPI SSP SMP & SATA Abort Command (64 bytes) 426 */ 427 struct task_abort_req { 428 __le32 tag; 429 __le32 device_id; 430 __le32 tag_to_abort; 431 __le32 abort_all; 432 u32 reserved[11]; 433 } __attribute__((packed, aligned(4))); 434 435 /* These flags used for SSP SMP & SATA Abort */ 436 #define ABORT_MASK 0x3 437 #define ABORT_SINGLE 0x0 438 #define ABORT_ALL 0x1 439 440 /** 441 * brief the data structure of SSP SATA SMP Abort Response 442 * use to describe SSP SMP & SATA Abort Response ( 64 bytes) 443 */ 444 struct task_abort_resp { 445 __le32 tag; 446 __le32 status; 447 __le32 scp; 448 u32 reserved[12]; 449 } __attribute__((packed, aligned(4))); 450 451 452 /** 453 * brief the data structure of SAS Diagnostic Start/End Command 454 * use to describe MPI SAS Diagnostic Start/End Command (64 bytes) 455 */ 456 struct sas_diag_start_end_req { 457 __le32 tag; 458 __le32 operation_phyid; 459 u32 reserved[13]; 460 } __attribute__((packed, aligned(4))); 461 462 463 /** 464 * brief the data structure of SAS Diagnostic Execute Command 465 * use to describe MPI SAS Diagnostic Execute Command (64 bytes) 466 */ 467 struct sas_diag_execute_req{ 468 __le32 tag; 469 __le32 cmdtype_cmddesc_phyid; 470 __le32 pat1_pat2; 471 __le32 threshold; 472 __le32 codepat_errmsk; 473 __le32 pmon; 474 __le32 pERF1CTL; 475 u32 reserved[8]; 476 } __attribute__((packed, aligned(4))); 477 478 479 #define SAS_DIAG_PARAM_BYTES 24 480 481 /* 482 * brief the data structure of Set Device State Command 483 * use to describe MPI Set Device State Command (64 bytes) 484 */ 485 struct set_dev_state_req { 486 __le32 tag; 487 __le32 device_id; 488 __le32 nds; 489 u32 reserved[12]; 490 } __attribute__((packed, aligned(4))); 491 492 /* 493 * brief the data structure of sas_re_initialization 494 */ 495 struct sas_re_initialization_req { 496 497 __le32 tag; 498 __le32 SSAHOLT;/* bit29-set max port; 499 ** bit28-set open reject cmd retries. 500 ** bit27-set open reject data retries. 501 ** bit26-set open reject option, remap:1 or not:0. 502 ** bit25-set sata head of line time out. 503 */ 504 __le32 reserved_maxPorts; 505 __le32 open_reject_cmdretries_data_retries;/* cmd retries: 31-bit16; 506 * data retries: bit15-bit0. 507 */ 508 __le32 sata_hol_tmo; 509 u32 reserved1[10]; 510 } __attribute__((packed, aligned(4))); 511 512 /* 513 * brief the data structure of SATA Start Command 514 * use to describe MPI SATA IO Start Command (64 bytes) 515 */ 516 517 struct sata_start_req { 518 __le32 tag; 519 __le32 device_id; 520 __le32 data_len; 521 __le32 ncqtag_atap_dir_m; 522 struct host_to_dev_fis sata_fis; 523 u32 reserved1; 524 u32 reserved2; 525 u32 addr_low; 526 u32 addr_high; 527 __le32 len; 528 __le32 esgl; 529 } __attribute__((packed, aligned(4))); 530 531 /** 532 * brief the data structure of SSP INI TM Start Command 533 * use to describe MPI SSP INI TM Start Command (64 bytes) 534 */ 535 struct ssp_ini_tm_start_req { 536 __le32 tag; 537 __le32 device_id; 538 __le32 relate_tag; 539 __le32 tmf; 540 u8 lun[8]; 541 __le32 ds_ads_m; 542 u32 reserved[8]; 543 } __attribute__((packed, aligned(4))); 544 545 546 struct ssp_info_unit { 547 u8 lun[8];/* SCSI Logical Unit Number */ 548 u8 reserved1;/* reserved */ 549 u8 efb_prio_attr; 550 /* B7 : enabledFirstBurst */ 551 /* B6-3 : taskPriority */ 552 /* B2-0 : taskAttribute */ 553 u8 reserved2; /* reserved */ 554 u8 additional_cdb_len; 555 /* B7-2 : additional_cdb_len */ 556 /* B1-0 : reserved */ 557 u8 cdb[16];/* The SCSI CDB up to 16 bytes length */ 558 } __attribute__((packed, aligned(4))); 559 560 561 /** 562 * brief the data structure of SSP INI IO Start Command 563 * use to describe MPI SSP INI IO Start Command (64 bytes) 564 */ 565 struct ssp_ini_io_start_req { 566 __le32 tag; 567 __le32 device_id; 568 __le32 data_len; 569 __le32 dir_m_tlr; 570 struct ssp_info_unit ssp_iu; 571 __le32 addr_low; 572 __le32 addr_high; 573 __le32 len; 574 __le32 esgl; 575 } __attribute__((packed, aligned(4))); 576 577 578 /** 579 * brief the data structure of Firmware download 580 * use to describe MPI FW DOWNLOAD Command (64 bytes) 581 */ 582 struct fw_flash_Update_req { 583 __le32 tag; 584 __le32 cur_image_offset; 585 __le32 cur_image_len; 586 __le32 total_image_len; 587 u32 reserved0[7]; 588 __le32 sgl_addr_lo; 589 __le32 sgl_addr_hi; 590 __le32 len; 591 __le32 ext_reserved; 592 } __attribute__((packed, aligned(4))); 593 594 595 #define FWFLASH_IOMB_RESERVED_LEN 0x07 596 /** 597 * brief the data structure of FW_FLASH_UPDATE Response 598 * use to describe MPI FW_FLASH_UPDATE Response (64 bytes) 599 * 600 */ 601 struct fw_flash_Update_resp { 602 __le32 tag; 603 __le32 status; 604 u32 reserved[13]; 605 } __attribute__((packed, aligned(4))); 606 607 608 /** 609 * brief the data structure of Get NVM Data Command 610 * use to get data from NVM in HBA(64 bytes) 611 */ 612 struct get_nvm_data_req { 613 __le32 tag; 614 __le32 len_ir_vpdd; 615 __le32 vpd_offset; 616 u32 reserved[8]; 617 __le32 resp_addr_lo; 618 __le32 resp_addr_hi; 619 __le32 resp_len; 620 u32 reserved1; 621 } __attribute__((packed, aligned(4))); 622 623 624 struct set_nvm_data_req { 625 __le32 tag; 626 __le32 len_ir_vpdd; 627 __le32 vpd_offset; 628 __le32 reserved[8]; 629 __le32 resp_addr_lo; 630 __le32 resp_addr_hi; 631 __le32 resp_len; 632 u32 reserved1; 633 } __attribute__((packed, aligned(4))); 634 635 636 #define TWI_DEVICE 0x0 637 #define C_SEEPROM 0x1 638 #define VPD_FLASH 0x4 639 #define AAP1_RDUMP 0x5 640 #define IOP_RDUMP 0x6 641 #define EXPAN_ROM 0x7 642 643 #define IPMode 0x80000000 644 #define NVMD_TYPE 0x0000000F 645 #define NVMD_STAT 0x0000FFFF 646 #define NVMD_LEN 0xFF000000 647 /** 648 * brief the data structure of Get NVMD Data Response 649 * use to describe MPI Get NVMD Data Response (64 bytes) 650 */ 651 struct get_nvm_data_resp { 652 __le32 tag; 653 __le32 ir_tda_bn_dps_das_nvm; 654 __le32 dlen_status; 655 __le32 nvm_data[12]; 656 } __attribute__((packed, aligned(4))); 657 658 659 /** 660 * brief the data structure of SAS Diagnostic Start/End Response 661 * use to describe MPI SAS Diagnostic Start/End Response (64 bytes) 662 * 663 */ 664 struct sas_diag_start_end_resp { 665 __le32 tag; 666 __le32 status; 667 u32 reserved[13]; 668 } __attribute__((packed, aligned(4))); 669 670 671 /** 672 * brief the data structure of SAS Diagnostic Execute Response 673 * use to describe MPI SAS Diagnostic Execute Response (64 bytes) 674 * 675 */ 676 struct sas_diag_execute_resp { 677 __le32 tag; 678 __le32 cmdtype_cmddesc_phyid; 679 __le32 Status; 680 __le32 ReportData; 681 u32 reserved[11]; 682 } __attribute__((packed, aligned(4))); 683 684 685 /** 686 * brief the data structure of Set Device State Response 687 * use to describe MPI Set Device State Response (64 bytes) 688 * 689 */ 690 struct set_dev_state_resp { 691 __le32 tag; 692 __le32 status; 693 __le32 device_id; 694 __le32 pds_nds; 695 u32 reserved[11]; 696 } __attribute__((packed, aligned(4))); 697 698 699 #define NDS_BITS 0x0F 700 #define PDS_BITS 0xF0 701 702 /* 703 * HW Events type 704 */ 705 706 #define HW_EVENT_RESET_START 0x01 707 #define HW_EVENT_CHIP_RESET_COMPLETE 0x02 708 #define HW_EVENT_PHY_STOP_STATUS 0x03 709 #define HW_EVENT_SAS_PHY_UP 0x04 710 #define HW_EVENT_SATA_PHY_UP 0x05 711 #define HW_EVENT_SATA_SPINUP_HOLD 0x06 712 #define HW_EVENT_PHY_DOWN 0x07 713 #define HW_EVENT_PORT_INVALID 0x08 714 #define HW_EVENT_BROADCAST_CHANGE 0x09 715 #define HW_EVENT_PHY_ERROR 0x0A 716 #define HW_EVENT_BROADCAST_SES 0x0B 717 #define HW_EVENT_INBOUND_CRC_ERROR 0x0C 718 #define HW_EVENT_HARD_RESET_RECEIVED 0x0D 719 #define HW_EVENT_MALFUNCTION 0x0E 720 #define HW_EVENT_ID_FRAME_TIMEOUT 0x0F 721 #define HW_EVENT_BROADCAST_EXP 0x10 722 #define HW_EVENT_PHY_START_STATUS 0x11 723 #define HW_EVENT_LINK_ERR_INVALID_DWORD 0x12 724 #define HW_EVENT_LINK_ERR_DISPARITY_ERROR 0x13 725 #define HW_EVENT_LINK_ERR_CODE_VIOLATION 0x14 726 #define HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH 0x15 727 #define HW_EVENT_LINK_ERR_PHY_RESET_FAILED 0x16 728 #define HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17 729 #define HW_EVENT_PORT_RECOVER 0x18 730 #define HW_EVENT_PORT_RESET_TIMER_TMO 0x19 731 #define HW_EVENT_PORT_RESET_COMPLETE 0x20 732 #define EVENT_BROADCAST_ASYNCH_EVENT 0x21 733 734 /* port state */ 735 #define PORT_NOT_ESTABLISHED 0x00 736 #define PORT_VALID 0x01 737 #define PORT_LOSTCOMM 0x02 738 #define PORT_IN_RESET 0x04 739 #define PORT_INVALID 0x08 740 741 /* 742 * SSP/SMP/SATA IO Completion Status values 743 */ 744 745 #define IO_SUCCESS 0x00 746 #define IO_ABORTED 0x01 747 #define IO_OVERFLOW 0x02 748 #define IO_UNDERFLOW 0x03 749 #define IO_FAILED 0x04 750 #define IO_ABORT_RESET 0x05 751 #define IO_NOT_VALID 0x06 752 #define IO_NO_DEVICE 0x07 753 #define IO_ILLEGAL_PARAMETER 0x08 754 #define IO_LINK_FAILURE 0x09 755 #define IO_PROG_ERROR 0x0A 756 #define IO_EDC_IN_ERROR 0x0B 757 #define IO_EDC_OUT_ERROR 0x0C 758 #define IO_ERROR_HW_TIMEOUT 0x0D 759 #define IO_XFER_ERROR_BREAK 0x0E 760 #define IO_XFER_ERROR_PHY_NOT_READY 0x0F 761 #define IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED 0x10 762 #define IO_OPEN_CNX_ERROR_ZONE_VIOLATION 0x11 763 #define IO_OPEN_CNX_ERROR_BREAK 0x12 764 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS 0x13 765 #define IO_OPEN_CNX_ERROR_BAD_DESTINATION 0x14 766 #define IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED 0x15 767 #define IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY 0x16 768 #define IO_OPEN_CNX_ERROR_WRONG_DESTINATION 0x17 769 #define IO_OPEN_CNX_ERROR_UNKNOWN_ERROR 0x18 770 #define IO_XFER_ERROR_NAK_RECEIVED 0x19 771 #define IO_XFER_ERROR_ACK_NAK_TIMEOUT 0x1A 772 #define IO_XFER_ERROR_PEER_ABORTED 0x1B 773 #define IO_XFER_ERROR_RX_FRAME 0x1C 774 #define IO_XFER_ERROR_DMA 0x1D 775 #define IO_XFER_ERROR_CREDIT_TIMEOUT 0x1E 776 #define IO_XFER_ERROR_SATA_LINK_TIMEOUT 0x1F 777 #define IO_XFER_ERROR_SATA 0x20 778 #define IO_XFER_ERROR_ABORTED_DUE_TO_SRST 0x22 779 #define IO_XFER_ERROR_REJECTED_NCQ_MODE 0x21 780 #define IO_XFER_ERROR_ABORTED_NCQ_MODE 0x23 781 #define IO_XFER_OPEN_RETRY_TIMEOUT 0x24 782 #define IO_XFER_SMP_RESP_CONNECTION_ERROR 0x25 783 #define IO_XFER_ERROR_UNEXPECTED_PHASE 0x26 784 #define IO_XFER_ERROR_XFER_RDY_OVERRUN 0x27 785 #define IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED 0x28 786 787 #define IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT 0x30 788 #define IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK 0x31 789 #define IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK 0x32 790 791 #define IO_XFER_ERROR_OFFSET_MISMATCH 0x34 792 #define IO_XFER_ERROR_XFER_ZERO_DATA_LEN 0x35 793 #define IO_XFER_CMD_FRAME_ISSUED 0x36 794 #define IO_ERROR_INTERNAL_SMP_RESOURCE 0x37 795 #define IO_PORT_IN_RESET 0x38 796 #define IO_DS_NON_OPERATIONAL 0x39 797 #define IO_DS_IN_RECOVERY 0x3A 798 #define IO_TM_TAG_NOT_FOUND 0x3B 799 #define IO_XFER_PIO_SETUP_ERROR 0x3C 800 #define IO_SSP_EXT_IU_ZERO_LEN_ERROR 0x3D 801 #define IO_DS_IN_ERROR 0x3E 802 #define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY 0x3F 803 #define IO_ABORT_IN_PROGRESS 0x40 804 #define IO_ABORT_DELAYED 0x41 805 #define IO_INVALID_LENGTH 0x42 806 807 /* WARNING: This error code must always be the last number. 808 * If you add error code, modify this code also 809 * It is used as an index 810 */ 811 #define IO_ERROR_UNKNOWN_GENERIC 0x43 812 813 /* MSGU CONFIGURATION TABLE*/ 814 815 #define SPC_MSGU_CFG_TABLE_UPDATE 0x01/* Inbound doorbell bit0 */ 816 #define SPC_MSGU_CFG_TABLE_RESET 0x02/* Inbound doorbell bit1 */ 817 #define SPC_MSGU_CFG_TABLE_FREEZE 0x04/* Inbound doorbell bit2 */ 818 #define SPC_MSGU_CFG_TABLE_UNFREEZE 0x08/* Inbound doorbell bit4 */ 819 #define MSGU_IBDB_SET 0x04 820 #define MSGU_HOST_INT_STATUS 0x08 821 #define MSGU_HOST_INT_MASK 0x0C 822 #define MSGU_IOPIB_INT_STATUS 0x18 823 #define MSGU_IOPIB_INT_MASK 0x1C 824 #define MSGU_IBDB_CLEAR 0x20/* RevB - Host not use */ 825 #define MSGU_MSGU_CONTROL 0x24 826 #define MSGU_ODR 0x3C/* RevB */ 827 #define MSGU_ODCR 0x40/* RevB */ 828 #define MSGU_SCRATCH_PAD_0 0x44 829 #define MSGU_SCRATCH_PAD_1 0x48 830 #define MSGU_SCRATCH_PAD_2 0x4C 831 #define MSGU_SCRATCH_PAD_3 0x50 832 #define MSGU_HOST_SCRATCH_PAD_0 0x54 833 #define MSGU_HOST_SCRATCH_PAD_1 0x58 834 #define MSGU_HOST_SCRATCH_PAD_2 0x5C 835 #define MSGU_HOST_SCRATCH_PAD_3 0x60 836 #define MSGU_HOST_SCRATCH_PAD_4 0x64 837 #define MSGU_HOST_SCRATCH_PAD_5 0x68 838 #define MSGU_HOST_SCRATCH_PAD_6 0x6C 839 #define MSGU_HOST_SCRATCH_PAD_7 0x70 840 #define MSGU_ODMR 0x74/* RevB */ 841 842 /* bit definition for ODMR register */ 843 #define ODMR_MASK_ALL 0xFFFFFFFF/* mask all 844 interrupt vector */ 845 #define ODMR_CLEAR_ALL 0/* clear all 846 interrupt vector */ 847 /* bit definition for ODCR register */ 848 #define ODCR_CLEAR_ALL 0xFFFFFFFF /* mask all 849 interrupt vector*/ 850 /* MSIX Interupts */ 851 #define MSIX_TABLE_OFFSET 0x2000 852 #define MSIX_TABLE_ELEMENT_SIZE 0x10 853 #define MSIX_INTERRUPT_CONTROL_OFFSET 0xC 854 #define MSIX_TABLE_BASE (MSIX_TABLE_OFFSET + MSIX_INTERRUPT_CONTROL_OFFSET) 855 #define MSIX_INTERRUPT_DISABLE 0x1 856 #define MSIX_INTERRUPT_ENABLE 0x0 857 858 859 /* state definition for Scratch Pad1 register */ 860 #define SCRATCH_PAD1_POR 0x00 /* power on reset state */ 861 #define SCRATCH_PAD1_SFR 0x01 /* soft reset state */ 862 #define SCRATCH_PAD1_ERR 0x02 /* error state */ 863 #define SCRATCH_PAD1_RDY 0x03 /* ready state */ 864 #define SCRATCH_PAD1_RST 0x04 /* soft reset toggle flag */ 865 #define SCRATCH_PAD1_AAP1RDY_RST 0x08 /* AAP1 ready for soft reset */ 866 #define SCRATCH_PAD1_STATE_MASK 0xFFFFFFF0 /* ScratchPad1 867 Mask, bit1-0 State, bit2 Soft Reset, bit3 FW RDY for Soft Reset */ 868 #define SCRATCH_PAD1_RESERVED 0x000003F8 /* Scratch Pad1 869 Reserved bit 3 to 9 */ 870 871 /* state definition for Scratch Pad2 register */ 872 #define SCRATCH_PAD2_POR 0x00 /* power on state */ 873 #define SCRATCH_PAD2_SFR 0x01 /* soft reset state */ 874 #define SCRATCH_PAD2_ERR 0x02 /* error state */ 875 #define SCRATCH_PAD2_RDY 0x03 /* ready state */ 876 #define SCRATCH_PAD2_FWRDY_RST 0x04 /* FW ready for soft reset flag*/ 877 #define SCRATCH_PAD2_IOPRDY_RST 0x08 /* IOP ready for soft reset */ 878 #define SCRATCH_PAD2_STATE_MASK 0xFFFFFFF4 /* ScratchPad 2 879 Mask, bit1-0 State */ 880 #define SCRATCH_PAD2_RESERVED 0x000003FC /* Scratch Pad1 881 Reserved bit 2 to 9 */ 882 883 #define SCRATCH_PAD_ERROR_MASK 0xFFFFFC00 /* Error mask bits */ 884 #define SCRATCH_PAD_STATE_MASK 0x00000003 /* State Mask bits */ 885 886 /* main configuration offset - byte offset */ 887 #define MAIN_SIGNATURE_OFFSET 0x00/* DWORD 0x00 */ 888 #define MAIN_INTERFACE_REVISION 0x04/* DWORD 0x01 */ 889 #define MAIN_FW_REVISION 0x08/* DWORD 0x02 */ 890 #define MAIN_MAX_OUTSTANDING_IO_OFFSET 0x0C/* DWORD 0x03 */ 891 #define MAIN_MAX_SGL_OFFSET 0x10/* DWORD 0x04 */ 892 #define MAIN_CNTRL_CAP_OFFSET 0x14/* DWORD 0x05 */ 893 #define MAIN_GST_OFFSET 0x18/* DWORD 0x06 */ 894 #define MAIN_IBQ_OFFSET 0x1C/* DWORD 0x07 */ 895 #define MAIN_OBQ_OFFSET 0x20/* DWORD 0x08 */ 896 #define MAIN_IQNPPD_HPPD_OFFSET 0x24/* DWORD 0x09 */ 897 #define MAIN_OB_HW_EVENT_PID03_OFFSET 0x28/* DWORD 0x0A */ 898 #define MAIN_OB_HW_EVENT_PID47_OFFSET 0x2C/* DWORD 0x0B */ 899 #define MAIN_OB_NCQ_EVENT_PID03_OFFSET 0x30/* DWORD 0x0C */ 900 #define MAIN_OB_NCQ_EVENT_PID47_OFFSET 0x34/* DWORD 0x0D */ 901 #define MAIN_TITNX_EVENT_PID03_OFFSET 0x38/* DWORD 0x0E */ 902 #define MAIN_TITNX_EVENT_PID47_OFFSET 0x3C/* DWORD 0x0F */ 903 #define MAIN_OB_SSP_EVENT_PID03_OFFSET 0x40/* DWORD 0x10 */ 904 #define MAIN_OB_SSP_EVENT_PID47_OFFSET 0x44/* DWORD 0x11 */ 905 #define MAIN_OB_SMP_EVENT_PID03_OFFSET 0x48/* DWORD 0x12 */ 906 #define MAIN_OB_SMP_EVENT_PID47_OFFSET 0x4C/* DWORD 0x13 */ 907 #define MAIN_EVENT_LOG_ADDR_HI 0x50/* DWORD 0x14 */ 908 #define MAIN_EVENT_LOG_ADDR_LO 0x54/* DWORD 0x15 */ 909 #define MAIN_EVENT_LOG_BUFF_SIZE 0x58/* DWORD 0x16 */ 910 #define MAIN_EVENT_LOG_OPTION 0x5C/* DWORD 0x17 */ 911 #define MAIN_IOP_EVENT_LOG_ADDR_HI 0x60/* DWORD 0x18 */ 912 #define MAIN_IOP_EVENT_LOG_ADDR_LO 0x64/* DWORD 0x19 */ 913 #define MAIN_IOP_EVENT_LOG_BUFF_SIZE 0x68/* DWORD 0x1A */ 914 #define MAIN_IOP_EVENT_LOG_OPTION 0x6C/* DWORD 0x1B */ 915 #define MAIN_FATAL_ERROR_INTERRUPT 0x70/* DWORD 0x1C */ 916 #define MAIN_FATAL_ERROR_RDUMP0_OFFSET 0x74/* DWORD 0x1D */ 917 #define MAIN_FATAL_ERROR_RDUMP0_LENGTH 0x78/* DWORD 0x1E */ 918 #define MAIN_FATAL_ERROR_RDUMP1_OFFSET 0x7C/* DWORD 0x1F */ 919 #define MAIN_FATAL_ERROR_RDUMP1_LENGTH 0x80/* DWORD 0x20 */ 920 #define MAIN_HDA_FLAGS_OFFSET 0x84/* DWORD 0x21 */ 921 #define MAIN_ANALOG_SETUP_OFFSET 0x88/* DWORD 0x22 */ 922 923 /* Gereral Status Table offset - byte offset */ 924 #define GST_GSTLEN_MPIS_OFFSET 0x00 925 #define GST_IQ_FREEZE_STATE0_OFFSET 0x04 926 #define GST_IQ_FREEZE_STATE1_OFFSET 0x08 927 #define GST_MSGUTCNT_OFFSET 0x0C 928 #define GST_IOPTCNT_OFFSET 0x10 929 #define GST_PHYSTATE_OFFSET 0x18 930 #define GST_PHYSTATE0_OFFSET 0x18 931 #define GST_PHYSTATE1_OFFSET 0x1C 932 #define GST_PHYSTATE2_OFFSET 0x20 933 #define GST_PHYSTATE3_OFFSET 0x24 934 #define GST_PHYSTATE4_OFFSET 0x28 935 #define GST_PHYSTATE5_OFFSET 0x2C 936 #define GST_PHYSTATE6_OFFSET 0x30 937 #define GST_PHYSTATE7_OFFSET 0x34 938 #define GST_RERRINFO_OFFSET 0x44 939 940 /* General Status Table - MPI state */ 941 #define GST_MPI_STATE_UNINIT 0x00 942 #define GST_MPI_STATE_INIT 0x01 943 #define GST_MPI_STATE_TERMINATION 0x02 944 #define GST_MPI_STATE_ERROR 0x03 945 #define GST_MPI_STATE_MASK 0x07 946 947 #define MBIC_NMI_ENABLE_VPE0_IOP 0x000418 948 #define MBIC_NMI_ENABLE_VPE0_AAP1 0x000418 949 /* PCIE registers - BAR2(0x18), BAR1(win) 0x010000 */ 950 #define PCIE_EVENT_INTERRUPT_ENABLE 0x003040 951 #define PCIE_EVENT_INTERRUPT 0x003044 952 #define PCIE_ERROR_INTERRUPT_ENABLE 0x003048 953 #define PCIE_ERROR_INTERRUPT 0x00304C 954 /* signature definition for host scratch pad0 register */ 955 #define SPC_SOFT_RESET_SIGNATURE 0x252acbcd 956 /* Signature for Soft Reset */ 957 958 /* SPC Reset register - BAR4(0x20), BAR2(win) (need dynamic mapping) */ 959 #define SPC_REG_RESET 0x000000/* reset register */ 960 961 /* bit difination for SPC_RESET register */ 962 #define SPC_REG_RESET_OSSP 0x00000001 963 #define SPC_REG_RESET_RAAE 0x00000002 964 #define SPC_REG_RESET_PCS_SPBC 0x00000004 965 #define SPC_REG_RESET_PCS_IOP_SS 0x00000008 966 #define SPC_REG_RESET_PCS_AAP1_SS 0x00000010 967 #define SPC_REG_RESET_PCS_AAP2_SS 0x00000020 968 #define SPC_REG_RESET_PCS_LM 0x00000040 969 #define SPC_REG_RESET_PCS 0x00000080 970 #define SPC_REG_RESET_GSM 0x00000100 971 #define SPC_REG_RESET_DDR2 0x00010000 972 #define SPC_REG_RESET_BDMA_CORE 0x00020000 973 #define SPC_REG_RESET_BDMA_SXCBI 0x00040000 974 #define SPC_REG_RESET_PCIE_AL_SXCBI 0x00080000 975 #define SPC_REG_RESET_PCIE_PWR 0x00100000 976 #define SPC_REG_RESET_PCIE_SFT 0x00200000 977 #define SPC_REG_RESET_PCS_SXCBI 0x00400000 978 #define SPC_REG_RESET_LMS_SXCBI 0x00800000 979 #define SPC_REG_RESET_PMIC_SXCBI 0x01000000 980 #define SPC_REG_RESET_PMIC_CORE 0x02000000 981 #define SPC_REG_RESET_PCIE_PC_SXCBI 0x04000000 982 #define SPC_REG_RESET_DEVICE 0x80000000 983 984 /* registers for BAR Shifting - BAR2(0x18), BAR1(win) */ 985 #define SPC_IBW_AXI_TRANSLATION_LOW 0x003258 986 987 #define MBIC_AAP1_ADDR_BASE 0x060000 988 #define MBIC_IOP_ADDR_BASE 0x070000 989 #define GSM_ADDR_BASE 0x0700000 990 /* Dynamic map through Bar4 - 0x00700000 */ 991 #define GSM_CONFIG_RESET 0x00000000 992 #define RAM_ECC_DB_ERR 0x00000018 993 #define GSM_READ_ADDR_PARITY_INDIC 0x00000058 994 #define GSM_WRITE_ADDR_PARITY_INDIC 0x00000060 995 #define GSM_WRITE_DATA_PARITY_INDIC 0x00000068 996 #define GSM_READ_ADDR_PARITY_CHECK 0x00000038 997 #define GSM_WRITE_ADDR_PARITY_CHECK 0x00000040 998 #define GSM_WRITE_DATA_PARITY_CHECK 0x00000048 999 1000 #define RB6_ACCESS_REG 0x6A0000 1001 #define HDAC_EXEC_CMD 0x0002 1002 #define HDA_C_PA 0xcb 1003 #define HDA_SEQ_ID_BITS 0x00ff0000 1004 #define HDA_GSM_OFFSET_BITS 0x00FFFFFF 1005 #define MBIC_AAP1_ADDR_BASE 0x060000 1006 #define MBIC_IOP_ADDR_BASE 0x070000 1007 #define GSM_ADDR_BASE 0x0700000 1008 #define SPC_TOP_LEVEL_ADDR_BASE 0x000000 1009 #define GSM_CONFIG_RESET_VALUE 0x00003b00 1010 #define GPIO_ADDR_BASE 0x00090000 1011 #define GPIO_GPIO_0_0UTPUT_CTL_OFFSET 0x0000010c 1012 1013 /* RB6 offset */ 1014 #define SPC_RB6_OFFSET 0x80C0 1015 /* Magic number of soft reset for RB6 */ 1016 #define RB6_MAGIC_NUMBER_RST 0x1234 1017 1018 /* Device Register status */ 1019 #define DEVREG_SUCCESS 0x00 1020 #define DEVREG_FAILURE_OUT_OF_RESOURCE 0x01 1021 #define DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED 0x02 1022 #define DEVREG_FAILURE_INVALID_PHY_ID 0x03 1023 #define DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04 1024 #define DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE 0x05 1025 #define DEVREG_FAILURE_PORT_NOT_VALID_STATE 0x06 1026 #define DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID 0x07 1027 1028 #endif 1029 1030