1 /* 2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 USI Co., Ltd. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 #include <linux/slab.h> 41 #include "pm8001_sas.h" 42 #include "pm8001_hwi.h" 43 #include "pm8001_chips.h" 44 #include "pm8001_ctl.h" 45 46 /** 47 * read_main_config_table - read the configure table and save it. 48 * @pm8001_ha: our hba card information 49 */ 50 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha) 51 { 52 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 53 pm8001_ha->main_cfg_tbl.pm8001_tbl.signature = 54 pm8001_mr32(address, 0x00); 55 pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev = 56 pm8001_mr32(address, 0x04); 57 pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev = 58 pm8001_mr32(address, 0x08); 59 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io = 60 pm8001_mr32(address, 0x0C); 61 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl = 62 pm8001_mr32(address, 0x10); 63 pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag = 64 pm8001_mr32(address, 0x14); 65 pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset = 66 pm8001_mr32(address, 0x18); 67 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset = 68 pm8001_mr32(address, MAIN_IBQ_OFFSET); 69 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset = 70 pm8001_mr32(address, MAIN_OBQ_OFFSET); 71 pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag = 72 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET); 73 74 /* read analog Setting offset from the configuration table */ 75 pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset = 76 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET); 77 78 /* read Error Dump Offset and Length */ 79 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 = 80 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET); 81 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 = 82 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH); 83 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 = 84 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET); 85 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 = 86 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH); 87 } 88 89 /** 90 * read_general_status_table - read the general status table and save it. 91 * @pm8001_ha: our hba card information 92 */ 93 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha) 94 { 95 void __iomem *address = pm8001_ha->general_stat_tbl_addr; 96 pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate = 97 pm8001_mr32(address, 0x00); 98 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0 = 99 pm8001_mr32(address, 0x04); 100 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1 = 101 pm8001_mr32(address, 0x08); 102 pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt = 103 pm8001_mr32(address, 0x0C); 104 pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt = 105 pm8001_mr32(address, 0x10); 106 pm8001_ha->gs_tbl.pm8001_tbl.rsvd = 107 pm8001_mr32(address, 0x14); 108 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0] = 109 pm8001_mr32(address, 0x18); 110 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1] = 111 pm8001_mr32(address, 0x1C); 112 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2] = 113 pm8001_mr32(address, 0x20); 114 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3] = 115 pm8001_mr32(address, 0x24); 116 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4] = 117 pm8001_mr32(address, 0x28); 118 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5] = 119 pm8001_mr32(address, 0x2C); 120 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6] = 121 pm8001_mr32(address, 0x30); 122 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7] = 123 pm8001_mr32(address, 0x34); 124 pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val = 125 pm8001_mr32(address, 0x38); 126 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0] = 127 pm8001_mr32(address, 0x3C); 128 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1] = 129 pm8001_mr32(address, 0x40); 130 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0] = 131 pm8001_mr32(address, 0x44); 132 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1] = 133 pm8001_mr32(address, 0x48); 134 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2] = 135 pm8001_mr32(address, 0x4C); 136 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3] = 137 pm8001_mr32(address, 0x50); 138 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4] = 139 pm8001_mr32(address, 0x54); 140 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5] = 141 pm8001_mr32(address, 0x58); 142 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6] = 143 pm8001_mr32(address, 0x5C); 144 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7] = 145 pm8001_mr32(address, 0x60); 146 } 147 148 /** 149 * read_inbnd_queue_table - read the inbound queue table and save it. 150 * @pm8001_ha: our hba card information 151 */ 152 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 153 { 154 int i; 155 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 156 for (i = 0; i < PM8001_MAX_INB_NUM; i++) { 157 u32 offset = i * 0x20; 158 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 159 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14))); 160 pm8001_ha->inbnd_q_tbl[i].pi_offset = 161 pm8001_mr32(address, (offset + 0x18)); 162 } 163 } 164 165 /** 166 * read_outbnd_queue_table - read the outbound queue table and save it. 167 * @pm8001_ha: our hba card information 168 */ 169 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 170 { 171 int i; 172 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 173 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) { 174 u32 offset = i * 0x24; 175 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 176 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14))); 177 pm8001_ha->outbnd_q_tbl[i].ci_offset = 178 pm8001_mr32(address, (offset + 0x18)); 179 } 180 } 181 182 /** 183 * init_default_table_values - init the default table. 184 * @pm8001_ha: our hba card information 185 */ 186 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha) 187 { 188 int i; 189 u32 offsetib, offsetob; 190 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr; 191 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr; 192 193 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd = 0; 194 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3 = 0; 195 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7 = 0; 196 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3 = 0; 197 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7 = 0; 198 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 = 199 0; 200 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 = 201 0; 202 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0; 203 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0; 204 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0; 205 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0; 206 207 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr = 208 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi; 209 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr = 210 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo; 211 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size = 212 PM8001_EVENT_LOG_SIZE; 213 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option = 0x01; 214 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr = 215 pm8001_ha->memoryMap.region[IOP].phys_addr_hi; 216 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr = 217 pm8001_ha->memoryMap.region[IOP].phys_addr_lo; 218 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size = 219 PM8001_EVENT_LOG_SIZE; 220 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option = 0x01; 221 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt = 0x01; 222 for (i = 0; i < PM8001_MAX_INB_NUM; i++) { 223 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt = 224 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30); 225 pm8001_ha->inbnd_q_tbl[i].upper_base_addr = 226 pm8001_ha->memoryMap.region[IB + i].phys_addr_hi; 227 pm8001_ha->inbnd_q_tbl[i].lower_base_addr = 228 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo; 229 pm8001_ha->inbnd_q_tbl[i].base_virt = 230 (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr; 231 pm8001_ha->inbnd_q_tbl[i].total_length = 232 pm8001_ha->memoryMap.region[IB + i].total_len; 233 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr = 234 pm8001_ha->memoryMap.region[CI + i].phys_addr_hi; 235 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr = 236 pm8001_ha->memoryMap.region[CI + i].phys_addr_lo; 237 pm8001_ha->inbnd_q_tbl[i].ci_virt = 238 pm8001_ha->memoryMap.region[CI + i].virt_ptr; 239 offsetib = i * 0x20; 240 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 241 get_pci_bar_index(pm8001_mr32(addressib, 242 (offsetib + 0x14))); 243 pm8001_ha->inbnd_q_tbl[i].pi_offset = 244 pm8001_mr32(addressib, (offsetib + 0x18)); 245 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0; 246 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0; 247 } 248 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) { 249 pm8001_ha->outbnd_q_tbl[i].element_size_cnt = 250 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30); 251 pm8001_ha->outbnd_q_tbl[i].upper_base_addr = 252 pm8001_ha->memoryMap.region[OB + i].phys_addr_hi; 253 pm8001_ha->outbnd_q_tbl[i].lower_base_addr = 254 pm8001_ha->memoryMap.region[OB + i].phys_addr_lo; 255 pm8001_ha->outbnd_q_tbl[i].base_virt = 256 (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr; 257 pm8001_ha->outbnd_q_tbl[i].total_length = 258 pm8001_ha->memoryMap.region[OB + i].total_len; 259 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr = 260 pm8001_ha->memoryMap.region[PI + i].phys_addr_hi; 261 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr = 262 pm8001_ha->memoryMap.region[PI + i].phys_addr_lo; 263 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = 264 0 | (10 << 16) | (i << 24); 265 pm8001_ha->outbnd_q_tbl[i].pi_virt = 266 pm8001_ha->memoryMap.region[PI + i].virt_ptr; 267 offsetob = i * 0x24; 268 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 269 get_pci_bar_index(pm8001_mr32(addressob, 270 offsetob + 0x14)); 271 pm8001_ha->outbnd_q_tbl[i].ci_offset = 272 pm8001_mr32(addressob, (offsetob + 0x18)); 273 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0; 274 pm8001_ha->outbnd_q_tbl[i].producer_index = 0; 275 } 276 } 277 278 /** 279 * update_main_config_table - update the main default table to the HBA. 280 * @pm8001_ha: our hba card information 281 */ 282 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha) 283 { 284 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 285 pm8001_mw32(address, 0x24, 286 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd); 287 pm8001_mw32(address, 0x28, 288 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3); 289 pm8001_mw32(address, 0x2C, 290 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7); 291 pm8001_mw32(address, 0x30, 292 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3); 293 pm8001_mw32(address, 0x34, 294 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7); 295 pm8001_mw32(address, 0x38, 296 pm8001_ha->main_cfg_tbl.pm8001_tbl. 297 outbound_tgt_ITNexus_event_pid0_3); 298 pm8001_mw32(address, 0x3C, 299 pm8001_ha->main_cfg_tbl.pm8001_tbl. 300 outbound_tgt_ITNexus_event_pid4_7); 301 pm8001_mw32(address, 0x40, 302 pm8001_ha->main_cfg_tbl.pm8001_tbl. 303 outbound_tgt_ssp_event_pid0_3); 304 pm8001_mw32(address, 0x44, 305 pm8001_ha->main_cfg_tbl.pm8001_tbl. 306 outbound_tgt_ssp_event_pid4_7); 307 pm8001_mw32(address, 0x48, 308 pm8001_ha->main_cfg_tbl.pm8001_tbl. 309 outbound_tgt_smp_event_pid0_3); 310 pm8001_mw32(address, 0x4C, 311 pm8001_ha->main_cfg_tbl.pm8001_tbl. 312 outbound_tgt_smp_event_pid4_7); 313 pm8001_mw32(address, 0x50, 314 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr); 315 pm8001_mw32(address, 0x54, 316 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr); 317 pm8001_mw32(address, 0x58, 318 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size); 319 pm8001_mw32(address, 0x5C, 320 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option); 321 pm8001_mw32(address, 0x60, 322 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr); 323 pm8001_mw32(address, 0x64, 324 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr); 325 pm8001_mw32(address, 0x68, 326 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size); 327 pm8001_mw32(address, 0x6C, 328 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option); 329 pm8001_mw32(address, 0x70, 330 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt); 331 } 332 333 /** 334 * update_inbnd_queue_table - update the inbound queue table to the HBA. 335 * @pm8001_ha: our hba card information 336 */ 337 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 338 int number) 339 { 340 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 341 u16 offset = number * 0x20; 342 pm8001_mw32(address, offset + 0x00, 343 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); 344 pm8001_mw32(address, offset + 0x04, 345 pm8001_ha->inbnd_q_tbl[number].upper_base_addr); 346 pm8001_mw32(address, offset + 0x08, 347 pm8001_ha->inbnd_q_tbl[number].lower_base_addr); 348 pm8001_mw32(address, offset + 0x0C, 349 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr); 350 pm8001_mw32(address, offset + 0x10, 351 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); 352 } 353 354 /** 355 * update_outbnd_queue_table - update the outbound queue table to the HBA. 356 * @pm8001_ha: our hba card information 357 */ 358 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 359 int number) 360 { 361 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 362 u16 offset = number * 0x24; 363 pm8001_mw32(address, offset + 0x00, 364 pm8001_ha->outbnd_q_tbl[number].element_size_cnt); 365 pm8001_mw32(address, offset + 0x04, 366 pm8001_ha->outbnd_q_tbl[number].upper_base_addr); 367 pm8001_mw32(address, offset + 0x08, 368 pm8001_ha->outbnd_q_tbl[number].lower_base_addr); 369 pm8001_mw32(address, offset + 0x0C, 370 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr); 371 pm8001_mw32(address, offset + 0x10, 372 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); 373 pm8001_mw32(address, offset + 0x1C, 374 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay); 375 } 376 377 /** 378 * pm8001_bar4_shift - function is called to shift BAR base address 379 * @pm8001_ha : our hba card infomation 380 * @shiftValue : shifting value in memory bar. 381 */ 382 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue) 383 { 384 u32 regVal; 385 unsigned long start; 386 387 /* program the inbound AXI translation Lower Address */ 388 pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue); 389 390 /* confirm the setting is written */ 391 start = jiffies + HZ; /* 1 sec */ 392 do { 393 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW); 394 } while ((regVal != shiftValue) && time_before(jiffies, start)); 395 396 if (regVal != shiftValue) { 397 PM8001_INIT_DBG(pm8001_ha, 398 pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW" 399 " = 0x%x\n", regVal)); 400 return -1; 401 } 402 return 0; 403 } 404 405 /** 406 * mpi_set_phys_g3_with_ssc 407 * @pm8001_ha: our hba card information 408 * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc. 409 */ 410 static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha, 411 u32 SSCbit) 412 { 413 u32 value, offset, i; 414 unsigned long flags; 415 416 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000 417 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000 418 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074 419 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074 420 #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12 421 #define PHY_G3_WITH_SSC_BIT_SHIFT 13 422 #define SNW3_PHY_CAPABILITIES_PARITY 31 423 424 /* 425 * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3) 426 * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7) 427 */ 428 spin_lock_irqsave(&pm8001_ha->lock, flags); 429 if (-1 == pm8001_bar4_shift(pm8001_ha, 430 SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) { 431 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 432 return; 433 } 434 435 for (i = 0; i < 4; i++) { 436 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i; 437 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501); 438 } 439 /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */ 440 if (-1 == pm8001_bar4_shift(pm8001_ha, 441 SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) { 442 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 443 return; 444 } 445 for (i = 4; i < 8; i++) { 446 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4); 447 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501); 448 } 449 /************************************************************* 450 Change the SSC upspreading value to 0x0 so that upspreading is disabled. 451 Device MABC SMOD0 Controls 452 Address: (via MEMBASE-III): 453 Using shifted destination address 0x0_0000: with Offset 0xD8 454 455 31:28 R/W Reserved Do not change 456 27:24 R/W SAS_SMOD_SPRDUP 0000 457 23:20 R/W SAS_SMOD_SPRDDN 0000 458 19:0 R/W Reserved Do not change 459 Upon power-up this register will read as 0x8990c016, 460 and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000 461 so that the written value will be 0x8090c016. 462 This will ensure only down-spreading SSC is enabled on the SPC. 463 *************************************************************/ 464 value = pm8001_cr32(pm8001_ha, 2, 0xd8); 465 pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016); 466 467 /*set the shifted destination address to 0x0 to avoid error operation */ 468 pm8001_bar4_shift(pm8001_ha, 0x0); 469 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 470 return; 471 } 472 473 /** 474 * mpi_set_open_retry_interval_reg 475 * @pm8001_ha: our hba card information 476 * @interval - interval time for each OPEN_REJECT (RETRY). The units are in 1us. 477 */ 478 static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha, 479 u32 interval) 480 { 481 u32 offset; 482 u32 value; 483 u32 i; 484 unsigned long flags; 485 486 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000 487 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000 488 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4 489 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4 490 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF 491 492 value = interval & OPEN_RETRY_INTERVAL_REG_MASK; 493 spin_lock_irqsave(&pm8001_ha->lock, flags); 494 /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/ 495 if (-1 == pm8001_bar4_shift(pm8001_ha, 496 OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) { 497 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 498 return; 499 } 500 for (i = 0; i < 4; i++) { 501 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i; 502 pm8001_cw32(pm8001_ha, 2, offset, value); 503 } 504 505 if (-1 == pm8001_bar4_shift(pm8001_ha, 506 OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) { 507 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 508 return; 509 } 510 for (i = 4; i < 8; i++) { 511 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4); 512 pm8001_cw32(pm8001_ha, 2, offset, value); 513 } 514 /*set the shifted destination address to 0x0 to avoid error operation */ 515 pm8001_bar4_shift(pm8001_ha, 0x0); 516 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 517 return; 518 } 519 520 /** 521 * mpi_init_check - check firmware initialization status. 522 * @pm8001_ha: our hba card information 523 */ 524 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha) 525 { 526 u32 max_wait_count; 527 u32 value; 528 u32 gst_len_mpistate; 529 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the 530 table is updated */ 531 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE); 532 /* wait until Inbound DoorBell Clear Register toggled */ 533 max_wait_count = 1 * 1000 * 1000;/* 1 sec */ 534 do { 535 udelay(1); 536 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 537 value &= SPC_MSGU_CFG_TABLE_UPDATE; 538 } while ((value != 0) && (--max_wait_count)); 539 540 if (!max_wait_count) 541 return -1; 542 /* check the MPI-State for initialization */ 543 gst_len_mpistate = 544 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 545 GST_GSTLEN_MPIS_OFFSET); 546 if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK)) 547 return -1; 548 /* check MPI Initialization error */ 549 gst_len_mpistate = gst_len_mpistate >> 16; 550 if (0x0000 != gst_len_mpistate) 551 return -1; 552 return 0; 553 } 554 555 /** 556 * check_fw_ready - The LLDD check if the FW is ready, if not, return error. 557 * @pm8001_ha: our hba card information 558 */ 559 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha) 560 { 561 u32 value, value1; 562 u32 max_wait_count; 563 /* check error state */ 564 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 565 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 566 /* check AAP error */ 567 if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) { 568 /* error state */ 569 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 570 return -1; 571 } 572 573 /* check IOP error */ 574 if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) { 575 /* error state */ 576 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 577 return -1; 578 } 579 580 /* bit 4-31 of scratch pad1 should be zeros if it is not 581 in error state*/ 582 if (value & SCRATCH_PAD1_STATE_MASK) { 583 /* error case */ 584 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 585 return -1; 586 } 587 588 /* bit 2, 4-31 of scratch pad2 should be zeros if it is not 589 in error state */ 590 if (value1 & SCRATCH_PAD2_STATE_MASK) { 591 /* error case */ 592 return -1; 593 } 594 595 max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */ 596 597 /* wait until scratch pad 1 and 2 registers in ready state */ 598 do { 599 udelay(1); 600 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) 601 & SCRATCH_PAD1_RDY; 602 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) 603 & SCRATCH_PAD2_RDY; 604 if ((--max_wait_count) == 0) 605 return -1; 606 } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY)); 607 return 0; 608 } 609 610 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha) 611 { 612 void __iomem *base_addr; 613 u32 value; 614 u32 offset; 615 u32 pcibar; 616 u32 pcilogic; 617 618 value = pm8001_cr32(pm8001_ha, 0, 0x44); 619 offset = value & 0x03FFFFFF; 620 PM8001_INIT_DBG(pm8001_ha, 621 pm8001_printk("Scratchpad 0 Offset: %x\n", offset)); 622 pcilogic = (value & 0xFC000000) >> 26; 623 pcibar = get_pci_bar_index(pcilogic); 624 PM8001_INIT_DBG(pm8001_ha, 625 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar)); 626 pm8001_ha->main_cfg_tbl_addr = base_addr = 627 pm8001_ha->io_mem[pcibar].memvirtaddr + offset; 628 pm8001_ha->general_stat_tbl_addr = 629 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18); 630 pm8001_ha->inbnd_q_tbl_addr = 631 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C); 632 pm8001_ha->outbnd_q_tbl_addr = 633 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20); 634 } 635 636 /** 637 * pm8001_chip_init - the main init function that initialize whole PM8001 chip. 638 * @pm8001_ha: our hba card information 639 */ 640 static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha) 641 { 642 u8 i = 0; 643 u16 deviceid; 644 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid); 645 /* 8081 controllers need BAR shift to access MPI space 646 * as this is shared with BIOS data */ 647 if (deviceid == 0x8081 || deviceid == 0x0042) { 648 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) { 649 PM8001_FAIL_DBG(pm8001_ha, 650 pm8001_printk("Shift Bar4 to 0x%x failed\n", 651 GSM_SM_BASE)); 652 return -1; 653 } 654 } 655 /* check the firmware status */ 656 if (-1 == check_fw_ready(pm8001_ha)) { 657 PM8001_FAIL_DBG(pm8001_ha, 658 pm8001_printk("Firmware is not ready!\n")); 659 return -EBUSY; 660 } 661 662 /* Initialize pci space address eg: mpi offset */ 663 init_pci_device_addresses(pm8001_ha); 664 init_default_table_values(pm8001_ha); 665 read_main_config_table(pm8001_ha); 666 read_general_status_table(pm8001_ha); 667 read_inbnd_queue_table(pm8001_ha); 668 read_outbnd_queue_table(pm8001_ha); 669 /* update main config table ,inbound table and outbound table */ 670 update_main_config_table(pm8001_ha); 671 for (i = 0; i < PM8001_MAX_INB_NUM; i++) 672 update_inbnd_queue_table(pm8001_ha, i); 673 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) 674 update_outbnd_queue_table(pm8001_ha, i); 675 /* 8081 controller donot require these operations */ 676 if (deviceid != 0x8081 && deviceid != 0x0042) { 677 mpi_set_phys_g3_with_ssc(pm8001_ha, 0); 678 /* 7->130ms, 34->500ms, 119->1.5s */ 679 mpi_set_open_retry_interval_reg(pm8001_ha, 119); 680 } 681 /* notify firmware update finished and check initialization status */ 682 if (0 == mpi_init_check(pm8001_ha)) { 683 PM8001_INIT_DBG(pm8001_ha, 684 pm8001_printk("MPI initialize successful!\n")); 685 } else 686 return -EBUSY; 687 /*This register is a 16-bit timer with a resolution of 1us. This is the 688 timer used for interrupt delay/coalescing in the PCIe Application Layer. 689 Zero is not a valid value. A value of 1 in the register will cause the 690 interrupts to be normal. A value greater than 1 will cause coalescing 691 delays.*/ 692 pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1); 693 pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0); 694 return 0; 695 } 696 697 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha) 698 { 699 u32 max_wait_count; 700 u32 value; 701 u32 gst_len_mpistate; 702 u16 deviceid; 703 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid); 704 if (deviceid == 0x8081 || deviceid == 0x0042) { 705 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) { 706 PM8001_FAIL_DBG(pm8001_ha, 707 pm8001_printk("Shift Bar4 to 0x%x failed\n", 708 GSM_SM_BASE)); 709 return -1; 710 } 711 } 712 init_pci_device_addresses(pm8001_ha); 713 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the 714 table is stop */ 715 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET); 716 717 /* wait until Inbound DoorBell Clear Register toggled */ 718 max_wait_count = 1 * 1000 * 1000;/* 1 sec */ 719 do { 720 udelay(1); 721 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 722 value &= SPC_MSGU_CFG_TABLE_RESET; 723 } while ((value != 0) && (--max_wait_count)); 724 725 if (!max_wait_count) { 726 PM8001_FAIL_DBG(pm8001_ha, 727 pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value)); 728 return -1; 729 } 730 731 /* check the MPI-State for termination in progress */ 732 /* wait until Inbound DoorBell Clear Register toggled */ 733 max_wait_count = 1 * 1000 * 1000; /* 1 sec */ 734 do { 735 udelay(1); 736 gst_len_mpistate = 737 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 738 GST_GSTLEN_MPIS_OFFSET); 739 if (GST_MPI_STATE_UNINIT == 740 (gst_len_mpistate & GST_MPI_STATE_MASK)) 741 break; 742 } while (--max_wait_count); 743 if (!max_wait_count) { 744 PM8001_FAIL_DBG(pm8001_ha, 745 pm8001_printk(" TIME OUT MPI State = 0x%x\n", 746 gst_len_mpistate & GST_MPI_STATE_MASK)); 747 return -1; 748 } 749 return 0; 750 } 751 752 /** 753 * soft_reset_ready_check - Function to check FW is ready for soft reset. 754 * @pm8001_ha: our hba card information 755 */ 756 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha) 757 { 758 u32 regVal, regVal1, regVal2; 759 if (mpi_uninit_check(pm8001_ha) != 0) { 760 PM8001_FAIL_DBG(pm8001_ha, 761 pm8001_printk("MPI state is not ready\n")); 762 return -1; 763 } 764 /* read the scratch pad 2 register bit 2 */ 765 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) 766 & SCRATCH_PAD2_FWRDY_RST; 767 if (regVal == SCRATCH_PAD2_FWRDY_RST) { 768 PM8001_INIT_DBG(pm8001_ha, 769 pm8001_printk("Firmware is ready for reset .\n")); 770 } else { 771 unsigned long flags; 772 /* Trigger NMI twice via RB6 */ 773 spin_lock_irqsave(&pm8001_ha->lock, flags); 774 if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) { 775 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 776 PM8001_FAIL_DBG(pm8001_ha, 777 pm8001_printk("Shift Bar4 to 0x%x failed\n", 778 RB6_ACCESS_REG)); 779 return -1; 780 } 781 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, 782 RB6_MAGIC_NUMBER_RST); 783 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST); 784 /* wait for 100 ms */ 785 mdelay(100); 786 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) & 787 SCRATCH_PAD2_FWRDY_RST; 788 if (regVal != SCRATCH_PAD2_FWRDY_RST) { 789 regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 790 regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 791 PM8001_FAIL_DBG(pm8001_ha, 792 pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1" 793 "=0x%x, MSGU_SCRATCH_PAD2=0x%x\n", 794 regVal1, regVal2)); 795 PM8001_FAIL_DBG(pm8001_ha, 796 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n", 797 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0))); 798 PM8001_FAIL_DBG(pm8001_ha, 799 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n", 800 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3))); 801 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 802 return -1; 803 } 804 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 805 } 806 return 0; 807 } 808 809 /** 810 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all 811 * the FW register status to the originated status. 812 * @pm8001_ha: our hba card information 813 */ 814 static int 815 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha) 816 { 817 u32 regVal, toggleVal; 818 u32 max_wait_count; 819 u32 regVal1, regVal2, regVal3; 820 u32 signature = 0x252acbcd; /* for host scratch pad0 */ 821 unsigned long flags; 822 823 /* step1: Check FW is ready for soft reset */ 824 if (soft_reset_ready_check(pm8001_ha) != 0) { 825 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("FW is not ready\n")); 826 return -1; 827 } 828 829 /* step 2: clear NMI status register on AAP1 and IOP, write the same 830 value to clear */ 831 /* map 0x60000 to BAR4(0x20), BAR2(win) */ 832 spin_lock_irqsave(&pm8001_ha->lock, flags); 833 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) { 834 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 835 PM8001_FAIL_DBG(pm8001_ha, 836 pm8001_printk("Shift Bar4 to 0x%x failed\n", 837 MBIC_AAP1_ADDR_BASE)); 838 return -1; 839 } 840 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP); 841 PM8001_INIT_DBG(pm8001_ha, 842 pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal)); 843 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0); 844 /* map 0x70000 to BAR4(0x20), BAR2(win) */ 845 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) { 846 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 847 PM8001_FAIL_DBG(pm8001_ha, 848 pm8001_printk("Shift Bar4 to 0x%x failed\n", 849 MBIC_IOP_ADDR_BASE)); 850 return -1; 851 } 852 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1); 853 PM8001_INIT_DBG(pm8001_ha, 854 pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal)); 855 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0); 856 857 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE); 858 PM8001_INIT_DBG(pm8001_ha, 859 pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal)); 860 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0); 861 862 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT); 863 PM8001_INIT_DBG(pm8001_ha, 864 pm8001_printk("PCIE - Event Interrupt = 0x%x\n", regVal)); 865 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal); 866 867 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE); 868 PM8001_INIT_DBG(pm8001_ha, 869 pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal)); 870 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0); 871 872 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT); 873 PM8001_INIT_DBG(pm8001_ha, 874 pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal)); 875 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal); 876 877 /* read the scratch pad 1 register bit 2 */ 878 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) 879 & SCRATCH_PAD1_RST; 880 toggleVal = regVal ^ SCRATCH_PAD1_RST; 881 882 /* set signature in host scratch pad0 register to tell SPC that the 883 host performs the soft reset */ 884 pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature); 885 886 /* read required registers for confirmming */ 887 /* map 0x0700000 to BAR4(0x20), BAR2(win) */ 888 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) { 889 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 890 PM8001_FAIL_DBG(pm8001_ha, 891 pm8001_printk("Shift Bar4 to 0x%x failed\n", 892 GSM_ADDR_BASE)); 893 return -1; 894 } 895 PM8001_INIT_DBG(pm8001_ha, 896 pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and" 897 " Reset = 0x%x\n", 898 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); 899 900 /* step 3: host read GSM Configuration and Reset register */ 901 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); 902 /* Put those bits to low */ 903 /* GSM XCBI offset = 0x70 0000 904 0x00 Bit 13 COM_SLV_SW_RSTB 1 905 0x00 Bit 12 QSSP_SW_RSTB 1 906 0x00 Bit 11 RAAE_SW_RSTB 1 907 0x00 Bit 9 RB_1_SW_RSTB 1 908 0x00 Bit 8 SM_SW_RSTB 1 909 */ 910 regVal &= ~(0x00003b00); 911 /* host write GSM Configuration and Reset register */ 912 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); 913 PM8001_INIT_DBG(pm8001_ha, 914 pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM " 915 "Configuration and Reset is set to = 0x%x\n", 916 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); 917 918 /* step 4: */ 919 /* disable GSM - Read Address Parity Check */ 920 regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK); 921 PM8001_INIT_DBG(pm8001_ha, 922 pm8001_printk("GSM 0x700038 - Read Address Parity Check " 923 "Enable = 0x%x\n", regVal1)); 924 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0); 925 PM8001_INIT_DBG(pm8001_ha, 926 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable" 927 "is set to = 0x%x\n", 928 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK))); 929 930 /* disable GSM - Write Address Parity Check */ 931 regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK); 932 PM8001_INIT_DBG(pm8001_ha, 933 pm8001_printk("GSM 0x700040 - Write Address Parity Check" 934 " Enable = 0x%x\n", regVal2)); 935 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0); 936 PM8001_INIT_DBG(pm8001_ha, 937 pm8001_printk("GSM 0x700040 - Write Address Parity Check " 938 "Enable is set to = 0x%x\n", 939 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK))); 940 941 /* disable GSM - Write Data Parity Check */ 942 regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK); 943 PM8001_INIT_DBG(pm8001_ha, 944 pm8001_printk("GSM 0x300048 - Write Data Parity Check" 945 " Enable = 0x%x\n", regVal3)); 946 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0); 947 PM8001_INIT_DBG(pm8001_ha, 948 pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable" 949 "is set to = 0x%x\n", 950 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK))); 951 952 /* step 5: delay 10 usec */ 953 udelay(10); 954 /* step 5-b: set GPIO-0 output control to tristate anyway */ 955 if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) { 956 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 957 PM8001_INIT_DBG(pm8001_ha, 958 pm8001_printk("Shift Bar4 to 0x%x failed\n", 959 GPIO_ADDR_BASE)); 960 return -1; 961 } 962 regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET); 963 PM8001_INIT_DBG(pm8001_ha, 964 pm8001_printk("GPIO Output Control Register:" 965 " = 0x%x\n", regVal)); 966 /* set GPIO-0 output control to tri-state */ 967 regVal &= 0xFFFFFFFC; 968 pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal); 969 970 /* Step 6: Reset the IOP and AAP1 */ 971 /* map 0x00000 to BAR4(0x20), BAR2(win) */ 972 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) { 973 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 974 PM8001_FAIL_DBG(pm8001_ha, 975 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n", 976 SPC_TOP_LEVEL_ADDR_BASE)); 977 return -1; 978 } 979 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 980 PM8001_INIT_DBG(pm8001_ha, 981 pm8001_printk("Top Register before resetting IOP/AAP1" 982 ":= 0x%x\n", regVal)); 983 regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS); 984 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 985 986 /* step 7: Reset the BDMA/OSSP */ 987 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 988 PM8001_INIT_DBG(pm8001_ha, 989 pm8001_printk("Top Register before resetting BDMA/OSSP" 990 ": = 0x%x\n", regVal)); 991 regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP); 992 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 993 994 /* step 8: delay 10 usec */ 995 udelay(10); 996 997 /* step 9: bring the BDMA and OSSP out of reset */ 998 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 999 PM8001_INIT_DBG(pm8001_ha, 1000 pm8001_printk("Top Register before bringing up BDMA/OSSP" 1001 ":= 0x%x\n", regVal)); 1002 regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP); 1003 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 1004 1005 /* step 10: delay 10 usec */ 1006 udelay(10); 1007 1008 /* step 11: reads and sets the GSM Configuration and Reset Register */ 1009 /* map 0x0700000 to BAR4(0x20), BAR2(win) */ 1010 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) { 1011 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1012 PM8001_FAIL_DBG(pm8001_ha, 1013 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n", 1014 GSM_ADDR_BASE)); 1015 return -1; 1016 } 1017 PM8001_INIT_DBG(pm8001_ha, 1018 pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and " 1019 "Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); 1020 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); 1021 /* Put those bits to high */ 1022 /* GSM XCBI offset = 0x70 0000 1023 0x00 Bit 13 COM_SLV_SW_RSTB 1 1024 0x00 Bit 12 QSSP_SW_RSTB 1 1025 0x00 Bit 11 RAAE_SW_RSTB 1 1026 0x00 Bit 9 RB_1_SW_RSTB 1 1027 0x00 Bit 8 SM_SW_RSTB 1 1028 */ 1029 regVal |= (GSM_CONFIG_RESET_VALUE); 1030 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); 1031 PM8001_INIT_DBG(pm8001_ha, 1032 pm8001_printk("GSM (0x00004088 ==> 0x00007b88) - GSM" 1033 " Configuration and Reset is set to = 0x%x\n", 1034 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); 1035 1036 /* step 12: Restore GSM - Read Address Parity Check */ 1037 regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK); 1038 /* just for debugging */ 1039 PM8001_INIT_DBG(pm8001_ha, 1040 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable" 1041 " = 0x%x\n", regVal)); 1042 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1); 1043 PM8001_INIT_DBG(pm8001_ha, 1044 pm8001_printk("GSM 0x700038 - Read Address Parity" 1045 " Check Enable is set to = 0x%x\n", 1046 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK))); 1047 /* Restore GSM - Write Address Parity Check */ 1048 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK); 1049 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2); 1050 PM8001_INIT_DBG(pm8001_ha, 1051 pm8001_printk("GSM 0x700040 - Write Address Parity Check" 1052 " Enable is set to = 0x%x\n", 1053 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK))); 1054 /* Restore GSM - Write Data Parity Check */ 1055 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK); 1056 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3); 1057 PM8001_INIT_DBG(pm8001_ha, 1058 pm8001_printk("GSM 0x700048 - Write Data Parity Check Enable" 1059 "is set to = 0x%x\n", 1060 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK))); 1061 1062 /* step 13: bring the IOP and AAP1 out of reset */ 1063 /* map 0x00000 to BAR4(0x20), BAR2(win) */ 1064 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) { 1065 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1066 PM8001_FAIL_DBG(pm8001_ha, 1067 pm8001_printk("Shift Bar4 to 0x%x failed\n", 1068 SPC_TOP_LEVEL_ADDR_BASE)); 1069 return -1; 1070 } 1071 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 1072 regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS); 1073 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 1074 1075 /* step 14: delay 10 usec - Normal Mode */ 1076 udelay(10); 1077 /* check Soft Reset Normal mode or Soft Reset HDA mode */ 1078 if (signature == SPC_SOFT_RESET_SIGNATURE) { 1079 /* step 15 (Normal Mode): wait until scratch pad1 register 1080 bit 2 toggled */ 1081 max_wait_count = 2 * 1000 * 1000;/* 2 sec */ 1082 do { 1083 udelay(1); 1084 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) & 1085 SCRATCH_PAD1_RST; 1086 } while ((regVal != toggleVal) && (--max_wait_count)); 1087 1088 if (!max_wait_count) { 1089 regVal = pm8001_cr32(pm8001_ha, 0, 1090 MSGU_SCRATCH_PAD_1); 1091 PM8001_FAIL_DBG(pm8001_ha, 1092 pm8001_printk("TIMEOUT : ToggleVal 0x%x," 1093 "MSGU_SCRATCH_PAD1 = 0x%x\n", 1094 toggleVal, regVal)); 1095 PM8001_FAIL_DBG(pm8001_ha, 1096 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n", 1097 pm8001_cr32(pm8001_ha, 0, 1098 MSGU_SCRATCH_PAD_0))); 1099 PM8001_FAIL_DBG(pm8001_ha, 1100 pm8001_printk("SCRATCH_PAD2 value = 0x%x\n", 1101 pm8001_cr32(pm8001_ha, 0, 1102 MSGU_SCRATCH_PAD_2))); 1103 PM8001_FAIL_DBG(pm8001_ha, 1104 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n", 1105 pm8001_cr32(pm8001_ha, 0, 1106 MSGU_SCRATCH_PAD_3))); 1107 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1108 return -1; 1109 } 1110 1111 /* step 16 (Normal) - Clear ODMR and ODCR */ 1112 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); 1113 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); 1114 1115 /* step 17 (Normal Mode): wait for the FW and IOP to get 1116 ready - 1 sec timeout */ 1117 /* Wait for the SPC Configuration Table to be ready */ 1118 if (check_fw_ready(pm8001_ha) == -1) { 1119 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1120 /* return error if MPI Configuration Table not ready */ 1121 PM8001_INIT_DBG(pm8001_ha, 1122 pm8001_printk("FW not ready SCRATCH_PAD1" 1123 " = 0x%x\n", regVal)); 1124 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 1125 /* return error if MPI Configuration Table not ready */ 1126 PM8001_INIT_DBG(pm8001_ha, 1127 pm8001_printk("FW not ready SCRATCH_PAD2" 1128 " = 0x%x\n", regVal)); 1129 PM8001_INIT_DBG(pm8001_ha, 1130 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n", 1131 pm8001_cr32(pm8001_ha, 0, 1132 MSGU_SCRATCH_PAD_0))); 1133 PM8001_INIT_DBG(pm8001_ha, 1134 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n", 1135 pm8001_cr32(pm8001_ha, 0, 1136 MSGU_SCRATCH_PAD_3))); 1137 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1138 return -1; 1139 } 1140 } 1141 pm8001_bar4_shift(pm8001_ha, 0); 1142 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1143 1144 PM8001_INIT_DBG(pm8001_ha, 1145 pm8001_printk("SPC soft reset Complete\n")); 1146 return 0; 1147 } 1148 1149 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha) 1150 { 1151 u32 i; 1152 u32 regVal; 1153 PM8001_INIT_DBG(pm8001_ha, 1154 pm8001_printk("chip reset start\n")); 1155 1156 /* do SPC chip reset. */ 1157 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); 1158 regVal &= ~(SPC_REG_RESET_DEVICE); 1159 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); 1160 1161 /* delay 10 usec */ 1162 udelay(10); 1163 1164 /* bring chip reset out of reset */ 1165 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); 1166 regVal |= SPC_REG_RESET_DEVICE; 1167 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); 1168 1169 /* delay 10 usec */ 1170 udelay(10); 1171 1172 /* wait for 20 msec until the firmware gets reloaded */ 1173 i = 20; 1174 do { 1175 mdelay(1); 1176 } while ((--i) != 0); 1177 1178 PM8001_INIT_DBG(pm8001_ha, 1179 pm8001_printk("chip reset finished\n")); 1180 } 1181 1182 /** 1183 * pm8001_chip_iounmap - which maped when initialized. 1184 * @pm8001_ha: our hba card information 1185 */ 1186 void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha) 1187 { 1188 s8 bar, logical = 0; 1189 for (bar = 0; bar < 6; bar++) { 1190 /* 1191 ** logical BARs for SPC: 1192 ** bar 0 and 1 - logical BAR0 1193 ** bar 2 and 3 - logical BAR1 1194 ** bar4 - logical BAR2 1195 ** bar5 - logical BAR3 1196 ** Skip the appropriate assignments: 1197 */ 1198 if ((bar == 1) || (bar == 3)) 1199 continue; 1200 if (pm8001_ha->io_mem[logical].memvirtaddr) { 1201 iounmap(pm8001_ha->io_mem[logical].memvirtaddr); 1202 logical++; 1203 } 1204 } 1205 } 1206 1207 #ifndef PM8001_USE_MSIX 1208 /** 1209 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt 1210 * @pm8001_ha: our hba card information 1211 */ 1212 static void 1213 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha) 1214 { 1215 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); 1216 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); 1217 } 1218 1219 /** 1220 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt 1221 * @pm8001_ha: our hba card information 1222 */ 1223 static void 1224 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha) 1225 { 1226 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL); 1227 } 1228 1229 #else 1230 1231 /** 1232 * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt 1233 * @pm8001_ha: our hba card information 1234 */ 1235 static void 1236 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha, 1237 u32 int_vec_idx) 1238 { 1239 u32 msi_index; 1240 u32 value; 1241 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE; 1242 msi_index += MSIX_TABLE_BASE; 1243 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE); 1244 value = (1 << int_vec_idx); 1245 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, value); 1246 1247 } 1248 1249 /** 1250 * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt 1251 * @pm8001_ha: our hba card information 1252 */ 1253 static void 1254 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha, 1255 u32 int_vec_idx) 1256 { 1257 u32 msi_index; 1258 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE; 1259 msi_index += MSIX_TABLE_BASE; 1260 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE); 1261 } 1262 #endif 1263 1264 /** 1265 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt 1266 * @pm8001_ha: our hba card information 1267 */ 1268 static void 1269 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1270 { 1271 #ifdef PM8001_USE_MSIX 1272 pm8001_chip_msix_interrupt_enable(pm8001_ha, 0); 1273 #else 1274 pm8001_chip_intx_interrupt_enable(pm8001_ha); 1275 #endif 1276 } 1277 1278 /** 1279 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt 1280 * @pm8001_ha: our hba card information 1281 */ 1282 static void 1283 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1284 { 1285 #ifdef PM8001_USE_MSIX 1286 pm8001_chip_msix_interrupt_disable(pm8001_ha, 0); 1287 #else 1288 pm8001_chip_intx_interrupt_disable(pm8001_ha); 1289 #endif 1290 } 1291 1292 /** 1293 * pm8001_mpi_msg_free_get - get the free message buffer for transfer 1294 * inbound queue. 1295 * @circularQ: the inbound queue we want to transfer to HBA. 1296 * @messageSize: the message size of this transfer, normally it is 64 bytes 1297 * @messagePtr: the pointer to message. 1298 */ 1299 int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ, 1300 u16 messageSize, void **messagePtr) 1301 { 1302 u32 offset, consumer_index; 1303 struct mpi_msg_hdr *msgHeader; 1304 u8 bcCount = 1; /* only support single buffer */ 1305 1306 /* Checks is the requested message size can be allocated in this queue*/ 1307 if (messageSize > IOMB_SIZE_SPCV) { 1308 *messagePtr = NULL; 1309 return -1; 1310 } 1311 1312 /* Stores the new consumer index */ 1313 consumer_index = pm8001_read_32(circularQ->ci_virt); 1314 circularQ->consumer_index = cpu_to_le32(consumer_index); 1315 if (((circularQ->producer_idx + bcCount) % PM8001_MPI_QUEUE) == 1316 le32_to_cpu(circularQ->consumer_index)) { 1317 *messagePtr = NULL; 1318 return -1; 1319 } 1320 /* get memory IOMB buffer address */ 1321 offset = circularQ->producer_idx * messageSize; 1322 /* increment to next bcCount element */ 1323 circularQ->producer_idx = (circularQ->producer_idx + bcCount) 1324 % PM8001_MPI_QUEUE; 1325 /* Adds that distance to the base of the region virtual address plus 1326 the message header size*/ 1327 msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset); 1328 *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr); 1329 return 0; 1330 } 1331 1332 /** 1333 * pm8001_mpi_build_cmd- build the message queue for transfer, update the PI to 1334 * FW to tell the fw to get this message from IOMB. 1335 * @pm8001_ha: our hba card information 1336 * @circularQ: the inbound queue we want to transfer to HBA. 1337 * @opCode: the operation code represents commands which LLDD and fw recognized. 1338 * @payload: the command payload of each operation command. 1339 */ 1340 int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha, 1341 struct inbound_queue_table *circularQ, 1342 u32 opCode, void *payload, u32 responseQueue) 1343 { 1344 u32 Header = 0, hpriority = 0, bc = 1, category = 0x02; 1345 void *pMessage; 1346 1347 if (pm8001_mpi_msg_free_get(circularQ, pm8001_ha->iomb_size, 1348 &pMessage) < 0) { 1349 PM8001_IO_DBG(pm8001_ha, 1350 pm8001_printk("No free mpi buffer\n")); 1351 return -ENOMEM; 1352 } 1353 BUG_ON(!payload); 1354 /*Copy to the payload*/ 1355 memcpy(pMessage, payload, (pm8001_ha->iomb_size - 1356 sizeof(struct mpi_msg_hdr))); 1357 1358 /*Build the header*/ 1359 Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24) 1360 | ((responseQueue & 0x3F) << 16) 1361 | ((category & 0xF) << 12) | (opCode & 0xFFF)); 1362 1363 pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header)); 1364 /*Update the PI to the firmware*/ 1365 pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar, 1366 circularQ->pi_offset, circularQ->producer_idx); 1367 PM8001_IO_DBG(pm8001_ha, 1368 pm8001_printk("INB Q %x OPCODE:%x , UPDATED PI=%d CI=%d\n", 1369 responseQueue, opCode, circularQ->producer_idx, 1370 circularQ->consumer_index)); 1371 return 0; 1372 } 1373 1374 u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg, 1375 struct outbound_queue_table *circularQ, u8 bc) 1376 { 1377 u32 producer_index; 1378 struct mpi_msg_hdr *msgHeader; 1379 struct mpi_msg_hdr *pOutBoundMsgHeader; 1380 1381 msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr)); 1382 pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + 1383 circularQ->consumer_idx * pm8001_ha->iomb_size); 1384 if (pOutBoundMsgHeader != msgHeader) { 1385 PM8001_FAIL_DBG(pm8001_ha, 1386 pm8001_printk("consumer_idx = %d msgHeader = %p\n", 1387 circularQ->consumer_idx, msgHeader)); 1388 1389 /* Update the producer index from SPC */ 1390 producer_index = pm8001_read_32(circularQ->pi_virt); 1391 circularQ->producer_index = cpu_to_le32(producer_index); 1392 PM8001_FAIL_DBG(pm8001_ha, 1393 pm8001_printk("consumer_idx = %d producer_index = %d" 1394 "msgHeader = %p\n", circularQ->consumer_idx, 1395 circularQ->producer_index, msgHeader)); 1396 return 0; 1397 } 1398 /* free the circular queue buffer elements associated with the message*/ 1399 circularQ->consumer_idx = (circularQ->consumer_idx + bc) 1400 % PM8001_MPI_QUEUE; 1401 /* update the CI of outbound queue */ 1402 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset, 1403 circularQ->consumer_idx); 1404 /* Update the producer index from SPC*/ 1405 producer_index = pm8001_read_32(circularQ->pi_virt); 1406 circularQ->producer_index = cpu_to_le32(producer_index); 1407 PM8001_IO_DBG(pm8001_ha, 1408 pm8001_printk(" CI=%d PI=%d\n", circularQ->consumer_idx, 1409 circularQ->producer_index)); 1410 return 0; 1411 } 1412 1413 /** 1414 * pm8001_mpi_msg_consume- get the MPI message from outbound queue 1415 * message table. 1416 * @pm8001_ha: our hba card information 1417 * @circularQ: the outbound queue table. 1418 * @messagePtr1: the message contents of this outbound message. 1419 * @pBC: the message size. 1420 */ 1421 u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha, 1422 struct outbound_queue_table *circularQ, 1423 void **messagePtr1, u8 *pBC) 1424 { 1425 struct mpi_msg_hdr *msgHeader; 1426 __le32 msgHeader_tmp; 1427 u32 header_tmp; 1428 do { 1429 /* If there are not-yet-delivered messages ... */ 1430 if (le32_to_cpu(circularQ->producer_index) 1431 != circularQ->consumer_idx) { 1432 /*Get the pointer to the circular queue buffer element*/ 1433 msgHeader = (struct mpi_msg_hdr *) 1434 (circularQ->base_virt + 1435 circularQ->consumer_idx * pm8001_ha->iomb_size); 1436 /* read header */ 1437 header_tmp = pm8001_read_32(msgHeader); 1438 msgHeader_tmp = cpu_to_le32(header_tmp); 1439 if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) { 1440 if (OPC_OUB_SKIP_ENTRY != 1441 (le32_to_cpu(msgHeader_tmp) & 0xfff)) { 1442 *messagePtr1 = 1443 ((u8 *)msgHeader) + 1444 sizeof(struct mpi_msg_hdr); 1445 *pBC = (u8)((le32_to_cpu(msgHeader_tmp) 1446 >> 24) & 0x1f); 1447 PM8001_IO_DBG(pm8001_ha, 1448 pm8001_printk(": CI=%d PI=%d " 1449 "msgHeader=%x\n", 1450 circularQ->consumer_idx, 1451 circularQ->producer_index, 1452 msgHeader_tmp)); 1453 return MPI_IO_STATUS_SUCCESS; 1454 } else { 1455 circularQ->consumer_idx = 1456 (circularQ->consumer_idx + 1457 ((le32_to_cpu(msgHeader_tmp) 1458 >> 24) & 0x1f)) 1459 % PM8001_MPI_QUEUE; 1460 msgHeader_tmp = 0; 1461 pm8001_write_32(msgHeader, 0, 0); 1462 /* update the CI of outbound queue */ 1463 pm8001_cw32(pm8001_ha, 1464 circularQ->ci_pci_bar, 1465 circularQ->ci_offset, 1466 circularQ->consumer_idx); 1467 } 1468 } else { 1469 circularQ->consumer_idx = 1470 (circularQ->consumer_idx + 1471 ((le32_to_cpu(msgHeader_tmp) >> 24) & 1472 0x1f)) % PM8001_MPI_QUEUE; 1473 msgHeader_tmp = 0; 1474 pm8001_write_32(msgHeader, 0, 0); 1475 /* update the CI of outbound queue */ 1476 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, 1477 circularQ->ci_offset, 1478 circularQ->consumer_idx); 1479 return MPI_IO_STATUS_FAIL; 1480 } 1481 } else { 1482 u32 producer_index; 1483 void *pi_virt = circularQ->pi_virt; 1484 /* spurious interrupt during setup if 1485 * kexec-ing and driver doing a doorbell access 1486 * with the pre-kexec oq interrupt setup 1487 */ 1488 if (!pi_virt) 1489 break; 1490 /* Update the producer index from SPC */ 1491 producer_index = pm8001_read_32(pi_virt); 1492 circularQ->producer_index = cpu_to_le32(producer_index); 1493 } 1494 } while (le32_to_cpu(circularQ->producer_index) != 1495 circularQ->consumer_idx); 1496 /* while we don't have any more not-yet-delivered message */ 1497 /* report empty */ 1498 return MPI_IO_STATUS_BUSY; 1499 } 1500 1501 void pm8001_work_fn(struct work_struct *work) 1502 { 1503 struct pm8001_work *pw = container_of(work, struct pm8001_work, work); 1504 struct pm8001_device *pm8001_dev; 1505 struct domain_device *dev; 1506 1507 /* 1508 * So far, all users of this stash an associated structure here. 1509 * If we get here, and this pointer is null, then the action 1510 * was cancelled. This nullification happens when the device 1511 * goes away. 1512 */ 1513 pm8001_dev = pw->data; /* Most stash device structure */ 1514 if ((pm8001_dev == NULL) 1515 || ((pw->handler != IO_XFER_ERROR_BREAK) 1516 && (pm8001_dev->dev_type == SAS_PHY_UNUSED))) { 1517 kfree(pw); 1518 return; 1519 } 1520 1521 switch (pw->handler) { 1522 case IO_XFER_ERROR_BREAK: 1523 { /* This one stashes the sas_task instead */ 1524 struct sas_task *t = (struct sas_task *)pm8001_dev; 1525 u32 tag; 1526 struct pm8001_ccb_info *ccb; 1527 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha; 1528 unsigned long flags, flags1; 1529 struct task_status_struct *ts; 1530 int i; 1531 1532 if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC) 1533 break; /* Task still on lu */ 1534 spin_lock_irqsave(&pm8001_ha->lock, flags); 1535 1536 spin_lock_irqsave(&t->task_state_lock, flags1); 1537 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) { 1538 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1539 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1540 break; /* Task got completed by another */ 1541 } 1542 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1543 1544 /* Search for a possible ccb that matches the task */ 1545 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) { 1546 ccb = &pm8001_ha->ccb_info[i]; 1547 tag = ccb->ccb_tag; 1548 if ((tag != 0xFFFFFFFF) && (ccb->task == t)) 1549 break; 1550 } 1551 if (!ccb) { 1552 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1553 break; /* Task got freed by another */ 1554 } 1555 ts = &t->task_status; 1556 ts->resp = SAS_TASK_COMPLETE; 1557 /* Force the midlayer to retry */ 1558 ts->stat = SAS_QUEUE_FULL; 1559 pm8001_dev = ccb->device; 1560 if (pm8001_dev) 1561 pm8001_dev->running_req--; 1562 spin_lock_irqsave(&t->task_state_lock, flags1); 1563 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 1564 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 1565 t->task_state_flags |= SAS_TASK_STATE_DONE; 1566 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 1567 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1568 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p" 1569 " done with event 0x%x resp 0x%x stat 0x%x but" 1570 " aborted by upper layer!\n", 1571 t, pw->handler, ts->resp, ts->stat)); 1572 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1573 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1574 } else { 1575 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1576 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1577 mb();/* in order to force CPU ordering */ 1578 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1579 t->task_done(t); 1580 } 1581 } break; 1582 case IO_XFER_OPEN_RETRY_TIMEOUT: 1583 { /* This one stashes the sas_task instead */ 1584 struct sas_task *t = (struct sas_task *)pm8001_dev; 1585 u32 tag; 1586 struct pm8001_ccb_info *ccb; 1587 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha; 1588 unsigned long flags, flags1; 1589 int i, ret = 0; 1590 1591 PM8001_IO_DBG(pm8001_ha, 1592 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 1593 1594 ret = pm8001_query_task(t); 1595 1596 PM8001_IO_DBG(pm8001_ha, 1597 switch (ret) { 1598 case TMF_RESP_FUNC_SUCC: 1599 pm8001_printk("...Task on lu\n"); 1600 break; 1601 1602 case TMF_RESP_FUNC_COMPLETE: 1603 pm8001_printk("...Task NOT on lu\n"); 1604 break; 1605 1606 default: 1607 pm8001_printk("...query task failed!!!\n"); 1608 break; 1609 }); 1610 1611 spin_lock_irqsave(&pm8001_ha->lock, flags); 1612 1613 spin_lock_irqsave(&t->task_state_lock, flags1); 1614 1615 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) { 1616 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1617 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1618 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */ 1619 (void)pm8001_abort_task(t); 1620 break; /* Task got completed by another */ 1621 } 1622 1623 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1624 1625 /* Search for a possible ccb that matches the task */ 1626 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) { 1627 ccb = &pm8001_ha->ccb_info[i]; 1628 tag = ccb->ccb_tag; 1629 if ((tag != 0xFFFFFFFF) && (ccb->task == t)) 1630 break; 1631 } 1632 if (!ccb) { 1633 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1634 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */ 1635 (void)pm8001_abort_task(t); 1636 break; /* Task got freed by another */ 1637 } 1638 1639 pm8001_dev = ccb->device; 1640 dev = pm8001_dev->sas_device; 1641 1642 switch (ret) { 1643 case TMF_RESP_FUNC_SUCC: /* task on lu */ 1644 ccb->open_retry = 1; /* Snub completion */ 1645 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1646 ret = pm8001_abort_task(t); 1647 ccb->open_retry = 0; 1648 switch (ret) { 1649 case TMF_RESP_FUNC_SUCC: 1650 case TMF_RESP_FUNC_COMPLETE: 1651 break; 1652 default: /* device misbehavior */ 1653 ret = TMF_RESP_FUNC_FAILED; 1654 PM8001_IO_DBG(pm8001_ha, 1655 pm8001_printk("...Reset phy\n")); 1656 pm8001_I_T_nexus_reset(dev); 1657 break; 1658 } 1659 break; 1660 1661 case TMF_RESP_FUNC_COMPLETE: /* task not on lu */ 1662 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1663 /* Do we need to abort the task locally? */ 1664 break; 1665 1666 default: /* device misbehavior */ 1667 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1668 ret = TMF_RESP_FUNC_FAILED; 1669 PM8001_IO_DBG(pm8001_ha, 1670 pm8001_printk("...Reset phy\n")); 1671 pm8001_I_T_nexus_reset(dev); 1672 } 1673 1674 if (ret == TMF_RESP_FUNC_FAILED) 1675 t = NULL; 1676 pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev); 1677 PM8001_IO_DBG(pm8001_ha, pm8001_printk("...Complete\n")); 1678 } break; 1679 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1680 dev = pm8001_dev->sas_device; 1681 pm8001_I_T_nexus_event_handler(dev); 1682 break; 1683 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 1684 dev = pm8001_dev->sas_device; 1685 pm8001_I_T_nexus_reset(dev); 1686 break; 1687 case IO_DS_IN_ERROR: 1688 dev = pm8001_dev->sas_device; 1689 pm8001_I_T_nexus_reset(dev); 1690 break; 1691 case IO_DS_NON_OPERATIONAL: 1692 dev = pm8001_dev->sas_device; 1693 pm8001_I_T_nexus_reset(dev); 1694 break; 1695 } 1696 kfree(pw); 1697 } 1698 1699 int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data, 1700 int handler) 1701 { 1702 struct pm8001_work *pw; 1703 int ret = 0; 1704 1705 pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC); 1706 if (pw) { 1707 pw->pm8001_ha = pm8001_ha; 1708 pw->data = data; 1709 pw->handler = handler; 1710 INIT_WORK(&pw->work, pm8001_work_fn); 1711 queue_work(pm8001_wq, &pw->work); 1712 } else 1713 ret = -ENOMEM; 1714 1715 return ret; 1716 } 1717 1718 static void pm8001_send_abort_all(struct pm8001_hba_info *pm8001_ha, 1719 struct pm8001_device *pm8001_ha_dev) 1720 { 1721 int res; 1722 u32 ccb_tag; 1723 struct pm8001_ccb_info *ccb; 1724 struct sas_task *task = NULL; 1725 struct task_abort_req task_abort; 1726 struct inbound_queue_table *circularQ; 1727 u32 opc = OPC_INB_SATA_ABORT; 1728 int ret; 1729 1730 if (!pm8001_ha_dev) { 1731 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n")); 1732 return; 1733 } 1734 1735 task = sas_alloc_slow_task(GFP_ATOMIC); 1736 1737 if (!task) { 1738 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot " 1739 "allocate task\n")); 1740 return; 1741 } 1742 1743 task->task_done = pm8001_task_done; 1744 1745 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); 1746 if (res) 1747 return; 1748 1749 ccb = &pm8001_ha->ccb_info[ccb_tag]; 1750 ccb->device = pm8001_ha_dev; 1751 ccb->ccb_tag = ccb_tag; 1752 ccb->task = task; 1753 1754 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1755 1756 memset(&task_abort, 0, sizeof(task_abort)); 1757 task_abort.abort_all = cpu_to_le32(1); 1758 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 1759 task_abort.tag = cpu_to_le32(ccb_tag); 1760 1761 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0); 1762 if (ret) 1763 pm8001_tag_free(pm8001_ha, ccb_tag); 1764 1765 } 1766 1767 static void pm8001_send_read_log(struct pm8001_hba_info *pm8001_ha, 1768 struct pm8001_device *pm8001_ha_dev) 1769 { 1770 struct sata_start_req sata_cmd; 1771 int res; 1772 u32 ccb_tag; 1773 struct pm8001_ccb_info *ccb; 1774 struct sas_task *task = NULL; 1775 struct host_to_dev_fis fis; 1776 struct domain_device *dev; 1777 struct inbound_queue_table *circularQ; 1778 u32 opc = OPC_INB_SATA_HOST_OPSTART; 1779 1780 task = sas_alloc_slow_task(GFP_ATOMIC); 1781 1782 if (!task) { 1783 PM8001_FAIL_DBG(pm8001_ha, 1784 pm8001_printk("cannot allocate task !!!\n")); 1785 return; 1786 } 1787 task->task_done = pm8001_task_done; 1788 1789 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); 1790 if (res) { 1791 sas_free_task(task); 1792 PM8001_FAIL_DBG(pm8001_ha, 1793 pm8001_printk("cannot allocate tag !!!\n")); 1794 return; 1795 } 1796 1797 /* allocate domain device by ourselves as libsas 1798 * is not going to provide any 1799 */ 1800 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC); 1801 if (!dev) { 1802 sas_free_task(task); 1803 pm8001_tag_free(pm8001_ha, ccb_tag); 1804 PM8001_FAIL_DBG(pm8001_ha, 1805 pm8001_printk("Domain device cannot be allocated\n")); 1806 return; 1807 } 1808 task->dev = dev; 1809 task->dev->lldd_dev = pm8001_ha_dev; 1810 1811 ccb = &pm8001_ha->ccb_info[ccb_tag]; 1812 ccb->device = pm8001_ha_dev; 1813 ccb->ccb_tag = ccb_tag; 1814 ccb->task = task; 1815 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG; 1816 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG; 1817 1818 memset(&sata_cmd, 0, sizeof(sata_cmd)); 1819 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1820 1821 /* construct read log FIS */ 1822 memset(&fis, 0, sizeof(struct host_to_dev_fis)); 1823 fis.fis_type = 0x27; 1824 fis.flags = 0x80; 1825 fis.command = ATA_CMD_READ_LOG_EXT; 1826 fis.lbal = 0x10; 1827 fis.sector_count = 0x1; 1828 1829 sata_cmd.tag = cpu_to_le32(ccb_tag); 1830 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 1831 sata_cmd.ncqtag_atap_dir_m |= ((0x1 << 7) | (0x5 << 9)); 1832 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis)); 1833 1834 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0); 1835 if (res) { 1836 sas_free_task(task); 1837 pm8001_tag_free(pm8001_ha, ccb_tag); 1838 kfree(dev); 1839 } 1840 } 1841 1842 /** 1843 * mpi_ssp_completion- process the event that FW response to the SSP request. 1844 * @pm8001_ha: our hba card information 1845 * @piomb: the message contents of this outbound message. 1846 * 1847 * When FW has completed a ssp request for example a IO request, after it has 1848 * filled the SG data with the data, it will trigger this event represent 1849 * that he has finished the job,please check the coresponding buffer. 1850 * So we will tell the caller who maybe waiting the result to tell upper layer 1851 * that the task has been finished. 1852 */ 1853 static void 1854 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb) 1855 { 1856 struct sas_task *t; 1857 struct pm8001_ccb_info *ccb; 1858 unsigned long flags; 1859 u32 status; 1860 u32 param; 1861 u32 tag; 1862 struct ssp_completion_resp *psspPayload; 1863 struct task_status_struct *ts; 1864 struct ssp_response_iu *iu; 1865 struct pm8001_device *pm8001_dev; 1866 psspPayload = (struct ssp_completion_resp *)(piomb + 4); 1867 status = le32_to_cpu(psspPayload->status); 1868 tag = le32_to_cpu(psspPayload->tag); 1869 ccb = &pm8001_ha->ccb_info[tag]; 1870 if ((status == IO_ABORTED) && ccb->open_retry) { 1871 /* Being completed by another */ 1872 ccb->open_retry = 0; 1873 return; 1874 } 1875 pm8001_dev = ccb->device; 1876 param = le32_to_cpu(psspPayload->param); 1877 1878 t = ccb->task; 1879 1880 if (status && status != IO_UNDERFLOW) 1881 PM8001_FAIL_DBG(pm8001_ha, 1882 pm8001_printk("sas IO status 0x%x\n", status)); 1883 if (unlikely(!t || !t->lldd_task || !t->dev)) 1884 return; 1885 ts = &t->task_status; 1886 /* Print sas address of IO failed device */ 1887 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 1888 (status != IO_UNDERFLOW)) 1889 PM8001_FAIL_DBG(pm8001_ha, 1890 pm8001_printk("SAS Address of IO Failure Drive:" 1891 "%016llx", SAS_ADDR(t->dev->sas_addr))); 1892 1893 switch (status) { 1894 case IO_SUCCESS: 1895 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS" 1896 ",param = %d\n", param)); 1897 if (param == 0) { 1898 ts->resp = SAS_TASK_COMPLETE; 1899 ts->stat = SAM_STAT_GOOD; 1900 } else { 1901 ts->resp = SAS_TASK_COMPLETE; 1902 ts->stat = SAS_PROTO_RESPONSE; 1903 ts->residual = param; 1904 iu = &psspPayload->ssp_resp_iu; 1905 sas_ssp_task_response(pm8001_ha->dev, t, iu); 1906 } 1907 if (pm8001_dev) 1908 pm8001_dev->running_req--; 1909 break; 1910 case IO_ABORTED: 1911 PM8001_IO_DBG(pm8001_ha, 1912 pm8001_printk("IO_ABORTED IOMB Tag\n")); 1913 ts->resp = SAS_TASK_COMPLETE; 1914 ts->stat = SAS_ABORTED_TASK; 1915 break; 1916 case IO_UNDERFLOW: 1917 /* SSP Completion with error */ 1918 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW" 1919 ",param = %d\n", param)); 1920 ts->resp = SAS_TASK_COMPLETE; 1921 ts->stat = SAS_DATA_UNDERRUN; 1922 ts->residual = param; 1923 if (pm8001_dev) 1924 pm8001_dev->running_req--; 1925 break; 1926 case IO_NO_DEVICE: 1927 PM8001_IO_DBG(pm8001_ha, 1928 pm8001_printk("IO_NO_DEVICE\n")); 1929 ts->resp = SAS_TASK_UNDELIVERED; 1930 ts->stat = SAS_PHY_DOWN; 1931 break; 1932 case IO_XFER_ERROR_BREAK: 1933 PM8001_IO_DBG(pm8001_ha, 1934 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 1935 ts->resp = SAS_TASK_COMPLETE; 1936 ts->stat = SAS_OPEN_REJECT; 1937 /* Force the midlayer to retry */ 1938 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1939 break; 1940 case IO_XFER_ERROR_PHY_NOT_READY: 1941 PM8001_IO_DBG(pm8001_ha, 1942 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 1943 ts->resp = SAS_TASK_COMPLETE; 1944 ts->stat = SAS_OPEN_REJECT; 1945 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1946 break; 1947 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 1948 PM8001_IO_DBG(pm8001_ha, 1949 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 1950 ts->resp = SAS_TASK_COMPLETE; 1951 ts->stat = SAS_OPEN_REJECT; 1952 ts->open_rej_reason = SAS_OREJ_EPROTO; 1953 break; 1954 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 1955 PM8001_IO_DBG(pm8001_ha, 1956 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 1957 ts->resp = SAS_TASK_COMPLETE; 1958 ts->stat = SAS_OPEN_REJECT; 1959 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1960 break; 1961 case IO_OPEN_CNX_ERROR_BREAK: 1962 PM8001_IO_DBG(pm8001_ha, 1963 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 1964 ts->resp = SAS_TASK_COMPLETE; 1965 ts->stat = SAS_OPEN_REJECT; 1966 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1967 break; 1968 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1969 PM8001_IO_DBG(pm8001_ha, 1970 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 1971 ts->resp = SAS_TASK_COMPLETE; 1972 ts->stat = SAS_OPEN_REJECT; 1973 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1974 if (!t->uldd_task) 1975 pm8001_handle_event(pm8001_ha, 1976 pm8001_dev, 1977 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 1978 break; 1979 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 1980 PM8001_IO_DBG(pm8001_ha, 1981 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 1982 ts->resp = SAS_TASK_COMPLETE; 1983 ts->stat = SAS_OPEN_REJECT; 1984 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 1985 break; 1986 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 1987 PM8001_IO_DBG(pm8001_ha, 1988 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 1989 "NOT_SUPPORTED\n")); 1990 ts->resp = SAS_TASK_COMPLETE; 1991 ts->stat = SAS_OPEN_REJECT; 1992 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 1993 break; 1994 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 1995 PM8001_IO_DBG(pm8001_ha, 1996 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 1997 ts->resp = SAS_TASK_UNDELIVERED; 1998 ts->stat = SAS_OPEN_REJECT; 1999 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2000 break; 2001 case IO_XFER_ERROR_NAK_RECEIVED: 2002 PM8001_IO_DBG(pm8001_ha, 2003 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 2004 ts->resp = SAS_TASK_COMPLETE; 2005 ts->stat = SAS_OPEN_REJECT; 2006 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2007 break; 2008 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2009 PM8001_IO_DBG(pm8001_ha, 2010 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 2011 ts->resp = SAS_TASK_COMPLETE; 2012 ts->stat = SAS_NAK_R_ERR; 2013 break; 2014 case IO_XFER_ERROR_DMA: 2015 PM8001_IO_DBG(pm8001_ha, 2016 pm8001_printk("IO_XFER_ERROR_DMA\n")); 2017 ts->resp = SAS_TASK_COMPLETE; 2018 ts->stat = SAS_OPEN_REJECT; 2019 break; 2020 case IO_XFER_OPEN_RETRY_TIMEOUT: 2021 PM8001_IO_DBG(pm8001_ha, 2022 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2023 ts->resp = SAS_TASK_COMPLETE; 2024 ts->stat = SAS_OPEN_REJECT; 2025 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2026 break; 2027 case IO_XFER_ERROR_OFFSET_MISMATCH: 2028 PM8001_IO_DBG(pm8001_ha, 2029 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 2030 ts->resp = SAS_TASK_COMPLETE; 2031 ts->stat = SAS_OPEN_REJECT; 2032 break; 2033 case IO_PORT_IN_RESET: 2034 PM8001_IO_DBG(pm8001_ha, 2035 pm8001_printk("IO_PORT_IN_RESET\n")); 2036 ts->resp = SAS_TASK_COMPLETE; 2037 ts->stat = SAS_OPEN_REJECT; 2038 break; 2039 case IO_DS_NON_OPERATIONAL: 2040 PM8001_IO_DBG(pm8001_ha, 2041 pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 2042 ts->resp = SAS_TASK_COMPLETE; 2043 ts->stat = SAS_OPEN_REJECT; 2044 if (!t->uldd_task) 2045 pm8001_handle_event(pm8001_ha, 2046 pm8001_dev, 2047 IO_DS_NON_OPERATIONAL); 2048 break; 2049 case IO_DS_IN_RECOVERY: 2050 PM8001_IO_DBG(pm8001_ha, 2051 pm8001_printk("IO_DS_IN_RECOVERY\n")); 2052 ts->resp = SAS_TASK_COMPLETE; 2053 ts->stat = SAS_OPEN_REJECT; 2054 break; 2055 case IO_TM_TAG_NOT_FOUND: 2056 PM8001_IO_DBG(pm8001_ha, 2057 pm8001_printk("IO_TM_TAG_NOT_FOUND\n")); 2058 ts->resp = SAS_TASK_COMPLETE; 2059 ts->stat = SAS_OPEN_REJECT; 2060 break; 2061 case IO_SSP_EXT_IU_ZERO_LEN_ERROR: 2062 PM8001_IO_DBG(pm8001_ha, 2063 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n")); 2064 ts->resp = SAS_TASK_COMPLETE; 2065 ts->stat = SAS_OPEN_REJECT; 2066 break; 2067 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2068 PM8001_IO_DBG(pm8001_ha, 2069 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 2070 ts->resp = SAS_TASK_COMPLETE; 2071 ts->stat = SAS_OPEN_REJECT; 2072 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2073 break; 2074 default: 2075 PM8001_IO_DBG(pm8001_ha, 2076 pm8001_printk("Unknown status 0x%x\n", status)); 2077 /* not allowed case. Therefore, return failed status */ 2078 ts->resp = SAS_TASK_COMPLETE; 2079 ts->stat = SAS_OPEN_REJECT; 2080 break; 2081 } 2082 PM8001_IO_DBG(pm8001_ha, 2083 pm8001_printk("scsi_status = %x\n ", 2084 psspPayload->ssp_resp_iu.status)); 2085 spin_lock_irqsave(&t->task_state_lock, flags); 2086 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2087 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2088 t->task_state_flags |= SAS_TASK_STATE_DONE; 2089 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2090 spin_unlock_irqrestore(&t->task_state_lock, flags); 2091 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with" 2092 " io_status 0x%x resp 0x%x " 2093 "stat 0x%x but aborted by upper layer!\n", 2094 t, status, ts->resp, ts->stat)); 2095 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2096 } else { 2097 spin_unlock_irqrestore(&t->task_state_lock, flags); 2098 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2099 mb();/* in order to force CPU ordering */ 2100 t->task_done(t); 2101 } 2102 } 2103 2104 /*See the comments for mpi_ssp_completion */ 2105 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 2106 { 2107 struct sas_task *t; 2108 unsigned long flags; 2109 struct task_status_struct *ts; 2110 struct pm8001_ccb_info *ccb; 2111 struct pm8001_device *pm8001_dev; 2112 struct ssp_event_resp *psspPayload = 2113 (struct ssp_event_resp *)(piomb + 4); 2114 u32 event = le32_to_cpu(psspPayload->event); 2115 u32 tag = le32_to_cpu(psspPayload->tag); 2116 u32 port_id = le32_to_cpu(psspPayload->port_id); 2117 u32 dev_id = le32_to_cpu(psspPayload->device_id); 2118 2119 ccb = &pm8001_ha->ccb_info[tag]; 2120 t = ccb->task; 2121 pm8001_dev = ccb->device; 2122 if (event) 2123 PM8001_FAIL_DBG(pm8001_ha, 2124 pm8001_printk("sas IO status 0x%x\n", event)); 2125 if (unlikely(!t || !t->lldd_task || !t->dev)) 2126 return; 2127 ts = &t->task_status; 2128 PM8001_IO_DBG(pm8001_ha, 2129 pm8001_printk("port_id = %x,device_id = %x\n", 2130 port_id, dev_id)); 2131 switch (event) { 2132 case IO_OVERFLOW: 2133 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");) 2134 ts->resp = SAS_TASK_COMPLETE; 2135 ts->stat = SAS_DATA_OVERRUN; 2136 ts->residual = 0; 2137 if (pm8001_dev) 2138 pm8001_dev->running_req--; 2139 break; 2140 case IO_XFER_ERROR_BREAK: 2141 PM8001_IO_DBG(pm8001_ha, 2142 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2143 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK); 2144 return; 2145 case IO_XFER_ERROR_PHY_NOT_READY: 2146 PM8001_IO_DBG(pm8001_ha, 2147 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2148 ts->resp = SAS_TASK_COMPLETE; 2149 ts->stat = SAS_OPEN_REJECT; 2150 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2151 break; 2152 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2153 PM8001_IO_DBG(pm8001_ha, 2154 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT" 2155 "_SUPPORTED\n")); 2156 ts->resp = SAS_TASK_COMPLETE; 2157 ts->stat = SAS_OPEN_REJECT; 2158 ts->open_rej_reason = SAS_OREJ_EPROTO; 2159 break; 2160 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2161 PM8001_IO_DBG(pm8001_ha, 2162 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2163 ts->resp = SAS_TASK_COMPLETE; 2164 ts->stat = SAS_OPEN_REJECT; 2165 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2166 break; 2167 case IO_OPEN_CNX_ERROR_BREAK: 2168 PM8001_IO_DBG(pm8001_ha, 2169 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2170 ts->resp = SAS_TASK_COMPLETE; 2171 ts->stat = SAS_OPEN_REJECT; 2172 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2173 break; 2174 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2175 PM8001_IO_DBG(pm8001_ha, 2176 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2177 ts->resp = SAS_TASK_COMPLETE; 2178 ts->stat = SAS_OPEN_REJECT; 2179 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2180 if (!t->uldd_task) 2181 pm8001_handle_event(pm8001_ha, 2182 pm8001_dev, 2183 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2184 break; 2185 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2186 PM8001_IO_DBG(pm8001_ha, 2187 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2188 ts->resp = SAS_TASK_COMPLETE; 2189 ts->stat = SAS_OPEN_REJECT; 2190 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2191 break; 2192 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2193 PM8001_IO_DBG(pm8001_ha, 2194 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 2195 "NOT_SUPPORTED\n")); 2196 ts->resp = SAS_TASK_COMPLETE; 2197 ts->stat = SAS_OPEN_REJECT; 2198 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2199 break; 2200 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2201 PM8001_IO_DBG(pm8001_ha, 2202 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2203 ts->resp = SAS_TASK_COMPLETE; 2204 ts->stat = SAS_OPEN_REJECT; 2205 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2206 break; 2207 case IO_XFER_ERROR_NAK_RECEIVED: 2208 PM8001_IO_DBG(pm8001_ha, 2209 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 2210 ts->resp = SAS_TASK_COMPLETE; 2211 ts->stat = SAS_OPEN_REJECT; 2212 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2213 break; 2214 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2215 PM8001_IO_DBG(pm8001_ha, 2216 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 2217 ts->resp = SAS_TASK_COMPLETE; 2218 ts->stat = SAS_NAK_R_ERR; 2219 break; 2220 case IO_XFER_OPEN_RETRY_TIMEOUT: 2221 PM8001_IO_DBG(pm8001_ha, 2222 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2223 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT); 2224 return; 2225 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2226 PM8001_IO_DBG(pm8001_ha, 2227 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n")); 2228 ts->resp = SAS_TASK_COMPLETE; 2229 ts->stat = SAS_DATA_OVERRUN; 2230 break; 2231 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2232 PM8001_IO_DBG(pm8001_ha, 2233 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n")); 2234 ts->resp = SAS_TASK_COMPLETE; 2235 ts->stat = SAS_DATA_OVERRUN; 2236 break; 2237 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2238 PM8001_IO_DBG(pm8001_ha, 2239 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n")); 2240 ts->resp = SAS_TASK_COMPLETE; 2241 ts->stat = SAS_DATA_OVERRUN; 2242 break; 2243 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT: 2244 PM8001_IO_DBG(pm8001_ha, 2245 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n")); 2246 ts->resp = SAS_TASK_COMPLETE; 2247 ts->stat = SAS_DATA_OVERRUN; 2248 break; 2249 case IO_XFER_ERROR_OFFSET_MISMATCH: 2250 PM8001_IO_DBG(pm8001_ha, 2251 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 2252 ts->resp = SAS_TASK_COMPLETE; 2253 ts->stat = SAS_DATA_OVERRUN; 2254 break; 2255 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2256 PM8001_IO_DBG(pm8001_ha, 2257 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n")); 2258 ts->resp = SAS_TASK_COMPLETE; 2259 ts->stat = SAS_DATA_OVERRUN; 2260 break; 2261 case IO_XFER_CMD_FRAME_ISSUED: 2262 PM8001_IO_DBG(pm8001_ha, 2263 pm8001_printk(" IO_XFER_CMD_FRAME_ISSUED\n")); 2264 return; 2265 default: 2266 PM8001_IO_DBG(pm8001_ha, 2267 pm8001_printk("Unknown status 0x%x\n", event)); 2268 /* not allowed case. Therefore, return failed status */ 2269 ts->resp = SAS_TASK_COMPLETE; 2270 ts->stat = SAS_DATA_OVERRUN; 2271 break; 2272 } 2273 spin_lock_irqsave(&t->task_state_lock, flags); 2274 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2275 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2276 t->task_state_flags |= SAS_TASK_STATE_DONE; 2277 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2278 spin_unlock_irqrestore(&t->task_state_lock, flags); 2279 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with" 2280 " event 0x%x resp 0x%x " 2281 "stat 0x%x but aborted by upper layer!\n", 2282 t, event, ts->resp, ts->stat)); 2283 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2284 } else { 2285 spin_unlock_irqrestore(&t->task_state_lock, flags); 2286 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2287 mb();/* in order to force CPU ordering */ 2288 t->task_done(t); 2289 } 2290 } 2291 2292 /*See the comments for mpi_ssp_completion */ 2293 static void 2294 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2295 { 2296 struct sas_task *t; 2297 struct pm8001_ccb_info *ccb; 2298 u32 param; 2299 u32 status; 2300 u32 tag; 2301 int i, j; 2302 u8 sata_addr_low[4]; 2303 u32 temp_sata_addr_low; 2304 u8 sata_addr_hi[4]; 2305 u32 temp_sata_addr_hi; 2306 struct sata_completion_resp *psataPayload; 2307 struct task_status_struct *ts; 2308 struct ata_task_resp *resp ; 2309 u32 *sata_resp; 2310 struct pm8001_device *pm8001_dev; 2311 unsigned long flags; 2312 2313 psataPayload = (struct sata_completion_resp *)(piomb + 4); 2314 status = le32_to_cpu(psataPayload->status); 2315 tag = le32_to_cpu(psataPayload->tag); 2316 2317 if (!tag) { 2318 PM8001_FAIL_DBG(pm8001_ha, 2319 pm8001_printk("tag null\n")); 2320 return; 2321 } 2322 ccb = &pm8001_ha->ccb_info[tag]; 2323 param = le32_to_cpu(psataPayload->param); 2324 if (ccb) { 2325 t = ccb->task; 2326 pm8001_dev = ccb->device; 2327 } else { 2328 PM8001_FAIL_DBG(pm8001_ha, 2329 pm8001_printk("ccb null\n")); 2330 return; 2331 } 2332 2333 if (t) { 2334 if (t->dev && (t->dev->lldd_dev)) 2335 pm8001_dev = t->dev->lldd_dev; 2336 } else { 2337 PM8001_FAIL_DBG(pm8001_ha, 2338 pm8001_printk("task null\n")); 2339 return; 2340 } 2341 2342 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG)) 2343 && unlikely(!t || !t->lldd_task || !t->dev)) { 2344 PM8001_FAIL_DBG(pm8001_ha, 2345 pm8001_printk("task or dev null\n")); 2346 return; 2347 } 2348 2349 ts = &t->task_status; 2350 if (!ts) { 2351 PM8001_FAIL_DBG(pm8001_ha, 2352 pm8001_printk("ts null\n")); 2353 return; 2354 } 2355 /* Print sas address of IO failed device */ 2356 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 2357 (status != IO_UNDERFLOW)) { 2358 if (!((t->dev->parent) && 2359 (dev_is_expander(t->dev->parent->dev_type)))) { 2360 for (i = 0 , j = 4; j <= 7 && i <= 3; i++ , j++) 2361 sata_addr_low[i] = pm8001_ha->sas_addr[j]; 2362 for (i = 0 , j = 0; j <= 3 && i <= 3; i++ , j++) 2363 sata_addr_hi[i] = pm8001_ha->sas_addr[j]; 2364 memcpy(&temp_sata_addr_low, sata_addr_low, 2365 sizeof(sata_addr_low)); 2366 memcpy(&temp_sata_addr_hi, sata_addr_hi, 2367 sizeof(sata_addr_hi)); 2368 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff) 2369 |((temp_sata_addr_hi << 8) & 2370 0xff0000) | 2371 ((temp_sata_addr_hi >> 8) 2372 & 0xff00) | 2373 ((temp_sata_addr_hi << 24) & 2374 0xff000000)); 2375 temp_sata_addr_low = ((((temp_sata_addr_low >> 24) 2376 & 0xff) | 2377 ((temp_sata_addr_low << 8) 2378 & 0xff0000) | 2379 ((temp_sata_addr_low >> 8) 2380 & 0xff00) | 2381 ((temp_sata_addr_low << 24) 2382 & 0xff000000)) + 2383 pm8001_dev->attached_phy + 2384 0x10); 2385 PM8001_FAIL_DBG(pm8001_ha, 2386 pm8001_printk("SAS Address of IO Failure Drive:" 2387 "%08x%08x", temp_sata_addr_hi, 2388 temp_sata_addr_low)); 2389 } else { 2390 PM8001_FAIL_DBG(pm8001_ha, 2391 pm8001_printk("SAS Address of IO Failure Drive:" 2392 "%016llx", SAS_ADDR(t->dev->sas_addr))); 2393 } 2394 } 2395 switch (status) { 2396 case IO_SUCCESS: 2397 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); 2398 if (param == 0) { 2399 ts->resp = SAS_TASK_COMPLETE; 2400 ts->stat = SAM_STAT_GOOD; 2401 /* check if response is for SEND READ LOG */ 2402 if (pm8001_dev && 2403 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) { 2404 /* set new bit for abort_all */ 2405 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG; 2406 /* clear bit for read log */ 2407 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF; 2408 pm8001_send_abort_all(pm8001_ha, pm8001_dev); 2409 /* Free the tag */ 2410 pm8001_tag_free(pm8001_ha, tag); 2411 sas_free_task(t); 2412 return; 2413 } 2414 } else { 2415 u8 len; 2416 ts->resp = SAS_TASK_COMPLETE; 2417 ts->stat = SAS_PROTO_RESPONSE; 2418 ts->residual = param; 2419 PM8001_IO_DBG(pm8001_ha, 2420 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n", 2421 param)); 2422 sata_resp = &psataPayload->sata_resp[0]; 2423 resp = (struct ata_task_resp *)ts->buf; 2424 if (t->ata_task.dma_xfer == 0 && 2425 t->data_dir == DMA_FROM_DEVICE) { 2426 len = sizeof(struct pio_setup_fis); 2427 PM8001_IO_DBG(pm8001_ha, 2428 pm8001_printk("PIO read len = %d\n", len)); 2429 } else if (t->ata_task.use_ncq) { 2430 len = sizeof(struct set_dev_bits_fis); 2431 PM8001_IO_DBG(pm8001_ha, 2432 pm8001_printk("FPDMA len = %d\n", len)); 2433 } else { 2434 len = sizeof(struct dev_to_host_fis); 2435 PM8001_IO_DBG(pm8001_ha, 2436 pm8001_printk("other len = %d\n", len)); 2437 } 2438 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) { 2439 resp->frame_len = len; 2440 memcpy(&resp->ending_fis[0], sata_resp, len); 2441 ts->buf_valid_size = sizeof(*resp); 2442 } else 2443 PM8001_IO_DBG(pm8001_ha, 2444 pm8001_printk("response to large\n")); 2445 } 2446 if (pm8001_dev) 2447 pm8001_dev->running_req--; 2448 break; 2449 case IO_ABORTED: 2450 PM8001_IO_DBG(pm8001_ha, 2451 pm8001_printk("IO_ABORTED IOMB Tag\n")); 2452 ts->resp = SAS_TASK_COMPLETE; 2453 ts->stat = SAS_ABORTED_TASK; 2454 if (pm8001_dev) 2455 pm8001_dev->running_req--; 2456 break; 2457 /* following cases are to do cases */ 2458 case IO_UNDERFLOW: 2459 /* SATA Completion with error */ 2460 PM8001_IO_DBG(pm8001_ha, 2461 pm8001_printk("IO_UNDERFLOW param = %d\n", param)); 2462 ts->resp = SAS_TASK_COMPLETE; 2463 ts->stat = SAS_DATA_UNDERRUN; 2464 ts->residual = param; 2465 if (pm8001_dev) 2466 pm8001_dev->running_req--; 2467 break; 2468 case IO_NO_DEVICE: 2469 PM8001_IO_DBG(pm8001_ha, 2470 pm8001_printk("IO_NO_DEVICE\n")); 2471 ts->resp = SAS_TASK_UNDELIVERED; 2472 ts->stat = SAS_PHY_DOWN; 2473 break; 2474 case IO_XFER_ERROR_BREAK: 2475 PM8001_IO_DBG(pm8001_ha, 2476 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2477 ts->resp = SAS_TASK_COMPLETE; 2478 ts->stat = SAS_INTERRUPTED; 2479 break; 2480 case IO_XFER_ERROR_PHY_NOT_READY: 2481 PM8001_IO_DBG(pm8001_ha, 2482 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2483 ts->resp = SAS_TASK_COMPLETE; 2484 ts->stat = SAS_OPEN_REJECT; 2485 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2486 break; 2487 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2488 PM8001_IO_DBG(pm8001_ha, 2489 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT" 2490 "_SUPPORTED\n")); 2491 ts->resp = SAS_TASK_COMPLETE; 2492 ts->stat = SAS_OPEN_REJECT; 2493 ts->open_rej_reason = SAS_OREJ_EPROTO; 2494 break; 2495 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2496 PM8001_IO_DBG(pm8001_ha, 2497 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2498 ts->resp = SAS_TASK_COMPLETE; 2499 ts->stat = SAS_OPEN_REJECT; 2500 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2501 break; 2502 case IO_OPEN_CNX_ERROR_BREAK: 2503 PM8001_IO_DBG(pm8001_ha, 2504 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2505 ts->resp = SAS_TASK_COMPLETE; 2506 ts->stat = SAS_OPEN_REJECT; 2507 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2508 break; 2509 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2510 PM8001_IO_DBG(pm8001_ha, 2511 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2512 ts->resp = SAS_TASK_COMPLETE; 2513 ts->stat = SAS_DEV_NO_RESPONSE; 2514 if (!t->uldd_task) { 2515 pm8001_handle_event(pm8001_ha, 2516 pm8001_dev, 2517 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2518 ts->resp = SAS_TASK_UNDELIVERED; 2519 ts->stat = SAS_QUEUE_FULL; 2520 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2521 return; 2522 } 2523 break; 2524 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2525 PM8001_IO_DBG(pm8001_ha, 2526 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2527 ts->resp = SAS_TASK_UNDELIVERED; 2528 ts->stat = SAS_OPEN_REJECT; 2529 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2530 if (!t->uldd_task) { 2531 pm8001_handle_event(pm8001_ha, 2532 pm8001_dev, 2533 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2534 ts->resp = SAS_TASK_UNDELIVERED; 2535 ts->stat = SAS_QUEUE_FULL; 2536 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2537 return; 2538 } 2539 break; 2540 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2541 PM8001_IO_DBG(pm8001_ha, 2542 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 2543 "NOT_SUPPORTED\n")); 2544 ts->resp = SAS_TASK_COMPLETE; 2545 ts->stat = SAS_OPEN_REJECT; 2546 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2547 break; 2548 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 2549 PM8001_IO_DBG(pm8001_ha, 2550 pm8001_printk("IO_OPEN_CNX_ERROR_STP_RESOURCES" 2551 "_BUSY\n")); 2552 ts->resp = SAS_TASK_COMPLETE; 2553 ts->stat = SAS_DEV_NO_RESPONSE; 2554 if (!t->uldd_task) { 2555 pm8001_handle_event(pm8001_ha, 2556 pm8001_dev, 2557 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY); 2558 ts->resp = SAS_TASK_UNDELIVERED; 2559 ts->stat = SAS_QUEUE_FULL; 2560 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2561 return; 2562 } 2563 break; 2564 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2565 PM8001_IO_DBG(pm8001_ha, 2566 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2567 ts->resp = SAS_TASK_COMPLETE; 2568 ts->stat = SAS_OPEN_REJECT; 2569 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2570 break; 2571 case IO_XFER_ERROR_NAK_RECEIVED: 2572 PM8001_IO_DBG(pm8001_ha, 2573 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 2574 ts->resp = SAS_TASK_COMPLETE; 2575 ts->stat = SAS_NAK_R_ERR; 2576 break; 2577 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2578 PM8001_IO_DBG(pm8001_ha, 2579 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 2580 ts->resp = SAS_TASK_COMPLETE; 2581 ts->stat = SAS_NAK_R_ERR; 2582 break; 2583 case IO_XFER_ERROR_DMA: 2584 PM8001_IO_DBG(pm8001_ha, 2585 pm8001_printk("IO_XFER_ERROR_DMA\n")); 2586 ts->resp = SAS_TASK_COMPLETE; 2587 ts->stat = SAS_ABORTED_TASK; 2588 break; 2589 case IO_XFER_ERROR_SATA_LINK_TIMEOUT: 2590 PM8001_IO_DBG(pm8001_ha, 2591 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n")); 2592 ts->resp = SAS_TASK_UNDELIVERED; 2593 ts->stat = SAS_DEV_NO_RESPONSE; 2594 break; 2595 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2596 PM8001_IO_DBG(pm8001_ha, 2597 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n")); 2598 ts->resp = SAS_TASK_COMPLETE; 2599 ts->stat = SAS_DATA_UNDERRUN; 2600 break; 2601 case IO_XFER_OPEN_RETRY_TIMEOUT: 2602 PM8001_IO_DBG(pm8001_ha, 2603 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2604 ts->resp = SAS_TASK_COMPLETE; 2605 ts->stat = SAS_OPEN_TO; 2606 break; 2607 case IO_PORT_IN_RESET: 2608 PM8001_IO_DBG(pm8001_ha, 2609 pm8001_printk("IO_PORT_IN_RESET\n")); 2610 ts->resp = SAS_TASK_COMPLETE; 2611 ts->stat = SAS_DEV_NO_RESPONSE; 2612 break; 2613 case IO_DS_NON_OPERATIONAL: 2614 PM8001_IO_DBG(pm8001_ha, 2615 pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 2616 ts->resp = SAS_TASK_COMPLETE; 2617 ts->stat = SAS_DEV_NO_RESPONSE; 2618 if (!t->uldd_task) { 2619 pm8001_handle_event(pm8001_ha, pm8001_dev, 2620 IO_DS_NON_OPERATIONAL); 2621 ts->resp = SAS_TASK_UNDELIVERED; 2622 ts->stat = SAS_QUEUE_FULL; 2623 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2624 return; 2625 } 2626 break; 2627 case IO_DS_IN_RECOVERY: 2628 PM8001_IO_DBG(pm8001_ha, 2629 pm8001_printk(" IO_DS_IN_RECOVERY\n")); 2630 ts->resp = SAS_TASK_COMPLETE; 2631 ts->stat = SAS_DEV_NO_RESPONSE; 2632 break; 2633 case IO_DS_IN_ERROR: 2634 PM8001_IO_DBG(pm8001_ha, 2635 pm8001_printk("IO_DS_IN_ERROR\n")); 2636 ts->resp = SAS_TASK_COMPLETE; 2637 ts->stat = SAS_DEV_NO_RESPONSE; 2638 if (!t->uldd_task) { 2639 pm8001_handle_event(pm8001_ha, pm8001_dev, 2640 IO_DS_IN_ERROR); 2641 ts->resp = SAS_TASK_UNDELIVERED; 2642 ts->stat = SAS_QUEUE_FULL; 2643 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2644 return; 2645 } 2646 break; 2647 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2648 PM8001_IO_DBG(pm8001_ha, 2649 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 2650 ts->resp = SAS_TASK_COMPLETE; 2651 ts->stat = SAS_OPEN_REJECT; 2652 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2653 break; 2654 default: 2655 PM8001_IO_DBG(pm8001_ha, 2656 pm8001_printk("Unknown status 0x%x\n", status)); 2657 /* not allowed case. Therefore, return failed status */ 2658 ts->resp = SAS_TASK_COMPLETE; 2659 ts->stat = SAS_DEV_NO_RESPONSE; 2660 break; 2661 } 2662 spin_lock_irqsave(&t->task_state_lock, flags); 2663 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2664 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2665 t->task_state_flags |= SAS_TASK_STATE_DONE; 2666 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2667 spin_unlock_irqrestore(&t->task_state_lock, flags); 2668 PM8001_FAIL_DBG(pm8001_ha, 2669 pm8001_printk("task 0x%p done with io_status 0x%x" 2670 " resp 0x%x stat 0x%x but aborted by upper layer!\n", 2671 t, status, ts->resp, ts->stat)); 2672 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2673 } else { 2674 spin_unlock_irqrestore(&t->task_state_lock, flags); 2675 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2676 } 2677 } 2678 2679 /*See the comments for mpi_ssp_completion */ 2680 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 2681 { 2682 struct sas_task *t; 2683 struct task_status_struct *ts; 2684 struct pm8001_ccb_info *ccb; 2685 struct pm8001_device *pm8001_dev; 2686 struct sata_event_resp *psataPayload = 2687 (struct sata_event_resp *)(piomb + 4); 2688 u32 event = le32_to_cpu(psataPayload->event); 2689 u32 tag = le32_to_cpu(psataPayload->tag); 2690 u32 port_id = le32_to_cpu(psataPayload->port_id); 2691 u32 dev_id = le32_to_cpu(psataPayload->device_id); 2692 unsigned long flags; 2693 2694 ccb = &pm8001_ha->ccb_info[tag]; 2695 2696 if (ccb) { 2697 t = ccb->task; 2698 pm8001_dev = ccb->device; 2699 } else { 2700 PM8001_FAIL_DBG(pm8001_ha, 2701 pm8001_printk("No CCB !!!. returning\n")); 2702 } 2703 if (event) 2704 PM8001_FAIL_DBG(pm8001_ha, 2705 pm8001_printk("SATA EVENT 0x%x\n", event)); 2706 2707 /* Check if this is NCQ error */ 2708 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) { 2709 /* find device using device id */ 2710 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id); 2711 /* send read log extension */ 2712 if (pm8001_dev) 2713 pm8001_send_read_log(pm8001_ha, pm8001_dev); 2714 return; 2715 } 2716 2717 ccb = &pm8001_ha->ccb_info[tag]; 2718 t = ccb->task; 2719 pm8001_dev = ccb->device; 2720 if (event) 2721 PM8001_FAIL_DBG(pm8001_ha, 2722 pm8001_printk("sata IO status 0x%x\n", event)); 2723 if (unlikely(!t || !t->lldd_task || !t->dev)) 2724 return; 2725 ts = &t->task_status; 2726 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 2727 "port_id:0x%x, device_id:0x%x, tag:0x%x, event:0x%x\n", 2728 port_id, dev_id, tag, event)); 2729 switch (event) { 2730 case IO_OVERFLOW: 2731 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n")); 2732 ts->resp = SAS_TASK_COMPLETE; 2733 ts->stat = SAS_DATA_OVERRUN; 2734 ts->residual = 0; 2735 if (pm8001_dev) 2736 pm8001_dev->running_req--; 2737 break; 2738 case IO_XFER_ERROR_BREAK: 2739 PM8001_IO_DBG(pm8001_ha, 2740 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2741 ts->resp = SAS_TASK_COMPLETE; 2742 ts->stat = SAS_INTERRUPTED; 2743 break; 2744 case IO_XFER_ERROR_PHY_NOT_READY: 2745 PM8001_IO_DBG(pm8001_ha, 2746 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2747 ts->resp = SAS_TASK_COMPLETE; 2748 ts->stat = SAS_OPEN_REJECT; 2749 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2750 break; 2751 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2752 PM8001_IO_DBG(pm8001_ha, 2753 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT" 2754 "_SUPPORTED\n")); 2755 ts->resp = SAS_TASK_COMPLETE; 2756 ts->stat = SAS_OPEN_REJECT; 2757 ts->open_rej_reason = SAS_OREJ_EPROTO; 2758 break; 2759 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2760 PM8001_IO_DBG(pm8001_ha, 2761 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2762 ts->resp = SAS_TASK_COMPLETE; 2763 ts->stat = SAS_OPEN_REJECT; 2764 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2765 break; 2766 case IO_OPEN_CNX_ERROR_BREAK: 2767 PM8001_IO_DBG(pm8001_ha, 2768 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2769 ts->resp = SAS_TASK_COMPLETE; 2770 ts->stat = SAS_OPEN_REJECT; 2771 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2772 break; 2773 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2774 PM8001_IO_DBG(pm8001_ha, 2775 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2776 ts->resp = SAS_TASK_UNDELIVERED; 2777 ts->stat = SAS_DEV_NO_RESPONSE; 2778 if (!t->uldd_task) { 2779 pm8001_handle_event(pm8001_ha, 2780 pm8001_dev, 2781 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2782 ts->resp = SAS_TASK_COMPLETE; 2783 ts->stat = SAS_QUEUE_FULL; 2784 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2785 return; 2786 } 2787 break; 2788 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2789 PM8001_IO_DBG(pm8001_ha, 2790 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2791 ts->resp = SAS_TASK_UNDELIVERED; 2792 ts->stat = SAS_OPEN_REJECT; 2793 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2794 break; 2795 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2796 PM8001_IO_DBG(pm8001_ha, 2797 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 2798 "NOT_SUPPORTED\n")); 2799 ts->resp = SAS_TASK_COMPLETE; 2800 ts->stat = SAS_OPEN_REJECT; 2801 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2802 break; 2803 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2804 PM8001_IO_DBG(pm8001_ha, 2805 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2806 ts->resp = SAS_TASK_COMPLETE; 2807 ts->stat = SAS_OPEN_REJECT; 2808 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2809 break; 2810 case IO_XFER_ERROR_NAK_RECEIVED: 2811 PM8001_IO_DBG(pm8001_ha, 2812 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 2813 ts->resp = SAS_TASK_COMPLETE; 2814 ts->stat = SAS_NAK_R_ERR; 2815 break; 2816 case IO_XFER_ERROR_PEER_ABORTED: 2817 PM8001_IO_DBG(pm8001_ha, 2818 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n")); 2819 ts->resp = SAS_TASK_COMPLETE; 2820 ts->stat = SAS_NAK_R_ERR; 2821 break; 2822 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2823 PM8001_IO_DBG(pm8001_ha, 2824 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n")); 2825 ts->resp = SAS_TASK_COMPLETE; 2826 ts->stat = SAS_DATA_UNDERRUN; 2827 break; 2828 case IO_XFER_OPEN_RETRY_TIMEOUT: 2829 PM8001_IO_DBG(pm8001_ha, 2830 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2831 ts->resp = SAS_TASK_COMPLETE; 2832 ts->stat = SAS_OPEN_TO; 2833 break; 2834 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2835 PM8001_IO_DBG(pm8001_ha, 2836 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n")); 2837 ts->resp = SAS_TASK_COMPLETE; 2838 ts->stat = SAS_OPEN_TO; 2839 break; 2840 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2841 PM8001_IO_DBG(pm8001_ha, 2842 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n")); 2843 ts->resp = SAS_TASK_COMPLETE; 2844 ts->stat = SAS_OPEN_TO; 2845 break; 2846 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2847 PM8001_IO_DBG(pm8001_ha, 2848 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n")); 2849 ts->resp = SAS_TASK_COMPLETE; 2850 ts->stat = SAS_OPEN_TO; 2851 break; 2852 case IO_XFER_ERROR_OFFSET_MISMATCH: 2853 PM8001_IO_DBG(pm8001_ha, 2854 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 2855 ts->resp = SAS_TASK_COMPLETE; 2856 ts->stat = SAS_OPEN_TO; 2857 break; 2858 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2859 PM8001_IO_DBG(pm8001_ha, 2860 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n")); 2861 ts->resp = SAS_TASK_COMPLETE; 2862 ts->stat = SAS_OPEN_TO; 2863 break; 2864 case IO_XFER_CMD_FRAME_ISSUED: 2865 PM8001_IO_DBG(pm8001_ha, 2866 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n")); 2867 break; 2868 case IO_XFER_PIO_SETUP_ERROR: 2869 PM8001_IO_DBG(pm8001_ha, 2870 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n")); 2871 ts->resp = SAS_TASK_COMPLETE; 2872 ts->stat = SAS_OPEN_TO; 2873 break; 2874 default: 2875 PM8001_IO_DBG(pm8001_ha, 2876 pm8001_printk("Unknown status 0x%x\n", event)); 2877 /* not allowed case. Therefore, return failed status */ 2878 ts->resp = SAS_TASK_COMPLETE; 2879 ts->stat = SAS_OPEN_TO; 2880 break; 2881 } 2882 spin_lock_irqsave(&t->task_state_lock, flags); 2883 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2884 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2885 t->task_state_flags |= SAS_TASK_STATE_DONE; 2886 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2887 spin_unlock_irqrestore(&t->task_state_lock, flags); 2888 PM8001_FAIL_DBG(pm8001_ha, 2889 pm8001_printk("task 0x%p done with io_status 0x%x" 2890 " resp 0x%x stat 0x%x but aborted by upper layer!\n", 2891 t, event, ts->resp, ts->stat)); 2892 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2893 } else { 2894 spin_unlock_irqrestore(&t->task_state_lock, flags); 2895 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2896 } 2897 } 2898 2899 /*See the comments for mpi_ssp_completion */ 2900 static void 2901 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2902 { 2903 struct sas_task *t; 2904 struct pm8001_ccb_info *ccb; 2905 unsigned long flags; 2906 u32 status; 2907 u32 tag; 2908 struct smp_completion_resp *psmpPayload; 2909 struct task_status_struct *ts; 2910 struct pm8001_device *pm8001_dev; 2911 2912 psmpPayload = (struct smp_completion_resp *)(piomb + 4); 2913 status = le32_to_cpu(psmpPayload->status); 2914 tag = le32_to_cpu(psmpPayload->tag); 2915 2916 ccb = &pm8001_ha->ccb_info[tag]; 2917 t = ccb->task; 2918 ts = &t->task_status; 2919 pm8001_dev = ccb->device; 2920 if (status) 2921 PM8001_FAIL_DBG(pm8001_ha, 2922 pm8001_printk("smp IO status 0x%x\n", status)); 2923 if (unlikely(!t || !t->lldd_task || !t->dev)) 2924 return; 2925 2926 switch (status) { 2927 case IO_SUCCESS: 2928 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); 2929 ts->resp = SAS_TASK_COMPLETE; 2930 ts->stat = SAM_STAT_GOOD; 2931 if (pm8001_dev) 2932 pm8001_dev->running_req--; 2933 break; 2934 case IO_ABORTED: 2935 PM8001_IO_DBG(pm8001_ha, 2936 pm8001_printk("IO_ABORTED IOMB\n")); 2937 ts->resp = SAS_TASK_COMPLETE; 2938 ts->stat = SAS_ABORTED_TASK; 2939 if (pm8001_dev) 2940 pm8001_dev->running_req--; 2941 break; 2942 case IO_OVERFLOW: 2943 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n")); 2944 ts->resp = SAS_TASK_COMPLETE; 2945 ts->stat = SAS_DATA_OVERRUN; 2946 ts->residual = 0; 2947 if (pm8001_dev) 2948 pm8001_dev->running_req--; 2949 break; 2950 case IO_NO_DEVICE: 2951 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n")); 2952 ts->resp = SAS_TASK_COMPLETE; 2953 ts->stat = SAS_PHY_DOWN; 2954 break; 2955 case IO_ERROR_HW_TIMEOUT: 2956 PM8001_IO_DBG(pm8001_ha, 2957 pm8001_printk("IO_ERROR_HW_TIMEOUT\n")); 2958 ts->resp = SAS_TASK_COMPLETE; 2959 ts->stat = SAM_STAT_BUSY; 2960 break; 2961 case IO_XFER_ERROR_BREAK: 2962 PM8001_IO_DBG(pm8001_ha, 2963 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2964 ts->resp = SAS_TASK_COMPLETE; 2965 ts->stat = SAM_STAT_BUSY; 2966 break; 2967 case IO_XFER_ERROR_PHY_NOT_READY: 2968 PM8001_IO_DBG(pm8001_ha, 2969 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2970 ts->resp = SAS_TASK_COMPLETE; 2971 ts->stat = SAM_STAT_BUSY; 2972 break; 2973 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2974 PM8001_IO_DBG(pm8001_ha, 2975 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 2976 ts->resp = SAS_TASK_COMPLETE; 2977 ts->stat = SAS_OPEN_REJECT; 2978 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2979 break; 2980 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2981 PM8001_IO_DBG(pm8001_ha, 2982 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2983 ts->resp = SAS_TASK_COMPLETE; 2984 ts->stat = SAS_OPEN_REJECT; 2985 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2986 break; 2987 case IO_OPEN_CNX_ERROR_BREAK: 2988 PM8001_IO_DBG(pm8001_ha, 2989 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2990 ts->resp = SAS_TASK_COMPLETE; 2991 ts->stat = SAS_OPEN_REJECT; 2992 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2993 break; 2994 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2995 PM8001_IO_DBG(pm8001_ha, 2996 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2997 ts->resp = SAS_TASK_COMPLETE; 2998 ts->stat = SAS_OPEN_REJECT; 2999 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 3000 pm8001_handle_event(pm8001_ha, 3001 pm8001_dev, 3002 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 3003 break; 3004 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 3005 PM8001_IO_DBG(pm8001_ha, 3006 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 3007 ts->resp = SAS_TASK_COMPLETE; 3008 ts->stat = SAS_OPEN_REJECT; 3009 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 3010 break; 3011 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 3012 PM8001_IO_DBG(pm8001_ha, 3013 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 3014 "NOT_SUPPORTED\n")); 3015 ts->resp = SAS_TASK_COMPLETE; 3016 ts->stat = SAS_OPEN_REJECT; 3017 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 3018 break; 3019 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 3020 PM8001_IO_DBG(pm8001_ha, 3021 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 3022 ts->resp = SAS_TASK_COMPLETE; 3023 ts->stat = SAS_OPEN_REJECT; 3024 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 3025 break; 3026 case IO_XFER_ERROR_RX_FRAME: 3027 PM8001_IO_DBG(pm8001_ha, 3028 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n")); 3029 ts->resp = SAS_TASK_COMPLETE; 3030 ts->stat = SAS_DEV_NO_RESPONSE; 3031 break; 3032 case IO_XFER_OPEN_RETRY_TIMEOUT: 3033 PM8001_IO_DBG(pm8001_ha, 3034 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 3035 ts->resp = SAS_TASK_COMPLETE; 3036 ts->stat = SAS_OPEN_REJECT; 3037 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3038 break; 3039 case IO_ERROR_INTERNAL_SMP_RESOURCE: 3040 PM8001_IO_DBG(pm8001_ha, 3041 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n")); 3042 ts->resp = SAS_TASK_COMPLETE; 3043 ts->stat = SAS_QUEUE_FULL; 3044 break; 3045 case IO_PORT_IN_RESET: 3046 PM8001_IO_DBG(pm8001_ha, 3047 pm8001_printk("IO_PORT_IN_RESET\n")); 3048 ts->resp = SAS_TASK_COMPLETE; 3049 ts->stat = SAS_OPEN_REJECT; 3050 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3051 break; 3052 case IO_DS_NON_OPERATIONAL: 3053 PM8001_IO_DBG(pm8001_ha, 3054 pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 3055 ts->resp = SAS_TASK_COMPLETE; 3056 ts->stat = SAS_DEV_NO_RESPONSE; 3057 break; 3058 case IO_DS_IN_RECOVERY: 3059 PM8001_IO_DBG(pm8001_ha, 3060 pm8001_printk("IO_DS_IN_RECOVERY\n")); 3061 ts->resp = SAS_TASK_COMPLETE; 3062 ts->stat = SAS_OPEN_REJECT; 3063 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3064 break; 3065 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 3066 PM8001_IO_DBG(pm8001_ha, 3067 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 3068 ts->resp = SAS_TASK_COMPLETE; 3069 ts->stat = SAS_OPEN_REJECT; 3070 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3071 break; 3072 default: 3073 PM8001_IO_DBG(pm8001_ha, 3074 pm8001_printk("Unknown status 0x%x\n", status)); 3075 ts->resp = SAS_TASK_COMPLETE; 3076 ts->stat = SAS_DEV_NO_RESPONSE; 3077 /* not allowed case. Therefore, return failed status */ 3078 break; 3079 } 3080 spin_lock_irqsave(&t->task_state_lock, flags); 3081 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 3082 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 3083 t->task_state_flags |= SAS_TASK_STATE_DONE; 3084 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 3085 spin_unlock_irqrestore(&t->task_state_lock, flags); 3086 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with" 3087 " io_status 0x%x resp 0x%x " 3088 "stat 0x%x but aborted by upper layer!\n", 3089 t, status, ts->resp, ts->stat)); 3090 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 3091 } else { 3092 spin_unlock_irqrestore(&t->task_state_lock, flags); 3093 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 3094 mb();/* in order to force CPU ordering */ 3095 t->task_done(t); 3096 } 3097 } 3098 3099 void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha, 3100 void *piomb) 3101 { 3102 struct set_dev_state_resp *pPayload = 3103 (struct set_dev_state_resp *)(piomb + 4); 3104 u32 tag = le32_to_cpu(pPayload->tag); 3105 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 3106 struct pm8001_device *pm8001_dev = ccb->device; 3107 u32 status = le32_to_cpu(pPayload->status); 3108 u32 device_id = le32_to_cpu(pPayload->device_id); 3109 u8 pds = le32_to_cpu(pPayload->pds_nds) & PDS_BITS; 3110 u8 nds = le32_to_cpu(pPayload->pds_nds) & NDS_BITS; 3111 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set device id = 0x%x state " 3112 "from 0x%x to 0x%x status = 0x%x!\n", 3113 device_id, pds, nds, status)); 3114 complete(pm8001_dev->setds_completion); 3115 ccb->task = NULL; 3116 ccb->ccb_tag = 0xFFFFFFFF; 3117 pm8001_tag_free(pm8001_ha, tag); 3118 } 3119 3120 void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3121 { 3122 struct get_nvm_data_resp *pPayload = 3123 (struct get_nvm_data_resp *)(piomb + 4); 3124 u32 tag = le32_to_cpu(pPayload->tag); 3125 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 3126 u32 dlen_status = le32_to_cpu(pPayload->dlen_status); 3127 complete(pm8001_ha->nvmd_completion); 3128 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set nvm data complete!\n")); 3129 if ((dlen_status & NVMD_STAT) != 0) { 3130 PM8001_FAIL_DBG(pm8001_ha, 3131 pm8001_printk("Set nvm data error!\n")); 3132 return; 3133 } 3134 ccb->task = NULL; 3135 ccb->ccb_tag = 0xFFFFFFFF; 3136 pm8001_tag_free(pm8001_ha, tag); 3137 } 3138 3139 void 3140 pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3141 { 3142 struct fw_control_ex *fw_control_context; 3143 struct get_nvm_data_resp *pPayload = 3144 (struct get_nvm_data_resp *)(piomb + 4); 3145 u32 tag = le32_to_cpu(pPayload->tag); 3146 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 3147 u32 dlen_status = le32_to_cpu(pPayload->dlen_status); 3148 u32 ir_tds_bn_dps_das_nvm = 3149 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm); 3150 void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr; 3151 fw_control_context = ccb->fw_control_context; 3152 3153 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Get nvm data complete!\n")); 3154 if ((dlen_status & NVMD_STAT) != 0) { 3155 PM8001_FAIL_DBG(pm8001_ha, 3156 pm8001_printk("Get nvm data error!\n")); 3157 complete(pm8001_ha->nvmd_completion); 3158 return; 3159 } 3160 3161 if (ir_tds_bn_dps_das_nvm & IPMode) { 3162 /* indirect mode - IR bit set */ 3163 PM8001_MSG_DBG(pm8001_ha, 3164 pm8001_printk("Get NVMD success, IR=1\n")); 3165 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) { 3166 if (ir_tds_bn_dps_das_nvm == 0x80a80200) { 3167 memcpy(pm8001_ha->sas_addr, 3168 ((u8 *)virt_addr + 4), 3169 SAS_ADDR_SIZE); 3170 PM8001_MSG_DBG(pm8001_ha, 3171 pm8001_printk("Get SAS address" 3172 " from VPD successfully!\n")); 3173 } 3174 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM) 3175 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) || 3176 ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) { 3177 ; 3178 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP) 3179 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) { 3180 ; 3181 } else { 3182 /* Should not be happened*/ 3183 PM8001_MSG_DBG(pm8001_ha, 3184 pm8001_printk("(IR=1)Wrong Device type 0x%x\n", 3185 ir_tds_bn_dps_das_nvm)); 3186 } 3187 } else /* direct mode */{ 3188 PM8001_MSG_DBG(pm8001_ha, 3189 pm8001_printk("Get NVMD success, IR=0, dataLen=%d\n", 3190 (dlen_status & NVMD_LEN) >> 24)); 3191 } 3192 /* Though fw_control_context is freed below, usrAddr still needs 3193 * to be updated as this holds the response to the request function 3194 */ 3195 memcpy(fw_control_context->usrAddr, 3196 pm8001_ha->memoryMap.region[NVMD].virt_ptr, 3197 fw_control_context->len); 3198 kfree(ccb->fw_control_context); 3199 ccb->task = NULL; 3200 ccb->ccb_tag = 0xFFFFFFFF; 3201 pm8001_tag_free(pm8001_ha, tag); 3202 complete(pm8001_ha->nvmd_completion); 3203 } 3204 3205 int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb) 3206 { 3207 u32 tag; 3208 struct local_phy_ctl_resp *pPayload = 3209 (struct local_phy_ctl_resp *)(piomb + 4); 3210 u32 status = le32_to_cpu(pPayload->status); 3211 u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS; 3212 u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS; 3213 tag = le32_to_cpu(pPayload->tag); 3214 if (status != 0) { 3215 PM8001_MSG_DBG(pm8001_ha, 3216 pm8001_printk("%x phy execute %x phy op failed!\n", 3217 phy_id, phy_op)); 3218 } else { 3219 PM8001_MSG_DBG(pm8001_ha, 3220 pm8001_printk("%x phy execute %x phy op success!\n", 3221 phy_id, phy_op)); 3222 pm8001_ha->phy[phy_id].reset_success = true; 3223 } 3224 if (pm8001_ha->phy[phy_id].enable_completion) { 3225 complete(pm8001_ha->phy[phy_id].enable_completion); 3226 pm8001_ha->phy[phy_id].enable_completion = NULL; 3227 } 3228 pm8001_tag_free(pm8001_ha, tag); 3229 return 0; 3230 } 3231 3232 /** 3233 * pm8001_bytes_dmaed - one of the interface function communication with libsas 3234 * @pm8001_ha: our hba card information 3235 * @i: which phy that received the event. 3236 * 3237 * when HBA driver received the identify done event or initiate FIS received 3238 * event(for SATA), it will invoke this function to notify the sas layer that 3239 * the sas toplogy has formed, please discover the the whole sas domain, 3240 * while receive a broadcast(change) primitive just tell the sas 3241 * layer to discover the changed domain rather than the whole domain. 3242 */ 3243 void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i) 3244 { 3245 struct pm8001_phy *phy = &pm8001_ha->phy[i]; 3246 struct asd_sas_phy *sas_phy = &phy->sas_phy; 3247 if (!phy->phy_attached) 3248 return; 3249 3250 if (sas_phy->phy) { 3251 struct sas_phy *sphy = sas_phy->phy; 3252 sphy->negotiated_linkrate = sas_phy->linkrate; 3253 sphy->minimum_linkrate = phy->minimum_linkrate; 3254 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS; 3255 sphy->maximum_linkrate = phy->maximum_linkrate; 3256 sphy->maximum_linkrate_hw = phy->maximum_linkrate; 3257 } 3258 3259 if (phy->phy_type & PORT_TYPE_SAS) { 3260 struct sas_identify_frame *id; 3261 id = (struct sas_identify_frame *)phy->frame_rcvd; 3262 id->dev_type = phy->identify.device_type; 3263 id->initiator_bits = SAS_PROTOCOL_ALL; 3264 id->target_bits = phy->identify.target_port_protocols; 3265 } else if (phy->phy_type & PORT_TYPE_SATA) { 3266 /*Nothing*/ 3267 } 3268 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("phy %d byte dmaded.\n", i)); 3269 3270 sas_phy->frame_rcvd_size = phy->frame_rcvd_size; 3271 pm8001_ha->sas->notify_port_event(sas_phy, PORTE_BYTES_DMAED); 3272 } 3273 3274 /* Get the link rate speed */ 3275 void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate) 3276 { 3277 struct sas_phy *sas_phy = phy->sas_phy.phy; 3278 3279 switch (link_rate) { 3280 case PHY_SPEED_120: 3281 phy->sas_phy.linkrate = SAS_LINK_RATE_12_0_GBPS; 3282 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_12_0_GBPS; 3283 break; 3284 case PHY_SPEED_60: 3285 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS; 3286 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS; 3287 break; 3288 case PHY_SPEED_30: 3289 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS; 3290 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS; 3291 break; 3292 case PHY_SPEED_15: 3293 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS; 3294 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS; 3295 break; 3296 } 3297 sas_phy->negotiated_linkrate = phy->sas_phy.linkrate; 3298 sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS; 3299 sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS; 3300 sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS; 3301 sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS; 3302 } 3303 3304 /** 3305 * asd_get_attached_sas_addr -- extract/generate attached SAS address 3306 * @phy: pointer to asd_phy 3307 * @sas_addr: pointer to buffer where the SAS address is to be written 3308 * 3309 * This function extracts the SAS address from an IDENTIFY frame 3310 * received. If OOB is SATA, then a SAS address is generated from the 3311 * HA tables. 3312 * 3313 * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame 3314 * buffer. 3315 */ 3316 void pm8001_get_attached_sas_addr(struct pm8001_phy *phy, 3317 u8 *sas_addr) 3318 { 3319 if (phy->sas_phy.frame_rcvd[0] == 0x34 3320 && phy->sas_phy.oob_mode == SATA_OOB_MODE) { 3321 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha; 3322 /* FIS device-to-host */ 3323 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr); 3324 addr += phy->sas_phy.id; 3325 *(__be64 *)sas_addr = cpu_to_be64(addr); 3326 } else { 3327 struct sas_identify_frame *idframe = 3328 (void *) phy->sas_phy.frame_rcvd; 3329 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE); 3330 } 3331 } 3332 3333 /** 3334 * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW. 3335 * @pm8001_ha: our hba card information 3336 * @Qnum: the outbound queue message number. 3337 * @SEA: source of event to ack 3338 * @port_id: port id. 3339 * @phyId: phy id. 3340 * @param0: parameter 0. 3341 * @param1: parameter 1. 3342 */ 3343 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha, 3344 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1) 3345 { 3346 struct hw_event_ack_req payload; 3347 u32 opc = OPC_INB_SAS_HW_EVENT_ACK; 3348 3349 struct inbound_queue_table *circularQ; 3350 3351 memset((u8 *)&payload, 0, sizeof(payload)); 3352 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum]; 3353 payload.tag = cpu_to_le32(1); 3354 payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) | 3355 ((phyId & 0x0F) << 4) | (port_id & 0x0F)); 3356 payload.param0 = cpu_to_le32(param0); 3357 payload.param1 = cpu_to_le32(param1); 3358 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 3359 } 3360 3361 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 3362 u32 phyId, u32 phy_op); 3363 3364 /** 3365 * hw_event_sas_phy_up -FW tells me a SAS phy up event. 3366 * @pm8001_ha: our hba card information 3367 * @piomb: IO message buffer 3368 */ 3369 static void 3370 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3371 { 3372 struct hw_event_resp *pPayload = 3373 (struct hw_event_resp *)(piomb + 4); 3374 u32 lr_evt_status_phyid_portid = 3375 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3376 u8 link_rate = 3377 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28); 3378 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3379 u8 phy_id = 3380 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3381 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate); 3382 u8 portstate = (u8)(npip_portstate & 0x0000000F); 3383 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3384 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3385 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3386 unsigned long flags; 3387 u8 deviceType = pPayload->sas_identify.dev_type; 3388 port->port_state = portstate; 3389 phy->phy_state = PHY_STATE_LINK_UP_SPC; 3390 PM8001_MSG_DBG(pm8001_ha, 3391 pm8001_printk("HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n", 3392 port_id, phy_id)); 3393 3394 switch (deviceType) { 3395 case SAS_PHY_UNUSED: 3396 PM8001_MSG_DBG(pm8001_ha, 3397 pm8001_printk("device type no device.\n")); 3398 break; 3399 case SAS_END_DEVICE: 3400 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n")); 3401 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id, 3402 PHY_NOTIFY_ENABLE_SPINUP); 3403 port->port_attached = 1; 3404 pm8001_get_lrate_mode(phy, link_rate); 3405 break; 3406 case SAS_EDGE_EXPANDER_DEVICE: 3407 PM8001_MSG_DBG(pm8001_ha, 3408 pm8001_printk("expander device.\n")); 3409 port->port_attached = 1; 3410 pm8001_get_lrate_mode(phy, link_rate); 3411 break; 3412 case SAS_FANOUT_EXPANDER_DEVICE: 3413 PM8001_MSG_DBG(pm8001_ha, 3414 pm8001_printk("fanout expander device.\n")); 3415 port->port_attached = 1; 3416 pm8001_get_lrate_mode(phy, link_rate); 3417 break; 3418 default: 3419 PM8001_MSG_DBG(pm8001_ha, 3420 pm8001_printk("unknown device type(%x)\n", deviceType)); 3421 break; 3422 } 3423 phy->phy_type |= PORT_TYPE_SAS; 3424 phy->identify.device_type = deviceType; 3425 phy->phy_attached = 1; 3426 if (phy->identify.device_type == SAS_END_DEVICE) 3427 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP; 3428 else if (phy->identify.device_type != SAS_PHY_UNUSED) 3429 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP; 3430 phy->sas_phy.oob_mode = SAS_OOB_MODE; 3431 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE); 3432 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3433 memcpy(phy->frame_rcvd, &pPayload->sas_identify, 3434 sizeof(struct sas_identify_frame)-4); 3435 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4; 3436 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3437 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3438 if (pm8001_ha->flags == PM8001F_RUN_TIME) 3439 mdelay(200);/*delay a moment to wait disk to spinup*/ 3440 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3441 } 3442 3443 /** 3444 * hw_event_sata_phy_up -FW tells me a SATA phy up event. 3445 * @pm8001_ha: our hba card information 3446 * @piomb: IO message buffer 3447 */ 3448 static void 3449 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3450 { 3451 struct hw_event_resp *pPayload = 3452 (struct hw_event_resp *)(piomb + 4); 3453 u32 lr_evt_status_phyid_portid = 3454 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3455 u8 link_rate = 3456 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28); 3457 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3458 u8 phy_id = 3459 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3460 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate); 3461 u8 portstate = (u8)(npip_portstate & 0x0000000F); 3462 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3463 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3464 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3465 unsigned long flags; 3466 PM8001_MSG_DBG(pm8001_ha, 3467 pm8001_printk("HW_EVENT_SATA_PHY_UP port id = %d," 3468 " phy id = %d\n", port_id, phy_id)); 3469 port->port_state = portstate; 3470 phy->phy_state = PHY_STATE_LINK_UP_SPC; 3471 port->port_attached = 1; 3472 pm8001_get_lrate_mode(phy, link_rate); 3473 phy->phy_type |= PORT_TYPE_SATA; 3474 phy->phy_attached = 1; 3475 phy->sas_phy.oob_mode = SATA_OOB_MODE; 3476 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE); 3477 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3478 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4), 3479 sizeof(struct dev_to_host_fis)); 3480 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 3481 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 3482 phy->identify.device_type = SAS_SATA_DEV; 3483 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3484 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3485 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3486 } 3487 3488 /** 3489 * hw_event_phy_down -we should notify the libsas the phy is down. 3490 * @pm8001_ha: our hba card information 3491 * @piomb: IO message buffer 3492 */ 3493 static void 3494 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb) 3495 { 3496 struct hw_event_resp *pPayload = 3497 (struct hw_event_resp *)(piomb + 4); 3498 u32 lr_evt_status_phyid_portid = 3499 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3500 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3501 u8 phy_id = 3502 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3503 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate); 3504 u8 portstate = (u8)(npip_portstate & 0x0000000F); 3505 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3506 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3507 port->port_state = portstate; 3508 phy->phy_type = 0; 3509 phy->identify.device_type = 0; 3510 phy->phy_attached = 0; 3511 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE); 3512 switch (portstate) { 3513 case PORT_VALID: 3514 break; 3515 case PORT_INVALID: 3516 PM8001_MSG_DBG(pm8001_ha, 3517 pm8001_printk(" PortInvalid portID %d\n", port_id)); 3518 PM8001_MSG_DBG(pm8001_ha, 3519 pm8001_printk(" Last phy Down and port invalid\n")); 3520 port->port_attached = 0; 3521 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3522 port_id, phy_id, 0, 0); 3523 break; 3524 case PORT_IN_RESET: 3525 PM8001_MSG_DBG(pm8001_ha, 3526 pm8001_printk(" Port In Reset portID %d\n", port_id)); 3527 break; 3528 case PORT_NOT_ESTABLISHED: 3529 PM8001_MSG_DBG(pm8001_ha, 3530 pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n")); 3531 port->port_attached = 0; 3532 break; 3533 case PORT_LOSTCOMM: 3534 PM8001_MSG_DBG(pm8001_ha, 3535 pm8001_printk(" phy Down and PORT_LOSTCOMM\n")); 3536 PM8001_MSG_DBG(pm8001_ha, 3537 pm8001_printk(" Last phy Down and port invalid\n")); 3538 port->port_attached = 0; 3539 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3540 port_id, phy_id, 0, 0); 3541 break; 3542 default: 3543 port->port_attached = 0; 3544 PM8001_MSG_DBG(pm8001_ha, 3545 pm8001_printk(" phy Down and(default) = %x\n", 3546 portstate)); 3547 break; 3548 3549 } 3550 } 3551 3552 /** 3553 * pm8001_mpi_reg_resp -process register device ID response. 3554 * @pm8001_ha: our hba card information 3555 * @piomb: IO message buffer 3556 * 3557 * when sas layer find a device it will notify LLDD, then the driver register 3558 * the domain device to FW, this event is the return device ID which the FW 3559 * has assigned, from now,inter-communication with FW is no longer using the 3560 * SAS address, use device ID which FW assigned. 3561 */ 3562 int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3563 { 3564 u32 status; 3565 u32 device_id; 3566 u32 htag; 3567 struct pm8001_ccb_info *ccb; 3568 struct pm8001_device *pm8001_dev; 3569 struct dev_reg_resp *registerRespPayload = 3570 (struct dev_reg_resp *)(piomb + 4); 3571 3572 htag = le32_to_cpu(registerRespPayload->tag); 3573 ccb = &pm8001_ha->ccb_info[htag]; 3574 pm8001_dev = ccb->device; 3575 status = le32_to_cpu(registerRespPayload->status); 3576 device_id = le32_to_cpu(registerRespPayload->device_id); 3577 PM8001_MSG_DBG(pm8001_ha, 3578 pm8001_printk(" register device is status = %d\n", status)); 3579 switch (status) { 3580 case DEVREG_SUCCESS: 3581 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("DEVREG_SUCCESS\n")); 3582 pm8001_dev->device_id = device_id; 3583 break; 3584 case DEVREG_FAILURE_OUT_OF_RESOURCE: 3585 PM8001_MSG_DBG(pm8001_ha, 3586 pm8001_printk("DEVREG_FAILURE_OUT_OF_RESOURCE\n")); 3587 break; 3588 case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED: 3589 PM8001_MSG_DBG(pm8001_ha, 3590 pm8001_printk("DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n")); 3591 break; 3592 case DEVREG_FAILURE_INVALID_PHY_ID: 3593 PM8001_MSG_DBG(pm8001_ha, 3594 pm8001_printk("DEVREG_FAILURE_INVALID_PHY_ID\n")); 3595 break; 3596 case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED: 3597 PM8001_MSG_DBG(pm8001_ha, 3598 pm8001_printk("DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n")); 3599 break; 3600 case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE: 3601 PM8001_MSG_DBG(pm8001_ha, 3602 pm8001_printk("DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n")); 3603 break; 3604 case DEVREG_FAILURE_PORT_NOT_VALID_STATE: 3605 PM8001_MSG_DBG(pm8001_ha, 3606 pm8001_printk("DEVREG_FAILURE_PORT_NOT_VALID_STATE\n")); 3607 break; 3608 case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID: 3609 PM8001_MSG_DBG(pm8001_ha, 3610 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n")); 3611 break; 3612 default: 3613 PM8001_MSG_DBG(pm8001_ha, 3614 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_SUPPORTED\n")); 3615 break; 3616 } 3617 complete(pm8001_dev->dcompletion); 3618 ccb->task = NULL; 3619 ccb->ccb_tag = 0xFFFFFFFF; 3620 pm8001_tag_free(pm8001_ha, htag); 3621 return 0; 3622 } 3623 3624 int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3625 { 3626 u32 status; 3627 u32 device_id; 3628 struct dev_reg_resp *registerRespPayload = 3629 (struct dev_reg_resp *)(piomb + 4); 3630 3631 status = le32_to_cpu(registerRespPayload->status); 3632 device_id = le32_to_cpu(registerRespPayload->device_id); 3633 if (status != 0) 3634 PM8001_MSG_DBG(pm8001_ha, 3635 pm8001_printk(" deregister device failed ,status = %x" 3636 ", device_id = %x\n", status, device_id)); 3637 return 0; 3638 } 3639 3640 /** 3641 * fw_flash_update_resp - Response from FW for flash update command. 3642 * @pm8001_ha: our hba card information 3643 * @piomb: IO message buffer 3644 */ 3645 int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha, 3646 void *piomb) 3647 { 3648 u32 status; 3649 struct fw_flash_Update_resp *ppayload = 3650 (struct fw_flash_Update_resp *)(piomb + 4); 3651 u32 tag = le32_to_cpu(ppayload->tag); 3652 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 3653 status = le32_to_cpu(ppayload->status); 3654 switch (status) { 3655 case FLASH_UPDATE_COMPLETE_PENDING_REBOOT: 3656 PM8001_MSG_DBG(pm8001_ha, 3657 pm8001_printk(": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n")); 3658 break; 3659 case FLASH_UPDATE_IN_PROGRESS: 3660 PM8001_MSG_DBG(pm8001_ha, 3661 pm8001_printk(": FLASH_UPDATE_IN_PROGRESS\n")); 3662 break; 3663 case FLASH_UPDATE_HDR_ERR: 3664 PM8001_MSG_DBG(pm8001_ha, 3665 pm8001_printk(": FLASH_UPDATE_HDR_ERR\n")); 3666 break; 3667 case FLASH_UPDATE_OFFSET_ERR: 3668 PM8001_MSG_DBG(pm8001_ha, 3669 pm8001_printk(": FLASH_UPDATE_OFFSET_ERR\n")); 3670 break; 3671 case FLASH_UPDATE_CRC_ERR: 3672 PM8001_MSG_DBG(pm8001_ha, 3673 pm8001_printk(": FLASH_UPDATE_CRC_ERR\n")); 3674 break; 3675 case FLASH_UPDATE_LENGTH_ERR: 3676 PM8001_MSG_DBG(pm8001_ha, 3677 pm8001_printk(": FLASH_UPDATE_LENGTH_ERR\n")); 3678 break; 3679 case FLASH_UPDATE_HW_ERR: 3680 PM8001_MSG_DBG(pm8001_ha, 3681 pm8001_printk(": FLASH_UPDATE_HW_ERR\n")); 3682 break; 3683 case FLASH_UPDATE_DNLD_NOT_SUPPORTED: 3684 PM8001_MSG_DBG(pm8001_ha, 3685 pm8001_printk(": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n")); 3686 break; 3687 case FLASH_UPDATE_DISABLED: 3688 PM8001_MSG_DBG(pm8001_ha, 3689 pm8001_printk(": FLASH_UPDATE_DISABLED\n")); 3690 break; 3691 default: 3692 PM8001_MSG_DBG(pm8001_ha, 3693 pm8001_printk("No matched status = %d\n", status)); 3694 break; 3695 } 3696 kfree(ccb->fw_control_context); 3697 ccb->task = NULL; 3698 ccb->ccb_tag = 0xFFFFFFFF; 3699 pm8001_tag_free(pm8001_ha, tag); 3700 complete(pm8001_ha->nvmd_completion); 3701 return 0; 3702 } 3703 3704 int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 3705 { 3706 u32 status; 3707 int i; 3708 struct general_event_resp *pPayload = 3709 (struct general_event_resp *)(piomb + 4); 3710 status = le32_to_cpu(pPayload->status); 3711 PM8001_MSG_DBG(pm8001_ha, 3712 pm8001_printk(" status = 0x%x\n", status)); 3713 for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++) 3714 PM8001_MSG_DBG(pm8001_ha, 3715 pm8001_printk("inb_IOMB_payload[0x%x] 0x%x,\n", i, 3716 pPayload->inb_IOMB_payload[i])); 3717 return 0; 3718 } 3719 3720 int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3721 { 3722 struct sas_task *t; 3723 struct pm8001_ccb_info *ccb; 3724 unsigned long flags; 3725 u32 status ; 3726 u32 tag, scp; 3727 struct task_status_struct *ts; 3728 struct pm8001_device *pm8001_dev; 3729 3730 struct task_abort_resp *pPayload = 3731 (struct task_abort_resp *)(piomb + 4); 3732 3733 status = le32_to_cpu(pPayload->status); 3734 tag = le32_to_cpu(pPayload->tag); 3735 if (!tag) { 3736 PM8001_FAIL_DBG(pm8001_ha, 3737 pm8001_printk(" TAG NULL. RETURNING !!!")); 3738 return -1; 3739 } 3740 3741 scp = le32_to_cpu(pPayload->scp); 3742 ccb = &pm8001_ha->ccb_info[tag]; 3743 t = ccb->task; 3744 pm8001_dev = ccb->device; /* retrieve device */ 3745 3746 if (!t) { 3747 PM8001_FAIL_DBG(pm8001_ha, 3748 pm8001_printk(" TASK NULL. RETURNING !!!")); 3749 return -1; 3750 } 3751 ts = &t->task_status; 3752 if (status != 0) 3753 PM8001_FAIL_DBG(pm8001_ha, 3754 pm8001_printk("task abort failed status 0x%x ," 3755 "tag = 0x%x, scp= 0x%x\n", status, tag, scp)); 3756 switch (status) { 3757 case IO_SUCCESS: 3758 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); 3759 ts->resp = SAS_TASK_COMPLETE; 3760 ts->stat = SAM_STAT_GOOD; 3761 break; 3762 case IO_NOT_VALID: 3763 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_NOT_VALID\n")); 3764 ts->resp = TMF_RESP_FUNC_FAILED; 3765 break; 3766 } 3767 spin_lock_irqsave(&t->task_state_lock, flags); 3768 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 3769 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 3770 t->task_state_flags |= SAS_TASK_STATE_DONE; 3771 spin_unlock_irqrestore(&t->task_state_lock, flags); 3772 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 3773 mb(); 3774 3775 if (pm8001_dev->id & NCQ_ABORT_ALL_FLAG) { 3776 pm8001_tag_free(pm8001_ha, tag); 3777 sas_free_task(t); 3778 /* clear the flag */ 3779 pm8001_dev->id &= 0xBFFFFFFF; 3780 } else 3781 t->task_done(t); 3782 3783 return 0; 3784 } 3785 3786 /** 3787 * mpi_hw_event -The hw event has come. 3788 * @pm8001_ha: our hba card information 3789 * @piomb: IO message buffer 3790 */ 3791 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb) 3792 { 3793 unsigned long flags; 3794 struct hw_event_resp *pPayload = 3795 (struct hw_event_resp *)(piomb + 4); 3796 u32 lr_evt_status_phyid_portid = 3797 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3798 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3799 u8 phy_id = 3800 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3801 u16 eventType = 3802 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8); 3803 u8 status = 3804 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24); 3805 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3806 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3807 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id]; 3808 PM8001_MSG_DBG(pm8001_ha, 3809 pm8001_printk("outbound queue HW event & event type : ")); 3810 switch (eventType) { 3811 case HW_EVENT_PHY_START_STATUS: 3812 PM8001_MSG_DBG(pm8001_ha, 3813 pm8001_printk("HW_EVENT_PHY_START_STATUS" 3814 " status = %x\n", status)); 3815 if (status == 0) { 3816 phy->phy_state = 1; 3817 if (pm8001_ha->flags == PM8001F_RUN_TIME && 3818 phy->enable_completion != NULL) 3819 complete(phy->enable_completion); 3820 } 3821 break; 3822 case HW_EVENT_SAS_PHY_UP: 3823 PM8001_MSG_DBG(pm8001_ha, 3824 pm8001_printk("HW_EVENT_PHY_START_STATUS\n")); 3825 hw_event_sas_phy_up(pm8001_ha, piomb); 3826 break; 3827 case HW_EVENT_SATA_PHY_UP: 3828 PM8001_MSG_DBG(pm8001_ha, 3829 pm8001_printk("HW_EVENT_SATA_PHY_UP\n")); 3830 hw_event_sata_phy_up(pm8001_ha, piomb); 3831 break; 3832 case HW_EVENT_PHY_STOP_STATUS: 3833 PM8001_MSG_DBG(pm8001_ha, 3834 pm8001_printk("HW_EVENT_PHY_STOP_STATUS " 3835 "status = %x\n", status)); 3836 if (status == 0) 3837 phy->phy_state = 0; 3838 break; 3839 case HW_EVENT_SATA_SPINUP_HOLD: 3840 PM8001_MSG_DBG(pm8001_ha, 3841 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n")); 3842 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD); 3843 break; 3844 case HW_EVENT_PHY_DOWN: 3845 PM8001_MSG_DBG(pm8001_ha, 3846 pm8001_printk("HW_EVENT_PHY_DOWN\n")); 3847 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL); 3848 phy->phy_attached = 0; 3849 phy->phy_state = 0; 3850 hw_event_phy_down(pm8001_ha, piomb); 3851 break; 3852 case HW_EVENT_PORT_INVALID: 3853 PM8001_MSG_DBG(pm8001_ha, 3854 pm8001_printk("HW_EVENT_PORT_INVALID\n")); 3855 sas_phy_disconnected(sas_phy); 3856 phy->phy_attached = 0; 3857 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3858 break; 3859 /* the broadcast change primitive received, tell the LIBSAS this event 3860 to revalidate the sas domain*/ 3861 case HW_EVENT_BROADCAST_CHANGE: 3862 PM8001_MSG_DBG(pm8001_ha, 3863 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n")); 3864 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE, 3865 port_id, phy_id, 1, 0); 3866 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3867 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE; 3868 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3869 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3870 break; 3871 case HW_EVENT_PHY_ERROR: 3872 PM8001_MSG_DBG(pm8001_ha, 3873 pm8001_printk("HW_EVENT_PHY_ERROR\n")); 3874 sas_phy_disconnected(&phy->sas_phy); 3875 phy->phy_attached = 0; 3876 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR); 3877 break; 3878 case HW_EVENT_BROADCAST_EXP: 3879 PM8001_MSG_DBG(pm8001_ha, 3880 pm8001_printk("HW_EVENT_BROADCAST_EXP\n")); 3881 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3882 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP; 3883 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3884 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3885 break; 3886 case HW_EVENT_LINK_ERR_INVALID_DWORD: 3887 PM8001_MSG_DBG(pm8001_ha, 3888 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n")); 3889 pm8001_hw_event_ack_req(pm8001_ha, 0, 3890 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0); 3891 sas_phy_disconnected(sas_phy); 3892 phy->phy_attached = 0; 3893 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3894 break; 3895 case HW_EVENT_LINK_ERR_DISPARITY_ERROR: 3896 PM8001_MSG_DBG(pm8001_ha, 3897 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n")); 3898 pm8001_hw_event_ack_req(pm8001_ha, 0, 3899 HW_EVENT_LINK_ERR_DISPARITY_ERROR, 3900 port_id, phy_id, 0, 0); 3901 sas_phy_disconnected(sas_phy); 3902 phy->phy_attached = 0; 3903 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3904 break; 3905 case HW_EVENT_LINK_ERR_CODE_VIOLATION: 3906 PM8001_MSG_DBG(pm8001_ha, 3907 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n")); 3908 pm8001_hw_event_ack_req(pm8001_ha, 0, 3909 HW_EVENT_LINK_ERR_CODE_VIOLATION, 3910 port_id, phy_id, 0, 0); 3911 sas_phy_disconnected(sas_phy); 3912 phy->phy_attached = 0; 3913 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3914 break; 3915 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH: 3916 PM8001_MSG_DBG(pm8001_ha, 3917 pm8001_printk("HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n")); 3918 pm8001_hw_event_ack_req(pm8001_ha, 0, 3919 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH, 3920 port_id, phy_id, 0, 0); 3921 sas_phy_disconnected(sas_phy); 3922 phy->phy_attached = 0; 3923 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3924 break; 3925 case HW_EVENT_MALFUNCTION: 3926 PM8001_MSG_DBG(pm8001_ha, 3927 pm8001_printk("HW_EVENT_MALFUNCTION\n")); 3928 break; 3929 case HW_EVENT_BROADCAST_SES: 3930 PM8001_MSG_DBG(pm8001_ha, 3931 pm8001_printk("HW_EVENT_BROADCAST_SES\n")); 3932 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3933 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES; 3934 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3935 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3936 break; 3937 case HW_EVENT_INBOUND_CRC_ERROR: 3938 PM8001_MSG_DBG(pm8001_ha, 3939 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n")); 3940 pm8001_hw_event_ack_req(pm8001_ha, 0, 3941 HW_EVENT_INBOUND_CRC_ERROR, 3942 port_id, phy_id, 0, 0); 3943 break; 3944 case HW_EVENT_HARD_RESET_RECEIVED: 3945 PM8001_MSG_DBG(pm8001_ha, 3946 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n")); 3947 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET); 3948 break; 3949 case HW_EVENT_ID_FRAME_TIMEOUT: 3950 PM8001_MSG_DBG(pm8001_ha, 3951 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n")); 3952 sas_phy_disconnected(sas_phy); 3953 phy->phy_attached = 0; 3954 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3955 break; 3956 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED: 3957 PM8001_MSG_DBG(pm8001_ha, 3958 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n")); 3959 pm8001_hw_event_ack_req(pm8001_ha, 0, 3960 HW_EVENT_LINK_ERR_PHY_RESET_FAILED, 3961 port_id, phy_id, 0, 0); 3962 sas_phy_disconnected(sas_phy); 3963 phy->phy_attached = 0; 3964 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3965 break; 3966 case HW_EVENT_PORT_RESET_TIMER_TMO: 3967 PM8001_MSG_DBG(pm8001_ha, 3968 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n")); 3969 sas_phy_disconnected(sas_phy); 3970 phy->phy_attached = 0; 3971 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3972 break; 3973 case HW_EVENT_PORT_RECOVERY_TIMER_TMO: 3974 PM8001_MSG_DBG(pm8001_ha, 3975 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n")); 3976 sas_phy_disconnected(sas_phy); 3977 phy->phy_attached = 0; 3978 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3979 break; 3980 case HW_EVENT_PORT_RECOVER: 3981 PM8001_MSG_DBG(pm8001_ha, 3982 pm8001_printk("HW_EVENT_PORT_RECOVER\n")); 3983 break; 3984 case HW_EVENT_PORT_RESET_COMPLETE: 3985 PM8001_MSG_DBG(pm8001_ha, 3986 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n")); 3987 break; 3988 case EVENT_BROADCAST_ASYNCH_EVENT: 3989 PM8001_MSG_DBG(pm8001_ha, 3990 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n")); 3991 break; 3992 default: 3993 PM8001_MSG_DBG(pm8001_ha, 3994 pm8001_printk("Unknown event type = %x\n", eventType)); 3995 break; 3996 } 3997 return 0; 3998 } 3999 4000 /** 4001 * process_one_iomb - process one outbound Queue memory block 4002 * @pm8001_ha: our hba card information 4003 * @piomb: IO message buffer 4004 */ 4005 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb) 4006 { 4007 __le32 pHeader = *(__le32 *)piomb; 4008 u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF); 4009 4010 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("process_one_iomb:")); 4011 4012 switch (opc) { 4013 case OPC_OUB_ECHO: 4014 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n")); 4015 break; 4016 case OPC_OUB_HW_EVENT: 4017 PM8001_MSG_DBG(pm8001_ha, 4018 pm8001_printk("OPC_OUB_HW_EVENT\n")); 4019 mpi_hw_event(pm8001_ha, piomb); 4020 break; 4021 case OPC_OUB_SSP_COMP: 4022 PM8001_MSG_DBG(pm8001_ha, 4023 pm8001_printk("OPC_OUB_SSP_COMP\n")); 4024 mpi_ssp_completion(pm8001_ha, piomb); 4025 break; 4026 case OPC_OUB_SMP_COMP: 4027 PM8001_MSG_DBG(pm8001_ha, 4028 pm8001_printk("OPC_OUB_SMP_COMP\n")); 4029 mpi_smp_completion(pm8001_ha, piomb); 4030 break; 4031 case OPC_OUB_LOCAL_PHY_CNTRL: 4032 PM8001_MSG_DBG(pm8001_ha, 4033 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n")); 4034 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb); 4035 break; 4036 case OPC_OUB_DEV_REGIST: 4037 PM8001_MSG_DBG(pm8001_ha, 4038 pm8001_printk("OPC_OUB_DEV_REGIST\n")); 4039 pm8001_mpi_reg_resp(pm8001_ha, piomb); 4040 break; 4041 case OPC_OUB_DEREG_DEV: 4042 PM8001_MSG_DBG(pm8001_ha, 4043 pm8001_printk("unregister the device\n")); 4044 pm8001_mpi_dereg_resp(pm8001_ha, piomb); 4045 break; 4046 case OPC_OUB_GET_DEV_HANDLE: 4047 PM8001_MSG_DBG(pm8001_ha, 4048 pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n")); 4049 break; 4050 case OPC_OUB_SATA_COMP: 4051 PM8001_MSG_DBG(pm8001_ha, 4052 pm8001_printk("OPC_OUB_SATA_COMP\n")); 4053 mpi_sata_completion(pm8001_ha, piomb); 4054 break; 4055 case OPC_OUB_SATA_EVENT: 4056 PM8001_MSG_DBG(pm8001_ha, 4057 pm8001_printk("OPC_OUB_SATA_EVENT\n")); 4058 mpi_sata_event(pm8001_ha, piomb); 4059 break; 4060 case OPC_OUB_SSP_EVENT: 4061 PM8001_MSG_DBG(pm8001_ha, 4062 pm8001_printk("OPC_OUB_SSP_EVENT\n")); 4063 mpi_ssp_event(pm8001_ha, piomb); 4064 break; 4065 case OPC_OUB_DEV_HANDLE_ARRIV: 4066 PM8001_MSG_DBG(pm8001_ha, 4067 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n")); 4068 /*This is for target*/ 4069 break; 4070 case OPC_OUB_SSP_RECV_EVENT: 4071 PM8001_MSG_DBG(pm8001_ha, 4072 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n")); 4073 /*This is for target*/ 4074 break; 4075 case OPC_OUB_DEV_INFO: 4076 PM8001_MSG_DBG(pm8001_ha, 4077 pm8001_printk("OPC_OUB_DEV_INFO\n")); 4078 break; 4079 case OPC_OUB_FW_FLASH_UPDATE: 4080 PM8001_MSG_DBG(pm8001_ha, 4081 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n")); 4082 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb); 4083 break; 4084 case OPC_OUB_GPIO_RESPONSE: 4085 PM8001_MSG_DBG(pm8001_ha, 4086 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n")); 4087 break; 4088 case OPC_OUB_GPIO_EVENT: 4089 PM8001_MSG_DBG(pm8001_ha, 4090 pm8001_printk("OPC_OUB_GPIO_EVENT\n")); 4091 break; 4092 case OPC_OUB_GENERAL_EVENT: 4093 PM8001_MSG_DBG(pm8001_ha, 4094 pm8001_printk("OPC_OUB_GENERAL_EVENT\n")); 4095 pm8001_mpi_general_event(pm8001_ha, piomb); 4096 break; 4097 case OPC_OUB_SSP_ABORT_RSP: 4098 PM8001_MSG_DBG(pm8001_ha, 4099 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n")); 4100 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 4101 break; 4102 case OPC_OUB_SATA_ABORT_RSP: 4103 PM8001_MSG_DBG(pm8001_ha, 4104 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n")); 4105 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 4106 break; 4107 case OPC_OUB_SAS_DIAG_MODE_START_END: 4108 PM8001_MSG_DBG(pm8001_ha, 4109 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n")); 4110 break; 4111 case OPC_OUB_SAS_DIAG_EXECUTE: 4112 PM8001_MSG_DBG(pm8001_ha, 4113 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n")); 4114 break; 4115 case OPC_OUB_GET_TIME_STAMP: 4116 PM8001_MSG_DBG(pm8001_ha, 4117 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n")); 4118 break; 4119 case OPC_OUB_SAS_HW_EVENT_ACK: 4120 PM8001_MSG_DBG(pm8001_ha, 4121 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n")); 4122 break; 4123 case OPC_OUB_PORT_CONTROL: 4124 PM8001_MSG_DBG(pm8001_ha, 4125 pm8001_printk("OPC_OUB_PORT_CONTROL\n")); 4126 break; 4127 case OPC_OUB_SMP_ABORT_RSP: 4128 PM8001_MSG_DBG(pm8001_ha, 4129 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n")); 4130 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 4131 break; 4132 case OPC_OUB_GET_NVMD_DATA: 4133 PM8001_MSG_DBG(pm8001_ha, 4134 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n")); 4135 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb); 4136 break; 4137 case OPC_OUB_SET_NVMD_DATA: 4138 PM8001_MSG_DBG(pm8001_ha, 4139 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n")); 4140 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb); 4141 break; 4142 case OPC_OUB_DEVICE_HANDLE_REMOVAL: 4143 PM8001_MSG_DBG(pm8001_ha, 4144 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n")); 4145 break; 4146 case OPC_OUB_SET_DEVICE_STATE: 4147 PM8001_MSG_DBG(pm8001_ha, 4148 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n")); 4149 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb); 4150 break; 4151 case OPC_OUB_GET_DEVICE_STATE: 4152 PM8001_MSG_DBG(pm8001_ha, 4153 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n")); 4154 break; 4155 case OPC_OUB_SET_DEV_INFO: 4156 PM8001_MSG_DBG(pm8001_ha, 4157 pm8001_printk("OPC_OUB_SET_DEV_INFO\n")); 4158 break; 4159 case OPC_OUB_SAS_RE_INITIALIZE: 4160 PM8001_MSG_DBG(pm8001_ha, 4161 pm8001_printk("OPC_OUB_SAS_RE_INITIALIZE\n")); 4162 break; 4163 default: 4164 PM8001_MSG_DBG(pm8001_ha, 4165 pm8001_printk("Unknown outbound Queue IOMB OPC = %x\n", 4166 opc)); 4167 break; 4168 } 4169 } 4170 4171 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec) 4172 { 4173 struct outbound_queue_table *circularQ; 4174 void *pMsg1 = NULL; 4175 u8 uninitialized_var(bc); 4176 u32 ret = MPI_IO_STATUS_FAIL; 4177 unsigned long flags; 4178 4179 spin_lock_irqsave(&pm8001_ha->lock, flags); 4180 circularQ = &pm8001_ha->outbnd_q_tbl[vec]; 4181 do { 4182 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc); 4183 if (MPI_IO_STATUS_SUCCESS == ret) { 4184 /* process the outbound message */ 4185 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4)); 4186 /* free the message from the outbound circular buffer */ 4187 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1, 4188 circularQ, bc); 4189 } 4190 if (MPI_IO_STATUS_BUSY == ret) { 4191 /* Update the producer index from SPC */ 4192 circularQ->producer_index = 4193 cpu_to_le32(pm8001_read_32(circularQ->pi_virt)); 4194 if (le32_to_cpu(circularQ->producer_index) == 4195 circularQ->consumer_idx) 4196 /* OQ is empty */ 4197 break; 4198 } 4199 } while (1); 4200 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 4201 return ret; 4202 } 4203 4204 /* DMA_... to our direction translation. */ 4205 static const u8 data_dir_flags[] = { 4206 [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */ 4207 [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */ 4208 [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */ 4209 [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */ 4210 }; 4211 void 4212 pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd) 4213 { 4214 int i; 4215 struct scatterlist *sg; 4216 struct pm8001_prd *buf_prd = prd; 4217 4218 for_each_sg(scatter, sg, nr, i) { 4219 buf_prd->addr = cpu_to_le64(sg_dma_address(sg)); 4220 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg)); 4221 buf_prd->im_len.e = 0; 4222 buf_prd++; 4223 } 4224 } 4225 4226 static void build_smp_cmd(u32 deviceID, __le32 hTag, struct smp_req *psmp_cmd) 4227 { 4228 psmp_cmd->tag = hTag; 4229 psmp_cmd->device_id = cpu_to_le32(deviceID); 4230 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1)); 4231 } 4232 4233 /** 4234 * pm8001_chip_smp_req - send a SMP task to FW 4235 * @pm8001_ha: our hba card information. 4236 * @ccb: the ccb information this request used. 4237 */ 4238 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha, 4239 struct pm8001_ccb_info *ccb) 4240 { 4241 int elem, rc; 4242 struct sas_task *task = ccb->task; 4243 struct domain_device *dev = task->dev; 4244 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4245 struct scatterlist *sg_req, *sg_resp; 4246 u32 req_len, resp_len; 4247 struct smp_req smp_cmd; 4248 u32 opc; 4249 struct inbound_queue_table *circularQ; 4250 4251 memset(&smp_cmd, 0, sizeof(smp_cmd)); 4252 /* 4253 * DMA-map SMP request, response buffers 4254 */ 4255 sg_req = &task->smp_task.smp_req; 4256 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE); 4257 if (!elem) 4258 return -ENOMEM; 4259 req_len = sg_dma_len(sg_req); 4260 4261 sg_resp = &task->smp_task.smp_resp; 4262 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE); 4263 if (!elem) { 4264 rc = -ENOMEM; 4265 goto err_out; 4266 } 4267 resp_len = sg_dma_len(sg_resp); 4268 /* must be in dwords */ 4269 if ((req_len & 0x3) || (resp_len & 0x3)) { 4270 rc = -EINVAL; 4271 goto err_out_2; 4272 } 4273 4274 opc = OPC_INB_SMP_REQUEST; 4275 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4276 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag); 4277 smp_cmd.long_smp_req.long_req_addr = 4278 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req)); 4279 smp_cmd.long_smp_req.long_req_size = 4280 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4); 4281 smp_cmd.long_smp_req.long_resp_addr = 4282 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp)); 4283 smp_cmd.long_smp_req.long_resp_size = 4284 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4); 4285 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd); 4286 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, 4287 (u32 *)&smp_cmd, 0); 4288 if (rc) 4289 goto err_out_2; 4290 4291 return 0; 4292 4293 err_out_2: 4294 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1, 4295 DMA_FROM_DEVICE); 4296 err_out: 4297 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1, 4298 DMA_TO_DEVICE); 4299 return rc; 4300 } 4301 4302 /** 4303 * pm8001_chip_ssp_io_req - send a SSP task to FW 4304 * @pm8001_ha: our hba card information. 4305 * @ccb: the ccb information this request used. 4306 */ 4307 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha, 4308 struct pm8001_ccb_info *ccb) 4309 { 4310 struct sas_task *task = ccb->task; 4311 struct domain_device *dev = task->dev; 4312 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4313 struct ssp_ini_io_start_req ssp_cmd; 4314 u32 tag = ccb->ccb_tag; 4315 int ret; 4316 u64 phys_addr; 4317 struct inbound_queue_table *circularQ; 4318 u32 opc = OPC_INB_SSPINIIOSTART; 4319 memset(&ssp_cmd, 0, sizeof(ssp_cmd)); 4320 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8); 4321 ssp_cmd.dir_m_tlr = 4322 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for 4323 SAS 1.1 compatible TLR*/ 4324 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4325 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id); 4326 ssp_cmd.tag = cpu_to_le32(tag); 4327 if (task->ssp_task.enable_first_burst) 4328 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80; 4329 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3); 4330 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7); 4331 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd, 4332 task->ssp_task.cmd->cmd_len); 4333 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4334 4335 /* fill in PRD (scatter/gather) table, if any */ 4336 if (task->num_scatter > 1) { 4337 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd); 4338 phys_addr = ccb->ccb_dma_handle + 4339 offsetof(struct pm8001_ccb_info, buf_prd[0]); 4340 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(phys_addr)); 4341 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr)); 4342 ssp_cmd.esgl = cpu_to_le32(1<<31); 4343 } else if (task->num_scatter == 1) { 4344 u64 dma_addr = sg_dma_address(task->scatter); 4345 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr)); 4346 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr)); 4347 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4348 ssp_cmd.esgl = 0; 4349 } else if (task->num_scatter == 0) { 4350 ssp_cmd.addr_low = 0; 4351 ssp_cmd.addr_high = 0; 4352 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4353 ssp_cmd.esgl = 0; 4354 } 4355 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd, 0); 4356 return ret; 4357 } 4358 4359 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha, 4360 struct pm8001_ccb_info *ccb) 4361 { 4362 struct sas_task *task = ccb->task; 4363 struct domain_device *dev = task->dev; 4364 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev; 4365 u32 tag = ccb->ccb_tag; 4366 int ret; 4367 struct sata_start_req sata_cmd; 4368 u32 hdr_tag, ncg_tag = 0; 4369 u64 phys_addr; 4370 u32 ATAP = 0x0; 4371 u32 dir; 4372 struct inbound_queue_table *circularQ; 4373 unsigned long flags; 4374 u32 opc = OPC_INB_SATA_HOST_OPSTART; 4375 memset(&sata_cmd, 0, sizeof(sata_cmd)); 4376 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4377 if (task->data_dir == DMA_NONE) { 4378 ATAP = 0x04; /* no data*/ 4379 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n")); 4380 } else if (likely(!task->ata_task.device_control_reg_update)) { 4381 if (task->ata_task.dma_xfer) { 4382 ATAP = 0x06; /* DMA */ 4383 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n")); 4384 } else { 4385 ATAP = 0x05; /* PIO*/ 4386 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n")); 4387 } 4388 if (task->ata_task.use_ncq && 4389 dev->sata_dev.class != ATA_DEV_ATAPI) { 4390 ATAP = 0x07; /* FPDMA */ 4391 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n")); 4392 } 4393 } 4394 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) { 4395 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 4396 ncg_tag = hdr_tag; 4397 } 4398 dir = data_dir_flags[task->data_dir] << 8; 4399 sata_cmd.tag = cpu_to_le32(tag); 4400 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 4401 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4402 sata_cmd.ncqtag_atap_dir_m = 4403 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir); 4404 sata_cmd.sata_fis = task->ata_task.fis; 4405 if (likely(!task->ata_task.device_control_reg_update)) 4406 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */ 4407 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */ 4408 /* fill in PRD (scatter/gather) table, if any */ 4409 if (task->num_scatter > 1) { 4410 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd); 4411 phys_addr = ccb->ccb_dma_handle + 4412 offsetof(struct pm8001_ccb_info, buf_prd[0]); 4413 sata_cmd.addr_low = lower_32_bits(phys_addr); 4414 sata_cmd.addr_high = upper_32_bits(phys_addr); 4415 sata_cmd.esgl = cpu_to_le32(1 << 31); 4416 } else if (task->num_scatter == 1) { 4417 u64 dma_addr = sg_dma_address(task->scatter); 4418 sata_cmd.addr_low = lower_32_bits(dma_addr); 4419 sata_cmd.addr_high = upper_32_bits(dma_addr); 4420 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4421 sata_cmd.esgl = 0; 4422 } else if (task->num_scatter == 0) { 4423 sata_cmd.addr_low = 0; 4424 sata_cmd.addr_high = 0; 4425 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4426 sata_cmd.esgl = 0; 4427 } 4428 4429 /* Check for read log for failed drive and return */ 4430 if (sata_cmd.sata_fis.command == 0x2f) { 4431 if (((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) || 4432 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) || 4433 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) { 4434 struct task_status_struct *ts; 4435 4436 pm8001_ha_dev->id &= 0xDFFFFFFF; 4437 ts = &task->task_status; 4438 4439 spin_lock_irqsave(&task->task_state_lock, flags); 4440 ts->resp = SAS_TASK_COMPLETE; 4441 ts->stat = SAM_STAT_GOOD; 4442 task->task_state_flags &= ~SAS_TASK_STATE_PENDING; 4443 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 4444 task->task_state_flags |= SAS_TASK_STATE_DONE; 4445 if (unlikely((task->task_state_flags & 4446 SAS_TASK_STATE_ABORTED))) { 4447 spin_unlock_irqrestore(&task->task_state_lock, 4448 flags); 4449 PM8001_FAIL_DBG(pm8001_ha, 4450 pm8001_printk("task 0x%p resp 0x%x " 4451 " stat 0x%x but aborted by upper layer " 4452 "\n", task, ts->resp, ts->stat)); 4453 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag); 4454 } else { 4455 spin_unlock_irqrestore(&task->task_state_lock, 4456 flags); 4457 pm8001_ccb_task_free_done(pm8001_ha, task, 4458 ccb, tag); 4459 return 0; 4460 } 4461 } 4462 } 4463 4464 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0); 4465 return ret; 4466 } 4467 4468 /** 4469 * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND 4470 * @pm8001_ha: our hba card information. 4471 * @num: the inbound queue number 4472 * @phy_id: the phy id which we wanted to start up. 4473 */ 4474 static int 4475 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id) 4476 { 4477 struct phy_start_req payload; 4478 struct inbound_queue_table *circularQ; 4479 int ret; 4480 u32 tag = 0x01; 4481 u32 opcode = OPC_INB_PHYSTART; 4482 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4483 memset(&payload, 0, sizeof(payload)); 4484 payload.tag = cpu_to_le32(tag); 4485 /* 4486 ** [0:7] PHY Identifier 4487 ** [8:11] link rate 1.5G, 3G, 6G 4488 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both 4489 ** [14] 0b disable spin up hold; 1b enable spin up hold 4490 */ 4491 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE | 4492 LINKMODE_AUTO | LINKRATE_15 | 4493 LINKRATE_30 | LINKRATE_60 | phy_id); 4494 payload.sas_identify.dev_type = SAS_END_DEVICE; 4495 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL; 4496 memcpy(payload.sas_identify.sas_addr, 4497 pm8001_ha->sas_addr, SAS_ADDR_SIZE); 4498 payload.sas_identify.phy_id = phy_id; 4499 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0); 4500 return ret; 4501 } 4502 4503 /** 4504 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND 4505 * @pm8001_ha: our hba card information. 4506 * @num: the inbound queue number 4507 * @phy_id: the phy id which we wanted to start up. 4508 */ 4509 static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha, 4510 u8 phy_id) 4511 { 4512 struct phy_stop_req payload; 4513 struct inbound_queue_table *circularQ; 4514 int ret; 4515 u32 tag = 0x01; 4516 u32 opcode = OPC_INB_PHYSTOP; 4517 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4518 memset(&payload, 0, sizeof(payload)); 4519 payload.tag = cpu_to_le32(tag); 4520 payload.phy_id = cpu_to_le32(phy_id); 4521 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0); 4522 return ret; 4523 } 4524 4525 /** 4526 * see comments on pm8001_mpi_reg_resp. 4527 */ 4528 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha, 4529 struct pm8001_device *pm8001_dev, u32 flag) 4530 { 4531 struct reg_dev_req payload; 4532 u32 opc; 4533 u32 stp_sspsmp_sata = 0x4; 4534 struct inbound_queue_table *circularQ; 4535 u32 linkrate, phy_id; 4536 int rc, tag = 0xdeadbeef; 4537 struct pm8001_ccb_info *ccb; 4538 u8 retryFlag = 0x1; 4539 u16 firstBurstSize = 0; 4540 u16 ITNT = 2000; 4541 struct domain_device *dev = pm8001_dev->sas_device; 4542 struct domain_device *parent_dev = dev->parent; 4543 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4544 4545 memset(&payload, 0, sizeof(payload)); 4546 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4547 if (rc) 4548 return rc; 4549 ccb = &pm8001_ha->ccb_info[tag]; 4550 ccb->device = pm8001_dev; 4551 ccb->ccb_tag = tag; 4552 payload.tag = cpu_to_le32(tag); 4553 if (flag == 1) 4554 stp_sspsmp_sata = 0x02; /*direct attached sata */ 4555 else { 4556 if (pm8001_dev->dev_type == SAS_SATA_DEV) 4557 stp_sspsmp_sata = 0x00; /* stp*/ 4558 else if (pm8001_dev->dev_type == SAS_END_DEVICE || 4559 pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE || 4560 pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE) 4561 stp_sspsmp_sata = 0x01; /*ssp or smp*/ 4562 } 4563 if (parent_dev && dev_is_expander(parent_dev->dev_type)) 4564 phy_id = parent_dev->ex_dev.ex_phy->phy_id; 4565 else 4566 phy_id = pm8001_dev->attached_phy; 4567 opc = OPC_INB_REG_DEV; 4568 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ? 4569 pm8001_dev->sas_device->linkrate : dev->port->linkrate; 4570 payload.phyid_portid = 4571 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) | 4572 ((phy_id & 0x0F) << 4)); 4573 payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) | 4574 ((linkrate & 0x0F) * 0x1000000) | 4575 ((stp_sspsmp_sata & 0x03) * 0x10000000)); 4576 payload.firstburstsize_ITNexustimeout = 4577 cpu_to_le32(ITNT | (firstBurstSize * 0x10000)); 4578 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr, 4579 SAS_ADDR_SIZE); 4580 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 4581 return rc; 4582 } 4583 4584 /** 4585 * see comments on pm8001_mpi_reg_resp. 4586 */ 4587 int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha, 4588 u32 device_id) 4589 { 4590 struct dereg_dev_req payload; 4591 u32 opc = OPC_INB_DEREG_DEV_HANDLE; 4592 int ret; 4593 struct inbound_queue_table *circularQ; 4594 4595 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4596 memset(&payload, 0, sizeof(payload)); 4597 payload.tag = cpu_to_le32(1); 4598 payload.device_id = cpu_to_le32(device_id); 4599 PM8001_MSG_DBG(pm8001_ha, 4600 pm8001_printk("unregister device device_id = %d\n", device_id)); 4601 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 4602 return ret; 4603 } 4604 4605 /** 4606 * pm8001_chip_phy_ctl_req - support the local phy operation 4607 * @pm8001_ha: our hba card information. 4608 * @num: the inbound queue number 4609 * @phy_id: the phy id which we wanted to operate 4610 * @phy_op: 4611 */ 4612 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 4613 u32 phyId, u32 phy_op) 4614 { 4615 struct local_phy_ctl_req payload; 4616 struct inbound_queue_table *circularQ; 4617 int ret; 4618 u32 opc = OPC_INB_LOCAL_PHY_CONTROL; 4619 memset(&payload, 0, sizeof(payload)); 4620 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4621 payload.tag = cpu_to_le32(1); 4622 payload.phyop_phyid = 4623 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F)); 4624 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 4625 return ret; 4626 } 4627 4628 static u32 pm8001_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha) 4629 { 4630 #ifdef PM8001_USE_MSIX 4631 return 1; 4632 #else 4633 u32 value; 4634 4635 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR); 4636 if (value) 4637 return 1; 4638 return 0; 4639 #endif 4640 } 4641 4642 /** 4643 * pm8001_chip_isr - PM8001 isr handler. 4644 * @pm8001_ha: our hba card information. 4645 * @irq: irq number. 4646 * @stat: stat. 4647 */ 4648 static irqreturn_t 4649 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec) 4650 { 4651 pm8001_chip_interrupt_disable(pm8001_ha, vec); 4652 process_oq(pm8001_ha, vec); 4653 pm8001_chip_interrupt_enable(pm8001_ha, vec); 4654 return IRQ_HANDLED; 4655 } 4656 4657 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc, 4658 u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag) 4659 { 4660 struct task_abort_req task_abort; 4661 struct inbound_queue_table *circularQ; 4662 int ret; 4663 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4664 memset(&task_abort, 0, sizeof(task_abort)); 4665 if (ABORT_SINGLE == (flag & ABORT_MASK)) { 4666 task_abort.abort_all = 0; 4667 task_abort.device_id = cpu_to_le32(dev_id); 4668 task_abort.tag_to_abort = cpu_to_le32(task_tag); 4669 task_abort.tag = cpu_to_le32(cmd_tag); 4670 } else if (ABORT_ALL == (flag & ABORT_MASK)) { 4671 task_abort.abort_all = cpu_to_le32(1); 4672 task_abort.device_id = cpu_to_le32(dev_id); 4673 task_abort.tag = cpu_to_le32(cmd_tag); 4674 } 4675 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0); 4676 return ret; 4677 } 4678 4679 /** 4680 * pm8001_chip_abort_task - SAS abort task when error or exception happened. 4681 * @task: the task we wanted to aborted. 4682 * @flag: the abort flag. 4683 */ 4684 int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha, 4685 struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag) 4686 { 4687 u32 opc, device_id; 4688 int rc = TMF_RESP_FUNC_FAILED; 4689 PM8001_EH_DBG(pm8001_ha, 4690 pm8001_printk("cmd_tag = %x, abort task tag = 0x%x", 4691 cmd_tag, task_tag)); 4692 if (pm8001_dev->dev_type == SAS_END_DEVICE) 4693 opc = OPC_INB_SSP_ABORT; 4694 else if (pm8001_dev->dev_type == SAS_SATA_DEV) 4695 opc = OPC_INB_SATA_ABORT; 4696 else 4697 opc = OPC_INB_SMP_ABORT;/* SMP */ 4698 device_id = pm8001_dev->device_id; 4699 rc = send_task_abort(pm8001_ha, opc, device_id, flag, 4700 task_tag, cmd_tag); 4701 if (rc != TMF_RESP_FUNC_COMPLETE) 4702 PM8001_EH_DBG(pm8001_ha, pm8001_printk("rc= %d\n", rc)); 4703 return rc; 4704 } 4705 4706 /** 4707 * pm8001_chip_ssp_tm_req - built the task management command. 4708 * @pm8001_ha: our hba card information. 4709 * @ccb: the ccb information. 4710 * @tmf: task management function. 4711 */ 4712 int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha, 4713 struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf) 4714 { 4715 struct sas_task *task = ccb->task; 4716 struct domain_device *dev = task->dev; 4717 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4718 u32 opc = OPC_INB_SSPINITMSTART; 4719 struct inbound_queue_table *circularQ; 4720 struct ssp_ini_tm_start_req sspTMCmd; 4721 int ret; 4722 4723 memset(&sspTMCmd, 0, sizeof(sspTMCmd)); 4724 sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id); 4725 sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed); 4726 sspTMCmd.tmf = cpu_to_le32(tmf->tmf); 4727 memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8); 4728 sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag); 4729 if (pm8001_ha->chip_id != chip_8001) 4730 sspTMCmd.ds_ads_m = 0x08; 4731 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4732 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd, 0); 4733 return ret; 4734 } 4735 4736 int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha, 4737 void *payload) 4738 { 4739 u32 opc = OPC_INB_GET_NVMD_DATA; 4740 u32 nvmd_type; 4741 int rc; 4742 u32 tag; 4743 struct pm8001_ccb_info *ccb; 4744 struct inbound_queue_table *circularQ; 4745 struct get_nvm_data_req nvmd_req; 4746 struct fw_control_ex *fw_control_context; 4747 struct pm8001_ioctl_payload *ioctl_payload = payload; 4748 4749 nvmd_type = ioctl_payload->minor_function; 4750 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); 4751 if (!fw_control_context) 4752 return -ENOMEM; 4753 fw_control_context->usrAddr = (u8 *)ioctl_payload->func_specific; 4754 fw_control_context->len = ioctl_payload->length; 4755 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4756 memset(&nvmd_req, 0, sizeof(nvmd_req)); 4757 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4758 if (rc) { 4759 kfree(fw_control_context); 4760 return rc; 4761 } 4762 ccb = &pm8001_ha->ccb_info[tag]; 4763 ccb->ccb_tag = tag; 4764 ccb->fw_control_context = fw_control_context; 4765 nvmd_req.tag = cpu_to_le32(tag); 4766 4767 switch (nvmd_type) { 4768 case TWI_DEVICE: { 4769 u32 twi_addr, twi_page_size; 4770 twi_addr = 0xa8; 4771 twi_page_size = 2; 4772 4773 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 | 4774 twi_page_size << 8 | TWI_DEVICE); 4775 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4776 nvmd_req.resp_addr_hi = 4777 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4778 nvmd_req.resp_addr_lo = 4779 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4780 break; 4781 } 4782 case C_SEEPROM: { 4783 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM); 4784 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4785 nvmd_req.resp_addr_hi = 4786 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4787 nvmd_req.resp_addr_lo = 4788 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4789 break; 4790 } 4791 case VPD_FLASH: { 4792 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH); 4793 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4794 nvmd_req.resp_addr_hi = 4795 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4796 nvmd_req.resp_addr_lo = 4797 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4798 break; 4799 } 4800 case EXPAN_ROM: { 4801 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM); 4802 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4803 nvmd_req.resp_addr_hi = 4804 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4805 nvmd_req.resp_addr_lo = 4806 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4807 break; 4808 } 4809 case IOP_RDUMP: { 4810 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | IOP_RDUMP); 4811 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4812 nvmd_req.vpd_offset = cpu_to_le32(ioctl_payload->offset); 4813 nvmd_req.resp_addr_hi = 4814 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4815 nvmd_req.resp_addr_lo = 4816 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4817 break; 4818 } 4819 default: 4820 break; 4821 } 4822 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req, 0); 4823 if (rc) { 4824 kfree(fw_control_context); 4825 pm8001_tag_free(pm8001_ha, tag); 4826 } 4827 return rc; 4828 } 4829 4830 int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha, 4831 void *payload) 4832 { 4833 u32 opc = OPC_INB_SET_NVMD_DATA; 4834 u32 nvmd_type; 4835 int rc; 4836 u32 tag; 4837 struct pm8001_ccb_info *ccb; 4838 struct inbound_queue_table *circularQ; 4839 struct set_nvm_data_req nvmd_req; 4840 struct fw_control_ex *fw_control_context; 4841 struct pm8001_ioctl_payload *ioctl_payload = payload; 4842 4843 nvmd_type = ioctl_payload->minor_function; 4844 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); 4845 if (!fw_control_context) 4846 return -ENOMEM; 4847 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4848 memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr, 4849 &ioctl_payload->func_specific, 4850 ioctl_payload->length); 4851 memset(&nvmd_req, 0, sizeof(nvmd_req)); 4852 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4853 if (rc) { 4854 kfree(fw_control_context); 4855 return -EBUSY; 4856 } 4857 ccb = &pm8001_ha->ccb_info[tag]; 4858 ccb->fw_control_context = fw_control_context; 4859 ccb->ccb_tag = tag; 4860 nvmd_req.tag = cpu_to_le32(tag); 4861 switch (nvmd_type) { 4862 case TWI_DEVICE: { 4863 u32 twi_addr, twi_page_size; 4864 twi_addr = 0xa8; 4865 twi_page_size = 2; 4866 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4867 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 | 4868 twi_page_size << 8 | TWI_DEVICE); 4869 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4870 nvmd_req.resp_addr_hi = 4871 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4872 nvmd_req.resp_addr_lo = 4873 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4874 break; 4875 } 4876 case C_SEEPROM: 4877 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM); 4878 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4879 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4880 nvmd_req.resp_addr_hi = 4881 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4882 nvmd_req.resp_addr_lo = 4883 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4884 break; 4885 case VPD_FLASH: 4886 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH); 4887 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4888 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4889 nvmd_req.resp_addr_hi = 4890 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4891 nvmd_req.resp_addr_lo = 4892 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4893 break; 4894 case EXPAN_ROM: 4895 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM); 4896 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4897 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4898 nvmd_req.resp_addr_hi = 4899 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4900 nvmd_req.resp_addr_lo = 4901 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4902 break; 4903 default: 4904 break; 4905 } 4906 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req, 0); 4907 if (rc) { 4908 kfree(fw_control_context); 4909 pm8001_tag_free(pm8001_ha, tag); 4910 } 4911 return rc; 4912 } 4913 4914 /** 4915 * pm8001_chip_fw_flash_update_build - support the firmware update operation 4916 * @pm8001_ha: our hba card information. 4917 * @fw_flash_updata_info: firmware flash update param 4918 */ 4919 int 4920 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha, 4921 void *fw_flash_updata_info, u32 tag) 4922 { 4923 struct fw_flash_Update_req payload; 4924 struct fw_flash_updata_info *info; 4925 struct inbound_queue_table *circularQ; 4926 int ret; 4927 u32 opc = OPC_INB_FW_FLASH_UPDATE; 4928 4929 memset(&payload, 0, sizeof(struct fw_flash_Update_req)); 4930 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4931 info = fw_flash_updata_info; 4932 payload.tag = cpu_to_le32(tag); 4933 payload.cur_image_len = cpu_to_le32(info->cur_image_len); 4934 payload.cur_image_offset = cpu_to_le32(info->cur_image_offset); 4935 payload.total_image_len = cpu_to_le32(info->total_image_len); 4936 payload.len = info->sgl.im_len.len ; 4937 payload.sgl_addr_lo = 4938 cpu_to_le32(lower_32_bits(le64_to_cpu(info->sgl.addr))); 4939 payload.sgl_addr_hi = 4940 cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr))); 4941 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 4942 return ret; 4943 } 4944 4945 int 4946 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha, 4947 void *payload) 4948 { 4949 struct fw_flash_updata_info flash_update_info; 4950 struct fw_control_info *fw_control; 4951 struct fw_control_ex *fw_control_context; 4952 int rc; 4953 u32 tag; 4954 struct pm8001_ccb_info *ccb; 4955 void *buffer = pm8001_ha->memoryMap.region[FW_FLASH].virt_ptr; 4956 dma_addr_t phys_addr = pm8001_ha->memoryMap.region[FW_FLASH].phys_addr; 4957 struct pm8001_ioctl_payload *ioctl_payload = payload; 4958 4959 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); 4960 if (!fw_control_context) 4961 return -ENOMEM; 4962 fw_control = (struct fw_control_info *)&ioctl_payload->func_specific; 4963 memcpy(buffer, fw_control->buffer, fw_control->len); 4964 flash_update_info.sgl.addr = cpu_to_le64(phys_addr); 4965 flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len); 4966 flash_update_info.sgl.im_len.e = 0; 4967 flash_update_info.cur_image_offset = fw_control->offset; 4968 flash_update_info.cur_image_len = fw_control->len; 4969 flash_update_info.total_image_len = fw_control->size; 4970 fw_control_context->fw_control = fw_control; 4971 fw_control_context->virtAddr = buffer; 4972 fw_control_context->phys_addr = phys_addr; 4973 fw_control_context->len = fw_control->len; 4974 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4975 if (rc) { 4976 kfree(fw_control_context); 4977 return -EBUSY; 4978 } 4979 ccb = &pm8001_ha->ccb_info[tag]; 4980 ccb->fw_control_context = fw_control_context; 4981 ccb->ccb_tag = tag; 4982 rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info, 4983 tag); 4984 return rc; 4985 } 4986 4987 ssize_t 4988 pm8001_get_gsm_dump(struct device *cdev, u32 length, char *buf) 4989 { 4990 u32 value, rem, offset = 0, bar = 0; 4991 u32 index, work_offset, dw_length; 4992 u32 shift_value, gsm_base, gsm_dump_offset; 4993 char *direct_data; 4994 struct Scsi_Host *shost = class_to_shost(cdev); 4995 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 4996 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 4997 4998 direct_data = buf; 4999 gsm_dump_offset = pm8001_ha->fatal_forensic_shift_offset; 5000 5001 /* check max is 1 Mbytes */ 5002 if ((length > 0x100000) || (gsm_dump_offset & 3) || 5003 ((gsm_dump_offset + length) > 0x1000000)) 5004 return -EINVAL; 5005 5006 if (pm8001_ha->chip_id == chip_8001) 5007 bar = 2; 5008 else 5009 bar = 1; 5010 5011 work_offset = gsm_dump_offset & 0xFFFF0000; 5012 offset = gsm_dump_offset & 0x0000FFFF; 5013 gsm_dump_offset = work_offset; 5014 /* adjust length to dword boundary */ 5015 rem = length & 3; 5016 dw_length = length >> 2; 5017 5018 for (index = 0; index < dw_length; index++) { 5019 if ((work_offset + offset) & 0xFFFF0000) { 5020 if (pm8001_ha->chip_id == chip_8001) 5021 shift_value = ((gsm_dump_offset + offset) & 5022 SHIFT_REG_64K_MASK); 5023 else 5024 shift_value = (((gsm_dump_offset + offset) & 5025 SHIFT_REG_64K_MASK) >> 5026 SHIFT_REG_BIT_SHIFT); 5027 5028 if (pm8001_ha->chip_id == chip_8001) { 5029 gsm_base = GSM_BASE; 5030 if (-1 == pm8001_bar4_shift(pm8001_ha, 5031 (gsm_base + shift_value))) 5032 return -EIO; 5033 } else { 5034 gsm_base = 0; 5035 if (-1 == pm80xx_bar4_shift(pm8001_ha, 5036 (gsm_base + shift_value))) 5037 return -EIO; 5038 } 5039 gsm_dump_offset = (gsm_dump_offset + offset) & 5040 0xFFFF0000; 5041 work_offset = 0; 5042 offset = offset & 0x0000FFFF; 5043 } 5044 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) & 5045 0x0000FFFF); 5046 direct_data += sprintf(direct_data, "%08x ", value); 5047 offset += 4; 5048 } 5049 if (rem != 0) { 5050 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) & 5051 0x0000FFFF); 5052 /* xfr for non_dw */ 5053 direct_data += sprintf(direct_data, "%08x ", value); 5054 } 5055 /* Shift back to BAR4 original address */ 5056 if (-1 == pm8001_bar4_shift(pm8001_ha, 0)) 5057 return -EIO; 5058 pm8001_ha->fatal_forensic_shift_offset += 1024; 5059 5060 if (pm8001_ha->fatal_forensic_shift_offset >= 0x100000) 5061 pm8001_ha->fatal_forensic_shift_offset = 0; 5062 return direct_data - buf; 5063 } 5064 5065 int 5066 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha, 5067 struct pm8001_device *pm8001_dev, u32 state) 5068 { 5069 struct set_dev_state_req payload; 5070 struct inbound_queue_table *circularQ; 5071 struct pm8001_ccb_info *ccb; 5072 int rc; 5073 u32 tag; 5074 u32 opc = OPC_INB_SET_DEVICE_STATE; 5075 memset(&payload, 0, sizeof(payload)); 5076 rc = pm8001_tag_alloc(pm8001_ha, &tag); 5077 if (rc) 5078 return -1; 5079 ccb = &pm8001_ha->ccb_info[tag]; 5080 ccb->ccb_tag = tag; 5081 ccb->device = pm8001_dev; 5082 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 5083 payload.tag = cpu_to_le32(tag); 5084 payload.device_id = cpu_to_le32(pm8001_dev->device_id); 5085 payload.nds = cpu_to_le32(state); 5086 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 5087 return rc; 5088 5089 } 5090 5091 static int 5092 pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha) 5093 { 5094 struct sas_re_initialization_req payload; 5095 struct inbound_queue_table *circularQ; 5096 struct pm8001_ccb_info *ccb; 5097 int rc; 5098 u32 tag; 5099 u32 opc = OPC_INB_SAS_RE_INITIALIZE; 5100 memset(&payload, 0, sizeof(payload)); 5101 rc = pm8001_tag_alloc(pm8001_ha, &tag); 5102 if (rc) 5103 return -ENOMEM; 5104 ccb = &pm8001_ha->ccb_info[tag]; 5105 ccb->ccb_tag = tag; 5106 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 5107 payload.tag = cpu_to_le32(tag); 5108 payload.SSAHOLT = cpu_to_le32(0xd << 25); 5109 payload.sata_hol_tmo = cpu_to_le32(80); 5110 payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff); 5111 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 5112 if (rc) 5113 pm8001_tag_free(pm8001_ha, tag); 5114 return rc; 5115 5116 } 5117 5118 const struct pm8001_dispatch pm8001_8001_dispatch = { 5119 .name = "pmc8001", 5120 .chip_init = pm8001_chip_init, 5121 .chip_soft_rst = pm8001_chip_soft_rst, 5122 .chip_rst = pm8001_hw_chip_rst, 5123 .chip_iounmap = pm8001_chip_iounmap, 5124 .isr = pm8001_chip_isr, 5125 .is_our_interrupt = pm8001_chip_is_our_interrupt, 5126 .isr_process_oq = process_oq, 5127 .interrupt_enable = pm8001_chip_interrupt_enable, 5128 .interrupt_disable = pm8001_chip_interrupt_disable, 5129 .make_prd = pm8001_chip_make_sg, 5130 .smp_req = pm8001_chip_smp_req, 5131 .ssp_io_req = pm8001_chip_ssp_io_req, 5132 .sata_req = pm8001_chip_sata_req, 5133 .phy_start_req = pm8001_chip_phy_start_req, 5134 .phy_stop_req = pm8001_chip_phy_stop_req, 5135 .reg_dev_req = pm8001_chip_reg_dev_req, 5136 .dereg_dev_req = pm8001_chip_dereg_dev_req, 5137 .phy_ctl_req = pm8001_chip_phy_ctl_req, 5138 .task_abort = pm8001_chip_abort_task, 5139 .ssp_tm_req = pm8001_chip_ssp_tm_req, 5140 .get_nvmd_req = pm8001_chip_get_nvmd_req, 5141 .set_nvmd_req = pm8001_chip_set_nvmd_req, 5142 .fw_flash_update_req = pm8001_chip_fw_flash_update_req, 5143 .set_dev_state_req = pm8001_chip_set_dev_state_req, 5144 .sas_re_init_req = pm8001_chip_sas_re_initialization, 5145 }; 5146