1 /* 2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 USI Co., Ltd. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 #include <linux/slab.h> 41 #include "pm8001_sas.h" 42 #include "pm8001_hwi.h" 43 #include "pm8001_chips.h" 44 #include "pm8001_ctl.h" 45 46 /** 47 * read_main_config_table - read the configure table and save it. 48 * @pm8001_ha: our hba card information 49 */ 50 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha) 51 { 52 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 53 pm8001_ha->main_cfg_tbl.pm8001_tbl.signature = 54 pm8001_mr32(address, 0x00); 55 pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev = 56 pm8001_mr32(address, 0x04); 57 pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev = 58 pm8001_mr32(address, 0x08); 59 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io = 60 pm8001_mr32(address, 0x0C); 61 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl = 62 pm8001_mr32(address, 0x10); 63 pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag = 64 pm8001_mr32(address, 0x14); 65 pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset = 66 pm8001_mr32(address, 0x18); 67 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset = 68 pm8001_mr32(address, MAIN_IBQ_OFFSET); 69 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset = 70 pm8001_mr32(address, MAIN_OBQ_OFFSET); 71 pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag = 72 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET); 73 74 /* read analog Setting offset from the configuration table */ 75 pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset = 76 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET); 77 78 /* read Error Dump Offset and Length */ 79 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 = 80 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET); 81 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 = 82 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH); 83 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 = 84 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET); 85 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 = 86 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH); 87 } 88 89 /** 90 * read_general_status_table - read the general status table and save it. 91 * @pm8001_ha: our hba card information 92 */ 93 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha) 94 { 95 void __iomem *address = pm8001_ha->general_stat_tbl_addr; 96 pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate = 97 pm8001_mr32(address, 0x00); 98 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0 = 99 pm8001_mr32(address, 0x04); 100 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1 = 101 pm8001_mr32(address, 0x08); 102 pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt = 103 pm8001_mr32(address, 0x0C); 104 pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt = 105 pm8001_mr32(address, 0x10); 106 pm8001_ha->gs_tbl.pm8001_tbl.rsvd = 107 pm8001_mr32(address, 0x14); 108 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0] = 109 pm8001_mr32(address, 0x18); 110 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1] = 111 pm8001_mr32(address, 0x1C); 112 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2] = 113 pm8001_mr32(address, 0x20); 114 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3] = 115 pm8001_mr32(address, 0x24); 116 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4] = 117 pm8001_mr32(address, 0x28); 118 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5] = 119 pm8001_mr32(address, 0x2C); 120 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6] = 121 pm8001_mr32(address, 0x30); 122 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7] = 123 pm8001_mr32(address, 0x34); 124 pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val = 125 pm8001_mr32(address, 0x38); 126 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0] = 127 pm8001_mr32(address, 0x3C); 128 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1] = 129 pm8001_mr32(address, 0x40); 130 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0] = 131 pm8001_mr32(address, 0x44); 132 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1] = 133 pm8001_mr32(address, 0x48); 134 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2] = 135 pm8001_mr32(address, 0x4C); 136 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3] = 137 pm8001_mr32(address, 0x50); 138 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4] = 139 pm8001_mr32(address, 0x54); 140 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5] = 141 pm8001_mr32(address, 0x58); 142 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6] = 143 pm8001_mr32(address, 0x5C); 144 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7] = 145 pm8001_mr32(address, 0x60); 146 } 147 148 /** 149 * read_inbnd_queue_table - read the inbound queue table and save it. 150 * @pm8001_ha: our hba card information 151 */ 152 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 153 { 154 int i; 155 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 156 for (i = 0; i < PM8001_MAX_INB_NUM; i++) { 157 u32 offset = i * 0x20; 158 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 159 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14))); 160 pm8001_ha->inbnd_q_tbl[i].pi_offset = 161 pm8001_mr32(address, (offset + 0x18)); 162 } 163 } 164 165 /** 166 * read_outbnd_queue_table - read the outbound queue table and save it. 167 * @pm8001_ha: our hba card information 168 */ 169 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 170 { 171 int i; 172 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 173 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) { 174 u32 offset = i * 0x24; 175 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 176 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14))); 177 pm8001_ha->outbnd_q_tbl[i].ci_offset = 178 pm8001_mr32(address, (offset + 0x18)); 179 } 180 } 181 182 /** 183 * init_default_table_values - init the default table. 184 * @pm8001_ha: our hba card information 185 */ 186 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha) 187 { 188 int i; 189 u32 offsetib, offsetob; 190 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr; 191 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr; 192 193 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd = 0; 194 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3 = 0; 195 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7 = 0; 196 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3 = 0; 197 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7 = 0; 198 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 = 199 0; 200 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 = 201 0; 202 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0; 203 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0; 204 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0; 205 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0; 206 207 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr = 208 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi; 209 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr = 210 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo; 211 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size = 212 PM8001_EVENT_LOG_SIZE; 213 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option = 0x01; 214 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr = 215 pm8001_ha->memoryMap.region[IOP].phys_addr_hi; 216 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr = 217 pm8001_ha->memoryMap.region[IOP].phys_addr_lo; 218 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size = 219 PM8001_EVENT_LOG_SIZE; 220 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option = 0x01; 221 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt = 0x01; 222 for (i = 0; i < PM8001_MAX_INB_NUM; i++) { 223 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt = 224 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30); 225 pm8001_ha->inbnd_q_tbl[i].upper_base_addr = 226 pm8001_ha->memoryMap.region[IB + i].phys_addr_hi; 227 pm8001_ha->inbnd_q_tbl[i].lower_base_addr = 228 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo; 229 pm8001_ha->inbnd_q_tbl[i].base_virt = 230 (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr; 231 pm8001_ha->inbnd_q_tbl[i].total_length = 232 pm8001_ha->memoryMap.region[IB + i].total_len; 233 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr = 234 pm8001_ha->memoryMap.region[CI + i].phys_addr_hi; 235 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr = 236 pm8001_ha->memoryMap.region[CI + i].phys_addr_lo; 237 pm8001_ha->inbnd_q_tbl[i].ci_virt = 238 pm8001_ha->memoryMap.region[CI + i].virt_ptr; 239 offsetib = i * 0x20; 240 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 241 get_pci_bar_index(pm8001_mr32(addressib, 242 (offsetib + 0x14))); 243 pm8001_ha->inbnd_q_tbl[i].pi_offset = 244 pm8001_mr32(addressib, (offsetib + 0x18)); 245 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0; 246 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0; 247 } 248 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) { 249 pm8001_ha->outbnd_q_tbl[i].element_size_cnt = 250 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30); 251 pm8001_ha->outbnd_q_tbl[i].upper_base_addr = 252 pm8001_ha->memoryMap.region[OB + i].phys_addr_hi; 253 pm8001_ha->outbnd_q_tbl[i].lower_base_addr = 254 pm8001_ha->memoryMap.region[OB + i].phys_addr_lo; 255 pm8001_ha->outbnd_q_tbl[i].base_virt = 256 (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr; 257 pm8001_ha->outbnd_q_tbl[i].total_length = 258 pm8001_ha->memoryMap.region[OB + i].total_len; 259 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr = 260 pm8001_ha->memoryMap.region[PI + i].phys_addr_hi; 261 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr = 262 pm8001_ha->memoryMap.region[PI + i].phys_addr_lo; 263 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = 264 0 | (10 << 16) | (i << 24); 265 pm8001_ha->outbnd_q_tbl[i].pi_virt = 266 pm8001_ha->memoryMap.region[PI + i].virt_ptr; 267 offsetob = i * 0x24; 268 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 269 get_pci_bar_index(pm8001_mr32(addressob, 270 offsetob + 0x14)); 271 pm8001_ha->outbnd_q_tbl[i].ci_offset = 272 pm8001_mr32(addressob, (offsetob + 0x18)); 273 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0; 274 pm8001_ha->outbnd_q_tbl[i].producer_index = 0; 275 } 276 } 277 278 /** 279 * update_main_config_table - update the main default table to the HBA. 280 * @pm8001_ha: our hba card information 281 */ 282 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha) 283 { 284 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 285 pm8001_mw32(address, 0x24, 286 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd); 287 pm8001_mw32(address, 0x28, 288 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3); 289 pm8001_mw32(address, 0x2C, 290 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7); 291 pm8001_mw32(address, 0x30, 292 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3); 293 pm8001_mw32(address, 0x34, 294 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7); 295 pm8001_mw32(address, 0x38, 296 pm8001_ha->main_cfg_tbl.pm8001_tbl. 297 outbound_tgt_ITNexus_event_pid0_3); 298 pm8001_mw32(address, 0x3C, 299 pm8001_ha->main_cfg_tbl.pm8001_tbl. 300 outbound_tgt_ITNexus_event_pid4_7); 301 pm8001_mw32(address, 0x40, 302 pm8001_ha->main_cfg_tbl.pm8001_tbl. 303 outbound_tgt_ssp_event_pid0_3); 304 pm8001_mw32(address, 0x44, 305 pm8001_ha->main_cfg_tbl.pm8001_tbl. 306 outbound_tgt_ssp_event_pid4_7); 307 pm8001_mw32(address, 0x48, 308 pm8001_ha->main_cfg_tbl.pm8001_tbl. 309 outbound_tgt_smp_event_pid0_3); 310 pm8001_mw32(address, 0x4C, 311 pm8001_ha->main_cfg_tbl.pm8001_tbl. 312 outbound_tgt_smp_event_pid4_7); 313 pm8001_mw32(address, 0x50, 314 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr); 315 pm8001_mw32(address, 0x54, 316 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr); 317 pm8001_mw32(address, 0x58, 318 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size); 319 pm8001_mw32(address, 0x5C, 320 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option); 321 pm8001_mw32(address, 0x60, 322 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr); 323 pm8001_mw32(address, 0x64, 324 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr); 325 pm8001_mw32(address, 0x68, 326 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size); 327 pm8001_mw32(address, 0x6C, 328 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option); 329 pm8001_mw32(address, 0x70, 330 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt); 331 } 332 333 /** 334 * update_inbnd_queue_table - update the inbound queue table to the HBA. 335 * @pm8001_ha: our hba card information 336 * @number: entry in the queue 337 */ 338 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 339 int number) 340 { 341 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 342 u16 offset = number * 0x20; 343 pm8001_mw32(address, offset + 0x00, 344 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); 345 pm8001_mw32(address, offset + 0x04, 346 pm8001_ha->inbnd_q_tbl[number].upper_base_addr); 347 pm8001_mw32(address, offset + 0x08, 348 pm8001_ha->inbnd_q_tbl[number].lower_base_addr); 349 pm8001_mw32(address, offset + 0x0C, 350 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr); 351 pm8001_mw32(address, offset + 0x10, 352 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); 353 } 354 355 /** 356 * update_outbnd_queue_table - update the outbound queue table to the HBA. 357 * @pm8001_ha: our hba card information 358 * @number: entry in the queue 359 */ 360 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 361 int number) 362 { 363 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 364 u16 offset = number * 0x24; 365 pm8001_mw32(address, offset + 0x00, 366 pm8001_ha->outbnd_q_tbl[number].element_size_cnt); 367 pm8001_mw32(address, offset + 0x04, 368 pm8001_ha->outbnd_q_tbl[number].upper_base_addr); 369 pm8001_mw32(address, offset + 0x08, 370 pm8001_ha->outbnd_q_tbl[number].lower_base_addr); 371 pm8001_mw32(address, offset + 0x0C, 372 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr); 373 pm8001_mw32(address, offset + 0x10, 374 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); 375 pm8001_mw32(address, offset + 0x1C, 376 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay); 377 } 378 379 /** 380 * pm8001_bar4_shift - function is called to shift BAR base address 381 * @pm8001_ha : our hba card infomation 382 * @shiftValue : shifting value in memory bar. 383 */ 384 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue) 385 { 386 u32 regVal; 387 unsigned long start; 388 389 /* program the inbound AXI translation Lower Address */ 390 pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue); 391 392 /* confirm the setting is written */ 393 start = jiffies + HZ; /* 1 sec */ 394 do { 395 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW); 396 } while ((regVal != shiftValue) && time_before(jiffies, start)); 397 398 if (regVal != shiftValue) { 399 PM8001_INIT_DBG(pm8001_ha, 400 pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW" 401 " = 0x%x\n", regVal)); 402 return -1; 403 } 404 return 0; 405 } 406 407 /** 408 * mpi_set_phys_g3_with_ssc 409 * @pm8001_ha: our hba card information 410 * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc. 411 */ 412 static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha, 413 u32 SSCbit) 414 { 415 u32 value, offset, i; 416 unsigned long flags; 417 418 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000 419 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000 420 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074 421 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074 422 #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12 423 #define PHY_G3_WITH_SSC_BIT_SHIFT 13 424 #define SNW3_PHY_CAPABILITIES_PARITY 31 425 426 /* 427 * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3) 428 * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7) 429 */ 430 spin_lock_irqsave(&pm8001_ha->lock, flags); 431 if (-1 == pm8001_bar4_shift(pm8001_ha, 432 SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) { 433 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 434 return; 435 } 436 437 for (i = 0; i < 4; i++) { 438 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i; 439 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501); 440 } 441 /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */ 442 if (-1 == pm8001_bar4_shift(pm8001_ha, 443 SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) { 444 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 445 return; 446 } 447 for (i = 4; i < 8; i++) { 448 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4); 449 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501); 450 } 451 /************************************************************* 452 Change the SSC upspreading value to 0x0 so that upspreading is disabled. 453 Device MABC SMOD0 Controls 454 Address: (via MEMBASE-III): 455 Using shifted destination address 0x0_0000: with Offset 0xD8 456 457 31:28 R/W Reserved Do not change 458 27:24 R/W SAS_SMOD_SPRDUP 0000 459 23:20 R/W SAS_SMOD_SPRDDN 0000 460 19:0 R/W Reserved Do not change 461 Upon power-up this register will read as 0x8990c016, 462 and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000 463 so that the written value will be 0x8090c016. 464 This will ensure only down-spreading SSC is enabled on the SPC. 465 *************************************************************/ 466 value = pm8001_cr32(pm8001_ha, 2, 0xd8); 467 pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016); 468 469 /*set the shifted destination address to 0x0 to avoid error operation */ 470 pm8001_bar4_shift(pm8001_ha, 0x0); 471 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 472 return; 473 } 474 475 /** 476 * mpi_set_open_retry_interval_reg 477 * @pm8001_ha: our hba card information 478 * @interval: interval time for each OPEN_REJECT (RETRY). The units are in 1us. 479 */ 480 static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha, 481 u32 interval) 482 { 483 u32 offset; 484 u32 value; 485 u32 i; 486 unsigned long flags; 487 488 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000 489 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000 490 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4 491 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4 492 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF 493 494 value = interval & OPEN_RETRY_INTERVAL_REG_MASK; 495 spin_lock_irqsave(&pm8001_ha->lock, flags); 496 /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/ 497 if (-1 == pm8001_bar4_shift(pm8001_ha, 498 OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) { 499 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 500 return; 501 } 502 for (i = 0; i < 4; i++) { 503 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i; 504 pm8001_cw32(pm8001_ha, 2, offset, value); 505 } 506 507 if (-1 == pm8001_bar4_shift(pm8001_ha, 508 OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) { 509 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 510 return; 511 } 512 for (i = 4; i < 8; i++) { 513 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4); 514 pm8001_cw32(pm8001_ha, 2, offset, value); 515 } 516 /*set the shifted destination address to 0x0 to avoid error operation */ 517 pm8001_bar4_shift(pm8001_ha, 0x0); 518 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 519 return; 520 } 521 522 /** 523 * mpi_init_check - check firmware initialization status. 524 * @pm8001_ha: our hba card information 525 */ 526 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha) 527 { 528 u32 max_wait_count; 529 u32 value; 530 u32 gst_len_mpistate; 531 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the 532 table is updated */ 533 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE); 534 /* wait until Inbound DoorBell Clear Register toggled */ 535 max_wait_count = 1 * 1000 * 1000;/* 1 sec */ 536 do { 537 udelay(1); 538 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 539 value &= SPC_MSGU_CFG_TABLE_UPDATE; 540 } while ((value != 0) && (--max_wait_count)); 541 542 if (!max_wait_count) 543 return -1; 544 /* check the MPI-State for initialization */ 545 gst_len_mpistate = 546 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 547 GST_GSTLEN_MPIS_OFFSET); 548 if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK)) 549 return -1; 550 /* check MPI Initialization error */ 551 gst_len_mpistate = gst_len_mpistate >> 16; 552 if (0x0000 != gst_len_mpistate) 553 return -1; 554 return 0; 555 } 556 557 /** 558 * check_fw_ready - The LLDD check if the FW is ready, if not, return error. 559 * @pm8001_ha: our hba card information 560 */ 561 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha) 562 { 563 u32 value, value1; 564 u32 max_wait_count; 565 /* check error state */ 566 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 567 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 568 /* check AAP error */ 569 if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) { 570 /* error state */ 571 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 572 return -1; 573 } 574 575 /* check IOP error */ 576 if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) { 577 /* error state */ 578 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 579 return -1; 580 } 581 582 /* bit 4-31 of scratch pad1 should be zeros if it is not 583 in error state*/ 584 if (value & SCRATCH_PAD1_STATE_MASK) { 585 /* error case */ 586 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 587 return -1; 588 } 589 590 /* bit 2, 4-31 of scratch pad2 should be zeros if it is not 591 in error state */ 592 if (value1 & SCRATCH_PAD2_STATE_MASK) { 593 /* error case */ 594 return -1; 595 } 596 597 max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */ 598 599 /* wait until scratch pad 1 and 2 registers in ready state */ 600 do { 601 udelay(1); 602 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) 603 & SCRATCH_PAD1_RDY; 604 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) 605 & SCRATCH_PAD2_RDY; 606 if ((--max_wait_count) == 0) 607 return -1; 608 } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY)); 609 return 0; 610 } 611 612 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha) 613 { 614 void __iomem *base_addr; 615 u32 value; 616 u32 offset; 617 u32 pcibar; 618 u32 pcilogic; 619 620 value = pm8001_cr32(pm8001_ha, 0, 0x44); 621 offset = value & 0x03FFFFFF; 622 PM8001_INIT_DBG(pm8001_ha, 623 pm8001_printk("Scratchpad 0 Offset: %x\n", offset)); 624 pcilogic = (value & 0xFC000000) >> 26; 625 pcibar = get_pci_bar_index(pcilogic); 626 PM8001_INIT_DBG(pm8001_ha, 627 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar)); 628 pm8001_ha->main_cfg_tbl_addr = base_addr = 629 pm8001_ha->io_mem[pcibar].memvirtaddr + offset; 630 pm8001_ha->general_stat_tbl_addr = 631 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18); 632 pm8001_ha->inbnd_q_tbl_addr = 633 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C); 634 pm8001_ha->outbnd_q_tbl_addr = 635 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20); 636 } 637 638 /** 639 * pm8001_chip_init - the main init function that initialize whole PM8001 chip. 640 * @pm8001_ha: our hba card information 641 */ 642 static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha) 643 { 644 u8 i = 0; 645 u16 deviceid; 646 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid); 647 /* 8081 controllers need BAR shift to access MPI space 648 * as this is shared with BIOS data */ 649 if (deviceid == 0x8081 || deviceid == 0x0042) { 650 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) { 651 PM8001_FAIL_DBG(pm8001_ha, 652 pm8001_printk("Shift Bar4 to 0x%x failed\n", 653 GSM_SM_BASE)); 654 return -1; 655 } 656 } 657 /* check the firmware status */ 658 if (-1 == check_fw_ready(pm8001_ha)) { 659 PM8001_FAIL_DBG(pm8001_ha, 660 pm8001_printk("Firmware is not ready!\n")); 661 return -EBUSY; 662 } 663 664 /* Initialize pci space address eg: mpi offset */ 665 init_pci_device_addresses(pm8001_ha); 666 init_default_table_values(pm8001_ha); 667 read_main_config_table(pm8001_ha); 668 read_general_status_table(pm8001_ha); 669 read_inbnd_queue_table(pm8001_ha); 670 read_outbnd_queue_table(pm8001_ha); 671 /* update main config table ,inbound table and outbound table */ 672 update_main_config_table(pm8001_ha); 673 for (i = 0; i < PM8001_MAX_INB_NUM; i++) 674 update_inbnd_queue_table(pm8001_ha, i); 675 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) 676 update_outbnd_queue_table(pm8001_ha, i); 677 /* 8081 controller donot require these operations */ 678 if (deviceid != 0x8081 && deviceid != 0x0042) { 679 mpi_set_phys_g3_with_ssc(pm8001_ha, 0); 680 /* 7->130ms, 34->500ms, 119->1.5s */ 681 mpi_set_open_retry_interval_reg(pm8001_ha, 119); 682 } 683 /* notify firmware update finished and check initialization status */ 684 if (0 == mpi_init_check(pm8001_ha)) { 685 PM8001_INIT_DBG(pm8001_ha, 686 pm8001_printk("MPI initialize successful!\n")); 687 } else 688 return -EBUSY; 689 /*This register is a 16-bit timer with a resolution of 1us. This is the 690 timer used for interrupt delay/coalescing in the PCIe Application Layer. 691 Zero is not a valid value. A value of 1 in the register will cause the 692 interrupts to be normal. A value greater than 1 will cause coalescing 693 delays.*/ 694 pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1); 695 pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0); 696 return 0; 697 } 698 699 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha) 700 { 701 u32 max_wait_count; 702 u32 value; 703 u32 gst_len_mpistate; 704 u16 deviceid; 705 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid); 706 if (deviceid == 0x8081 || deviceid == 0x0042) { 707 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) { 708 PM8001_FAIL_DBG(pm8001_ha, 709 pm8001_printk("Shift Bar4 to 0x%x failed\n", 710 GSM_SM_BASE)); 711 return -1; 712 } 713 } 714 init_pci_device_addresses(pm8001_ha); 715 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the 716 table is stop */ 717 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET); 718 719 /* wait until Inbound DoorBell Clear Register toggled */ 720 max_wait_count = 1 * 1000 * 1000;/* 1 sec */ 721 do { 722 udelay(1); 723 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 724 value &= SPC_MSGU_CFG_TABLE_RESET; 725 } while ((value != 0) && (--max_wait_count)); 726 727 if (!max_wait_count) { 728 PM8001_FAIL_DBG(pm8001_ha, 729 pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value)); 730 return -1; 731 } 732 733 /* check the MPI-State for termination in progress */ 734 /* wait until Inbound DoorBell Clear Register toggled */ 735 max_wait_count = 1 * 1000 * 1000; /* 1 sec */ 736 do { 737 udelay(1); 738 gst_len_mpistate = 739 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 740 GST_GSTLEN_MPIS_OFFSET); 741 if (GST_MPI_STATE_UNINIT == 742 (gst_len_mpistate & GST_MPI_STATE_MASK)) 743 break; 744 } while (--max_wait_count); 745 if (!max_wait_count) { 746 PM8001_FAIL_DBG(pm8001_ha, 747 pm8001_printk(" TIME OUT MPI State = 0x%x\n", 748 gst_len_mpistate & GST_MPI_STATE_MASK)); 749 return -1; 750 } 751 return 0; 752 } 753 754 /** 755 * soft_reset_ready_check - Function to check FW is ready for soft reset. 756 * @pm8001_ha: our hba card information 757 */ 758 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha) 759 { 760 u32 regVal, regVal1, regVal2; 761 if (mpi_uninit_check(pm8001_ha) != 0) { 762 PM8001_FAIL_DBG(pm8001_ha, 763 pm8001_printk("MPI state is not ready\n")); 764 return -1; 765 } 766 /* read the scratch pad 2 register bit 2 */ 767 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) 768 & SCRATCH_PAD2_FWRDY_RST; 769 if (regVal == SCRATCH_PAD2_FWRDY_RST) { 770 PM8001_INIT_DBG(pm8001_ha, 771 pm8001_printk("Firmware is ready for reset .\n")); 772 } else { 773 unsigned long flags; 774 /* Trigger NMI twice via RB6 */ 775 spin_lock_irqsave(&pm8001_ha->lock, flags); 776 if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) { 777 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 778 PM8001_FAIL_DBG(pm8001_ha, 779 pm8001_printk("Shift Bar4 to 0x%x failed\n", 780 RB6_ACCESS_REG)); 781 return -1; 782 } 783 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, 784 RB6_MAGIC_NUMBER_RST); 785 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST); 786 /* wait for 100 ms */ 787 mdelay(100); 788 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) & 789 SCRATCH_PAD2_FWRDY_RST; 790 if (regVal != SCRATCH_PAD2_FWRDY_RST) { 791 regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 792 regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 793 PM8001_FAIL_DBG(pm8001_ha, 794 pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1" 795 "=0x%x, MSGU_SCRATCH_PAD2=0x%x\n", 796 regVal1, regVal2)); 797 PM8001_FAIL_DBG(pm8001_ha, 798 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n", 799 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0))); 800 PM8001_FAIL_DBG(pm8001_ha, 801 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n", 802 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3))); 803 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 804 return -1; 805 } 806 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 807 } 808 return 0; 809 } 810 811 /** 812 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all 813 * the FW register status to the originated status. 814 * @pm8001_ha: our hba card information 815 */ 816 static int 817 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha) 818 { 819 u32 regVal, toggleVal; 820 u32 max_wait_count; 821 u32 regVal1, regVal2, regVal3; 822 u32 signature = 0x252acbcd; /* for host scratch pad0 */ 823 unsigned long flags; 824 825 /* step1: Check FW is ready for soft reset */ 826 if (soft_reset_ready_check(pm8001_ha) != 0) { 827 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("FW is not ready\n")); 828 return -1; 829 } 830 831 /* step 2: clear NMI status register on AAP1 and IOP, write the same 832 value to clear */ 833 /* map 0x60000 to BAR4(0x20), BAR2(win) */ 834 spin_lock_irqsave(&pm8001_ha->lock, flags); 835 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) { 836 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 837 PM8001_FAIL_DBG(pm8001_ha, 838 pm8001_printk("Shift Bar4 to 0x%x failed\n", 839 MBIC_AAP1_ADDR_BASE)); 840 return -1; 841 } 842 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP); 843 PM8001_INIT_DBG(pm8001_ha, 844 pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal)); 845 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0); 846 /* map 0x70000 to BAR4(0x20), BAR2(win) */ 847 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) { 848 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 849 PM8001_FAIL_DBG(pm8001_ha, 850 pm8001_printk("Shift Bar4 to 0x%x failed\n", 851 MBIC_IOP_ADDR_BASE)); 852 return -1; 853 } 854 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1); 855 PM8001_INIT_DBG(pm8001_ha, 856 pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal)); 857 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0); 858 859 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE); 860 PM8001_INIT_DBG(pm8001_ha, 861 pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal)); 862 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0); 863 864 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT); 865 PM8001_INIT_DBG(pm8001_ha, 866 pm8001_printk("PCIE - Event Interrupt = 0x%x\n", regVal)); 867 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal); 868 869 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE); 870 PM8001_INIT_DBG(pm8001_ha, 871 pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal)); 872 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0); 873 874 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT); 875 PM8001_INIT_DBG(pm8001_ha, 876 pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal)); 877 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal); 878 879 /* read the scratch pad 1 register bit 2 */ 880 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) 881 & SCRATCH_PAD1_RST; 882 toggleVal = regVal ^ SCRATCH_PAD1_RST; 883 884 /* set signature in host scratch pad0 register to tell SPC that the 885 host performs the soft reset */ 886 pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature); 887 888 /* read required registers for confirmming */ 889 /* map 0x0700000 to BAR4(0x20), BAR2(win) */ 890 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) { 891 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 892 PM8001_FAIL_DBG(pm8001_ha, 893 pm8001_printk("Shift Bar4 to 0x%x failed\n", 894 GSM_ADDR_BASE)); 895 return -1; 896 } 897 PM8001_INIT_DBG(pm8001_ha, 898 pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and" 899 " Reset = 0x%x\n", 900 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); 901 902 /* step 3: host read GSM Configuration and Reset register */ 903 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); 904 /* Put those bits to low */ 905 /* GSM XCBI offset = 0x70 0000 906 0x00 Bit 13 COM_SLV_SW_RSTB 1 907 0x00 Bit 12 QSSP_SW_RSTB 1 908 0x00 Bit 11 RAAE_SW_RSTB 1 909 0x00 Bit 9 RB_1_SW_RSTB 1 910 0x00 Bit 8 SM_SW_RSTB 1 911 */ 912 regVal &= ~(0x00003b00); 913 /* host write GSM Configuration and Reset register */ 914 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); 915 PM8001_INIT_DBG(pm8001_ha, 916 pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM " 917 "Configuration and Reset is set to = 0x%x\n", 918 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); 919 920 /* step 4: */ 921 /* disable GSM - Read Address Parity Check */ 922 regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK); 923 PM8001_INIT_DBG(pm8001_ha, 924 pm8001_printk("GSM 0x700038 - Read Address Parity Check " 925 "Enable = 0x%x\n", regVal1)); 926 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0); 927 PM8001_INIT_DBG(pm8001_ha, 928 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable" 929 "is set to = 0x%x\n", 930 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK))); 931 932 /* disable GSM - Write Address Parity Check */ 933 regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK); 934 PM8001_INIT_DBG(pm8001_ha, 935 pm8001_printk("GSM 0x700040 - Write Address Parity Check" 936 " Enable = 0x%x\n", regVal2)); 937 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0); 938 PM8001_INIT_DBG(pm8001_ha, 939 pm8001_printk("GSM 0x700040 - Write Address Parity Check " 940 "Enable is set to = 0x%x\n", 941 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK))); 942 943 /* disable GSM - Write Data Parity Check */ 944 regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK); 945 PM8001_INIT_DBG(pm8001_ha, 946 pm8001_printk("GSM 0x300048 - Write Data Parity Check" 947 " Enable = 0x%x\n", regVal3)); 948 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0); 949 PM8001_INIT_DBG(pm8001_ha, 950 pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable" 951 "is set to = 0x%x\n", 952 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK))); 953 954 /* step 5: delay 10 usec */ 955 udelay(10); 956 /* step 5-b: set GPIO-0 output control to tristate anyway */ 957 if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) { 958 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 959 PM8001_INIT_DBG(pm8001_ha, 960 pm8001_printk("Shift Bar4 to 0x%x failed\n", 961 GPIO_ADDR_BASE)); 962 return -1; 963 } 964 regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET); 965 PM8001_INIT_DBG(pm8001_ha, 966 pm8001_printk("GPIO Output Control Register:" 967 " = 0x%x\n", regVal)); 968 /* set GPIO-0 output control to tri-state */ 969 regVal &= 0xFFFFFFFC; 970 pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal); 971 972 /* Step 6: Reset the IOP and AAP1 */ 973 /* map 0x00000 to BAR4(0x20), BAR2(win) */ 974 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) { 975 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 976 PM8001_FAIL_DBG(pm8001_ha, 977 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n", 978 SPC_TOP_LEVEL_ADDR_BASE)); 979 return -1; 980 } 981 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 982 PM8001_INIT_DBG(pm8001_ha, 983 pm8001_printk("Top Register before resetting IOP/AAP1" 984 ":= 0x%x\n", regVal)); 985 regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS); 986 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 987 988 /* step 7: Reset the BDMA/OSSP */ 989 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 990 PM8001_INIT_DBG(pm8001_ha, 991 pm8001_printk("Top Register before resetting BDMA/OSSP" 992 ": = 0x%x\n", regVal)); 993 regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP); 994 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 995 996 /* step 8: delay 10 usec */ 997 udelay(10); 998 999 /* step 9: bring the BDMA and OSSP out of reset */ 1000 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 1001 PM8001_INIT_DBG(pm8001_ha, 1002 pm8001_printk("Top Register before bringing up BDMA/OSSP" 1003 ":= 0x%x\n", regVal)); 1004 regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP); 1005 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 1006 1007 /* step 10: delay 10 usec */ 1008 udelay(10); 1009 1010 /* step 11: reads and sets the GSM Configuration and Reset Register */ 1011 /* map 0x0700000 to BAR4(0x20), BAR2(win) */ 1012 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) { 1013 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1014 PM8001_FAIL_DBG(pm8001_ha, 1015 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n", 1016 GSM_ADDR_BASE)); 1017 return -1; 1018 } 1019 PM8001_INIT_DBG(pm8001_ha, 1020 pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and " 1021 "Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); 1022 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); 1023 /* Put those bits to high */ 1024 /* GSM XCBI offset = 0x70 0000 1025 0x00 Bit 13 COM_SLV_SW_RSTB 1 1026 0x00 Bit 12 QSSP_SW_RSTB 1 1027 0x00 Bit 11 RAAE_SW_RSTB 1 1028 0x00 Bit 9 RB_1_SW_RSTB 1 1029 0x00 Bit 8 SM_SW_RSTB 1 1030 */ 1031 regVal |= (GSM_CONFIG_RESET_VALUE); 1032 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); 1033 PM8001_INIT_DBG(pm8001_ha, 1034 pm8001_printk("GSM (0x00004088 ==> 0x00007b88) - GSM" 1035 " Configuration and Reset is set to = 0x%x\n", 1036 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); 1037 1038 /* step 12: Restore GSM - Read Address Parity Check */ 1039 regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK); 1040 /* just for debugging */ 1041 PM8001_INIT_DBG(pm8001_ha, 1042 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable" 1043 " = 0x%x\n", regVal)); 1044 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1); 1045 PM8001_INIT_DBG(pm8001_ha, 1046 pm8001_printk("GSM 0x700038 - Read Address Parity" 1047 " Check Enable is set to = 0x%x\n", 1048 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK))); 1049 /* Restore GSM - Write Address Parity Check */ 1050 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK); 1051 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2); 1052 PM8001_INIT_DBG(pm8001_ha, 1053 pm8001_printk("GSM 0x700040 - Write Address Parity Check" 1054 " Enable is set to = 0x%x\n", 1055 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK))); 1056 /* Restore GSM - Write Data Parity Check */ 1057 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK); 1058 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3); 1059 PM8001_INIT_DBG(pm8001_ha, 1060 pm8001_printk("GSM 0x700048 - Write Data Parity Check Enable" 1061 "is set to = 0x%x\n", 1062 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK))); 1063 1064 /* step 13: bring the IOP and AAP1 out of reset */ 1065 /* map 0x00000 to BAR4(0x20), BAR2(win) */ 1066 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) { 1067 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1068 PM8001_FAIL_DBG(pm8001_ha, 1069 pm8001_printk("Shift Bar4 to 0x%x failed\n", 1070 SPC_TOP_LEVEL_ADDR_BASE)); 1071 return -1; 1072 } 1073 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 1074 regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS); 1075 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 1076 1077 /* step 14: delay 10 usec - Normal Mode */ 1078 udelay(10); 1079 /* check Soft Reset Normal mode or Soft Reset HDA mode */ 1080 if (signature == SPC_SOFT_RESET_SIGNATURE) { 1081 /* step 15 (Normal Mode): wait until scratch pad1 register 1082 bit 2 toggled */ 1083 max_wait_count = 2 * 1000 * 1000;/* 2 sec */ 1084 do { 1085 udelay(1); 1086 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) & 1087 SCRATCH_PAD1_RST; 1088 } while ((regVal != toggleVal) && (--max_wait_count)); 1089 1090 if (!max_wait_count) { 1091 regVal = pm8001_cr32(pm8001_ha, 0, 1092 MSGU_SCRATCH_PAD_1); 1093 PM8001_FAIL_DBG(pm8001_ha, 1094 pm8001_printk("TIMEOUT : ToggleVal 0x%x," 1095 "MSGU_SCRATCH_PAD1 = 0x%x\n", 1096 toggleVal, regVal)); 1097 PM8001_FAIL_DBG(pm8001_ha, 1098 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n", 1099 pm8001_cr32(pm8001_ha, 0, 1100 MSGU_SCRATCH_PAD_0))); 1101 PM8001_FAIL_DBG(pm8001_ha, 1102 pm8001_printk("SCRATCH_PAD2 value = 0x%x\n", 1103 pm8001_cr32(pm8001_ha, 0, 1104 MSGU_SCRATCH_PAD_2))); 1105 PM8001_FAIL_DBG(pm8001_ha, 1106 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n", 1107 pm8001_cr32(pm8001_ha, 0, 1108 MSGU_SCRATCH_PAD_3))); 1109 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1110 return -1; 1111 } 1112 1113 /* step 16 (Normal) - Clear ODMR and ODCR */ 1114 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); 1115 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); 1116 1117 /* step 17 (Normal Mode): wait for the FW and IOP to get 1118 ready - 1 sec timeout */ 1119 /* Wait for the SPC Configuration Table to be ready */ 1120 if (check_fw_ready(pm8001_ha) == -1) { 1121 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1122 /* return error if MPI Configuration Table not ready */ 1123 PM8001_INIT_DBG(pm8001_ha, 1124 pm8001_printk("FW not ready SCRATCH_PAD1" 1125 " = 0x%x\n", regVal)); 1126 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 1127 /* return error if MPI Configuration Table not ready */ 1128 PM8001_INIT_DBG(pm8001_ha, 1129 pm8001_printk("FW not ready SCRATCH_PAD2" 1130 " = 0x%x\n", regVal)); 1131 PM8001_INIT_DBG(pm8001_ha, 1132 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n", 1133 pm8001_cr32(pm8001_ha, 0, 1134 MSGU_SCRATCH_PAD_0))); 1135 PM8001_INIT_DBG(pm8001_ha, 1136 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n", 1137 pm8001_cr32(pm8001_ha, 0, 1138 MSGU_SCRATCH_PAD_3))); 1139 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1140 return -1; 1141 } 1142 } 1143 pm8001_bar4_shift(pm8001_ha, 0); 1144 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1145 1146 PM8001_INIT_DBG(pm8001_ha, 1147 pm8001_printk("SPC soft reset Complete\n")); 1148 return 0; 1149 } 1150 1151 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha) 1152 { 1153 u32 i; 1154 u32 regVal; 1155 PM8001_INIT_DBG(pm8001_ha, 1156 pm8001_printk("chip reset start\n")); 1157 1158 /* do SPC chip reset. */ 1159 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); 1160 regVal &= ~(SPC_REG_RESET_DEVICE); 1161 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); 1162 1163 /* delay 10 usec */ 1164 udelay(10); 1165 1166 /* bring chip reset out of reset */ 1167 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); 1168 regVal |= SPC_REG_RESET_DEVICE; 1169 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); 1170 1171 /* delay 10 usec */ 1172 udelay(10); 1173 1174 /* wait for 20 msec until the firmware gets reloaded */ 1175 i = 20; 1176 do { 1177 mdelay(1); 1178 } while ((--i) != 0); 1179 1180 PM8001_INIT_DBG(pm8001_ha, 1181 pm8001_printk("chip reset finished\n")); 1182 } 1183 1184 /** 1185 * pm8001_chip_iounmap - which maped when initialized. 1186 * @pm8001_ha: our hba card information 1187 */ 1188 void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha) 1189 { 1190 s8 bar, logical = 0; 1191 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { 1192 /* 1193 ** logical BARs for SPC: 1194 ** bar 0 and 1 - logical BAR0 1195 ** bar 2 and 3 - logical BAR1 1196 ** bar4 - logical BAR2 1197 ** bar5 - logical BAR3 1198 ** Skip the appropriate assignments: 1199 */ 1200 if ((bar == 1) || (bar == 3)) 1201 continue; 1202 if (pm8001_ha->io_mem[logical].memvirtaddr) { 1203 iounmap(pm8001_ha->io_mem[logical].memvirtaddr); 1204 logical++; 1205 } 1206 } 1207 } 1208 1209 #ifndef PM8001_USE_MSIX 1210 /** 1211 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt 1212 * @pm8001_ha: our hba card information 1213 */ 1214 static void 1215 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha) 1216 { 1217 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); 1218 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); 1219 } 1220 1221 /** 1222 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt 1223 * @pm8001_ha: our hba card information 1224 */ 1225 static void 1226 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha) 1227 { 1228 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL); 1229 } 1230 1231 #else 1232 1233 /** 1234 * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt 1235 * @pm8001_ha: our hba card information 1236 * @int_vec_idx: interrupt number to enable 1237 */ 1238 static void 1239 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha, 1240 u32 int_vec_idx) 1241 { 1242 u32 msi_index; 1243 u32 value; 1244 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE; 1245 msi_index += MSIX_TABLE_BASE; 1246 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE); 1247 value = (1 << int_vec_idx); 1248 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, value); 1249 1250 } 1251 1252 /** 1253 * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt 1254 * @pm8001_ha: our hba card information 1255 * @int_vec_idx: interrupt number to disable 1256 */ 1257 static void 1258 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha, 1259 u32 int_vec_idx) 1260 { 1261 u32 msi_index; 1262 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE; 1263 msi_index += MSIX_TABLE_BASE; 1264 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE); 1265 } 1266 #endif 1267 1268 /** 1269 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt 1270 * @pm8001_ha: our hba card information 1271 * @vec: unused 1272 */ 1273 static void 1274 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1275 { 1276 #ifdef PM8001_USE_MSIX 1277 pm8001_chip_msix_interrupt_enable(pm8001_ha, 0); 1278 #else 1279 pm8001_chip_intx_interrupt_enable(pm8001_ha); 1280 #endif 1281 } 1282 1283 /** 1284 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt 1285 * @pm8001_ha: our hba card information 1286 * @vec: unused 1287 */ 1288 static void 1289 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1290 { 1291 #ifdef PM8001_USE_MSIX 1292 pm8001_chip_msix_interrupt_disable(pm8001_ha, 0); 1293 #else 1294 pm8001_chip_intx_interrupt_disable(pm8001_ha); 1295 #endif 1296 } 1297 1298 /** 1299 * pm8001_mpi_msg_free_get - get the free message buffer for transfer 1300 * inbound queue. 1301 * @circularQ: the inbound queue we want to transfer to HBA. 1302 * @messageSize: the message size of this transfer, normally it is 64 bytes 1303 * @messagePtr: the pointer to message. 1304 */ 1305 int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ, 1306 u16 messageSize, void **messagePtr) 1307 { 1308 u32 offset, consumer_index; 1309 struct mpi_msg_hdr *msgHeader; 1310 u8 bcCount = 1; /* only support single buffer */ 1311 1312 /* Checks is the requested message size can be allocated in this queue*/ 1313 if (messageSize > IOMB_SIZE_SPCV) { 1314 *messagePtr = NULL; 1315 return -1; 1316 } 1317 1318 /* Stores the new consumer index */ 1319 consumer_index = pm8001_read_32(circularQ->ci_virt); 1320 circularQ->consumer_index = cpu_to_le32(consumer_index); 1321 if (((circularQ->producer_idx + bcCount) % PM8001_MPI_QUEUE) == 1322 le32_to_cpu(circularQ->consumer_index)) { 1323 *messagePtr = NULL; 1324 return -1; 1325 } 1326 /* get memory IOMB buffer address */ 1327 offset = circularQ->producer_idx * messageSize; 1328 /* increment to next bcCount element */ 1329 circularQ->producer_idx = (circularQ->producer_idx + bcCount) 1330 % PM8001_MPI_QUEUE; 1331 /* Adds that distance to the base of the region virtual address plus 1332 the message header size*/ 1333 msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset); 1334 *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr); 1335 return 0; 1336 } 1337 1338 /** 1339 * pm8001_mpi_build_cmd- build the message queue for transfer, update the PI to 1340 * FW to tell the fw to get this message from IOMB. 1341 * @pm8001_ha: our hba card information 1342 * @circularQ: the inbound queue we want to transfer to HBA. 1343 * @opCode: the operation code represents commands which LLDD and fw recognized. 1344 * @payload: the command payload of each operation command. 1345 * @nb: size in bytes of the command payload 1346 * @responseQueue: queue to interrupt on w/ command response (if any) 1347 */ 1348 int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha, 1349 struct inbound_queue_table *circularQ, 1350 u32 opCode, void *payload, size_t nb, 1351 u32 responseQueue) 1352 { 1353 u32 Header = 0, hpriority = 0, bc = 1, category = 0x02; 1354 void *pMessage; 1355 1356 if (pm8001_mpi_msg_free_get(circularQ, pm8001_ha->iomb_size, 1357 &pMessage) < 0) { 1358 PM8001_IO_DBG(pm8001_ha, 1359 pm8001_printk("No free mpi buffer\n")); 1360 return -ENOMEM; 1361 } 1362 1363 if (nb > (pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr))) 1364 nb = pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr); 1365 memcpy(pMessage, payload, nb); 1366 if (nb + sizeof(struct mpi_msg_hdr) < pm8001_ha->iomb_size) 1367 memset(pMessage + nb, 0, pm8001_ha->iomb_size - 1368 (nb + sizeof(struct mpi_msg_hdr))); 1369 1370 /*Build the header*/ 1371 Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24) 1372 | ((responseQueue & 0x3F) << 16) 1373 | ((category & 0xF) << 12) | (opCode & 0xFFF)); 1374 1375 pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header)); 1376 /*Update the PI to the firmware*/ 1377 pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar, 1378 circularQ->pi_offset, circularQ->producer_idx); 1379 PM8001_DEVIO_DBG(pm8001_ha, 1380 pm8001_printk("INB Q %x OPCODE:%x , UPDATED PI=%d CI=%d\n", 1381 responseQueue, opCode, circularQ->producer_idx, 1382 circularQ->consumer_index)); 1383 return 0; 1384 } 1385 1386 u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg, 1387 struct outbound_queue_table *circularQ, u8 bc) 1388 { 1389 u32 producer_index; 1390 struct mpi_msg_hdr *msgHeader; 1391 struct mpi_msg_hdr *pOutBoundMsgHeader; 1392 1393 msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr)); 1394 pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + 1395 circularQ->consumer_idx * pm8001_ha->iomb_size); 1396 if (pOutBoundMsgHeader != msgHeader) { 1397 PM8001_FAIL_DBG(pm8001_ha, 1398 pm8001_printk("consumer_idx = %d msgHeader = %p\n", 1399 circularQ->consumer_idx, msgHeader)); 1400 1401 /* Update the producer index from SPC */ 1402 producer_index = pm8001_read_32(circularQ->pi_virt); 1403 circularQ->producer_index = cpu_to_le32(producer_index); 1404 PM8001_FAIL_DBG(pm8001_ha, 1405 pm8001_printk("consumer_idx = %d producer_index = %d" 1406 "msgHeader = %p\n", circularQ->consumer_idx, 1407 circularQ->producer_index, msgHeader)); 1408 return 0; 1409 } 1410 /* free the circular queue buffer elements associated with the message*/ 1411 circularQ->consumer_idx = (circularQ->consumer_idx + bc) 1412 % PM8001_MPI_QUEUE; 1413 /* update the CI of outbound queue */ 1414 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset, 1415 circularQ->consumer_idx); 1416 /* Update the producer index from SPC*/ 1417 producer_index = pm8001_read_32(circularQ->pi_virt); 1418 circularQ->producer_index = cpu_to_le32(producer_index); 1419 PM8001_IO_DBG(pm8001_ha, 1420 pm8001_printk(" CI=%d PI=%d\n", circularQ->consumer_idx, 1421 circularQ->producer_index)); 1422 return 0; 1423 } 1424 1425 /** 1426 * pm8001_mpi_msg_consume- get the MPI message from outbound queue 1427 * message table. 1428 * @pm8001_ha: our hba card information 1429 * @circularQ: the outbound queue table. 1430 * @messagePtr1: the message contents of this outbound message. 1431 * @pBC: the message size. 1432 */ 1433 u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha, 1434 struct outbound_queue_table *circularQ, 1435 void **messagePtr1, u8 *pBC) 1436 { 1437 struct mpi_msg_hdr *msgHeader; 1438 __le32 msgHeader_tmp; 1439 u32 header_tmp; 1440 do { 1441 /* If there are not-yet-delivered messages ... */ 1442 if (le32_to_cpu(circularQ->producer_index) 1443 != circularQ->consumer_idx) { 1444 /*Get the pointer to the circular queue buffer element*/ 1445 msgHeader = (struct mpi_msg_hdr *) 1446 (circularQ->base_virt + 1447 circularQ->consumer_idx * pm8001_ha->iomb_size); 1448 /* read header */ 1449 header_tmp = pm8001_read_32(msgHeader); 1450 msgHeader_tmp = cpu_to_le32(header_tmp); 1451 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk( 1452 "outbound opcode msgheader:%x ci=%d pi=%d\n", 1453 msgHeader_tmp, circularQ->consumer_idx, 1454 circularQ->producer_index)); 1455 if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) { 1456 if (OPC_OUB_SKIP_ENTRY != 1457 (le32_to_cpu(msgHeader_tmp) & 0xfff)) { 1458 *messagePtr1 = 1459 ((u8 *)msgHeader) + 1460 sizeof(struct mpi_msg_hdr); 1461 *pBC = (u8)((le32_to_cpu(msgHeader_tmp) 1462 >> 24) & 0x1f); 1463 PM8001_IO_DBG(pm8001_ha, 1464 pm8001_printk(": CI=%d PI=%d " 1465 "msgHeader=%x\n", 1466 circularQ->consumer_idx, 1467 circularQ->producer_index, 1468 msgHeader_tmp)); 1469 return MPI_IO_STATUS_SUCCESS; 1470 } else { 1471 circularQ->consumer_idx = 1472 (circularQ->consumer_idx + 1473 ((le32_to_cpu(msgHeader_tmp) 1474 >> 24) & 0x1f)) 1475 % PM8001_MPI_QUEUE; 1476 msgHeader_tmp = 0; 1477 pm8001_write_32(msgHeader, 0, 0); 1478 /* update the CI of outbound queue */ 1479 pm8001_cw32(pm8001_ha, 1480 circularQ->ci_pci_bar, 1481 circularQ->ci_offset, 1482 circularQ->consumer_idx); 1483 } 1484 } else { 1485 circularQ->consumer_idx = 1486 (circularQ->consumer_idx + 1487 ((le32_to_cpu(msgHeader_tmp) >> 24) & 1488 0x1f)) % PM8001_MPI_QUEUE; 1489 msgHeader_tmp = 0; 1490 pm8001_write_32(msgHeader, 0, 0); 1491 /* update the CI of outbound queue */ 1492 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, 1493 circularQ->ci_offset, 1494 circularQ->consumer_idx); 1495 return MPI_IO_STATUS_FAIL; 1496 } 1497 } else { 1498 u32 producer_index; 1499 void *pi_virt = circularQ->pi_virt; 1500 /* spurious interrupt during setup if 1501 * kexec-ing and driver doing a doorbell access 1502 * with the pre-kexec oq interrupt setup 1503 */ 1504 if (!pi_virt) 1505 break; 1506 /* Update the producer index from SPC */ 1507 producer_index = pm8001_read_32(pi_virt); 1508 circularQ->producer_index = cpu_to_le32(producer_index); 1509 } 1510 } while (le32_to_cpu(circularQ->producer_index) != 1511 circularQ->consumer_idx); 1512 /* while we don't have any more not-yet-delivered message */ 1513 /* report empty */ 1514 return MPI_IO_STATUS_BUSY; 1515 } 1516 1517 void pm8001_work_fn(struct work_struct *work) 1518 { 1519 struct pm8001_work *pw = container_of(work, struct pm8001_work, work); 1520 struct pm8001_device *pm8001_dev; 1521 struct domain_device *dev; 1522 1523 /* 1524 * So far, all users of this stash an associated structure here. 1525 * If we get here, and this pointer is null, then the action 1526 * was cancelled. This nullification happens when the device 1527 * goes away. 1528 */ 1529 pm8001_dev = pw->data; /* Most stash device structure */ 1530 if ((pm8001_dev == NULL) 1531 || ((pw->handler != IO_XFER_ERROR_BREAK) 1532 && (pm8001_dev->dev_type == SAS_PHY_UNUSED))) { 1533 kfree(pw); 1534 return; 1535 } 1536 1537 switch (pw->handler) { 1538 case IO_XFER_ERROR_BREAK: 1539 { /* This one stashes the sas_task instead */ 1540 struct sas_task *t = (struct sas_task *)pm8001_dev; 1541 u32 tag; 1542 struct pm8001_ccb_info *ccb; 1543 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha; 1544 unsigned long flags, flags1; 1545 struct task_status_struct *ts; 1546 int i; 1547 1548 if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC) 1549 break; /* Task still on lu */ 1550 spin_lock_irqsave(&pm8001_ha->lock, flags); 1551 1552 spin_lock_irqsave(&t->task_state_lock, flags1); 1553 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) { 1554 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1555 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1556 break; /* Task got completed by another */ 1557 } 1558 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1559 1560 /* Search for a possible ccb that matches the task */ 1561 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) { 1562 ccb = &pm8001_ha->ccb_info[i]; 1563 tag = ccb->ccb_tag; 1564 if ((tag != 0xFFFFFFFF) && (ccb->task == t)) 1565 break; 1566 } 1567 if (!ccb) { 1568 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1569 break; /* Task got freed by another */ 1570 } 1571 ts = &t->task_status; 1572 ts->resp = SAS_TASK_COMPLETE; 1573 /* Force the midlayer to retry */ 1574 ts->stat = SAS_QUEUE_FULL; 1575 pm8001_dev = ccb->device; 1576 if (pm8001_dev) 1577 pm8001_dev->running_req--; 1578 spin_lock_irqsave(&t->task_state_lock, flags1); 1579 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 1580 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 1581 t->task_state_flags |= SAS_TASK_STATE_DONE; 1582 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 1583 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1584 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p" 1585 " done with event 0x%x resp 0x%x stat 0x%x but" 1586 " aborted by upper layer!\n", 1587 t, pw->handler, ts->resp, ts->stat)); 1588 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1589 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1590 } else { 1591 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1592 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1593 mb();/* in order to force CPU ordering */ 1594 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1595 t->task_done(t); 1596 } 1597 } break; 1598 case IO_XFER_OPEN_RETRY_TIMEOUT: 1599 { /* This one stashes the sas_task instead */ 1600 struct sas_task *t = (struct sas_task *)pm8001_dev; 1601 u32 tag; 1602 struct pm8001_ccb_info *ccb; 1603 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha; 1604 unsigned long flags, flags1; 1605 int i, ret = 0; 1606 1607 PM8001_IO_DBG(pm8001_ha, 1608 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 1609 1610 ret = pm8001_query_task(t); 1611 1612 PM8001_IO_DBG(pm8001_ha, 1613 switch (ret) { 1614 case TMF_RESP_FUNC_SUCC: 1615 pm8001_printk("...Task on lu\n"); 1616 break; 1617 1618 case TMF_RESP_FUNC_COMPLETE: 1619 pm8001_printk("...Task NOT on lu\n"); 1620 break; 1621 1622 default: 1623 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk( 1624 "...query task failed!!!\n")); 1625 break; 1626 }); 1627 1628 spin_lock_irqsave(&pm8001_ha->lock, flags); 1629 1630 spin_lock_irqsave(&t->task_state_lock, flags1); 1631 1632 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) { 1633 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1634 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1635 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */ 1636 (void)pm8001_abort_task(t); 1637 break; /* Task got completed by another */ 1638 } 1639 1640 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1641 1642 /* Search for a possible ccb that matches the task */ 1643 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) { 1644 ccb = &pm8001_ha->ccb_info[i]; 1645 tag = ccb->ccb_tag; 1646 if ((tag != 0xFFFFFFFF) && (ccb->task == t)) 1647 break; 1648 } 1649 if (!ccb) { 1650 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1651 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */ 1652 (void)pm8001_abort_task(t); 1653 break; /* Task got freed by another */ 1654 } 1655 1656 pm8001_dev = ccb->device; 1657 dev = pm8001_dev->sas_device; 1658 1659 switch (ret) { 1660 case TMF_RESP_FUNC_SUCC: /* task on lu */ 1661 ccb->open_retry = 1; /* Snub completion */ 1662 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1663 ret = pm8001_abort_task(t); 1664 ccb->open_retry = 0; 1665 switch (ret) { 1666 case TMF_RESP_FUNC_SUCC: 1667 case TMF_RESP_FUNC_COMPLETE: 1668 break; 1669 default: /* device misbehavior */ 1670 ret = TMF_RESP_FUNC_FAILED; 1671 PM8001_IO_DBG(pm8001_ha, 1672 pm8001_printk("...Reset phy\n")); 1673 pm8001_I_T_nexus_reset(dev); 1674 break; 1675 } 1676 break; 1677 1678 case TMF_RESP_FUNC_COMPLETE: /* task not on lu */ 1679 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1680 /* Do we need to abort the task locally? */ 1681 break; 1682 1683 default: /* device misbehavior */ 1684 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1685 ret = TMF_RESP_FUNC_FAILED; 1686 PM8001_IO_DBG(pm8001_ha, 1687 pm8001_printk("...Reset phy\n")); 1688 pm8001_I_T_nexus_reset(dev); 1689 } 1690 1691 if (ret == TMF_RESP_FUNC_FAILED) 1692 t = NULL; 1693 pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev); 1694 PM8001_IO_DBG(pm8001_ha, pm8001_printk("...Complete\n")); 1695 } break; 1696 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1697 dev = pm8001_dev->sas_device; 1698 pm8001_I_T_nexus_event_handler(dev); 1699 break; 1700 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 1701 dev = pm8001_dev->sas_device; 1702 pm8001_I_T_nexus_reset(dev); 1703 break; 1704 case IO_DS_IN_ERROR: 1705 dev = pm8001_dev->sas_device; 1706 pm8001_I_T_nexus_reset(dev); 1707 break; 1708 case IO_DS_NON_OPERATIONAL: 1709 dev = pm8001_dev->sas_device; 1710 pm8001_I_T_nexus_reset(dev); 1711 break; 1712 } 1713 kfree(pw); 1714 } 1715 1716 int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data, 1717 int handler) 1718 { 1719 struct pm8001_work *pw; 1720 int ret = 0; 1721 1722 pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC); 1723 if (pw) { 1724 pw->pm8001_ha = pm8001_ha; 1725 pw->data = data; 1726 pw->handler = handler; 1727 INIT_WORK(&pw->work, pm8001_work_fn); 1728 queue_work(pm8001_wq, &pw->work); 1729 } else 1730 ret = -ENOMEM; 1731 1732 return ret; 1733 } 1734 1735 static void pm8001_send_abort_all(struct pm8001_hba_info *pm8001_ha, 1736 struct pm8001_device *pm8001_ha_dev) 1737 { 1738 int res; 1739 u32 ccb_tag; 1740 struct pm8001_ccb_info *ccb; 1741 struct sas_task *task = NULL; 1742 struct task_abort_req task_abort; 1743 struct inbound_queue_table *circularQ; 1744 u32 opc = OPC_INB_SATA_ABORT; 1745 int ret; 1746 1747 if (!pm8001_ha_dev) { 1748 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n")); 1749 return; 1750 } 1751 1752 task = sas_alloc_slow_task(GFP_ATOMIC); 1753 1754 if (!task) { 1755 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot " 1756 "allocate task\n")); 1757 return; 1758 } 1759 1760 task->task_done = pm8001_task_done; 1761 1762 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); 1763 if (res) 1764 return; 1765 1766 ccb = &pm8001_ha->ccb_info[ccb_tag]; 1767 ccb->device = pm8001_ha_dev; 1768 ccb->ccb_tag = ccb_tag; 1769 ccb->task = task; 1770 1771 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1772 1773 memset(&task_abort, 0, sizeof(task_abort)); 1774 task_abort.abort_all = cpu_to_le32(1); 1775 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 1776 task_abort.tag = cpu_to_le32(ccb_tag); 1777 1778 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 1779 sizeof(task_abort), 0); 1780 if (ret) 1781 pm8001_tag_free(pm8001_ha, ccb_tag); 1782 1783 } 1784 1785 static void pm8001_send_read_log(struct pm8001_hba_info *pm8001_ha, 1786 struct pm8001_device *pm8001_ha_dev) 1787 { 1788 struct sata_start_req sata_cmd; 1789 int res; 1790 u32 ccb_tag; 1791 struct pm8001_ccb_info *ccb; 1792 struct sas_task *task = NULL; 1793 struct host_to_dev_fis fis; 1794 struct domain_device *dev; 1795 struct inbound_queue_table *circularQ; 1796 u32 opc = OPC_INB_SATA_HOST_OPSTART; 1797 1798 task = sas_alloc_slow_task(GFP_ATOMIC); 1799 1800 if (!task) { 1801 PM8001_FAIL_DBG(pm8001_ha, 1802 pm8001_printk("cannot allocate task !!!\n")); 1803 return; 1804 } 1805 task->task_done = pm8001_task_done; 1806 1807 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); 1808 if (res) { 1809 sas_free_task(task); 1810 PM8001_FAIL_DBG(pm8001_ha, 1811 pm8001_printk("cannot allocate tag !!!\n")); 1812 return; 1813 } 1814 1815 /* allocate domain device by ourselves as libsas 1816 * is not going to provide any 1817 */ 1818 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC); 1819 if (!dev) { 1820 sas_free_task(task); 1821 pm8001_tag_free(pm8001_ha, ccb_tag); 1822 PM8001_FAIL_DBG(pm8001_ha, 1823 pm8001_printk("Domain device cannot be allocated\n")); 1824 return; 1825 } 1826 task->dev = dev; 1827 task->dev->lldd_dev = pm8001_ha_dev; 1828 1829 ccb = &pm8001_ha->ccb_info[ccb_tag]; 1830 ccb->device = pm8001_ha_dev; 1831 ccb->ccb_tag = ccb_tag; 1832 ccb->task = task; 1833 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG; 1834 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG; 1835 1836 memset(&sata_cmd, 0, sizeof(sata_cmd)); 1837 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1838 1839 /* construct read log FIS */ 1840 memset(&fis, 0, sizeof(struct host_to_dev_fis)); 1841 fis.fis_type = 0x27; 1842 fis.flags = 0x80; 1843 fis.command = ATA_CMD_READ_LOG_EXT; 1844 fis.lbal = 0x10; 1845 fis.sector_count = 0x1; 1846 1847 sata_cmd.tag = cpu_to_le32(ccb_tag); 1848 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 1849 sata_cmd.ncqtag_atap_dir_m |= ((0x1 << 7) | (0x5 << 9)); 1850 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis)); 1851 1852 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 1853 sizeof(sata_cmd), 0); 1854 if (res) { 1855 sas_free_task(task); 1856 pm8001_tag_free(pm8001_ha, ccb_tag); 1857 kfree(dev); 1858 } 1859 } 1860 1861 /** 1862 * mpi_ssp_completion- process the event that FW response to the SSP request. 1863 * @pm8001_ha: our hba card information 1864 * @piomb: the message contents of this outbound message. 1865 * 1866 * When FW has completed a ssp request for example a IO request, after it has 1867 * filled the SG data with the data, it will trigger this event represent 1868 * that he has finished the job,please check the coresponding buffer. 1869 * So we will tell the caller who maybe waiting the result to tell upper layer 1870 * that the task has been finished. 1871 */ 1872 static void 1873 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb) 1874 { 1875 struct sas_task *t; 1876 struct pm8001_ccb_info *ccb; 1877 unsigned long flags; 1878 u32 status; 1879 u32 param; 1880 u32 tag; 1881 struct ssp_completion_resp *psspPayload; 1882 struct task_status_struct *ts; 1883 struct ssp_response_iu *iu; 1884 struct pm8001_device *pm8001_dev; 1885 psspPayload = (struct ssp_completion_resp *)(piomb + 4); 1886 status = le32_to_cpu(psspPayload->status); 1887 tag = le32_to_cpu(psspPayload->tag); 1888 ccb = &pm8001_ha->ccb_info[tag]; 1889 if ((status == IO_ABORTED) && ccb->open_retry) { 1890 /* Being completed by another */ 1891 ccb->open_retry = 0; 1892 return; 1893 } 1894 pm8001_dev = ccb->device; 1895 param = le32_to_cpu(psspPayload->param); 1896 1897 t = ccb->task; 1898 1899 if (status && status != IO_UNDERFLOW) 1900 PM8001_FAIL_DBG(pm8001_ha, 1901 pm8001_printk("sas IO status 0x%x\n", status)); 1902 if (unlikely(!t || !t->lldd_task || !t->dev)) 1903 return; 1904 ts = &t->task_status; 1905 /* Print sas address of IO failed device */ 1906 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 1907 (status != IO_UNDERFLOW)) 1908 PM8001_FAIL_DBG(pm8001_ha, 1909 pm8001_printk("SAS Address of IO Failure Drive:" 1910 "%016llx", SAS_ADDR(t->dev->sas_addr))); 1911 1912 if (status) 1913 PM8001_IOERR_DBG(pm8001_ha, pm8001_printk( 1914 "status:0x%x, tag:0x%x, task:0x%p\n", 1915 status, tag, t)); 1916 1917 switch (status) { 1918 case IO_SUCCESS: 1919 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS" 1920 ",param = %d\n", param)); 1921 if (param == 0) { 1922 ts->resp = SAS_TASK_COMPLETE; 1923 ts->stat = SAM_STAT_GOOD; 1924 } else { 1925 ts->resp = SAS_TASK_COMPLETE; 1926 ts->stat = SAS_PROTO_RESPONSE; 1927 ts->residual = param; 1928 iu = &psspPayload->ssp_resp_iu; 1929 sas_ssp_task_response(pm8001_ha->dev, t, iu); 1930 } 1931 if (pm8001_dev) 1932 pm8001_dev->running_req--; 1933 break; 1934 case IO_ABORTED: 1935 PM8001_IO_DBG(pm8001_ha, 1936 pm8001_printk("IO_ABORTED IOMB Tag\n")); 1937 ts->resp = SAS_TASK_COMPLETE; 1938 ts->stat = SAS_ABORTED_TASK; 1939 break; 1940 case IO_UNDERFLOW: 1941 /* SSP Completion with error */ 1942 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW" 1943 ",param = %d\n", param)); 1944 ts->resp = SAS_TASK_COMPLETE; 1945 ts->stat = SAS_DATA_UNDERRUN; 1946 ts->residual = param; 1947 if (pm8001_dev) 1948 pm8001_dev->running_req--; 1949 break; 1950 case IO_NO_DEVICE: 1951 PM8001_IO_DBG(pm8001_ha, 1952 pm8001_printk("IO_NO_DEVICE\n")); 1953 ts->resp = SAS_TASK_UNDELIVERED; 1954 ts->stat = SAS_PHY_DOWN; 1955 break; 1956 case IO_XFER_ERROR_BREAK: 1957 PM8001_IO_DBG(pm8001_ha, 1958 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 1959 ts->resp = SAS_TASK_COMPLETE; 1960 ts->stat = SAS_OPEN_REJECT; 1961 /* Force the midlayer to retry */ 1962 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1963 break; 1964 case IO_XFER_ERROR_PHY_NOT_READY: 1965 PM8001_IO_DBG(pm8001_ha, 1966 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 1967 ts->resp = SAS_TASK_COMPLETE; 1968 ts->stat = SAS_OPEN_REJECT; 1969 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1970 break; 1971 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 1972 PM8001_IO_DBG(pm8001_ha, 1973 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 1974 ts->resp = SAS_TASK_COMPLETE; 1975 ts->stat = SAS_OPEN_REJECT; 1976 ts->open_rej_reason = SAS_OREJ_EPROTO; 1977 break; 1978 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 1979 PM8001_IO_DBG(pm8001_ha, 1980 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 1981 ts->resp = SAS_TASK_COMPLETE; 1982 ts->stat = SAS_OPEN_REJECT; 1983 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1984 break; 1985 case IO_OPEN_CNX_ERROR_BREAK: 1986 PM8001_IO_DBG(pm8001_ha, 1987 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 1988 ts->resp = SAS_TASK_COMPLETE; 1989 ts->stat = SAS_OPEN_REJECT; 1990 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1991 break; 1992 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1993 PM8001_IO_DBG(pm8001_ha, 1994 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 1995 ts->resp = SAS_TASK_COMPLETE; 1996 ts->stat = SAS_OPEN_REJECT; 1997 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1998 if (!t->uldd_task) 1999 pm8001_handle_event(pm8001_ha, 2000 pm8001_dev, 2001 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2002 break; 2003 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2004 PM8001_IO_DBG(pm8001_ha, 2005 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2006 ts->resp = SAS_TASK_COMPLETE; 2007 ts->stat = SAS_OPEN_REJECT; 2008 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2009 break; 2010 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2011 PM8001_IO_DBG(pm8001_ha, 2012 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 2013 "NOT_SUPPORTED\n")); 2014 ts->resp = SAS_TASK_COMPLETE; 2015 ts->stat = SAS_OPEN_REJECT; 2016 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2017 break; 2018 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2019 PM8001_IO_DBG(pm8001_ha, 2020 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2021 ts->resp = SAS_TASK_UNDELIVERED; 2022 ts->stat = SAS_OPEN_REJECT; 2023 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2024 break; 2025 case IO_XFER_ERROR_NAK_RECEIVED: 2026 PM8001_IO_DBG(pm8001_ha, 2027 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 2028 ts->resp = SAS_TASK_COMPLETE; 2029 ts->stat = SAS_OPEN_REJECT; 2030 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2031 break; 2032 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2033 PM8001_IO_DBG(pm8001_ha, 2034 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 2035 ts->resp = SAS_TASK_COMPLETE; 2036 ts->stat = SAS_NAK_R_ERR; 2037 break; 2038 case IO_XFER_ERROR_DMA: 2039 PM8001_IO_DBG(pm8001_ha, 2040 pm8001_printk("IO_XFER_ERROR_DMA\n")); 2041 ts->resp = SAS_TASK_COMPLETE; 2042 ts->stat = SAS_OPEN_REJECT; 2043 break; 2044 case IO_XFER_OPEN_RETRY_TIMEOUT: 2045 PM8001_IO_DBG(pm8001_ha, 2046 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2047 ts->resp = SAS_TASK_COMPLETE; 2048 ts->stat = SAS_OPEN_REJECT; 2049 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2050 break; 2051 case IO_XFER_ERROR_OFFSET_MISMATCH: 2052 PM8001_IO_DBG(pm8001_ha, 2053 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 2054 ts->resp = SAS_TASK_COMPLETE; 2055 ts->stat = SAS_OPEN_REJECT; 2056 break; 2057 case IO_PORT_IN_RESET: 2058 PM8001_IO_DBG(pm8001_ha, 2059 pm8001_printk("IO_PORT_IN_RESET\n")); 2060 ts->resp = SAS_TASK_COMPLETE; 2061 ts->stat = SAS_OPEN_REJECT; 2062 break; 2063 case IO_DS_NON_OPERATIONAL: 2064 PM8001_IO_DBG(pm8001_ha, 2065 pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 2066 ts->resp = SAS_TASK_COMPLETE; 2067 ts->stat = SAS_OPEN_REJECT; 2068 if (!t->uldd_task) 2069 pm8001_handle_event(pm8001_ha, 2070 pm8001_dev, 2071 IO_DS_NON_OPERATIONAL); 2072 break; 2073 case IO_DS_IN_RECOVERY: 2074 PM8001_IO_DBG(pm8001_ha, 2075 pm8001_printk("IO_DS_IN_RECOVERY\n")); 2076 ts->resp = SAS_TASK_COMPLETE; 2077 ts->stat = SAS_OPEN_REJECT; 2078 break; 2079 case IO_TM_TAG_NOT_FOUND: 2080 PM8001_IO_DBG(pm8001_ha, 2081 pm8001_printk("IO_TM_TAG_NOT_FOUND\n")); 2082 ts->resp = SAS_TASK_COMPLETE; 2083 ts->stat = SAS_OPEN_REJECT; 2084 break; 2085 case IO_SSP_EXT_IU_ZERO_LEN_ERROR: 2086 PM8001_IO_DBG(pm8001_ha, 2087 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n")); 2088 ts->resp = SAS_TASK_COMPLETE; 2089 ts->stat = SAS_OPEN_REJECT; 2090 break; 2091 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2092 PM8001_IO_DBG(pm8001_ha, 2093 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 2094 ts->resp = SAS_TASK_COMPLETE; 2095 ts->stat = SAS_OPEN_REJECT; 2096 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2097 break; 2098 default: 2099 PM8001_DEVIO_DBG(pm8001_ha, 2100 pm8001_printk("Unknown status 0x%x\n", status)); 2101 /* not allowed case. Therefore, return failed status */ 2102 ts->resp = SAS_TASK_COMPLETE; 2103 ts->stat = SAS_OPEN_REJECT; 2104 break; 2105 } 2106 PM8001_IO_DBG(pm8001_ha, 2107 pm8001_printk("scsi_status = %x\n ", 2108 psspPayload->ssp_resp_iu.status)); 2109 spin_lock_irqsave(&t->task_state_lock, flags); 2110 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2111 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2112 t->task_state_flags |= SAS_TASK_STATE_DONE; 2113 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2114 spin_unlock_irqrestore(&t->task_state_lock, flags); 2115 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with" 2116 " io_status 0x%x resp 0x%x " 2117 "stat 0x%x but aborted by upper layer!\n", 2118 t, status, ts->resp, ts->stat)); 2119 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2120 } else { 2121 spin_unlock_irqrestore(&t->task_state_lock, flags); 2122 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2123 mb();/* in order to force CPU ordering */ 2124 t->task_done(t); 2125 } 2126 } 2127 2128 /*See the comments for mpi_ssp_completion */ 2129 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 2130 { 2131 struct sas_task *t; 2132 unsigned long flags; 2133 struct task_status_struct *ts; 2134 struct pm8001_ccb_info *ccb; 2135 struct pm8001_device *pm8001_dev; 2136 struct ssp_event_resp *psspPayload = 2137 (struct ssp_event_resp *)(piomb + 4); 2138 u32 event = le32_to_cpu(psspPayload->event); 2139 u32 tag = le32_to_cpu(psspPayload->tag); 2140 u32 port_id = le32_to_cpu(psspPayload->port_id); 2141 u32 dev_id = le32_to_cpu(psspPayload->device_id); 2142 2143 ccb = &pm8001_ha->ccb_info[tag]; 2144 t = ccb->task; 2145 pm8001_dev = ccb->device; 2146 if (event) 2147 PM8001_FAIL_DBG(pm8001_ha, 2148 pm8001_printk("sas IO status 0x%x\n", event)); 2149 if (unlikely(!t || !t->lldd_task || !t->dev)) 2150 return; 2151 ts = &t->task_status; 2152 PM8001_DEVIO_DBG(pm8001_ha, 2153 pm8001_printk("port_id = %x,device_id = %x\n", 2154 port_id, dev_id)); 2155 switch (event) { 2156 case IO_OVERFLOW: 2157 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");) 2158 ts->resp = SAS_TASK_COMPLETE; 2159 ts->stat = SAS_DATA_OVERRUN; 2160 ts->residual = 0; 2161 if (pm8001_dev) 2162 pm8001_dev->running_req--; 2163 break; 2164 case IO_XFER_ERROR_BREAK: 2165 PM8001_IO_DBG(pm8001_ha, 2166 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2167 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK); 2168 return; 2169 case IO_XFER_ERROR_PHY_NOT_READY: 2170 PM8001_IO_DBG(pm8001_ha, 2171 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2172 ts->resp = SAS_TASK_COMPLETE; 2173 ts->stat = SAS_OPEN_REJECT; 2174 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2175 break; 2176 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2177 PM8001_IO_DBG(pm8001_ha, 2178 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT" 2179 "_SUPPORTED\n")); 2180 ts->resp = SAS_TASK_COMPLETE; 2181 ts->stat = SAS_OPEN_REJECT; 2182 ts->open_rej_reason = SAS_OREJ_EPROTO; 2183 break; 2184 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2185 PM8001_IO_DBG(pm8001_ha, 2186 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2187 ts->resp = SAS_TASK_COMPLETE; 2188 ts->stat = SAS_OPEN_REJECT; 2189 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2190 break; 2191 case IO_OPEN_CNX_ERROR_BREAK: 2192 PM8001_IO_DBG(pm8001_ha, 2193 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2194 ts->resp = SAS_TASK_COMPLETE; 2195 ts->stat = SAS_OPEN_REJECT; 2196 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2197 break; 2198 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2199 PM8001_IO_DBG(pm8001_ha, 2200 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2201 ts->resp = SAS_TASK_COMPLETE; 2202 ts->stat = SAS_OPEN_REJECT; 2203 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2204 if (!t->uldd_task) 2205 pm8001_handle_event(pm8001_ha, 2206 pm8001_dev, 2207 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2208 break; 2209 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2210 PM8001_IO_DBG(pm8001_ha, 2211 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2212 ts->resp = SAS_TASK_COMPLETE; 2213 ts->stat = SAS_OPEN_REJECT; 2214 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2215 break; 2216 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2217 PM8001_IO_DBG(pm8001_ha, 2218 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 2219 "NOT_SUPPORTED\n")); 2220 ts->resp = SAS_TASK_COMPLETE; 2221 ts->stat = SAS_OPEN_REJECT; 2222 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2223 break; 2224 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2225 PM8001_IO_DBG(pm8001_ha, 2226 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2227 ts->resp = SAS_TASK_COMPLETE; 2228 ts->stat = SAS_OPEN_REJECT; 2229 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2230 break; 2231 case IO_XFER_ERROR_NAK_RECEIVED: 2232 PM8001_IO_DBG(pm8001_ha, 2233 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 2234 ts->resp = SAS_TASK_COMPLETE; 2235 ts->stat = SAS_OPEN_REJECT; 2236 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2237 break; 2238 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2239 PM8001_IO_DBG(pm8001_ha, 2240 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 2241 ts->resp = SAS_TASK_COMPLETE; 2242 ts->stat = SAS_NAK_R_ERR; 2243 break; 2244 case IO_XFER_OPEN_RETRY_TIMEOUT: 2245 PM8001_IO_DBG(pm8001_ha, 2246 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2247 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT); 2248 return; 2249 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2250 PM8001_IO_DBG(pm8001_ha, 2251 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n")); 2252 ts->resp = SAS_TASK_COMPLETE; 2253 ts->stat = SAS_DATA_OVERRUN; 2254 break; 2255 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2256 PM8001_IO_DBG(pm8001_ha, 2257 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n")); 2258 ts->resp = SAS_TASK_COMPLETE; 2259 ts->stat = SAS_DATA_OVERRUN; 2260 break; 2261 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2262 PM8001_IO_DBG(pm8001_ha, 2263 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n")); 2264 ts->resp = SAS_TASK_COMPLETE; 2265 ts->stat = SAS_DATA_OVERRUN; 2266 break; 2267 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT: 2268 PM8001_IO_DBG(pm8001_ha, 2269 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n")); 2270 ts->resp = SAS_TASK_COMPLETE; 2271 ts->stat = SAS_DATA_OVERRUN; 2272 break; 2273 case IO_XFER_ERROR_OFFSET_MISMATCH: 2274 PM8001_IO_DBG(pm8001_ha, 2275 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 2276 ts->resp = SAS_TASK_COMPLETE; 2277 ts->stat = SAS_DATA_OVERRUN; 2278 break; 2279 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2280 PM8001_IO_DBG(pm8001_ha, 2281 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n")); 2282 ts->resp = SAS_TASK_COMPLETE; 2283 ts->stat = SAS_DATA_OVERRUN; 2284 break; 2285 case IO_XFER_CMD_FRAME_ISSUED: 2286 PM8001_IO_DBG(pm8001_ha, 2287 pm8001_printk(" IO_XFER_CMD_FRAME_ISSUED\n")); 2288 return; 2289 default: 2290 PM8001_DEVIO_DBG(pm8001_ha, 2291 pm8001_printk("Unknown status 0x%x\n", event)); 2292 /* not allowed case. Therefore, return failed status */ 2293 ts->resp = SAS_TASK_COMPLETE; 2294 ts->stat = SAS_DATA_OVERRUN; 2295 break; 2296 } 2297 spin_lock_irqsave(&t->task_state_lock, flags); 2298 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2299 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2300 t->task_state_flags |= SAS_TASK_STATE_DONE; 2301 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2302 spin_unlock_irqrestore(&t->task_state_lock, flags); 2303 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with" 2304 " event 0x%x resp 0x%x " 2305 "stat 0x%x but aborted by upper layer!\n", 2306 t, event, ts->resp, ts->stat)); 2307 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2308 } else { 2309 spin_unlock_irqrestore(&t->task_state_lock, flags); 2310 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2311 mb();/* in order to force CPU ordering */ 2312 t->task_done(t); 2313 } 2314 } 2315 2316 /*See the comments for mpi_ssp_completion */ 2317 static void 2318 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2319 { 2320 struct sas_task *t; 2321 struct pm8001_ccb_info *ccb; 2322 u32 param; 2323 u32 status; 2324 u32 tag; 2325 int i, j; 2326 u8 sata_addr_low[4]; 2327 u32 temp_sata_addr_low; 2328 u8 sata_addr_hi[4]; 2329 u32 temp_sata_addr_hi; 2330 struct sata_completion_resp *psataPayload; 2331 struct task_status_struct *ts; 2332 struct ata_task_resp *resp ; 2333 u32 *sata_resp; 2334 struct pm8001_device *pm8001_dev; 2335 unsigned long flags; 2336 2337 psataPayload = (struct sata_completion_resp *)(piomb + 4); 2338 status = le32_to_cpu(psataPayload->status); 2339 tag = le32_to_cpu(psataPayload->tag); 2340 2341 if (!tag) { 2342 PM8001_FAIL_DBG(pm8001_ha, 2343 pm8001_printk("tag null\n")); 2344 return; 2345 } 2346 ccb = &pm8001_ha->ccb_info[tag]; 2347 param = le32_to_cpu(psataPayload->param); 2348 if (ccb) { 2349 t = ccb->task; 2350 pm8001_dev = ccb->device; 2351 } else { 2352 PM8001_FAIL_DBG(pm8001_ha, 2353 pm8001_printk("ccb null\n")); 2354 return; 2355 } 2356 2357 if (t) { 2358 if (t->dev && (t->dev->lldd_dev)) 2359 pm8001_dev = t->dev->lldd_dev; 2360 } else { 2361 PM8001_FAIL_DBG(pm8001_ha, 2362 pm8001_printk("task null\n")); 2363 return; 2364 } 2365 2366 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG)) 2367 && unlikely(!t || !t->lldd_task || !t->dev)) { 2368 PM8001_FAIL_DBG(pm8001_ha, 2369 pm8001_printk("task or dev null\n")); 2370 return; 2371 } 2372 2373 ts = &t->task_status; 2374 if (!ts) { 2375 PM8001_FAIL_DBG(pm8001_ha, 2376 pm8001_printk("ts null\n")); 2377 return; 2378 } 2379 2380 if (status) 2381 PM8001_IOERR_DBG(pm8001_ha, pm8001_printk( 2382 "status:0x%x, tag:0x%x, task::0x%p\n", 2383 status, tag, t)); 2384 2385 /* Print sas address of IO failed device */ 2386 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 2387 (status != IO_UNDERFLOW)) { 2388 if (!((t->dev->parent) && 2389 (dev_is_expander(t->dev->parent->dev_type)))) { 2390 for (i = 0 , j = 4; j <= 7 && i <= 3; i++ , j++) 2391 sata_addr_low[i] = pm8001_ha->sas_addr[j]; 2392 for (i = 0 , j = 0; j <= 3 && i <= 3; i++ , j++) 2393 sata_addr_hi[i] = pm8001_ha->sas_addr[j]; 2394 memcpy(&temp_sata_addr_low, sata_addr_low, 2395 sizeof(sata_addr_low)); 2396 memcpy(&temp_sata_addr_hi, sata_addr_hi, 2397 sizeof(sata_addr_hi)); 2398 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff) 2399 |((temp_sata_addr_hi << 8) & 2400 0xff0000) | 2401 ((temp_sata_addr_hi >> 8) 2402 & 0xff00) | 2403 ((temp_sata_addr_hi << 24) & 2404 0xff000000)); 2405 temp_sata_addr_low = ((((temp_sata_addr_low >> 24) 2406 & 0xff) | 2407 ((temp_sata_addr_low << 8) 2408 & 0xff0000) | 2409 ((temp_sata_addr_low >> 8) 2410 & 0xff00) | 2411 ((temp_sata_addr_low << 24) 2412 & 0xff000000)) + 2413 pm8001_dev->attached_phy + 2414 0x10); 2415 PM8001_FAIL_DBG(pm8001_ha, 2416 pm8001_printk("SAS Address of IO Failure Drive:" 2417 "%08x%08x", temp_sata_addr_hi, 2418 temp_sata_addr_low)); 2419 } else { 2420 PM8001_FAIL_DBG(pm8001_ha, 2421 pm8001_printk("SAS Address of IO Failure Drive:" 2422 "%016llx", SAS_ADDR(t->dev->sas_addr))); 2423 } 2424 } 2425 switch (status) { 2426 case IO_SUCCESS: 2427 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); 2428 if (param == 0) { 2429 ts->resp = SAS_TASK_COMPLETE; 2430 ts->stat = SAM_STAT_GOOD; 2431 /* check if response is for SEND READ LOG */ 2432 if (pm8001_dev && 2433 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) { 2434 /* set new bit for abort_all */ 2435 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG; 2436 /* clear bit for read log */ 2437 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF; 2438 pm8001_send_abort_all(pm8001_ha, pm8001_dev); 2439 /* Free the tag */ 2440 pm8001_tag_free(pm8001_ha, tag); 2441 sas_free_task(t); 2442 return; 2443 } 2444 } else { 2445 u8 len; 2446 ts->resp = SAS_TASK_COMPLETE; 2447 ts->stat = SAS_PROTO_RESPONSE; 2448 ts->residual = param; 2449 PM8001_IO_DBG(pm8001_ha, 2450 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n", 2451 param)); 2452 sata_resp = &psataPayload->sata_resp[0]; 2453 resp = (struct ata_task_resp *)ts->buf; 2454 if (t->ata_task.dma_xfer == 0 && 2455 t->data_dir == DMA_FROM_DEVICE) { 2456 len = sizeof(struct pio_setup_fis); 2457 PM8001_IO_DBG(pm8001_ha, 2458 pm8001_printk("PIO read len = %d\n", len)); 2459 } else if (t->ata_task.use_ncq) { 2460 len = sizeof(struct set_dev_bits_fis); 2461 PM8001_IO_DBG(pm8001_ha, 2462 pm8001_printk("FPDMA len = %d\n", len)); 2463 } else { 2464 len = sizeof(struct dev_to_host_fis); 2465 PM8001_IO_DBG(pm8001_ha, 2466 pm8001_printk("other len = %d\n", len)); 2467 } 2468 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) { 2469 resp->frame_len = len; 2470 memcpy(&resp->ending_fis[0], sata_resp, len); 2471 ts->buf_valid_size = sizeof(*resp); 2472 } else 2473 PM8001_IO_DBG(pm8001_ha, 2474 pm8001_printk("response to large\n")); 2475 } 2476 if (pm8001_dev) 2477 pm8001_dev->running_req--; 2478 break; 2479 case IO_ABORTED: 2480 PM8001_IO_DBG(pm8001_ha, 2481 pm8001_printk("IO_ABORTED IOMB Tag\n")); 2482 ts->resp = SAS_TASK_COMPLETE; 2483 ts->stat = SAS_ABORTED_TASK; 2484 if (pm8001_dev) 2485 pm8001_dev->running_req--; 2486 break; 2487 /* following cases are to do cases */ 2488 case IO_UNDERFLOW: 2489 /* SATA Completion with error */ 2490 PM8001_IO_DBG(pm8001_ha, 2491 pm8001_printk("IO_UNDERFLOW param = %d\n", param)); 2492 ts->resp = SAS_TASK_COMPLETE; 2493 ts->stat = SAS_DATA_UNDERRUN; 2494 ts->residual = param; 2495 if (pm8001_dev) 2496 pm8001_dev->running_req--; 2497 break; 2498 case IO_NO_DEVICE: 2499 PM8001_IO_DBG(pm8001_ha, 2500 pm8001_printk("IO_NO_DEVICE\n")); 2501 ts->resp = SAS_TASK_UNDELIVERED; 2502 ts->stat = SAS_PHY_DOWN; 2503 break; 2504 case IO_XFER_ERROR_BREAK: 2505 PM8001_IO_DBG(pm8001_ha, 2506 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2507 ts->resp = SAS_TASK_COMPLETE; 2508 ts->stat = SAS_INTERRUPTED; 2509 break; 2510 case IO_XFER_ERROR_PHY_NOT_READY: 2511 PM8001_IO_DBG(pm8001_ha, 2512 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2513 ts->resp = SAS_TASK_COMPLETE; 2514 ts->stat = SAS_OPEN_REJECT; 2515 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2516 break; 2517 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2518 PM8001_IO_DBG(pm8001_ha, 2519 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT" 2520 "_SUPPORTED\n")); 2521 ts->resp = SAS_TASK_COMPLETE; 2522 ts->stat = SAS_OPEN_REJECT; 2523 ts->open_rej_reason = SAS_OREJ_EPROTO; 2524 break; 2525 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2526 PM8001_IO_DBG(pm8001_ha, 2527 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2528 ts->resp = SAS_TASK_COMPLETE; 2529 ts->stat = SAS_OPEN_REJECT; 2530 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2531 break; 2532 case IO_OPEN_CNX_ERROR_BREAK: 2533 PM8001_IO_DBG(pm8001_ha, 2534 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2535 ts->resp = SAS_TASK_COMPLETE; 2536 ts->stat = SAS_OPEN_REJECT; 2537 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2538 break; 2539 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2540 PM8001_IO_DBG(pm8001_ha, 2541 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2542 ts->resp = SAS_TASK_COMPLETE; 2543 ts->stat = SAS_DEV_NO_RESPONSE; 2544 if (!t->uldd_task) { 2545 pm8001_handle_event(pm8001_ha, 2546 pm8001_dev, 2547 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2548 ts->resp = SAS_TASK_UNDELIVERED; 2549 ts->stat = SAS_QUEUE_FULL; 2550 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2551 return; 2552 } 2553 break; 2554 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2555 PM8001_IO_DBG(pm8001_ha, 2556 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2557 ts->resp = SAS_TASK_UNDELIVERED; 2558 ts->stat = SAS_OPEN_REJECT; 2559 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2560 if (!t->uldd_task) { 2561 pm8001_handle_event(pm8001_ha, 2562 pm8001_dev, 2563 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2564 ts->resp = SAS_TASK_UNDELIVERED; 2565 ts->stat = SAS_QUEUE_FULL; 2566 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2567 return; 2568 } 2569 break; 2570 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2571 PM8001_IO_DBG(pm8001_ha, 2572 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 2573 "NOT_SUPPORTED\n")); 2574 ts->resp = SAS_TASK_COMPLETE; 2575 ts->stat = SAS_OPEN_REJECT; 2576 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2577 break; 2578 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 2579 PM8001_IO_DBG(pm8001_ha, 2580 pm8001_printk("IO_OPEN_CNX_ERROR_STP_RESOURCES" 2581 "_BUSY\n")); 2582 ts->resp = SAS_TASK_COMPLETE; 2583 ts->stat = SAS_DEV_NO_RESPONSE; 2584 if (!t->uldd_task) { 2585 pm8001_handle_event(pm8001_ha, 2586 pm8001_dev, 2587 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY); 2588 ts->resp = SAS_TASK_UNDELIVERED; 2589 ts->stat = SAS_QUEUE_FULL; 2590 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2591 return; 2592 } 2593 break; 2594 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2595 PM8001_IO_DBG(pm8001_ha, 2596 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2597 ts->resp = SAS_TASK_COMPLETE; 2598 ts->stat = SAS_OPEN_REJECT; 2599 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2600 break; 2601 case IO_XFER_ERROR_NAK_RECEIVED: 2602 PM8001_IO_DBG(pm8001_ha, 2603 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 2604 ts->resp = SAS_TASK_COMPLETE; 2605 ts->stat = SAS_NAK_R_ERR; 2606 break; 2607 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2608 PM8001_IO_DBG(pm8001_ha, 2609 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 2610 ts->resp = SAS_TASK_COMPLETE; 2611 ts->stat = SAS_NAK_R_ERR; 2612 break; 2613 case IO_XFER_ERROR_DMA: 2614 PM8001_IO_DBG(pm8001_ha, 2615 pm8001_printk("IO_XFER_ERROR_DMA\n")); 2616 ts->resp = SAS_TASK_COMPLETE; 2617 ts->stat = SAS_ABORTED_TASK; 2618 break; 2619 case IO_XFER_ERROR_SATA_LINK_TIMEOUT: 2620 PM8001_IO_DBG(pm8001_ha, 2621 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n")); 2622 ts->resp = SAS_TASK_UNDELIVERED; 2623 ts->stat = SAS_DEV_NO_RESPONSE; 2624 break; 2625 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2626 PM8001_IO_DBG(pm8001_ha, 2627 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n")); 2628 ts->resp = SAS_TASK_COMPLETE; 2629 ts->stat = SAS_DATA_UNDERRUN; 2630 break; 2631 case IO_XFER_OPEN_RETRY_TIMEOUT: 2632 PM8001_IO_DBG(pm8001_ha, 2633 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2634 ts->resp = SAS_TASK_COMPLETE; 2635 ts->stat = SAS_OPEN_TO; 2636 break; 2637 case IO_PORT_IN_RESET: 2638 PM8001_IO_DBG(pm8001_ha, 2639 pm8001_printk("IO_PORT_IN_RESET\n")); 2640 ts->resp = SAS_TASK_COMPLETE; 2641 ts->stat = SAS_DEV_NO_RESPONSE; 2642 break; 2643 case IO_DS_NON_OPERATIONAL: 2644 PM8001_IO_DBG(pm8001_ha, 2645 pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 2646 ts->resp = SAS_TASK_COMPLETE; 2647 ts->stat = SAS_DEV_NO_RESPONSE; 2648 if (!t->uldd_task) { 2649 pm8001_handle_event(pm8001_ha, pm8001_dev, 2650 IO_DS_NON_OPERATIONAL); 2651 ts->resp = SAS_TASK_UNDELIVERED; 2652 ts->stat = SAS_QUEUE_FULL; 2653 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2654 return; 2655 } 2656 break; 2657 case IO_DS_IN_RECOVERY: 2658 PM8001_IO_DBG(pm8001_ha, 2659 pm8001_printk(" IO_DS_IN_RECOVERY\n")); 2660 ts->resp = SAS_TASK_COMPLETE; 2661 ts->stat = SAS_DEV_NO_RESPONSE; 2662 break; 2663 case IO_DS_IN_ERROR: 2664 PM8001_IO_DBG(pm8001_ha, 2665 pm8001_printk("IO_DS_IN_ERROR\n")); 2666 ts->resp = SAS_TASK_COMPLETE; 2667 ts->stat = SAS_DEV_NO_RESPONSE; 2668 if (!t->uldd_task) { 2669 pm8001_handle_event(pm8001_ha, pm8001_dev, 2670 IO_DS_IN_ERROR); 2671 ts->resp = SAS_TASK_UNDELIVERED; 2672 ts->stat = SAS_QUEUE_FULL; 2673 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2674 return; 2675 } 2676 break; 2677 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2678 PM8001_IO_DBG(pm8001_ha, 2679 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 2680 ts->resp = SAS_TASK_COMPLETE; 2681 ts->stat = SAS_OPEN_REJECT; 2682 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2683 break; 2684 default: 2685 PM8001_DEVIO_DBG(pm8001_ha, 2686 pm8001_printk("Unknown status 0x%x\n", status)); 2687 /* not allowed case. Therefore, return failed status */ 2688 ts->resp = SAS_TASK_COMPLETE; 2689 ts->stat = SAS_DEV_NO_RESPONSE; 2690 break; 2691 } 2692 spin_lock_irqsave(&t->task_state_lock, flags); 2693 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2694 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2695 t->task_state_flags |= SAS_TASK_STATE_DONE; 2696 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2697 spin_unlock_irqrestore(&t->task_state_lock, flags); 2698 PM8001_FAIL_DBG(pm8001_ha, 2699 pm8001_printk("task 0x%p done with io_status 0x%x" 2700 " resp 0x%x stat 0x%x but aborted by upper layer!\n", 2701 t, status, ts->resp, ts->stat)); 2702 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2703 } else { 2704 spin_unlock_irqrestore(&t->task_state_lock, flags); 2705 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2706 } 2707 } 2708 2709 /*See the comments for mpi_ssp_completion */ 2710 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 2711 { 2712 struct sas_task *t; 2713 struct task_status_struct *ts; 2714 struct pm8001_ccb_info *ccb; 2715 struct pm8001_device *pm8001_dev; 2716 struct sata_event_resp *psataPayload = 2717 (struct sata_event_resp *)(piomb + 4); 2718 u32 event = le32_to_cpu(psataPayload->event); 2719 u32 tag = le32_to_cpu(psataPayload->tag); 2720 u32 port_id = le32_to_cpu(psataPayload->port_id); 2721 u32 dev_id = le32_to_cpu(psataPayload->device_id); 2722 unsigned long flags; 2723 2724 ccb = &pm8001_ha->ccb_info[tag]; 2725 2726 if (ccb) { 2727 t = ccb->task; 2728 pm8001_dev = ccb->device; 2729 } else { 2730 PM8001_FAIL_DBG(pm8001_ha, 2731 pm8001_printk("No CCB !!!. returning\n")); 2732 } 2733 if (event) 2734 PM8001_FAIL_DBG(pm8001_ha, 2735 pm8001_printk("SATA EVENT 0x%x\n", event)); 2736 2737 /* Check if this is NCQ error */ 2738 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) { 2739 /* find device using device id */ 2740 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id); 2741 /* send read log extension */ 2742 if (pm8001_dev) 2743 pm8001_send_read_log(pm8001_ha, pm8001_dev); 2744 return; 2745 } 2746 2747 ccb = &pm8001_ha->ccb_info[tag]; 2748 t = ccb->task; 2749 pm8001_dev = ccb->device; 2750 if (event) 2751 PM8001_FAIL_DBG(pm8001_ha, 2752 pm8001_printk("sata IO status 0x%x\n", event)); 2753 if (unlikely(!t || !t->lldd_task || !t->dev)) 2754 return; 2755 ts = &t->task_status; 2756 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk( 2757 "port_id:0x%x, device_id:0x%x, tag:0x%x, event:0x%x\n", 2758 port_id, dev_id, tag, event)); 2759 switch (event) { 2760 case IO_OVERFLOW: 2761 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n")); 2762 ts->resp = SAS_TASK_COMPLETE; 2763 ts->stat = SAS_DATA_OVERRUN; 2764 ts->residual = 0; 2765 if (pm8001_dev) 2766 pm8001_dev->running_req--; 2767 break; 2768 case IO_XFER_ERROR_BREAK: 2769 PM8001_IO_DBG(pm8001_ha, 2770 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2771 ts->resp = SAS_TASK_COMPLETE; 2772 ts->stat = SAS_INTERRUPTED; 2773 break; 2774 case IO_XFER_ERROR_PHY_NOT_READY: 2775 PM8001_IO_DBG(pm8001_ha, 2776 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2777 ts->resp = SAS_TASK_COMPLETE; 2778 ts->stat = SAS_OPEN_REJECT; 2779 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2780 break; 2781 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2782 PM8001_IO_DBG(pm8001_ha, 2783 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT" 2784 "_SUPPORTED\n")); 2785 ts->resp = SAS_TASK_COMPLETE; 2786 ts->stat = SAS_OPEN_REJECT; 2787 ts->open_rej_reason = SAS_OREJ_EPROTO; 2788 break; 2789 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2790 PM8001_IO_DBG(pm8001_ha, 2791 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2792 ts->resp = SAS_TASK_COMPLETE; 2793 ts->stat = SAS_OPEN_REJECT; 2794 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2795 break; 2796 case IO_OPEN_CNX_ERROR_BREAK: 2797 PM8001_IO_DBG(pm8001_ha, 2798 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2799 ts->resp = SAS_TASK_COMPLETE; 2800 ts->stat = SAS_OPEN_REJECT; 2801 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2802 break; 2803 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2804 PM8001_IO_DBG(pm8001_ha, 2805 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2806 ts->resp = SAS_TASK_UNDELIVERED; 2807 ts->stat = SAS_DEV_NO_RESPONSE; 2808 if (!t->uldd_task) { 2809 pm8001_handle_event(pm8001_ha, 2810 pm8001_dev, 2811 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2812 ts->resp = SAS_TASK_COMPLETE; 2813 ts->stat = SAS_QUEUE_FULL; 2814 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2815 return; 2816 } 2817 break; 2818 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2819 PM8001_IO_DBG(pm8001_ha, 2820 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2821 ts->resp = SAS_TASK_UNDELIVERED; 2822 ts->stat = SAS_OPEN_REJECT; 2823 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2824 break; 2825 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2826 PM8001_IO_DBG(pm8001_ha, 2827 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 2828 "NOT_SUPPORTED\n")); 2829 ts->resp = SAS_TASK_COMPLETE; 2830 ts->stat = SAS_OPEN_REJECT; 2831 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2832 break; 2833 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2834 PM8001_IO_DBG(pm8001_ha, 2835 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2836 ts->resp = SAS_TASK_COMPLETE; 2837 ts->stat = SAS_OPEN_REJECT; 2838 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2839 break; 2840 case IO_XFER_ERROR_NAK_RECEIVED: 2841 PM8001_IO_DBG(pm8001_ha, 2842 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 2843 ts->resp = SAS_TASK_COMPLETE; 2844 ts->stat = SAS_NAK_R_ERR; 2845 break; 2846 case IO_XFER_ERROR_PEER_ABORTED: 2847 PM8001_IO_DBG(pm8001_ha, 2848 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n")); 2849 ts->resp = SAS_TASK_COMPLETE; 2850 ts->stat = SAS_NAK_R_ERR; 2851 break; 2852 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2853 PM8001_IO_DBG(pm8001_ha, 2854 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n")); 2855 ts->resp = SAS_TASK_COMPLETE; 2856 ts->stat = SAS_DATA_UNDERRUN; 2857 break; 2858 case IO_XFER_OPEN_RETRY_TIMEOUT: 2859 PM8001_IO_DBG(pm8001_ha, 2860 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2861 ts->resp = SAS_TASK_COMPLETE; 2862 ts->stat = SAS_OPEN_TO; 2863 break; 2864 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2865 PM8001_IO_DBG(pm8001_ha, 2866 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n")); 2867 ts->resp = SAS_TASK_COMPLETE; 2868 ts->stat = SAS_OPEN_TO; 2869 break; 2870 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2871 PM8001_IO_DBG(pm8001_ha, 2872 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n")); 2873 ts->resp = SAS_TASK_COMPLETE; 2874 ts->stat = SAS_OPEN_TO; 2875 break; 2876 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2877 PM8001_IO_DBG(pm8001_ha, 2878 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n")); 2879 ts->resp = SAS_TASK_COMPLETE; 2880 ts->stat = SAS_OPEN_TO; 2881 break; 2882 case IO_XFER_ERROR_OFFSET_MISMATCH: 2883 PM8001_IO_DBG(pm8001_ha, 2884 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 2885 ts->resp = SAS_TASK_COMPLETE; 2886 ts->stat = SAS_OPEN_TO; 2887 break; 2888 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2889 PM8001_IO_DBG(pm8001_ha, 2890 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n")); 2891 ts->resp = SAS_TASK_COMPLETE; 2892 ts->stat = SAS_OPEN_TO; 2893 break; 2894 case IO_XFER_CMD_FRAME_ISSUED: 2895 PM8001_IO_DBG(pm8001_ha, 2896 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n")); 2897 break; 2898 case IO_XFER_PIO_SETUP_ERROR: 2899 PM8001_IO_DBG(pm8001_ha, 2900 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n")); 2901 ts->resp = SAS_TASK_COMPLETE; 2902 ts->stat = SAS_OPEN_TO; 2903 break; 2904 default: 2905 PM8001_DEVIO_DBG(pm8001_ha, 2906 pm8001_printk("Unknown status 0x%x\n", event)); 2907 /* not allowed case. Therefore, return failed status */ 2908 ts->resp = SAS_TASK_COMPLETE; 2909 ts->stat = SAS_OPEN_TO; 2910 break; 2911 } 2912 spin_lock_irqsave(&t->task_state_lock, flags); 2913 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2914 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2915 t->task_state_flags |= SAS_TASK_STATE_DONE; 2916 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2917 spin_unlock_irqrestore(&t->task_state_lock, flags); 2918 PM8001_FAIL_DBG(pm8001_ha, 2919 pm8001_printk("task 0x%p done with io_status 0x%x" 2920 " resp 0x%x stat 0x%x but aborted by upper layer!\n", 2921 t, event, ts->resp, ts->stat)); 2922 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2923 } else { 2924 spin_unlock_irqrestore(&t->task_state_lock, flags); 2925 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2926 } 2927 } 2928 2929 /*See the comments for mpi_ssp_completion */ 2930 static void 2931 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2932 { 2933 struct sas_task *t; 2934 struct pm8001_ccb_info *ccb; 2935 unsigned long flags; 2936 u32 status; 2937 u32 tag; 2938 struct smp_completion_resp *psmpPayload; 2939 struct task_status_struct *ts; 2940 struct pm8001_device *pm8001_dev; 2941 2942 psmpPayload = (struct smp_completion_resp *)(piomb + 4); 2943 status = le32_to_cpu(psmpPayload->status); 2944 tag = le32_to_cpu(psmpPayload->tag); 2945 2946 ccb = &pm8001_ha->ccb_info[tag]; 2947 t = ccb->task; 2948 ts = &t->task_status; 2949 pm8001_dev = ccb->device; 2950 if (status) { 2951 PM8001_FAIL_DBG(pm8001_ha, 2952 pm8001_printk("smp IO status 0x%x\n", status)); 2953 PM8001_IOERR_DBG(pm8001_ha, 2954 pm8001_printk("status:0x%x, tag:0x%x, task:0x%p\n", 2955 status, tag, t)); 2956 } 2957 if (unlikely(!t || !t->lldd_task || !t->dev)) 2958 return; 2959 2960 switch (status) { 2961 case IO_SUCCESS: 2962 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); 2963 ts->resp = SAS_TASK_COMPLETE; 2964 ts->stat = SAM_STAT_GOOD; 2965 if (pm8001_dev) 2966 pm8001_dev->running_req--; 2967 break; 2968 case IO_ABORTED: 2969 PM8001_IO_DBG(pm8001_ha, 2970 pm8001_printk("IO_ABORTED IOMB\n")); 2971 ts->resp = SAS_TASK_COMPLETE; 2972 ts->stat = SAS_ABORTED_TASK; 2973 if (pm8001_dev) 2974 pm8001_dev->running_req--; 2975 break; 2976 case IO_OVERFLOW: 2977 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n")); 2978 ts->resp = SAS_TASK_COMPLETE; 2979 ts->stat = SAS_DATA_OVERRUN; 2980 ts->residual = 0; 2981 if (pm8001_dev) 2982 pm8001_dev->running_req--; 2983 break; 2984 case IO_NO_DEVICE: 2985 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n")); 2986 ts->resp = SAS_TASK_COMPLETE; 2987 ts->stat = SAS_PHY_DOWN; 2988 break; 2989 case IO_ERROR_HW_TIMEOUT: 2990 PM8001_IO_DBG(pm8001_ha, 2991 pm8001_printk("IO_ERROR_HW_TIMEOUT\n")); 2992 ts->resp = SAS_TASK_COMPLETE; 2993 ts->stat = SAM_STAT_BUSY; 2994 break; 2995 case IO_XFER_ERROR_BREAK: 2996 PM8001_IO_DBG(pm8001_ha, 2997 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2998 ts->resp = SAS_TASK_COMPLETE; 2999 ts->stat = SAM_STAT_BUSY; 3000 break; 3001 case IO_XFER_ERROR_PHY_NOT_READY: 3002 PM8001_IO_DBG(pm8001_ha, 3003 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 3004 ts->resp = SAS_TASK_COMPLETE; 3005 ts->stat = SAM_STAT_BUSY; 3006 break; 3007 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 3008 PM8001_IO_DBG(pm8001_ha, 3009 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 3010 ts->resp = SAS_TASK_COMPLETE; 3011 ts->stat = SAS_OPEN_REJECT; 3012 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 3013 break; 3014 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 3015 PM8001_IO_DBG(pm8001_ha, 3016 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 3017 ts->resp = SAS_TASK_COMPLETE; 3018 ts->stat = SAS_OPEN_REJECT; 3019 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 3020 break; 3021 case IO_OPEN_CNX_ERROR_BREAK: 3022 PM8001_IO_DBG(pm8001_ha, 3023 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 3024 ts->resp = SAS_TASK_COMPLETE; 3025 ts->stat = SAS_OPEN_REJECT; 3026 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 3027 break; 3028 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 3029 PM8001_IO_DBG(pm8001_ha, 3030 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 3031 ts->resp = SAS_TASK_COMPLETE; 3032 ts->stat = SAS_OPEN_REJECT; 3033 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 3034 pm8001_handle_event(pm8001_ha, 3035 pm8001_dev, 3036 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 3037 break; 3038 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 3039 PM8001_IO_DBG(pm8001_ha, 3040 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 3041 ts->resp = SAS_TASK_COMPLETE; 3042 ts->stat = SAS_OPEN_REJECT; 3043 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 3044 break; 3045 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 3046 PM8001_IO_DBG(pm8001_ha, 3047 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 3048 "NOT_SUPPORTED\n")); 3049 ts->resp = SAS_TASK_COMPLETE; 3050 ts->stat = SAS_OPEN_REJECT; 3051 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 3052 break; 3053 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 3054 PM8001_IO_DBG(pm8001_ha, 3055 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 3056 ts->resp = SAS_TASK_COMPLETE; 3057 ts->stat = SAS_OPEN_REJECT; 3058 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 3059 break; 3060 case IO_XFER_ERROR_RX_FRAME: 3061 PM8001_IO_DBG(pm8001_ha, 3062 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n")); 3063 ts->resp = SAS_TASK_COMPLETE; 3064 ts->stat = SAS_DEV_NO_RESPONSE; 3065 break; 3066 case IO_XFER_OPEN_RETRY_TIMEOUT: 3067 PM8001_IO_DBG(pm8001_ha, 3068 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 3069 ts->resp = SAS_TASK_COMPLETE; 3070 ts->stat = SAS_OPEN_REJECT; 3071 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3072 break; 3073 case IO_ERROR_INTERNAL_SMP_RESOURCE: 3074 PM8001_IO_DBG(pm8001_ha, 3075 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n")); 3076 ts->resp = SAS_TASK_COMPLETE; 3077 ts->stat = SAS_QUEUE_FULL; 3078 break; 3079 case IO_PORT_IN_RESET: 3080 PM8001_IO_DBG(pm8001_ha, 3081 pm8001_printk("IO_PORT_IN_RESET\n")); 3082 ts->resp = SAS_TASK_COMPLETE; 3083 ts->stat = SAS_OPEN_REJECT; 3084 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3085 break; 3086 case IO_DS_NON_OPERATIONAL: 3087 PM8001_IO_DBG(pm8001_ha, 3088 pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 3089 ts->resp = SAS_TASK_COMPLETE; 3090 ts->stat = SAS_DEV_NO_RESPONSE; 3091 break; 3092 case IO_DS_IN_RECOVERY: 3093 PM8001_IO_DBG(pm8001_ha, 3094 pm8001_printk("IO_DS_IN_RECOVERY\n")); 3095 ts->resp = SAS_TASK_COMPLETE; 3096 ts->stat = SAS_OPEN_REJECT; 3097 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3098 break; 3099 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 3100 PM8001_IO_DBG(pm8001_ha, 3101 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 3102 ts->resp = SAS_TASK_COMPLETE; 3103 ts->stat = SAS_OPEN_REJECT; 3104 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3105 break; 3106 default: 3107 PM8001_DEVIO_DBG(pm8001_ha, 3108 pm8001_printk("Unknown status 0x%x\n", status)); 3109 ts->resp = SAS_TASK_COMPLETE; 3110 ts->stat = SAS_DEV_NO_RESPONSE; 3111 /* not allowed case. Therefore, return failed status */ 3112 break; 3113 } 3114 spin_lock_irqsave(&t->task_state_lock, flags); 3115 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 3116 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 3117 t->task_state_flags |= SAS_TASK_STATE_DONE; 3118 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 3119 spin_unlock_irqrestore(&t->task_state_lock, flags); 3120 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with" 3121 " io_status 0x%x resp 0x%x " 3122 "stat 0x%x but aborted by upper layer!\n", 3123 t, status, ts->resp, ts->stat)); 3124 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 3125 } else { 3126 spin_unlock_irqrestore(&t->task_state_lock, flags); 3127 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 3128 mb();/* in order to force CPU ordering */ 3129 t->task_done(t); 3130 } 3131 } 3132 3133 void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha, 3134 void *piomb) 3135 { 3136 struct set_dev_state_resp *pPayload = 3137 (struct set_dev_state_resp *)(piomb + 4); 3138 u32 tag = le32_to_cpu(pPayload->tag); 3139 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 3140 struct pm8001_device *pm8001_dev = ccb->device; 3141 u32 status = le32_to_cpu(pPayload->status); 3142 u32 device_id = le32_to_cpu(pPayload->device_id); 3143 u8 pds = le32_to_cpu(pPayload->pds_nds) & PDS_BITS; 3144 u8 nds = le32_to_cpu(pPayload->pds_nds) & NDS_BITS; 3145 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set device id = 0x%x state " 3146 "from 0x%x to 0x%x status = 0x%x!\n", 3147 device_id, pds, nds, status)); 3148 complete(pm8001_dev->setds_completion); 3149 ccb->task = NULL; 3150 ccb->ccb_tag = 0xFFFFFFFF; 3151 pm8001_tag_free(pm8001_ha, tag); 3152 } 3153 3154 void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3155 { 3156 struct get_nvm_data_resp *pPayload = 3157 (struct get_nvm_data_resp *)(piomb + 4); 3158 u32 tag = le32_to_cpu(pPayload->tag); 3159 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 3160 u32 dlen_status = le32_to_cpu(pPayload->dlen_status); 3161 complete(pm8001_ha->nvmd_completion); 3162 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set nvm data complete!\n")); 3163 if ((dlen_status & NVMD_STAT) != 0) { 3164 PM8001_FAIL_DBG(pm8001_ha, 3165 pm8001_printk("Set nvm data error!\n")); 3166 return; 3167 } 3168 ccb->task = NULL; 3169 ccb->ccb_tag = 0xFFFFFFFF; 3170 pm8001_tag_free(pm8001_ha, tag); 3171 } 3172 3173 void 3174 pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3175 { 3176 struct fw_control_ex *fw_control_context; 3177 struct get_nvm_data_resp *pPayload = 3178 (struct get_nvm_data_resp *)(piomb + 4); 3179 u32 tag = le32_to_cpu(pPayload->tag); 3180 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 3181 u32 dlen_status = le32_to_cpu(pPayload->dlen_status); 3182 u32 ir_tds_bn_dps_das_nvm = 3183 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm); 3184 void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr; 3185 fw_control_context = ccb->fw_control_context; 3186 3187 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Get nvm data complete!\n")); 3188 if ((dlen_status & NVMD_STAT) != 0) { 3189 PM8001_FAIL_DBG(pm8001_ha, 3190 pm8001_printk("Get nvm data error!\n")); 3191 complete(pm8001_ha->nvmd_completion); 3192 return; 3193 } 3194 3195 if (ir_tds_bn_dps_das_nvm & IPMode) { 3196 /* indirect mode - IR bit set */ 3197 PM8001_MSG_DBG(pm8001_ha, 3198 pm8001_printk("Get NVMD success, IR=1\n")); 3199 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) { 3200 if (ir_tds_bn_dps_das_nvm == 0x80a80200) { 3201 memcpy(pm8001_ha->sas_addr, 3202 ((u8 *)virt_addr + 4), 3203 SAS_ADDR_SIZE); 3204 PM8001_MSG_DBG(pm8001_ha, 3205 pm8001_printk("Get SAS address" 3206 " from VPD successfully!\n")); 3207 } 3208 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM) 3209 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) || 3210 ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) { 3211 ; 3212 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP) 3213 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) { 3214 ; 3215 } else { 3216 /* Should not be happened*/ 3217 PM8001_MSG_DBG(pm8001_ha, 3218 pm8001_printk("(IR=1)Wrong Device type 0x%x\n", 3219 ir_tds_bn_dps_das_nvm)); 3220 } 3221 } else /* direct mode */{ 3222 PM8001_MSG_DBG(pm8001_ha, 3223 pm8001_printk("Get NVMD success, IR=0, dataLen=%d\n", 3224 (dlen_status & NVMD_LEN) >> 24)); 3225 } 3226 /* Though fw_control_context is freed below, usrAddr still needs 3227 * to be updated as this holds the response to the request function 3228 */ 3229 memcpy(fw_control_context->usrAddr, 3230 pm8001_ha->memoryMap.region[NVMD].virt_ptr, 3231 fw_control_context->len); 3232 kfree(ccb->fw_control_context); 3233 ccb->task = NULL; 3234 ccb->ccb_tag = 0xFFFFFFFF; 3235 pm8001_tag_free(pm8001_ha, tag); 3236 complete(pm8001_ha->nvmd_completion); 3237 } 3238 3239 int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb) 3240 { 3241 u32 tag; 3242 struct local_phy_ctl_resp *pPayload = 3243 (struct local_phy_ctl_resp *)(piomb + 4); 3244 u32 status = le32_to_cpu(pPayload->status); 3245 u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS; 3246 u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS; 3247 tag = le32_to_cpu(pPayload->tag); 3248 if (status != 0) { 3249 PM8001_MSG_DBG(pm8001_ha, 3250 pm8001_printk("%x phy execute %x phy op failed!\n", 3251 phy_id, phy_op)); 3252 } else { 3253 PM8001_MSG_DBG(pm8001_ha, 3254 pm8001_printk("%x phy execute %x phy op success!\n", 3255 phy_id, phy_op)); 3256 pm8001_ha->phy[phy_id].reset_success = true; 3257 } 3258 if (pm8001_ha->phy[phy_id].enable_completion) { 3259 complete(pm8001_ha->phy[phy_id].enable_completion); 3260 pm8001_ha->phy[phy_id].enable_completion = NULL; 3261 } 3262 pm8001_tag_free(pm8001_ha, tag); 3263 return 0; 3264 } 3265 3266 /** 3267 * pm8001_bytes_dmaed - one of the interface function communication with libsas 3268 * @pm8001_ha: our hba card information 3269 * @i: which phy that received the event. 3270 * 3271 * when HBA driver received the identify done event or initiate FIS received 3272 * event(for SATA), it will invoke this function to notify the sas layer that 3273 * the sas toplogy has formed, please discover the the whole sas domain, 3274 * while receive a broadcast(change) primitive just tell the sas 3275 * layer to discover the changed domain rather than the whole domain. 3276 */ 3277 void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i) 3278 { 3279 struct pm8001_phy *phy = &pm8001_ha->phy[i]; 3280 struct asd_sas_phy *sas_phy = &phy->sas_phy; 3281 if (!phy->phy_attached) 3282 return; 3283 3284 if (sas_phy->phy) { 3285 struct sas_phy *sphy = sas_phy->phy; 3286 sphy->negotiated_linkrate = sas_phy->linkrate; 3287 sphy->minimum_linkrate = phy->minimum_linkrate; 3288 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS; 3289 sphy->maximum_linkrate = phy->maximum_linkrate; 3290 sphy->maximum_linkrate_hw = phy->maximum_linkrate; 3291 } 3292 3293 if (phy->phy_type & PORT_TYPE_SAS) { 3294 struct sas_identify_frame *id; 3295 id = (struct sas_identify_frame *)phy->frame_rcvd; 3296 id->dev_type = phy->identify.device_type; 3297 id->initiator_bits = SAS_PROTOCOL_ALL; 3298 id->target_bits = phy->identify.target_port_protocols; 3299 } else if (phy->phy_type & PORT_TYPE_SATA) { 3300 /*Nothing*/ 3301 } 3302 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("phy %d byte dmaded.\n", i)); 3303 3304 sas_phy->frame_rcvd_size = phy->frame_rcvd_size; 3305 pm8001_ha->sas->notify_port_event(sas_phy, PORTE_BYTES_DMAED); 3306 } 3307 3308 /* Get the link rate speed */ 3309 void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate) 3310 { 3311 struct sas_phy *sas_phy = phy->sas_phy.phy; 3312 3313 switch (link_rate) { 3314 case PHY_SPEED_120: 3315 phy->sas_phy.linkrate = SAS_LINK_RATE_12_0_GBPS; 3316 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_12_0_GBPS; 3317 break; 3318 case PHY_SPEED_60: 3319 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS; 3320 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS; 3321 break; 3322 case PHY_SPEED_30: 3323 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS; 3324 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS; 3325 break; 3326 case PHY_SPEED_15: 3327 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS; 3328 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS; 3329 break; 3330 } 3331 sas_phy->negotiated_linkrate = phy->sas_phy.linkrate; 3332 sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS; 3333 sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS; 3334 sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS; 3335 sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS; 3336 } 3337 3338 /** 3339 * asd_get_attached_sas_addr -- extract/generate attached SAS address 3340 * @phy: pointer to asd_phy 3341 * @sas_addr: pointer to buffer where the SAS address is to be written 3342 * 3343 * This function extracts the SAS address from an IDENTIFY frame 3344 * received. If OOB is SATA, then a SAS address is generated from the 3345 * HA tables. 3346 * 3347 * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame 3348 * buffer. 3349 */ 3350 void pm8001_get_attached_sas_addr(struct pm8001_phy *phy, 3351 u8 *sas_addr) 3352 { 3353 if (phy->sas_phy.frame_rcvd[0] == 0x34 3354 && phy->sas_phy.oob_mode == SATA_OOB_MODE) { 3355 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha; 3356 /* FIS device-to-host */ 3357 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr); 3358 addr += phy->sas_phy.id; 3359 *(__be64 *)sas_addr = cpu_to_be64(addr); 3360 } else { 3361 struct sas_identify_frame *idframe = 3362 (void *) phy->sas_phy.frame_rcvd; 3363 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE); 3364 } 3365 } 3366 3367 /** 3368 * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW. 3369 * @pm8001_ha: our hba card information 3370 * @Qnum: the outbound queue message number. 3371 * @SEA: source of event to ack 3372 * @port_id: port id. 3373 * @phyId: phy id. 3374 * @param0: parameter 0. 3375 * @param1: parameter 1. 3376 */ 3377 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha, 3378 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1) 3379 { 3380 struct hw_event_ack_req payload; 3381 u32 opc = OPC_INB_SAS_HW_EVENT_ACK; 3382 3383 struct inbound_queue_table *circularQ; 3384 3385 memset((u8 *)&payload, 0, sizeof(payload)); 3386 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum]; 3387 payload.tag = cpu_to_le32(1); 3388 payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) | 3389 ((phyId & 0x0F) << 4) | (port_id & 0x0F)); 3390 payload.param0 = cpu_to_le32(param0); 3391 payload.param1 = cpu_to_le32(param1); 3392 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 3393 sizeof(payload), 0); 3394 } 3395 3396 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 3397 u32 phyId, u32 phy_op); 3398 3399 /** 3400 * hw_event_sas_phy_up -FW tells me a SAS phy up event. 3401 * @pm8001_ha: our hba card information 3402 * @piomb: IO message buffer 3403 */ 3404 static void 3405 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3406 { 3407 struct hw_event_resp *pPayload = 3408 (struct hw_event_resp *)(piomb + 4); 3409 u32 lr_evt_status_phyid_portid = 3410 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3411 u8 link_rate = 3412 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28); 3413 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3414 u8 phy_id = 3415 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3416 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate); 3417 u8 portstate = (u8)(npip_portstate & 0x0000000F); 3418 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3419 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3420 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3421 unsigned long flags; 3422 u8 deviceType = pPayload->sas_identify.dev_type; 3423 port->port_state = portstate; 3424 phy->phy_state = PHY_STATE_LINK_UP_SPC; 3425 PM8001_MSG_DBG(pm8001_ha, 3426 pm8001_printk("HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n", 3427 port_id, phy_id)); 3428 3429 switch (deviceType) { 3430 case SAS_PHY_UNUSED: 3431 PM8001_MSG_DBG(pm8001_ha, 3432 pm8001_printk("device type no device.\n")); 3433 break; 3434 case SAS_END_DEVICE: 3435 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n")); 3436 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id, 3437 PHY_NOTIFY_ENABLE_SPINUP); 3438 port->port_attached = 1; 3439 pm8001_get_lrate_mode(phy, link_rate); 3440 break; 3441 case SAS_EDGE_EXPANDER_DEVICE: 3442 PM8001_MSG_DBG(pm8001_ha, 3443 pm8001_printk("expander device.\n")); 3444 port->port_attached = 1; 3445 pm8001_get_lrate_mode(phy, link_rate); 3446 break; 3447 case SAS_FANOUT_EXPANDER_DEVICE: 3448 PM8001_MSG_DBG(pm8001_ha, 3449 pm8001_printk("fanout expander device.\n")); 3450 port->port_attached = 1; 3451 pm8001_get_lrate_mode(phy, link_rate); 3452 break; 3453 default: 3454 PM8001_DEVIO_DBG(pm8001_ha, 3455 pm8001_printk("unknown device type(%x)\n", deviceType)); 3456 break; 3457 } 3458 phy->phy_type |= PORT_TYPE_SAS; 3459 phy->identify.device_type = deviceType; 3460 phy->phy_attached = 1; 3461 if (phy->identify.device_type == SAS_END_DEVICE) 3462 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP; 3463 else if (phy->identify.device_type != SAS_PHY_UNUSED) 3464 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP; 3465 phy->sas_phy.oob_mode = SAS_OOB_MODE; 3466 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE); 3467 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3468 memcpy(phy->frame_rcvd, &pPayload->sas_identify, 3469 sizeof(struct sas_identify_frame)-4); 3470 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4; 3471 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3472 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3473 if (pm8001_ha->flags == PM8001F_RUN_TIME) 3474 mdelay(200);/*delay a moment to wait disk to spinup*/ 3475 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3476 } 3477 3478 /** 3479 * hw_event_sata_phy_up -FW tells me a SATA phy up event. 3480 * @pm8001_ha: our hba card information 3481 * @piomb: IO message buffer 3482 */ 3483 static void 3484 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3485 { 3486 struct hw_event_resp *pPayload = 3487 (struct hw_event_resp *)(piomb + 4); 3488 u32 lr_evt_status_phyid_portid = 3489 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3490 u8 link_rate = 3491 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28); 3492 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3493 u8 phy_id = 3494 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3495 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate); 3496 u8 portstate = (u8)(npip_portstate & 0x0000000F); 3497 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3498 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3499 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3500 unsigned long flags; 3501 PM8001_DEVIO_DBG(pm8001_ha, 3502 pm8001_printk("HW_EVENT_SATA_PHY_UP port id = %d," 3503 " phy id = %d\n", port_id, phy_id)); 3504 port->port_state = portstate; 3505 phy->phy_state = PHY_STATE_LINK_UP_SPC; 3506 port->port_attached = 1; 3507 pm8001_get_lrate_mode(phy, link_rate); 3508 phy->phy_type |= PORT_TYPE_SATA; 3509 phy->phy_attached = 1; 3510 phy->sas_phy.oob_mode = SATA_OOB_MODE; 3511 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE); 3512 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3513 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4), 3514 sizeof(struct dev_to_host_fis)); 3515 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 3516 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 3517 phy->identify.device_type = SAS_SATA_DEV; 3518 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3519 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3520 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3521 } 3522 3523 /** 3524 * hw_event_phy_down -we should notify the libsas the phy is down. 3525 * @pm8001_ha: our hba card information 3526 * @piomb: IO message buffer 3527 */ 3528 static void 3529 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb) 3530 { 3531 struct hw_event_resp *pPayload = 3532 (struct hw_event_resp *)(piomb + 4); 3533 u32 lr_evt_status_phyid_portid = 3534 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3535 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3536 u8 phy_id = 3537 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3538 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate); 3539 u8 portstate = (u8)(npip_portstate & 0x0000000F); 3540 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3541 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3542 port->port_state = portstate; 3543 phy->phy_type = 0; 3544 phy->identify.device_type = 0; 3545 phy->phy_attached = 0; 3546 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE); 3547 switch (portstate) { 3548 case PORT_VALID: 3549 break; 3550 case PORT_INVALID: 3551 PM8001_MSG_DBG(pm8001_ha, 3552 pm8001_printk(" PortInvalid portID %d\n", port_id)); 3553 PM8001_MSG_DBG(pm8001_ha, 3554 pm8001_printk(" Last phy Down and port invalid\n")); 3555 port->port_attached = 0; 3556 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3557 port_id, phy_id, 0, 0); 3558 break; 3559 case PORT_IN_RESET: 3560 PM8001_MSG_DBG(pm8001_ha, 3561 pm8001_printk(" Port In Reset portID %d\n", port_id)); 3562 break; 3563 case PORT_NOT_ESTABLISHED: 3564 PM8001_MSG_DBG(pm8001_ha, 3565 pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n")); 3566 port->port_attached = 0; 3567 break; 3568 case PORT_LOSTCOMM: 3569 PM8001_MSG_DBG(pm8001_ha, 3570 pm8001_printk(" phy Down and PORT_LOSTCOMM\n")); 3571 PM8001_MSG_DBG(pm8001_ha, 3572 pm8001_printk(" Last phy Down and port invalid\n")); 3573 port->port_attached = 0; 3574 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3575 port_id, phy_id, 0, 0); 3576 break; 3577 default: 3578 port->port_attached = 0; 3579 PM8001_DEVIO_DBG(pm8001_ha, 3580 pm8001_printk(" phy Down and(default) = %x\n", 3581 portstate)); 3582 break; 3583 3584 } 3585 } 3586 3587 /** 3588 * pm8001_mpi_reg_resp -process register device ID response. 3589 * @pm8001_ha: our hba card information 3590 * @piomb: IO message buffer 3591 * 3592 * when sas layer find a device it will notify LLDD, then the driver register 3593 * the domain device to FW, this event is the return device ID which the FW 3594 * has assigned, from now,inter-communication with FW is no longer using the 3595 * SAS address, use device ID which FW assigned. 3596 */ 3597 int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3598 { 3599 u32 status; 3600 u32 device_id; 3601 u32 htag; 3602 struct pm8001_ccb_info *ccb; 3603 struct pm8001_device *pm8001_dev; 3604 struct dev_reg_resp *registerRespPayload = 3605 (struct dev_reg_resp *)(piomb + 4); 3606 3607 htag = le32_to_cpu(registerRespPayload->tag); 3608 ccb = &pm8001_ha->ccb_info[htag]; 3609 pm8001_dev = ccb->device; 3610 status = le32_to_cpu(registerRespPayload->status); 3611 device_id = le32_to_cpu(registerRespPayload->device_id); 3612 PM8001_MSG_DBG(pm8001_ha, 3613 pm8001_printk(" register device is status = %d\n", status)); 3614 switch (status) { 3615 case DEVREG_SUCCESS: 3616 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("DEVREG_SUCCESS\n")); 3617 pm8001_dev->device_id = device_id; 3618 break; 3619 case DEVREG_FAILURE_OUT_OF_RESOURCE: 3620 PM8001_MSG_DBG(pm8001_ha, 3621 pm8001_printk("DEVREG_FAILURE_OUT_OF_RESOURCE\n")); 3622 break; 3623 case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED: 3624 PM8001_MSG_DBG(pm8001_ha, 3625 pm8001_printk("DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n")); 3626 break; 3627 case DEVREG_FAILURE_INVALID_PHY_ID: 3628 PM8001_MSG_DBG(pm8001_ha, 3629 pm8001_printk("DEVREG_FAILURE_INVALID_PHY_ID\n")); 3630 break; 3631 case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED: 3632 PM8001_MSG_DBG(pm8001_ha, 3633 pm8001_printk("DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n")); 3634 break; 3635 case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE: 3636 PM8001_MSG_DBG(pm8001_ha, 3637 pm8001_printk("DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n")); 3638 break; 3639 case DEVREG_FAILURE_PORT_NOT_VALID_STATE: 3640 PM8001_MSG_DBG(pm8001_ha, 3641 pm8001_printk("DEVREG_FAILURE_PORT_NOT_VALID_STATE\n")); 3642 break; 3643 case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID: 3644 PM8001_MSG_DBG(pm8001_ha, 3645 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n")); 3646 break; 3647 default: 3648 PM8001_MSG_DBG(pm8001_ha, 3649 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_SUPPORTED\n")); 3650 break; 3651 } 3652 complete(pm8001_dev->dcompletion); 3653 ccb->task = NULL; 3654 ccb->ccb_tag = 0xFFFFFFFF; 3655 pm8001_tag_free(pm8001_ha, htag); 3656 return 0; 3657 } 3658 3659 int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3660 { 3661 u32 status; 3662 u32 device_id; 3663 struct dev_reg_resp *registerRespPayload = 3664 (struct dev_reg_resp *)(piomb + 4); 3665 3666 status = le32_to_cpu(registerRespPayload->status); 3667 device_id = le32_to_cpu(registerRespPayload->device_id); 3668 if (status != 0) 3669 PM8001_MSG_DBG(pm8001_ha, 3670 pm8001_printk(" deregister device failed ,status = %x" 3671 ", device_id = %x\n", status, device_id)); 3672 return 0; 3673 } 3674 3675 /** 3676 * fw_flash_update_resp - Response from FW for flash update command. 3677 * @pm8001_ha: our hba card information 3678 * @piomb: IO message buffer 3679 */ 3680 int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha, 3681 void *piomb) 3682 { 3683 u32 status; 3684 struct fw_flash_Update_resp *ppayload = 3685 (struct fw_flash_Update_resp *)(piomb + 4); 3686 u32 tag = le32_to_cpu(ppayload->tag); 3687 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 3688 status = le32_to_cpu(ppayload->status); 3689 switch (status) { 3690 case FLASH_UPDATE_COMPLETE_PENDING_REBOOT: 3691 PM8001_MSG_DBG(pm8001_ha, 3692 pm8001_printk(": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n")); 3693 break; 3694 case FLASH_UPDATE_IN_PROGRESS: 3695 PM8001_MSG_DBG(pm8001_ha, 3696 pm8001_printk(": FLASH_UPDATE_IN_PROGRESS\n")); 3697 break; 3698 case FLASH_UPDATE_HDR_ERR: 3699 PM8001_MSG_DBG(pm8001_ha, 3700 pm8001_printk(": FLASH_UPDATE_HDR_ERR\n")); 3701 break; 3702 case FLASH_UPDATE_OFFSET_ERR: 3703 PM8001_MSG_DBG(pm8001_ha, 3704 pm8001_printk(": FLASH_UPDATE_OFFSET_ERR\n")); 3705 break; 3706 case FLASH_UPDATE_CRC_ERR: 3707 PM8001_MSG_DBG(pm8001_ha, 3708 pm8001_printk(": FLASH_UPDATE_CRC_ERR\n")); 3709 break; 3710 case FLASH_UPDATE_LENGTH_ERR: 3711 PM8001_MSG_DBG(pm8001_ha, 3712 pm8001_printk(": FLASH_UPDATE_LENGTH_ERR\n")); 3713 break; 3714 case FLASH_UPDATE_HW_ERR: 3715 PM8001_MSG_DBG(pm8001_ha, 3716 pm8001_printk(": FLASH_UPDATE_HW_ERR\n")); 3717 break; 3718 case FLASH_UPDATE_DNLD_NOT_SUPPORTED: 3719 PM8001_MSG_DBG(pm8001_ha, 3720 pm8001_printk(": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n")); 3721 break; 3722 case FLASH_UPDATE_DISABLED: 3723 PM8001_MSG_DBG(pm8001_ha, 3724 pm8001_printk(": FLASH_UPDATE_DISABLED\n")); 3725 break; 3726 default: 3727 PM8001_DEVIO_DBG(pm8001_ha, 3728 pm8001_printk("No matched status = %d\n", status)); 3729 break; 3730 } 3731 kfree(ccb->fw_control_context); 3732 ccb->task = NULL; 3733 ccb->ccb_tag = 0xFFFFFFFF; 3734 pm8001_tag_free(pm8001_ha, tag); 3735 complete(pm8001_ha->nvmd_completion); 3736 return 0; 3737 } 3738 3739 int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 3740 { 3741 u32 status; 3742 int i; 3743 struct general_event_resp *pPayload = 3744 (struct general_event_resp *)(piomb + 4); 3745 status = le32_to_cpu(pPayload->status); 3746 PM8001_MSG_DBG(pm8001_ha, 3747 pm8001_printk(" status = 0x%x\n", status)); 3748 for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++) 3749 PM8001_MSG_DBG(pm8001_ha, 3750 pm8001_printk("inb_IOMB_payload[0x%x] 0x%x,\n", i, 3751 pPayload->inb_IOMB_payload[i])); 3752 return 0; 3753 } 3754 3755 int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3756 { 3757 struct sas_task *t; 3758 struct pm8001_ccb_info *ccb; 3759 unsigned long flags; 3760 u32 status ; 3761 u32 tag, scp; 3762 struct task_status_struct *ts; 3763 struct pm8001_device *pm8001_dev; 3764 3765 struct task_abort_resp *pPayload = 3766 (struct task_abort_resp *)(piomb + 4); 3767 3768 status = le32_to_cpu(pPayload->status); 3769 tag = le32_to_cpu(pPayload->tag); 3770 if (!tag) { 3771 PM8001_FAIL_DBG(pm8001_ha, 3772 pm8001_printk(" TAG NULL. RETURNING !!!")); 3773 return -1; 3774 } 3775 3776 scp = le32_to_cpu(pPayload->scp); 3777 ccb = &pm8001_ha->ccb_info[tag]; 3778 t = ccb->task; 3779 pm8001_dev = ccb->device; /* retrieve device */ 3780 3781 if (!t) { 3782 PM8001_FAIL_DBG(pm8001_ha, 3783 pm8001_printk(" TASK NULL. RETURNING !!!")); 3784 return -1; 3785 } 3786 ts = &t->task_status; 3787 if (status != 0) 3788 PM8001_FAIL_DBG(pm8001_ha, 3789 pm8001_printk("task abort failed status 0x%x ," 3790 "tag = 0x%x, scp= 0x%x\n", status, tag, scp)); 3791 switch (status) { 3792 case IO_SUCCESS: 3793 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); 3794 ts->resp = SAS_TASK_COMPLETE; 3795 ts->stat = SAM_STAT_GOOD; 3796 break; 3797 case IO_NOT_VALID: 3798 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_NOT_VALID\n")); 3799 ts->resp = TMF_RESP_FUNC_FAILED; 3800 break; 3801 } 3802 spin_lock_irqsave(&t->task_state_lock, flags); 3803 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 3804 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 3805 t->task_state_flags |= SAS_TASK_STATE_DONE; 3806 spin_unlock_irqrestore(&t->task_state_lock, flags); 3807 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 3808 mb(); 3809 3810 if (pm8001_dev->id & NCQ_ABORT_ALL_FLAG) { 3811 pm8001_tag_free(pm8001_ha, tag); 3812 sas_free_task(t); 3813 /* clear the flag */ 3814 pm8001_dev->id &= 0xBFFFFFFF; 3815 } else 3816 t->task_done(t); 3817 3818 return 0; 3819 } 3820 3821 /** 3822 * mpi_hw_event -The hw event has come. 3823 * @pm8001_ha: our hba card information 3824 * @piomb: IO message buffer 3825 */ 3826 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb) 3827 { 3828 unsigned long flags; 3829 struct hw_event_resp *pPayload = 3830 (struct hw_event_resp *)(piomb + 4); 3831 u32 lr_evt_status_phyid_portid = 3832 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3833 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3834 u8 phy_id = 3835 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3836 u16 eventType = 3837 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8); 3838 u8 status = 3839 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24); 3840 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3841 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3842 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id]; 3843 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk( 3844 "SPC HW event for portid:%d, phyid:%d, event:%x, status:%x\n", 3845 port_id, phy_id, eventType, status)); 3846 switch (eventType) { 3847 case HW_EVENT_PHY_START_STATUS: 3848 PM8001_MSG_DBG(pm8001_ha, 3849 pm8001_printk("HW_EVENT_PHY_START_STATUS" 3850 " status = %x\n", status)); 3851 if (status == 0) { 3852 phy->phy_state = 1; 3853 if (pm8001_ha->flags == PM8001F_RUN_TIME && 3854 phy->enable_completion != NULL) 3855 complete(phy->enable_completion); 3856 } 3857 break; 3858 case HW_EVENT_SAS_PHY_UP: 3859 PM8001_MSG_DBG(pm8001_ha, 3860 pm8001_printk("HW_EVENT_PHY_START_STATUS\n")); 3861 hw_event_sas_phy_up(pm8001_ha, piomb); 3862 break; 3863 case HW_EVENT_SATA_PHY_UP: 3864 PM8001_MSG_DBG(pm8001_ha, 3865 pm8001_printk("HW_EVENT_SATA_PHY_UP\n")); 3866 hw_event_sata_phy_up(pm8001_ha, piomb); 3867 break; 3868 case HW_EVENT_PHY_STOP_STATUS: 3869 PM8001_MSG_DBG(pm8001_ha, 3870 pm8001_printk("HW_EVENT_PHY_STOP_STATUS " 3871 "status = %x\n", status)); 3872 if (status == 0) 3873 phy->phy_state = 0; 3874 break; 3875 case HW_EVENT_SATA_SPINUP_HOLD: 3876 PM8001_MSG_DBG(pm8001_ha, 3877 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n")); 3878 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD); 3879 break; 3880 case HW_EVENT_PHY_DOWN: 3881 PM8001_MSG_DBG(pm8001_ha, 3882 pm8001_printk("HW_EVENT_PHY_DOWN\n")); 3883 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL); 3884 phy->phy_attached = 0; 3885 phy->phy_state = 0; 3886 hw_event_phy_down(pm8001_ha, piomb); 3887 break; 3888 case HW_EVENT_PORT_INVALID: 3889 PM8001_MSG_DBG(pm8001_ha, 3890 pm8001_printk("HW_EVENT_PORT_INVALID\n")); 3891 sas_phy_disconnected(sas_phy); 3892 phy->phy_attached = 0; 3893 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3894 break; 3895 /* the broadcast change primitive received, tell the LIBSAS this event 3896 to revalidate the sas domain*/ 3897 case HW_EVENT_BROADCAST_CHANGE: 3898 PM8001_MSG_DBG(pm8001_ha, 3899 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n")); 3900 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE, 3901 port_id, phy_id, 1, 0); 3902 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3903 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE; 3904 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3905 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3906 break; 3907 case HW_EVENT_PHY_ERROR: 3908 PM8001_MSG_DBG(pm8001_ha, 3909 pm8001_printk("HW_EVENT_PHY_ERROR\n")); 3910 sas_phy_disconnected(&phy->sas_phy); 3911 phy->phy_attached = 0; 3912 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR); 3913 break; 3914 case HW_EVENT_BROADCAST_EXP: 3915 PM8001_MSG_DBG(pm8001_ha, 3916 pm8001_printk("HW_EVENT_BROADCAST_EXP\n")); 3917 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3918 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP; 3919 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3920 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3921 break; 3922 case HW_EVENT_LINK_ERR_INVALID_DWORD: 3923 PM8001_MSG_DBG(pm8001_ha, 3924 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n")); 3925 pm8001_hw_event_ack_req(pm8001_ha, 0, 3926 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0); 3927 sas_phy_disconnected(sas_phy); 3928 phy->phy_attached = 0; 3929 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3930 break; 3931 case HW_EVENT_LINK_ERR_DISPARITY_ERROR: 3932 PM8001_MSG_DBG(pm8001_ha, 3933 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n")); 3934 pm8001_hw_event_ack_req(pm8001_ha, 0, 3935 HW_EVENT_LINK_ERR_DISPARITY_ERROR, 3936 port_id, phy_id, 0, 0); 3937 sas_phy_disconnected(sas_phy); 3938 phy->phy_attached = 0; 3939 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3940 break; 3941 case HW_EVENT_LINK_ERR_CODE_VIOLATION: 3942 PM8001_MSG_DBG(pm8001_ha, 3943 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n")); 3944 pm8001_hw_event_ack_req(pm8001_ha, 0, 3945 HW_EVENT_LINK_ERR_CODE_VIOLATION, 3946 port_id, phy_id, 0, 0); 3947 sas_phy_disconnected(sas_phy); 3948 phy->phy_attached = 0; 3949 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3950 break; 3951 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH: 3952 PM8001_MSG_DBG(pm8001_ha, 3953 pm8001_printk("HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n")); 3954 pm8001_hw_event_ack_req(pm8001_ha, 0, 3955 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH, 3956 port_id, phy_id, 0, 0); 3957 sas_phy_disconnected(sas_phy); 3958 phy->phy_attached = 0; 3959 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3960 break; 3961 case HW_EVENT_MALFUNCTION: 3962 PM8001_MSG_DBG(pm8001_ha, 3963 pm8001_printk("HW_EVENT_MALFUNCTION\n")); 3964 break; 3965 case HW_EVENT_BROADCAST_SES: 3966 PM8001_MSG_DBG(pm8001_ha, 3967 pm8001_printk("HW_EVENT_BROADCAST_SES\n")); 3968 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3969 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES; 3970 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3971 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3972 break; 3973 case HW_EVENT_INBOUND_CRC_ERROR: 3974 PM8001_MSG_DBG(pm8001_ha, 3975 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n")); 3976 pm8001_hw_event_ack_req(pm8001_ha, 0, 3977 HW_EVENT_INBOUND_CRC_ERROR, 3978 port_id, phy_id, 0, 0); 3979 break; 3980 case HW_EVENT_HARD_RESET_RECEIVED: 3981 PM8001_MSG_DBG(pm8001_ha, 3982 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n")); 3983 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET); 3984 break; 3985 case HW_EVENT_ID_FRAME_TIMEOUT: 3986 PM8001_MSG_DBG(pm8001_ha, 3987 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n")); 3988 sas_phy_disconnected(sas_phy); 3989 phy->phy_attached = 0; 3990 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3991 break; 3992 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED: 3993 PM8001_MSG_DBG(pm8001_ha, 3994 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n")); 3995 pm8001_hw_event_ack_req(pm8001_ha, 0, 3996 HW_EVENT_LINK_ERR_PHY_RESET_FAILED, 3997 port_id, phy_id, 0, 0); 3998 sas_phy_disconnected(sas_phy); 3999 phy->phy_attached = 0; 4000 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 4001 break; 4002 case HW_EVENT_PORT_RESET_TIMER_TMO: 4003 PM8001_MSG_DBG(pm8001_ha, 4004 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n")); 4005 sas_phy_disconnected(sas_phy); 4006 phy->phy_attached = 0; 4007 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 4008 break; 4009 case HW_EVENT_PORT_RECOVERY_TIMER_TMO: 4010 PM8001_MSG_DBG(pm8001_ha, 4011 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n")); 4012 sas_phy_disconnected(sas_phy); 4013 phy->phy_attached = 0; 4014 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 4015 break; 4016 case HW_EVENT_PORT_RECOVER: 4017 PM8001_MSG_DBG(pm8001_ha, 4018 pm8001_printk("HW_EVENT_PORT_RECOVER\n")); 4019 break; 4020 case HW_EVENT_PORT_RESET_COMPLETE: 4021 PM8001_MSG_DBG(pm8001_ha, 4022 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n")); 4023 break; 4024 case EVENT_BROADCAST_ASYNCH_EVENT: 4025 PM8001_MSG_DBG(pm8001_ha, 4026 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n")); 4027 break; 4028 default: 4029 PM8001_DEVIO_DBG(pm8001_ha, 4030 pm8001_printk("Unknown event type = %x\n", eventType)); 4031 break; 4032 } 4033 return 0; 4034 } 4035 4036 /** 4037 * process_one_iomb - process one outbound Queue memory block 4038 * @pm8001_ha: our hba card information 4039 * @piomb: IO message buffer 4040 */ 4041 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb) 4042 { 4043 __le32 pHeader = *(__le32 *)piomb; 4044 u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF); 4045 4046 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("process_one_iomb:")); 4047 4048 switch (opc) { 4049 case OPC_OUB_ECHO: 4050 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n")); 4051 break; 4052 case OPC_OUB_HW_EVENT: 4053 PM8001_MSG_DBG(pm8001_ha, 4054 pm8001_printk("OPC_OUB_HW_EVENT\n")); 4055 mpi_hw_event(pm8001_ha, piomb); 4056 break; 4057 case OPC_OUB_SSP_COMP: 4058 PM8001_MSG_DBG(pm8001_ha, 4059 pm8001_printk("OPC_OUB_SSP_COMP\n")); 4060 mpi_ssp_completion(pm8001_ha, piomb); 4061 break; 4062 case OPC_OUB_SMP_COMP: 4063 PM8001_MSG_DBG(pm8001_ha, 4064 pm8001_printk("OPC_OUB_SMP_COMP\n")); 4065 mpi_smp_completion(pm8001_ha, piomb); 4066 break; 4067 case OPC_OUB_LOCAL_PHY_CNTRL: 4068 PM8001_MSG_DBG(pm8001_ha, 4069 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n")); 4070 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb); 4071 break; 4072 case OPC_OUB_DEV_REGIST: 4073 PM8001_MSG_DBG(pm8001_ha, 4074 pm8001_printk("OPC_OUB_DEV_REGIST\n")); 4075 pm8001_mpi_reg_resp(pm8001_ha, piomb); 4076 break; 4077 case OPC_OUB_DEREG_DEV: 4078 PM8001_MSG_DBG(pm8001_ha, 4079 pm8001_printk("unregister the device\n")); 4080 pm8001_mpi_dereg_resp(pm8001_ha, piomb); 4081 break; 4082 case OPC_OUB_GET_DEV_HANDLE: 4083 PM8001_MSG_DBG(pm8001_ha, 4084 pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n")); 4085 break; 4086 case OPC_OUB_SATA_COMP: 4087 PM8001_MSG_DBG(pm8001_ha, 4088 pm8001_printk("OPC_OUB_SATA_COMP\n")); 4089 mpi_sata_completion(pm8001_ha, piomb); 4090 break; 4091 case OPC_OUB_SATA_EVENT: 4092 PM8001_MSG_DBG(pm8001_ha, 4093 pm8001_printk("OPC_OUB_SATA_EVENT\n")); 4094 mpi_sata_event(pm8001_ha, piomb); 4095 break; 4096 case OPC_OUB_SSP_EVENT: 4097 PM8001_MSG_DBG(pm8001_ha, 4098 pm8001_printk("OPC_OUB_SSP_EVENT\n")); 4099 mpi_ssp_event(pm8001_ha, piomb); 4100 break; 4101 case OPC_OUB_DEV_HANDLE_ARRIV: 4102 PM8001_MSG_DBG(pm8001_ha, 4103 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n")); 4104 /*This is for target*/ 4105 break; 4106 case OPC_OUB_SSP_RECV_EVENT: 4107 PM8001_MSG_DBG(pm8001_ha, 4108 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n")); 4109 /*This is for target*/ 4110 break; 4111 case OPC_OUB_DEV_INFO: 4112 PM8001_MSG_DBG(pm8001_ha, 4113 pm8001_printk("OPC_OUB_DEV_INFO\n")); 4114 break; 4115 case OPC_OUB_FW_FLASH_UPDATE: 4116 PM8001_MSG_DBG(pm8001_ha, 4117 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n")); 4118 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb); 4119 break; 4120 case OPC_OUB_GPIO_RESPONSE: 4121 PM8001_MSG_DBG(pm8001_ha, 4122 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n")); 4123 break; 4124 case OPC_OUB_GPIO_EVENT: 4125 PM8001_MSG_DBG(pm8001_ha, 4126 pm8001_printk("OPC_OUB_GPIO_EVENT\n")); 4127 break; 4128 case OPC_OUB_GENERAL_EVENT: 4129 PM8001_MSG_DBG(pm8001_ha, 4130 pm8001_printk("OPC_OUB_GENERAL_EVENT\n")); 4131 pm8001_mpi_general_event(pm8001_ha, piomb); 4132 break; 4133 case OPC_OUB_SSP_ABORT_RSP: 4134 PM8001_MSG_DBG(pm8001_ha, 4135 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n")); 4136 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 4137 break; 4138 case OPC_OUB_SATA_ABORT_RSP: 4139 PM8001_MSG_DBG(pm8001_ha, 4140 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n")); 4141 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 4142 break; 4143 case OPC_OUB_SAS_DIAG_MODE_START_END: 4144 PM8001_MSG_DBG(pm8001_ha, 4145 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n")); 4146 break; 4147 case OPC_OUB_SAS_DIAG_EXECUTE: 4148 PM8001_MSG_DBG(pm8001_ha, 4149 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n")); 4150 break; 4151 case OPC_OUB_GET_TIME_STAMP: 4152 PM8001_MSG_DBG(pm8001_ha, 4153 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n")); 4154 break; 4155 case OPC_OUB_SAS_HW_EVENT_ACK: 4156 PM8001_MSG_DBG(pm8001_ha, 4157 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n")); 4158 break; 4159 case OPC_OUB_PORT_CONTROL: 4160 PM8001_MSG_DBG(pm8001_ha, 4161 pm8001_printk("OPC_OUB_PORT_CONTROL\n")); 4162 break; 4163 case OPC_OUB_SMP_ABORT_RSP: 4164 PM8001_MSG_DBG(pm8001_ha, 4165 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n")); 4166 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 4167 break; 4168 case OPC_OUB_GET_NVMD_DATA: 4169 PM8001_MSG_DBG(pm8001_ha, 4170 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n")); 4171 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb); 4172 break; 4173 case OPC_OUB_SET_NVMD_DATA: 4174 PM8001_MSG_DBG(pm8001_ha, 4175 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n")); 4176 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb); 4177 break; 4178 case OPC_OUB_DEVICE_HANDLE_REMOVAL: 4179 PM8001_MSG_DBG(pm8001_ha, 4180 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n")); 4181 break; 4182 case OPC_OUB_SET_DEVICE_STATE: 4183 PM8001_MSG_DBG(pm8001_ha, 4184 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n")); 4185 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb); 4186 break; 4187 case OPC_OUB_GET_DEVICE_STATE: 4188 PM8001_MSG_DBG(pm8001_ha, 4189 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n")); 4190 break; 4191 case OPC_OUB_SET_DEV_INFO: 4192 PM8001_MSG_DBG(pm8001_ha, 4193 pm8001_printk("OPC_OUB_SET_DEV_INFO\n")); 4194 break; 4195 case OPC_OUB_SAS_RE_INITIALIZE: 4196 PM8001_MSG_DBG(pm8001_ha, 4197 pm8001_printk("OPC_OUB_SAS_RE_INITIALIZE\n")); 4198 break; 4199 default: 4200 PM8001_DEVIO_DBG(pm8001_ha, 4201 pm8001_printk("Unknown outbound Queue IOMB OPC = %x\n", 4202 opc)); 4203 break; 4204 } 4205 } 4206 4207 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec) 4208 { 4209 struct outbound_queue_table *circularQ; 4210 void *pMsg1 = NULL; 4211 u8 uninitialized_var(bc); 4212 u32 ret = MPI_IO_STATUS_FAIL; 4213 unsigned long flags; 4214 4215 spin_lock_irqsave(&pm8001_ha->lock, flags); 4216 circularQ = &pm8001_ha->outbnd_q_tbl[vec]; 4217 do { 4218 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc); 4219 if (MPI_IO_STATUS_SUCCESS == ret) { 4220 /* process the outbound message */ 4221 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4)); 4222 /* free the message from the outbound circular buffer */ 4223 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1, 4224 circularQ, bc); 4225 } 4226 if (MPI_IO_STATUS_BUSY == ret) { 4227 /* Update the producer index from SPC */ 4228 circularQ->producer_index = 4229 cpu_to_le32(pm8001_read_32(circularQ->pi_virt)); 4230 if (le32_to_cpu(circularQ->producer_index) == 4231 circularQ->consumer_idx) 4232 /* OQ is empty */ 4233 break; 4234 } 4235 } while (1); 4236 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 4237 return ret; 4238 } 4239 4240 /* DMA_... to our direction translation. */ 4241 static const u8 data_dir_flags[] = { 4242 [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */ 4243 [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */ 4244 [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */ 4245 [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */ 4246 }; 4247 void 4248 pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd) 4249 { 4250 int i; 4251 struct scatterlist *sg; 4252 struct pm8001_prd *buf_prd = prd; 4253 4254 for_each_sg(scatter, sg, nr, i) { 4255 buf_prd->addr = cpu_to_le64(sg_dma_address(sg)); 4256 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg)); 4257 buf_prd->im_len.e = 0; 4258 buf_prd++; 4259 } 4260 } 4261 4262 static void build_smp_cmd(u32 deviceID, __le32 hTag, struct smp_req *psmp_cmd) 4263 { 4264 psmp_cmd->tag = hTag; 4265 psmp_cmd->device_id = cpu_to_le32(deviceID); 4266 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1)); 4267 } 4268 4269 /** 4270 * pm8001_chip_smp_req - send a SMP task to FW 4271 * @pm8001_ha: our hba card information. 4272 * @ccb: the ccb information this request used. 4273 */ 4274 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha, 4275 struct pm8001_ccb_info *ccb) 4276 { 4277 int elem, rc; 4278 struct sas_task *task = ccb->task; 4279 struct domain_device *dev = task->dev; 4280 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4281 struct scatterlist *sg_req, *sg_resp; 4282 u32 req_len, resp_len; 4283 struct smp_req smp_cmd; 4284 u32 opc; 4285 struct inbound_queue_table *circularQ; 4286 4287 memset(&smp_cmd, 0, sizeof(smp_cmd)); 4288 /* 4289 * DMA-map SMP request, response buffers 4290 */ 4291 sg_req = &task->smp_task.smp_req; 4292 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE); 4293 if (!elem) 4294 return -ENOMEM; 4295 req_len = sg_dma_len(sg_req); 4296 4297 sg_resp = &task->smp_task.smp_resp; 4298 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE); 4299 if (!elem) { 4300 rc = -ENOMEM; 4301 goto err_out; 4302 } 4303 resp_len = sg_dma_len(sg_resp); 4304 /* must be in dwords */ 4305 if ((req_len & 0x3) || (resp_len & 0x3)) { 4306 rc = -EINVAL; 4307 goto err_out_2; 4308 } 4309 4310 opc = OPC_INB_SMP_REQUEST; 4311 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4312 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag); 4313 smp_cmd.long_smp_req.long_req_addr = 4314 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req)); 4315 smp_cmd.long_smp_req.long_req_size = 4316 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4); 4317 smp_cmd.long_smp_req.long_resp_addr = 4318 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp)); 4319 smp_cmd.long_smp_req.long_resp_size = 4320 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4); 4321 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd); 4322 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, 4323 &smp_cmd, sizeof(smp_cmd), 0); 4324 if (rc) 4325 goto err_out_2; 4326 4327 return 0; 4328 4329 err_out_2: 4330 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1, 4331 DMA_FROM_DEVICE); 4332 err_out: 4333 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1, 4334 DMA_TO_DEVICE); 4335 return rc; 4336 } 4337 4338 /** 4339 * pm8001_chip_ssp_io_req - send a SSP task to FW 4340 * @pm8001_ha: our hba card information. 4341 * @ccb: the ccb information this request used. 4342 */ 4343 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha, 4344 struct pm8001_ccb_info *ccb) 4345 { 4346 struct sas_task *task = ccb->task; 4347 struct domain_device *dev = task->dev; 4348 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4349 struct ssp_ini_io_start_req ssp_cmd; 4350 u32 tag = ccb->ccb_tag; 4351 int ret; 4352 u64 phys_addr; 4353 struct inbound_queue_table *circularQ; 4354 u32 opc = OPC_INB_SSPINIIOSTART; 4355 memset(&ssp_cmd, 0, sizeof(ssp_cmd)); 4356 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8); 4357 ssp_cmd.dir_m_tlr = 4358 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for 4359 SAS 1.1 compatible TLR*/ 4360 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4361 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id); 4362 ssp_cmd.tag = cpu_to_le32(tag); 4363 if (task->ssp_task.enable_first_burst) 4364 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80; 4365 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3); 4366 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7); 4367 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd, 4368 task->ssp_task.cmd->cmd_len); 4369 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4370 4371 /* fill in PRD (scatter/gather) table, if any */ 4372 if (task->num_scatter > 1) { 4373 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd); 4374 phys_addr = ccb->ccb_dma_handle + 4375 offsetof(struct pm8001_ccb_info, buf_prd[0]); 4376 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(phys_addr)); 4377 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr)); 4378 ssp_cmd.esgl = cpu_to_le32(1<<31); 4379 } else if (task->num_scatter == 1) { 4380 u64 dma_addr = sg_dma_address(task->scatter); 4381 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr)); 4382 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr)); 4383 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4384 ssp_cmd.esgl = 0; 4385 } else if (task->num_scatter == 0) { 4386 ssp_cmd.addr_low = 0; 4387 ssp_cmd.addr_high = 0; 4388 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4389 ssp_cmd.esgl = 0; 4390 } 4391 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd, 4392 sizeof(ssp_cmd), 0); 4393 return ret; 4394 } 4395 4396 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha, 4397 struct pm8001_ccb_info *ccb) 4398 { 4399 struct sas_task *task = ccb->task; 4400 struct domain_device *dev = task->dev; 4401 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev; 4402 u32 tag = ccb->ccb_tag; 4403 int ret; 4404 struct sata_start_req sata_cmd; 4405 u32 hdr_tag, ncg_tag = 0; 4406 u64 phys_addr; 4407 u32 ATAP = 0x0; 4408 u32 dir; 4409 struct inbound_queue_table *circularQ; 4410 unsigned long flags; 4411 u32 opc = OPC_INB_SATA_HOST_OPSTART; 4412 memset(&sata_cmd, 0, sizeof(sata_cmd)); 4413 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4414 if (task->data_dir == DMA_NONE) { 4415 ATAP = 0x04; /* no data*/ 4416 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n")); 4417 } else if (likely(!task->ata_task.device_control_reg_update)) { 4418 if (task->ata_task.dma_xfer) { 4419 ATAP = 0x06; /* DMA */ 4420 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n")); 4421 } else { 4422 ATAP = 0x05; /* PIO*/ 4423 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n")); 4424 } 4425 if (task->ata_task.use_ncq && 4426 dev->sata_dev.class != ATA_DEV_ATAPI) { 4427 ATAP = 0x07; /* FPDMA */ 4428 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n")); 4429 } 4430 } 4431 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) { 4432 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 4433 ncg_tag = hdr_tag; 4434 } 4435 dir = data_dir_flags[task->data_dir] << 8; 4436 sata_cmd.tag = cpu_to_le32(tag); 4437 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 4438 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4439 sata_cmd.ncqtag_atap_dir_m = 4440 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir); 4441 sata_cmd.sata_fis = task->ata_task.fis; 4442 if (likely(!task->ata_task.device_control_reg_update)) 4443 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */ 4444 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */ 4445 /* fill in PRD (scatter/gather) table, if any */ 4446 if (task->num_scatter > 1) { 4447 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd); 4448 phys_addr = ccb->ccb_dma_handle + 4449 offsetof(struct pm8001_ccb_info, buf_prd[0]); 4450 sata_cmd.addr_low = lower_32_bits(phys_addr); 4451 sata_cmd.addr_high = upper_32_bits(phys_addr); 4452 sata_cmd.esgl = cpu_to_le32(1 << 31); 4453 } else if (task->num_scatter == 1) { 4454 u64 dma_addr = sg_dma_address(task->scatter); 4455 sata_cmd.addr_low = lower_32_bits(dma_addr); 4456 sata_cmd.addr_high = upper_32_bits(dma_addr); 4457 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4458 sata_cmd.esgl = 0; 4459 } else if (task->num_scatter == 0) { 4460 sata_cmd.addr_low = 0; 4461 sata_cmd.addr_high = 0; 4462 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4463 sata_cmd.esgl = 0; 4464 } 4465 4466 /* Check for read log for failed drive and return */ 4467 if (sata_cmd.sata_fis.command == 0x2f) { 4468 if (((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) || 4469 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) || 4470 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) { 4471 struct task_status_struct *ts; 4472 4473 pm8001_ha_dev->id &= 0xDFFFFFFF; 4474 ts = &task->task_status; 4475 4476 spin_lock_irqsave(&task->task_state_lock, flags); 4477 ts->resp = SAS_TASK_COMPLETE; 4478 ts->stat = SAM_STAT_GOOD; 4479 task->task_state_flags &= ~SAS_TASK_STATE_PENDING; 4480 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 4481 task->task_state_flags |= SAS_TASK_STATE_DONE; 4482 if (unlikely((task->task_state_flags & 4483 SAS_TASK_STATE_ABORTED))) { 4484 spin_unlock_irqrestore(&task->task_state_lock, 4485 flags); 4486 PM8001_FAIL_DBG(pm8001_ha, 4487 pm8001_printk("task 0x%p resp 0x%x " 4488 " stat 0x%x but aborted by upper layer " 4489 "\n", task, ts->resp, ts->stat)); 4490 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag); 4491 } else { 4492 spin_unlock_irqrestore(&task->task_state_lock, 4493 flags); 4494 pm8001_ccb_task_free_done(pm8001_ha, task, 4495 ccb, tag); 4496 return 0; 4497 } 4498 } 4499 } 4500 4501 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 4502 sizeof(sata_cmd), 0); 4503 return ret; 4504 } 4505 4506 /** 4507 * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND 4508 * @pm8001_ha: our hba card information. 4509 * @phy_id: the phy id which we wanted to start up. 4510 */ 4511 static int 4512 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id) 4513 { 4514 struct phy_start_req payload; 4515 struct inbound_queue_table *circularQ; 4516 int ret; 4517 u32 tag = 0x01; 4518 u32 opcode = OPC_INB_PHYSTART; 4519 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4520 memset(&payload, 0, sizeof(payload)); 4521 payload.tag = cpu_to_le32(tag); 4522 /* 4523 ** [0:7] PHY Identifier 4524 ** [8:11] link rate 1.5G, 3G, 6G 4525 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both 4526 ** [14] 0b disable spin up hold; 1b enable spin up hold 4527 */ 4528 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE | 4529 LINKMODE_AUTO | LINKRATE_15 | 4530 LINKRATE_30 | LINKRATE_60 | phy_id); 4531 payload.sas_identify.dev_type = SAS_END_DEVICE; 4532 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL; 4533 memcpy(payload.sas_identify.sas_addr, 4534 pm8001_ha->sas_addr, SAS_ADDR_SIZE); 4535 payload.sas_identify.phy_id = phy_id; 4536 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 4537 sizeof(payload), 0); 4538 return ret; 4539 } 4540 4541 /** 4542 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND 4543 * @pm8001_ha: our hba card information. 4544 * @phy_id: the phy id which we wanted to start up. 4545 */ 4546 static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha, 4547 u8 phy_id) 4548 { 4549 struct phy_stop_req payload; 4550 struct inbound_queue_table *circularQ; 4551 int ret; 4552 u32 tag = 0x01; 4553 u32 opcode = OPC_INB_PHYSTOP; 4554 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4555 memset(&payload, 0, sizeof(payload)); 4556 payload.tag = cpu_to_le32(tag); 4557 payload.phy_id = cpu_to_le32(phy_id); 4558 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 4559 sizeof(payload), 0); 4560 return ret; 4561 } 4562 4563 /* 4564 * see comments on pm8001_mpi_reg_resp. 4565 */ 4566 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha, 4567 struct pm8001_device *pm8001_dev, u32 flag) 4568 { 4569 struct reg_dev_req payload; 4570 u32 opc; 4571 u32 stp_sspsmp_sata = 0x4; 4572 struct inbound_queue_table *circularQ; 4573 u32 linkrate, phy_id; 4574 int rc, tag = 0xdeadbeef; 4575 struct pm8001_ccb_info *ccb; 4576 u8 retryFlag = 0x1; 4577 u16 firstBurstSize = 0; 4578 u16 ITNT = 2000; 4579 struct domain_device *dev = pm8001_dev->sas_device; 4580 struct domain_device *parent_dev = dev->parent; 4581 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4582 4583 memset(&payload, 0, sizeof(payload)); 4584 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4585 if (rc) 4586 return rc; 4587 ccb = &pm8001_ha->ccb_info[tag]; 4588 ccb->device = pm8001_dev; 4589 ccb->ccb_tag = tag; 4590 payload.tag = cpu_to_le32(tag); 4591 if (flag == 1) 4592 stp_sspsmp_sata = 0x02; /*direct attached sata */ 4593 else { 4594 if (pm8001_dev->dev_type == SAS_SATA_DEV) 4595 stp_sspsmp_sata = 0x00; /* stp*/ 4596 else if (pm8001_dev->dev_type == SAS_END_DEVICE || 4597 pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE || 4598 pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE) 4599 stp_sspsmp_sata = 0x01; /*ssp or smp*/ 4600 } 4601 if (parent_dev && dev_is_expander(parent_dev->dev_type)) 4602 phy_id = parent_dev->ex_dev.ex_phy->phy_id; 4603 else 4604 phy_id = pm8001_dev->attached_phy; 4605 opc = OPC_INB_REG_DEV; 4606 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ? 4607 pm8001_dev->sas_device->linkrate : dev->port->linkrate; 4608 payload.phyid_portid = 4609 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) | 4610 ((phy_id & 0x0F) << 4)); 4611 payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) | 4612 ((linkrate & 0x0F) * 0x1000000) | 4613 ((stp_sspsmp_sata & 0x03) * 0x10000000)); 4614 payload.firstburstsize_ITNexustimeout = 4615 cpu_to_le32(ITNT | (firstBurstSize * 0x10000)); 4616 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr, 4617 SAS_ADDR_SIZE); 4618 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4619 sizeof(payload), 0); 4620 return rc; 4621 } 4622 4623 /* 4624 * see comments on pm8001_mpi_reg_resp. 4625 */ 4626 int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha, 4627 u32 device_id) 4628 { 4629 struct dereg_dev_req payload; 4630 u32 opc = OPC_INB_DEREG_DEV_HANDLE; 4631 int ret; 4632 struct inbound_queue_table *circularQ; 4633 4634 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4635 memset(&payload, 0, sizeof(payload)); 4636 payload.tag = cpu_to_le32(1); 4637 payload.device_id = cpu_to_le32(device_id); 4638 PM8001_MSG_DBG(pm8001_ha, 4639 pm8001_printk("unregister device device_id = %d\n", device_id)); 4640 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4641 sizeof(payload), 0); 4642 return ret; 4643 } 4644 4645 /** 4646 * pm8001_chip_phy_ctl_req - support the local phy operation 4647 * @pm8001_ha: our hba card information. 4648 * @phyId: the phy id which we wanted to operate 4649 * @phy_op: the phy operation to request 4650 */ 4651 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 4652 u32 phyId, u32 phy_op) 4653 { 4654 struct local_phy_ctl_req payload; 4655 struct inbound_queue_table *circularQ; 4656 int ret; 4657 u32 opc = OPC_INB_LOCAL_PHY_CONTROL; 4658 memset(&payload, 0, sizeof(payload)); 4659 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4660 payload.tag = cpu_to_le32(1); 4661 payload.phyop_phyid = 4662 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F)); 4663 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4664 sizeof(payload), 0); 4665 return ret; 4666 } 4667 4668 static u32 pm8001_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha) 4669 { 4670 #ifdef PM8001_USE_MSIX 4671 return 1; 4672 #else 4673 u32 value; 4674 4675 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR); 4676 if (value) 4677 return 1; 4678 return 0; 4679 #endif 4680 } 4681 4682 /** 4683 * pm8001_chip_isr - PM8001 isr handler. 4684 * @pm8001_ha: our hba card information. 4685 * @vec: IRQ number 4686 */ 4687 static irqreturn_t 4688 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec) 4689 { 4690 pm8001_chip_interrupt_disable(pm8001_ha, vec); 4691 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk( 4692 "irq vec %d, ODMR:0x%x\n", 4693 vec, pm8001_cr32(pm8001_ha, 0, 0x30))); 4694 process_oq(pm8001_ha, vec); 4695 pm8001_chip_interrupt_enable(pm8001_ha, vec); 4696 return IRQ_HANDLED; 4697 } 4698 4699 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc, 4700 u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag) 4701 { 4702 struct task_abort_req task_abort; 4703 struct inbound_queue_table *circularQ; 4704 int ret; 4705 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4706 memset(&task_abort, 0, sizeof(task_abort)); 4707 if (ABORT_SINGLE == (flag & ABORT_MASK)) { 4708 task_abort.abort_all = 0; 4709 task_abort.device_id = cpu_to_le32(dev_id); 4710 task_abort.tag_to_abort = cpu_to_le32(task_tag); 4711 task_abort.tag = cpu_to_le32(cmd_tag); 4712 } else if (ABORT_ALL == (flag & ABORT_MASK)) { 4713 task_abort.abort_all = cpu_to_le32(1); 4714 task_abort.device_id = cpu_to_le32(dev_id); 4715 task_abort.tag = cpu_to_le32(cmd_tag); 4716 } 4717 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 4718 sizeof(task_abort), 0); 4719 return ret; 4720 } 4721 4722 /* 4723 * pm8001_chip_abort_task - SAS abort task when error or exception happened. 4724 */ 4725 int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha, 4726 struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag) 4727 { 4728 u32 opc, device_id; 4729 int rc = TMF_RESP_FUNC_FAILED; 4730 PM8001_EH_DBG(pm8001_ha, 4731 pm8001_printk("cmd_tag = %x, abort task tag = 0x%x", 4732 cmd_tag, task_tag)); 4733 if (pm8001_dev->dev_type == SAS_END_DEVICE) 4734 opc = OPC_INB_SSP_ABORT; 4735 else if (pm8001_dev->dev_type == SAS_SATA_DEV) 4736 opc = OPC_INB_SATA_ABORT; 4737 else 4738 opc = OPC_INB_SMP_ABORT;/* SMP */ 4739 device_id = pm8001_dev->device_id; 4740 rc = send_task_abort(pm8001_ha, opc, device_id, flag, 4741 task_tag, cmd_tag); 4742 if (rc != TMF_RESP_FUNC_COMPLETE) 4743 PM8001_EH_DBG(pm8001_ha, pm8001_printk("rc= %d\n", rc)); 4744 return rc; 4745 } 4746 4747 /** 4748 * pm8001_chip_ssp_tm_req - built the task management command. 4749 * @pm8001_ha: our hba card information. 4750 * @ccb: the ccb information. 4751 * @tmf: task management function. 4752 */ 4753 int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha, 4754 struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf) 4755 { 4756 struct sas_task *task = ccb->task; 4757 struct domain_device *dev = task->dev; 4758 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4759 u32 opc = OPC_INB_SSPINITMSTART; 4760 struct inbound_queue_table *circularQ; 4761 struct ssp_ini_tm_start_req sspTMCmd; 4762 int ret; 4763 4764 memset(&sspTMCmd, 0, sizeof(sspTMCmd)); 4765 sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id); 4766 sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed); 4767 sspTMCmd.tmf = cpu_to_le32(tmf->tmf); 4768 memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8); 4769 sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag); 4770 if (pm8001_ha->chip_id != chip_8001) 4771 sspTMCmd.ds_ads_m = 0x08; 4772 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4773 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd, 4774 sizeof(sspTMCmd), 0); 4775 return ret; 4776 } 4777 4778 int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha, 4779 void *payload) 4780 { 4781 u32 opc = OPC_INB_GET_NVMD_DATA; 4782 u32 nvmd_type; 4783 int rc; 4784 u32 tag; 4785 struct pm8001_ccb_info *ccb; 4786 struct inbound_queue_table *circularQ; 4787 struct get_nvm_data_req nvmd_req; 4788 struct fw_control_ex *fw_control_context; 4789 struct pm8001_ioctl_payload *ioctl_payload = payload; 4790 4791 nvmd_type = ioctl_payload->minor_function; 4792 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); 4793 if (!fw_control_context) 4794 return -ENOMEM; 4795 fw_control_context->usrAddr = (u8 *)ioctl_payload->func_specific; 4796 fw_control_context->len = ioctl_payload->rd_length; 4797 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4798 memset(&nvmd_req, 0, sizeof(nvmd_req)); 4799 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4800 if (rc) { 4801 kfree(fw_control_context); 4802 return rc; 4803 } 4804 ccb = &pm8001_ha->ccb_info[tag]; 4805 ccb->ccb_tag = tag; 4806 ccb->fw_control_context = fw_control_context; 4807 nvmd_req.tag = cpu_to_le32(tag); 4808 4809 switch (nvmd_type) { 4810 case TWI_DEVICE: { 4811 u32 twi_addr, twi_page_size; 4812 twi_addr = 0xa8; 4813 twi_page_size = 2; 4814 4815 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 | 4816 twi_page_size << 8 | TWI_DEVICE); 4817 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length); 4818 nvmd_req.resp_addr_hi = 4819 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4820 nvmd_req.resp_addr_lo = 4821 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4822 break; 4823 } 4824 case C_SEEPROM: { 4825 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM); 4826 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length); 4827 nvmd_req.resp_addr_hi = 4828 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4829 nvmd_req.resp_addr_lo = 4830 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4831 break; 4832 } 4833 case VPD_FLASH: { 4834 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH); 4835 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length); 4836 nvmd_req.resp_addr_hi = 4837 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4838 nvmd_req.resp_addr_lo = 4839 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4840 break; 4841 } 4842 case EXPAN_ROM: { 4843 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM); 4844 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length); 4845 nvmd_req.resp_addr_hi = 4846 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4847 nvmd_req.resp_addr_lo = 4848 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4849 break; 4850 } 4851 case IOP_RDUMP: { 4852 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | IOP_RDUMP); 4853 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length); 4854 nvmd_req.vpd_offset = cpu_to_le32(ioctl_payload->offset); 4855 nvmd_req.resp_addr_hi = 4856 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4857 nvmd_req.resp_addr_lo = 4858 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4859 break; 4860 } 4861 default: 4862 break; 4863 } 4864 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req, 4865 sizeof(nvmd_req), 0); 4866 if (rc) { 4867 kfree(fw_control_context); 4868 pm8001_tag_free(pm8001_ha, tag); 4869 } 4870 return rc; 4871 } 4872 4873 int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha, 4874 void *payload) 4875 { 4876 u32 opc = OPC_INB_SET_NVMD_DATA; 4877 u32 nvmd_type; 4878 int rc; 4879 u32 tag; 4880 struct pm8001_ccb_info *ccb; 4881 struct inbound_queue_table *circularQ; 4882 struct set_nvm_data_req nvmd_req; 4883 struct fw_control_ex *fw_control_context; 4884 struct pm8001_ioctl_payload *ioctl_payload = payload; 4885 4886 nvmd_type = ioctl_payload->minor_function; 4887 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); 4888 if (!fw_control_context) 4889 return -ENOMEM; 4890 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4891 memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr, 4892 &ioctl_payload->func_specific, 4893 ioctl_payload->wr_length); 4894 memset(&nvmd_req, 0, sizeof(nvmd_req)); 4895 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4896 if (rc) { 4897 kfree(fw_control_context); 4898 return -EBUSY; 4899 } 4900 ccb = &pm8001_ha->ccb_info[tag]; 4901 ccb->fw_control_context = fw_control_context; 4902 ccb->ccb_tag = tag; 4903 nvmd_req.tag = cpu_to_le32(tag); 4904 switch (nvmd_type) { 4905 case TWI_DEVICE: { 4906 u32 twi_addr, twi_page_size; 4907 twi_addr = 0xa8; 4908 twi_page_size = 2; 4909 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4910 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 | 4911 twi_page_size << 8 | TWI_DEVICE); 4912 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length); 4913 nvmd_req.resp_addr_hi = 4914 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4915 nvmd_req.resp_addr_lo = 4916 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4917 break; 4918 } 4919 case C_SEEPROM: 4920 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM); 4921 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length); 4922 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4923 nvmd_req.resp_addr_hi = 4924 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4925 nvmd_req.resp_addr_lo = 4926 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4927 break; 4928 case VPD_FLASH: 4929 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH); 4930 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length); 4931 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4932 nvmd_req.resp_addr_hi = 4933 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4934 nvmd_req.resp_addr_lo = 4935 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4936 break; 4937 case EXPAN_ROM: 4938 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM); 4939 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length); 4940 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4941 nvmd_req.resp_addr_hi = 4942 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4943 nvmd_req.resp_addr_lo = 4944 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4945 break; 4946 default: 4947 break; 4948 } 4949 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req, 4950 sizeof(nvmd_req), 0); 4951 if (rc) { 4952 kfree(fw_control_context); 4953 pm8001_tag_free(pm8001_ha, tag); 4954 } 4955 return rc; 4956 } 4957 4958 /** 4959 * pm8001_chip_fw_flash_update_build - support the firmware update operation 4960 * @pm8001_ha: our hba card information. 4961 * @fw_flash_updata_info: firmware flash update param 4962 * @tag: Tag to apply to the payload 4963 */ 4964 int 4965 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha, 4966 void *fw_flash_updata_info, u32 tag) 4967 { 4968 struct fw_flash_Update_req payload; 4969 struct fw_flash_updata_info *info; 4970 struct inbound_queue_table *circularQ; 4971 int ret; 4972 u32 opc = OPC_INB_FW_FLASH_UPDATE; 4973 4974 memset(&payload, 0, sizeof(struct fw_flash_Update_req)); 4975 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4976 info = fw_flash_updata_info; 4977 payload.tag = cpu_to_le32(tag); 4978 payload.cur_image_len = cpu_to_le32(info->cur_image_len); 4979 payload.cur_image_offset = cpu_to_le32(info->cur_image_offset); 4980 payload.total_image_len = cpu_to_le32(info->total_image_len); 4981 payload.len = info->sgl.im_len.len ; 4982 payload.sgl_addr_lo = 4983 cpu_to_le32(lower_32_bits(le64_to_cpu(info->sgl.addr))); 4984 payload.sgl_addr_hi = 4985 cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr))); 4986 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4987 sizeof(payload), 0); 4988 return ret; 4989 } 4990 4991 int 4992 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha, 4993 void *payload) 4994 { 4995 struct fw_flash_updata_info flash_update_info; 4996 struct fw_control_info *fw_control; 4997 struct fw_control_ex *fw_control_context; 4998 int rc; 4999 u32 tag; 5000 struct pm8001_ccb_info *ccb; 5001 void *buffer = pm8001_ha->memoryMap.region[FW_FLASH].virt_ptr; 5002 dma_addr_t phys_addr = pm8001_ha->memoryMap.region[FW_FLASH].phys_addr; 5003 struct pm8001_ioctl_payload *ioctl_payload = payload; 5004 5005 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); 5006 if (!fw_control_context) 5007 return -ENOMEM; 5008 fw_control = (struct fw_control_info *)&ioctl_payload->func_specific; 5009 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk( 5010 "dma fw_control context input length :%x\n", fw_control->len)); 5011 memcpy(buffer, fw_control->buffer, fw_control->len); 5012 flash_update_info.sgl.addr = cpu_to_le64(phys_addr); 5013 flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len); 5014 flash_update_info.sgl.im_len.e = 0; 5015 flash_update_info.cur_image_offset = fw_control->offset; 5016 flash_update_info.cur_image_len = fw_control->len; 5017 flash_update_info.total_image_len = fw_control->size; 5018 fw_control_context->fw_control = fw_control; 5019 fw_control_context->virtAddr = buffer; 5020 fw_control_context->phys_addr = phys_addr; 5021 fw_control_context->len = fw_control->len; 5022 rc = pm8001_tag_alloc(pm8001_ha, &tag); 5023 if (rc) { 5024 kfree(fw_control_context); 5025 return -EBUSY; 5026 } 5027 ccb = &pm8001_ha->ccb_info[tag]; 5028 ccb->fw_control_context = fw_control_context; 5029 ccb->ccb_tag = tag; 5030 rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info, 5031 tag); 5032 return rc; 5033 } 5034 5035 ssize_t 5036 pm8001_get_gsm_dump(struct device *cdev, u32 length, char *buf) 5037 { 5038 u32 value, rem, offset = 0, bar = 0; 5039 u32 index, work_offset, dw_length; 5040 u32 shift_value, gsm_base, gsm_dump_offset; 5041 char *direct_data; 5042 struct Scsi_Host *shost = class_to_shost(cdev); 5043 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 5044 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 5045 5046 direct_data = buf; 5047 gsm_dump_offset = pm8001_ha->fatal_forensic_shift_offset; 5048 5049 /* check max is 1 Mbytes */ 5050 if ((length > 0x100000) || (gsm_dump_offset & 3) || 5051 ((gsm_dump_offset + length) > 0x1000000)) 5052 return -EINVAL; 5053 5054 if (pm8001_ha->chip_id == chip_8001) 5055 bar = 2; 5056 else 5057 bar = 1; 5058 5059 work_offset = gsm_dump_offset & 0xFFFF0000; 5060 offset = gsm_dump_offset & 0x0000FFFF; 5061 gsm_dump_offset = work_offset; 5062 /* adjust length to dword boundary */ 5063 rem = length & 3; 5064 dw_length = length >> 2; 5065 5066 for (index = 0; index < dw_length; index++) { 5067 if ((work_offset + offset) & 0xFFFF0000) { 5068 if (pm8001_ha->chip_id == chip_8001) 5069 shift_value = ((gsm_dump_offset + offset) & 5070 SHIFT_REG_64K_MASK); 5071 else 5072 shift_value = (((gsm_dump_offset + offset) & 5073 SHIFT_REG_64K_MASK) >> 5074 SHIFT_REG_BIT_SHIFT); 5075 5076 if (pm8001_ha->chip_id == chip_8001) { 5077 gsm_base = GSM_BASE; 5078 if (-1 == pm8001_bar4_shift(pm8001_ha, 5079 (gsm_base + shift_value))) 5080 return -EIO; 5081 } else { 5082 gsm_base = 0; 5083 if (-1 == pm80xx_bar4_shift(pm8001_ha, 5084 (gsm_base + shift_value))) 5085 return -EIO; 5086 } 5087 gsm_dump_offset = (gsm_dump_offset + offset) & 5088 0xFFFF0000; 5089 work_offset = 0; 5090 offset = offset & 0x0000FFFF; 5091 } 5092 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) & 5093 0x0000FFFF); 5094 direct_data += sprintf(direct_data, "%08x ", value); 5095 offset += 4; 5096 } 5097 if (rem != 0) { 5098 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) & 5099 0x0000FFFF); 5100 /* xfr for non_dw */ 5101 direct_data += sprintf(direct_data, "%08x ", value); 5102 } 5103 /* Shift back to BAR4 original address */ 5104 if (-1 == pm8001_bar4_shift(pm8001_ha, 0)) 5105 return -EIO; 5106 pm8001_ha->fatal_forensic_shift_offset += 1024; 5107 5108 if (pm8001_ha->fatal_forensic_shift_offset >= 0x100000) 5109 pm8001_ha->fatal_forensic_shift_offset = 0; 5110 return direct_data - buf; 5111 } 5112 5113 int 5114 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha, 5115 struct pm8001_device *pm8001_dev, u32 state) 5116 { 5117 struct set_dev_state_req payload; 5118 struct inbound_queue_table *circularQ; 5119 struct pm8001_ccb_info *ccb; 5120 int rc; 5121 u32 tag; 5122 u32 opc = OPC_INB_SET_DEVICE_STATE; 5123 memset(&payload, 0, sizeof(payload)); 5124 rc = pm8001_tag_alloc(pm8001_ha, &tag); 5125 if (rc) 5126 return -1; 5127 ccb = &pm8001_ha->ccb_info[tag]; 5128 ccb->ccb_tag = tag; 5129 ccb->device = pm8001_dev; 5130 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 5131 payload.tag = cpu_to_le32(tag); 5132 payload.device_id = cpu_to_le32(pm8001_dev->device_id); 5133 payload.nds = cpu_to_le32(state); 5134 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 5135 sizeof(payload), 0); 5136 return rc; 5137 5138 } 5139 5140 static int 5141 pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha) 5142 { 5143 struct sas_re_initialization_req payload; 5144 struct inbound_queue_table *circularQ; 5145 struct pm8001_ccb_info *ccb; 5146 int rc; 5147 u32 tag; 5148 u32 opc = OPC_INB_SAS_RE_INITIALIZE; 5149 memset(&payload, 0, sizeof(payload)); 5150 rc = pm8001_tag_alloc(pm8001_ha, &tag); 5151 if (rc) 5152 return -ENOMEM; 5153 ccb = &pm8001_ha->ccb_info[tag]; 5154 ccb->ccb_tag = tag; 5155 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 5156 payload.tag = cpu_to_le32(tag); 5157 payload.SSAHOLT = cpu_to_le32(0xd << 25); 5158 payload.sata_hol_tmo = cpu_to_le32(80); 5159 payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff); 5160 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 5161 sizeof(payload), 0); 5162 if (rc) 5163 pm8001_tag_free(pm8001_ha, tag); 5164 return rc; 5165 5166 } 5167 5168 const struct pm8001_dispatch pm8001_8001_dispatch = { 5169 .name = "pmc8001", 5170 .chip_init = pm8001_chip_init, 5171 .chip_soft_rst = pm8001_chip_soft_rst, 5172 .chip_rst = pm8001_hw_chip_rst, 5173 .chip_iounmap = pm8001_chip_iounmap, 5174 .isr = pm8001_chip_isr, 5175 .is_our_interrupt = pm8001_chip_is_our_interrupt, 5176 .isr_process_oq = process_oq, 5177 .interrupt_enable = pm8001_chip_interrupt_enable, 5178 .interrupt_disable = pm8001_chip_interrupt_disable, 5179 .make_prd = pm8001_chip_make_sg, 5180 .smp_req = pm8001_chip_smp_req, 5181 .ssp_io_req = pm8001_chip_ssp_io_req, 5182 .sata_req = pm8001_chip_sata_req, 5183 .phy_start_req = pm8001_chip_phy_start_req, 5184 .phy_stop_req = pm8001_chip_phy_stop_req, 5185 .reg_dev_req = pm8001_chip_reg_dev_req, 5186 .dereg_dev_req = pm8001_chip_dereg_dev_req, 5187 .phy_ctl_req = pm8001_chip_phy_ctl_req, 5188 .task_abort = pm8001_chip_abort_task, 5189 .ssp_tm_req = pm8001_chip_ssp_tm_req, 5190 .get_nvmd_req = pm8001_chip_get_nvmd_req, 5191 .set_nvmd_req = pm8001_chip_set_nvmd_req, 5192 .fw_flash_update_req = pm8001_chip_fw_flash_update_req, 5193 .set_dev_state_req = pm8001_chip_set_dev_state_req, 5194 .sas_re_init_req = pm8001_chip_sas_re_initialization, 5195 }; 5196