1 /* 2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 USI Co., Ltd. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 #include <linux/slab.h> 41 #include "pm8001_sas.h" 42 #include "pm8001_hwi.h" 43 #include "pm8001_chips.h" 44 #include "pm8001_ctl.h" 45 46 /** 47 * read_main_config_table - read the configure table and save it. 48 * @pm8001_ha: our hba card information 49 */ 50 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha) 51 { 52 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 53 pm8001_ha->main_cfg_tbl.pm8001_tbl.signature = 54 pm8001_mr32(address, 0x00); 55 pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev = 56 pm8001_mr32(address, 0x04); 57 pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev = 58 pm8001_mr32(address, 0x08); 59 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io = 60 pm8001_mr32(address, 0x0C); 61 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl = 62 pm8001_mr32(address, 0x10); 63 pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag = 64 pm8001_mr32(address, 0x14); 65 pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset = 66 pm8001_mr32(address, 0x18); 67 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset = 68 pm8001_mr32(address, MAIN_IBQ_OFFSET); 69 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset = 70 pm8001_mr32(address, MAIN_OBQ_OFFSET); 71 pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag = 72 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET); 73 74 /* read analog Setting offset from the configuration table */ 75 pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset = 76 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET); 77 78 /* read Error Dump Offset and Length */ 79 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 = 80 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET); 81 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 = 82 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH); 83 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 = 84 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET); 85 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 = 86 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH); 87 } 88 89 /** 90 * read_general_status_table - read the general status table and save it. 91 * @pm8001_ha: our hba card information 92 */ 93 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha) 94 { 95 void __iomem *address = pm8001_ha->general_stat_tbl_addr; 96 pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate = 97 pm8001_mr32(address, 0x00); 98 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0 = 99 pm8001_mr32(address, 0x04); 100 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1 = 101 pm8001_mr32(address, 0x08); 102 pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt = 103 pm8001_mr32(address, 0x0C); 104 pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt = 105 pm8001_mr32(address, 0x10); 106 pm8001_ha->gs_tbl.pm8001_tbl.rsvd = 107 pm8001_mr32(address, 0x14); 108 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0] = 109 pm8001_mr32(address, 0x18); 110 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1] = 111 pm8001_mr32(address, 0x1C); 112 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2] = 113 pm8001_mr32(address, 0x20); 114 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3] = 115 pm8001_mr32(address, 0x24); 116 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4] = 117 pm8001_mr32(address, 0x28); 118 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5] = 119 pm8001_mr32(address, 0x2C); 120 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6] = 121 pm8001_mr32(address, 0x30); 122 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7] = 123 pm8001_mr32(address, 0x34); 124 pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val = 125 pm8001_mr32(address, 0x38); 126 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0] = 127 pm8001_mr32(address, 0x3C); 128 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1] = 129 pm8001_mr32(address, 0x40); 130 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0] = 131 pm8001_mr32(address, 0x44); 132 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1] = 133 pm8001_mr32(address, 0x48); 134 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2] = 135 pm8001_mr32(address, 0x4C); 136 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3] = 137 pm8001_mr32(address, 0x50); 138 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4] = 139 pm8001_mr32(address, 0x54); 140 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5] = 141 pm8001_mr32(address, 0x58); 142 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6] = 143 pm8001_mr32(address, 0x5C); 144 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7] = 145 pm8001_mr32(address, 0x60); 146 } 147 148 /** 149 * read_inbnd_queue_table - read the inbound queue table and save it. 150 * @pm8001_ha: our hba card information 151 */ 152 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 153 { 154 int i; 155 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 156 for (i = 0; i < PM8001_MAX_INB_NUM; i++) { 157 u32 offset = i * 0x20; 158 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 159 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14))); 160 pm8001_ha->inbnd_q_tbl[i].pi_offset = 161 pm8001_mr32(address, (offset + 0x18)); 162 } 163 } 164 165 /** 166 * read_outbnd_queue_table - read the outbound queue table and save it. 167 * @pm8001_ha: our hba card information 168 */ 169 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 170 { 171 int i; 172 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 173 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) { 174 u32 offset = i * 0x24; 175 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 176 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14))); 177 pm8001_ha->outbnd_q_tbl[i].ci_offset = 178 pm8001_mr32(address, (offset + 0x18)); 179 } 180 } 181 182 /** 183 * init_default_table_values - init the default table. 184 * @pm8001_ha: our hba card information 185 */ 186 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha) 187 { 188 int i; 189 u32 offsetib, offsetob; 190 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr; 191 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr; 192 193 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd = 0; 194 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3 = 0; 195 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7 = 0; 196 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3 = 0; 197 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7 = 0; 198 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 = 199 0; 200 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 = 201 0; 202 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0; 203 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0; 204 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0; 205 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0; 206 207 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr = 208 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi; 209 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr = 210 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo; 211 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size = 212 PM8001_EVENT_LOG_SIZE; 213 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option = 0x01; 214 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr = 215 pm8001_ha->memoryMap.region[IOP].phys_addr_hi; 216 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr = 217 pm8001_ha->memoryMap.region[IOP].phys_addr_lo; 218 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size = 219 PM8001_EVENT_LOG_SIZE; 220 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option = 0x01; 221 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt = 0x01; 222 for (i = 0; i < PM8001_MAX_INB_NUM; i++) { 223 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt = 224 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30); 225 pm8001_ha->inbnd_q_tbl[i].upper_base_addr = 226 pm8001_ha->memoryMap.region[IB + i].phys_addr_hi; 227 pm8001_ha->inbnd_q_tbl[i].lower_base_addr = 228 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo; 229 pm8001_ha->inbnd_q_tbl[i].base_virt = 230 (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr; 231 pm8001_ha->inbnd_q_tbl[i].total_length = 232 pm8001_ha->memoryMap.region[IB + i].total_len; 233 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr = 234 pm8001_ha->memoryMap.region[CI + i].phys_addr_hi; 235 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr = 236 pm8001_ha->memoryMap.region[CI + i].phys_addr_lo; 237 pm8001_ha->inbnd_q_tbl[i].ci_virt = 238 pm8001_ha->memoryMap.region[CI + i].virt_ptr; 239 offsetib = i * 0x20; 240 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 241 get_pci_bar_index(pm8001_mr32(addressib, 242 (offsetib + 0x14))); 243 pm8001_ha->inbnd_q_tbl[i].pi_offset = 244 pm8001_mr32(addressib, (offsetib + 0x18)); 245 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0; 246 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0; 247 } 248 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) { 249 pm8001_ha->outbnd_q_tbl[i].element_size_cnt = 250 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30); 251 pm8001_ha->outbnd_q_tbl[i].upper_base_addr = 252 pm8001_ha->memoryMap.region[OB + i].phys_addr_hi; 253 pm8001_ha->outbnd_q_tbl[i].lower_base_addr = 254 pm8001_ha->memoryMap.region[OB + i].phys_addr_lo; 255 pm8001_ha->outbnd_q_tbl[i].base_virt = 256 (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr; 257 pm8001_ha->outbnd_q_tbl[i].total_length = 258 pm8001_ha->memoryMap.region[OB + i].total_len; 259 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr = 260 pm8001_ha->memoryMap.region[PI + i].phys_addr_hi; 261 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr = 262 pm8001_ha->memoryMap.region[PI + i].phys_addr_lo; 263 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = 264 0 | (10 << 16) | (i << 24); 265 pm8001_ha->outbnd_q_tbl[i].pi_virt = 266 pm8001_ha->memoryMap.region[PI + i].virt_ptr; 267 offsetob = i * 0x24; 268 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 269 get_pci_bar_index(pm8001_mr32(addressob, 270 offsetob + 0x14)); 271 pm8001_ha->outbnd_q_tbl[i].ci_offset = 272 pm8001_mr32(addressob, (offsetob + 0x18)); 273 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0; 274 pm8001_ha->outbnd_q_tbl[i].producer_index = 0; 275 } 276 } 277 278 /** 279 * update_main_config_table - update the main default table to the HBA. 280 * @pm8001_ha: our hba card information 281 */ 282 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha) 283 { 284 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 285 pm8001_mw32(address, 0x24, 286 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd); 287 pm8001_mw32(address, 0x28, 288 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3); 289 pm8001_mw32(address, 0x2C, 290 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7); 291 pm8001_mw32(address, 0x30, 292 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3); 293 pm8001_mw32(address, 0x34, 294 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7); 295 pm8001_mw32(address, 0x38, 296 pm8001_ha->main_cfg_tbl.pm8001_tbl. 297 outbound_tgt_ITNexus_event_pid0_3); 298 pm8001_mw32(address, 0x3C, 299 pm8001_ha->main_cfg_tbl.pm8001_tbl. 300 outbound_tgt_ITNexus_event_pid4_7); 301 pm8001_mw32(address, 0x40, 302 pm8001_ha->main_cfg_tbl.pm8001_tbl. 303 outbound_tgt_ssp_event_pid0_3); 304 pm8001_mw32(address, 0x44, 305 pm8001_ha->main_cfg_tbl.pm8001_tbl. 306 outbound_tgt_ssp_event_pid4_7); 307 pm8001_mw32(address, 0x48, 308 pm8001_ha->main_cfg_tbl.pm8001_tbl. 309 outbound_tgt_smp_event_pid0_3); 310 pm8001_mw32(address, 0x4C, 311 pm8001_ha->main_cfg_tbl.pm8001_tbl. 312 outbound_tgt_smp_event_pid4_7); 313 pm8001_mw32(address, 0x50, 314 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr); 315 pm8001_mw32(address, 0x54, 316 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr); 317 pm8001_mw32(address, 0x58, 318 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size); 319 pm8001_mw32(address, 0x5C, 320 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option); 321 pm8001_mw32(address, 0x60, 322 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr); 323 pm8001_mw32(address, 0x64, 324 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr); 325 pm8001_mw32(address, 0x68, 326 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size); 327 pm8001_mw32(address, 0x6C, 328 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option); 329 pm8001_mw32(address, 0x70, 330 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt); 331 } 332 333 /** 334 * update_inbnd_queue_table - update the inbound queue table to the HBA. 335 * @pm8001_ha: our hba card information 336 */ 337 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 338 int number) 339 { 340 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 341 u16 offset = number * 0x20; 342 pm8001_mw32(address, offset + 0x00, 343 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); 344 pm8001_mw32(address, offset + 0x04, 345 pm8001_ha->inbnd_q_tbl[number].upper_base_addr); 346 pm8001_mw32(address, offset + 0x08, 347 pm8001_ha->inbnd_q_tbl[number].lower_base_addr); 348 pm8001_mw32(address, offset + 0x0C, 349 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr); 350 pm8001_mw32(address, offset + 0x10, 351 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); 352 } 353 354 /** 355 * update_outbnd_queue_table - update the outbound queue table to the HBA. 356 * @pm8001_ha: our hba card information 357 */ 358 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 359 int number) 360 { 361 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 362 u16 offset = number * 0x24; 363 pm8001_mw32(address, offset + 0x00, 364 pm8001_ha->outbnd_q_tbl[number].element_size_cnt); 365 pm8001_mw32(address, offset + 0x04, 366 pm8001_ha->outbnd_q_tbl[number].upper_base_addr); 367 pm8001_mw32(address, offset + 0x08, 368 pm8001_ha->outbnd_q_tbl[number].lower_base_addr); 369 pm8001_mw32(address, offset + 0x0C, 370 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr); 371 pm8001_mw32(address, offset + 0x10, 372 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); 373 pm8001_mw32(address, offset + 0x1C, 374 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay); 375 } 376 377 /** 378 * pm8001_bar4_shift - function is called to shift BAR base address 379 * @pm8001_ha : our hba card infomation 380 * @shiftValue : shifting value in memory bar. 381 */ 382 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue) 383 { 384 u32 regVal; 385 unsigned long start; 386 387 /* program the inbound AXI translation Lower Address */ 388 pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue); 389 390 /* confirm the setting is written */ 391 start = jiffies + HZ; /* 1 sec */ 392 do { 393 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW); 394 } while ((regVal != shiftValue) && time_before(jiffies, start)); 395 396 if (regVal != shiftValue) { 397 PM8001_INIT_DBG(pm8001_ha, 398 pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW" 399 " = 0x%x\n", regVal)); 400 return -1; 401 } 402 return 0; 403 } 404 405 /** 406 * mpi_set_phys_g3_with_ssc 407 * @pm8001_ha: our hba card information 408 * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc. 409 */ 410 static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha, 411 u32 SSCbit) 412 { 413 u32 value, offset, i; 414 unsigned long flags; 415 416 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000 417 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000 418 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074 419 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074 420 #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12 421 #define PHY_G3_WITH_SSC_BIT_SHIFT 13 422 #define SNW3_PHY_CAPABILITIES_PARITY 31 423 424 /* 425 * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3) 426 * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7) 427 */ 428 spin_lock_irqsave(&pm8001_ha->lock, flags); 429 if (-1 == pm8001_bar4_shift(pm8001_ha, 430 SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) { 431 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 432 return; 433 } 434 435 for (i = 0; i < 4; i++) { 436 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i; 437 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501); 438 } 439 /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */ 440 if (-1 == pm8001_bar4_shift(pm8001_ha, 441 SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) { 442 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 443 return; 444 } 445 for (i = 4; i < 8; i++) { 446 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4); 447 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501); 448 } 449 /************************************************************* 450 Change the SSC upspreading value to 0x0 so that upspreading is disabled. 451 Device MABC SMOD0 Controls 452 Address: (via MEMBASE-III): 453 Using shifted destination address 0x0_0000: with Offset 0xD8 454 455 31:28 R/W Reserved Do not change 456 27:24 R/W SAS_SMOD_SPRDUP 0000 457 23:20 R/W SAS_SMOD_SPRDDN 0000 458 19:0 R/W Reserved Do not change 459 Upon power-up this register will read as 0x8990c016, 460 and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000 461 so that the written value will be 0x8090c016. 462 This will ensure only down-spreading SSC is enabled on the SPC. 463 *************************************************************/ 464 value = pm8001_cr32(pm8001_ha, 2, 0xd8); 465 pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016); 466 467 /*set the shifted destination address to 0x0 to avoid error operation */ 468 pm8001_bar4_shift(pm8001_ha, 0x0); 469 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 470 return; 471 } 472 473 /** 474 * mpi_set_open_retry_interval_reg 475 * @pm8001_ha: our hba card information 476 * @interval - interval time for each OPEN_REJECT (RETRY). The units are in 1us. 477 */ 478 static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha, 479 u32 interval) 480 { 481 u32 offset; 482 u32 value; 483 u32 i; 484 unsigned long flags; 485 486 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000 487 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000 488 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4 489 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4 490 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF 491 492 value = interval & OPEN_RETRY_INTERVAL_REG_MASK; 493 spin_lock_irqsave(&pm8001_ha->lock, flags); 494 /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/ 495 if (-1 == pm8001_bar4_shift(pm8001_ha, 496 OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) { 497 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 498 return; 499 } 500 for (i = 0; i < 4; i++) { 501 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i; 502 pm8001_cw32(pm8001_ha, 2, offset, value); 503 } 504 505 if (-1 == pm8001_bar4_shift(pm8001_ha, 506 OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) { 507 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 508 return; 509 } 510 for (i = 4; i < 8; i++) { 511 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4); 512 pm8001_cw32(pm8001_ha, 2, offset, value); 513 } 514 /*set the shifted destination address to 0x0 to avoid error operation */ 515 pm8001_bar4_shift(pm8001_ha, 0x0); 516 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 517 return; 518 } 519 520 /** 521 * mpi_init_check - check firmware initialization status. 522 * @pm8001_ha: our hba card information 523 */ 524 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha) 525 { 526 u32 max_wait_count; 527 u32 value; 528 u32 gst_len_mpistate; 529 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the 530 table is updated */ 531 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE); 532 /* wait until Inbound DoorBell Clear Register toggled */ 533 max_wait_count = 1 * 1000 * 1000;/* 1 sec */ 534 do { 535 udelay(1); 536 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 537 value &= SPC_MSGU_CFG_TABLE_UPDATE; 538 } while ((value != 0) && (--max_wait_count)); 539 540 if (!max_wait_count) 541 return -1; 542 /* check the MPI-State for initialization */ 543 gst_len_mpistate = 544 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 545 GST_GSTLEN_MPIS_OFFSET); 546 if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK)) 547 return -1; 548 /* check MPI Initialization error */ 549 gst_len_mpistate = gst_len_mpistate >> 16; 550 if (0x0000 != gst_len_mpistate) 551 return -1; 552 return 0; 553 } 554 555 /** 556 * check_fw_ready - The LLDD check if the FW is ready, if not, return error. 557 * @pm8001_ha: our hba card information 558 */ 559 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha) 560 { 561 u32 value, value1; 562 u32 max_wait_count; 563 /* check error state */ 564 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 565 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 566 /* check AAP error */ 567 if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) { 568 /* error state */ 569 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 570 return -1; 571 } 572 573 /* check IOP error */ 574 if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) { 575 /* error state */ 576 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 577 return -1; 578 } 579 580 /* bit 4-31 of scratch pad1 should be zeros if it is not 581 in error state*/ 582 if (value & SCRATCH_PAD1_STATE_MASK) { 583 /* error case */ 584 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 585 return -1; 586 } 587 588 /* bit 2, 4-31 of scratch pad2 should be zeros if it is not 589 in error state */ 590 if (value1 & SCRATCH_PAD2_STATE_MASK) { 591 /* error case */ 592 return -1; 593 } 594 595 max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */ 596 597 /* wait until scratch pad 1 and 2 registers in ready state */ 598 do { 599 udelay(1); 600 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) 601 & SCRATCH_PAD1_RDY; 602 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) 603 & SCRATCH_PAD2_RDY; 604 if ((--max_wait_count) == 0) 605 return -1; 606 } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY)); 607 return 0; 608 } 609 610 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha) 611 { 612 void __iomem *base_addr; 613 u32 value; 614 u32 offset; 615 u32 pcibar; 616 u32 pcilogic; 617 618 value = pm8001_cr32(pm8001_ha, 0, 0x44); 619 offset = value & 0x03FFFFFF; 620 PM8001_INIT_DBG(pm8001_ha, 621 pm8001_printk("Scratchpad 0 Offset: %x\n", offset)); 622 pcilogic = (value & 0xFC000000) >> 26; 623 pcibar = get_pci_bar_index(pcilogic); 624 PM8001_INIT_DBG(pm8001_ha, 625 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar)); 626 pm8001_ha->main_cfg_tbl_addr = base_addr = 627 pm8001_ha->io_mem[pcibar].memvirtaddr + offset; 628 pm8001_ha->general_stat_tbl_addr = 629 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18); 630 pm8001_ha->inbnd_q_tbl_addr = 631 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C); 632 pm8001_ha->outbnd_q_tbl_addr = 633 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20); 634 } 635 636 /** 637 * pm8001_chip_init - the main init function that initialize whole PM8001 chip. 638 * @pm8001_ha: our hba card information 639 */ 640 static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha) 641 { 642 u8 i = 0; 643 u16 deviceid; 644 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid); 645 /* 8081 controllers need BAR shift to access MPI space 646 * as this is shared with BIOS data */ 647 if (deviceid == 0x8081 || deviceid == 0x0042) { 648 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) { 649 PM8001_FAIL_DBG(pm8001_ha, 650 pm8001_printk("Shift Bar4 to 0x%x failed\n", 651 GSM_SM_BASE)); 652 return -1; 653 } 654 } 655 /* check the firmware status */ 656 if (-1 == check_fw_ready(pm8001_ha)) { 657 PM8001_FAIL_DBG(pm8001_ha, 658 pm8001_printk("Firmware is not ready!\n")); 659 return -EBUSY; 660 } 661 662 /* Initialize pci space address eg: mpi offset */ 663 init_pci_device_addresses(pm8001_ha); 664 init_default_table_values(pm8001_ha); 665 read_main_config_table(pm8001_ha); 666 read_general_status_table(pm8001_ha); 667 read_inbnd_queue_table(pm8001_ha); 668 read_outbnd_queue_table(pm8001_ha); 669 /* update main config table ,inbound table and outbound table */ 670 update_main_config_table(pm8001_ha); 671 for (i = 0; i < PM8001_MAX_INB_NUM; i++) 672 update_inbnd_queue_table(pm8001_ha, i); 673 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) 674 update_outbnd_queue_table(pm8001_ha, i); 675 /* 8081 controller donot require these operations */ 676 if (deviceid != 0x8081 && deviceid != 0x0042) { 677 mpi_set_phys_g3_with_ssc(pm8001_ha, 0); 678 /* 7->130ms, 34->500ms, 119->1.5s */ 679 mpi_set_open_retry_interval_reg(pm8001_ha, 119); 680 } 681 /* notify firmware update finished and check initialization status */ 682 if (0 == mpi_init_check(pm8001_ha)) { 683 PM8001_INIT_DBG(pm8001_ha, 684 pm8001_printk("MPI initialize successful!\n")); 685 } else 686 return -EBUSY; 687 /*This register is a 16-bit timer with a resolution of 1us. This is the 688 timer used for interrupt delay/coalescing in the PCIe Application Layer. 689 Zero is not a valid value. A value of 1 in the register will cause the 690 interrupts to be normal. A value greater than 1 will cause coalescing 691 delays.*/ 692 pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1); 693 pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0); 694 return 0; 695 } 696 697 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha) 698 { 699 u32 max_wait_count; 700 u32 value; 701 u32 gst_len_mpistate; 702 u16 deviceid; 703 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid); 704 if (deviceid == 0x8081 || deviceid == 0x0042) { 705 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) { 706 PM8001_FAIL_DBG(pm8001_ha, 707 pm8001_printk("Shift Bar4 to 0x%x failed\n", 708 GSM_SM_BASE)); 709 return -1; 710 } 711 } 712 init_pci_device_addresses(pm8001_ha); 713 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the 714 table is stop */ 715 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET); 716 717 /* wait until Inbound DoorBell Clear Register toggled */ 718 max_wait_count = 1 * 1000 * 1000;/* 1 sec */ 719 do { 720 udelay(1); 721 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 722 value &= SPC_MSGU_CFG_TABLE_RESET; 723 } while ((value != 0) && (--max_wait_count)); 724 725 if (!max_wait_count) { 726 PM8001_FAIL_DBG(pm8001_ha, 727 pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value)); 728 return -1; 729 } 730 731 /* check the MPI-State for termination in progress */ 732 /* wait until Inbound DoorBell Clear Register toggled */ 733 max_wait_count = 1 * 1000 * 1000; /* 1 sec */ 734 do { 735 udelay(1); 736 gst_len_mpistate = 737 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 738 GST_GSTLEN_MPIS_OFFSET); 739 if (GST_MPI_STATE_UNINIT == 740 (gst_len_mpistate & GST_MPI_STATE_MASK)) 741 break; 742 } while (--max_wait_count); 743 if (!max_wait_count) { 744 PM8001_FAIL_DBG(pm8001_ha, 745 pm8001_printk(" TIME OUT MPI State = 0x%x\n", 746 gst_len_mpistate & GST_MPI_STATE_MASK)); 747 return -1; 748 } 749 return 0; 750 } 751 752 /** 753 * soft_reset_ready_check - Function to check FW is ready for soft reset. 754 * @pm8001_ha: our hba card information 755 */ 756 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha) 757 { 758 u32 regVal, regVal1, regVal2; 759 if (mpi_uninit_check(pm8001_ha) != 0) { 760 PM8001_FAIL_DBG(pm8001_ha, 761 pm8001_printk("MPI state is not ready\n")); 762 return -1; 763 } 764 /* read the scratch pad 2 register bit 2 */ 765 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) 766 & SCRATCH_PAD2_FWRDY_RST; 767 if (regVal == SCRATCH_PAD2_FWRDY_RST) { 768 PM8001_INIT_DBG(pm8001_ha, 769 pm8001_printk("Firmware is ready for reset .\n")); 770 } else { 771 unsigned long flags; 772 /* Trigger NMI twice via RB6 */ 773 spin_lock_irqsave(&pm8001_ha->lock, flags); 774 if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) { 775 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 776 PM8001_FAIL_DBG(pm8001_ha, 777 pm8001_printk("Shift Bar4 to 0x%x failed\n", 778 RB6_ACCESS_REG)); 779 return -1; 780 } 781 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, 782 RB6_MAGIC_NUMBER_RST); 783 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST); 784 /* wait for 100 ms */ 785 mdelay(100); 786 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) & 787 SCRATCH_PAD2_FWRDY_RST; 788 if (regVal != SCRATCH_PAD2_FWRDY_RST) { 789 regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 790 regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 791 PM8001_FAIL_DBG(pm8001_ha, 792 pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1" 793 "=0x%x, MSGU_SCRATCH_PAD2=0x%x\n", 794 regVal1, regVal2)); 795 PM8001_FAIL_DBG(pm8001_ha, 796 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n", 797 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0))); 798 PM8001_FAIL_DBG(pm8001_ha, 799 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n", 800 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3))); 801 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 802 return -1; 803 } 804 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 805 } 806 return 0; 807 } 808 809 /** 810 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all 811 * the FW register status to the originated status. 812 * @pm8001_ha: our hba card information 813 */ 814 static int 815 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha) 816 { 817 u32 regVal, toggleVal; 818 u32 max_wait_count; 819 u32 regVal1, regVal2, regVal3; 820 u32 signature = 0x252acbcd; /* for host scratch pad0 */ 821 unsigned long flags; 822 823 /* step1: Check FW is ready for soft reset */ 824 if (soft_reset_ready_check(pm8001_ha) != 0) { 825 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("FW is not ready\n")); 826 return -1; 827 } 828 829 /* step 2: clear NMI status register on AAP1 and IOP, write the same 830 value to clear */ 831 /* map 0x60000 to BAR4(0x20), BAR2(win) */ 832 spin_lock_irqsave(&pm8001_ha->lock, flags); 833 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) { 834 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 835 PM8001_FAIL_DBG(pm8001_ha, 836 pm8001_printk("Shift Bar4 to 0x%x failed\n", 837 MBIC_AAP1_ADDR_BASE)); 838 return -1; 839 } 840 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP); 841 PM8001_INIT_DBG(pm8001_ha, 842 pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal)); 843 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0); 844 /* map 0x70000 to BAR4(0x20), BAR2(win) */ 845 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) { 846 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 847 PM8001_FAIL_DBG(pm8001_ha, 848 pm8001_printk("Shift Bar4 to 0x%x failed\n", 849 MBIC_IOP_ADDR_BASE)); 850 return -1; 851 } 852 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1); 853 PM8001_INIT_DBG(pm8001_ha, 854 pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal)); 855 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0); 856 857 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE); 858 PM8001_INIT_DBG(pm8001_ha, 859 pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal)); 860 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0); 861 862 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT); 863 PM8001_INIT_DBG(pm8001_ha, 864 pm8001_printk("PCIE - Event Interrupt = 0x%x\n", regVal)); 865 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal); 866 867 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE); 868 PM8001_INIT_DBG(pm8001_ha, 869 pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal)); 870 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0); 871 872 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT); 873 PM8001_INIT_DBG(pm8001_ha, 874 pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal)); 875 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal); 876 877 /* read the scratch pad 1 register bit 2 */ 878 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) 879 & SCRATCH_PAD1_RST; 880 toggleVal = regVal ^ SCRATCH_PAD1_RST; 881 882 /* set signature in host scratch pad0 register to tell SPC that the 883 host performs the soft reset */ 884 pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature); 885 886 /* read required registers for confirmming */ 887 /* map 0x0700000 to BAR4(0x20), BAR2(win) */ 888 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) { 889 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 890 PM8001_FAIL_DBG(pm8001_ha, 891 pm8001_printk("Shift Bar4 to 0x%x failed\n", 892 GSM_ADDR_BASE)); 893 return -1; 894 } 895 PM8001_INIT_DBG(pm8001_ha, 896 pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and" 897 " Reset = 0x%x\n", 898 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); 899 900 /* step 3: host read GSM Configuration and Reset register */ 901 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); 902 /* Put those bits to low */ 903 /* GSM XCBI offset = 0x70 0000 904 0x00 Bit 13 COM_SLV_SW_RSTB 1 905 0x00 Bit 12 QSSP_SW_RSTB 1 906 0x00 Bit 11 RAAE_SW_RSTB 1 907 0x00 Bit 9 RB_1_SW_RSTB 1 908 0x00 Bit 8 SM_SW_RSTB 1 909 */ 910 regVal &= ~(0x00003b00); 911 /* host write GSM Configuration and Reset register */ 912 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); 913 PM8001_INIT_DBG(pm8001_ha, 914 pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM " 915 "Configuration and Reset is set to = 0x%x\n", 916 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); 917 918 /* step 4: */ 919 /* disable GSM - Read Address Parity Check */ 920 regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK); 921 PM8001_INIT_DBG(pm8001_ha, 922 pm8001_printk("GSM 0x700038 - Read Address Parity Check " 923 "Enable = 0x%x\n", regVal1)); 924 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0); 925 PM8001_INIT_DBG(pm8001_ha, 926 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable" 927 "is set to = 0x%x\n", 928 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK))); 929 930 /* disable GSM - Write Address Parity Check */ 931 regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK); 932 PM8001_INIT_DBG(pm8001_ha, 933 pm8001_printk("GSM 0x700040 - Write Address Parity Check" 934 " Enable = 0x%x\n", regVal2)); 935 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0); 936 PM8001_INIT_DBG(pm8001_ha, 937 pm8001_printk("GSM 0x700040 - Write Address Parity Check " 938 "Enable is set to = 0x%x\n", 939 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK))); 940 941 /* disable GSM - Write Data Parity Check */ 942 regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK); 943 PM8001_INIT_DBG(pm8001_ha, 944 pm8001_printk("GSM 0x300048 - Write Data Parity Check" 945 " Enable = 0x%x\n", regVal3)); 946 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0); 947 PM8001_INIT_DBG(pm8001_ha, 948 pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable" 949 "is set to = 0x%x\n", 950 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK))); 951 952 /* step 5: delay 10 usec */ 953 udelay(10); 954 /* step 5-b: set GPIO-0 output control to tristate anyway */ 955 if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) { 956 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 957 PM8001_INIT_DBG(pm8001_ha, 958 pm8001_printk("Shift Bar4 to 0x%x failed\n", 959 GPIO_ADDR_BASE)); 960 return -1; 961 } 962 regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET); 963 PM8001_INIT_DBG(pm8001_ha, 964 pm8001_printk("GPIO Output Control Register:" 965 " = 0x%x\n", regVal)); 966 /* set GPIO-0 output control to tri-state */ 967 regVal &= 0xFFFFFFFC; 968 pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal); 969 970 /* Step 6: Reset the IOP and AAP1 */ 971 /* map 0x00000 to BAR4(0x20), BAR2(win) */ 972 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) { 973 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 974 PM8001_FAIL_DBG(pm8001_ha, 975 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n", 976 SPC_TOP_LEVEL_ADDR_BASE)); 977 return -1; 978 } 979 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 980 PM8001_INIT_DBG(pm8001_ha, 981 pm8001_printk("Top Register before resetting IOP/AAP1" 982 ":= 0x%x\n", regVal)); 983 regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS); 984 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 985 986 /* step 7: Reset the BDMA/OSSP */ 987 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 988 PM8001_INIT_DBG(pm8001_ha, 989 pm8001_printk("Top Register before resetting BDMA/OSSP" 990 ": = 0x%x\n", regVal)); 991 regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP); 992 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 993 994 /* step 8: delay 10 usec */ 995 udelay(10); 996 997 /* step 9: bring the BDMA and OSSP out of reset */ 998 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 999 PM8001_INIT_DBG(pm8001_ha, 1000 pm8001_printk("Top Register before bringing up BDMA/OSSP" 1001 ":= 0x%x\n", regVal)); 1002 regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP); 1003 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 1004 1005 /* step 10: delay 10 usec */ 1006 udelay(10); 1007 1008 /* step 11: reads and sets the GSM Configuration and Reset Register */ 1009 /* map 0x0700000 to BAR4(0x20), BAR2(win) */ 1010 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) { 1011 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1012 PM8001_FAIL_DBG(pm8001_ha, 1013 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n", 1014 GSM_ADDR_BASE)); 1015 return -1; 1016 } 1017 PM8001_INIT_DBG(pm8001_ha, 1018 pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and " 1019 "Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); 1020 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); 1021 /* Put those bits to high */ 1022 /* GSM XCBI offset = 0x70 0000 1023 0x00 Bit 13 COM_SLV_SW_RSTB 1 1024 0x00 Bit 12 QSSP_SW_RSTB 1 1025 0x00 Bit 11 RAAE_SW_RSTB 1 1026 0x00 Bit 9 RB_1_SW_RSTB 1 1027 0x00 Bit 8 SM_SW_RSTB 1 1028 */ 1029 regVal |= (GSM_CONFIG_RESET_VALUE); 1030 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); 1031 PM8001_INIT_DBG(pm8001_ha, 1032 pm8001_printk("GSM (0x00004088 ==> 0x00007b88) - GSM" 1033 " Configuration and Reset is set to = 0x%x\n", 1034 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); 1035 1036 /* step 12: Restore GSM - Read Address Parity Check */ 1037 regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK); 1038 /* just for debugging */ 1039 PM8001_INIT_DBG(pm8001_ha, 1040 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable" 1041 " = 0x%x\n", regVal)); 1042 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1); 1043 PM8001_INIT_DBG(pm8001_ha, 1044 pm8001_printk("GSM 0x700038 - Read Address Parity" 1045 " Check Enable is set to = 0x%x\n", 1046 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK))); 1047 /* Restore GSM - Write Address Parity Check */ 1048 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK); 1049 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2); 1050 PM8001_INIT_DBG(pm8001_ha, 1051 pm8001_printk("GSM 0x700040 - Write Address Parity Check" 1052 " Enable is set to = 0x%x\n", 1053 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK))); 1054 /* Restore GSM - Write Data Parity Check */ 1055 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK); 1056 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3); 1057 PM8001_INIT_DBG(pm8001_ha, 1058 pm8001_printk("GSM 0x700048 - Write Data Parity Check Enable" 1059 "is set to = 0x%x\n", 1060 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK))); 1061 1062 /* step 13: bring the IOP and AAP1 out of reset */ 1063 /* map 0x00000 to BAR4(0x20), BAR2(win) */ 1064 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) { 1065 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1066 PM8001_FAIL_DBG(pm8001_ha, 1067 pm8001_printk("Shift Bar4 to 0x%x failed\n", 1068 SPC_TOP_LEVEL_ADDR_BASE)); 1069 return -1; 1070 } 1071 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 1072 regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS); 1073 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 1074 1075 /* step 14: delay 10 usec - Normal Mode */ 1076 udelay(10); 1077 /* check Soft Reset Normal mode or Soft Reset HDA mode */ 1078 if (signature == SPC_SOFT_RESET_SIGNATURE) { 1079 /* step 15 (Normal Mode): wait until scratch pad1 register 1080 bit 2 toggled */ 1081 max_wait_count = 2 * 1000 * 1000;/* 2 sec */ 1082 do { 1083 udelay(1); 1084 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) & 1085 SCRATCH_PAD1_RST; 1086 } while ((regVal != toggleVal) && (--max_wait_count)); 1087 1088 if (!max_wait_count) { 1089 regVal = pm8001_cr32(pm8001_ha, 0, 1090 MSGU_SCRATCH_PAD_1); 1091 PM8001_FAIL_DBG(pm8001_ha, 1092 pm8001_printk("TIMEOUT : ToggleVal 0x%x," 1093 "MSGU_SCRATCH_PAD1 = 0x%x\n", 1094 toggleVal, regVal)); 1095 PM8001_FAIL_DBG(pm8001_ha, 1096 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n", 1097 pm8001_cr32(pm8001_ha, 0, 1098 MSGU_SCRATCH_PAD_0))); 1099 PM8001_FAIL_DBG(pm8001_ha, 1100 pm8001_printk("SCRATCH_PAD2 value = 0x%x\n", 1101 pm8001_cr32(pm8001_ha, 0, 1102 MSGU_SCRATCH_PAD_2))); 1103 PM8001_FAIL_DBG(pm8001_ha, 1104 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n", 1105 pm8001_cr32(pm8001_ha, 0, 1106 MSGU_SCRATCH_PAD_3))); 1107 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1108 return -1; 1109 } 1110 1111 /* step 16 (Normal) - Clear ODMR and ODCR */ 1112 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); 1113 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); 1114 1115 /* step 17 (Normal Mode): wait for the FW and IOP to get 1116 ready - 1 sec timeout */ 1117 /* Wait for the SPC Configuration Table to be ready */ 1118 if (check_fw_ready(pm8001_ha) == -1) { 1119 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1120 /* return error if MPI Configuration Table not ready */ 1121 PM8001_INIT_DBG(pm8001_ha, 1122 pm8001_printk("FW not ready SCRATCH_PAD1" 1123 " = 0x%x\n", regVal)); 1124 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 1125 /* return error if MPI Configuration Table not ready */ 1126 PM8001_INIT_DBG(pm8001_ha, 1127 pm8001_printk("FW not ready SCRATCH_PAD2" 1128 " = 0x%x\n", regVal)); 1129 PM8001_INIT_DBG(pm8001_ha, 1130 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n", 1131 pm8001_cr32(pm8001_ha, 0, 1132 MSGU_SCRATCH_PAD_0))); 1133 PM8001_INIT_DBG(pm8001_ha, 1134 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n", 1135 pm8001_cr32(pm8001_ha, 0, 1136 MSGU_SCRATCH_PAD_3))); 1137 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1138 return -1; 1139 } 1140 } 1141 pm8001_bar4_shift(pm8001_ha, 0); 1142 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1143 1144 PM8001_INIT_DBG(pm8001_ha, 1145 pm8001_printk("SPC soft reset Complete\n")); 1146 return 0; 1147 } 1148 1149 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha) 1150 { 1151 u32 i; 1152 u32 regVal; 1153 PM8001_INIT_DBG(pm8001_ha, 1154 pm8001_printk("chip reset start\n")); 1155 1156 /* do SPC chip reset. */ 1157 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); 1158 regVal &= ~(SPC_REG_RESET_DEVICE); 1159 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); 1160 1161 /* delay 10 usec */ 1162 udelay(10); 1163 1164 /* bring chip reset out of reset */ 1165 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); 1166 regVal |= SPC_REG_RESET_DEVICE; 1167 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); 1168 1169 /* delay 10 usec */ 1170 udelay(10); 1171 1172 /* wait for 20 msec until the firmware gets reloaded */ 1173 i = 20; 1174 do { 1175 mdelay(1); 1176 } while ((--i) != 0); 1177 1178 PM8001_INIT_DBG(pm8001_ha, 1179 pm8001_printk("chip reset finished\n")); 1180 } 1181 1182 /** 1183 * pm8001_chip_iounmap - which maped when initialized. 1184 * @pm8001_ha: our hba card information 1185 */ 1186 void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha) 1187 { 1188 s8 bar, logical = 0; 1189 for (bar = 0; bar < 6; bar++) { 1190 /* 1191 ** logical BARs for SPC: 1192 ** bar 0 and 1 - logical BAR0 1193 ** bar 2 and 3 - logical BAR1 1194 ** bar4 - logical BAR2 1195 ** bar5 - logical BAR3 1196 ** Skip the appropriate assignments: 1197 */ 1198 if ((bar == 1) || (bar == 3)) 1199 continue; 1200 if (pm8001_ha->io_mem[logical].memvirtaddr) { 1201 iounmap(pm8001_ha->io_mem[logical].memvirtaddr); 1202 logical++; 1203 } 1204 } 1205 } 1206 1207 /** 1208 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt 1209 * @pm8001_ha: our hba card information 1210 */ 1211 static void 1212 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha) 1213 { 1214 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); 1215 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); 1216 } 1217 1218 /** 1219 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt 1220 * @pm8001_ha: our hba card information 1221 */ 1222 static void 1223 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha) 1224 { 1225 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL); 1226 } 1227 1228 /** 1229 * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt 1230 * @pm8001_ha: our hba card information 1231 */ 1232 static void 1233 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha, 1234 u32 int_vec_idx) 1235 { 1236 u32 msi_index; 1237 u32 value; 1238 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE; 1239 msi_index += MSIX_TABLE_BASE; 1240 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE); 1241 value = (1 << int_vec_idx); 1242 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, value); 1243 1244 } 1245 1246 /** 1247 * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt 1248 * @pm8001_ha: our hba card information 1249 */ 1250 static void 1251 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha, 1252 u32 int_vec_idx) 1253 { 1254 u32 msi_index; 1255 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE; 1256 msi_index += MSIX_TABLE_BASE; 1257 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE); 1258 } 1259 1260 /** 1261 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt 1262 * @pm8001_ha: our hba card information 1263 */ 1264 static void 1265 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1266 { 1267 #ifdef PM8001_USE_MSIX 1268 pm8001_chip_msix_interrupt_enable(pm8001_ha, 0); 1269 return; 1270 #endif 1271 pm8001_chip_intx_interrupt_enable(pm8001_ha); 1272 1273 } 1274 1275 /** 1276 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt 1277 * @pm8001_ha: our hba card information 1278 */ 1279 static void 1280 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1281 { 1282 #ifdef PM8001_USE_MSIX 1283 pm8001_chip_msix_interrupt_disable(pm8001_ha, 0); 1284 return; 1285 #endif 1286 pm8001_chip_intx_interrupt_disable(pm8001_ha); 1287 1288 } 1289 1290 /** 1291 * pm8001_mpi_msg_free_get - get the free message buffer for transfer 1292 * inbound queue. 1293 * @circularQ: the inbound queue we want to transfer to HBA. 1294 * @messageSize: the message size of this transfer, normally it is 64 bytes 1295 * @messagePtr: the pointer to message. 1296 */ 1297 int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ, 1298 u16 messageSize, void **messagePtr) 1299 { 1300 u32 offset, consumer_index; 1301 struct mpi_msg_hdr *msgHeader; 1302 u8 bcCount = 1; /* only support single buffer */ 1303 1304 /* Checks is the requested message size can be allocated in this queue*/ 1305 if (messageSize > IOMB_SIZE_SPCV) { 1306 *messagePtr = NULL; 1307 return -1; 1308 } 1309 1310 /* Stores the new consumer index */ 1311 consumer_index = pm8001_read_32(circularQ->ci_virt); 1312 circularQ->consumer_index = cpu_to_le32(consumer_index); 1313 if (((circularQ->producer_idx + bcCount) % PM8001_MPI_QUEUE) == 1314 le32_to_cpu(circularQ->consumer_index)) { 1315 *messagePtr = NULL; 1316 return -1; 1317 } 1318 /* get memory IOMB buffer address */ 1319 offset = circularQ->producer_idx * messageSize; 1320 /* increment to next bcCount element */ 1321 circularQ->producer_idx = (circularQ->producer_idx + bcCount) 1322 % PM8001_MPI_QUEUE; 1323 /* Adds that distance to the base of the region virtual address plus 1324 the message header size*/ 1325 msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset); 1326 *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr); 1327 return 0; 1328 } 1329 1330 /** 1331 * pm8001_mpi_build_cmd- build the message queue for transfer, update the PI to 1332 * FW to tell the fw to get this message from IOMB. 1333 * @pm8001_ha: our hba card information 1334 * @circularQ: the inbound queue we want to transfer to HBA. 1335 * @opCode: the operation code represents commands which LLDD and fw recognized. 1336 * @payload: the command payload of each operation command. 1337 */ 1338 int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha, 1339 struct inbound_queue_table *circularQ, 1340 u32 opCode, void *payload, u32 responseQueue) 1341 { 1342 u32 Header = 0, hpriority = 0, bc = 1, category = 0x02; 1343 void *pMessage; 1344 1345 if (pm8001_mpi_msg_free_get(circularQ, pm8001_ha->iomb_size, 1346 &pMessage) < 0) { 1347 PM8001_IO_DBG(pm8001_ha, 1348 pm8001_printk("No free mpi buffer\n")); 1349 return -1; 1350 } 1351 BUG_ON(!payload); 1352 /*Copy to the payload*/ 1353 memcpy(pMessage, payload, (pm8001_ha->iomb_size - 1354 sizeof(struct mpi_msg_hdr))); 1355 1356 /*Build the header*/ 1357 Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24) 1358 | ((responseQueue & 0x3F) << 16) 1359 | ((category & 0xF) << 12) | (opCode & 0xFFF)); 1360 1361 pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header)); 1362 /*Update the PI to the firmware*/ 1363 pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar, 1364 circularQ->pi_offset, circularQ->producer_idx); 1365 PM8001_IO_DBG(pm8001_ha, 1366 pm8001_printk("INB Q %x OPCODE:%x , UPDATED PI=%d CI=%d\n", 1367 responseQueue, opCode, circularQ->producer_idx, 1368 circularQ->consumer_index)); 1369 return 0; 1370 } 1371 1372 u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg, 1373 struct outbound_queue_table *circularQ, u8 bc) 1374 { 1375 u32 producer_index; 1376 struct mpi_msg_hdr *msgHeader; 1377 struct mpi_msg_hdr *pOutBoundMsgHeader; 1378 1379 msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr)); 1380 pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + 1381 circularQ->consumer_idx * pm8001_ha->iomb_size); 1382 if (pOutBoundMsgHeader != msgHeader) { 1383 PM8001_FAIL_DBG(pm8001_ha, 1384 pm8001_printk("consumer_idx = %d msgHeader = %p\n", 1385 circularQ->consumer_idx, msgHeader)); 1386 1387 /* Update the producer index from SPC */ 1388 producer_index = pm8001_read_32(circularQ->pi_virt); 1389 circularQ->producer_index = cpu_to_le32(producer_index); 1390 PM8001_FAIL_DBG(pm8001_ha, 1391 pm8001_printk("consumer_idx = %d producer_index = %d" 1392 "msgHeader = %p\n", circularQ->consumer_idx, 1393 circularQ->producer_index, msgHeader)); 1394 return 0; 1395 } 1396 /* free the circular queue buffer elements associated with the message*/ 1397 circularQ->consumer_idx = (circularQ->consumer_idx + bc) 1398 % PM8001_MPI_QUEUE; 1399 /* update the CI of outbound queue */ 1400 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset, 1401 circularQ->consumer_idx); 1402 /* Update the producer index from SPC*/ 1403 producer_index = pm8001_read_32(circularQ->pi_virt); 1404 circularQ->producer_index = cpu_to_le32(producer_index); 1405 PM8001_IO_DBG(pm8001_ha, 1406 pm8001_printk(" CI=%d PI=%d\n", circularQ->consumer_idx, 1407 circularQ->producer_index)); 1408 return 0; 1409 } 1410 1411 /** 1412 * pm8001_mpi_msg_consume- get the MPI message from outbound queue 1413 * message table. 1414 * @pm8001_ha: our hba card information 1415 * @circularQ: the outbound queue table. 1416 * @messagePtr1: the message contents of this outbound message. 1417 * @pBC: the message size. 1418 */ 1419 u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha, 1420 struct outbound_queue_table *circularQ, 1421 void **messagePtr1, u8 *pBC) 1422 { 1423 struct mpi_msg_hdr *msgHeader; 1424 __le32 msgHeader_tmp; 1425 u32 header_tmp; 1426 do { 1427 /* If there are not-yet-delivered messages ... */ 1428 if (le32_to_cpu(circularQ->producer_index) 1429 != circularQ->consumer_idx) { 1430 /*Get the pointer to the circular queue buffer element*/ 1431 msgHeader = (struct mpi_msg_hdr *) 1432 (circularQ->base_virt + 1433 circularQ->consumer_idx * pm8001_ha->iomb_size); 1434 /* read header */ 1435 header_tmp = pm8001_read_32(msgHeader); 1436 msgHeader_tmp = cpu_to_le32(header_tmp); 1437 if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) { 1438 if (OPC_OUB_SKIP_ENTRY != 1439 (le32_to_cpu(msgHeader_tmp) & 0xfff)) { 1440 *messagePtr1 = 1441 ((u8 *)msgHeader) + 1442 sizeof(struct mpi_msg_hdr); 1443 *pBC = (u8)((le32_to_cpu(msgHeader_tmp) 1444 >> 24) & 0x1f); 1445 PM8001_IO_DBG(pm8001_ha, 1446 pm8001_printk(": CI=%d PI=%d " 1447 "msgHeader=%x\n", 1448 circularQ->consumer_idx, 1449 circularQ->producer_index, 1450 msgHeader_tmp)); 1451 return MPI_IO_STATUS_SUCCESS; 1452 } else { 1453 circularQ->consumer_idx = 1454 (circularQ->consumer_idx + 1455 ((le32_to_cpu(msgHeader_tmp) 1456 >> 24) & 0x1f)) 1457 % PM8001_MPI_QUEUE; 1458 msgHeader_tmp = 0; 1459 pm8001_write_32(msgHeader, 0, 0); 1460 /* update the CI of outbound queue */ 1461 pm8001_cw32(pm8001_ha, 1462 circularQ->ci_pci_bar, 1463 circularQ->ci_offset, 1464 circularQ->consumer_idx); 1465 } 1466 } else { 1467 circularQ->consumer_idx = 1468 (circularQ->consumer_idx + 1469 ((le32_to_cpu(msgHeader_tmp) >> 24) & 1470 0x1f)) % PM8001_MPI_QUEUE; 1471 msgHeader_tmp = 0; 1472 pm8001_write_32(msgHeader, 0, 0); 1473 /* update the CI of outbound queue */ 1474 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, 1475 circularQ->ci_offset, 1476 circularQ->consumer_idx); 1477 return MPI_IO_STATUS_FAIL; 1478 } 1479 } else { 1480 u32 producer_index; 1481 void *pi_virt = circularQ->pi_virt; 1482 /* Update the producer index from SPC */ 1483 producer_index = pm8001_read_32(pi_virt); 1484 circularQ->producer_index = cpu_to_le32(producer_index); 1485 } 1486 } while (le32_to_cpu(circularQ->producer_index) != 1487 circularQ->consumer_idx); 1488 /* while we don't have any more not-yet-delivered message */ 1489 /* report empty */ 1490 return MPI_IO_STATUS_BUSY; 1491 } 1492 1493 void pm8001_work_fn(struct work_struct *work) 1494 { 1495 struct pm8001_work *pw = container_of(work, struct pm8001_work, work); 1496 struct pm8001_device *pm8001_dev; 1497 struct domain_device *dev; 1498 1499 /* 1500 * So far, all users of this stash an associated structure here. 1501 * If we get here, and this pointer is null, then the action 1502 * was cancelled. This nullification happens when the device 1503 * goes away. 1504 */ 1505 pm8001_dev = pw->data; /* Most stash device structure */ 1506 if ((pm8001_dev == NULL) 1507 || ((pw->handler != IO_XFER_ERROR_BREAK) 1508 && (pm8001_dev->dev_type == SAS_PHY_UNUSED))) { 1509 kfree(pw); 1510 return; 1511 } 1512 1513 switch (pw->handler) { 1514 case IO_XFER_ERROR_BREAK: 1515 { /* This one stashes the sas_task instead */ 1516 struct sas_task *t = (struct sas_task *)pm8001_dev; 1517 u32 tag; 1518 struct pm8001_ccb_info *ccb; 1519 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha; 1520 unsigned long flags, flags1; 1521 struct task_status_struct *ts; 1522 int i; 1523 1524 if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC) 1525 break; /* Task still on lu */ 1526 spin_lock_irqsave(&pm8001_ha->lock, flags); 1527 1528 spin_lock_irqsave(&t->task_state_lock, flags1); 1529 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) { 1530 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1531 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1532 break; /* Task got completed by another */ 1533 } 1534 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1535 1536 /* Search for a possible ccb that matches the task */ 1537 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) { 1538 ccb = &pm8001_ha->ccb_info[i]; 1539 tag = ccb->ccb_tag; 1540 if ((tag != 0xFFFFFFFF) && (ccb->task == t)) 1541 break; 1542 } 1543 if (!ccb) { 1544 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1545 break; /* Task got freed by another */ 1546 } 1547 ts = &t->task_status; 1548 ts->resp = SAS_TASK_COMPLETE; 1549 /* Force the midlayer to retry */ 1550 ts->stat = SAS_QUEUE_FULL; 1551 pm8001_dev = ccb->device; 1552 if (pm8001_dev) 1553 pm8001_dev->running_req--; 1554 spin_lock_irqsave(&t->task_state_lock, flags1); 1555 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 1556 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 1557 t->task_state_flags |= SAS_TASK_STATE_DONE; 1558 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 1559 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1560 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p" 1561 " done with event 0x%x resp 0x%x stat 0x%x but" 1562 " aborted by upper layer!\n", 1563 t, pw->handler, ts->resp, ts->stat)); 1564 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1565 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1566 } else { 1567 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1568 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1569 mb();/* in order to force CPU ordering */ 1570 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1571 t->task_done(t); 1572 } 1573 } break; 1574 case IO_XFER_OPEN_RETRY_TIMEOUT: 1575 { /* This one stashes the sas_task instead */ 1576 struct sas_task *t = (struct sas_task *)pm8001_dev; 1577 u32 tag; 1578 struct pm8001_ccb_info *ccb; 1579 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha; 1580 unsigned long flags, flags1; 1581 int i, ret = 0; 1582 1583 PM8001_IO_DBG(pm8001_ha, 1584 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 1585 1586 ret = pm8001_query_task(t); 1587 1588 PM8001_IO_DBG(pm8001_ha, 1589 switch (ret) { 1590 case TMF_RESP_FUNC_SUCC: 1591 pm8001_printk("...Task on lu\n"); 1592 break; 1593 1594 case TMF_RESP_FUNC_COMPLETE: 1595 pm8001_printk("...Task NOT on lu\n"); 1596 break; 1597 1598 default: 1599 pm8001_printk("...query task failed!!!\n"); 1600 break; 1601 }); 1602 1603 spin_lock_irqsave(&pm8001_ha->lock, flags); 1604 1605 spin_lock_irqsave(&t->task_state_lock, flags1); 1606 1607 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) { 1608 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1609 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1610 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */ 1611 (void)pm8001_abort_task(t); 1612 break; /* Task got completed by another */ 1613 } 1614 1615 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1616 1617 /* Search for a possible ccb that matches the task */ 1618 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) { 1619 ccb = &pm8001_ha->ccb_info[i]; 1620 tag = ccb->ccb_tag; 1621 if ((tag != 0xFFFFFFFF) && (ccb->task == t)) 1622 break; 1623 } 1624 if (!ccb) { 1625 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1626 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */ 1627 (void)pm8001_abort_task(t); 1628 break; /* Task got freed by another */ 1629 } 1630 1631 pm8001_dev = ccb->device; 1632 dev = pm8001_dev->sas_device; 1633 1634 switch (ret) { 1635 case TMF_RESP_FUNC_SUCC: /* task on lu */ 1636 ccb->open_retry = 1; /* Snub completion */ 1637 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1638 ret = pm8001_abort_task(t); 1639 ccb->open_retry = 0; 1640 switch (ret) { 1641 case TMF_RESP_FUNC_SUCC: 1642 case TMF_RESP_FUNC_COMPLETE: 1643 break; 1644 default: /* device misbehavior */ 1645 ret = TMF_RESP_FUNC_FAILED; 1646 PM8001_IO_DBG(pm8001_ha, 1647 pm8001_printk("...Reset phy\n")); 1648 pm8001_I_T_nexus_reset(dev); 1649 break; 1650 } 1651 break; 1652 1653 case TMF_RESP_FUNC_COMPLETE: /* task not on lu */ 1654 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1655 /* Do we need to abort the task locally? */ 1656 break; 1657 1658 default: /* device misbehavior */ 1659 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1660 ret = TMF_RESP_FUNC_FAILED; 1661 PM8001_IO_DBG(pm8001_ha, 1662 pm8001_printk("...Reset phy\n")); 1663 pm8001_I_T_nexus_reset(dev); 1664 } 1665 1666 if (ret == TMF_RESP_FUNC_FAILED) 1667 t = NULL; 1668 pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev); 1669 PM8001_IO_DBG(pm8001_ha, pm8001_printk("...Complete\n")); 1670 } break; 1671 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1672 dev = pm8001_dev->sas_device; 1673 pm8001_I_T_nexus_event_handler(dev); 1674 break; 1675 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 1676 dev = pm8001_dev->sas_device; 1677 pm8001_I_T_nexus_reset(dev); 1678 break; 1679 case IO_DS_IN_ERROR: 1680 dev = pm8001_dev->sas_device; 1681 pm8001_I_T_nexus_reset(dev); 1682 break; 1683 case IO_DS_NON_OPERATIONAL: 1684 dev = pm8001_dev->sas_device; 1685 pm8001_I_T_nexus_reset(dev); 1686 break; 1687 } 1688 kfree(pw); 1689 } 1690 1691 int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data, 1692 int handler) 1693 { 1694 struct pm8001_work *pw; 1695 int ret = 0; 1696 1697 pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC); 1698 if (pw) { 1699 pw->pm8001_ha = pm8001_ha; 1700 pw->data = data; 1701 pw->handler = handler; 1702 INIT_WORK(&pw->work, pm8001_work_fn); 1703 queue_work(pm8001_wq, &pw->work); 1704 } else 1705 ret = -ENOMEM; 1706 1707 return ret; 1708 } 1709 1710 static void pm8001_send_abort_all(struct pm8001_hba_info *pm8001_ha, 1711 struct pm8001_device *pm8001_ha_dev) 1712 { 1713 int res; 1714 u32 ccb_tag; 1715 struct pm8001_ccb_info *ccb; 1716 struct sas_task *task = NULL; 1717 struct task_abort_req task_abort; 1718 struct inbound_queue_table *circularQ; 1719 u32 opc = OPC_INB_SATA_ABORT; 1720 int ret; 1721 1722 if (!pm8001_ha_dev) { 1723 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n")); 1724 return; 1725 } 1726 1727 task = sas_alloc_slow_task(GFP_ATOMIC); 1728 1729 if (!task) { 1730 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot " 1731 "allocate task\n")); 1732 return; 1733 } 1734 1735 task->task_done = pm8001_task_done; 1736 1737 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); 1738 if (res) 1739 return; 1740 1741 ccb = &pm8001_ha->ccb_info[ccb_tag]; 1742 ccb->device = pm8001_ha_dev; 1743 ccb->ccb_tag = ccb_tag; 1744 ccb->task = task; 1745 1746 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1747 1748 memset(&task_abort, 0, sizeof(task_abort)); 1749 task_abort.abort_all = cpu_to_le32(1); 1750 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 1751 task_abort.tag = cpu_to_le32(ccb_tag); 1752 1753 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0); 1754 1755 } 1756 1757 static void pm8001_send_read_log(struct pm8001_hba_info *pm8001_ha, 1758 struct pm8001_device *pm8001_ha_dev) 1759 { 1760 struct sata_start_req sata_cmd; 1761 int res; 1762 u32 ccb_tag; 1763 struct pm8001_ccb_info *ccb; 1764 struct sas_task *task = NULL; 1765 struct host_to_dev_fis fis; 1766 struct domain_device *dev; 1767 struct inbound_queue_table *circularQ; 1768 u32 opc = OPC_INB_SATA_HOST_OPSTART; 1769 1770 task = sas_alloc_slow_task(GFP_ATOMIC); 1771 1772 if (!task) { 1773 PM8001_FAIL_DBG(pm8001_ha, 1774 pm8001_printk("cannot allocate task !!!\n")); 1775 return; 1776 } 1777 task->task_done = pm8001_task_done; 1778 1779 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); 1780 if (res) { 1781 PM8001_FAIL_DBG(pm8001_ha, 1782 pm8001_printk("cannot allocate tag !!!\n")); 1783 return; 1784 } 1785 1786 /* allocate domain device by ourselves as libsas 1787 * is not going to provide any 1788 */ 1789 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC); 1790 if (!dev) { 1791 PM8001_FAIL_DBG(pm8001_ha, 1792 pm8001_printk("Domain device cannot be allocated\n")); 1793 sas_free_task(task); 1794 return; 1795 } else { 1796 task->dev = dev; 1797 task->dev->lldd_dev = pm8001_ha_dev; 1798 } 1799 1800 ccb = &pm8001_ha->ccb_info[ccb_tag]; 1801 ccb->device = pm8001_ha_dev; 1802 ccb->ccb_tag = ccb_tag; 1803 ccb->task = task; 1804 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG; 1805 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG; 1806 1807 memset(&sata_cmd, 0, sizeof(sata_cmd)); 1808 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1809 1810 /* construct read log FIS */ 1811 memset(&fis, 0, sizeof(struct host_to_dev_fis)); 1812 fis.fis_type = 0x27; 1813 fis.flags = 0x80; 1814 fis.command = ATA_CMD_READ_LOG_EXT; 1815 fis.lbal = 0x10; 1816 fis.sector_count = 0x1; 1817 1818 sata_cmd.tag = cpu_to_le32(ccb_tag); 1819 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 1820 sata_cmd.ncqtag_atap_dir_m |= ((0x1 << 7) | (0x5 << 9)); 1821 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis)); 1822 1823 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0); 1824 1825 } 1826 1827 /** 1828 * mpi_ssp_completion- process the event that FW response to the SSP request. 1829 * @pm8001_ha: our hba card information 1830 * @piomb: the message contents of this outbound message. 1831 * 1832 * When FW has completed a ssp request for example a IO request, after it has 1833 * filled the SG data with the data, it will trigger this event represent 1834 * that he has finished the job,please check the coresponding buffer. 1835 * So we will tell the caller who maybe waiting the result to tell upper layer 1836 * that the task has been finished. 1837 */ 1838 static void 1839 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb) 1840 { 1841 struct sas_task *t; 1842 struct pm8001_ccb_info *ccb; 1843 unsigned long flags; 1844 u32 status; 1845 u32 param; 1846 u32 tag; 1847 struct ssp_completion_resp *psspPayload; 1848 struct task_status_struct *ts; 1849 struct ssp_response_iu *iu; 1850 struct pm8001_device *pm8001_dev; 1851 psspPayload = (struct ssp_completion_resp *)(piomb + 4); 1852 status = le32_to_cpu(psspPayload->status); 1853 tag = le32_to_cpu(psspPayload->tag); 1854 ccb = &pm8001_ha->ccb_info[tag]; 1855 if ((status == IO_ABORTED) && ccb->open_retry) { 1856 /* Being completed by another */ 1857 ccb->open_retry = 0; 1858 return; 1859 } 1860 pm8001_dev = ccb->device; 1861 param = le32_to_cpu(psspPayload->param); 1862 1863 t = ccb->task; 1864 1865 if (status && status != IO_UNDERFLOW) 1866 PM8001_FAIL_DBG(pm8001_ha, 1867 pm8001_printk("sas IO status 0x%x\n", status)); 1868 if (unlikely(!t || !t->lldd_task || !t->dev)) 1869 return; 1870 ts = &t->task_status; 1871 /* Print sas address of IO failed device */ 1872 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 1873 (status != IO_UNDERFLOW)) 1874 PM8001_FAIL_DBG(pm8001_ha, 1875 pm8001_printk("SAS Address of IO Failure Drive:" 1876 "%016llx", SAS_ADDR(t->dev->sas_addr))); 1877 1878 switch (status) { 1879 case IO_SUCCESS: 1880 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS" 1881 ",param = %d\n", param)); 1882 if (param == 0) { 1883 ts->resp = SAS_TASK_COMPLETE; 1884 ts->stat = SAM_STAT_GOOD; 1885 } else { 1886 ts->resp = SAS_TASK_COMPLETE; 1887 ts->stat = SAS_PROTO_RESPONSE; 1888 ts->residual = param; 1889 iu = &psspPayload->ssp_resp_iu; 1890 sas_ssp_task_response(pm8001_ha->dev, t, iu); 1891 } 1892 if (pm8001_dev) 1893 pm8001_dev->running_req--; 1894 break; 1895 case IO_ABORTED: 1896 PM8001_IO_DBG(pm8001_ha, 1897 pm8001_printk("IO_ABORTED IOMB Tag\n")); 1898 ts->resp = SAS_TASK_COMPLETE; 1899 ts->stat = SAS_ABORTED_TASK; 1900 break; 1901 case IO_UNDERFLOW: 1902 /* SSP Completion with error */ 1903 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW" 1904 ",param = %d\n", param)); 1905 ts->resp = SAS_TASK_COMPLETE; 1906 ts->stat = SAS_DATA_UNDERRUN; 1907 ts->residual = param; 1908 if (pm8001_dev) 1909 pm8001_dev->running_req--; 1910 break; 1911 case IO_NO_DEVICE: 1912 PM8001_IO_DBG(pm8001_ha, 1913 pm8001_printk("IO_NO_DEVICE\n")); 1914 ts->resp = SAS_TASK_UNDELIVERED; 1915 ts->stat = SAS_PHY_DOWN; 1916 break; 1917 case IO_XFER_ERROR_BREAK: 1918 PM8001_IO_DBG(pm8001_ha, 1919 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 1920 ts->resp = SAS_TASK_COMPLETE; 1921 ts->stat = SAS_OPEN_REJECT; 1922 /* Force the midlayer to retry */ 1923 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1924 break; 1925 case IO_XFER_ERROR_PHY_NOT_READY: 1926 PM8001_IO_DBG(pm8001_ha, 1927 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 1928 ts->resp = SAS_TASK_COMPLETE; 1929 ts->stat = SAS_OPEN_REJECT; 1930 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1931 break; 1932 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 1933 PM8001_IO_DBG(pm8001_ha, 1934 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 1935 ts->resp = SAS_TASK_COMPLETE; 1936 ts->stat = SAS_OPEN_REJECT; 1937 ts->open_rej_reason = SAS_OREJ_EPROTO; 1938 break; 1939 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 1940 PM8001_IO_DBG(pm8001_ha, 1941 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 1942 ts->resp = SAS_TASK_COMPLETE; 1943 ts->stat = SAS_OPEN_REJECT; 1944 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1945 break; 1946 case IO_OPEN_CNX_ERROR_BREAK: 1947 PM8001_IO_DBG(pm8001_ha, 1948 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 1949 ts->resp = SAS_TASK_COMPLETE; 1950 ts->stat = SAS_OPEN_REJECT; 1951 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1952 break; 1953 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1954 PM8001_IO_DBG(pm8001_ha, 1955 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 1956 ts->resp = SAS_TASK_COMPLETE; 1957 ts->stat = SAS_OPEN_REJECT; 1958 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1959 if (!t->uldd_task) 1960 pm8001_handle_event(pm8001_ha, 1961 pm8001_dev, 1962 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 1963 break; 1964 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 1965 PM8001_IO_DBG(pm8001_ha, 1966 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 1967 ts->resp = SAS_TASK_COMPLETE; 1968 ts->stat = SAS_OPEN_REJECT; 1969 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 1970 break; 1971 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 1972 PM8001_IO_DBG(pm8001_ha, 1973 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 1974 "NOT_SUPPORTED\n")); 1975 ts->resp = SAS_TASK_COMPLETE; 1976 ts->stat = SAS_OPEN_REJECT; 1977 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 1978 break; 1979 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 1980 PM8001_IO_DBG(pm8001_ha, 1981 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 1982 ts->resp = SAS_TASK_UNDELIVERED; 1983 ts->stat = SAS_OPEN_REJECT; 1984 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 1985 break; 1986 case IO_XFER_ERROR_NAK_RECEIVED: 1987 PM8001_IO_DBG(pm8001_ha, 1988 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 1989 ts->resp = SAS_TASK_COMPLETE; 1990 ts->stat = SAS_OPEN_REJECT; 1991 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1992 break; 1993 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 1994 PM8001_IO_DBG(pm8001_ha, 1995 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 1996 ts->resp = SAS_TASK_COMPLETE; 1997 ts->stat = SAS_NAK_R_ERR; 1998 break; 1999 case IO_XFER_ERROR_DMA: 2000 PM8001_IO_DBG(pm8001_ha, 2001 pm8001_printk("IO_XFER_ERROR_DMA\n")); 2002 ts->resp = SAS_TASK_COMPLETE; 2003 ts->stat = SAS_OPEN_REJECT; 2004 break; 2005 case IO_XFER_OPEN_RETRY_TIMEOUT: 2006 PM8001_IO_DBG(pm8001_ha, 2007 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2008 ts->resp = SAS_TASK_COMPLETE; 2009 ts->stat = SAS_OPEN_REJECT; 2010 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2011 break; 2012 case IO_XFER_ERROR_OFFSET_MISMATCH: 2013 PM8001_IO_DBG(pm8001_ha, 2014 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 2015 ts->resp = SAS_TASK_COMPLETE; 2016 ts->stat = SAS_OPEN_REJECT; 2017 break; 2018 case IO_PORT_IN_RESET: 2019 PM8001_IO_DBG(pm8001_ha, 2020 pm8001_printk("IO_PORT_IN_RESET\n")); 2021 ts->resp = SAS_TASK_COMPLETE; 2022 ts->stat = SAS_OPEN_REJECT; 2023 break; 2024 case IO_DS_NON_OPERATIONAL: 2025 PM8001_IO_DBG(pm8001_ha, 2026 pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 2027 ts->resp = SAS_TASK_COMPLETE; 2028 ts->stat = SAS_OPEN_REJECT; 2029 if (!t->uldd_task) 2030 pm8001_handle_event(pm8001_ha, 2031 pm8001_dev, 2032 IO_DS_NON_OPERATIONAL); 2033 break; 2034 case IO_DS_IN_RECOVERY: 2035 PM8001_IO_DBG(pm8001_ha, 2036 pm8001_printk("IO_DS_IN_RECOVERY\n")); 2037 ts->resp = SAS_TASK_COMPLETE; 2038 ts->stat = SAS_OPEN_REJECT; 2039 break; 2040 case IO_TM_TAG_NOT_FOUND: 2041 PM8001_IO_DBG(pm8001_ha, 2042 pm8001_printk("IO_TM_TAG_NOT_FOUND\n")); 2043 ts->resp = SAS_TASK_COMPLETE; 2044 ts->stat = SAS_OPEN_REJECT; 2045 break; 2046 case IO_SSP_EXT_IU_ZERO_LEN_ERROR: 2047 PM8001_IO_DBG(pm8001_ha, 2048 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n")); 2049 ts->resp = SAS_TASK_COMPLETE; 2050 ts->stat = SAS_OPEN_REJECT; 2051 break; 2052 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2053 PM8001_IO_DBG(pm8001_ha, 2054 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 2055 ts->resp = SAS_TASK_COMPLETE; 2056 ts->stat = SAS_OPEN_REJECT; 2057 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2058 break; 2059 default: 2060 PM8001_IO_DBG(pm8001_ha, 2061 pm8001_printk("Unknown status 0x%x\n", status)); 2062 /* not allowed case. Therefore, return failed status */ 2063 ts->resp = SAS_TASK_COMPLETE; 2064 ts->stat = SAS_OPEN_REJECT; 2065 break; 2066 } 2067 PM8001_IO_DBG(pm8001_ha, 2068 pm8001_printk("scsi_status = %x\n ", 2069 psspPayload->ssp_resp_iu.status)); 2070 spin_lock_irqsave(&t->task_state_lock, flags); 2071 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2072 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2073 t->task_state_flags |= SAS_TASK_STATE_DONE; 2074 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2075 spin_unlock_irqrestore(&t->task_state_lock, flags); 2076 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with" 2077 " io_status 0x%x resp 0x%x " 2078 "stat 0x%x but aborted by upper layer!\n", 2079 t, status, ts->resp, ts->stat)); 2080 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2081 } else { 2082 spin_unlock_irqrestore(&t->task_state_lock, flags); 2083 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2084 mb();/* in order to force CPU ordering */ 2085 t->task_done(t); 2086 } 2087 } 2088 2089 /*See the comments for mpi_ssp_completion */ 2090 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 2091 { 2092 struct sas_task *t; 2093 unsigned long flags; 2094 struct task_status_struct *ts; 2095 struct pm8001_ccb_info *ccb; 2096 struct pm8001_device *pm8001_dev; 2097 struct ssp_event_resp *psspPayload = 2098 (struct ssp_event_resp *)(piomb + 4); 2099 u32 event = le32_to_cpu(psspPayload->event); 2100 u32 tag = le32_to_cpu(psspPayload->tag); 2101 u32 port_id = le32_to_cpu(psspPayload->port_id); 2102 u32 dev_id = le32_to_cpu(psspPayload->device_id); 2103 2104 ccb = &pm8001_ha->ccb_info[tag]; 2105 t = ccb->task; 2106 pm8001_dev = ccb->device; 2107 if (event) 2108 PM8001_FAIL_DBG(pm8001_ha, 2109 pm8001_printk("sas IO status 0x%x\n", event)); 2110 if (unlikely(!t || !t->lldd_task || !t->dev)) 2111 return; 2112 ts = &t->task_status; 2113 PM8001_IO_DBG(pm8001_ha, 2114 pm8001_printk("port_id = %x,device_id = %x\n", 2115 port_id, dev_id)); 2116 switch (event) { 2117 case IO_OVERFLOW: 2118 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");) 2119 ts->resp = SAS_TASK_COMPLETE; 2120 ts->stat = SAS_DATA_OVERRUN; 2121 ts->residual = 0; 2122 if (pm8001_dev) 2123 pm8001_dev->running_req--; 2124 break; 2125 case IO_XFER_ERROR_BREAK: 2126 PM8001_IO_DBG(pm8001_ha, 2127 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2128 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK); 2129 return; 2130 case IO_XFER_ERROR_PHY_NOT_READY: 2131 PM8001_IO_DBG(pm8001_ha, 2132 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2133 ts->resp = SAS_TASK_COMPLETE; 2134 ts->stat = SAS_OPEN_REJECT; 2135 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2136 break; 2137 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2138 PM8001_IO_DBG(pm8001_ha, 2139 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT" 2140 "_SUPPORTED\n")); 2141 ts->resp = SAS_TASK_COMPLETE; 2142 ts->stat = SAS_OPEN_REJECT; 2143 ts->open_rej_reason = SAS_OREJ_EPROTO; 2144 break; 2145 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2146 PM8001_IO_DBG(pm8001_ha, 2147 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2148 ts->resp = SAS_TASK_COMPLETE; 2149 ts->stat = SAS_OPEN_REJECT; 2150 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2151 break; 2152 case IO_OPEN_CNX_ERROR_BREAK: 2153 PM8001_IO_DBG(pm8001_ha, 2154 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2155 ts->resp = SAS_TASK_COMPLETE; 2156 ts->stat = SAS_OPEN_REJECT; 2157 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2158 break; 2159 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2160 PM8001_IO_DBG(pm8001_ha, 2161 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2162 ts->resp = SAS_TASK_COMPLETE; 2163 ts->stat = SAS_OPEN_REJECT; 2164 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2165 if (!t->uldd_task) 2166 pm8001_handle_event(pm8001_ha, 2167 pm8001_dev, 2168 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2169 break; 2170 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2171 PM8001_IO_DBG(pm8001_ha, 2172 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2173 ts->resp = SAS_TASK_COMPLETE; 2174 ts->stat = SAS_OPEN_REJECT; 2175 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2176 break; 2177 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2178 PM8001_IO_DBG(pm8001_ha, 2179 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 2180 "NOT_SUPPORTED\n")); 2181 ts->resp = SAS_TASK_COMPLETE; 2182 ts->stat = SAS_OPEN_REJECT; 2183 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2184 break; 2185 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2186 PM8001_IO_DBG(pm8001_ha, 2187 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2188 ts->resp = SAS_TASK_COMPLETE; 2189 ts->stat = SAS_OPEN_REJECT; 2190 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2191 break; 2192 case IO_XFER_ERROR_NAK_RECEIVED: 2193 PM8001_IO_DBG(pm8001_ha, 2194 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 2195 ts->resp = SAS_TASK_COMPLETE; 2196 ts->stat = SAS_OPEN_REJECT; 2197 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2198 break; 2199 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2200 PM8001_IO_DBG(pm8001_ha, 2201 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 2202 ts->resp = SAS_TASK_COMPLETE; 2203 ts->stat = SAS_NAK_R_ERR; 2204 break; 2205 case IO_XFER_OPEN_RETRY_TIMEOUT: 2206 PM8001_IO_DBG(pm8001_ha, 2207 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2208 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT); 2209 return; 2210 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2211 PM8001_IO_DBG(pm8001_ha, 2212 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n")); 2213 ts->resp = SAS_TASK_COMPLETE; 2214 ts->stat = SAS_DATA_OVERRUN; 2215 break; 2216 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2217 PM8001_IO_DBG(pm8001_ha, 2218 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n")); 2219 ts->resp = SAS_TASK_COMPLETE; 2220 ts->stat = SAS_DATA_OVERRUN; 2221 break; 2222 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2223 PM8001_IO_DBG(pm8001_ha, 2224 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n")); 2225 ts->resp = SAS_TASK_COMPLETE; 2226 ts->stat = SAS_DATA_OVERRUN; 2227 break; 2228 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT: 2229 PM8001_IO_DBG(pm8001_ha, 2230 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n")); 2231 ts->resp = SAS_TASK_COMPLETE; 2232 ts->stat = SAS_DATA_OVERRUN; 2233 break; 2234 case IO_XFER_ERROR_OFFSET_MISMATCH: 2235 PM8001_IO_DBG(pm8001_ha, 2236 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 2237 ts->resp = SAS_TASK_COMPLETE; 2238 ts->stat = SAS_DATA_OVERRUN; 2239 break; 2240 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2241 PM8001_IO_DBG(pm8001_ha, 2242 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n")); 2243 ts->resp = SAS_TASK_COMPLETE; 2244 ts->stat = SAS_DATA_OVERRUN; 2245 break; 2246 case IO_XFER_CMD_FRAME_ISSUED: 2247 PM8001_IO_DBG(pm8001_ha, 2248 pm8001_printk(" IO_XFER_CMD_FRAME_ISSUED\n")); 2249 return; 2250 default: 2251 PM8001_IO_DBG(pm8001_ha, 2252 pm8001_printk("Unknown status 0x%x\n", event)); 2253 /* not allowed case. Therefore, return failed status */ 2254 ts->resp = SAS_TASK_COMPLETE; 2255 ts->stat = SAS_DATA_OVERRUN; 2256 break; 2257 } 2258 spin_lock_irqsave(&t->task_state_lock, flags); 2259 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2260 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2261 t->task_state_flags |= SAS_TASK_STATE_DONE; 2262 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2263 spin_unlock_irqrestore(&t->task_state_lock, flags); 2264 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with" 2265 " event 0x%x resp 0x%x " 2266 "stat 0x%x but aborted by upper layer!\n", 2267 t, event, ts->resp, ts->stat)); 2268 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2269 } else { 2270 spin_unlock_irqrestore(&t->task_state_lock, flags); 2271 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2272 mb();/* in order to force CPU ordering */ 2273 t->task_done(t); 2274 } 2275 } 2276 2277 /*See the comments for mpi_ssp_completion */ 2278 static void 2279 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2280 { 2281 struct sas_task *t; 2282 struct pm8001_ccb_info *ccb; 2283 u32 param; 2284 u32 status; 2285 u32 tag; 2286 int i, j; 2287 u8 sata_addr_low[4]; 2288 u32 temp_sata_addr_low; 2289 u8 sata_addr_hi[4]; 2290 u32 temp_sata_addr_hi; 2291 struct sata_completion_resp *psataPayload; 2292 struct task_status_struct *ts; 2293 struct ata_task_resp *resp ; 2294 u32 *sata_resp; 2295 struct pm8001_device *pm8001_dev; 2296 unsigned long flags; 2297 2298 psataPayload = (struct sata_completion_resp *)(piomb + 4); 2299 status = le32_to_cpu(psataPayload->status); 2300 tag = le32_to_cpu(psataPayload->tag); 2301 2302 if (!tag) { 2303 PM8001_FAIL_DBG(pm8001_ha, 2304 pm8001_printk("tag null\n")); 2305 return; 2306 } 2307 ccb = &pm8001_ha->ccb_info[tag]; 2308 param = le32_to_cpu(psataPayload->param); 2309 if (ccb) { 2310 t = ccb->task; 2311 pm8001_dev = ccb->device; 2312 } else { 2313 PM8001_FAIL_DBG(pm8001_ha, 2314 pm8001_printk("ccb null\n")); 2315 return; 2316 } 2317 2318 if (t) { 2319 if (t->dev && (t->dev->lldd_dev)) 2320 pm8001_dev = t->dev->lldd_dev; 2321 } else { 2322 PM8001_FAIL_DBG(pm8001_ha, 2323 pm8001_printk("task null\n")); 2324 return; 2325 } 2326 2327 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG)) 2328 && unlikely(!t || !t->lldd_task || !t->dev)) { 2329 PM8001_FAIL_DBG(pm8001_ha, 2330 pm8001_printk("task or dev null\n")); 2331 return; 2332 } 2333 2334 ts = &t->task_status; 2335 if (!ts) { 2336 PM8001_FAIL_DBG(pm8001_ha, 2337 pm8001_printk("ts null\n")); 2338 return; 2339 } 2340 /* Print sas address of IO failed device */ 2341 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 2342 (status != IO_UNDERFLOW)) { 2343 if (!((t->dev->parent) && 2344 (DEV_IS_EXPANDER(t->dev->parent->dev_type)))) { 2345 for (i = 0 , j = 4; j <= 7 && i <= 3; i++ , j++) 2346 sata_addr_low[i] = pm8001_ha->sas_addr[j]; 2347 for (i = 0 , j = 0; j <= 3 && i <= 3; i++ , j++) 2348 sata_addr_hi[i] = pm8001_ha->sas_addr[j]; 2349 memcpy(&temp_sata_addr_low, sata_addr_low, 2350 sizeof(sata_addr_low)); 2351 memcpy(&temp_sata_addr_hi, sata_addr_hi, 2352 sizeof(sata_addr_hi)); 2353 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff) 2354 |((temp_sata_addr_hi << 8) & 2355 0xff0000) | 2356 ((temp_sata_addr_hi >> 8) 2357 & 0xff00) | 2358 ((temp_sata_addr_hi << 24) & 2359 0xff000000)); 2360 temp_sata_addr_low = ((((temp_sata_addr_low >> 24) 2361 & 0xff) | 2362 ((temp_sata_addr_low << 8) 2363 & 0xff0000) | 2364 ((temp_sata_addr_low >> 8) 2365 & 0xff00) | 2366 ((temp_sata_addr_low << 24) 2367 & 0xff000000)) + 2368 pm8001_dev->attached_phy + 2369 0x10); 2370 PM8001_FAIL_DBG(pm8001_ha, 2371 pm8001_printk("SAS Address of IO Failure Drive:" 2372 "%08x%08x", temp_sata_addr_hi, 2373 temp_sata_addr_low)); 2374 } else { 2375 PM8001_FAIL_DBG(pm8001_ha, 2376 pm8001_printk("SAS Address of IO Failure Drive:" 2377 "%016llx", SAS_ADDR(t->dev->sas_addr))); 2378 } 2379 } 2380 switch (status) { 2381 case IO_SUCCESS: 2382 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); 2383 if (param == 0) { 2384 ts->resp = SAS_TASK_COMPLETE; 2385 ts->stat = SAM_STAT_GOOD; 2386 /* check if response is for SEND READ LOG */ 2387 if (pm8001_dev && 2388 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) { 2389 /* set new bit for abort_all */ 2390 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG; 2391 /* clear bit for read log */ 2392 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF; 2393 pm8001_send_abort_all(pm8001_ha, pm8001_dev); 2394 /* Free the tag */ 2395 pm8001_tag_free(pm8001_ha, tag); 2396 sas_free_task(t); 2397 return; 2398 } 2399 } else { 2400 u8 len; 2401 ts->resp = SAS_TASK_COMPLETE; 2402 ts->stat = SAS_PROTO_RESPONSE; 2403 ts->residual = param; 2404 PM8001_IO_DBG(pm8001_ha, 2405 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n", 2406 param)); 2407 sata_resp = &psataPayload->sata_resp[0]; 2408 resp = (struct ata_task_resp *)ts->buf; 2409 if (t->ata_task.dma_xfer == 0 && 2410 t->data_dir == PCI_DMA_FROMDEVICE) { 2411 len = sizeof(struct pio_setup_fis); 2412 PM8001_IO_DBG(pm8001_ha, 2413 pm8001_printk("PIO read len = %d\n", len)); 2414 } else if (t->ata_task.use_ncq) { 2415 len = sizeof(struct set_dev_bits_fis); 2416 PM8001_IO_DBG(pm8001_ha, 2417 pm8001_printk("FPDMA len = %d\n", len)); 2418 } else { 2419 len = sizeof(struct dev_to_host_fis); 2420 PM8001_IO_DBG(pm8001_ha, 2421 pm8001_printk("other len = %d\n", len)); 2422 } 2423 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) { 2424 resp->frame_len = len; 2425 memcpy(&resp->ending_fis[0], sata_resp, len); 2426 ts->buf_valid_size = sizeof(*resp); 2427 } else 2428 PM8001_IO_DBG(pm8001_ha, 2429 pm8001_printk("response to large\n")); 2430 } 2431 if (pm8001_dev) 2432 pm8001_dev->running_req--; 2433 break; 2434 case IO_ABORTED: 2435 PM8001_IO_DBG(pm8001_ha, 2436 pm8001_printk("IO_ABORTED IOMB Tag\n")); 2437 ts->resp = SAS_TASK_COMPLETE; 2438 ts->stat = SAS_ABORTED_TASK; 2439 if (pm8001_dev) 2440 pm8001_dev->running_req--; 2441 break; 2442 /* following cases are to do cases */ 2443 case IO_UNDERFLOW: 2444 /* SATA Completion with error */ 2445 PM8001_IO_DBG(pm8001_ha, 2446 pm8001_printk("IO_UNDERFLOW param = %d\n", param)); 2447 ts->resp = SAS_TASK_COMPLETE; 2448 ts->stat = SAS_DATA_UNDERRUN; 2449 ts->residual = param; 2450 if (pm8001_dev) 2451 pm8001_dev->running_req--; 2452 break; 2453 case IO_NO_DEVICE: 2454 PM8001_IO_DBG(pm8001_ha, 2455 pm8001_printk("IO_NO_DEVICE\n")); 2456 ts->resp = SAS_TASK_UNDELIVERED; 2457 ts->stat = SAS_PHY_DOWN; 2458 break; 2459 case IO_XFER_ERROR_BREAK: 2460 PM8001_IO_DBG(pm8001_ha, 2461 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2462 ts->resp = SAS_TASK_COMPLETE; 2463 ts->stat = SAS_INTERRUPTED; 2464 break; 2465 case IO_XFER_ERROR_PHY_NOT_READY: 2466 PM8001_IO_DBG(pm8001_ha, 2467 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2468 ts->resp = SAS_TASK_COMPLETE; 2469 ts->stat = SAS_OPEN_REJECT; 2470 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2471 break; 2472 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2473 PM8001_IO_DBG(pm8001_ha, 2474 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT" 2475 "_SUPPORTED\n")); 2476 ts->resp = SAS_TASK_COMPLETE; 2477 ts->stat = SAS_OPEN_REJECT; 2478 ts->open_rej_reason = SAS_OREJ_EPROTO; 2479 break; 2480 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2481 PM8001_IO_DBG(pm8001_ha, 2482 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2483 ts->resp = SAS_TASK_COMPLETE; 2484 ts->stat = SAS_OPEN_REJECT; 2485 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2486 break; 2487 case IO_OPEN_CNX_ERROR_BREAK: 2488 PM8001_IO_DBG(pm8001_ha, 2489 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2490 ts->resp = SAS_TASK_COMPLETE; 2491 ts->stat = SAS_OPEN_REJECT; 2492 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2493 break; 2494 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2495 PM8001_IO_DBG(pm8001_ha, 2496 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2497 ts->resp = SAS_TASK_COMPLETE; 2498 ts->stat = SAS_DEV_NO_RESPONSE; 2499 if (!t->uldd_task) { 2500 pm8001_handle_event(pm8001_ha, 2501 pm8001_dev, 2502 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2503 ts->resp = SAS_TASK_UNDELIVERED; 2504 ts->stat = SAS_QUEUE_FULL; 2505 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2506 return; 2507 } 2508 break; 2509 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2510 PM8001_IO_DBG(pm8001_ha, 2511 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2512 ts->resp = SAS_TASK_UNDELIVERED; 2513 ts->stat = SAS_OPEN_REJECT; 2514 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2515 if (!t->uldd_task) { 2516 pm8001_handle_event(pm8001_ha, 2517 pm8001_dev, 2518 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2519 ts->resp = SAS_TASK_UNDELIVERED; 2520 ts->stat = SAS_QUEUE_FULL; 2521 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2522 return; 2523 } 2524 break; 2525 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2526 PM8001_IO_DBG(pm8001_ha, 2527 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 2528 "NOT_SUPPORTED\n")); 2529 ts->resp = SAS_TASK_COMPLETE; 2530 ts->stat = SAS_OPEN_REJECT; 2531 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2532 break; 2533 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 2534 PM8001_IO_DBG(pm8001_ha, 2535 pm8001_printk("IO_OPEN_CNX_ERROR_STP_RESOURCES" 2536 "_BUSY\n")); 2537 ts->resp = SAS_TASK_COMPLETE; 2538 ts->stat = SAS_DEV_NO_RESPONSE; 2539 if (!t->uldd_task) { 2540 pm8001_handle_event(pm8001_ha, 2541 pm8001_dev, 2542 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY); 2543 ts->resp = SAS_TASK_UNDELIVERED; 2544 ts->stat = SAS_QUEUE_FULL; 2545 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2546 return; 2547 } 2548 break; 2549 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2550 PM8001_IO_DBG(pm8001_ha, 2551 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2552 ts->resp = SAS_TASK_COMPLETE; 2553 ts->stat = SAS_OPEN_REJECT; 2554 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2555 break; 2556 case IO_XFER_ERROR_NAK_RECEIVED: 2557 PM8001_IO_DBG(pm8001_ha, 2558 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 2559 ts->resp = SAS_TASK_COMPLETE; 2560 ts->stat = SAS_NAK_R_ERR; 2561 break; 2562 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2563 PM8001_IO_DBG(pm8001_ha, 2564 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 2565 ts->resp = SAS_TASK_COMPLETE; 2566 ts->stat = SAS_NAK_R_ERR; 2567 break; 2568 case IO_XFER_ERROR_DMA: 2569 PM8001_IO_DBG(pm8001_ha, 2570 pm8001_printk("IO_XFER_ERROR_DMA\n")); 2571 ts->resp = SAS_TASK_COMPLETE; 2572 ts->stat = SAS_ABORTED_TASK; 2573 break; 2574 case IO_XFER_ERROR_SATA_LINK_TIMEOUT: 2575 PM8001_IO_DBG(pm8001_ha, 2576 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n")); 2577 ts->resp = SAS_TASK_UNDELIVERED; 2578 ts->stat = SAS_DEV_NO_RESPONSE; 2579 break; 2580 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2581 PM8001_IO_DBG(pm8001_ha, 2582 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n")); 2583 ts->resp = SAS_TASK_COMPLETE; 2584 ts->stat = SAS_DATA_UNDERRUN; 2585 break; 2586 case IO_XFER_OPEN_RETRY_TIMEOUT: 2587 PM8001_IO_DBG(pm8001_ha, 2588 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2589 ts->resp = SAS_TASK_COMPLETE; 2590 ts->stat = SAS_OPEN_TO; 2591 break; 2592 case IO_PORT_IN_RESET: 2593 PM8001_IO_DBG(pm8001_ha, 2594 pm8001_printk("IO_PORT_IN_RESET\n")); 2595 ts->resp = SAS_TASK_COMPLETE; 2596 ts->stat = SAS_DEV_NO_RESPONSE; 2597 break; 2598 case IO_DS_NON_OPERATIONAL: 2599 PM8001_IO_DBG(pm8001_ha, 2600 pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 2601 ts->resp = SAS_TASK_COMPLETE; 2602 ts->stat = SAS_DEV_NO_RESPONSE; 2603 if (!t->uldd_task) { 2604 pm8001_handle_event(pm8001_ha, pm8001_dev, 2605 IO_DS_NON_OPERATIONAL); 2606 ts->resp = SAS_TASK_UNDELIVERED; 2607 ts->stat = SAS_QUEUE_FULL; 2608 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2609 return; 2610 } 2611 break; 2612 case IO_DS_IN_RECOVERY: 2613 PM8001_IO_DBG(pm8001_ha, 2614 pm8001_printk(" IO_DS_IN_RECOVERY\n")); 2615 ts->resp = SAS_TASK_COMPLETE; 2616 ts->stat = SAS_DEV_NO_RESPONSE; 2617 break; 2618 case IO_DS_IN_ERROR: 2619 PM8001_IO_DBG(pm8001_ha, 2620 pm8001_printk("IO_DS_IN_ERROR\n")); 2621 ts->resp = SAS_TASK_COMPLETE; 2622 ts->stat = SAS_DEV_NO_RESPONSE; 2623 if (!t->uldd_task) { 2624 pm8001_handle_event(pm8001_ha, pm8001_dev, 2625 IO_DS_IN_ERROR); 2626 ts->resp = SAS_TASK_UNDELIVERED; 2627 ts->stat = SAS_QUEUE_FULL; 2628 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2629 return; 2630 } 2631 break; 2632 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2633 PM8001_IO_DBG(pm8001_ha, 2634 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 2635 ts->resp = SAS_TASK_COMPLETE; 2636 ts->stat = SAS_OPEN_REJECT; 2637 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2638 default: 2639 PM8001_IO_DBG(pm8001_ha, 2640 pm8001_printk("Unknown status 0x%x\n", status)); 2641 /* not allowed case. Therefore, return failed status */ 2642 ts->resp = SAS_TASK_COMPLETE; 2643 ts->stat = SAS_DEV_NO_RESPONSE; 2644 break; 2645 } 2646 spin_lock_irqsave(&t->task_state_lock, flags); 2647 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2648 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2649 t->task_state_flags |= SAS_TASK_STATE_DONE; 2650 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2651 spin_unlock_irqrestore(&t->task_state_lock, flags); 2652 PM8001_FAIL_DBG(pm8001_ha, 2653 pm8001_printk("task 0x%p done with io_status 0x%x" 2654 " resp 0x%x stat 0x%x but aborted by upper layer!\n", 2655 t, status, ts->resp, ts->stat)); 2656 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2657 } else { 2658 spin_unlock_irqrestore(&t->task_state_lock, flags); 2659 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2660 } 2661 } 2662 2663 /*See the comments for mpi_ssp_completion */ 2664 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 2665 { 2666 struct sas_task *t; 2667 struct task_status_struct *ts; 2668 struct pm8001_ccb_info *ccb; 2669 struct pm8001_device *pm8001_dev; 2670 struct sata_event_resp *psataPayload = 2671 (struct sata_event_resp *)(piomb + 4); 2672 u32 event = le32_to_cpu(psataPayload->event); 2673 u32 tag = le32_to_cpu(psataPayload->tag); 2674 u32 port_id = le32_to_cpu(psataPayload->port_id); 2675 u32 dev_id = le32_to_cpu(psataPayload->device_id); 2676 unsigned long flags; 2677 2678 ccb = &pm8001_ha->ccb_info[tag]; 2679 2680 if (ccb) { 2681 t = ccb->task; 2682 pm8001_dev = ccb->device; 2683 } else { 2684 PM8001_FAIL_DBG(pm8001_ha, 2685 pm8001_printk("No CCB !!!. returning\n")); 2686 } 2687 if (event) 2688 PM8001_FAIL_DBG(pm8001_ha, 2689 pm8001_printk("SATA EVENT 0x%x\n", event)); 2690 2691 /* Check if this is NCQ error */ 2692 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) { 2693 /* find device using device id */ 2694 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id); 2695 /* send read log extension */ 2696 if (pm8001_dev) 2697 pm8001_send_read_log(pm8001_ha, pm8001_dev); 2698 return; 2699 } 2700 2701 ccb = &pm8001_ha->ccb_info[tag]; 2702 t = ccb->task; 2703 pm8001_dev = ccb->device; 2704 if (event) 2705 PM8001_FAIL_DBG(pm8001_ha, 2706 pm8001_printk("sata IO status 0x%x\n", event)); 2707 if (unlikely(!t || !t->lldd_task || !t->dev)) 2708 return; 2709 ts = &t->task_status; 2710 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 2711 "port_id:0x%x, device_id:0x%x, tag:0x%x, event:0x%x\n", 2712 port_id, dev_id, tag, event)); 2713 switch (event) { 2714 case IO_OVERFLOW: 2715 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n")); 2716 ts->resp = SAS_TASK_COMPLETE; 2717 ts->stat = SAS_DATA_OVERRUN; 2718 ts->residual = 0; 2719 if (pm8001_dev) 2720 pm8001_dev->running_req--; 2721 break; 2722 case IO_XFER_ERROR_BREAK: 2723 PM8001_IO_DBG(pm8001_ha, 2724 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2725 ts->resp = SAS_TASK_COMPLETE; 2726 ts->stat = SAS_INTERRUPTED; 2727 break; 2728 case IO_XFER_ERROR_PHY_NOT_READY: 2729 PM8001_IO_DBG(pm8001_ha, 2730 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2731 ts->resp = SAS_TASK_COMPLETE; 2732 ts->stat = SAS_OPEN_REJECT; 2733 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2734 break; 2735 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2736 PM8001_IO_DBG(pm8001_ha, 2737 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT" 2738 "_SUPPORTED\n")); 2739 ts->resp = SAS_TASK_COMPLETE; 2740 ts->stat = SAS_OPEN_REJECT; 2741 ts->open_rej_reason = SAS_OREJ_EPROTO; 2742 break; 2743 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2744 PM8001_IO_DBG(pm8001_ha, 2745 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2746 ts->resp = SAS_TASK_COMPLETE; 2747 ts->stat = SAS_OPEN_REJECT; 2748 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2749 break; 2750 case IO_OPEN_CNX_ERROR_BREAK: 2751 PM8001_IO_DBG(pm8001_ha, 2752 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2753 ts->resp = SAS_TASK_COMPLETE; 2754 ts->stat = SAS_OPEN_REJECT; 2755 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2756 break; 2757 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2758 PM8001_IO_DBG(pm8001_ha, 2759 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2760 ts->resp = SAS_TASK_UNDELIVERED; 2761 ts->stat = SAS_DEV_NO_RESPONSE; 2762 if (!t->uldd_task) { 2763 pm8001_handle_event(pm8001_ha, 2764 pm8001_dev, 2765 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2766 ts->resp = SAS_TASK_COMPLETE; 2767 ts->stat = SAS_QUEUE_FULL; 2768 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2769 return; 2770 } 2771 break; 2772 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2773 PM8001_IO_DBG(pm8001_ha, 2774 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2775 ts->resp = SAS_TASK_UNDELIVERED; 2776 ts->stat = SAS_OPEN_REJECT; 2777 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2778 break; 2779 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2780 PM8001_IO_DBG(pm8001_ha, 2781 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 2782 "NOT_SUPPORTED\n")); 2783 ts->resp = SAS_TASK_COMPLETE; 2784 ts->stat = SAS_OPEN_REJECT; 2785 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2786 break; 2787 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2788 PM8001_IO_DBG(pm8001_ha, 2789 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2790 ts->resp = SAS_TASK_COMPLETE; 2791 ts->stat = SAS_OPEN_REJECT; 2792 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2793 break; 2794 case IO_XFER_ERROR_NAK_RECEIVED: 2795 PM8001_IO_DBG(pm8001_ha, 2796 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 2797 ts->resp = SAS_TASK_COMPLETE; 2798 ts->stat = SAS_NAK_R_ERR; 2799 break; 2800 case IO_XFER_ERROR_PEER_ABORTED: 2801 PM8001_IO_DBG(pm8001_ha, 2802 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n")); 2803 ts->resp = SAS_TASK_COMPLETE; 2804 ts->stat = SAS_NAK_R_ERR; 2805 break; 2806 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2807 PM8001_IO_DBG(pm8001_ha, 2808 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n")); 2809 ts->resp = SAS_TASK_COMPLETE; 2810 ts->stat = SAS_DATA_UNDERRUN; 2811 break; 2812 case IO_XFER_OPEN_RETRY_TIMEOUT: 2813 PM8001_IO_DBG(pm8001_ha, 2814 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2815 ts->resp = SAS_TASK_COMPLETE; 2816 ts->stat = SAS_OPEN_TO; 2817 break; 2818 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2819 PM8001_IO_DBG(pm8001_ha, 2820 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n")); 2821 ts->resp = SAS_TASK_COMPLETE; 2822 ts->stat = SAS_OPEN_TO; 2823 break; 2824 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2825 PM8001_IO_DBG(pm8001_ha, 2826 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n")); 2827 ts->resp = SAS_TASK_COMPLETE; 2828 ts->stat = SAS_OPEN_TO; 2829 break; 2830 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2831 PM8001_IO_DBG(pm8001_ha, 2832 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n")); 2833 ts->resp = SAS_TASK_COMPLETE; 2834 ts->stat = SAS_OPEN_TO; 2835 break; 2836 case IO_XFER_ERROR_OFFSET_MISMATCH: 2837 PM8001_IO_DBG(pm8001_ha, 2838 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 2839 ts->resp = SAS_TASK_COMPLETE; 2840 ts->stat = SAS_OPEN_TO; 2841 break; 2842 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2843 PM8001_IO_DBG(pm8001_ha, 2844 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n")); 2845 ts->resp = SAS_TASK_COMPLETE; 2846 ts->stat = SAS_OPEN_TO; 2847 break; 2848 case IO_XFER_CMD_FRAME_ISSUED: 2849 PM8001_IO_DBG(pm8001_ha, 2850 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n")); 2851 break; 2852 case IO_XFER_PIO_SETUP_ERROR: 2853 PM8001_IO_DBG(pm8001_ha, 2854 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n")); 2855 ts->resp = SAS_TASK_COMPLETE; 2856 ts->stat = SAS_OPEN_TO; 2857 break; 2858 default: 2859 PM8001_IO_DBG(pm8001_ha, 2860 pm8001_printk("Unknown status 0x%x\n", event)); 2861 /* not allowed case. Therefore, return failed status */ 2862 ts->resp = SAS_TASK_COMPLETE; 2863 ts->stat = SAS_OPEN_TO; 2864 break; 2865 } 2866 spin_lock_irqsave(&t->task_state_lock, flags); 2867 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2868 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2869 t->task_state_flags |= SAS_TASK_STATE_DONE; 2870 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2871 spin_unlock_irqrestore(&t->task_state_lock, flags); 2872 PM8001_FAIL_DBG(pm8001_ha, 2873 pm8001_printk("task 0x%p done with io_status 0x%x" 2874 " resp 0x%x stat 0x%x but aborted by upper layer!\n", 2875 t, event, ts->resp, ts->stat)); 2876 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2877 } else { 2878 spin_unlock_irqrestore(&t->task_state_lock, flags); 2879 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2880 } 2881 } 2882 2883 /*See the comments for mpi_ssp_completion */ 2884 static void 2885 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2886 { 2887 u32 param; 2888 struct sas_task *t; 2889 struct pm8001_ccb_info *ccb; 2890 unsigned long flags; 2891 u32 status; 2892 u32 tag; 2893 struct smp_completion_resp *psmpPayload; 2894 struct task_status_struct *ts; 2895 struct pm8001_device *pm8001_dev; 2896 2897 psmpPayload = (struct smp_completion_resp *)(piomb + 4); 2898 status = le32_to_cpu(psmpPayload->status); 2899 tag = le32_to_cpu(psmpPayload->tag); 2900 2901 ccb = &pm8001_ha->ccb_info[tag]; 2902 param = le32_to_cpu(psmpPayload->param); 2903 t = ccb->task; 2904 ts = &t->task_status; 2905 pm8001_dev = ccb->device; 2906 if (status) 2907 PM8001_FAIL_DBG(pm8001_ha, 2908 pm8001_printk("smp IO status 0x%x\n", status)); 2909 if (unlikely(!t || !t->lldd_task || !t->dev)) 2910 return; 2911 2912 switch (status) { 2913 case IO_SUCCESS: 2914 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); 2915 ts->resp = SAS_TASK_COMPLETE; 2916 ts->stat = SAM_STAT_GOOD; 2917 if (pm8001_dev) 2918 pm8001_dev->running_req--; 2919 break; 2920 case IO_ABORTED: 2921 PM8001_IO_DBG(pm8001_ha, 2922 pm8001_printk("IO_ABORTED IOMB\n")); 2923 ts->resp = SAS_TASK_COMPLETE; 2924 ts->stat = SAS_ABORTED_TASK; 2925 if (pm8001_dev) 2926 pm8001_dev->running_req--; 2927 break; 2928 case IO_OVERFLOW: 2929 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n")); 2930 ts->resp = SAS_TASK_COMPLETE; 2931 ts->stat = SAS_DATA_OVERRUN; 2932 ts->residual = 0; 2933 if (pm8001_dev) 2934 pm8001_dev->running_req--; 2935 break; 2936 case IO_NO_DEVICE: 2937 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n")); 2938 ts->resp = SAS_TASK_COMPLETE; 2939 ts->stat = SAS_PHY_DOWN; 2940 break; 2941 case IO_ERROR_HW_TIMEOUT: 2942 PM8001_IO_DBG(pm8001_ha, 2943 pm8001_printk("IO_ERROR_HW_TIMEOUT\n")); 2944 ts->resp = SAS_TASK_COMPLETE; 2945 ts->stat = SAM_STAT_BUSY; 2946 break; 2947 case IO_XFER_ERROR_BREAK: 2948 PM8001_IO_DBG(pm8001_ha, 2949 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2950 ts->resp = SAS_TASK_COMPLETE; 2951 ts->stat = SAM_STAT_BUSY; 2952 break; 2953 case IO_XFER_ERROR_PHY_NOT_READY: 2954 PM8001_IO_DBG(pm8001_ha, 2955 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2956 ts->resp = SAS_TASK_COMPLETE; 2957 ts->stat = SAM_STAT_BUSY; 2958 break; 2959 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2960 PM8001_IO_DBG(pm8001_ha, 2961 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 2962 ts->resp = SAS_TASK_COMPLETE; 2963 ts->stat = SAS_OPEN_REJECT; 2964 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2965 break; 2966 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2967 PM8001_IO_DBG(pm8001_ha, 2968 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2969 ts->resp = SAS_TASK_COMPLETE; 2970 ts->stat = SAS_OPEN_REJECT; 2971 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2972 break; 2973 case IO_OPEN_CNX_ERROR_BREAK: 2974 PM8001_IO_DBG(pm8001_ha, 2975 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2976 ts->resp = SAS_TASK_COMPLETE; 2977 ts->stat = SAS_OPEN_REJECT; 2978 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2979 break; 2980 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2981 PM8001_IO_DBG(pm8001_ha, 2982 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2983 ts->resp = SAS_TASK_COMPLETE; 2984 ts->stat = SAS_OPEN_REJECT; 2985 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2986 pm8001_handle_event(pm8001_ha, 2987 pm8001_dev, 2988 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2989 break; 2990 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2991 PM8001_IO_DBG(pm8001_ha, 2992 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2993 ts->resp = SAS_TASK_COMPLETE; 2994 ts->stat = SAS_OPEN_REJECT; 2995 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2996 break; 2997 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2998 PM8001_IO_DBG(pm8001_ha, 2999 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 3000 "NOT_SUPPORTED\n")); 3001 ts->resp = SAS_TASK_COMPLETE; 3002 ts->stat = SAS_OPEN_REJECT; 3003 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 3004 break; 3005 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 3006 PM8001_IO_DBG(pm8001_ha, 3007 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 3008 ts->resp = SAS_TASK_COMPLETE; 3009 ts->stat = SAS_OPEN_REJECT; 3010 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 3011 break; 3012 case IO_XFER_ERROR_RX_FRAME: 3013 PM8001_IO_DBG(pm8001_ha, 3014 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n")); 3015 ts->resp = SAS_TASK_COMPLETE; 3016 ts->stat = SAS_DEV_NO_RESPONSE; 3017 break; 3018 case IO_XFER_OPEN_RETRY_TIMEOUT: 3019 PM8001_IO_DBG(pm8001_ha, 3020 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 3021 ts->resp = SAS_TASK_COMPLETE; 3022 ts->stat = SAS_OPEN_REJECT; 3023 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3024 break; 3025 case IO_ERROR_INTERNAL_SMP_RESOURCE: 3026 PM8001_IO_DBG(pm8001_ha, 3027 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n")); 3028 ts->resp = SAS_TASK_COMPLETE; 3029 ts->stat = SAS_QUEUE_FULL; 3030 break; 3031 case IO_PORT_IN_RESET: 3032 PM8001_IO_DBG(pm8001_ha, 3033 pm8001_printk("IO_PORT_IN_RESET\n")); 3034 ts->resp = SAS_TASK_COMPLETE; 3035 ts->stat = SAS_OPEN_REJECT; 3036 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3037 break; 3038 case IO_DS_NON_OPERATIONAL: 3039 PM8001_IO_DBG(pm8001_ha, 3040 pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 3041 ts->resp = SAS_TASK_COMPLETE; 3042 ts->stat = SAS_DEV_NO_RESPONSE; 3043 break; 3044 case IO_DS_IN_RECOVERY: 3045 PM8001_IO_DBG(pm8001_ha, 3046 pm8001_printk("IO_DS_IN_RECOVERY\n")); 3047 ts->resp = SAS_TASK_COMPLETE; 3048 ts->stat = SAS_OPEN_REJECT; 3049 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3050 break; 3051 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 3052 PM8001_IO_DBG(pm8001_ha, 3053 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 3054 ts->resp = SAS_TASK_COMPLETE; 3055 ts->stat = SAS_OPEN_REJECT; 3056 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3057 break; 3058 default: 3059 PM8001_IO_DBG(pm8001_ha, 3060 pm8001_printk("Unknown status 0x%x\n", status)); 3061 ts->resp = SAS_TASK_COMPLETE; 3062 ts->stat = SAS_DEV_NO_RESPONSE; 3063 /* not allowed case. Therefore, return failed status */ 3064 break; 3065 } 3066 spin_lock_irqsave(&t->task_state_lock, flags); 3067 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 3068 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 3069 t->task_state_flags |= SAS_TASK_STATE_DONE; 3070 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 3071 spin_unlock_irqrestore(&t->task_state_lock, flags); 3072 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with" 3073 " io_status 0x%x resp 0x%x " 3074 "stat 0x%x but aborted by upper layer!\n", 3075 t, status, ts->resp, ts->stat)); 3076 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 3077 } else { 3078 spin_unlock_irqrestore(&t->task_state_lock, flags); 3079 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 3080 mb();/* in order to force CPU ordering */ 3081 t->task_done(t); 3082 } 3083 } 3084 3085 void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha, 3086 void *piomb) 3087 { 3088 struct set_dev_state_resp *pPayload = 3089 (struct set_dev_state_resp *)(piomb + 4); 3090 u32 tag = le32_to_cpu(pPayload->tag); 3091 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 3092 struct pm8001_device *pm8001_dev = ccb->device; 3093 u32 status = le32_to_cpu(pPayload->status); 3094 u32 device_id = le32_to_cpu(pPayload->device_id); 3095 u8 pds = le32_to_cpu(pPayload->pds_nds) & PDS_BITS; 3096 u8 nds = le32_to_cpu(pPayload->pds_nds) & NDS_BITS; 3097 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set device id = 0x%x state " 3098 "from 0x%x to 0x%x status = 0x%x!\n", 3099 device_id, pds, nds, status)); 3100 complete(pm8001_dev->setds_completion); 3101 ccb->task = NULL; 3102 ccb->ccb_tag = 0xFFFFFFFF; 3103 pm8001_ccb_free(pm8001_ha, tag); 3104 } 3105 3106 void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3107 { 3108 struct get_nvm_data_resp *pPayload = 3109 (struct get_nvm_data_resp *)(piomb + 4); 3110 u32 tag = le32_to_cpu(pPayload->tag); 3111 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 3112 u32 dlen_status = le32_to_cpu(pPayload->dlen_status); 3113 complete(pm8001_ha->nvmd_completion); 3114 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set nvm data complete!\n")); 3115 if ((dlen_status & NVMD_STAT) != 0) { 3116 PM8001_FAIL_DBG(pm8001_ha, 3117 pm8001_printk("Set nvm data error!\n")); 3118 return; 3119 } 3120 ccb->task = NULL; 3121 ccb->ccb_tag = 0xFFFFFFFF; 3122 pm8001_ccb_free(pm8001_ha, tag); 3123 } 3124 3125 void 3126 pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3127 { 3128 struct fw_control_ex *fw_control_context; 3129 struct get_nvm_data_resp *pPayload = 3130 (struct get_nvm_data_resp *)(piomb + 4); 3131 u32 tag = le32_to_cpu(pPayload->tag); 3132 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 3133 u32 dlen_status = le32_to_cpu(pPayload->dlen_status); 3134 u32 ir_tds_bn_dps_das_nvm = 3135 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm); 3136 void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr; 3137 fw_control_context = ccb->fw_control_context; 3138 3139 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Get nvm data complete!\n")); 3140 if ((dlen_status & NVMD_STAT) != 0) { 3141 PM8001_FAIL_DBG(pm8001_ha, 3142 pm8001_printk("Get nvm data error!\n")); 3143 complete(pm8001_ha->nvmd_completion); 3144 return; 3145 } 3146 3147 if (ir_tds_bn_dps_das_nvm & IPMode) { 3148 /* indirect mode - IR bit set */ 3149 PM8001_MSG_DBG(pm8001_ha, 3150 pm8001_printk("Get NVMD success, IR=1\n")); 3151 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) { 3152 if (ir_tds_bn_dps_das_nvm == 0x80a80200) { 3153 memcpy(pm8001_ha->sas_addr, 3154 ((u8 *)virt_addr + 4), 3155 SAS_ADDR_SIZE); 3156 PM8001_MSG_DBG(pm8001_ha, 3157 pm8001_printk("Get SAS address" 3158 " from VPD successfully!\n")); 3159 } 3160 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM) 3161 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) || 3162 ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) { 3163 ; 3164 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP) 3165 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) { 3166 ; 3167 } else { 3168 /* Should not be happened*/ 3169 PM8001_MSG_DBG(pm8001_ha, 3170 pm8001_printk("(IR=1)Wrong Device type 0x%x\n", 3171 ir_tds_bn_dps_das_nvm)); 3172 } 3173 } else /* direct mode */{ 3174 PM8001_MSG_DBG(pm8001_ha, 3175 pm8001_printk("Get NVMD success, IR=0, dataLen=%d\n", 3176 (dlen_status & NVMD_LEN) >> 24)); 3177 } 3178 memcpy(fw_control_context->usrAddr, 3179 pm8001_ha->memoryMap.region[NVMD].virt_ptr, 3180 fw_control_context->len); 3181 complete(pm8001_ha->nvmd_completion); 3182 ccb->task = NULL; 3183 ccb->ccb_tag = 0xFFFFFFFF; 3184 pm8001_ccb_free(pm8001_ha, tag); 3185 } 3186 3187 int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb) 3188 { 3189 struct local_phy_ctl_resp *pPayload = 3190 (struct local_phy_ctl_resp *)(piomb + 4); 3191 u32 status = le32_to_cpu(pPayload->status); 3192 u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS; 3193 u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS; 3194 if (status != 0) { 3195 PM8001_MSG_DBG(pm8001_ha, 3196 pm8001_printk("%x phy execute %x phy op failed!\n", 3197 phy_id, phy_op)); 3198 } else 3199 PM8001_MSG_DBG(pm8001_ha, 3200 pm8001_printk("%x phy execute %x phy op success!\n", 3201 phy_id, phy_op)); 3202 return 0; 3203 } 3204 3205 /** 3206 * pm8001_bytes_dmaed - one of the interface function communication with libsas 3207 * @pm8001_ha: our hba card information 3208 * @i: which phy that received the event. 3209 * 3210 * when HBA driver received the identify done event or initiate FIS received 3211 * event(for SATA), it will invoke this function to notify the sas layer that 3212 * the sas toplogy has formed, please discover the the whole sas domain, 3213 * while receive a broadcast(change) primitive just tell the sas 3214 * layer to discover the changed domain rather than the whole domain. 3215 */ 3216 void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i) 3217 { 3218 struct pm8001_phy *phy = &pm8001_ha->phy[i]; 3219 struct asd_sas_phy *sas_phy = &phy->sas_phy; 3220 struct sas_ha_struct *sas_ha; 3221 if (!phy->phy_attached) 3222 return; 3223 3224 sas_ha = pm8001_ha->sas; 3225 if (sas_phy->phy) { 3226 struct sas_phy *sphy = sas_phy->phy; 3227 sphy->negotiated_linkrate = sas_phy->linkrate; 3228 sphy->minimum_linkrate = phy->minimum_linkrate; 3229 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS; 3230 sphy->maximum_linkrate = phy->maximum_linkrate; 3231 sphy->maximum_linkrate_hw = phy->maximum_linkrate; 3232 } 3233 3234 if (phy->phy_type & PORT_TYPE_SAS) { 3235 struct sas_identify_frame *id; 3236 id = (struct sas_identify_frame *)phy->frame_rcvd; 3237 id->dev_type = phy->identify.device_type; 3238 id->initiator_bits = SAS_PROTOCOL_ALL; 3239 id->target_bits = phy->identify.target_port_protocols; 3240 } else if (phy->phy_type & PORT_TYPE_SATA) { 3241 /*Nothing*/ 3242 } 3243 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("phy %d byte dmaded.\n", i)); 3244 3245 sas_phy->frame_rcvd_size = phy->frame_rcvd_size; 3246 pm8001_ha->sas->notify_port_event(sas_phy, PORTE_BYTES_DMAED); 3247 } 3248 3249 /* Get the link rate speed */ 3250 void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate) 3251 { 3252 struct sas_phy *sas_phy = phy->sas_phy.phy; 3253 3254 switch (link_rate) { 3255 case PHY_SPEED_60: 3256 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS; 3257 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS; 3258 break; 3259 case PHY_SPEED_30: 3260 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS; 3261 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS; 3262 break; 3263 case PHY_SPEED_15: 3264 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS; 3265 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS; 3266 break; 3267 } 3268 sas_phy->negotiated_linkrate = phy->sas_phy.linkrate; 3269 sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS; 3270 sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS; 3271 sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS; 3272 sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS; 3273 } 3274 3275 /** 3276 * asd_get_attached_sas_addr -- extract/generate attached SAS address 3277 * @phy: pointer to asd_phy 3278 * @sas_addr: pointer to buffer where the SAS address is to be written 3279 * 3280 * This function extracts the SAS address from an IDENTIFY frame 3281 * received. If OOB is SATA, then a SAS address is generated from the 3282 * HA tables. 3283 * 3284 * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame 3285 * buffer. 3286 */ 3287 void pm8001_get_attached_sas_addr(struct pm8001_phy *phy, 3288 u8 *sas_addr) 3289 { 3290 if (phy->sas_phy.frame_rcvd[0] == 0x34 3291 && phy->sas_phy.oob_mode == SATA_OOB_MODE) { 3292 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha; 3293 /* FIS device-to-host */ 3294 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr); 3295 addr += phy->sas_phy.id; 3296 *(__be64 *)sas_addr = cpu_to_be64(addr); 3297 } else { 3298 struct sas_identify_frame *idframe = 3299 (void *) phy->sas_phy.frame_rcvd; 3300 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE); 3301 } 3302 } 3303 3304 /** 3305 * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW. 3306 * @pm8001_ha: our hba card information 3307 * @Qnum: the outbound queue message number. 3308 * @SEA: source of event to ack 3309 * @port_id: port id. 3310 * @phyId: phy id. 3311 * @param0: parameter 0. 3312 * @param1: parameter 1. 3313 */ 3314 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha, 3315 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1) 3316 { 3317 struct hw_event_ack_req payload; 3318 u32 opc = OPC_INB_SAS_HW_EVENT_ACK; 3319 3320 struct inbound_queue_table *circularQ; 3321 3322 memset((u8 *)&payload, 0, sizeof(payload)); 3323 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum]; 3324 payload.tag = cpu_to_le32(1); 3325 payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) | 3326 ((phyId & 0x0F) << 4) | (port_id & 0x0F)); 3327 payload.param0 = cpu_to_le32(param0); 3328 payload.param1 = cpu_to_le32(param1); 3329 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 3330 } 3331 3332 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 3333 u32 phyId, u32 phy_op); 3334 3335 /** 3336 * hw_event_sas_phy_up -FW tells me a SAS phy up event. 3337 * @pm8001_ha: our hba card information 3338 * @piomb: IO message buffer 3339 */ 3340 static void 3341 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3342 { 3343 struct hw_event_resp *pPayload = 3344 (struct hw_event_resp *)(piomb + 4); 3345 u32 lr_evt_status_phyid_portid = 3346 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3347 u8 link_rate = 3348 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28); 3349 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3350 u8 phy_id = 3351 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3352 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate); 3353 u8 portstate = (u8)(npip_portstate & 0x0000000F); 3354 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3355 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3356 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3357 unsigned long flags; 3358 u8 deviceType = pPayload->sas_identify.dev_type; 3359 port->port_state = portstate; 3360 phy->phy_state = PHY_STATE_LINK_UP_SPC; 3361 PM8001_MSG_DBG(pm8001_ha, 3362 pm8001_printk("HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n", 3363 port_id, phy_id)); 3364 3365 switch (deviceType) { 3366 case SAS_PHY_UNUSED: 3367 PM8001_MSG_DBG(pm8001_ha, 3368 pm8001_printk("device type no device.\n")); 3369 break; 3370 case SAS_END_DEVICE: 3371 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n")); 3372 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id, 3373 PHY_NOTIFY_ENABLE_SPINUP); 3374 port->port_attached = 1; 3375 pm8001_get_lrate_mode(phy, link_rate); 3376 break; 3377 case SAS_EDGE_EXPANDER_DEVICE: 3378 PM8001_MSG_DBG(pm8001_ha, 3379 pm8001_printk("expander device.\n")); 3380 port->port_attached = 1; 3381 pm8001_get_lrate_mode(phy, link_rate); 3382 break; 3383 case SAS_FANOUT_EXPANDER_DEVICE: 3384 PM8001_MSG_DBG(pm8001_ha, 3385 pm8001_printk("fanout expander device.\n")); 3386 port->port_attached = 1; 3387 pm8001_get_lrate_mode(phy, link_rate); 3388 break; 3389 default: 3390 PM8001_MSG_DBG(pm8001_ha, 3391 pm8001_printk("unknown device type(%x)\n", deviceType)); 3392 break; 3393 } 3394 phy->phy_type |= PORT_TYPE_SAS; 3395 phy->identify.device_type = deviceType; 3396 phy->phy_attached = 1; 3397 if (phy->identify.device_type == SAS_END_DEVICE) 3398 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP; 3399 else if (phy->identify.device_type != SAS_PHY_UNUSED) 3400 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP; 3401 phy->sas_phy.oob_mode = SAS_OOB_MODE; 3402 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE); 3403 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3404 memcpy(phy->frame_rcvd, &pPayload->sas_identify, 3405 sizeof(struct sas_identify_frame)-4); 3406 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4; 3407 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3408 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3409 if (pm8001_ha->flags == PM8001F_RUN_TIME) 3410 mdelay(200);/*delay a moment to wait disk to spinup*/ 3411 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3412 } 3413 3414 /** 3415 * hw_event_sata_phy_up -FW tells me a SATA phy up event. 3416 * @pm8001_ha: our hba card information 3417 * @piomb: IO message buffer 3418 */ 3419 static void 3420 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3421 { 3422 struct hw_event_resp *pPayload = 3423 (struct hw_event_resp *)(piomb + 4); 3424 u32 lr_evt_status_phyid_portid = 3425 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3426 u8 link_rate = 3427 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28); 3428 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3429 u8 phy_id = 3430 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3431 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate); 3432 u8 portstate = (u8)(npip_portstate & 0x0000000F); 3433 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3434 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3435 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3436 unsigned long flags; 3437 PM8001_MSG_DBG(pm8001_ha, 3438 pm8001_printk("HW_EVENT_SATA_PHY_UP port id = %d," 3439 " phy id = %d\n", port_id, phy_id)); 3440 port->port_state = portstate; 3441 phy->phy_state = PHY_STATE_LINK_UP_SPC; 3442 port->port_attached = 1; 3443 pm8001_get_lrate_mode(phy, link_rate); 3444 phy->phy_type |= PORT_TYPE_SATA; 3445 phy->phy_attached = 1; 3446 phy->sas_phy.oob_mode = SATA_OOB_MODE; 3447 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE); 3448 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3449 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4), 3450 sizeof(struct dev_to_host_fis)); 3451 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 3452 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 3453 phy->identify.device_type = SAS_SATA_DEV; 3454 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3455 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3456 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3457 } 3458 3459 /** 3460 * hw_event_phy_down -we should notify the libsas the phy is down. 3461 * @pm8001_ha: our hba card information 3462 * @piomb: IO message buffer 3463 */ 3464 static void 3465 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb) 3466 { 3467 struct hw_event_resp *pPayload = 3468 (struct hw_event_resp *)(piomb + 4); 3469 u32 lr_evt_status_phyid_portid = 3470 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3471 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3472 u8 phy_id = 3473 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3474 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate); 3475 u8 portstate = (u8)(npip_portstate & 0x0000000F); 3476 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3477 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3478 port->port_state = portstate; 3479 phy->phy_type = 0; 3480 phy->identify.device_type = 0; 3481 phy->phy_attached = 0; 3482 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE); 3483 switch (portstate) { 3484 case PORT_VALID: 3485 break; 3486 case PORT_INVALID: 3487 PM8001_MSG_DBG(pm8001_ha, 3488 pm8001_printk(" PortInvalid portID %d\n", port_id)); 3489 PM8001_MSG_DBG(pm8001_ha, 3490 pm8001_printk(" Last phy Down and port invalid\n")); 3491 port->port_attached = 0; 3492 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3493 port_id, phy_id, 0, 0); 3494 break; 3495 case PORT_IN_RESET: 3496 PM8001_MSG_DBG(pm8001_ha, 3497 pm8001_printk(" Port In Reset portID %d\n", port_id)); 3498 break; 3499 case PORT_NOT_ESTABLISHED: 3500 PM8001_MSG_DBG(pm8001_ha, 3501 pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n")); 3502 port->port_attached = 0; 3503 break; 3504 case PORT_LOSTCOMM: 3505 PM8001_MSG_DBG(pm8001_ha, 3506 pm8001_printk(" phy Down and PORT_LOSTCOMM\n")); 3507 PM8001_MSG_DBG(pm8001_ha, 3508 pm8001_printk(" Last phy Down and port invalid\n")); 3509 port->port_attached = 0; 3510 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3511 port_id, phy_id, 0, 0); 3512 break; 3513 default: 3514 port->port_attached = 0; 3515 PM8001_MSG_DBG(pm8001_ha, 3516 pm8001_printk(" phy Down and(default) = %x\n", 3517 portstate)); 3518 break; 3519 3520 } 3521 } 3522 3523 /** 3524 * pm8001_mpi_reg_resp -process register device ID response. 3525 * @pm8001_ha: our hba card information 3526 * @piomb: IO message buffer 3527 * 3528 * when sas layer find a device it will notify LLDD, then the driver register 3529 * the domain device to FW, this event is the return device ID which the FW 3530 * has assigned, from now,inter-communication with FW is no longer using the 3531 * SAS address, use device ID which FW assigned. 3532 */ 3533 int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3534 { 3535 u32 status; 3536 u32 device_id; 3537 u32 htag; 3538 struct pm8001_ccb_info *ccb; 3539 struct pm8001_device *pm8001_dev; 3540 struct dev_reg_resp *registerRespPayload = 3541 (struct dev_reg_resp *)(piomb + 4); 3542 3543 htag = le32_to_cpu(registerRespPayload->tag); 3544 ccb = &pm8001_ha->ccb_info[htag]; 3545 pm8001_dev = ccb->device; 3546 status = le32_to_cpu(registerRespPayload->status); 3547 device_id = le32_to_cpu(registerRespPayload->device_id); 3548 PM8001_MSG_DBG(pm8001_ha, 3549 pm8001_printk(" register device is status = %d\n", status)); 3550 switch (status) { 3551 case DEVREG_SUCCESS: 3552 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("DEVREG_SUCCESS\n")); 3553 pm8001_dev->device_id = device_id; 3554 break; 3555 case DEVREG_FAILURE_OUT_OF_RESOURCE: 3556 PM8001_MSG_DBG(pm8001_ha, 3557 pm8001_printk("DEVREG_FAILURE_OUT_OF_RESOURCE\n")); 3558 break; 3559 case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED: 3560 PM8001_MSG_DBG(pm8001_ha, 3561 pm8001_printk("DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n")); 3562 break; 3563 case DEVREG_FAILURE_INVALID_PHY_ID: 3564 PM8001_MSG_DBG(pm8001_ha, 3565 pm8001_printk("DEVREG_FAILURE_INVALID_PHY_ID\n")); 3566 break; 3567 case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED: 3568 PM8001_MSG_DBG(pm8001_ha, 3569 pm8001_printk("DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n")); 3570 break; 3571 case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE: 3572 PM8001_MSG_DBG(pm8001_ha, 3573 pm8001_printk("DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n")); 3574 break; 3575 case DEVREG_FAILURE_PORT_NOT_VALID_STATE: 3576 PM8001_MSG_DBG(pm8001_ha, 3577 pm8001_printk("DEVREG_FAILURE_PORT_NOT_VALID_STATE\n")); 3578 break; 3579 case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID: 3580 PM8001_MSG_DBG(pm8001_ha, 3581 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n")); 3582 break; 3583 default: 3584 PM8001_MSG_DBG(pm8001_ha, 3585 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_UNSORPORTED\n")); 3586 break; 3587 } 3588 complete(pm8001_dev->dcompletion); 3589 ccb->task = NULL; 3590 ccb->ccb_tag = 0xFFFFFFFF; 3591 pm8001_ccb_free(pm8001_ha, htag); 3592 return 0; 3593 } 3594 3595 int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3596 { 3597 u32 status; 3598 u32 device_id; 3599 struct dev_reg_resp *registerRespPayload = 3600 (struct dev_reg_resp *)(piomb + 4); 3601 3602 status = le32_to_cpu(registerRespPayload->status); 3603 device_id = le32_to_cpu(registerRespPayload->device_id); 3604 if (status != 0) 3605 PM8001_MSG_DBG(pm8001_ha, 3606 pm8001_printk(" deregister device failed ,status = %x" 3607 ", device_id = %x\n", status, device_id)); 3608 return 0; 3609 } 3610 3611 /** 3612 * fw_flash_update_resp - Response from FW for flash update command. 3613 * @pm8001_ha: our hba card information 3614 * @piomb: IO message buffer 3615 */ 3616 int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha, 3617 void *piomb) 3618 { 3619 u32 status; 3620 struct fw_control_ex fw_control_context; 3621 struct fw_flash_Update_resp *ppayload = 3622 (struct fw_flash_Update_resp *)(piomb + 4); 3623 u32 tag = le32_to_cpu(ppayload->tag); 3624 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 3625 status = le32_to_cpu(ppayload->status); 3626 memcpy(&fw_control_context, 3627 ccb->fw_control_context, 3628 sizeof(fw_control_context)); 3629 switch (status) { 3630 case FLASH_UPDATE_COMPLETE_PENDING_REBOOT: 3631 PM8001_MSG_DBG(pm8001_ha, 3632 pm8001_printk(": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n")); 3633 break; 3634 case FLASH_UPDATE_IN_PROGRESS: 3635 PM8001_MSG_DBG(pm8001_ha, 3636 pm8001_printk(": FLASH_UPDATE_IN_PROGRESS\n")); 3637 break; 3638 case FLASH_UPDATE_HDR_ERR: 3639 PM8001_MSG_DBG(pm8001_ha, 3640 pm8001_printk(": FLASH_UPDATE_HDR_ERR\n")); 3641 break; 3642 case FLASH_UPDATE_OFFSET_ERR: 3643 PM8001_MSG_DBG(pm8001_ha, 3644 pm8001_printk(": FLASH_UPDATE_OFFSET_ERR\n")); 3645 break; 3646 case FLASH_UPDATE_CRC_ERR: 3647 PM8001_MSG_DBG(pm8001_ha, 3648 pm8001_printk(": FLASH_UPDATE_CRC_ERR\n")); 3649 break; 3650 case FLASH_UPDATE_LENGTH_ERR: 3651 PM8001_MSG_DBG(pm8001_ha, 3652 pm8001_printk(": FLASH_UPDATE_LENGTH_ERR\n")); 3653 break; 3654 case FLASH_UPDATE_HW_ERR: 3655 PM8001_MSG_DBG(pm8001_ha, 3656 pm8001_printk(": FLASH_UPDATE_HW_ERR\n")); 3657 break; 3658 case FLASH_UPDATE_DNLD_NOT_SUPPORTED: 3659 PM8001_MSG_DBG(pm8001_ha, 3660 pm8001_printk(": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n")); 3661 break; 3662 case FLASH_UPDATE_DISABLED: 3663 PM8001_MSG_DBG(pm8001_ha, 3664 pm8001_printk(": FLASH_UPDATE_DISABLED\n")); 3665 break; 3666 default: 3667 PM8001_MSG_DBG(pm8001_ha, 3668 pm8001_printk("No matched status = %d\n", status)); 3669 break; 3670 } 3671 ccb->fw_control_context->fw_control->retcode = status; 3672 complete(pm8001_ha->nvmd_completion); 3673 ccb->task = NULL; 3674 ccb->ccb_tag = 0xFFFFFFFF; 3675 pm8001_ccb_free(pm8001_ha, tag); 3676 return 0; 3677 } 3678 3679 int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 3680 { 3681 u32 status; 3682 int i; 3683 struct general_event_resp *pPayload = 3684 (struct general_event_resp *)(piomb + 4); 3685 status = le32_to_cpu(pPayload->status); 3686 PM8001_MSG_DBG(pm8001_ha, 3687 pm8001_printk(" status = 0x%x\n", status)); 3688 for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++) 3689 PM8001_MSG_DBG(pm8001_ha, 3690 pm8001_printk("inb_IOMB_payload[0x%x] 0x%x,\n", i, 3691 pPayload->inb_IOMB_payload[i])); 3692 return 0; 3693 } 3694 3695 int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3696 { 3697 struct sas_task *t; 3698 struct pm8001_ccb_info *ccb; 3699 unsigned long flags; 3700 u32 status ; 3701 u32 tag, scp; 3702 struct task_status_struct *ts; 3703 struct pm8001_device *pm8001_dev; 3704 3705 struct task_abort_resp *pPayload = 3706 (struct task_abort_resp *)(piomb + 4); 3707 3708 status = le32_to_cpu(pPayload->status); 3709 tag = le32_to_cpu(pPayload->tag); 3710 if (!tag) { 3711 PM8001_FAIL_DBG(pm8001_ha, 3712 pm8001_printk(" TAG NULL. RETURNING !!!")); 3713 return -1; 3714 } 3715 3716 scp = le32_to_cpu(pPayload->scp); 3717 ccb = &pm8001_ha->ccb_info[tag]; 3718 t = ccb->task; 3719 pm8001_dev = ccb->device; /* retrieve device */ 3720 3721 if (!t) { 3722 PM8001_FAIL_DBG(pm8001_ha, 3723 pm8001_printk(" TASK NULL. RETURNING !!!")); 3724 return -1; 3725 } 3726 ts = &t->task_status; 3727 if (status != 0) 3728 PM8001_FAIL_DBG(pm8001_ha, 3729 pm8001_printk("task abort failed status 0x%x ," 3730 "tag = 0x%x, scp= 0x%x\n", status, tag, scp)); 3731 switch (status) { 3732 case IO_SUCCESS: 3733 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); 3734 ts->resp = SAS_TASK_COMPLETE; 3735 ts->stat = SAM_STAT_GOOD; 3736 break; 3737 case IO_NOT_VALID: 3738 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_NOT_VALID\n")); 3739 ts->resp = TMF_RESP_FUNC_FAILED; 3740 break; 3741 } 3742 spin_lock_irqsave(&t->task_state_lock, flags); 3743 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 3744 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 3745 t->task_state_flags |= SAS_TASK_STATE_DONE; 3746 spin_unlock_irqrestore(&t->task_state_lock, flags); 3747 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 3748 mb(); 3749 3750 if (pm8001_dev->id & NCQ_ABORT_ALL_FLAG) { 3751 pm8001_tag_free(pm8001_ha, tag); 3752 sas_free_task(t); 3753 /* clear the flag */ 3754 pm8001_dev->id &= 0xBFFFFFFF; 3755 } else 3756 t->task_done(t); 3757 3758 return 0; 3759 } 3760 3761 /** 3762 * mpi_hw_event -The hw event has come. 3763 * @pm8001_ha: our hba card information 3764 * @piomb: IO message buffer 3765 */ 3766 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb) 3767 { 3768 unsigned long flags; 3769 struct hw_event_resp *pPayload = 3770 (struct hw_event_resp *)(piomb + 4); 3771 u32 lr_evt_status_phyid_portid = 3772 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3773 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3774 u8 phy_id = 3775 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3776 u16 eventType = 3777 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8); 3778 u8 status = 3779 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24); 3780 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3781 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3782 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id]; 3783 PM8001_MSG_DBG(pm8001_ha, 3784 pm8001_printk("outbound queue HW event & event type : ")); 3785 switch (eventType) { 3786 case HW_EVENT_PHY_START_STATUS: 3787 PM8001_MSG_DBG(pm8001_ha, 3788 pm8001_printk("HW_EVENT_PHY_START_STATUS" 3789 " status = %x\n", status)); 3790 if (status == 0) { 3791 phy->phy_state = 1; 3792 if (pm8001_ha->flags == PM8001F_RUN_TIME) 3793 complete(phy->enable_completion); 3794 } 3795 break; 3796 case HW_EVENT_SAS_PHY_UP: 3797 PM8001_MSG_DBG(pm8001_ha, 3798 pm8001_printk("HW_EVENT_PHY_START_STATUS\n")); 3799 hw_event_sas_phy_up(pm8001_ha, piomb); 3800 break; 3801 case HW_EVENT_SATA_PHY_UP: 3802 PM8001_MSG_DBG(pm8001_ha, 3803 pm8001_printk("HW_EVENT_SATA_PHY_UP\n")); 3804 hw_event_sata_phy_up(pm8001_ha, piomb); 3805 break; 3806 case HW_EVENT_PHY_STOP_STATUS: 3807 PM8001_MSG_DBG(pm8001_ha, 3808 pm8001_printk("HW_EVENT_PHY_STOP_STATUS " 3809 "status = %x\n", status)); 3810 if (status == 0) 3811 phy->phy_state = 0; 3812 break; 3813 case HW_EVENT_SATA_SPINUP_HOLD: 3814 PM8001_MSG_DBG(pm8001_ha, 3815 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n")); 3816 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD); 3817 break; 3818 case HW_EVENT_PHY_DOWN: 3819 PM8001_MSG_DBG(pm8001_ha, 3820 pm8001_printk("HW_EVENT_PHY_DOWN\n")); 3821 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL); 3822 phy->phy_attached = 0; 3823 phy->phy_state = 0; 3824 hw_event_phy_down(pm8001_ha, piomb); 3825 break; 3826 case HW_EVENT_PORT_INVALID: 3827 PM8001_MSG_DBG(pm8001_ha, 3828 pm8001_printk("HW_EVENT_PORT_INVALID\n")); 3829 sas_phy_disconnected(sas_phy); 3830 phy->phy_attached = 0; 3831 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3832 break; 3833 /* the broadcast change primitive received, tell the LIBSAS this event 3834 to revalidate the sas domain*/ 3835 case HW_EVENT_BROADCAST_CHANGE: 3836 PM8001_MSG_DBG(pm8001_ha, 3837 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n")); 3838 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE, 3839 port_id, phy_id, 1, 0); 3840 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3841 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE; 3842 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3843 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3844 break; 3845 case HW_EVENT_PHY_ERROR: 3846 PM8001_MSG_DBG(pm8001_ha, 3847 pm8001_printk("HW_EVENT_PHY_ERROR\n")); 3848 sas_phy_disconnected(&phy->sas_phy); 3849 phy->phy_attached = 0; 3850 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR); 3851 break; 3852 case HW_EVENT_BROADCAST_EXP: 3853 PM8001_MSG_DBG(pm8001_ha, 3854 pm8001_printk("HW_EVENT_BROADCAST_EXP\n")); 3855 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3856 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP; 3857 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3858 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3859 break; 3860 case HW_EVENT_LINK_ERR_INVALID_DWORD: 3861 PM8001_MSG_DBG(pm8001_ha, 3862 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n")); 3863 pm8001_hw_event_ack_req(pm8001_ha, 0, 3864 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0); 3865 sas_phy_disconnected(sas_phy); 3866 phy->phy_attached = 0; 3867 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3868 break; 3869 case HW_EVENT_LINK_ERR_DISPARITY_ERROR: 3870 PM8001_MSG_DBG(pm8001_ha, 3871 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n")); 3872 pm8001_hw_event_ack_req(pm8001_ha, 0, 3873 HW_EVENT_LINK_ERR_DISPARITY_ERROR, 3874 port_id, phy_id, 0, 0); 3875 sas_phy_disconnected(sas_phy); 3876 phy->phy_attached = 0; 3877 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3878 break; 3879 case HW_EVENT_LINK_ERR_CODE_VIOLATION: 3880 PM8001_MSG_DBG(pm8001_ha, 3881 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n")); 3882 pm8001_hw_event_ack_req(pm8001_ha, 0, 3883 HW_EVENT_LINK_ERR_CODE_VIOLATION, 3884 port_id, phy_id, 0, 0); 3885 sas_phy_disconnected(sas_phy); 3886 phy->phy_attached = 0; 3887 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3888 break; 3889 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH: 3890 PM8001_MSG_DBG(pm8001_ha, 3891 pm8001_printk("HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n")); 3892 pm8001_hw_event_ack_req(pm8001_ha, 0, 3893 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH, 3894 port_id, phy_id, 0, 0); 3895 sas_phy_disconnected(sas_phy); 3896 phy->phy_attached = 0; 3897 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3898 break; 3899 case HW_EVENT_MALFUNCTION: 3900 PM8001_MSG_DBG(pm8001_ha, 3901 pm8001_printk("HW_EVENT_MALFUNCTION\n")); 3902 break; 3903 case HW_EVENT_BROADCAST_SES: 3904 PM8001_MSG_DBG(pm8001_ha, 3905 pm8001_printk("HW_EVENT_BROADCAST_SES\n")); 3906 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3907 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES; 3908 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3909 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3910 break; 3911 case HW_EVENT_INBOUND_CRC_ERROR: 3912 PM8001_MSG_DBG(pm8001_ha, 3913 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n")); 3914 pm8001_hw_event_ack_req(pm8001_ha, 0, 3915 HW_EVENT_INBOUND_CRC_ERROR, 3916 port_id, phy_id, 0, 0); 3917 break; 3918 case HW_EVENT_HARD_RESET_RECEIVED: 3919 PM8001_MSG_DBG(pm8001_ha, 3920 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n")); 3921 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET); 3922 break; 3923 case HW_EVENT_ID_FRAME_TIMEOUT: 3924 PM8001_MSG_DBG(pm8001_ha, 3925 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n")); 3926 sas_phy_disconnected(sas_phy); 3927 phy->phy_attached = 0; 3928 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3929 break; 3930 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED: 3931 PM8001_MSG_DBG(pm8001_ha, 3932 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n")); 3933 pm8001_hw_event_ack_req(pm8001_ha, 0, 3934 HW_EVENT_LINK_ERR_PHY_RESET_FAILED, 3935 port_id, phy_id, 0, 0); 3936 sas_phy_disconnected(sas_phy); 3937 phy->phy_attached = 0; 3938 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3939 break; 3940 case HW_EVENT_PORT_RESET_TIMER_TMO: 3941 PM8001_MSG_DBG(pm8001_ha, 3942 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n")); 3943 sas_phy_disconnected(sas_phy); 3944 phy->phy_attached = 0; 3945 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3946 break; 3947 case HW_EVENT_PORT_RECOVERY_TIMER_TMO: 3948 PM8001_MSG_DBG(pm8001_ha, 3949 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n")); 3950 sas_phy_disconnected(sas_phy); 3951 phy->phy_attached = 0; 3952 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3953 break; 3954 case HW_EVENT_PORT_RECOVER: 3955 PM8001_MSG_DBG(pm8001_ha, 3956 pm8001_printk("HW_EVENT_PORT_RECOVER\n")); 3957 break; 3958 case HW_EVENT_PORT_RESET_COMPLETE: 3959 PM8001_MSG_DBG(pm8001_ha, 3960 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n")); 3961 break; 3962 case EVENT_BROADCAST_ASYNCH_EVENT: 3963 PM8001_MSG_DBG(pm8001_ha, 3964 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n")); 3965 break; 3966 default: 3967 PM8001_MSG_DBG(pm8001_ha, 3968 pm8001_printk("Unknown event type = %x\n", eventType)); 3969 break; 3970 } 3971 return 0; 3972 } 3973 3974 /** 3975 * process_one_iomb - process one outbound Queue memory block 3976 * @pm8001_ha: our hba card information 3977 * @piomb: IO message buffer 3978 */ 3979 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb) 3980 { 3981 __le32 pHeader = *(__le32 *)piomb; 3982 u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF); 3983 3984 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("process_one_iomb:")); 3985 3986 switch (opc) { 3987 case OPC_OUB_ECHO: 3988 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n")); 3989 break; 3990 case OPC_OUB_HW_EVENT: 3991 PM8001_MSG_DBG(pm8001_ha, 3992 pm8001_printk("OPC_OUB_HW_EVENT\n")); 3993 mpi_hw_event(pm8001_ha, piomb); 3994 break; 3995 case OPC_OUB_SSP_COMP: 3996 PM8001_MSG_DBG(pm8001_ha, 3997 pm8001_printk("OPC_OUB_SSP_COMP\n")); 3998 mpi_ssp_completion(pm8001_ha, piomb); 3999 break; 4000 case OPC_OUB_SMP_COMP: 4001 PM8001_MSG_DBG(pm8001_ha, 4002 pm8001_printk("OPC_OUB_SMP_COMP\n")); 4003 mpi_smp_completion(pm8001_ha, piomb); 4004 break; 4005 case OPC_OUB_LOCAL_PHY_CNTRL: 4006 PM8001_MSG_DBG(pm8001_ha, 4007 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n")); 4008 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb); 4009 break; 4010 case OPC_OUB_DEV_REGIST: 4011 PM8001_MSG_DBG(pm8001_ha, 4012 pm8001_printk("OPC_OUB_DEV_REGIST\n")); 4013 pm8001_mpi_reg_resp(pm8001_ha, piomb); 4014 break; 4015 case OPC_OUB_DEREG_DEV: 4016 PM8001_MSG_DBG(pm8001_ha, 4017 pm8001_printk("unregister the device\n")); 4018 pm8001_mpi_dereg_resp(pm8001_ha, piomb); 4019 break; 4020 case OPC_OUB_GET_DEV_HANDLE: 4021 PM8001_MSG_DBG(pm8001_ha, 4022 pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n")); 4023 break; 4024 case OPC_OUB_SATA_COMP: 4025 PM8001_MSG_DBG(pm8001_ha, 4026 pm8001_printk("OPC_OUB_SATA_COMP\n")); 4027 mpi_sata_completion(pm8001_ha, piomb); 4028 break; 4029 case OPC_OUB_SATA_EVENT: 4030 PM8001_MSG_DBG(pm8001_ha, 4031 pm8001_printk("OPC_OUB_SATA_EVENT\n")); 4032 mpi_sata_event(pm8001_ha, piomb); 4033 break; 4034 case OPC_OUB_SSP_EVENT: 4035 PM8001_MSG_DBG(pm8001_ha, 4036 pm8001_printk("OPC_OUB_SSP_EVENT\n")); 4037 mpi_ssp_event(pm8001_ha, piomb); 4038 break; 4039 case OPC_OUB_DEV_HANDLE_ARRIV: 4040 PM8001_MSG_DBG(pm8001_ha, 4041 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n")); 4042 /*This is for target*/ 4043 break; 4044 case OPC_OUB_SSP_RECV_EVENT: 4045 PM8001_MSG_DBG(pm8001_ha, 4046 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n")); 4047 /*This is for target*/ 4048 break; 4049 case OPC_OUB_DEV_INFO: 4050 PM8001_MSG_DBG(pm8001_ha, 4051 pm8001_printk("OPC_OUB_DEV_INFO\n")); 4052 break; 4053 case OPC_OUB_FW_FLASH_UPDATE: 4054 PM8001_MSG_DBG(pm8001_ha, 4055 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n")); 4056 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb); 4057 break; 4058 case OPC_OUB_GPIO_RESPONSE: 4059 PM8001_MSG_DBG(pm8001_ha, 4060 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n")); 4061 break; 4062 case OPC_OUB_GPIO_EVENT: 4063 PM8001_MSG_DBG(pm8001_ha, 4064 pm8001_printk("OPC_OUB_GPIO_EVENT\n")); 4065 break; 4066 case OPC_OUB_GENERAL_EVENT: 4067 PM8001_MSG_DBG(pm8001_ha, 4068 pm8001_printk("OPC_OUB_GENERAL_EVENT\n")); 4069 pm8001_mpi_general_event(pm8001_ha, piomb); 4070 break; 4071 case OPC_OUB_SSP_ABORT_RSP: 4072 PM8001_MSG_DBG(pm8001_ha, 4073 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n")); 4074 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 4075 break; 4076 case OPC_OUB_SATA_ABORT_RSP: 4077 PM8001_MSG_DBG(pm8001_ha, 4078 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n")); 4079 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 4080 break; 4081 case OPC_OUB_SAS_DIAG_MODE_START_END: 4082 PM8001_MSG_DBG(pm8001_ha, 4083 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n")); 4084 break; 4085 case OPC_OUB_SAS_DIAG_EXECUTE: 4086 PM8001_MSG_DBG(pm8001_ha, 4087 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n")); 4088 break; 4089 case OPC_OUB_GET_TIME_STAMP: 4090 PM8001_MSG_DBG(pm8001_ha, 4091 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n")); 4092 break; 4093 case OPC_OUB_SAS_HW_EVENT_ACK: 4094 PM8001_MSG_DBG(pm8001_ha, 4095 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n")); 4096 break; 4097 case OPC_OUB_PORT_CONTROL: 4098 PM8001_MSG_DBG(pm8001_ha, 4099 pm8001_printk("OPC_OUB_PORT_CONTROL\n")); 4100 break; 4101 case OPC_OUB_SMP_ABORT_RSP: 4102 PM8001_MSG_DBG(pm8001_ha, 4103 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n")); 4104 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 4105 break; 4106 case OPC_OUB_GET_NVMD_DATA: 4107 PM8001_MSG_DBG(pm8001_ha, 4108 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n")); 4109 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb); 4110 break; 4111 case OPC_OUB_SET_NVMD_DATA: 4112 PM8001_MSG_DBG(pm8001_ha, 4113 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n")); 4114 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb); 4115 break; 4116 case OPC_OUB_DEVICE_HANDLE_REMOVAL: 4117 PM8001_MSG_DBG(pm8001_ha, 4118 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n")); 4119 break; 4120 case OPC_OUB_SET_DEVICE_STATE: 4121 PM8001_MSG_DBG(pm8001_ha, 4122 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n")); 4123 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb); 4124 break; 4125 case OPC_OUB_GET_DEVICE_STATE: 4126 PM8001_MSG_DBG(pm8001_ha, 4127 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n")); 4128 break; 4129 case OPC_OUB_SET_DEV_INFO: 4130 PM8001_MSG_DBG(pm8001_ha, 4131 pm8001_printk("OPC_OUB_SET_DEV_INFO\n")); 4132 break; 4133 case OPC_OUB_SAS_RE_INITIALIZE: 4134 PM8001_MSG_DBG(pm8001_ha, 4135 pm8001_printk("OPC_OUB_SAS_RE_INITIALIZE\n")); 4136 break; 4137 default: 4138 PM8001_MSG_DBG(pm8001_ha, 4139 pm8001_printk("Unknown outbound Queue IOMB OPC = %x\n", 4140 opc)); 4141 break; 4142 } 4143 } 4144 4145 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec) 4146 { 4147 struct outbound_queue_table *circularQ; 4148 void *pMsg1 = NULL; 4149 u8 uninitialized_var(bc); 4150 u32 ret = MPI_IO_STATUS_FAIL; 4151 unsigned long flags; 4152 4153 spin_lock_irqsave(&pm8001_ha->lock, flags); 4154 circularQ = &pm8001_ha->outbnd_q_tbl[vec]; 4155 do { 4156 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc); 4157 if (MPI_IO_STATUS_SUCCESS == ret) { 4158 /* process the outbound message */ 4159 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4)); 4160 /* free the message from the outbound circular buffer */ 4161 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1, 4162 circularQ, bc); 4163 } 4164 if (MPI_IO_STATUS_BUSY == ret) { 4165 /* Update the producer index from SPC */ 4166 circularQ->producer_index = 4167 cpu_to_le32(pm8001_read_32(circularQ->pi_virt)); 4168 if (le32_to_cpu(circularQ->producer_index) == 4169 circularQ->consumer_idx) 4170 /* OQ is empty */ 4171 break; 4172 } 4173 } while (1); 4174 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 4175 return ret; 4176 } 4177 4178 /* PCI_DMA_... to our direction translation. */ 4179 static const u8 data_dir_flags[] = { 4180 [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */ 4181 [PCI_DMA_TODEVICE] = DATA_DIR_OUT,/* OUTBOUND */ 4182 [PCI_DMA_FROMDEVICE] = DATA_DIR_IN,/* INBOUND */ 4183 [PCI_DMA_NONE] = DATA_DIR_NONE,/* NO TRANSFER */ 4184 }; 4185 void 4186 pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd) 4187 { 4188 int i; 4189 struct scatterlist *sg; 4190 struct pm8001_prd *buf_prd = prd; 4191 4192 for_each_sg(scatter, sg, nr, i) { 4193 buf_prd->addr = cpu_to_le64(sg_dma_address(sg)); 4194 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg)); 4195 buf_prd->im_len.e = 0; 4196 buf_prd++; 4197 } 4198 } 4199 4200 static void build_smp_cmd(u32 deviceID, __le32 hTag, struct smp_req *psmp_cmd) 4201 { 4202 psmp_cmd->tag = hTag; 4203 psmp_cmd->device_id = cpu_to_le32(deviceID); 4204 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1)); 4205 } 4206 4207 /** 4208 * pm8001_chip_smp_req - send a SMP task to FW 4209 * @pm8001_ha: our hba card information. 4210 * @ccb: the ccb information this request used. 4211 */ 4212 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha, 4213 struct pm8001_ccb_info *ccb) 4214 { 4215 int elem, rc; 4216 struct sas_task *task = ccb->task; 4217 struct domain_device *dev = task->dev; 4218 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4219 struct scatterlist *sg_req, *sg_resp; 4220 u32 req_len, resp_len; 4221 struct smp_req smp_cmd; 4222 u32 opc; 4223 struct inbound_queue_table *circularQ; 4224 4225 memset(&smp_cmd, 0, sizeof(smp_cmd)); 4226 /* 4227 * DMA-map SMP request, response buffers 4228 */ 4229 sg_req = &task->smp_task.smp_req; 4230 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE); 4231 if (!elem) 4232 return -ENOMEM; 4233 req_len = sg_dma_len(sg_req); 4234 4235 sg_resp = &task->smp_task.smp_resp; 4236 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE); 4237 if (!elem) { 4238 rc = -ENOMEM; 4239 goto err_out; 4240 } 4241 resp_len = sg_dma_len(sg_resp); 4242 /* must be in dwords */ 4243 if ((req_len & 0x3) || (resp_len & 0x3)) { 4244 rc = -EINVAL; 4245 goto err_out_2; 4246 } 4247 4248 opc = OPC_INB_SMP_REQUEST; 4249 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4250 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag); 4251 smp_cmd.long_smp_req.long_req_addr = 4252 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req)); 4253 smp_cmd.long_smp_req.long_req_size = 4254 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4); 4255 smp_cmd.long_smp_req.long_resp_addr = 4256 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp)); 4257 smp_cmd.long_smp_req.long_resp_size = 4258 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4); 4259 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd); 4260 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd, 0); 4261 return 0; 4262 4263 err_out_2: 4264 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1, 4265 PCI_DMA_FROMDEVICE); 4266 err_out: 4267 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1, 4268 PCI_DMA_TODEVICE); 4269 return rc; 4270 } 4271 4272 /** 4273 * pm8001_chip_ssp_io_req - send a SSP task to FW 4274 * @pm8001_ha: our hba card information. 4275 * @ccb: the ccb information this request used. 4276 */ 4277 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha, 4278 struct pm8001_ccb_info *ccb) 4279 { 4280 struct sas_task *task = ccb->task; 4281 struct domain_device *dev = task->dev; 4282 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4283 struct ssp_ini_io_start_req ssp_cmd; 4284 u32 tag = ccb->ccb_tag; 4285 int ret; 4286 u64 phys_addr; 4287 struct inbound_queue_table *circularQ; 4288 u32 opc = OPC_INB_SSPINIIOSTART; 4289 memset(&ssp_cmd, 0, sizeof(ssp_cmd)); 4290 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8); 4291 ssp_cmd.dir_m_tlr = 4292 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for 4293 SAS 1.1 compatible TLR*/ 4294 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4295 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id); 4296 ssp_cmd.tag = cpu_to_le32(tag); 4297 if (task->ssp_task.enable_first_burst) 4298 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80; 4299 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3); 4300 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7); 4301 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd, 4302 task->ssp_task.cmd->cmd_len); 4303 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4304 4305 /* fill in PRD (scatter/gather) table, if any */ 4306 if (task->num_scatter > 1) { 4307 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd); 4308 phys_addr = ccb->ccb_dma_handle + 4309 offsetof(struct pm8001_ccb_info, buf_prd[0]); 4310 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(phys_addr)); 4311 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr)); 4312 ssp_cmd.esgl = cpu_to_le32(1<<31); 4313 } else if (task->num_scatter == 1) { 4314 u64 dma_addr = sg_dma_address(task->scatter); 4315 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr)); 4316 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr)); 4317 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4318 ssp_cmd.esgl = 0; 4319 } else if (task->num_scatter == 0) { 4320 ssp_cmd.addr_low = 0; 4321 ssp_cmd.addr_high = 0; 4322 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4323 ssp_cmd.esgl = 0; 4324 } 4325 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd, 0); 4326 return ret; 4327 } 4328 4329 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha, 4330 struct pm8001_ccb_info *ccb) 4331 { 4332 struct sas_task *task = ccb->task; 4333 struct domain_device *dev = task->dev; 4334 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev; 4335 u32 tag = ccb->ccb_tag; 4336 int ret; 4337 struct sata_start_req sata_cmd; 4338 u32 hdr_tag, ncg_tag = 0; 4339 u64 phys_addr; 4340 u32 ATAP = 0x0; 4341 u32 dir; 4342 struct inbound_queue_table *circularQ; 4343 unsigned long flags; 4344 u32 opc = OPC_INB_SATA_HOST_OPSTART; 4345 memset(&sata_cmd, 0, sizeof(sata_cmd)); 4346 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4347 if (task->data_dir == PCI_DMA_NONE) { 4348 ATAP = 0x04; /* no data*/ 4349 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n")); 4350 } else if (likely(!task->ata_task.device_control_reg_update)) { 4351 if (task->ata_task.dma_xfer) { 4352 ATAP = 0x06; /* DMA */ 4353 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n")); 4354 } else { 4355 ATAP = 0x05; /* PIO*/ 4356 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n")); 4357 } 4358 if (task->ata_task.use_ncq && 4359 dev->sata_dev.command_set != ATAPI_COMMAND_SET) { 4360 ATAP = 0x07; /* FPDMA */ 4361 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n")); 4362 } 4363 } 4364 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) { 4365 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 4366 ncg_tag = hdr_tag; 4367 } 4368 dir = data_dir_flags[task->data_dir] << 8; 4369 sata_cmd.tag = cpu_to_le32(tag); 4370 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 4371 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4372 sata_cmd.ncqtag_atap_dir_m = 4373 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir); 4374 sata_cmd.sata_fis = task->ata_task.fis; 4375 if (likely(!task->ata_task.device_control_reg_update)) 4376 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */ 4377 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */ 4378 /* fill in PRD (scatter/gather) table, if any */ 4379 if (task->num_scatter > 1) { 4380 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd); 4381 phys_addr = ccb->ccb_dma_handle + 4382 offsetof(struct pm8001_ccb_info, buf_prd[0]); 4383 sata_cmd.addr_low = lower_32_bits(phys_addr); 4384 sata_cmd.addr_high = upper_32_bits(phys_addr); 4385 sata_cmd.esgl = cpu_to_le32(1 << 31); 4386 } else if (task->num_scatter == 1) { 4387 u64 dma_addr = sg_dma_address(task->scatter); 4388 sata_cmd.addr_low = lower_32_bits(dma_addr); 4389 sata_cmd.addr_high = upper_32_bits(dma_addr); 4390 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4391 sata_cmd.esgl = 0; 4392 } else if (task->num_scatter == 0) { 4393 sata_cmd.addr_low = 0; 4394 sata_cmd.addr_high = 0; 4395 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4396 sata_cmd.esgl = 0; 4397 } 4398 4399 /* Check for read log for failed drive and return */ 4400 if (sata_cmd.sata_fis.command == 0x2f) { 4401 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) || 4402 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) || 4403 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) { 4404 struct task_status_struct *ts; 4405 4406 pm8001_ha_dev->id &= 0xDFFFFFFF; 4407 ts = &task->task_status; 4408 4409 spin_lock_irqsave(&task->task_state_lock, flags); 4410 ts->resp = SAS_TASK_COMPLETE; 4411 ts->stat = SAM_STAT_GOOD; 4412 task->task_state_flags &= ~SAS_TASK_STATE_PENDING; 4413 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 4414 task->task_state_flags |= SAS_TASK_STATE_DONE; 4415 if (unlikely((task->task_state_flags & 4416 SAS_TASK_STATE_ABORTED))) { 4417 spin_unlock_irqrestore(&task->task_state_lock, 4418 flags); 4419 PM8001_FAIL_DBG(pm8001_ha, 4420 pm8001_printk("task 0x%p resp 0x%x " 4421 " stat 0x%x but aborted by upper layer " 4422 "\n", task, ts->resp, ts->stat)); 4423 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag); 4424 } else { 4425 spin_unlock_irqrestore(&task->task_state_lock, 4426 flags); 4427 pm8001_ccb_task_free_done(pm8001_ha, task, 4428 ccb, tag); 4429 return 0; 4430 } 4431 } 4432 } 4433 4434 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0); 4435 return ret; 4436 } 4437 4438 /** 4439 * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND 4440 * @pm8001_ha: our hba card information. 4441 * @num: the inbound queue number 4442 * @phy_id: the phy id which we wanted to start up. 4443 */ 4444 static int 4445 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id) 4446 { 4447 struct phy_start_req payload; 4448 struct inbound_queue_table *circularQ; 4449 int ret; 4450 u32 tag = 0x01; 4451 u32 opcode = OPC_INB_PHYSTART; 4452 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4453 memset(&payload, 0, sizeof(payload)); 4454 payload.tag = cpu_to_le32(tag); 4455 /* 4456 ** [0:7] PHY Identifier 4457 ** [8:11] link rate 1.5G, 3G, 6G 4458 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both 4459 ** [14] 0b disable spin up hold; 1b enable spin up hold 4460 */ 4461 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE | 4462 LINKMODE_AUTO | LINKRATE_15 | 4463 LINKRATE_30 | LINKRATE_60 | phy_id); 4464 payload.sas_identify.dev_type = SAS_END_DEVICE; 4465 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL; 4466 memcpy(payload.sas_identify.sas_addr, 4467 pm8001_ha->sas_addr, SAS_ADDR_SIZE); 4468 payload.sas_identify.phy_id = phy_id; 4469 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0); 4470 return ret; 4471 } 4472 4473 /** 4474 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND 4475 * @pm8001_ha: our hba card information. 4476 * @num: the inbound queue number 4477 * @phy_id: the phy id which we wanted to start up. 4478 */ 4479 int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha, 4480 u8 phy_id) 4481 { 4482 struct phy_stop_req payload; 4483 struct inbound_queue_table *circularQ; 4484 int ret; 4485 u32 tag = 0x01; 4486 u32 opcode = OPC_INB_PHYSTOP; 4487 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4488 memset(&payload, 0, sizeof(payload)); 4489 payload.tag = cpu_to_le32(tag); 4490 payload.phy_id = cpu_to_le32(phy_id); 4491 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0); 4492 return ret; 4493 } 4494 4495 /** 4496 * see comments on pm8001_mpi_reg_resp. 4497 */ 4498 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha, 4499 struct pm8001_device *pm8001_dev, u32 flag) 4500 { 4501 struct reg_dev_req payload; 4502 u32 opc; 4503 u32 stp_sspsmp_sata = 0x4; 4504 struct inbound_queue_table *circularQ; 4505 u32 linkrate, phy_id; 4506 int rc, tag = 0xdeadbeef; 4507 struct pm8001_ccb_info *ccb; 4508 u8 retryFlag = 0x1; 4509 u16 firstBurstSize = 0; 4510 u16 ITNT = 2000; 4511 struct domain_device *dev = pm8001_dev->sas_device; 4512 struct domain_device *parent_dev = dev->parent; 4513 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4514 4515 memset(&payload, 0, sizeof(payload)); 4516 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4517 if (rc) 4518 return rc; 4519 ccb = &pm8001_ha->ccb_info[tag]; 4520 ccb->device = pm8001_dev; 4521 ccb->ccb_tag = tag; 4522 payload.tag = cpu_to_le32(tag); 4523 if (flag == 1) 4524 stp_sspsmp_sata = 0x02; /*direct attached sata */ 4525 else { 4526 if (pm8001_dev->dev_type == SAS_SATA_DEV) 4527 stp_sspsmp_sata = 0x00; /* stp*/ 4528 else if (pm8001_dev->dev_type == SAS_END_DEVICE || 4529 pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE || 4530 pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE) 4531 stp_sspsmp_sata = 0x01; /*ssp or smp*/ 4532 } 4533 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 4534 phy_id = parent_dev->ex_dev.ex_phy->phy_id; 4535 else 4536 phy_id = pm8001_dev->attached_phy; 4537 opc = OPC_INB_REG_DEV; 4538 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ? 4539 pm8001_dev->sas_device->linkrate : dev->port->linkrate; 4540 payload.phyid_portid = 4541 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) | 4542 ((phy_id & 0x0F) << 4)); 4543 payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) | 4544 ((linkrate & 0x0F) * 0x1000000) | 4545 ((stp_sspsmp_sata & 0x03) * 0x10000000)); 4546 payload.firstburstsize_ITNexustimeout = 4547 cpu_to_le32(ITNT | (firstBurstSize * 0x10000)); 4548 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr, 4549 SAS_ADDR_SIZE); 4550 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 4551 return rc; 4552 } 4553 4554 /** 4555 * see comments on pm8001_mpi_reg_resp. 4556 */ 4557 int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha, 4558 u32 device_id) 4559 { 4560 struct dereg_dev_req payload; 4561 u32 opc = OPC_INB_DEREG_DEV_HANDLE; 4562 int ret; 4563 struct inbound_queue_table *circularQ; 4564 4565 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4566 memset(&payload, 0, sizeof(payload)); 4567 payload.tag = cpu_to_le32(1); 4568 payload.device_id = cpu_to_le32(device_id); 4569 PM8001_MSG_DBG(pm8001_ha, 4570 pm8001_printk("unregister device device_id = %d\n", device_id)); 4571 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 4572 return ret; 4573 } 4574 4575 /** 4576 * pm8001_chip_phy_ctl_req - support the local phy operation 4577 * @pm8001_ha: our hba card information. 4578 * @num: the inbound queue number 4579 * @phy_id: the phy id which we wanted to operate 4580 * @phy_op: 4581 */ 4582 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 4583 u32 phyId, u32 phy_op) 4584 { 4585 struct local_phy_ctl_req payload; 4586 struct inbound_queue_table *circularQ; 4587 int ret; 4588 u32 opc = OPC_INB_LOCAL_PHY_CONTROL; 4589 memset(&payload, 0, sizeof(payload)); 4590 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4591 payload.tag = cpu_to_le32(1); 4592 payload.phyop_phyid = 4593 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F)); 4594 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 4595 return ret; 4596 } 4597 4598 static u32 pm8001_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha) 4599 { 4600 u32 value; 4601 #ifdef PM8001_USE_MSIX 4602 return 1; 4603 #endif 4604 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR); 4605 if (value) 4606 return 1; 4607 return 0; 4608 4609 } 4610 4611 /** 4612 * pm8001_chip_isr - PM8001 isr handler. 4613 * @pm8001_ha: our hba card information. 4614 * @irq: irq number. 4615 * @stat: stat. 4616 */ 4617 static irqreturn_t 4618 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec) 4619 { 4620 pm8001_chip_interrupt_disable(pm8001_ha, vec); 4621 process_oq(pm8001_ha, vec); 4622 pm8001_chip_interrupt_enable(pm8001_ha, vec); 4623 return IRQ_HANDLED; 4624 } 4625 4626 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc, 4627 u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag) 4628 { 4629 struct task_abort_req task_abort; 4630 struct inbound_queue_table *circularQ; 4631 int ret; 4632 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4633 memset(&task_abort, 0, sizeof(task_abort)); 4634 if (ABORT_SINGLE == (flag & ABORT_MASK)) { 4635 task_abort.abort_all = 0; 4636 task_abort.device_id = cpu_to_le32(dev_id); 4637 task_abort.tag_to_abort = cpu_to_le32(task_tag); 4638 task_abort.tag = cpu_to_le32(cmd_tag); 4639 } else if (ABORT_ALL == (flag & ABORT_MASK)) { 4640 task_abort.abort_all = cpu_to_le32(1); 4641 task_abort.device_id = cpu_to_le32(dev_id); 4642 task_abort.tag = cpu_to_le32(cmd_tag); 4643 } 4644 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0); 4645 return ret; 4646 } 4647 4648 /** 4649 * pm8001_chip_abort_task - SAS abort task when error or exception happened. 4650 * @task: the task we wanted to aborted. 4651 * @flag: the abort flag. 4652 */ 4653 int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha, 4654 struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag) 4655 { 4656 u32 opc, device_id; 4657 int rc = TMF_RESP_FUNC_FAILED; 4658 PM8001_EH_DBG(pm8001_ha, 4659 pm8001_printk("cmd_tag = %x, abort task tag = 0x%x", 4660 cmd_tag, task_tag)); 4661 if (pm8001_dev->dev_type == SAS_END_DEVICE) 4662 opc = OPC_INB_SSP_ABORT; 4663 else if (pm8001_dev->dev_type == SAS_SATA_DEV) 4664 opc = OPC_INB_SATA_ABORT; 4665 else 4666 opc = OPC_INB_SMP_ABORT;/* SMP */ 4667 device_id = pm8001_dev->device_id; 4668 rc = send_task_abort(pm8001_ha, opc, device_id, flag, 4669 task_tag, cmd_tag); 4670 if (rc != TMF_RESP_FUNC_COMPLETE) 4671 PM8001_EH_DBG(pm8001_ha, pm8001_printk("rc= %d\n", rc)); 4672 return rc; 4673 } 4674 4675 /** 4676 * pm8001_chip_ssp_tm_req - built the task management command. 4677 * @pm8001_ha: our hba card information. 4678 * @ccb: the ccb information. 4679 * @tmf: task management function. 4680 */ 4681 int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha, 4682 struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf) 4683 { 4684 struct sas_task *task = ccb->task; 4685 struct domain_device *dev = task->dev; 4686 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4687 u32 opc = OPC_INB_SSPINITMSTART; 4688 struct inbound_queue_table *circularQ; 4689 struct ssp_ini_tm_start_req sspTMCmd; 4690 int ret; 4691 4692 memset(&sspTMCmd, 0, sizeof(sspTMCmd)); 4693 sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id); 4694 sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed); 4695 sspTMCmd.tmf = cpu_to_le32(tmf->tmf); 4696 memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8); 4697 sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag); 4698 if (pm8001_ha->chip_id != chip_8001) 4699 sspTMCmd.ds_ads_m = 0x08; 4700 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4701 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd, 0); 4702 return ret; 4703 } 4704 4705 int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha, 4706 void *payload) 4707 { 4708 u32 opc = OPC_INB_GET_NVMD_DATA; 4709 u32 nvmd_type; 4710 int rc; 4711 u32 tag; 4712 struct pm8001_ccb_info *ccb; 4713 struct inbound_queue_table *circularQ; 4714 struct get_nvm_data_req nvmd_req; 4715 struct fw_control_ex *fw_control_context; 4716 struct pm8001_ioctl_payload *ioctl_payload = payload; 4717 4718 nvmd_type = ioctl_payload->minor_function; 4719 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); 4720 if (!fw_control_context) 4721 return -ENOMEM; 4722 fw_control_context->usrAddr = (u8 *)ioctl_payload->func_specific; 4723 fw_control_context->len = ioctl_payload->length; 4724 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4725 memset(&nvmd_req, 0, sizeof(nvmd_req)); 4726 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4727 if (rc) { 4728 kfree(fw_control_context); 4729 return rc; 4730 } 4731 ccb = &pm8001_ha->ccb_info[tag]; 4732 ccb->ccb_tag = tag; 4733 ccb->fw_control_context = fw_control_context; 4734 nvmd_req.tag = cpu_to_le32(tag); 4735 4736 switch (nvmd_type) { 4737 case TWI_DEVICE: { 4738 u32 twi_addr, twi_page_size; 4739 twi_addr = 0xa8; 4740 twi_page_size = 2; 4741 4742 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 | 4743 twi_page_size << 8 | TWI_DEVICE); 4744 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4745 nvmd_req.resp_addr_hi = 4746 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4747 nvmd_req.resp_addr_lo = 4748 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4749 break; 4750 } 4751 case C_SEEPROM: { 4752 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM); 4753 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4754 nvmd_req.resp_addr_hi = 4755 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4756 nvmd_req.resp_addr_lo = 4757 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4758 break; 4759 } 4760 case VPD_FLASH: { 4761 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH); 4762 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4763 nvmd_req.resp_addr_hi = 4764 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4765 nvmd_req.resp_addr_lo = 4766 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4767 break; 4768 } 4769 case EXPAN_ROM: { 4770 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM); 4771 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4772 nvmd_req.resp_addr_hi = 4773 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4774 nvmd_req.resp_addr_lo = 4775 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4776 break; 4777 } 4778 case IOP_RDUMP: { 4779 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | IOP_RDUMP); 4780 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4781 nvmd_req.vpd_offset = cpu_to_le32(ioctl_payload->offset); 4782 nvmd_req.resp_addr_hi = 4783 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4784 nvmd_req.resp_addr_lo = 4785 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4786 break; 4787 } 4788 default: 4789 break; 4790 } 4791 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req, 0); 4792 return rc; 4793 } 4794 4795 int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha, 4796 void *payload) 4797 { 4798 u32 opc = OPC_INB_SET_NVMD_DATA; 4799 u32 nvmd_type; 4800 int rc; 4801 u32 tag; 4802 struct pm8001_ccb_info *ccb; 4803 struct inbound_queue_table *circularQ; 4804 struct set_nvm_data_req nvmd_req; 4805 struct fw_control_ex *fw_control_context; 4806 struct pm8001_ioctl_payload *ioctl_payload = payload; 4807 4808 nvmd_type = ioctl_payload->minor_function; 4809 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); 4810 if (!fw_control_context) 4811 return -ENOMEM; 4812 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4813 memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr, 4814 &ioctl_payload->func_specific, 4815 ioctl_payload->length); 4816 memset(&nvmd_req, 0, sizeof(nvmd_req)); 4817 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4818 if (rc) { 4819 kfree(fw_control_context); 4820 return rc; 4821 } 4822 ccb = &pm8001_ha->ccb_info[tag]; 4823 ccb->fw_control_context = fw_control_context; 4824 ccb->ccb_tag = tag; 4825 nvmd_req.tag = cpu_to_le32(tag); 4826 switch (nvmd_type) { 4827 case TWI_DEVICE: { 4828 u32 twi_addr, twi_page_size; 4829 twi_addr = 0xa8; 4830 twi_page_size = 2; 4831 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4832 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 | 4833 twi_page_size << 8 | TWI_DEVICE); 4834 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4835 nvmd_req.resp_addr_hi = 4836 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4837 nvmd_req.resp_addr_lo = 4838 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4839 break; 4840 } 4841 case C_SEEPROM: 4842 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM); 4843 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4844 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4845 nvmd_req.resp_addr_hi = 4846 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4847 nvmd_req.resp_addr_lo = 4848 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4849 break; 4850 case VPD_FLASH: 4851 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH); 4852 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4853 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4854 nvmd_req.resp_addr_hi = 4855 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4856 nvmd_req.resp_addr_lo = 4857 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4858 break; 4859 case EXPAN_ROM: 4860 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM); 4861 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4862 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4863 nvmd_req.resp_addr_hi = 4864 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4865 nvmd_req.resp_addr_lo = 4866 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4867 break; 4868 default: 4869 break; 4870 } 4871 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req, 0); 4872 return rc; 4873 } 4874 4875 /** 4876 * pm8001_chip_fw_flash_update_build - support the firmware update operation 4877 * @pm8001_ha: our hba card information. 4878 * @fw_flash_updata_info: firmware flash update param 4879 */ 4880 int 4881 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha, 4882 void *fw_flash_updata_info, u32 tag) 4883 { 4884 struct fw_flash_Update_req payload; 4885 struct fw_flash_updata_info *info; 4886 struct inbound_queue_table *circularQ; 4887 int ret; 4888 u32 opc = OPC_INB_FW_FLASH_UPDATE; 4889 4890 memset(&payload, 0, sizeof(struct fw_flash_Update_req)); 4891 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4892 info = fw_flash_updata_info; 4893 payload.tag = cpu_to_le32(tag); 4894 payload.cur_image_len = cpu_to_le32(info->cur_image_len); 4895 payload.cur_image_offset = cpu_to_le32(info->cur_image_offset); 4896 payload.total_image_len = cpu_to_le32(info->total_image_len); 4897 payload.len = info->sgl.im_len.len ; 4898 payload.sgl_addr_lo = 4899 cpu_to_le32(lower_32_bits(le64_to_cpu(info->sgl.addr))); 4900 payload.sgl_addr_hi = 4901 cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr))); 4902 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 4903 return ret; 4904 } 4905 4906 int 4907 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha, 4908 void *payload) 4909 { 4910 struct fw_flash_updata_info flash_update_info; 4911 struct fw_control_info *fw_control; 4912 struct fw_control_ex *fw_control_context; 4913 int rc; 4914 u32 tag; 4915 struct pm8001_ccb_info *ccb; 4916 void *buffer = pm8001_ha->memoryMap.region[FW_FLASH].virt_ptr; 4917 dma_addr_t phys_addr = pm8001_ha->memoryMap.region[FW_FLASH].phys_addr; 4918 struct pm8001_ioctl_payload *ioctl_payload = payload; 4919 4920 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); 4921 if (!fw_control_context) 4922 return -ENOMEM; 4923 fw_control = (struct fw_control_info *)&ioctl_payload->func_specific; 4924 memcpy(buffer, fw_control->buffer, fw_control->len); 4925 flash_update_info.sgl.addr = cpu_to_le64(phys_addr); 4926 flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len); 4927 flash_update_info.sgl.im_len.e = 0; 4928 flash_update_info.cur_image_offset = fw_control->offset; 4929 flash_update_info.cur_image_len = fw_control->len; 4930 flash_update_info.total_image_len = fw_control->size; 4931 fw_control_context->fw_control = fw_control; 4932 fw_control_context->virtAddr = buffer; 4933 fw_control_context->phys_addr = phys_addr; 4934 fw_control_context->len = fw_control->len; 4935 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4936 if (rc) { 4937 kfree(fw_control_context); 4938 return rc; 4939 } 4940 ccb = &pm8001_ha->ccb_info[tag]; 4941 ccb->fw_control_context = fw_control_context; 4942 ccb->ccb_tag = tag; 4943 rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info, 4944 tag); 4945 return rc; 4946 } 4947 4948 ssize_t 4949 pm8001_get_gsm_dump(struct device *cdev, u32 length, char *buf) 4950 { 4951 u32 value, rem, offset = 0, bar = 0; 4952 u32 index, work_offset, dw_length; 4953 u32 shift_value, gsm_base, gsm_dump_offset; 4954 char *direct_data; 4955 struct Scsi_Host *shost = class_to_shost(cdev); 4956 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 4957 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 4958 4959 direct_data = buf; 4960 gsm_dump_offset = pm8001_ha->fatal_forensic_shift_offset; 4961 4962 /* check max is 1 Mbytes */ 4963 if ((length > 0x100000) || (gsm_dump_offset & 3) || 4964 ((gsm_dump_offset + length) > 0x1000000)) 4965 return -EINVAL; 4966 4967 if (pm8001_ha->chip_id == chip_8001) 4968 bar = 2; 4969 else 4970 bar = 1; 4971 4972 work_offset = gsm_dump_offset & 0xFFFF0000; 4973 offset = gsm_dump_offset & 0x0000FFFF; 4974 gsm_dump_offset = work_offset; 4975 /* adjust length to dword boundary */ 4976 rem = length & 3; 4977 dw_length = length >> 2; 4978 4979 for (index = 0; index < dw_length; index++) { 4980 if ((work_offset + offset) & 0xFFFF0000) { 4981 if (pm8001_ha->chip_id == chip_8001) 4982 shift_value = ((gsm_dump_offset + offset) & 4983 SHIFT_REG_64K_MASK); 4984 else 4985 shift_value = (((gsm_dump_offset + offset) & 4986 SHIFT_REG_64K_MASK) >> 4987 SHIFT_REG_BIT_SHIFT); 4988 4989 if (pm8001_ha->chip_id == chip_8001) { 4990 gsm_base = GSM_BASE; 4991 if (-1 == pm8001_bar4_shift(pm8001_ha, 4992 (gsm_base + shift_value))) 4993 return -EIO; 4994 } else { 4995 gsm_base = 0; 4996 if (-1 == pm80xx_bar4_shift(pm8001_ha, 4997 (gsm_base + shift_value))) 4998 return -EIO; 4999 } 5000 gsm_dump_offset = (gsm_dump_offset + offset) & 5001 0xFFFF0000; 5002 work_offset = 0; 5003 offset = offset & 0x0000FFFF; 5004 } 5005 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) & 5006 0x0000FFFF); 5007 direct_data += sprintf(direct_data, "%08x ", value); 5008 offset += 4; 5009 } 5010 if (rem != 0) { 5011 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) & 5012 0x0000FFFF); 5013 /* xfr for non_dw */ 5014 direct_data += sprintf(direct_data, "%08x ", value); 5015 } 5016 /* Shift back to BAR4 original address */ 5017 if (-1 == pm8001_bar4_shift(pm8001_ha, 0)) 5018 return -EIO; 5019 pm8001_ha->fatal_forensic_shift_offset += 1024; 5020 5021 if (pm8001_ha->fatal_forensic_shift_offset >= 0x100000) 5022 pm8001_ha->fatal_forensic_shift_offset = 0; 5023 return direct_data - buf; 5024 } 5025 5026 int 5027 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha, 5028 struct pm8001_device *pm8001_dev, u32 state) 5029 { 5030 struct set_dev_state_req payload; 5031 struct inbound_queue_table *circularQ; 5032 struct pm8001_ccb_info *ccb; 5033 int rc; 5034 u32 tag; 5035 u32 opc = OPC_INB_SET_DEVICE_STATE; 5036 memset(&payload, 0, sizeof(payload)); 5037 rc = pm8001_tag_alloc(pm8001_ha, &tag); 5038 if (rc) 5039 return -1; 5040 ccb = &pm8001_ha->ccb_info[tag]; 5041 ccb->ccb_tag = tag; 5042 ccb->device = pm8001_dev; 5043 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 5044 payload.tag = cpu_to_le32(tag); 5045 payload.device_id = cpu_to_le32(pm8001_dev->device_id); 5046 payload.nds = cpu_to_le32(state); 5047 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 5048 return rc; 5049 5050 } 5051 5052 static int 5053 pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha) 5054 { 5055 struct sas_re_initialization_req payload; 5056 struct inbound_queue_table *circularQ; 5057 struct pm8001_ccb_info *ccb; 5058 int rc; 5059 u32 tag; 5060 u32 opc = OPC_INB_SAS_RE_INITIALIZE; 5061 memset(&payload, 0, sizeof(payload)); 5062 rc = pm8001_tag_alloc(pm8001_ha, &tag); 5063 if (rc) 5064 return -1; 5065 ccb = &pm8001_ha->ccb_info[tag]; 5066 ccb->ccb_tag = tag; 5067 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 5068 payload.tag = cpu_to_le32(tag); 5069 payload.SSAHOLT = cpu_to_le32(0xd << 25); 5070 payload.sata_hol_tmo = cpu_to_le32(80); 5071 payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff); 5072 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 5073 return rc; 5074 5075 } 5076 5077 const struct pm8001_dispatch pm8001_8001_dispatch = { 5078 .name = "pmc8001", 5079 .chip_init = pm8001_chip_init, 5080 .chip_soft_rst = pm8001_chip_soft_rst, 5081 .chip_rst = pm8001_hw_chip_rst, 5082 .chip_iounmap = pm8001_chip_iounmap, 5083 .isr = pm8001_chip_isr, 5084 .is_our_interupt = pm8001_chip_is_our_interupt, 5085 .isr_process_oq = process_oq, 5086 .interrupt_enable = pm8001_chip_interrupt_enable, 5087 .interrupt_disable = pm8001_chip_interrupt_disable, 5088 .make_prd = pm8001_chip_make_sg, 5089 .smp_req = pm8001_chip_smp_req, 5090 .ssp_io_req = pm8001_chip_ssp_io_req, 5091 .sata_req = pm8001_chip_sata_req, 5092 .phy_start_req = pm8001_chip_phy_start_req, 5093 .phy_stop_req = pm8001_chip_phy_stop_req, 5094 .reg_dev_req = pm8001_chip_reg_dev_req, 5095 .dereg_dev_req = pm8001_chip_dereg_dev_req, 5096 .phy_ctl_req = pm8001_chip_phy_ctl_req, 5097 .task_abort = pm8001_chip_abort_task, 5098 .ssp_tm_req = pm8001_chip_ssp_tm_req, 5099 .get_nvmd_req = pm8001_chip_get_nvmd_req, 5100 .set_nvmd_req = pm8001_chip_set_nvmd_req, 5101 .fw_flash_update_req = pm8001_chip_fw_flash_update_req, 5102 .set_dev_state_req = pm8001_chip_set_dev_state_req, 5103 .sas_re_init_req = pm8001_chip_sas_re_initialization, 5104 }; 5105