1 /* 2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 USI Co., Ltd. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 #include <linux/slab.h> 41 #include "pm8001_sas.h" 42 #include "pm8001_hwi.h" 43 #include "pm8001_chips.h" 44 #include "pm8001_ctl.h" 45 46 /** 47 * read_main_config_table - read the configure table and save it. 48 * @pm8001_ha: our hba card information 49 */ 50 static void __devinit read_main_config_table(struct pm8001_hba_info *pm8001_ha) 51 { 52 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 53 pm8001_ha->main_cfg_tbl.signature = pm8001_mr32(address, 0x00); 54 pm8001_ha->main_cfg_tbl.interface_rev = pm8001_mr32(address, 0x04); 55 pm8001_ha->main_cfg_tbl.firmware_rev = pm8001_mr32(address, 0x08); 56 pm8001_ha->main_cfg_tbl.max_out_io = pm8001_mr32(address, 0x0C); 57 pm8001_ha->main_cfg_tbl.max_sgl = pm8001_mr32(address, 0x10); 58 pm8001_ha->main_cfg_tbl.ctrl_cap_flag = pm8001_mr32(address, 0x14); 59 pm8001_ha->main_cfg_tbl.gst_offset = pm8001_mr32(address, 0x18); 60 pm8001_ha->main_cfg_tbl.inbound_queue_offset = 61 pm8001_mr32(address, MAIN_IBQ_OFFSET); 62 pm8001_ha->main_cfg_tbl.outbound_queue_offset = 63 pm8001_mr32(address, MAIN_OBQ_OFFSET); 64 pm8001_ha->main_cfg_tbl.hda_mode_flag = 65 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET); 66 67 /* read analog Setting offset from the configuration table */ 68 pm8001_ha->main_cfg_tbl.anolog_setup_table_offset = 69 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET); 70 71 /* read Error Dump Offset and Length */ 72 pm8001_ha->main_cfg_tbl.fatal_err_dump_offset0 = 73 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET); 74 pm8001_ha->main_cfg_tbl.fatal_err_dump_length0 = 75 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH); 76 pm8001_ha->main_cfg_tbl.fatal_err_dump_offset1 = 77 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET); 78 pm8001_ha->main_cfg_tbl.fatal_err_dump_length1 = 79 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH); 80 } 81 82 /** 83 * read_general_status_table - read the general status table and save it. 84 * @pm8001_ha: our hba card information 85 */ 86 static void __devinit 87 read_general_status_table(struct pm8001_hba_info *pm8001_ha) 88 { 89 void __iomem *address = pm8001_ha->general_stat_tbl_addr; 90 pm8001_ha->gs_tbl.gst_len_mpistate = pm8001_mr32(address, 0x00); 91 pm8001_ha->gs_tbl.iq_freeze_state0 = pm8001_mr32(address, 0x04); 92 pm8001_ha->gs_tbl.iq_freeze_state1 = pm8001_mr32(address, 0x08); 93 pm8001_ha->gs_tbl.msgu_tcnt = pm8001_mr32(address, 0x0C); 94 pm8001_ha->gs_tbl.iop_tcnt = pm8001_mr32(address, 0x10); 95 pm8001_ha->gs_tbl.reserved = pm8001_mr32(address, 0x14); 96 pm8001_ha->gs_tbl.phy_state[0] = pm8001_mr32(address, 0x18); 97 pm8001_ha->gs_tbl.phy_state[1] = pm8001_mr32(address, 0x1C); 98 pm8001_ha->gs_tbl.phy_state[2] = pm8001_mr32(address, 0x20); 99 pm8001_ha->gs_tbl.phy_state[3] = pm8001_mr32(address, 0x24); 100 pm8001_ha->gs_tbl.phy_state[4] = pm8001_mr32(address, 0x28); 101 pm8001_ha->gs_tbl.phy_state[5] = pm8001_mr32(address, 0x2C); 102 pm8001_ha->gs_tbl.phy_state[6] = pm8001_mr32(address, 0x30); 103 pm8001_ha->gs_tbl.phy_state[7] = pm8001_mr32(address, 0x34); 104 pm8001_ha->gs_tbl.reserved1 = pm8001_mr32(address, 0x38); 105 pm8001_ha->gs_tbl.reserved2 = pm8001_mr32(address, 0x3C); 106 pm8001_ha->gs_tbl.reserved3 = pm8001_mr32(address, 0x40); 107 pm8001_ha->gs_tbl.recover_err_info[0] = pm8001_mr32(address, 0x44); 108 pm8001_ha->gs_tbl.recover_err_info[1] = pm8001_mr32(address, 0x48); 109 pm8001_ha->gs_tbl.recover_err_info[2] = pm8001_mr32(address, 0x4C); 110 pm8001_ha->gs_tbl.recover_err_info[3] = pm8001_mr32(address, 0x50); 111 pm8001_ha->gs_tbl.recover_err_info[4] = pm8001_mr32(address, 0x54); 112 pm8001_ha->gs_tbl.recover_err_info[5] = pm8001_mr32(address, 0x58); 113 pm8001_ha->gs_tbl.recover_err_info[6] = pm8001_mr32(address, 0x5C); 114 pm8001_ha->gs_tbl.recover_err_info[7] = pm8001_mr32(address, 0x60); 115 } 116 117 /** 118 * read_inbnd_queue_table - read the inbound queue table and save it. 119 * @pm8001_ha: our hba card information 120 */ 121 static void __devinit 122 read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 123 { 124 int inbQ_num = 1; 125 int i; 126 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 127 for (i = 0; i < inbQ_num; i++) { 128 u32 offset = i * 0x20; 129 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 130 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14))); 131 pm8001_ha->inbnd_q_tbl[i].pi_offset = 132 pm8001_mr32(address, (offset + 0x18)); 133 } 134 } 135 136 /** 137 * read_outbnd_queue_table - read the outbound queue table and save it. 138 * @pm8001_ha: our hba card information 139 */ 140 static void __devinit 141 read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 142 { 143 int outbQ_num = 1; 144 int i; 145 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 146 for (i = 0; i < outbQ_num; i++) { 147 u32 offset = i * 0x24; 148 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 149 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14))); 150 pm8001_ha->outbnd_q_tbl[i].ci_offset = 151 pm8001_mr32(address, (offset + 0x18)); 152 } 153 } 154 155 /** 156 * init_default_table_values - init the default table. 157 * @pm8001_ha: our hba card information 158 */ 159 static void __devinit 160 init_default_table_values(struct pm8001_hba_info *pm8001_ha) 161 { 162 int qn = 1; 163 int i; 164 u32 offsetib, offsetob; 165 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr; 166 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr; 167 168 pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd = 0; 169 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3 = 0; 170 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7 = 0; 171 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3 = 0; 172 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7 = 0; 173 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3 = 0; 174 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7 = 0; 175 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3 = 0; 176 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7 = 0; 177 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3 = 0; 178 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7 = 0; 179 180 pm8001_ha->main_cfg_tbl.upper_event_log_addr = 181 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi; 182 pm8001_ha->main_cfg_tbl.lower_event_log_addr = 183 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo; 184 pm8001_ha->main_cfg_tbl.event_log_size = PM8001_EVENT_LOG_SIZE; 185 pm8001_ha->main_cfg_tbl.event_log_option = 0x01; 186 pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr = 187 pm8001_ha->memoryMap.region[IOP].phys_addr_hi; 188 pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr = 189 pm8001_ha->memoryMap.region[IOP].phys_addr_lo; 190 pm8001_ha->main_cfg_tbl.iop_event_log_size = PM8001_EVENT_LOG_SIZE; 191 pm8001_ha->main_cfg_tbl.iop_event_log_option = 0x01; 192 pm8001_ha->main_cfg_tbl.fatal_err_interrupt = 0x01; 193 for (i = 0; i < qn; i++) { 194 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt = 195 0x00000100 | (0x00000040 << 16) | (0x00<<30); 196 pm8001_ha->inbnd_q_tbl[i].upper_base_addr = 197 pm8001_ha->memoryMap.region[IB].phys_addr_hi; 198 pm8001_ha->inbnd_q_tbl[i].lower_base_addr = 199 pm8001_ha->memoryMap.region[IB].phys_addr_lo; 200 pm8001_ha->inbnd_q_tbl[i].base_virt = 201 (u8 *)pm8001_ha->memoryMap.region[IB].virt_ptr; 202 pm8001_ha->inbnd_q_tbl[i].total_length = 203 pm8001_ha->memoryMap.region[IB].total_len; 204 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr = 205 pm8001_ha->memoryMap.region[CI].phys_addr_hi; 206 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr = 207 pm8001_ha->memoryMap.region[CI].phys_addr_lo; 208 pm8001_ha->inbnd_q_tbl[i].ci_virt = 209 pm8001_ha->memoryMap.region[CI].virt_ptr; 210 offsetib = i * 0x20; 211 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 212 get_pci_bar_index(pm8001_mr32(addressib, 213 (offsetib + 0x14))); 214 pm8001_ha->inbnd_q_tbl[i].pi_offset = 215 pm8001_mr32(addressib, (offsetib + 0x18)); 216 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0; 217 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0; 218 } 219 for (i = 0; i < qn; i++) { 220 pm8001_ha->outbnd_q_tbl[i].element_size_cnt = 221 256 | (64 << 16) | (1<<30); 222 pm8001_ha->outbnd_q_tbl[i].upper_base_addr = 223 pm8001_ha->memoryMap.region[OB].phys_addr_hi; 224 pm8001_ha->outbnd_q_tbl[i].lower_base_addr = 225 pm8001_ha->memoryMap.region[OB].phys_addr_lo; 226 pm8001_ha->outbnd_q_tbl[i].base_virt = 227 (u8 *)pm8001_ha->memoryMap.region[OB].virt_ptr; 228 pm8001_ha->outbnd_q_tbl[i].total_length = 229 pm8001_ha->memoryMap.region[OB].total_len; 230 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr = 231 pm8001_ha->memoryMap.region[PI].phys_addr_hi; 232 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr = 233 pm8001_ha->memoryMap.region[PI].phys_addr_lo; 234 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = 235 0 | (10 << 16) | (0 << 24); 236 pm8001_ha->outbnd_q_tbl[i].pi_virt = 237 pm8001_ha->memoryMap.region[PI].virt_ptr; 238 offsetob = i * 0x24; 239 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 240 get_pci_bar_index(pm8001_mr32(addressob, 241 offsetob + 0x14)); 242 pm8001_ha->outbnd_q_tbl[i].ci_offset = 243 pm8001_mr32(addressob, (offsetob + 0x18)); 244 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0; 245 pm8001_ha->outbnd_q_tbl[i].producer_index = 0; 246 } 247 } 248 249 /** 250 * update_main_config_table - update the main default table to the HBA. 251 * @pm8001_ha: our hba card information 252 */ 253 static void __devinit 254 update_main_config_table(struct pm8001_hba_info *pm8001_ha) 255 { 256 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 257 pm8001_mw32(address, 0x24, 258 pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd); 259 pm8001_mw32(address, 0x28, 260 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3); 261 pm8001_mw32(address, 0x2C, 262 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7); 263 pm8001_mw32(address, 0x30, 264 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3); 265 pm8001_mw32(address, 0x34, 266 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7); 267 pm8001_mw32(address, 0x38, 268 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3); 269 pm8001_mw32(address, 0x3C, 270 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7); 271 pm8001_mw32(address, 0x40, 272 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3); 273 pm8001_mw32(address, 0x44, 274 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7); 275 pm8001_mw32(address, 0x48, 276 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3); 277 pm8001_mw32(address, 0x4C, 278 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7); 279 pm8001_mw32(address, 0x50, 280 pm8001_ha->main_cfg_tbl.upper_event_log_addr); 281 pm8001_mw32(address, 0x54, 282 pm8001_ha->main_cfg_tbl.lower_event_log_addr); 283 pm8001_mw32(address, 0x58, pm8001_ha->main_cfg_tbl.event_log_size); 284 pm8001_mw32(address, 0x5C, pm8001_ha->main_cfg_tbl.event_log_option); 285 pm8001_mw32(address, 0x60, 286 pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr); 287 pm8001_mw32(address, 0x64, 288 pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr); 289 pm8001_mw32(address, 0x68, pm8001_ha->main_cfg_tbl.iop_event_log_size); 290 pm8001_mw32(address, 0x6C, 291 pm8001_ha->main_cfg_tbl.iop_event_log_option); 292 pm8001_mw32(address, 0x70, 293 pm8001_ha->main_cfg_tbl.fatal_err_interrupt); 294 } 295 296 /** 297 * update_inbnd_queue_table - update the inbound queue table to the HBA. 298 * @pm8001_ha: our hba card information 299 */ 300 static void __devinit 301 update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, int number) 302 { 303 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 304 u16 offset = number * 0x20; 305 pm8001_mw32(address, offset + 0x00, 306 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); 307 pm8001_mw32(address, offset + 0x04, 308 pm8001_ha->inbnd_q_tbl[number].upper_base_addr); 309 pm8001_mw32(address, offset + 0x08, 310 pm8001_ha->inbnd_q_tbl[number].lower_base_addr); 311 pm8001_mw32(address, offset + 0x0C, 312 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr); 313 pm8001_mw32(address, offset + 0x10, 314 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); 315 } 316 317 /** 318 * update_outbnd_queue_table - update the outbound queue table to the HBA. 319 * @pm8001_ha: our hba card information 320 */ 321 static void __devinit 322 update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, int number) 323 { 324 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 325 u16 offset = number * 0x24; 326 pm8001_mw32(address, offset + 0x00, 327 pm8001_ha->outbnd_q_tbl[number].element_size_cnt); 328 pm8001_mw32(address, offset + 0x04, 329 pm8001_ha->outbnd_q_tbl[number].upper_base_addr); 330 pm8001_mw32(address, offset + 0x08, 331 pm8001_ha->outbnd_q_tbl[number].lower_base_addr); 332 pm8001_mw32(address, offset + 0x0C, 333 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr); 334 pm8001_mw32(address, offset + 0x10, 335 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); 336 pm8001_mw32(address, offset + 0x1C, 337 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay); 338 } 339 340 /** 341 * bar4_shift - function is called to shift BAR base address 342 * @pm8001_ha : our hba card infomation 343 * @shiftValue : shifting value in memory bar. 344 */ 345 static int bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue) 346 { 347 u32 regVal; 348 u32 max_wait_count; 349 350 /* program the inbound AXI translation Lower Address */ 351 pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue); 352 353 /* confirm the setting is written */ 354 max_wait_count = 1 * 1000 * 1000; /* 1 sec */ 355 do { 356 udelay(1); 357 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW); 358 } while ((regVal != shiftValue) && (--max_wait_count)); 359 360 if (!max_wait_count) { 361 PM8001_INIT_DBG(pm8001_ha, 362 pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW" 363 " = 0x%x\n", regVal)); 364 return -1; 365 } 366 return 0; 367 } 368 369 /** 370 * mpi_set_phys_g3_with_ssc 371 * @pm8001_ha: our hba card information 372 * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc. 373 */ 374 static void __devinit 375 mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha, u32 SSCbit) 376 { 377 u32 value, offset, i; 378 379 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000 380 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000 381 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074 382 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074 383 #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12 384 #define PHY_G3_WITH_SSC_BIT_SHIFT 13 385 #define SNW3_PHY_CAPABILITIES_PARITY 31 386 387 /* 388 * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3) 389 * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7) 390 */ 391 if (-1 == bar4_shift(pm8001_ha, SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) 392 return; 393 394 for (i = 0; i < 4; i++) { 395 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i; 396 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501); 397 } 398 /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */ 399 if (-1 == bar4_shift(pm8001_ha, SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) 400 return; 401 for (i = 4; i < 8; i++) { 402 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4); 403 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501); 404 } 405 /************************************************************* 406 Change the SSC upspreading value to 0x0 so that upspreading is disabled. 407 Device MABC SMOD0 Controls 408 Address: (via MEMBASE-III): 409 Using shifted destination address 0x0_0000: with Offset 0xD8 410 411 31:28 R/W Reserved Do not change 412 27:24 R/W SAS_SMOD_SPRDUP 0000 413 23:20 R/W SAS_SMOD_SPRDDN 0000 414 19:0 R/W Reserved Do not change 415 Upon power-up this register will read as 0x8990c016, 416 and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000 417 so that the written value will be 0x8090c016. 418 This will ensure only down-spreading SSC is enabled on the SPC. 419 *************************************************************/ 420 value = pm8001_cr32(pm8001_ha, 2, 0xd8); 421 pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016); 422 423 /*set the shifted destination address to 0x0 to avoid error operation */ 424 bar4_shift(pm8001_ha, 0x0); 425 return; 426 } 427 428 /** 429 * mpi_set_open_retry_interval_reg 430 * @pm8001_ha: our hba card information 431 * @interval - interval time for each OPEN_REJECT (RETRY). The units are in 1us. 432 */ 433 static void __devinit 434 mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha, 435 u32 interval) 436 { 437 u32 offset; 438 u32 value; 439 u32 i; 440 441 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000 442 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000 443 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4 444 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4 445 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF 446 447 value = interval & OPEN_RETRY_INTERVAL_REG_MASK; 448 /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/ 449 if (-1 == bar4_shift(pm8001_ha, 450 OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) 451 return; 452 for (i = 0; i < 4; i++) { 453 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i; 454 pm8001_cw32(pm8001_ha, 2, offset, value); 455 } 456 457 if (-1 == bar4_shift(pm8001_ha, 458 OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) 459 return; 460 for (i = 4; i < 8; i++) { 461 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4); 462 pm8001_cw32(pm8001_ha, 2, offset, value); 463 } 464 /*set the shifted destination address to 0x0 to avoid error operation */ 465 bar4_shift(pm8001_ha, 0x0); 466 return; 467 } 468 469 /** 470 * mpi_init_check - check firmware initialization status. 471 * @pm8001_ha: our hba card information 472 */ 473 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha) 474 { 475 u32 max_wait_count; 476 u32 value; 477 u32 gst_len_mpistate; 478 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the 479 table is updated */ 480 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE); 481 /* wait until Inbound DoorBell Clear Register toggled */ 482 max_wait_count = 1 * 1000 * 1000;/* 1 sec */ 483 do { 484 udelay(1); 485 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 486 value &= SPC_MSGU_CFG_TABLE_UPDATE; 487 } while ((value != 0) && (--max_wait_count)); 488 489 if (!max_wait_count) 490 return -1; 491 /* check the MPI-State for initialization */ 492 gst_len_mpistate = 493 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 494 GST_GSTLEN_MPIS_OFFSET); 495 if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK)) 496 return -1; 497 /* check MPI Initialization error */ 498 gst_len_mpistate = gst_len_mpistate >> 16; 499 if (0x0000 != gst_len_mpistate) 500 return -1; 501 return 0; 502 } 503 504 /** 505 * check_fw_ready - The LLDD check if the FW is ready, if not, return error. 506 * @pm8001_ha: our hba card information 507 */ 508 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha) 509 { 510 u32 value, value1; 511 u32 max_wait_count; 512 /* check error state */ 513 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 514 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 515 /* check AAP error */ 516 if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) { 517 /* error state */ 518 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 519 return -1; 520 } 521 522 /* check IOP error */ 523 if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) { 524 /* error state */ 525 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 526 return -1; 527 } 528 529 /* bit 4-31 of scratch pad1 should be zeros if it is not 530 in error state*/ 531 if (value & SCRATCH_PAD1_STATE_MASK) { 532 /* error case */ 533 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 534 return -1; 535 } 536 537 /* bit 2, 4-31 of scratch pad2 should be zeros if it is not 538 in error state */ 539 if (value1 & SCRATCH_PAD2_STATE_MASK) { 540 /* error case */ 541 return -1; 542 } 543 544 max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */ 545 546 /* wait until scratch pad 1 and 2 registers in ready state */ 547 do { 548 udelay(1); 549 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) 550 & SCRATCH_PAD1_RDY; 551 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) 552 & SCRATCH_PAD2_RDY; 553 if ((--max_wait_count) == 0) 554 return -1; 555 } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY)); 556 return 0; 557 } 558 559 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha) 560 { 561 void __iomem *base_addr; 562 u32 value; 563 u32 offset; 564 u32 pcibar; 565 u32 pcilogic; 566 567 value = pm8001_cr32(pm8001_ha, 0, 0x44); 568 offset = value & 0x03FFFFFF; 569 PM8001_INIT_DBG(pm8001_ha, 570 pm8001_printk("Scratchpad 0 Offset: %x \n", offset)); 571 pcilogic = (value & 0xFC000000) >> 26; 572 pcibar = get_pci_bar_index(pcilogic); 573 PM8001_INIT_DBG(pm8001_ha, 574 pm8001_printk("Scratchpad 0 PCI BAR: %d \n", pcibar)); 575 pm8001_ha->main_cfg_tbl_addr = base_addr = 576 pm8001_ha->io_mem[pcibar].memvirtaddr + offset; 577 pm8001_ha->general_stat_tbl_addr = 578 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18); 579 pm8001_ha->inbnd_q_tbl_addr = 580 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C); 581 pm8001_ha->outbnd_q_tbl_addr = 582 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20); 583 } 584 585 /** 586 * pm8001_chip_init - the main init function that initialize whole PM8001 chip. 587 * @pm8001_ha: our hba card information 588 */ 589 static int __devinit pm8001_chip_init(struct pm8001_hba_info *pm8001_ha) 590 { 591 /* check the firmware status */ 592 if (-1 == check_fw_ready(pm8001_ha)) { 593 PM8001_FAIL_DBG(pm8001_ha, 594 pm8001_printk("Firmware is not ready!\n")); 595 return -EBUSY; 596 } 597 598 /* Initialize pci space address eg: mpi offset */ 599 init_pci_device_addresses(pm8001_ha); 600 init_default_table_values(pm8001_ha); 601 read_main_config_table(pm8001_ha); 602 read_general_status_table(pm8001_ha); 603 read_inbnd_queue_table(pm8001_ha); 604 read_outbnd_queue_table(pm8001_ha); 605 /* update main config table ,inbound table and outbound table */ 606 update_main_config_table(pm8001_ha); 607 update_inbnd_queue_table(pm8001_ha, 0); 608 update_outbnd_queue_table(pm8001_ha, 0); 609 mpi_set_phys_g3_with_ssc(pm8001_ha, 0); 610 mpi_set_open_retry_interval_reg(pm8001_ha, 7); 611 /* notify firmware update finished and check initialization status */ 612 if (0 == mpi_init_check(pm8001_ha)) { 613 PM8001_INIT_DBG(pm8001_ha, 614 pm8001_printk("MPI initialize successful!\n")); 615 } else 616 return -EBUSY; 617 /*This register is a 16-bit timer with a resolution of 1us. This is the 618 timer used for interrupt delay/coalescing in the PCIe Application Layer. 619 Zero is not a valid value. A value of 1 in the register will cause the 620 interrupts to be normal. A value greater than 1 will cause coalescing 621 delays.*/ 622 pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1); 623 pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0); 624 return 0; 625 } 626 627 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha) 628 { 629 u32 max_wait_count; 630 u32 value; 631 u32 gst_len_mpistate; 632 init_pci_device_addresses(pm8001_ha); 633 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the 634 table is stop */ 635 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET); 636 637 /* wait until Inbound DoorBell Clear Register toggled */ 638 max_wait_count = 1 * 1000 * 1000;/* 1 sec */ 639 do { 640 udelay(1); 641 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 642 value &= SPC_MSGU_CFG_TABLE_RESET; 643 } while ((value != 0) && (--max_wait_count)); 644 645 if (!max_wait_count) { 646 PM8001_FAIL_DBG(pm8001_ha, 647 pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value)); 648 return -1; 649 } 650 651 /* check the MPI-State for termination in progress */ 652 /* wait until Inbound DoorBell Clear Register toggled */ 653 max_wait_count = 1 * 1000 * 1000; /* 1 sec */ 654 do { 655 udelay(1); 656 gst_len_mpistate = 657 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 658 GST_GSTLEN_MPIS_OFFSET); 659 if (GST_MPI_STATE_UNINIT == 660 (gst_len_mpistate & GST_MPI_STATE_MASK)) 661 break; 662 } while (--max_wait_count); 663 if (!max_wait_count) { 664 PM8001_FAIL_DBG(pm8001_ha, 665 pm8001_printk(" TIME OUT MPI State = 0x%x\n", 666 gst_len_mpistate & GST_MPI_STATE_MASK)); 667 return -1; 668 } 669 return 0; 670 } 671 672 /** 673 * soft_reset_ready_check - Function to check FW is ready for soft reset. 674 * @pm8001_ha: our hba card information 675 */ 676 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha) 677 { 678 u32 regVal, regVal1, regVal2; 679 if (mpi_uninit_check(pm8001_ha) != 0) { 680 PM8001_FAIL_DBG(pm8001_ha, 681 pm8001_printk("MPI state is not ready\n")); 682 return -1; 683 } 684 /* read the scratch pad 2 register bit 2 */ 685 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) 686 & SCRATCH_PAD2_FWRDY_RST; 687 if (regVal == SCRATCH_PAD2_FWRDY_RST) { 688 PM8001_INIT_DBG(pm8001_ha, 689 pm8001_printk("Firmware is ready for reset .\n")); 690 } else { 691 /* Trigger NMI twice via RB6 */ 692 if (-1 == bar4_shift(pm8001_ha, RB6_ACCESS_REG)) { 693 PM8001_FAIL_DBG(pm8001_ha, 694 pm8001_printk("Shift Bar4 to 0x%x failed\n", 695 RB6_ACCESS_REG)); 696 return -1; 697 } 698 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, 699 RB6_MAGIC_NUMBER_RST); 700 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST); 701 /* wait for 100 ms */ 702 mdelay(100); 703 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) & 704 SCRATCH_PAD2_FWRDY_RST; 705 if (regVal != SCRATCH_PAD2_FWRDY_RST) { 706 regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 707 regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 708 PM8001_FAIL_DBG(pm8001_ha, 709 pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1" 710 "=0x%x, MSGU_SCRATCH_PAD2=0x%x\n", 711 regVal1, regVal2)); 712 PM8001_FAIL_DBG(pm8001_ha, 713 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n", 714 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0))); 715 PM8001_FAIL_DBG(pm8001_ha, 716 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n", 717 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3))); 718 return -1; 719 } 720 } 721 return 0; 722 } 723 724 /** 725 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all 726 * the FW register status to the originated status. 727 * @pm8001_ha: our hba card information 728 * @signature: signature in host scratch pad0 register. 729 */ 730 static int 731 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha, u32 signature) 732 { 733 u32 regVal, toggleVal; 734 u32 max_wait_count; 735 u32 regVal1, regVal2, regVal3; 736 737 /* step1: Check FW is ready for soft reset */ 738 if (soft_reset_ready_check(pm8001_ha) != 0) { 739 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("FW is not ready\n")); 740 return -1; 741 } 742 743 /* step 2: clear NMI status register on AAP1 and IOP, write the same 744 value to clear */ 745 /* map 0x60000 to BAR4(0x20), BAR2(win) */ 746 if (-1 == bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) { 747 PM8001_FAIL_DBG(pm8001_ha, 748 pm8001_printk("Shift Bar4 to 0x%x failed\n", 749 MBIC_AAP1_ADDR_BASE)); 750 return -1; 751 } 752 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP); 753 PM8001_INIT_DBG(pm8001_ha, 754 pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal)); 755 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0); 756 /* map 0x70000 to BAR4(0x20), BAR2(win) */ 757 if (-1 == bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) { 758 PM8001_FAIL_DBG(pm8001_ha, 759 pm8001_printk("Shift Bar4 to 0x%x failed\n", 760 MBIC_IOP_ADDR_BASE)); 761 return -1; 762 } 763 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1); 764 PM8001_INIT_DBG(pm8001_ha, 765 pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal)); 766 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0); 767 768 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE); 769 PM8001_INIT_DBG(pm8001_ha, 770 pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal)); 771 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0); 772 773 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT); 774 PM8001_INIT_DBG(pm8001_ha, 775 pm8001_printk("PCIE - Event Interrupt = 0x%x\n", regVal)); 776 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal); 777 778 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE); 779 PM8001_INIT_DBG(pm8001_ha, 780 pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal)); 781 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0); 782 783 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT); 784 PM8001_INIT_DBG(pm8001_ha, 785 pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal)); 786 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal); 787 788 /* read the scratch pad 1 register bit 2 */ 789 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) 790 & SCRATCH_PAD1_RST; 791 toggleVal = regVal ^ SCRATCH_PAD1_RST; 792 793 /* set signature in host scratch pad0 register to tell SPC that the 794 host performs the soft reset */ 795 pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature); 796 797 /* read required registers for confirmming */ 798 /* map 0x0700000 to BAR4(0x20), BAR2(win) */ 799 if (-1 == bar4_shift(pm8001_ha, GSM_ADDR_BASE)) { 800 PM8001_FAIL_DBG(pm8001_ha, 801 pm8001_printk("Shift Bar4 to 0x%x failed\n", 802 GSM_ADDR_BASE)); 803 return -1; 804 } 805 PM8001_INIT_DBG(pm8001_ha, 806 pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and" 807 " Reset = 0x%x\n", 808 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); 809 810 /* step 3: host read GSM Configuration and Reset register */ 811 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); 812 /* Put those bits to low */ 813 /* GSM XCBI offset = 0x70 0000 814 0x00 Bit 13 COM_SLV_SW_RSTB 1 815 0x00 Bit 12 QSSP_SW_RSTB 1 816 0x00 Bit 11 RAAE_SW_RSTB 1 817 0x00 Bit 9 RB_1_SW_RSTB 1 818 0x00 Bit 8 SM_SW_RSTB 1 819 */ 820 regVal &= ~(0x00003b00); 821 /* host write GSM Configuration and Reset register */ 822 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); 823 PM8001_INIT_DBG(pm8001_ha, 824 pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM " 825 "Configuration and Reset is set to = 0x%x\n", 826 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); 827 828 /* step 4: */ 829 /* disable GSM - Read Address Parity Check */ 830 regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK); 831 PM8001_INIT_DBG(pm8001_ha, 832 pm8001_printk("GSM 0x700038 - Read Address Parity Check " 833 "Enable = 0x%x\n", regVal1)); 834 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0); 835 PM8001_INIT_DBG(pm8001_ha, 836 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable" 837 "is set to = 0x%x\n", 838 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK))); 839 840 /* disable GSM - Write Address Parity Check */ 841 regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK); 842 PM8001_INIT_DBG(pm8001_ha, 843 pm8001_printk("GSM 0x700040 - Write Address Parity Check" 844 " Enable = 0x%x\n", regVal2)); 845 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0); 846 PM8001_INIT_DBG(pm8001_ha, 847 pm8001_printk("GSM 0x700040 - Write Address Parity Check " 848 "Enable is set to = 0x%x\n", 849 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK))); 850 851 /* disable GSM - Write Data Parity Check */ 852 regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK); 853 PM8001_INIT_DBG(pm8001_ha, 854 pm8001_printk("GSM 0x300048 - Write Data Parity Check" 855 " Enable = 0x%x\n", regVal3)); 856 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0); 857 PM8001_INIT_DBG(pm8001_ha, 858 pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable" 859 "is set to = 0x%x\n", 860 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK))); 861 862 /* step 5: delay 10 usec */ 863 udelay(10); 864 /* step 5-b: set GPIO-0 output control to tristate anyway */ 865 if (-1 == bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) { 866 PM8001_INIT_DBG(pm8001_ha, 867 pm8001_printk("Shift Bar4 to 0x%x failed\n", 868 GPIO_ADDR_BASE)); 869 return -1; 870 } 871 regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET); 872 PM8001_INIT_DBG(pm8001_ha, 873 pm8001_printk("GPIO Output Control Register:" 874 " = 0x%x\n", regVal)); 875 /* set GPIO-0 output control to tri-state */ 876 regVal &= 0xFFFFFFFC; 877 pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal); 878 879 /* Step 6: Reset the IOP and AAP1 */ 880 /* map 0x00000 to BAR4(0x20), BAR2(win) */ 881 if (-1 == bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) { 882 PM8001_FAIL_DBG(pm8001_ha, 883 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n", 884 SPC_TOP_LEVEL_ADDR_BASE)); 885 return -1; 886 } 887 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 888 PM8001_INIT_DBG(pm8001_ha, 889 pm8001_printk("Top Register before resetting IOP/AAP1" 890 ":= 0x%x\n", regVal)); 891 regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS); 892 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 893 894 /* step 7: Reset the BDMA/OSSP */ 895 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 896 PM8001_INIT_DBG(pm8001_ha, 897 pm8001_printk("Top Register before resetting BDMA/OSSP" 898 ": = 0x%x\n", regVal)); 899 regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP); 900 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 901 902 /* step 8: delay 10 usec */ 903 udelay(10); 904 905 /* step 9: bring the BDMA and OSSP out of reset */ 906 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 907 PM8001_INIT_DBG(pm8001_ha, 908 pm8001_printk("Top Register before bringing up BDMA/OSSP" 909 ":= 0x%x\n", regVal)); 910 regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP); 911 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 912 913 /* step 10: delay 10 usec */ 914 udelay(10); 915 916 /* step 11: reads and sets the GSM Configuration and Reset Register */ 917 /* map 0x0700000 to BAR4(0x20), BAR2(win) */ 918 if (-1 == bar4_shift(pm8001_ha, GSM_ADDR_BASE)) { 919 PM8001_FAIL_DBG(pm8001_ha, 920 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n", 921 GSM_ADDR_BASE)); 922 return -1; 923 } 924 PM8001_INIT_DBG(pm8001_ha, 925 pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and " 926 "Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); 927 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); 928 /* Put those bits to high */ 929 /* GSM XCBI offset = 0x70 0000 930 0x00 Bit 13 COM_SLV_SW_RSTB 1 931 0x00 Bit 12 QSSP_SW_RSTB 1 932 0x00 Bit 11 RAAE_SW_RSTB 1 933 0x00 Bit 9 RB_1_SW_RSTB 1 934 0x00 Bit 8 SM_SW_RSTB 1 935 */ 936 regVal |= (GSM_CONFIG_RESET_VALUE); 937 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); 938 PM8001_INIT_DBG(pm8001_ha, 939 pm8001_printk("GSM (0x00004088 ==> 0x00007b88) - GSM" 940 " Configuration and Reset is set to = 0x%x\n", 941 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); 942 943 /* step 12: Restore GSM - Read Address Parity Check */ 944 regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK); 945 /* just for debugging */ 946 PM8001_INIT_DBG(pm8001_ha, 947 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable" 948 " = 0x%x\n", regVal)); 949 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1); 950 PM8001_INIT_DBG(pm8001_ha, 951 pm8001_printk("GSM 0x700038 - Read Address Parity" 952 " Check Enable is set to = 0x%x\n", 953 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK))); 954 /* Restore GSM - Write Address Parity Check */ 955 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK); 956 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2); 957 PM8001_INIT_DBG(pm8001_ha, 958 pm8001_printk("GSM 0x700040 - Write Address Parity Check" 959 " Enable is set to = 0x%x\n", 960 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK))); 961 /* Restore GSM - Write Data Parity Check */ 962 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK); 963 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3); 964 PM8001_INIT_DBG(pm8001_ha, 965 pm8001_printk("GSM 0x700048 - Write Data Parity Check Enable" 966 "is set to = 0x%x\n", 967 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK))); 968 969 /* step 13: bring the IOP and AAP1 out of reset */ 970 /* map 0x00000 to BAR4(0x20), BAR2(win) */ 971 if (-1 == bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) { 972 PM8001_FAIL_DBG(pm8001_ha, 973 pm8001_printk("Shift Bar4 to 0x%x failed\n", 974 SPC_TOP_LEVEL_ADDR_BASE)); 975 return -1; 976 } 977 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 978 regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS); 979 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 980 981 /* step 14: delay 10 usec - Normal Mode */ 982 udelay(10); 983 /* check Soft Reset Normal mode or Soft Reset HDA mode */ 984 if (signature == SPC_SOFT_RESET_SIGNATURE) { 985 /* step 15 (Normal Mode): wait until scratch pad1 register 986 bit 2 toggled */ 987 max_wait_count = 2 * 1000 * 1000;/* 2 sec */ 988 do { 989 udelay(1); 990 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) & 991 SCRATCH_PAD1_RST; 992 } while ((regVal != toggleVal) && (--max_wait_count)); 993 994 if (!max_wait_count) { 995 regVal = pm8001_cr32(pm8001_ha, 0, 996 MSGU_SCRATCH_PAD_1); 997 PM8001_FAIL_DBG(pm8001_ha, 998 pm8001_printk("TIMEOUT : ToggleVal 0x%x," 999 "MSGU_SCRATCH_PAD1 = 0x%x\n", 1000 toggleVal, regVal)); 1001 PM8001_FAIL_DBG(pm8001_ha, 1002 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n", 1003 pm8001_cr32(pm8001_ha, 0, 1004 MSGU_SCRATCH_PAD_0))); 1005 PM8001_FAIL_DBG(pm8001_ha, 1006 pm8001_printk("SCRATCH_PAD2 value = 0x%x\n", 1007 pm8001_cr32(pm8001_ha, 0, 1008 MSGU_SCRATCH_PAD_2))); 1009 PM8001_FAIL_DBG(pm8001_ha, 1010 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n", 1011 pm8001_cr32(pm8001_ha, 0, 1012 MSGU_SCRATCH_PAD_3))); 1013 return -1; 1014 } 1015 1016 /* step 16 (Normal) - Clear ODMR and ODCR */ 1017 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); 1018 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); 1019 1020 /* step 17 (Normal Mode): wait for the FW and IOP to get 1021 ready - 1 sec timeout */ 1022 /* Wait for the SPC Configuration Table to be ready */ 1023 if (check_fw_ready(pm8001_ha) == -1) { 1024 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1025 /* return error if MPI Configuration Table not ready */ 1026 PM8001_INIT_DBG(pm8001_ha, 1027 pm8001_printk("FW not ready SCRATCH_PAD1" 1028 " = 0x%x\n", regVal)); 1029 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 1030 /* return error if MPI Configuration Table not ready */ 1031 PM8001_INIT_DBG(pm8001_ha, 1032 pm8001_printk("FW not ready SCRATCH_PAD2" 1033 " = 0x%x\n", regVal)); 1034 PM8001_INIT_DBG(pm8001_ha, 1035 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n", 1036 pm8001_cr32(pm8001_ha, 0, 1037 MSGU_SCRATCH_PAD_0))); 1038 PM8001_INIT_DBG(pm8001_ha, 1039 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n", 1040 pm8001_cr32(pm8001_ha, 0, 1041 MSGU_SCRATCH_PAD_3))); 1042 return -1; 1043 } 1044 } 1045 1046 PM8001_INIT_DBG(pm8001_ha, 1047 pm8001_printk("SPC soft reset Complete\n")); 1048 return 0; 1049 } 1050 1051 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha) 1052 { 1053 u32 i; 1054 u32 regVal; 1055 PM8001_INIT_DBG(pm8001_ha, 1056 pm8001_printk("chip reset start\n")); 1057 1058 /* do SPC chip reset. */ 1059 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); 1060 regVal &= ~(SPC_REG_RESET_DEVICE); 1061 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); 1062 1063 /* delay 10 usec */ 1064 udelay(10); 1065 1066 /* bring chip reset out of reset */ 1067 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); 1068 regVal |= SPC_REG_RESET_DEVICE; 1069 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); 1070 1071 /* delay 10 usec */ 1072 udelay(10); 1073 1074 /* wait for 20 msec until the firmware gets reloaded */ 1075 i = 20; 1076 do { 1077 mdelay(1); 1078 } while ((--i) != 0); 1079 1080 PM8001_INIT_DBG(pm8001_ha, 1081 pm8001_printk("chip reset finished\n")); 1082 } 1083 1084 /** 1085 * pm8001_chip_iounmap - which maped when initialized. 1086 * @pm8001_ha: our hba card information 1087 */ 1088 static void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha) 1089 { 1090 s8 bar, logical = 0; 1091 for (bar = 0; bar < 6; bar++) { 1092 /* 1093 ** logical BARs for SPC: 1094 ** bar 0 and 1 - logical BAR0 1095 ** bar 2 and 3 - logical BAR1 1096 ** bar4 - logical BAR2 1097 ** bar5 - logical BAR3 1098 ** Skip the appropriate assignments: 1099 */ 1100 if ((bar == 1) || (bar == 3)) 1101 continue; 1102 if (pm8001_ha->io_mem[logical].memvirtaddr) { 1103 iounmap(pm8001_ha->io_mem[logical].memvirtaddr); 1104 logical++; 1105 } 1106 } 1107 } 1108 1109 /** 1110 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt 1111 * @pm8001_ha: our hba card information 1112 */ 1113 static void 1114 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha) 1115 { 1116 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); 1117 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); 1118 } 1119 1120 /** 1121 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt 1122 * @pm8001_ha: our hba card information 1123 */ 1124 static void 1125 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha) 1126 { 1127 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL); 1128 } 1129 1130 /** 1131 * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt 1132 * @pm8001_ha: our hba card information 1133 */ 1134 static void 1135 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha, 1136 u32 int_vec_idx) 1137 { 1138 u32 msi_index; 1139 u32 value; 1140 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE; 1141 msi_index += MSIX_TABLE_BASE; 1142 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE); 1143 value = (1 << int_vec_idx); 1144 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, value); 1145 1146 } 1147 1148 /** 1149 * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt 1150 * @pm8001_ha: our hba card information 1151 */ 1152 static void 1153 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha, 1154 u32 int_vec_idx) 1155 { 1156 u32 msi_index; 1157 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE; 1158 msi_index += MSIX_TABLE_BASE; 1159 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE); 1160 1161 } 1162 /** 1163 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt 1164 * @pm8001_ha: our hba card information 1165 */ 1166 static void 1167 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha) 1168 { 1169 #ifdef PM8001_USE_MSIX 1170 pm8001_chip_msix_interrupt_enable(pm8001_ha, 0); 1171 return; 1172 #endif 1173 pm8001_chip_intx_interrupt_enable(pm8001_ha); 1174 1175 } 1176 1177 /** 1178 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt 1179 * @pm8001_ha: our hba card information 1180 */ 1181 static void 1182 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha) 1183 { 1184 #ifdef PM8001_USE_MSIX 1185 pm8001_chip_msix_interrupt_disable(pm8001_ha, 0); 1186 return; 1187 #endif 1188 pm8001_chip_intx_interrupt_disable(pm8001_ha); 1189 1190 } 1191 1192 /** 1193 * mpi_msg_free_get- get the free message buffer for transfer inbound queue. 1194 * @circularQ: the inbound queue we want to transfer to HBA. 1195 * @messageSize: the message size of this transfer, normally it is 64 bytes 1196 * @messagePtr: the pointer to message. 1197 */ 1198 static int mpi_msg_free_get(struct inbound_queue_table *circularQ, 1199 u16 messageSize, void **messagePtr) 1200 { 1201 u32 offset, consumer_index; 1202 struct mpi_msg_hdr *msgHeader; 1203 u8 bcCount = 1; /* only support single buffer */ 1204 1205 /* Checks is the requested message size can be allocated in this queue*/ 1206 if (messageSize > 64) { 1207 *messagePtr = NULL; 1208 return -1; 1209 } 1210 1211 /* Stores the new consumer index */ 1212 consumer_index = pm8001_read_32(circularQ->ci_virt); 1213 circularQ->consumer_index = cpu_to_le32(consumer_index); 1214 if (((circularQ->producer_idx + bcCount) % 256) == 1215 circularQ->consumer_index) { 1216 *messagePtr = NULL; 1217 return -1; 1218 } 1219 /* get memory IOMB buffer address */ 1220 offset = circularQ->producer_idx * 64; 1221 /* increment to next bcCount element */ 1222 circularQ->producer_idx = (circularQ->producer_idx + bcCount) % 256; 1223 /* Adds that distance to the base of the region virtual address plus 1224 the message header size*/ 1225 msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset); 1226 *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr); 1227 return 0; 1228 } 1229 1230 /** 1231 * mpi_build_cmd- build the message queue for transfer, update the PI to FW 1232 * to tell the fw to get this message from IOMB. 1233 * @pm8001_ha: our hba card information 1234 * @circularQ: the inbound queue we want to transfer to HBA. 1235 * @opCode: the operation code represents commands which LLDD and fw recognized. 1236 * @payload: the command payload of each operation command. 1237 */ 1238 static int mpi_build_cmd(struct pm8001_hba_info *pm8001_ha, 1239 struct inbound_queue_table *circularQ, 1240 u32 opCode, void *payload) 1241 { 1242 u32 Header = 0, hpriority = 0, bc = 1, category = 0x02; 1243 u32 responseQueue = 0; 1244 void *pMessage; 1245 1246 if (mpi_msg_free_get(circularQ, 64, &pMessage) < 0) { 1247 PM8001_IO_DBG(pm8001_ha, 1248 pm8001_printk("No free mpi buffer \n")); 1249 return -1; 1250 } 1251 BUG_ON(!payload); 1252 /*Copy to the payload*/ 1253 memcpy(pMessage, payload, (64 - sizeof(struct mpi_msg_hdr))); 1254 1255 /*Build the header*/ 1256 Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24) 1257 | ((responseQueue & 0x3F) << 16) 1258 | ((category & 0xF) << 12) | (opCode & 0xFFF)); 1259 1260 pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header)); 1261 /*Update the PI to the firmware*/ 1262 pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar, 1263 circularQ->pi_offset, circularQ->producer_idx); 1264 PM8001_IO_DBG(pm8001_ha, 1265 pm8001_printk("after PI= %d CI= %d \n", circularQ->producer_idx, 1266 circularQ->consumer_index)); 1267 return 0; 1268 } 1269 1270 static u32 mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg, 1271 struct outbound_queue_table *circularQ, u8 bc) 1272 { 1273 u32 producer_index; 1274 struct mpi_msg_hdr *msgHeader; 1275 struct mpi_msg_hdr *pOutBoundMsgHeader; 1276 1277 msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr)); 1278 pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + 1279 circularQ->consumer_idx * 64); 1280 if (pOutBoundMsgHeader != msgHeader) { 1281 PM8001_FAIL_DBG(pm8001_ha, 1282 pm8001_printk("consumer_idx = %d msgHeader = %p\n", 1283 circularQ->consumer_idx, msgHeader)); 1284 1285 /* Update the producer index from SPC */ 1286 producer_index = pm8001_read_32(circularQ->pi_virt); 1287 circularQ->producer_index = cpu_to_le32(producer_index); 1288 PM8001_FAIL_DBG(pm8001_ha, 1289 pm8001_printk("consumer_idx = %d producer_index = %d" 1290 "msgHeader = %p\n", circularQ->consumer_idx, 1291 circularQ->producer_index, msgHeader)); 1292 return 0; 1293 } 1294 /* free the circular queue buffer elements associated with the message*/ 1295 circularQ->consumer_idx = (circularQ->consumer_idx + bc) % 256; 1296 /* update the CI of outbound queue */ 1297 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset, 1298 circularQ->consumer_idx); 1299 /* Update the producer index from SPC*/ 1300 producer_index = pm8001_read_32(circularQ->pi_virt); 1301 circularQ->producer_index = cpu_to_le32(producer_index); 1302 PM8001_IO_DBG(pm8001_ha, 1303 pm8001_printk(" CI=%d PI=%d\n", circularQ->consumer_idx, 1304 circularQ->producer_index)); 1305 return 0; 1306 } 1307 1308 /** 1309 * mpi_msg_consume- get the MPI message from outbound queue message table. 1310 * @pm8001_ha: our hba card information 1311 * @circularQ: the outbound queue table. 1312 * @messagePtr1: the message contents of this outbound message. 1313 * @pBC: the message size. 1314 */ 1315 static u32 mpi_msg_consume(struct pm8001_hba_info *pm8001_ha, 1316 struct outbound_queue_table *circularQ, 1317 void **messagePtr1, u8 *pBC) 1318 { 1319 struct mpi_msg_hdr *msgHeader; 1320 __le32 msgHeader_tmp; 1321 u32 header_tmp; 1322 do { 1323 /* If there are not-yet-delivered messages ... */ 1324 if (circularQ->producer_index != circularQ->consumer_idx) { 1325 /*Get the pointer to the circular queue buffer element*/ 1326 msgHeader = (struct mpi_msg_hdr *) 1327 (circularQ->base_virt + 1328 circularQ->consumer_idx * 64); 1329 /* read header */ 1330 header_tmp = pm8001_read_32(msgHeader); 1331 msgHeader_tmp = cpu_to_le32(header_tmp); 1332 if (0 != (msgHeader_tmp & 0x80000000)) { 1333 if (OPC_OUB_SKIP_ENTRY != 1334 (msgHeader_tmp & 0xfff)) { 1335 *messagePtr1 = 1336 ((u8 *)msgHeader) + 1337 sizeof(struct mpi_msg_hdr); 1338 *pBC = (u8)((msgHeader_tmp >> 24) & 1339 0x1f); 1340 PM8001_IO_DBG(pm8001_ha, 1341 pm8001_printk(": CI=%d PI=%d " 1342 "msgHeader=%x\n", 1343 circularQ->consumer_idx, 1344 circularQ->producer_index, 1345 msgHeader_tmp)); 1346 return MPI_IO_STATUS_SUCCESS; 1347 } else { 1348 circularQ->consumer_idx = 1349 (circularQ->consumer_idx + 1350 ((msgHeader_tmp >> 24) & 0x1f)) 1351 % 256; 1352 msgHeader_tmp = 0; 1353 pm8001_write_32(msgHeader, 0, 0); 1354 /* update the CI of outbound queue */ 1355 pm8001_cw32(pm8001_ha, 1356 circularQ->ci_pci_bar, 1357 circularQ->ci_offset, 1358 circularQ->consumer_idx); 1359 } 1360 } else { 1361 circularQ->consumer_idx = 1362 (circularQ->consumer_idx + 1363 ((msgHeader_tmp >> 24) & 0x1f)) % 256; 1364 msgHeader_tmp = 0; 1365 pm8001_write_32(msgHeader, 0, 0); 1366 /* update the CI of outbound queue */ 1367 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, 1368 circularQ->ci_offset, 1369 circularQ->consumer_idx); 1370 return MPI_IO_STATUS_FAIL; 1371 } 1372 } else { 1373 u32 producer_index; 1374 void *pi_virt = circularQ->pi_virt; 1375 /* Update the producer index from SPC */ 1376 producer_index = pm8001_read_32(pi_virt); 1377 circularQ->producer_index = cpu_to_le32(producer_index); 1378 } 1379 } while (circularQ->producer_index != circularQ->consumer_idx); 1380 /* while we don't have any more not-yet-delivered message */ 1381 /* report empty */ 1382 return MPI_IO_STATUS_BUSY; 1383 } 1384 1385 static void pm8001_work_fn(struct work_struct *work) 1386 { 1387 struct pm8001_work *pw = container_of(work, struct pm8001_work, work); 1388 struct pm8001_device *pm8001_dev; 1389 struct domain_device *dev; 1390 1391 switch (pw->handler) { 1392 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1393 pm8001_dev = pw->data; 1394 dev = pm8001_dev->sas_device; 1395 pm8001_I_T_nexus_reset(dev); 1396 break; 1397 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 1398 pm8001_dev = pw->data; 1399 dev = pm8001_dev->sas_device; 1400 pm8001_I_T_nexus_reset(dev); 1401 break; 1402 case IO_DS_IN_ERROR: 1403 pm8001_dev = pw->data; 1404 dev = pm8001_dev->sas_device; 1405 pm8001_I_T_nexus_reset(dev); 1406 break; 1407 case IO_DS_NON_OPERATIONAL: 1408 pm8001_dev = pw->data; 1409 dev = pm8001_dev->sas_device; 1410 pm8001_I_T_nexus_reset(dev); 1411 break; 1412 } 1413 kfree(pw); 1414 } 1415 1416 static int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data, 1417 int handler) 1418 { 1419 struct pm8001_work *pw; 1420 int ret = 0; 1421 1422 pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC); 1423 if (pw) { 1424 pw->pm8001_ha = pm8001_ha; 1425 pw->data = data; 1426 pw->handler = handler; 1427 INIT_WORK(&pw->work, pm8001_work_fn); 1428 queue_work(pm8001_wq, &pw->work); 1429 } else 1430 ret = -ENOMEM; 1431 1432 return ret; 1433 } 1434 1435 /** 1436 * mpi_ssp_completion- process the event that FW response to the SSP request. 1437 * @pm8001_ha: our hba card information 1438 * @piomb: the message contents of this outbound message. 1439 * 1440 * When FW has completed a ssp request for example a IO request, after it has 1441 * filled the SG data with the data, it will trigger this event represent 1442 * that he has finished the job,please check the coresponding buffer. 1443 * So we will tell the caller who maybe waiting the result to tell upper layer 1444 * that the task has been finished. 1445 */ 1446 static void 1447 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb) 1448 { 1449 struct sas_task *t; 1450 struct pm8001_ccb_info *ccb; 1451 unsigned long flags; 1452 u32 status; 1453 u32 param; 1454 u32 tag; 1455 struct ssp_completion_resp *psspPayload; 1456 struct task_status_struct *ts; 1457 struct ssp_response_iu *iu; 1458 struct pm8001_device *pm8001_dev; 1459 psspPayload = (struct ssp_completion_resp *)(piomb + 4); 1460 status = le32_to_cpu(psspPayload->status); 1461 tag = le32_to_cpu(psspPayload->tag); 1462 ccb = &pm8001_ha->ccb_info[tag]; 1463 pm8001_dev = ccb->device; 1464 param = le32_to_cpu(psspPayload->param); 1465 1466 t = ccb->task; 1467 1468 if (status && status != IO_UNDERFLOW) 1469 PM8001_FAIL_DBG(pm8001_ha, 1470 pm8001_printk("sas IO status 0x%x\n", status)); 1471 if (unlikely(!t || !t->lldd_task || !t->dev)) 1472 return; 1473 ts = &t->task_status; 1474 switch (status) { 1475 case IO_SUCCESS: 1476 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS" 1477 ",param = %d \n", param)); 1478 if (param == 0) { 1479 ts->resp = SAS_TASK_COMPLETE; 1480 ts->stat = SAM_STAT_GOOD; 1481 } else { 1482 ts->resp = SAS_TASK_COMPLETE; 1483 ts->stat = SAS_PROTO_RESPONSE; 1484 ts->residual = param; 1485 iu = &psspPayload->ssp_resp_iu; 1486 sas_ssp_task_response(pm8001_ha->dev, t, iu); 1487 } 1488 if (pm8001_dev) 1489 pm8001_dev->running_req--; 1490 break; 1491 case IO_ABORTED: 1492 PM8001_IO_DBG(pm8001_ha, 1493 pm8001_printk("IO_ABORTED IOMB Tag \n")); 1494 ts->resp = SAS_TASK_COMPLETE; 1495 ts->stat = SAS_ABORTED_TASK; 1496 break; 1497 case IO_UNDERFLOW: 1498 /* SSP Completion with error */ 1499 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW" 1500 ",param = %d \n", param)); 1501 ts->resp = SAS_TASK_COMPLETE; 1502 ts->stat = SAS_DATA_UNDERRUN; 1503 ts->residual = param; 1504 if (pm8001_dev) 1505 pm8001_dev->running_req--; 1506 break; 1507 case IO_NO_DEVICE: 1508 PM8001_IO_DBG(pm8001_ha, 1509 pm8001_printk("IO_NO_DEVICE\n")); 1510 ts->resp = SAS_TASK_UNDELIVERED; 1511 ts->stat = SAS_PHY_DOWN; 1512 break; 1513 case IO_XFER_ERROR_BREAK: 1514 PM8001_IO_DBG(pm8001_ha, 1515 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 1516 ts->resp = SAS_TASK_COMPLETE; 1517 ts->stat = SAS_OPEN_REJECT; 1518 break; 1519 case IO_XFER_ERROR_PHY_NOT_READY: 1520 PM8001_IO_DBG(pm8001_ha, 1521 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 1522 ts->resp = SAS_TASK_COMPLETE; 1523 ts->stat = SAS_OPEN_REJECT; 1524 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1525 break; 1526 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 1527 PM8001_IO_DBG(pm8001_ha, 1528 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 1529 ts->resp = SAS_TASK_COMPLETE; 1530 ts->stat = SAS_OPEN_REJECT; 1531 ts->open_rej_reason = SAS_OREJ_EPROTO; 1532 break; 1533 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 1534 PM8001_IO_DBG(pm8001_ha, 1535 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 1536 ts->resp = SAS_TASK_COMPLETE; 1537 ts->stat = SAS_OPEN_REJECT; 1538 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1539 break; 1540 case IO_OPEN_CNX_ERROR_BREAK: 1541 PM8001_IO_DBG(pm8001_ha, 1542 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 1543 ts->resp = SAS_TASK_COMPLETE; 1544 ts->stat = SAS_OPEN_REJECT; 1545 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1546 break; 1547 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1548 PM8001_IO_DBG(pm8001_ha, 1549 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 1550 ts->resp = SAS_TASK_COMPLETE; 1551 ts->stat = SAS_OPEN_REJECT; 1552 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1553 if (!t->uldd_task) 1554 pm8001_handle_event(pm8001_ha, 1555 pm8001_dev, 1556 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 1557 break; 1558 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 1559 PM8001_IO_DBG(pm8001_ha, 1560 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 1561 ts->resp = SAS_TASK_COMPLETE; 1562 ts->stat = SAS_OPEN_REJECT; 1563 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 1564 break; 1565 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 1566 PM8001_IO_DBG(pm8001_ha, 1567 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 1568 "NOT_SUPPORTED\n")); 1569 ts->resp = SAS_TASK_COMPLETE; 1570 ts->stat = SAS_OPEN_REJECT; 1571 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 1572 break; 1573 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 1574 PM8001_IO_DBG(pm8001_ha, 1575 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 1576 ts->resp = SAS_TASK_UNDELIVERED; 1577 ts->stat = SAS_OPEN_REJECT; 1578 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 1579 break; 1580 case IO_XFER_ERROR_NAK_RECEIVED: 1581 PM8001_IO_DBG(pm8001_ha, 1582 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 1583 ts->resp = SAS_TASK_COMPLETE; 1584 ts->stat = SAS_OPEN_REJECT; 1585 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1586 break; 1587 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 1588 PM8001_IO_DBG(pm8001_ha, 1589 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 1590 ts->resp = SAS_TASK_COMPLETE; 1591 ts->stat = SAS_NAK_R_ERR; 1592 break; 1593 case IO_XFER_ERROR_DMA: 1594 PM8001_IO_DBG(pm8001_ha, 1595 pm8001_printk("IO_XFER_ERROR_DMA\n")); 1596 ts->resp = SAS_TASK_COMPLETE; 1597 ts->stat = SAS_OPEN_REJECT; 1598 break; 1599 case IO_XFER_OPEN_RETRY_TIMEOUT: 1600 PM8001_IO_DBG(pm8001_ha, 1601 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 1602 ts->resp = SAS_TASK_COMPLETE; 1603 ts->stat = SAS_OPEN_REJECT; 1604 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1605 break; 1606 case IO_XFER_ERROR_OFFSET_MISMATCH: 1607 PM8001_IO_DBG(pm8001_ha, 1608 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 1609 ts->resp = SAS_TASK_COMPLETE; 1610 ts->stat = SAS_OPEN_REJECT; 1611 break; 1612 case IO_PORT_IN_RESET: 1613 PM8001_IO_DBG(pm8001_ha, 1614 pm8001_printk("IO_PORT_IN_RESET\n")); 1615 ts->resp = SAS_TASK_COMPLETE; 1616 ts->stat = SAS_OPEN_REJECT; 1617 break; 1618 case IO_DS_NON_OPERATIONAL: 1619 PM8001_IO_DBG(pm8001_ha, 1620 pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 1621 ts->resp = SAS_TASK_COMPLETE; 1622 ts->stat = SAS_OPEN_REJECT; 1623 if (!t->uldd_task) 1624 pm8001_handle_event(pm8001_ha, 1625 pm8001_dev, 1626 IO_DS_NON_OPERATIONAL); 1627 break; 1628 case IO_DS_IN_RECOVERY: 1629 PM8001_IO_DBG(pm8001_ha, 1630 pm8001_printk("IO_DS_IN_RECOVERY\n")); 1631 ts->resp = SAS_TASK_COMPLETE; 1632 ts->stat = SAS_OPEN_REJECT; 1633 break; 1634 case IO_TM_TAG_NOT_FOUND: 1635 PM8001_IO_DBG(pm8001_ha, 1636 pm8001_printk("IO_TM_TAG_NOT_FOUND\n")); 1637 ts->resp = SAS_TASK_COMPLETE; 1638 ts->stat = SAS_OPEN_REJECT; 1639 break; 1640 case IO_SSP_EXT_IU_ZERO_LEN_ERROR: 1641 PM8001_IO_DBG(pm8001_ha, 1642 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n")); 1643 ts->resp = SAS_TASK_COMPLETE; 1644 ts->stat = SAS_OPEN_REJECT; 1645 break; 1646 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 1647 PM8001_IO_DBG(pm8001_ha, 1648 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 1649 ts->resp = SAS_TASK_COMPLETE; 1650 ts->stat = SAS_OPEN_REJECT; 1651 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1652 default: 1653 PM8001_IO_DBG(pm8001_ha, 1654 pm8001_printk("Unknown status 0x%x\n", status)); 1655 /* not allowed case. Therefore, return failed status */ 1656 ts->resp = SAS_TASK_COMPLETE; 1657 ts->stat = SAS_OPEN_REJECT; 1658 break; 1659 } 1660 PM8001_IO_DBG(pm8001_ha, 1661 pm8001_printk("scsi_status = %x \n ", 1662 psspPayload->ssp_resp_iu.status)); 1663 spin_lock_irqsave(&t->task_state_lock, flags); 1664 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 1665 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 1666 t->task_state_flags |= SAS_TASK_STATE_DONE; 1667 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 1668 spin_unlock_irqrestore(&t->task_state_lock, flags); 1669 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with" 1670 " io_status 0x%x resp 0x%x " 1671 "stat 0x%x but aborted by upper layer!\n", 1672 t, status, ts->resp, ts->stat)); 1673 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1674 } else { 1675 spin_unlock_irqrestore(&t->task_state_lock, flags); 1676 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1677 mb();/* in order to force CPU ordering */ 1678 t->task_done(t); 1679 } 1680 } 1681 1682 /*See the comments for mpi_ssp_completion */ 1683 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 1684 { 1685 struct sas_task *t; 1686 unsigned long flags; 1687 struct task_status_struct *ts; 1688 struct pm8001_ccb_info *ccb; 1689 struct pm8001_device *pm8001_dev; 1690 struct ssp_event_resp *psspPayload = 1691 (struct ssp_event_resp *)(piomb + 4); 1692 u32 event = le32_to_cpu(psspPayload->event); 1693 u32 tag = le32_to_cpu(psspPayload->tag); 1694 u32 port_id = le32_to_cpu(psspPayload->port_id); 1695 u32 dev_id = le32_to_cpu(psspPayload->device_id); 1696 1697 ccb = &pm8001_ha->ccb_info[tag]; 1698 t = ccb->task; 1699 pm8001_dev = ccb->device; 1700 if (event) 1701 PM8001_FAIL_DBG(pm8001_ha, 1702 pm8001_printk("sas IO status 0x%x\n", event)); 1703 if (unlikely(!t || !t->lldd_task || !t->dev)) 1704 return; 1705 ts = &t->task_status; 1706 PM8001_IO_DBG(pm8001_ha, 1707 pm8001_printk("port_id = %x,device_id = %x\n", 1708 port_id, dev_id)); 1709 switch (event) { 1710 case IO_OVERFLOW: 1711 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");) 1712 ts->resp = SAS_TASK_COMPLETE; 1713 ts->stat = SAS_DATA_OVERRUN; 1714 ts->residual = 0; 1715 if (pm8001_dev) 1716 pm8001_dev->running_req--; 1717 break; 1718 case IO_XFER_ERROR_BREAK: 1719 PM8001_IO_DBG(pm8001_ha, 1720 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 1721 ts->resp = SAS_TASK_COMPLETE; 1722 ts->stat = SAS_INTERRUPTED; 1723 break; 1724 case IO_XFER_ERROR_PHY_NOT_READY: 1725 PM8001_IO_DBG(pm8001_ha, 1726 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 1727 ts->resp = SAS_TASK_COMPLETE; 1728 ts->stat = SAS_OPEN_REJECT; 1729 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1730 break; 1731 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 1732 PM8001_IO_DBG(pm8001_ha, 1733 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT" 1734 "_SUPPORTED\n")); 1735 ts->resp = SAS_TASK_COMPLETE; 1736 ts->stat = SAS_OPEN_REJECT; 1737 ts->open_rej_reason = SAS_OREJ_EPROTO; 1738 break; 1739 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 1740 PM8001_IO_DBG(pm8001_ha, 1741 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 1742 ts->resp = SAS_TASK_COMPLETE; 1743 ts->stat = SAS_OPEN_REJECT; 1744 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1745 break; 1746 case IO_OPEN_CNX_ERROR_BREAK: 1747 PM8001_IO_DBG(pm8001_ha, 1748 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 1749 ts->resp = SAS_TASK_COMPLETE; 1750 ts->stat = SAS_OPEN_REJECT; 1751 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1752 break; 1753 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1754 PM8001_IO_DBG(pm8001_ha, 1755 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 1756 ts->resp = SAS_TASK_COMPLETE; 1757 ts->stat = SAS_OPEN_REJECT; 1758 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1759 if (!t->uldd_task) 1760 pm8001_handle_event(pm8001_ha, 1761 pm8001_dev, 1762 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 1763 break; 1764 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 1765 PM8001_IO_DBG(pm8001_ha, 1766 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 1767 ts->resp = SAS_TASK_COMPLETE; 1768 ts->stat = SAS_OPEN_REJECT; 1769 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 1770 break; 1771 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 1772 PM8001_IO_DBG(pm8001_ha, 1773 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 1774 "NOT_SUPPORTED\n")); 1775 ts->resp = SAS_TASK_COMPLETE; 1776 ts->stat = SAS_OPEN_REJECT; 1777 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 1778 break; 1779 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 1780 PM8001_IO_DBG(pm8001_ha, 1781 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 1782 ts->resp = SAS_TASK_COMPLETE; 1783 ts->stat = SAS_OPEN_REJECT; 1784 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 1785 break; 1786 case IO_XFER_ERROR_NAK_RECEIVED: 1787 PM8001_IO_DBG(pm8001_ha, 1788 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 1789 ts->resp = SAS_TASK_COMPLETE; 1790 ts->stat = SAS_OPEN_REJECT; 1791 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1792 break; 1793 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 1794 PM8001_IO_DBG(pm8001_ha, 1795 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 1796 ts->resp = SAS_TASK_COMPLETE; 1797 ts->stat = SAS_NAK_R_ERR; 1798 break; 1799 case IO_XFER_OPEN_RETRY_TIMEOUT: 1800 PM8001_IO_DBG(pm8001_ha, 1801 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 1802 ts->resp = SAS_TASK_COMPLETE; 1803 ts->stat = SAS_OPEN_REJECT; 1804 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1805 break; 1806 case IO_XFER_ERROR_UNEXPECTED_PHASE: 1807 PM8001_IO_DBG(pm8001_ha, 1808 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n")); 1809 ts->resp = SAS_TASK_COMPLETE; 1810 ts->stat = SAS_DATA_OVERRUN; 1811 break; 1812 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 1813 PM8001_IO_DBG(pm8001_ha, 1814 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n")); 1815 ts->resp = SAS_TASK_COMPLETE; 1816 ts->stat = SAS_DATA_OVERRUN; 1817 break; 1818 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 1819 PM8001_IO_DBG(pm8001_ha, 1820 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n")); 1821 ts->resp = SAS_TASK_COMPLETE; 1822 ts->stat = SAS_DATA_OVERRUN; 1823 break; 1824 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT: 1825 PM8001_IO_DBG(pm8001_ha, 1826 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n")); 1827 ts->resp = SAS_TASK_COMPLETE; 1828 ts->stat = SAS_DATA_OVERRUN; 1829 break; 1830 case IO_XFER_ERROR_OFFSET_MISMATCH: 1831 PM8001_IO_DBG(pm8001_ha, 1832 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 1833 ts->resp = SAS_TASK_COMPLETE; 1834 ts->stat = SAS_DATA_OVERRUN; 1835 break; 1836 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 1837 PM8001_IO_DBG(pm8001_ha, 1838 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n")); 1839 ts->resp = SAS_TASK_COMPLETE; 1840 ts->stat = SAS_DATA_OVERRUN; 1841 break; 1842 case IO_XFER_CMD_FRAME_ISSUED: 1843 PM8001_IO_DBG(pm8001_ha, 1844 pm8001_printk(" IO_XFER_CMD_FRAME_ISSUED\n")); 1845 return; 1846 default: 1847 PM8001_IO_DBG(pm8001_ha, 1848 pm8001_printk("Unknown status 0x%x\n", event)); 1849 /* not allowed case. Therefore, return failed status */ 1850 ts->resp = SAS_TASK_COMPLETE; 1851 ts->stat = SAS_DATA_OVERRUN; 1852 break; 1853 } 1854 spin_lock_irqsave(&t->task_state_lock, flags); 1855 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 1856 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 1857 t->task_state_flags |= SAS_TASK_STATE_DONE; 1858 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 1859 spin_unlock_irqrestore(&t->task_state_lock, flags); 1860 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with" 1861 " event 0x%x resp 0x%x " 1862 "stat 0x%x but aborted by upper layer!\n", 1863 t, event, ts->resp, ts->stat)); 1864 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1865 } else { 1866 spin_unlock_irqrestore(&t->task_state_lock, flags); 1867 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1868 mb();/* in order to force CPU ordering */ 1869 t->task_done(t); 1870 } 1871 } 1872 1873 /*See the comments for mpi_ssp_completion */ 1874 static void 1875 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 1876 { 1877 struct sas_task *t; 1878 struct pm8001_ccb_info *ccb; 1879 unsigned long flags = 0; 1880 u32 param; 1881 u32 status; 1882 u32 tag; 1883 struct sata_completion_resp *psataPayload; 1884 struct task_status_struct *ts; 1885 struct ata_task_resp *resp ; 1886 u32 *sata_resp; 1887 struct pm8001_device *pm8001_dev; 1888 1889 psataPayload = (struct sata_completion_resp *)(piomb + 4); 1890 status = le32_to_cpu(psataPayload->status); 1891 tag = le32_to_cpu(psataPayload->tag); 1892 1893 ccb = &pm8001_ha->ccb_info[tag]; 1894 param = le32_to_cpu(psataPayload->param); 1895 t = ccb->task; 1896 ts = &t->task_status; 1897 pm8001_dev = ccb->device; 1898 if (status) 1899 PM8001_FAIL_DBG(pm8001_ha, 1900 pm8001_printk("sata IO status 0x%x\n", status)); 1901 if (unlikely(!t || !t->lldd_task || !t->dev)) 1902 return; 1903 1904 switch (status) { 1905 case IO_SUCCESS: 1906 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); 1907 if (param == 0) { 1908 ts->resp = SAS_TASK_COMPLETE; 1909 ts->stat = SAM_STAT_GOOD; 1910 } else { 1911 u8 len; 1912 ts->resp = SAS_TASK_COMPLETE; 1913 ts->stat = SAS_PROTO_RESPONSE; 1914 ts->residual = param; 1915 PM8001_IO_DBG(pm8001_ha, 1916 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n", 1917 param)); 1918 sata_resp = &psataPayload->sata_resp[0]; 1919 resp = (struct ata_task_resp *)ts->buf; 1920 if (t->ata_task.dma_xfer == 0 && 1921 t->data_dir == PCI_DMA_FROMDEVICE) { 1922 len = sizeof(struct pio_setup_fis); 1923 PM8001_IO_DBG(pm8001_ha, 1924 pm8001_printk("PIO read len = %d\n", len)); 1925 } else if (t->ata_task.use_ncq) { 1926 len = sizeof(struct set_dev_bits_fis); 1927 PM8001_IO_DBG(pm8001_ha, 1928 pm8001_printk("FPDMA len = %d\n", len)); 1929 } else { 1930 len = sizeof(struct dev_to_host_fis); 1931 PM8001_IO_DBG(pm8001_ha, 1932 pm8001_printk("other len = %d\n", len)); 1933 } 1934 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) { 1935 resp->frame_len = len; 1936 memcpy(&resp->ending_fis[0], sata_resp, len); 1937 ts->buf_valid_size = sizeof(*resp); 1938 } else 1939 PM8001_IO_DBG(pm8001_ha, 1940 pm8001_printk("response to large \n")); 1941 } 1942 if (pm8001_dev) 1943 pm8001_dev->running_req--; 1944 break; 1945 case IO_ABORTED: 1946 PM8001_IO_DBG(pm8001_ha, 1947 pm8001_printk("IO_ABORTED IOMB Tag \n")); 1948 ts->resp = SAS_TASK_COMPLETE; 1949 ts->stat = SAS_ABORTED_TASK; 1950 if (pm8001_dev) 1951 pm8001_dev->running_req--; 1952 break; 1953 /* following cases are to do cases */ 1954 case IO_UNDERFLOW: 1955 /* SATA Completion with error */ 1956 PM8001_IO_DBG(pm8001_ha, 1957 pm8001_printk("IO_UNDERFLOW param = %d\n", param)); 1958 ts->resp = SAS_TASK_COMPLETE; 1959 ts->stat = SAS_DATA_UNDERRUN; 1960 ts->residual = param; 1961 if (pm8001_dev) 1962 pm8001_dev->running_req--; 1963 break; 1964 case IO_NO_DEVICE: 1965 PM8001_IO_DBG(pm8001_ha, 1966 pm8001_printk("IO_NO_DEVICE\n")); 1967 ts->resp = SAS_TASK_UNDELIVERED; 1968 ts->stat = SAS_PHY_DOWN; 1969 break; 1970 case IO_XFER_ERROR_BREAK: 1971 PM8001_IO_DBG(pm8001_ha, 1972 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 1973 ts->resp = SAS_TASK_COMPLETE; 1974 ts->stat = SAS_INTERRUPTED; 1975 break; 1976 case IO_XFER_ERROR_PHY_NOT_READY: 1977 PM8001_IO_DBG(pm8001_ha, 1978 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 1979 ts->resp = SAS_TASK_COMPLETE; 1980 ts->stat = SAS_OPEN_REJECT; 1981 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1982 break; 1983 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 1984 PM8001_IO_DBG(pm8001_ha, 1985 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT" 1986 "_SUPPORTED\n")); 1987 ts->resp = SAS_TASK_COMPLETE; 1988 ts->stat = SAS_OPEN_REJECT; 1989 ts->open_rej_reason = SAS_OREJ_EPROTO; 1990 break; 1991 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 1992 PM8001_IO_DBG(pm8001_ha, 1993 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 1994 ts->resp = SAS_TASK_COMPLETE; 1995 ts->stat = SAS_OPEN_REJECT; 1996 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1997 break; 1998 case IO_OPEN_CNX_ERROR_BREAK: 1999 PM8001_IO_DBG(pm8001_ha, 2000 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2001 ts->resp = SAS_TASK_COMPLETE; 2002 ts->stat = SAS_OPEN_REJECT; 2003 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2004 break; 2005 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2006 PM8001_IO_DBG(pm8001_ha, 2007 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2008 ts->resp = SAS_TASK_COMPLETE; 2009 ts->stat = SAS_DEV_NO_RESPONSE; 2010 if (!t->uldd_task) { 2011 pm8001_handle_event(pm8001_ha, 2012 pm8001_dev, 2013 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2014 ts->resp = SAS_TASK_UNDELIVERED; 2015 ts->stat = SAS_QUEUE_FULL; 2016 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2017 mb();/*in order to force CPU ordering*/ 2018 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 2019 t->task_done(t); 2020 spin_lock_irqsave(&pm8001_ha->lock, flags); 2021 return; 2022 } 2023 break; 2024 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2025 PM8001_IO_DBG(pm8001_ha, 2026 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2027 ts->resp = SAS_TASK_UNDELIVERED; 2028 ts->stat = SAS_OPEN_REJECT; 2029 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2030 if (!t->uldd_task) { 2031 pm8001_handle_event(pm8001_ha, 2032 pm8001_dev, 2033 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2034 ts->resp = SAS_TASK_UNDELIVERED; 2035 ts->stat = SAS_QUEUE_FULL; 2036 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2037 mb();/*ditto*/ 2038 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 2039 t->task_done(t); 2040 spin_lock_irqsave(&pm8001_ha->lock, flags); 2041 return; 2042 } 2043 break; 2044 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2045 PM8001_IO_DBG(pm8001_ha, 2046 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 2047 "NOT_SUPPORTED\n")); 2048 ts->resp = SAS_TASK_COMPLETE; 2049 ts->stat = SAS_OPEN_REJECT; 2050 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2051 break; 2052 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 2053 PM8001_IO_DBG(pm8001_ha, 2054 pm8001_printk("IO_OPEN_CNX_ERROR_STP_RESOURCES" 2055 "_BUSY\n")); 2056 ts->resp = SAS_TASK_COMPLETE; 2057 ts->stat = SAS_DEV_NO_RESPONSE; 2058 if (!t->uldd_task) { 2059 pm8001_handle_event(pm8001_ha, 2060 pm8001_dev, 2061 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY); 2062 ts->resp = SAS_TASK_UNDELIVERED; 2063 ts->stat = SAS_QUEUE_FULL; 2064 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2065 mb();/* ditto*/ 2066 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 2067 t->task_done(t); 2068 spin_lock_irqsave(&pm8001_ha->lock, flags); 2069 return; 2070 } 2071 break; 2072 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2073 PM8001_IO_DBG(pm8001_ha, 2074 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2075 ts->resp = SAS_TASK_COMPLETE; 2076 ts->stat = SAS_OPEN_REJECT; 2077 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2078 break; 2079 case IO_XFER_ERROR_NAK_RECEIVED: 2080 PM8001_IO_DBG(pm8001_ha, 2081 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 2082 ts->resp = SAS_TASK_COMPLETE; 2083 ts->stat = SAS_NAK_R_ERR; 2084 break; 2085 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2086 PM8001_IO_DBG(pm8001_ha, 2087 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 2088 ts->resp = SAS_TASK_COMPLETE; 2089 ts->stat = SAS_NAK_R_ERR; 2090 break; 2091 case IO_XFER_ERROR_DMA: 2092 PM8001_IO_DBG(pm8001_ha, 2093 pm8001_printk("IO_XFER_ERROR_DMA\n")); 2094 ts->resp = SAS_TASK_COMPLETE; 2095 ts->stat = SAS_ABORTED_TASK; 2096 break; 2097 case IO_XFER_ERROR_SATA_LINK_TIMEOUT: 2098 PM8001_IO_DBG(pm8001_ha, 2099 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n")); 2100 ts->resp = SAS_TASK_UNDELIVERED; 2101 ts->stat = SAS_DEV_NO_RESPONSE; 2102 break; 2103 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2104 PM8001_IO_DBG(pm8001_ha, 2105 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n")); 2106 ts->resp = SAS_TASK_COMPLETE; 2107 ts->stat = SAS_DATA_UNDERRUN; 2108 break; 2109 case IO_XFER_OPEN_RETRY_TIMEOUT: 2110 PM8001_IO_DBG(pm8001_ha, 2111 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2112 ts->resp = SAS_TASK_COMPLETE; 2113 ts->stat = SAS_OPEN_TO; 2114 break; 2115 case IO_PORT_IN_RESET: 2116 PM8001_IO_DBG(pm8001_ha, 2117 pm8001_printk("IO_PORT_IN_RESET\n")); 2118 ts->resp = SAS_TASK_COMPLETE; 2119 ts->stat = SAS_DEV_NO_RESPONSE; 2120 break; 2121 case IO_DS_NON_OPERATIONAL: 2122 PM8001_IO_DBG(pm8001_ha, 2123 pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 2124 ts->resp = SAS_TASK_COMPLETE; 2125 ts->stat = SAS_DEV_NO_RESPONSE; 2126 if (!t->uldd_task) { 2127 pm8001_handle_event(pm8001_ha, pm8001_dev, 2128 IO_DS_NON_OPERATIONAL); 2129 ts->resp = SAS_TASK_UNDELIVERED; 2130 ts->stat = SAS_QUEUE_FULL; 2131 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2132 mb();/*ditto*/ 2133 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 2134 t->task_done(t); 2135 spin_lock_irqsave(&pm8001_ha->lock, flags); 2136 return; 2137 } 2138 break; 2139 case IO_DS_IN_RECOVERY: 2140 PM8001_IO_DBG(pm8001_ha, 2141 pm8001_printk(" IO_DS_IN_RECOVERY\n")); 2142 ts->resp = SAS_TASK_COMPLETE; 2143 ts->stat = SAS_DEV_NO_RESPONSE; 2144 break; 2145 case IO_DS_IN_ERROR: 2146 PM8001_IO_DBG(pm8001_ha, 2147 pm8001_printk("IO_DS_IN_ERROR\n")); 2148 ts->resp = SAS_TASK_COMPLETE; 2149 ts->stat = SAS_DEV_NO_RESPONSE; 2150 if (!t->uldd_task) { 2151 pm8001_handle_event(pm8001_ha, pm8001_dev, 2152 IO_DS_IN_ERROR); 2153 ts->resp = SAS_TASK_UNDELIVERED; 2154 ts->stat = SAS_QUEUE_FULL; 2155 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2156 mb();/*ditto*/ 2157 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 2158 t->task_done(t); 2159 spin_lock_irqsave(&pm8001_ha->lock, flags); 2160 return; 2161 } 2162 break; 2163 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2164 PM8001_IO_DBG(pm8001_ha, 2165 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 2166 ts->resp = SAS_TASK_COMPLETE; 2167 ts->stat = SAS_OPEN_REJECT; 2168 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2169 default: 2170 PM8001_IO_DBG(pm8001_ha, 2171 pm8001_printk("Unknown status 0x%x\n", status)); 2172 /* not allowed case. Therefore, return failed status */ 2173 ts->resp = SAS_TASK_COMPLETE; 2174 ts->stat = SAS_DEV_NO_RESPONSE; 2175 break; 2176 } 2177 spin_lock_irqsave(&t->task_state_lock, flags); 2178 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2179 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2180 t->task_state_flags |= SAS_TASK_STATE_DONE; 2181 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2182 spin_unlock_irqrestore(&t->task_state_lock, flags); 2183 PM8001_FAIL_DBG(pm8001_ha, 2184 pm8001_printk("task 0x%p done with io_status 0x%x" 2185 " resp 0x%x stat 0x%x but aborted by upper layer!\n", 2186 t, status, ts->resp, ts->stat)); 2187 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2188 } else if (t->uldd_task) { 2189 spin_unlock_irqrestore(&t->task_state_lock, flags); 2190 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2191 mb();/* ditto */ 2192 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 2193 t->task_done(t); 2194 spin_lock_irqsave(&pm8001_ha->lock, flags); 2195 } else if (!t->uldd_task) { 2196 spin_unlock_irqrestore(&t->task_state_lock, flags); 2197 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2198 mb();/*ditto*/ 2199 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 2200 t->task_done(t); 2201 spin_lock_irqsave(&pm8001_ha->lock, flags); 2202 } 2203 } 2204 2205 /*See the comments for mpi_ssp_completion */ 2206 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 2207 { 2208 struct sas_task *t; 2209 unsigned long flags = 0; 2210 struct task_status_struct *ts; 2211 struct pm8001_ccb_info *ccb; 2212 struct pm8001_device *pm8001_dev; 2213 struct sata_event_resp *psataPayload = 2214 (struct sata_event_resp *)(piomb + 4); 2215 u32 event = le32_to_cpu(psataPayload->event); 2216 u32 tag = le32_to_cpu(psataPayload->tag); 2217 u32 port_id = le32_to_cpu(psataPayload->port_id); 2218 u32 dev_id = le32_to_cpu(psataPayload->device_id); 2219 2220 ccb = &pm8001_ha->ccb_info[tag]; 2221 t = ccb->task; 2222 pm8001_dev = ccb->device; 2223 if (event) 2224 PM8001_FAIL_DBG(pm8001_ha, 2225 pm8001_printk("sata IO status 0x%x\n", event)); 2226 if (unlikely(!t || !t->lldd_task || !t->dev)) 2227 return; 2228 ts = &t->task_status; 2229 PM8001_IO_DBG(pm8001_ha, 2230 pm8001_printk("port_id = %x,device_id = %x\n", 2231 port_id, dev_id)); 2232 switch (event) { 2233 case IO_OVERFLOW: 2234 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n")); 2235 ts->resp = SAS_TASK_COMPLETE; 2236 ts->stat = SAS_DATA_OVERRUN; 2237 ts->residual = 0; 2238 if (pm8001_dev) 2239 pm8001_dev->running_req--; 2240 break; 2241 case IO_XFER_ERROR_BREAK: 2242 PM8001_IO_DBG(pm8001_ha, 2243 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2244 ts->resp = SAS_TASK_COMPLETE; 2245 ts->stat = SAS_INTERRUPTED; 2246 break; 2247 case IO_XFER_ERROR_PHY_NOT_READY: 2248 PM8001_IO_DBG(pm8001_ha, 2249 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2250 ts->resp = SAS_TASK_COMPLETE; 2251 ts->stat = SAS_OPEN_REJECT; 2252 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2253 break; 2254 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2255 PM8001_IO_DBG(pm8001_ha, 2256 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT" 2257 "_SUPPORTED\n")); 2258 ts->resp = SAS_TASK_COMPLETE; 2259 ts->stat = SAS_OPEN_REJECT; 2260 ts->open_rej_reason = SAS_OREJ_EPROTO; 2261 break; 2262 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2263 PM8001_IO_DBG(pm8001_ha, 2264 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2265 ts->resp = SAS_TASK_COMPLETE; 2266 ts->stat = SAS_OPEN_REJECT; 2267 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2268 break; 2269 case IO_OPEN_CNX_ERROR_BREAK: 2270 PM8001_IO_DBG(pm8001_ha, 2271 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2272 ts->resp = SAS_TASK_COMPLETE; 2273 ts->stat = SAS_OPEN_REJECT; 2274 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2275 break; 2276 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2277 PM8001_IO_DBG(pm8001_ha, 2278 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2279 ts->resp = SAS_TASK_UNDELIVERED; 2280 ts->stat = SAS_DEV_NO_RESPONSE; 2281 if (!t->uldd_task) { 2282 pm8001_handle_event(pm8001_ha, 2283 pm8001_dev, 2284 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2285 ts->resp = SAS_TASK_COMPLETE; 2286 ts->stat = SAS_QUEUE_FULL; 2287 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2288 mb();/*ditto*/ 2289 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 2290 t->task_done(t); 2291 spin_lock_irqsave(&pm8001_ha->lock, flags); 2292 return; 2293 } 2294 break; 2295 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2296 PM8001_IO_DBG(pm8001_ha, 2297 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2298 ts->resp = SAS_TASK_UNDELIVERED; 2299 ts->stat = SAS_OPEN_REJECT; 2300 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2301 break; 2302 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2303 PM8001_IO_DBG(pm8001_ha, 2304 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 2305 "NOT_SUPPORTED\n")); 2306 ts->resp = SAS_TASK_COMPLETE; 2307 ts->stat = SAS_OPEN_REJECT; 2308 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2309 break; 2310 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2311 PM8001_IO_DBG(pm8001_ha, 2312 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2313 ts->resp = SAS_TASK_COMPLETE; 2314 ts->stat = SAS_OPEN_REJECT; 2315 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2316 break; 2317 case IO_XFER_ERROR_NAK_RECEIVED: 2318 PM8001_IO_DBG(pm8001_ha, 2319 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 2320 ts->resp = SAS_TASK_COMPLETE; 2321 ts->stat = SAS_NAK_R_ERR; 2322 break; 2323 case IO_XFER_ERROR_PEER_ABORTED: 2324 PM8001_IO_DBG(pm8001_ha, 2325 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n")); 2326 ts->resp = SAS_TASK_COMPLETE; 2327 ts->stat = SAS_NAK_R_ERR; 2328 break; 2329 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2330 PM8001_IO_DBG(pm8001_ha, 2331 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n")); 2332 ts->resp = SAS_TASK_COMPLETE; 2333 ts->stat = SAS_DATA_UNDERRUN; 2334 break; 2335 case IO_XFER_OPEN_RETRY_TIMEOUT: 2336 PM8001_IO_DBG(pm8001_ha, 2337 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2338 ts->resp = SAS_TASK_COMPLETE; 2339 ts->stat = SAS_OPEN_TO; 2340 break; 2341 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2342 PM8001_IO_DBG(pm8001_ha, 2343 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n")); 2344 ts->resp = SAS_TASK_COMPLETE; 2345 ts->stat = SAS_OPEN_TO; 2346 break; 2347 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2348 PM8001_IO_DBG(pm8001_ha, 2349 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n")); 2350 ts->resp = SAS_TASK_COMPLETE; 2351 ts->stat = SAS_OPEN_TO; 2352 break; 2353 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2354 PM8001_IO_DBG(pm8001_ha, 2355 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n")); 2356 ts->resp = SAS_TASK_COMPLETE; 2357 ts->stat = SAS_OPEN_TO; 2358 break; 2359 case IO_XFER_ERROR_OFFSET_MISMATCH: 2360 PM8001_IO_DBG(pm8001_ha, 2361 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 2362 ts->resp = SAS_TASK_COMPLETE; 2363 ts->stat = SAS_OPEN_TO; 2364 break; 2365 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2366 PM8001_IO_DBG(pm8001_ha, 2367 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n")); 2368 ts->resp = SAS_TASK_COMPLETE; 2369 ts->stat = SAS_OPEN_TO; 2370 break; 2371 case IO_XFER_CMD_FRAME_ISSUED: 2372 PM8001_IO_DBG(pm8001_ha, 2373 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n")); 2374 break; 2375 case IO_XFER_PIO_SETUP_ERROR: 2376 PM8001_IO_DBG(pm8001_ha, 2377 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n")); 2378 ts->resp = SAS_TASK_COMPLETE; 2379 ts->stat = SAS_OPEN_TO; 2380 break; 2381 default: 2382 PM8001_IO_DBG(pm8001_ha, 2383 pm8001_printk("Unknown status 0x%x\n", event)); 2384 /* not allowed case. Therefore, return failed status */ 2385 ts->resp = SAS_TASK_COMPLETE; 2386 ts->stat = SAS_OPEN_TO; 2387 break; 2388 } 2389 spin_lock_irqsave(&t->task_state_lock, flags); 2390 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2391 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2392 t->task_state_flags |= SAS_TASK_STATE_DONE; 2393 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2394 spin_unlock_irqrestore(&t->task_state_lock, flags); 2395 PM8001_FAIL_DBG(pm8001_ha, 2396 pm8001_printk("task 0x%p done with io_status 0x%x" 2397 " resp 0x%x stat 0x%x but aborted by upper layer!\n", 2398 t, event, ts->resp, ts->stat)); 2399 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2400 } else if (t->uldd_task) { 2401 spin_unlock_irqrestore(&t->task_state_lock, flags); 2402 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2403 mb();/* ditto */ 2404 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 2405 t->task_done(t); 2406 spin_lock_irqsave(&pm8001_ha->lock, flags); 2407 } else if (!t->uldd_task) { 2408 spin_unlock_irqrestore(&t->task_state_lock, flags); 2409 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2410 mb();/*ditto*/ 2411 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 2412 t->task_done(t); 2413 spin_lock_irqsave(&pm8001_ha->lock, flags); 2414 } 2415 } 2416 2417 /*See the comments for mpi_ssp_completion */ 2418 static void 2419 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2420 { 2421 u32 param; 2422 struct sas_task *t; 2423 struct pm8001_ccb_info *ccb; 2424 unsigned long flags; 2425 u32 status; 2426 u32 tag; 2427 struct smp_completion_resp *psmpPayload; 2428 struct task_status_struct *ts; 2429 struct pm8001_device *pm8001_dev; 2430 2431 psmpPayload = (struct smp_completion_resp *)(piomb + 4); 2432 status = le32_to_cpu(psmpPayload->status); 2433 tag = le32_to_cpu(psmpPayload->tag); 2434 2435 ccb = &pm8001_ha->ccb_info[tag]; 2436 param = le32_to_cpu(psmpPayload->param); 2437 t = ccb->task; 2438 ts = &t->task_status; 2439 pm8001_dev = ccb->device; 2440 if (status) 2441 PM8001_FAIL_DBG(pm8001_ha, 2442 pm8001_printk("smp IO status 0x%x\n", status)); 2443 if (unlikely(!t || !t->lldd_task || !t->dev)) 2444 return; 2445 2446 switch (status) { 2447 case IO_SUCCESS: 2448 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); 2449 ts->resp = SAS_TASK_COMPLETE; 2450 ts->stat = SAM_STAT_GOOD; 2451 if (pm8001_dev) 2452 pm8001_dev->running_req--; 2453 break; 2454 case IO_ABORTED: 2455 PM8001_IO_DBG(pm8001_ha, 2456 pm8001_printk("IO_ABORTED IOMB\n")); 2457 ts->resp = SAS_TASK_COMPLETE; 2458 ts->stat = SAS_ABORTED_TASK; 2459 if (pm8001_dev) 2460 pm8001_dev->running_req--; 2461 break; 2462 case IO_OVERFLOW: 2463 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n")); 2464 ts->resp = SAS_TASK_COMPLETE; 2465 ts->stat = SAS_DATA_OVERRUN; 2466 ts->residual = 0; 2467 if (pm8001_dev) 2468 pm8001_dev->running_req--; 2469 break; 2470 case IO_NO_DEVICE: 2471 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n")); 2472 ts->resp = SAS_TASK_COMPLETE; 2473 ts->stat = SAS_PHY_DOWN; 2474 break; 2475 case IO_ERROR_HW_TIMEOUT: 2476 PM8001_IO_DBG(pm8001_ha, 2477 pm8001_printk("IO_ERROR_HW_TIMEOUT\n")); 2478 ts->resp = SAS_TASK_COMPLETE; 2479 ts->stat = SAM_STAT_BUSY; 2480 break; 2481 case IO_XFER_ERROR_BREAK: 2482 PM8001_IO_DBG(pm8001_ha, 2483 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2484 ts->resp = SAS_TASK_COMPLETE; 2485 ts->stat = SAM_STAT_BUSY; 2486 break; 2487 case IO_XFER_ERROR_PHY_NOT_READY: 2488 PM8001_IO_DBG(pm8001_ha, 2489 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2490 ts->resp = SAS_TASK_COMPLETE; 2491 ts->stat = SAM_STAT_BUSY; 2492 break; 2493 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2494 PM8001_IO_DBG(pm8001_ha, 2495 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 2496 ts->resp = SAS_TASK_COMPLETE; 2497 ts->stat = SAS_OPEN_REJECT; 2498 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2499 break; 2500 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2501 PM8001_IO_DBG(pm8001_ha, 2502 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2503 ts->resp = SAS_TASK_COMPLETE; 2504 ts->stat = SAS_OPEN_REJECT; 2505 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2506 break; 2507 case IO_OPEN_CNX_ERROR_BREAK: 2508 PM8001_IO_DBG(pm8001_ha, 2509 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2510 ts->resp = SAS_TASK_COMPLETE; 2511 ts->stat = SAS_OPEN_REJECT; 2512 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2513 break; 2514 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2515 PM8001_IO_DBG(pm8001_ha, 2516 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2517 ts->resp = SAS_TASK_COMPLETE; 2518 ts->stat = SAS_OPEN_REJECT; 2519 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2520 pm8001_handle_event(pm8001_ha, 2521 pm8001_dev, 2522 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2523 break; 2524 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2525 PM8001_IO_DBG(pm8001_ha, 2526 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2527 ts->resp = SAS_TASK_COMPLETE; 2528 ts->stat = SAS_OPEN_REJECT; 2529 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2530 break; 2531 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2532 PM8001_IO_DBG(pm8001_ha, 2533 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 2534 "NOT_SUPPORTED\n")); 2535 ts->resp = SAS_TASK_COMPLETE; 2536 ts->stat = SAS_OPEN_REJECT; 2537 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2538 break; 2539 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2540 PM8001_IO_DBG(pm8001_ha, 2541 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2542 ts->resp = SAS_TASK_COMPLETE; 2543 ts->stat = SAS_OPEN_REJECT; 2544 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2545 break; 2546 case IO_XFER_ERROR_RX_FRAME: 2547 PM8001_IO_DBG(pm8001_ha, 2548 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n")); 2549 ts->resp = SAS_TASK_COMPLETE; 2550 ts->stat = SAS_DEV_NO_RESPONSE; 2551 break; 2552 case IO_XFER_OPEN_RETRY_TIMEOUT: 2553 PM8001_IO_DBG(pm8001_ha, 2554 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2555 ts->resp = SAS_TASK_COMPLETE; 2556 ts->stat = SAS_OPEN_REJECT; 2557 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2558 break; 2559 case IO_ERROR_INTERNAL_SMP_RESOURCE: 2560 PM8001_IO_DBG(pm8001_ha, 2561 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n")); 2562 ts->resp = SAS_TASK_COMPLETE; 2563 ts->stat = SAS_QUEUE_FULL; 2564 break; 2565 case IO_PORT_IN_RESET: 2566 PM8001_IO_DBG(pm8001_ha, 2567 pm8001_printk("IO_PORT_IN_RESET\n")); 2568 ts->resp = SAS_TASK_COMPLETE; 2569 ts->stat = SAS_OPEN_REJECT; 2570 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2571 break; 2572 case IO_DS_NON_OPERATIONAL: 2573 PM8001_IO_DBG(pm8001_ha, 2574 pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 2575 ts->resp = SAS_TASK_COMPLETE; 2576 ts->stat = SAS_DEV_NO_RESPONSE; 2577 break; 2578 case IO_DS_IN_RECOVERY: 2579 PM8001_IO_DBG(pm8001_ha, 2580 pm8001_printk("IO_DS_IN_RECOVERY\n")); 2581 ts->resp = SAS_TASK_COMPLETE; 2582 ts->stat = SAS_OPEN_REJECT; 2583 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2584 break; 2585 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2586 PM8001_IO_DBG(pm8001_ha, 2587 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 2588 ts->resp = SAS_TASK_COMPLETE; 2589 ts->stat = SAS_OPEN_REJECT; 2590 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2591 break; 2592 default: 2593 PM8001_IO_DBG(pm8001_ha, 2594 pm8001_printk("Unknown status 0x%x\n", status)); 2595 ts->resp = SAS_TASK_COMPLETE; 2596 ts->stat = SAS_DEV_NO_RESPONSE; 2597 /* not allowed case. Therefore, return failed status */ 2598 break; 2599 } 2600 spin_lock_irqsave(&t->task_state_lock, flags); 2601 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2602 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2603 t->task_state_flags |= SAS_TASK_STATE_DONE; 2604 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2605 spin_unlock_irqrestore(&t->task_state_lock, flags); 2606 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with" 2607 " io_status 0x%x resp 0x%x " 2608 "stat 0x%x but aborted by upper layer!\n", 2609 t, status, ts->resp, ts->stat)); 2610 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2611 } else { 2612 spin_unlock_irqrestore(&t->task_state_lock, flags); 2613 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2614 mb();/* in order to force CPU ordering */ 2615 t->task_done(t); 2616 } 2617 } 2618 2619 static void 2620 mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 2621 { 2622 struct set_dev_state_resp *pPayload = 2623 (struct set_dev_state_resp *)(piomb + 4); 2624 u32 tag = le32_to_cpu(pPayload->tag); 2625 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 2626 struct pm8001_device *pm8001_dev = ccb->device; 2627 u32 status = le32_to_cpu(pPayload->status); 2628 u32 device_id = le32_to_cpu(pPayload->device_id); 2629 u8 pds = le32_to_cpu(pPayload->pds_nds) | PDS_BITS; 2630 u8 nds = le32_to_cpu(pPayload->pds_nds) | NDS_BITS; 2631 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set device id = 0x%x state " 2632 "from 0x%x to 0x%x status = 0x%x!\n", 2633 device_id, pds, nds, status)); 2634 complete(pm8001_dev->setds_completion); 2635 ccb->task = NULL; 2636 ccb->ccb_tag = 0xFFFFFFFF; 2637 pm8001_ccb_free(pm8001_ha, tag); 2638 } 2639 2640 static void 2641 mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 2642 { 2643 struct get_nvm_data_resp *pPayload = 2644 (struct get_nvm_data_resp *)(piomb + 4); 2645 u32 tag = le32_to_cpu(pPayload->tag); 2646 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 2647 u32 dlen_status = le32_to_cpu(pPayload->dlen_status); 2648 complete(pm8001_ha->nvmd_completion); 2649 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set nvm data complete!\n")); 2650 if ((dlen_status & NVMD_STAT) != 0) { 2651 PM8001_FAIL_DBG(pm8001_ha, 2652 pm8001_printk("Set nvm data error!\n")); 2653 return; 2654 } 2655 ccb->task = NULL; 2656 ccb->ccb_tag = 0xFFFFFFFF; 2657 pm8001_ccb_free(pm8001_ha, tag); 2658 } 2659 2660 static void 2661 mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 2662 { 2663 struct fw_control_ex *fw_control_context; 2664 struct get_nvm_data_resp *pPayload = 2665 (struct get_nvm_data_resp *)(piomb + 4); 2666 u32 tag = le32_to_cpu(pPayload->tag); 2667 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 2668 u32 dlen_status = le32_to_cpu(pPayload->dlen_status); 2669 u32 ir_tds_bn_dps_das_nvm = 2670 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm); 2671 void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr; 2672 fw_control_context = ccb->fw_control_context; 2673 2674 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Get nvm data complete!\n")); 2675 if ((dlen_status & NVMD_STAT) != 0) { 2676 PM8001_FAIL_DBG(pm8001_ha, 2677 pm8001_printk("Get nvm data error!\n")); 2678 complete(pm8001_ha->nvmd_completion); 2679 return; 2680 } 2681 2682 if (ir_tds_bn_dps_das_nvm & IPMode) { 2683 /* indirect mode - IR bit set */ 2684 PM8001_MSG_DBG(pm8001_ha, 2685 pm8001_printk("Get NVMD success, IR=1\n")); 2686 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) { 2687 if (ir_tds_bn_dps_das_nvm == 0x80a80200) { 2688 memcpy(pm8001_ha->sas_addr, 2689 ((u8 *)virt_addr + 4), 2690 SAS_ADDR_SIZE); 2691 PM8001_MSG_DBG(pm8001_ha, 2692 pm8001_printk("Get SAS address" 2693 " from VPD successfully!\n")); 2694 } 2695 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM) 2696 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) || 2697 ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) { 2698 ; 2699 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP) 2700 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) { 2701 ; 2702 } else { 2703 /* Should not be happened*/ 2704 PM8001_MSG_DBG(pm8001_ha, 2705 pm8001_printk("(IR=1)Wrong Device type 0x%x\n", 2706 ir_tds_bn_dps_das_nvm)); 2707 } 2708 } else /* direct mode */{ 2709 PM8001_MSG_DBG(pm8001_ha, 2710 pm8001_printk("Get NVMD success, IR=0, dataLen=%d\n", 2711 (dlen_status & NVMD_LEN) >> 24)); 2712 } 2713 memcpy(fw_control_context->usrAddr, 2714 pm8001_ha->memoryMap.region[NVMD].virt_ptr, 2715 fw_control_context->len); 2716 complete(pm8001_ha->nvmd_completion); 2717 ccb->task = NULL; 2718 ccb->ccb_tag = 0xFFFFFFFF; 2719 pm8001_ccb_free(pm8001_ha, tag); 2720 } 2721 2722 static int mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb) 2723 { 2724 struct local_phy_ctl_resp *pPayload = 2725 (struct local_phy_ctl_resp *)(piomb + 4); 2726 u32 status = le32_to_cpu(pPayload->status); 2727 u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS; 2728 u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS; 2729 if (status != 0) { 2730 PM8001_MSG_DBG(pm8001_ha, 2731 pm8001_printk("%x phy execute %x phy op failed! \n", 2732 phy_id, phy_op)); 2733 } else 2734 PM8001_MSG_DBG(pm8001_ha, 2735 pm8001_printk("%x phy execute %x phy op success! \n", 2736 phy_id, phy_op)); 2737 return 0; 2738 } 2739 2740 /** 2741 * pm8001_bytes_dmaed - one of the interface function communication with libsas 2742 * @pm8001_ha: our hba card information 2743 * @i: which phy that received the event. 2744 * 2745 * when HBA driver received the identify done event or initiate FIS received 2746 * event(for SATA), it will invoke this function to notify the sas layer that 2747 * the sas toplogy has formed, please discover the the whole sas domain, 2748 * while receive a broadcast(change) primitive just tell the sas 2749 * layer to discover the changed domain rather than the whole domain. 2750 */ 2751 static void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i) 2752 { 2753 struct pm8001_phy *phy = &pm8001_ha->phy[i]; 2754 struct asd_sas_phy *sas_phy = &phy->sas_phy; 2755 struct sas_ha_struct *sas_ha; 2756 if (!phy->phy_attached) 2757 return; 2758 2759 sas_ha = pm8001_ha->sas; 2760 if (sas_phy->phy) { 2761 struct sas_phy *sphy = sas_phy->phy; 2762 sphy->negotiated_linkrate = sas_phy->linkrate; 2763 sphy->minimum_linkrate = phy->minimum_linkrate; 2764 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS; 2765 sphy->maximum_linkrate = phy->maximum_linkrate; 2766 sphy->maximum_linkrate_hw = phy->maximum_linkrate; 2767 } 2768 2769 if (phy->phy_type & PORT_TYPE_SAS) { 2770 struct sas_identify_frame *id; 2771 id = (struct sas_identify_frame *)phy->frame_rcvd; 2772 id->dev_type = phy->identify.device_type; 2773 id->initiator_bits = SAS_PROTOCOL_ALL; 2774 id->target_bits = phy->identify.target_port_protocols; 2775 } else if (phy->phy_type & PORT_TYPE_SATA) { 2776 /*Nothing*/ 2777 } 2778 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("phy %d byte dmaded.\n", i)); 2779 2780 sas_phy->frame_rcvd_size = phy->frame_rcvd_size; 2781 pm8001_ha->sas->notify_port_event(sas_phy, PORTE_BYTES_DMAED); 2782 } 2783 2784 /* Get the link rate speed */ 2785 static void get_lrate_mode(struct pm8001_phy *phy, u8 link_rate) 2786 { 2787 struct sas_phy *sas_phy = phy->sas_phy.phy; 2788 2789 switch (link_rate) { 2790 case PHY_SPEED_60: 2791 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS; 2792 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS; 2793 break; 2794 case PHY_SPEED_30: 2795 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS; 2796 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS; 2797 break; 2798 case PHY_SPEED_15: 2799 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS; 2800 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS; 2801 break; 2802 } 2803 sas_phy->negotiated_linkrate = phy->sas_phy.linkrate; 2804 sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS; 2805 sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS; 2806 sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS; 2807 sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS; 2808 } 2809 2810 /** 2811 * asd_get_attached_sas_addr -- extract/generate attached SAS address 2812 * @phy: pointer to asd_phy 2813 * @sas_addr: pointer to buffer where the SAS address is to be written 2814 * 2815 * This function extracts the SAS address from an IDENTIFY frame 2816 * received. If OOB is SATA, then a SAS address is generated from the 2817 * HA tables. 2818 * 2819 * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame 2820 * buffer. 2821 */ 2822 static void pm8001_get_attached_sas_addr(struct pm8001_phy *phy, 2823 u8 *sas_addr) 2824 { 2825 if (phy->sas_phy.frame_rcvd[0] == 0x34 2826 && phy->sas_phy.oob_mode == SATA_OOB_MODE) { 2827 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha; 2828 /* FIS device-to-host */ 2829 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr); 2830 addr += phy->sas_phy.id; 2831 *(__be64 *)sas_addr = cpu_to_be64(addr); 2832 } else { 2833 struct sas_identify_frame *idframe = 2834 (void *) phy->sas_phy.frame_rcvd; 2835 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE); 2836 } 2837 } 2838 2839 /** 2840 * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW. 2841 * @pm8001_ha: our hba card information 2842 * @Qnum: the outbound queue message number. 2843 * @SEA: source of event to ack 2844 * @port_id: port id. 2845 * @phyId: phy id. 2846 * @param0: parameter 0. 2847 * @param1: parameter 1. 2848 */ 2849 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha, 2850 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1) 2851 { 2852 struct hw_event_ack_req payload; 2853 u32 opc = OPC_INB_SAS_HW_EVENT_ACK; 2854 2855 struct inbound_queue_table *circularQ; 2856 2857 memset((u8 *)&payload, 0, sizeof(payload)); 2858 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum]; 2859 payload.tag = 1; 2860 payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) | 2861 ((phyId & 0x0F) << 4) | (port_id & 0x0F)); 2862 payload.param0 = cpu_to_le32(param0); 2863 payload.param1 = cpu_to_le32(param1); 2864 mpi_build_cmd(pm8001_ha, circularQ, opc, &payload); 2865 } 2866 2867 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 2868 u32 phyId, u32 phy_op); 2869 2870 /** 2871 * hw_event_sas_phy_up -FW tells me a SAS phy up event. 2872 * @pm8001_ha: our hba card information 2873 * @piomb: IO message buffer 2874 */ 2875 static void 2876 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 2877 { 2878 struct hw_event_resp *pPayload = 2879 (struct hw_event_resp *)(piomb + 4); 2880 u32 lr_evt_status_phyid_portid = 2881 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 2882 u8 link_rate = 2883 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28); 2884 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 2885 u8 phy_id = 2886 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 2887 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate); 2888 u8 portstate = (u8)(npip_portstate & 0x0000000F); 2889 struct pm8001_port *port = &pm8001_ha->port[port_id]; 2890 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 2891 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 2892 unsigned long flags; 2893 u8 deviceType = pPayload->sas_identify.dev_type; 2894 port->port_state = portstate; 2895 PM8001_MSG_DBG(pm8001_ha, 2896 pm8001_printk("HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n", 2897 port_id, phy_id)); 2898 2899 switch (deviceType) { 2900 case SAS_PHY_UNUSED: 2901 PM8001_MSG_DBG(pm8001_ha, 2902 pm8001_printk("device type no device.\n")); 2903 break; 2904 case SAS_END_DEVICE: 2905 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n")); 2906 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id, 2907 PHY_NOTIFY_ENABLE_SPINUP); 2908 port->port_attached = 1; 2909 get_lrate_mode(phy, link_rate); 2910 break; 2911 case SAS_EDGE_EXPANDER_DEVICE: 2912 PM8001_MSG_DBG(pm8001_ha, 2913 pm8001_printk("expander device.\n")); 2914 port->port_attached = 1; 2915 get_lrate_mode(phy, link_rate); 2916 break; 2917 case SAS_FANOUT_EXPANDER_DEVICE: 2918 PM8001_MSG_DBG(pm8001_ha, 2919 pm8001_printk("fanout expander device.\n")); 2920 port->port_attached = 1; 2921 get_lrate_mode(phy, link_rate); 2922 break; 2923 default: 2924 PM8001_MSG_DBG(pm8001_ha, 2925 pm8001_printk("unknown device type(%x)\n", deviceType)); 2926 break; 2927 } 2928 phy->phy_type |= PORT_TYPE_SAS; 2929 phy->identify.device_type = deviceType; 2930 phy->phy_attached = 1; 2931 if (phy->identify.device_type == SAS_END_DEV) 2932 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP; 2933 else if (phy->identify.device_type != NO_DEVICE) 2934 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP; 2935 phy->sas_phy.oob_mode = SAS_OOB_MODE; 2936 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE); 2937 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 2938 memcpy(phy->frame_rcvd, &pPayload->sas_identify, 2939 sizeof(struct sas_identify_frame)-4); 2940 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4; 2941 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 2942 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 2943 if (pm8001_ha->flags == PM8001F_RUN_TIME) 2944 mdelay(200);/*delay a moment to wait disk to spinup*/ 2945 pm8001_bytes_dmaed(pm8001_ha, phy_id); 2946 } 2947 2948 /** 2949 * hw_event_sata_phy_up -FW tells me a SATA phy up event. 2950 * @pm8001_ha: our hba card information 2951 * @piomb: IO message buffer 2952 */ 2953 static void 2954 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 2955 { 2956 struct hw_event_resp *pPayload = 2957 (struct hw_event_resp *)(piomb + 4); 2958 u32 lr_evt_status_phyid_portid = 2959 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 2960 u8 link_rate = 2961 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28); 2962 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 2963 u8 phy_id = 2964 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 2965 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate); 2966 u8 portstate = (u8)(npip_portstate & 0x0000000F); 2967 struct pm8001_port *port = &pm8001_ha->port[port_id]; 2968 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 2969 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 2970 unsigned long flags; 2971 PM8001_MSG_DBG(pm8001_ha, 2972 pm8001_printk("HW_EVENT_SATA_PHY_UP port id = %d," 2973 " phy id = %d\n", port_id, phy_id)); 2974 port->port_state = portstate; 2975 port->port_attached = 1; 2976 get_lrate_mode(phy, link_rate); 2977 phy->phy_type |= PORT_TYPE_SATA; 2978 phy->phy_attached = 1; 2979 phy->sas_phy.oob_mode = SATA_OOB_MODE; 2980 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE); 2981 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 2982 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4), 2983 sizeof(struct dev_to_host_fis)); 2984 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 2985 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 2986 phy->identify.device_type = SATA_DEV; 2987 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 2988 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 2989 pm8001_bytes_dmaed(pm8001_ha, phy_id); 2990 } 2991 2992 /** 2993 * hw_event_phy_down -we should notify the libsas the phy is down. 2994 * @pm8001_ha: our hba card information 2995 * @piomb: IO message buffer 2996 */ 2997 static void 2998 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb) 2999 { 3000 struct hw_event_resp *pPayload = 3001 (struct hw_event_resp *)(piomb + 4); 3002 u32 lr_evt_status_phyid_portid = 3003 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3004 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3005 u8 phy_id = 3006 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3007 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate); 3008 u8 portstate = (u8)(npip_portstate & 0x0000000F); 3009 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3010 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3011 port->port_state = portstate; 3012 phy->phy_type = 0; 3013 phy->identify.device_type = 0; 3014 phy->phy_attached = 0; 3015 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE); 3016 switch (portstate) { 3017 case PORT_VALID: 3018 break; 3019 case PORT_INVALID: 3020 PM8001_MSG_DBG(pm8001_ha, 3021 pm8001_printk(" PortInvalid portID %d \n", port_id)); 3022 PM8001_MSG_DBG(pm8001_ha, 3023 pm8001_printk(" Last phy Down and port invalid\n")); 3024 port->port_attached = 0; 3025 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3026 port_id, phy_id, 0, 0); 3027 break; 3028 case PORT_IN_RESET: 3029 PM8001_MSG_DBG(pm8001_ha, 3030 pm8001_printk(" Port In Reset portID %d \n", port_id)); 3031 break; 3032 case PORT_NOT_ESTABLISHED: 3033 PM8001_MSG_DBG(pm8001_ha, 3034 pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n")); 3035 port->port_attached = 0; 3036 break; 3037 case PORT_LOSTCOMM: 3038 PM8001_MSG_DBG(pm8001_ha, 3039 pm8001_printk(" phy Down and PORT_LOSTCOMM\n")); 3040 PM8001_MSG_DBG(pm8001_ha, 3041 pm8001_printk(" Last phy Down and port invalid\n")); 3042 port->port_attached = 0; 3043 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3044 port_id, phy_id, 0, 0); 3045 break; 3046 default: 3047 port->port_attached = 0; 3048 PM8001_MSG_DBG(pm8001_ha, 3049 pm8001_printk(" phy Down and(default) = %x\n", 3050 portstate)); 3051 break; 3052 3053 } 3054 } 3055 3056 /** 3057 * mpi_reg_resp -process register device ID response. 3058 * @pm8001_ha: our hba card information 3059 * @piomb: IO message buffer 3060 * 3061 * when sas layer find a device it will notify LLDD, then the driver register 3062 * the domain device to FW, this event is the return device ID which the FW 3063 * has assigned, from now,inter-communication with FW is no longer using the 3064 * SAS address, use device ID which FW assigned. 3065 */ 3066 static int mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3067 { 3068 u32 status; 3069 u32 device_id; 3070 u32 htag; 3071 struct pm8001_ccb_info *ccb; 3072 struct pm8001_device *pm8001_dev; 3073 struct dev_reg_resp *registerRespPayload = 3074 (struct dev_reg_resp *)(piomb + 4); 3075 3076 htag = le32_to_cpu(registerRespPayload->tag); 3077 ccb = &pm8001_ha->ccb_info[registerRespPayload->tag]; 3078 pm8001_dev = ccb->device; 3079 status = le32_to_cpu(registerRespPayload->status); 3080 device_id = le32_to_cpu(registerRespPayload->device_id); 3081 PM8001_MSG_DBG(pm8001_ha, 3082 pm8001_printk(" register device is status = %d\n", status)); 3083 switch (status) { 3084 case DEVREG_SUCCESS: 3085 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("DEVREG_SUCCESS\n")); 3086 pm8001_dev->device_id = device_id; 3087 break; 3088 case DEVREG_FAILURE_OUT_OF_RESOURCE: 3089 PM8001_MSG_DBG(pm8001_ha, 3090 pm8001_printk("DEVREG_FAILURE_OUT_OF_RESOURCE\n")); 3091 break; 3092 case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED: 3093 PM8001_MSG_DBG(pm8001_ha, 3094 pm8001_printk("DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n")); 3095 break; 3096 case DEVREG_FAILURE_INVALID_PHY_ID: 3097 PM8001_MSG_DBG(pm8001_ha, 3098 pm8001_printk("DEVREG_FAILURE_INVALID_PHY_ID\n")); 3099 break; 3100 case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED: 3101 PM8001_MSG_DBG(pm8001_ha, 3102 pm8001_printk("DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n")); 3103 break; 3104 case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE: 3105 PM8001_MSG_DBG(pm8001_ha, 3106 pm8001_printk("DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n")); 3107 break; 3108 case DEVREG_FAILURE_PORT_NOT_VALID_STATE: 3109 PM8001_MSG_DBG(pm8001_ha, 3110 pm8001_printk("DEVREG_FAILURE_PORT_NOT_VALID_STATE\n")); 3111 break; 3112 case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID: 3113 PM8001_MSG_DBG(pm8001_ha, 3114 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n")); 3115 break; 3116 default: 3117 PM8001_MSG_DBG(pm8001_ha, 3118 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_UNSORPORTED\n")); 3119 break; 3120 } 3121 complete(pm8001_dev->dcompletion); 3122 ccb->task = NULL; 3123 ccb->ccb_tag = 0xFFFFFFFF; 3124 pm8001_ccb_free(pm8001_ha, htag); 3125 return 0; 3126 } 3127 3128 static int mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3129 { 3130 u32 status; 3131 u32 device_id; 3132 struct dev_reg_resp *registerRespPayload = 3133 (struct dev_reg_resp *)(piomb + 4); 3134 3135 status = le32_to_cpu(registerRespPayload->status); 3136 device_id = le32_to_cpu(registerRespPayload->device_id); 3137 if (status != 0) 3138 PM8001_MSG_DBG(pm8001_ha, 3139 pm8001_printk(" deregister device failed ,status = %x" 3140 ", device_id = %x\n", status, device_id)); 3141 return 0; 3142 } 3143 3144 static int 3145 mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3146 { 3147 u32 status; 3148 struct fw_control_ex fw_control_context; 3149 struct fw_flash_Update_resp *ppayload = 3150 (struct fw_flash_Update_resp *)(piomb + 4); 3151 u32 tag = le32_to_cpu(ppayload->tag); 3152 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 3153 status = le32_to_cpu(ppayload->status); 3154 memcpy(&fw_control_context, 3155 ccb->fw_control_context, 3156 sizeof(fw_control_context)); 3157 switch (status) { 3158 case FLASH_UPDATE_COMPLETE_PENDING_REBOOT: 3159 PM8001_MSG_DBG(pm8001_ha, 3160 pm8001_printk(": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n")); 3161 break; 3162 case FLASH_UPDATE_IN_PROGRESS: 3163 PM8001_MSG_DBG(pm8001_ha, 3164 pm8001_printk(": FLASH_UPDATE_IN_PROGRESS\n")); 3165 break; 3166 case FLASH_UPDATE_HDR_ERR: 3167 PM8001_MSG_DBG(pm8001_ha, 3168 pm8001_printk(": FLASH_UPDATE_HDR_ERR\n")); 3169 break; 3170 case FLASH_UPDATE_OFFSET_ERR: 3171 PM8001_MSG_DBG(pm8001_ha, 3172 pm8001_printk(": FLASH_UPDATE_OFFSET_ERR\n")); 3173 break; 3174 case FLASH_UPDATE_CRC_ERR: 3175 PM8001_MSG_DBG(pm8001_ha, 3176 pm8001_printk(": FLASH_UPDATE_CRC_ERR\n")); 3177 break; 3178 case FLASH_UPDATE_LENGTH_ERR: 3179 PM8001_MSG_DBG(pm8001_ha, 3180 pm8001_printk(": FLASH_UPDATE_LENGTH_ERR\n")); 3181 break; 3182 case FLASH_UPDATE_HW_ERR: 3183 PM8001_MSG_DBG(pm8001_ha, 3184 pm8001_printk(": FLASH_UPDATE_HW_ERR\n")); 3185 break; 3186 case FLASH_UPDATE_DNLD_NOT_SUPPORTED: 3187 PM8001_MSG_DBG(pm8001_ha, 3188 pm8001_printk(": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n")); 3189 break; 3190 case FLASH_UPDATE_DISABLED: 3191 PM8001_MSG_DBG(pm8001_ha, 3192 pm8001_printk(": FLASH_UPDATE_DISABLED\n")); 3193 break; 3194 default: 3195 PM8001_MSG_DBG(pm8001_ha, 3196 pm8001_printk("No matched status = %d\n", status)); 3197 break; 3198 } 3199 ccb->fw_control_context->fw_control->retcode = status; 3200 pci_free_consistent(pm8001_ha->pdev, 3201 fw_control_context.len, 3202 fw_control_context.virtAddr, 3203 fw_control_context.phys_addr); 3204 complete(pm8001_ha->nvmd_completion); 3205 ccb->task = NULL; 3206 ccb->ccb_tag = 0xFFFFFFFF; 3207 pm8001_ccb_free(pm8001_ha, tag); 3208 return 0; 3209 } 3210 3211 static int 3212 mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 3213 { 3214 u32 status; 3215 int i; 3216 struct general_event_resp *pPayload = 3217 (struct general_event_resp *)(piomb + 4); 3218 status = le32_to_cpu(pPayload->status); 3219 PM8001_MSG_DBG(pm8001_ha, 3220 pm8001_printk(" status = 0x%x\n", status)); 3221 for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++) 3222 PM8001_MSG_DBG(pm8001_ha, 3223 pm8001_printk("inb_IOMB_payload[0x%x] 0x%x, \n", i, 3224 pPayload->inb_IOMB_payload[i])); 3225 return 0; 3226 } 3227 3228 static int 3229 mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3230 { 3231 struct sas_task *t; 3232 struct pm8001_ccb_info *ccb; 3233 unsigned long flags; 3234 u32 status ; 3235 u32 tag, scp; 3236 struct task_status_struct *ts; 3237 3238 struct task_abort_resp *pPayload = 3239 (struct task_abort_resp *)(piomb + 4); 3240 ccb = &pm8001_ha->ccb_info[pPayload->tag]; 3241 t = ccb->task; 3242 3243 3244 status = le32_to_cpu(pPayload->status); 3245 tag = le32_to_cpu(pPayload->tag); 3246 scp = le32_to_cpu(pPayload->scp); 3247 PM8001_IO_DBG(pm8001_ha, 3248 pm8001_printk(" status = 0x%x\n", status)); 3249 if (t == NULL) 3250 return -1; 3251 ts = &t->task_status; 3252 if (status != 0) 3253 PM8001_FAIL_DBG(pm8001_ha, 3254 pm8001_printk("task abort failed status 0x%x ," 3255 "tag = 0x%x, scp= 0x%x\n", status, tag, scp)); 3256 switch (status) { 3257 case IO_SUCCESS: 3258 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); 3259 ts->resp = SAS_TASK_COMPLETE; 3260 ts->stat = SAM_STAT_GOOD; 3261 break; 3262 case IO_NOT_VALID: 3263 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_NOT_VALID\n")); 3264 ts->resp = TMF_RESP_FUNC_FAILED; 3265 break; 3266 } 3267 spin_lock_irqsave(&t->task_state_lock, flags); 3268 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 3269 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 3270 t->task_state_flags |= SAS_TASK_STATE_DONE; 3271 spin_unlock_irqrestore(&t->task_state_lock, flags); 3272 pm8001_ccb_task_free(pm8001_ha, t, ccb, pPayload->tag); 3273 mb(); 3274 t->task_done(t); 3275 return 0; 3276 } 3277 3278 /** 3279 * mpi_hw_event -The hw event has come. 3280 * @pm8001_ha: our hba card information 3281 * @piomb: IO message buffer 3282 */ 3283 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb) 3284 { 3285 unsigned long flags; 3286 struct hw_event_resp *pPayload = 3287 (struct hw_event_resp *)(piomb + 4); 3288 u32 lr_evt_status_phyid_portid = 3289 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3290 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3291 u8 phy_id = 3292 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3293 u16 eventType = 3294 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8); 3295 u8 status = 3296 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24); 3297 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3298 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3299 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id]; 3300 PM8001_MSG_DBG(pm8001_ha, 3301 pm8001_printk("outbound queue HW event & event type : ")); 3302 switch (eventType) { 3303 case HW_EVENT_PHY_START_STATUS: 3304 PM8001_MSG_DBG(pm8001_ha, 3305 pm8001_printk("HW_EVENT_PHY_START_STATUS" 3306 " status = %x\n", status)); 3307 if (status == 0) { 3308 phy->phy_state = 1; 3309 if (pm8001_ha->flags == PM8001F_RUN_TIME) 3310 complete(phy->enable_completion); 3311 } 3312 break; 3313 case HW_EVENT_SAS_PHY_UP: 3314 PM8001_MSG_DBG(pm8001_ha, 3315 pm8001_printk("HW_EVENT_PHY_START_STATUS \n")); 3316 hw_event_sas_phy_up(pm8001_ha, piomb); 3317 break; 3318 case HW_EVENT_SATA_PHY_UP: 3319 PM8001_MSG_DBG(pm8001_ha, 3320 pm8001_printk("HW_EVENT_SATA_PHY_UP \n")); 3321 hw_event_sata_phy_up(pm8001_ha, piomb); 3322 break; 3323 case HW_EVENT_PHY_STOP_STATUS: 3324 PM8001_MSG_DBG(pm8001_ha, 3325 pm8001_printk("HW_EVENT_PHY_STOP_STATUS " 3326 "status = %x\n", status)); 3327 if (status == 0) 3328 phy->phy_state = 0; 3329 break; 3330 case HW_EVENT_SATA_SPINUP_HOLD: 3331 PM8001_MSG_DBG(pm8001_ha, 3332 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD \n")); 3333 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD); 3334 break; 3335 case HW_EVENT_PHY_DOWN: 3336 PM8001_MSG_DBG(pm8001_ha, 3337 pm8001_printk("HW_EVENT_PHY_DOWN \n")); 3338 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL); 3339 phy->phy_attached = 0; 3340 phy->phy_state = 0; 3341 hw_event_phy_down(pm8001_ha, piomb); 3342 break; 3343 case HW_EVENT_PORT_INVALID: 3344 PM8001_MSG_DBG(pm8001_ha, 3345 pm8001_printk("HW_EVENT_PORT_INVALID\n")); 3346 sas_phy_disconnected(sas_phy); 3347 phy->phy_attached = 0; 3348 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3349 break; 3350 /* the broadcast change primitive received, tell the LIBSAS this event 3351 to revalidate the sas domain*/ 3352 case HW_EVENT_BROADCAST_CHANGE: 3353 PM8001_MSG_DBG(pm8001_ha, 3354 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n")); 3355 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE, 3356 port_id, phy_id, 1, 0); 3357 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3358 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE; 3359 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3360 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3361 break; 3362 case HW_EVENT_PHY_ERROR: 3363 PM8001_MSG_DBG(pm8001_ha, 3364 pm8001_printk("HW_EVENT_PHY_ERROR\n")); 3365 sas_phy_disconnected(&phy->sas_phy); 3366 phy->phy_attached = 0; 3367 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR); 3368 break; 3369 case HW_EVENT_BROADCAST_EXP: 3370 PM8001_MSG_DBG(pm8001_ha, 3371 pm8001_printk("HW_EVENT_BROADCAST_EXP\n")); 3372 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3373 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP; 3374 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3375 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3376 break; 3377 case HW_EVENT_LINK_ERR_INVALID_DWORD: 3378 PM8001_MSG_DBG(pm8001_ha, 3379 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n")); 3380 pm8001_hw_event_ack_req(pm8001_ha, 0, 3381 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0); 3382 sas_phy_disconnected(sas_phy); 3383 phy->phy_attached = 0; 3384 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3385 break; 3386 case HW_EVENT_LINK_ERR_DISPARITY_ERROR: 3387 PM8001_MSG_DBG(pm8001_ha, 3388 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n")); 3389 pm8001_hw_event_ack_req(pm8001_ha, 0, 3390 HW_EVENT_LINK_ERR_DISPARITY_ERROR, 3391 port_id, phy_id, 0, 0); 3392 sas_phy_disconnected(sas_phy); 3393 phy->phy_attached = 0; 3394 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3395 break; 3396 case HW_EVENT_LINK_ERR_CODE_VIOLATION: 3397 PM8001_MSG_DBG(pm8001_ha, 3398 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n")); 3399 pm8001_hw_event_ack_req(pm8001_ha, 0, 3400 HW_EVENT_LINK_ERR_CODE_VIOLATION, 3401 port_id, phy_id, 0, 0); 3402 sas_phy_disconnected(sas_phy); 3403 phy->phy_attached = 0; 3404 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3405 break; 3406 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH: 3407 PM8001_MSG_DBG(pm8001_ha, 3408 pm8001_printk("HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n")); 3409 pm8001_hw_event_ack_req(pm8001_ha, 0, 3410 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH, 3411 port_id, phy_id, 0, 0); 3412 sas_phy_disconnected(sas_phy); 3413 phy->phy_attached = 0; 3414 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3415 break; 3416 case HW_EVENT_MALFUNCTION: 3417 PM8001_MSG_DBG(pm8001_ha, 3418 pm8001_printk("HW_EVENT_MALFUNCTION\n")); 3419 break; 3420 case HW_EVENT_BROADCAST_SES: 3421 PM8001_MSG_DBG(pm8001_ha, 3422 pm8001_printk("HW_EVENT_BROADCAST_SES\n")); 3423 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3424 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES; 3425 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3426 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3427 break; 3428 case HW_EVENT_INBOUND_CRC_ERROR: 3429 PM8001_MSG_DBG(pm8001_ha, 3430 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n")); 3431 pm8001_hw_event_ack_req(pm8001_ha, 0, 3432 HW_EVENT_INBOUND_CRC_ERROR, 3433 port_id, phy_id, 0, 0); 3434 break; 3435 case HW_EVENT_HARD_RESET_RECEIVED: 3436 PM8001_MSG_DBG(pm8001_ha, 3437 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n")); 3438 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET); 3439 break; 3440 case HW_EVENT_ID_FRAME_TIMEOUT: 3441 PM8001_MSG_DBG(pm8001_ha, 3442 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n")); 3443 sas_phy_disconnected(sas_phy); 3444 phy->phy_attached = 0; 3445 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3446 break; 3447 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED: 3448 PM8001_MSG_DBG(pm8001_ha, 3449 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED \n")); 3450 pm8001_hw_event_ack_req(pm8001_ha, 0, 3451 HW_EVENT_LINK_ERR_PHY_RESET_FAILED, 3452 port_id, phy_id, 0, 0); 3453 sas_phy_disconnected(sas_phy); 3454 phy->phy_attached = 0; 3455 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3456 break; 3457 case HW_EVENT_PORT_RESET_TIMER_TMO: 3458 PM8001_MSG_DBG(pm8001_ha, 3459 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO \n")); 3460 sas_phy_disconnected(sas_phy); 3461 phy->phy_attached = 0; 3462 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3463 break; 3464 case HW_EVENT_PORT_RECOVERY_TIMER_TMO: 3465 PM8001_MSG_DBG(pm8001_ha, 3466 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO \n")); 3467 sas_phy_disconnected(sas_phy); 3468 phy->phy_attached = 0; 3469 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3470 break; 3471 case HW_EVENT_PORT_RECOVER: 3472 PM8001_MSG_DBG(pm8001_ha, 3473 pm8001_printk("HW_EVENT_PORT_RECOVER \n")); 3474 break; 3475 case HW_EVENT_PORT_RESET_COMPLETE: 3476 PM8001_MSG_DBG(pm8001_ha, 3477 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE \n")); 3478 break; 3479 case EVENT_BROADCAST_ASYNCH_EVENT: 3480 PM8001_MSG_DBG(pm8001_ha, 3481 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n")); 3482 break; 3483 default: 3484 PM8001_MSG_DBG(pm8001_ha, 3485 pm8001_printk("Unknown event type = %x\n", eventType)); 3486 break; 3487 } 3488 return 0; 3489 } 3490 3491 /** 3492 * process_one_iomb - process one outbound Queue memory block 3493 * @pm8001_ha: our hba card information 3494 * @piomb: IO message buffer 3495 */ 3496 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb) 3497 { 3498 u32 pHeader = (u32)*(u32 *)piomb; 3499 u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF); 3500 3501 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("process_one_iomb:")); 3502 3503 switch (opc) { 3504 case OPC_OUB_ECHO: 3505 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO \n")); 3506 break; 3507 case OPC_OUB_HW_EVENT: 3508 PM8001_MSG_DBG(pm8001_ha, 3509 pm8001_printk("OPC_OUB_HW_EVENT \n")); 3510 mpi_hw_event(pm8001_ha, piomb); 3511 break; 3512 case OPC_OUB_SSP_COMP: 3513 PM8001_MSG_DBG(pm8001_ha, 3514 pm8001_printk("OPC_OUB_SSP_COMP \n")); 3515 mpi_ssp_completion(pm8001_ha, piomb); 3516 break; 3517 case OPC_OUB_SMP_COMP: 3518 PM8001_MSG_DBG(pm8001_ha, 3519 pm8001_printk("OPC_OUB_SMP_COMP \n")); 3520 mpi_smp_completion(pm8001_ha, piomb); 3521 break; 3522 case OPC_OUB_LOCAL_PHY_CNTRL: 3523 PM8001_MSG_DBG(pm8001_ha, 3524 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n")); 3525 mpi_local_phy_ctl(pm8001_ha, piomb); 3526 break; 3527 case OPC_OUB_DEV_REGIST: 3528 PM8001_MSG_DBG(pm8001_ha, 3529 pm8001_printk("OPC_OUB_DEV_REGIST \n")); 3530 mpi_reg_resp(pm8001_ha, piomb); 3531 break; 3532 case OPC_OUB_DEREG_DEV: 3533 PM8001_MSG_DBG(pm8001_ha, 3534 pm8001_printk("unresgister the deviece \n")); 3535 mpi_dereg_resp(pm8001_ha, piomb); 3536 break; 3537 case OPC_OUB_GET_DEV_HANDLE: 3538 PM8001_MSG_DBG(pm8001_ha, 3539 pm8001_printk("OPC_OUB_GET_DEV_HANDLE \n")); 3540 break; 3541 case OPC_OUB_SATA_COMP: 3542 PM8001_MSG_DBG(pm8001_ha, 3543 pm8001_printk("OPC_OUB_SATA_COMP \n")); 3544 mpi_sata_completion(pm8001_ha, piomb); 3545 break; 3546 case OPC_OUB_SATA_EVENT: 3547 PM8001_MSG_DBG(pm8001_ha, 3548 pm8001_printk("OPC_OUB_SATA_EVENT \n")); 3549 mpi_sata_event(pm8001_ha, piomb); 3550 break; 3551 case OPC_OUB_SSP_EVENT: 3552 PM8001_MSG_DBG(pm8001_ha, 3553 pm8001_printk("OPC_OUB_SSP_EVENT\n")); 3554 mpi_ssp_event(pm8001_ha, piomb); 3555 break; 3556 case OPC_OUB_DEV_HANDLE_ARRIV: 3557 PM8001_MSG_DBG(pm8001_ha, 3558 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n")); 3559 /*This is for target*/ 3560 break; 3561 case OPC_OUB_SSP_RECV_EVENT: 3562 PM8001_MSG_DBG(pm8001_ha, 3563 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n")); 3564 /*This is for target*/ 3565 break; 3566 case OPC_OUB_DEV_INFO: 3567 PM8001_MSG_DBG(pm8001_ha, 3568 pm8001_printk("OPC_OUB_DEV_INFO\n")); 3569 break; 3570 case OPC_OUB_FW_FLASH_UPDATE: 3571 PM8001_MSG_DBG(pm8001_ha, 3572 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n")); 3573 mpi_fw_flash_update_resp(pm8001_ha, piomb); 3574 break; 3575 case OPC_OUB_GPIO_RESPONSE: 3576 PM8001_MSG_DBG(pm8001_ha, 3577 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n")); 3578 break; 3579 case OPC_OUB_GPIO_EVENT: 3580 PM8001_MSG_DBG(pm8001_ha, 3581 pm8001_printk("OPC_OUB_GPIO_EVENT\n")); 3582 break; 3583 case OPC_OUB_GENERAL_EVENT: 3584 PM8001_MSG_DBG(pm8001_ha, 3585 pm8001_printk("OPC_OUB_GENERAL_EVENT\n")); 3586 mpi_general_event(pm8001_ha, piomb); 3587 break; 3588 case OPC_OUB_SSP_ABORT_RSP: 3589 PM8001_MSG_DBG(pm8001_ha, 3590 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n")); 3591 mpi_task_abort_resp(pm8001_ha, piomb); 3592 break; 3593 case OPC_OUB_SATA_ABORT_RSP: 3594 PM8001_MSG_DBG(pm8001_ha, 3595 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n")); 3596 mpi_task_abort_resp(pm8001_ha, piomb); 3597 break; 3598 case OPC_OUB_SAS_DIAG_MODE_START_END: 3599 PM8001_MSG_DBG(pm8001_ha, 3600 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n")); 3601 break; 3602 case OPC_OUB_SAS_DIAG_EXECUTE: 3603 PM8001_MSG_DBG(pm8001_ha, 3604 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n")); 3605 break; 3606 case OPC_OUB_GET_TIME_STAMP: 3607 PM8001_MSG_DBG(pm8001_ha, 3608 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n")); 3609 break; 3610 case OPC_OUB_SAS_HW_EVENT_ACK: 3611 PM8001_MSG_DBG(pm8001_ha, 3612 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n")); 3613 break; 3614 case OPC_OUB_PORT_CONTROL: 3615 PM8001_MSG_DBG(pm8001_ha, 3616 pm8001_printk("OPC_OUB_PORT_CONTROL\n")); 3617 break; 3618 case OPC_OUB_SMP_ABORT_RSP: 3619 PM8001_MSG_DBG(pm8001_ha, 3620 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n")); 3621 mpi_task_abort_resp(pm8001_ha, piomb); 3622 break; 3623 case OPC_OUB_GET_NVMD_DATA: 3624 PM8001_MSG_DBG(pm8001_ha, 3625 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n")); 3626 mpi_get_nvmd_resp(pm8001_ha, piomb); 3627 break; 3628 case OPC_OUB_SET_NVMD_DATA: 3629 PM8001_MSG_DBG(pm8001_ha, 3630 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n")); 3631 mpi_set_nvmd_resp(pm8001_ha, piomb); 3632 break; 3633 case OPC_OUB_DEVICE_HANDLE_REMOVAL: 3634 PM8001_MSG_DBG(pm8001_ha, 3635 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n")); 3636 break; 3637 case OPC_OUB_SET_DEVICE_STATE: 3638 PM8001_MSG_DBG(pm8001_ha, 3639 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n")); 3640 mpi_set_dev_state_resp(pm8001_ha, piomb); 3641 break; 3642 case OPC_OUB_GET_DEVICE_STATE: 3643 PM8001_MSG_DBG(pm8001_ha, 3644 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n")); 3645 break; 3646 case OPC_OUB_SET_DEV_INFO: 3647 PM8001_MSG_DBG(pm8001_ha, 3648 pm8001_printk("OPC_OUB_SET_DEV_INFO\n")); 3649 break; 3650 case OPC_OUB_SAS_RE_INITIALIZE: 3651 PM8001_MSG_DBG(pm8001_ha, 3652 pm8001_printk("OPC_OUB_SAS_RE_INITIALIZE\n")); 3653 break; 3654 default: 3655 PM8001_MSG_DBG(pm8001_ha, 3656 pm8001_printk("Unknown outbound Queue IOMB OPC = %x\n", 3657 opc)); 3658 break; 3659 } 3660 } 3661 3662 static int process_oq(struct pm8001_hba_info *pm8001_ha) 3663 { 3664 struct outbound_queue_table *circularQ; 3665 void *pMsg1 = NULL; 3666 u8 bc = 0; 3667 u32 ret = MPI_IO_STATUS_FAIL; 3668 3669 circularQ = &pm8001_ha->outbnd_q_tbl[0]; 3670 do { 3671 ret = mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc); 3672 if (MPI_IO_STATUS_SUCCESS == ret) { 3673 /* process the outbound message */ 3674 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4)); 3675 /* free the message from the outbound circular buffer */ 3676 mpi_msg_free_set(pm8001_ha, pMsg1, circularQ, bc); 3677 } 3678 if (MPI_IO_STATUS_BUSY == ret) { 3679 u32 producer_idx; 3680 /* Update the producer index from SPC */ 3681 producer_idx = pm8001_read_32(circularQ->pi_virt); 3682 circularQ->producer_index = cpu_to_le32(producer_idx); 3683 if (circularQ->producer_index == 3684 circularQ->consumer_idx) 3685 /* OQ is empty */ 3686 break; 3687 } 3688 } while (1); 3689 return ret; 3690 } 3691 3692 /* PCI_DMA_... to our direction translation. */ 3693 static const u8 data_dir_flags[] = { 3694 [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */ 3695 [PCI_DMA_TODEVICE] = DATA_DIR_OUT,/* OUTBOUND */ 3696 [PCI_DMA_FROMDEVICE] = DATA_DIR_IN,/* INBOUND */ 3697 [PCI_DMA_NONE] = DATA_DIR_NONE,/* NO TRANSFER */ 3698 }; 3699 static void 3700 pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd) 3701 { 3702 int i; 3703 struct scatterlist *sg; 3704 struct pm8001_prd *buf_prd = prd; 3705 3706 for_each_sg(scatter, sg, nr, i) { 3707 buf_prd->addr = cpu_to_le64(sg_dma_address(sg)); 3708 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg)); 3709 buf_prd->im_len.e = 0; 3710 buf_prd++; 3711 } 3712 } 3713 3714 static void build_smp_cmd(u32 deviceID, u32 hTag, struct smp_req *psmp_cmd) 3715 { 3716 psmp_cmd->tag = cpu_to_le32(hTag); 3717 psmp_cmd->device_id = cpu_to_le32(deviceID); 3718 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1)); 3719 } 3720 3721 /** 3722 * pm8001_chip_smp_req - send a SMP task to FW 3723 * @pm8001_ha: our hba card information. 3724 * @ccb: the ccb information this request used. 3725 */ 3726 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha, 3727 struct pm8001_ccb_info *ccb) 3728 { 3729 int elem, rc; 3730 struct sas_task *task = ccb->task; 3731 struct domain_device *dev = task->dev; 3732 struct pm8001_device *pm8001_dev = dev->lldd_dev; 3733 struct scatterlist *sg_req, *sg_resp; 3734 u32 req_len, resp_len; 3735 struct smp_req smp_cmd; 3736 u32 opc; 3737 struct inbound_queue_table *circularQ; 3738 3739 memset(&smp_cmd, 0, sizeof(smp_cmd)); 3740 /* 3741 * DMA-map SMP request, response buffers 3742 */ 3743 sg_req = &task->smp_task.smp_req; 3744 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE); 3745 if (!elem) 3746 return -ENOMEM; 3747 req_len = sg_dma_len(sg_req); 3748 3749 sg_resp = &task->smp_task.smp_resp; 3750 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE); 3751 if (!elem) { 3752 rc = -ENOMEM; 3753 goto err_out; 3754 } 3755 resp_len = sg_dma_len(sg_resp); 3756 /* must be in dwords */ 3757 if ((req_len & 0x3) || (resp_len & 0x3)) { 3758 rc = -EINVAL; 3759 goto err_out_2; 3760 } 3761 3762 opc = OPC_INB_SMP_REQUEST; 3763 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 3764 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag); 3765 smp_cmd.long_smp_req.long_req_addr = 3766 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req)); 3767 smp_cmd.long_smp_req.long_req_size = 3768 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4); 3769 smp_cmd.long_smp_req.long_resp_addr = 3770 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp)); 3771 smp_cmd.long_smp_req.long_resp_size = 3772 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4); 3773 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd); 3774 mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd); 3775 return 0; 3776 3777 err_out_2: 3778 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1, 3779 PCI_DMA_FROMDEVICE); 3780 err_out: 3781 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1, 3782 PCI_DMA_TODEVICE); 3783 return rc; 3784 } 3785 3786 /** 3787 * pm8001_chip_ssp_io_req - send a SSP task to FW 3788 * @pm8001_ha: our hba card information. 3789 * @ccb: the ccb information this request used. 3790 */ 3791 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha, 3792 struct pm8001_ccb_info *ccb) 3793 { 3794 struct sas_task *task = ccb->task; 3795 struct domain_device *dev = task->dev; 3796 struct pm8001_device *pm8001_dev = dev->lldd_dev; 3797 struct ssp_ini_io_start_req ssp_cmd; 3798 u32 tag = ccb->ccb_tag; 3799 int ret; 3800 __le64 phys_addr; 3801 struct inbound_queue_table *circularQ; 3802 u32 opc = OPC_INB_SSPINIIOSTART; 3803 memset(&ssp_cmd, 0, sizeof(ssp_cmd)); 3804 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8); 3805 ssp_cmd.dir_m_tlr = 3806 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for 3807 SAS 1.1 compatible TLR*/ 3808 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len); 3809 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id); 3810 ssp_cmd.tag = cpu_to_le32(tag); 3811 if (task->ssp_task.enable_first_burst) 3812 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80; 3813 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3); 3814 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7); 3815 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cdb, 16); 3816 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 3817 3818 /* fill in PRD (scatter/gather) table, if any */ 3819 if (task->num_scatter > 1) { 3820 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd); 3821 phys_addr = cpu_to_le64(ccb->ccb_dma_handle + 3822 offsetof(struct pm8001_ccb_info, buf_prd[0])); 3823 ssp_cmd.addr_low = lower_32_bits(phys_addr); 3824 ssp_cmd.addr_high = upper_32_bits(phys_addr); 3825 ssp_cmd.esgl = cpu_to_le32(1<<31); 3826 } else if (task->num_scatter == 1) { 3827 __le64 dma_addr = cpu_to_le64(sg_dma_address(task->scatter)); 3828 ssp_cmd.addr_low = lower_32_bits(dma_addr); 3829 ssp_cmd.addr_high = upper_32_bits(dma_addr); 3830 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 3831 ssp_cmd.esgl = 0; 3832 } else if (task->num_scatter == 0) { 3833 ssp_cmd.addr_low = 0; 3834 ssp_cmd.addr_high = 0; 3835 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 3836 ssp_cmd.esgl = 0; 3837 } 3838 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd); 3839 return ret; 3840 } 3841 3842 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha, 3843 struct pm8001_ccb_info *ccb) 3844 { 3845 struct sas_task *task = ccb->task; 3846 struct domain_device *dev = task->dev; 3847 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev; 3848 u32 tag = ccb->ccb_tag; 3849 int ret; 3850 struct sata_start_req sata_cmd; 3851 u32 hdr_tag, ncg_tag = 0; 3852 __le64 phys_addr; 3853 u32 ATAP = 0x0; 3854 u32 dir; 3855 struct inbound_queue_table *circularQ; 3856 u32 opc = OPC_INB_SATA_HOST_OPSTART; 3857 memset(&sata_cmd, 0, sizeof(sata_cmd)); 3858 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 3859 if (task->data_dir == PCI_DMA_NONE) { 3860 ATAP = 0x04; /* no data*/ 3861 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data \n")); 3862 } else if (likely(!task->ata_task.device_control_reg_update)) { 3863 if (task->ata_task.dma_xfer) { 3864 ATAP = 0x06; /* DMA */ 3865 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA \n")); 3866 } else { 3867 ATAP = 0x05; /* PIO*/ 3868 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO \n")); 3869 } 3870 if (task->ata_task.use_ncq && 3871 dev->sata_dev.command_set != ATAPI_COMMAND_SET) { 3872 ATAP = 0x07; /* FPDMA */ 3873 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA \n")); 3874 } 3875 } 3876 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) 3877 ncg_tag = hdr_tag; 3878 dir = data_dir_flags[task->data_dir] << 8; 3879 sata_cmd.tag = cpu_to_le32(tag); 3880 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 3881 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len); 3882 sata_cmd.ncqtag_atap_dir_m = 3883 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir); 3884 sata_cmd.sata_fis = task->ata_task.fis; 3885 if (likely(!task->ata_task.device_control_reg_update)) 3886 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */ 3887 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */ 3888 /* fill in PRD (scatter/gather) table, if any */ 3889 if (task->num_scatter > 1) { 3890 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd); 3891 phys_addr = cpu_to_le64(ccb->ccb_dma_handle + 3892 offsetof(struct pm8001_ccb_info, buf_prd[0])); 3893 sata_cmd.addr_low = lower_32_bits(phys_addr); 3894 sata_cmd.addr_high = upper_32_bits(phys_addr); 3895 sata_cmd.esgl = cpu_to_le32(1 << 31); 3896 } else if (task->num_scatter == 1) { 3897 __le64 dma_addr = cpu_to_le64(sg_dma_address(task->scatter)); 3898 sata_cmd.addr_low = lower_32_bits(dma_addr); 3899 sata_cmd.addr_high = upper_32_bits(dma_addr); 3900 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 3901 sata_cmd.esgl = 0; 3902 } else if (task->num_scatter == 0) { 3903 sata_cmd.addr_low = 0; 3904 sata_cmd.addr_high = 0; 3905 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 3906 sata_cmd.esgl = 0; 3907 } 3908 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd); 3909 return ret; 3910 } 3911 3912 /** 3913 * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND 3914 * @pm8001_ha: our hba card information. 3915 * @num: the inbound queue number 3916 * @phy_id: the phy id which we wanted to start up. 3917 */ 3918 static int 3919 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id) 3920 { 3921 struct phy_start_req payload; 3922 struct inbound_queue_table *circularQ; 3923 int ret; 3924 u32 tag = 0x01; 3925 u32 opcode = OPC_INB_PHYSTART; 3926 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 3927 memset(&payload, 0, sizeof(payload)); 3928 payload.tag = cpu_to_le32(tag); 3929 /* 3930 ** [0:7] PHY Identifier 3931 ** [8:11] link rate 1.5G, 3G, 6G 3932 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both 3933 ** [14] 0b disable spin up hold; 1b enable spin up hold 3934 */ 3935 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE | 3936 LINKMODE_AUTO | LINKRATE_15 | 3937 LINKRATE_30 | LINKRATE_60 | phy_id); 3938 payload.sas_identify.dev_type = SAS_END_DEV; 3939 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL; 3940 memcpy(payload.sas_identify.sas_addr, 3941 pm8001_ha->sas_addr, SAS_ADDR_SIZE); 3942 payload.sas_identify.phy_id = phy_id; 3943 ret = mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload); 3944 return ret; 3945 } 3946 3947 /** 3948 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND 3949 * @pm8001_ha: our hba card information. 3950 * @num: the inbound queue number 3951 * @phy_id: the phy id which we wanted to start up. 3952 */ 3953 static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha, 3954 u8 phy_id) 3955 { 3956 struct phy_stop_req payload; 3957 struct inbound_queue_table *circularQ; 3958 int ret; 3959 u32 tag = 0x01; 3960 u32 opcode = OPC_INB_PHYSTOP; 3961 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 3962 memset(&payload, 0, sizeof(payload)); 3963 payload.tag = cpu_to_le32(tag); 3964 payload.phy_id = cpu_to_le32(phy_id); 3965 ret = mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload); 3966 return ret; 3967 } 3968 3969 /** 3970 * see comments on mpi_reg_resp. 3971 */ 3972 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha, 3973 struct pm8001_device *pm8001_dev, u32 flag) 3974 { 3975 struct reg_dev_req payload; 3976 u32 opc; 3977 u32 stp_sspsmp_sata = 0x4; 3978 struct inbound_queue_table *circularQ; 3979 u32 linkrate, phy_id; 3980 int rc, tag = 0xdeadbeef; 3981 struct pm8001_ccb_info *ccb; 3982 u8 retryFlag = 0x1; 3983 u16 firstBurstSize = 0; 3984 u16 ITNT = 2000; 3985 struct domain_device *dev = pm8001_dev->sas_device; 3986 struct domain_device *parent_dev = dev->parent; 3987 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 3988 3989 memset(&payload, 0, sizeof(payload)); 3990 rc = pm8001_tag_alloc(pm8001_ha, &tag); 3991 if (rc) 3992 return rc; 3993 ccb = &pm8001_ha->ccb_info[tag]; 3994 ccb->device = pm8001_dev; 3995 ccb->ccb_tag = tag; 3996 payload.tag = cpu_to_le32(tag); 3997 if (flag == 1) 3998 stp_sspsmp_sata = 0x02; /*direct attached sata */ 3999 else { 4000 if (pm8001_dev->dev_type == SATA_DEV) 4001 stp_sspsmp_sata = 0x00; /* stp*/ 4002 else if (pm8001_dev->dev_type == SAS_END_DEV || 4003 pm8001_dev->dev_type == EDGE_DEV || 4004 pm8001_dev->dev_type == FANOUT_DEV) 4005 stp_sspsmp_sata = 0x01; /*ssp or smp*/ 4006 } 4007 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 4008 phy_id = parent_dev->ex_dev.ex_phy->phy_id; 4009 else 4010 phy_id = pm8001_dev->attached_phy; 4011 opc = OPC_INB_REG_DEV; 4012 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ? 4013 pm8001_dev->sas_device->linkrate : dev->port->linkrate; 4014 payload.phyid_portid = 4015 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) | 4016 ((phy_id & 0x0F) << 4)); 4017 payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) | 4018 ((linkrate & 0x0F) * 0x1000000) | 4019 ((stp_sspsmp_sata & 0x03) * 0x10000000)); 4020 payload.firstburstsize_ITNexustimeout = 4021 cpu_to_le32(ITNT | (firstBurstSize * 0x10000)); 4022 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr, 4023 SAS_ADDR_SIZE); 4024 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload); 4025 return rc; 4026 } 4027 4028 /** 4029 * see comments on mpi_reg_resp. 4030 */ 4031 static int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha, 4032 u32 device_id) 4033 { 4034 struct dereg_dev_req payload; 4035 u32 opc = OPC_INB_DEREG_DEV_HANDLE; 4036 int ret; 4037 struct inbound_queue_table *circularQ; 4038 4039 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4040 memset(&payload, 0, sizeof(payload)); 4041 payload.tag = 1; 4042 payload.device_id = cpu_to_le32(device_id); 4043 PM8001_MSG_DBG(pm8001_ha, 4044 pm8001_printk("unregister device device_id = %d\n", device_id)); 4045 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload); 4046 return ret; 4047 } 4048 4049 /** 4050 * pm8001_chip_phy_ctl_req - support the local phy operation 4051 * @pm8001_ha: our hba card information. 4052 * @num: the inbound queue number 4053 * @phy_id: the phy id which we wanted to operate 4054 * @phy_op: 4055 */ 4056 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 4057 u32 phyId, u32 phy_op) 4058 { 4059 struct local_phy_ctl_req payload; 4060 struct inbound_queue_table *circularQ; 4061 int ret; 4062 u32 opc = OPC_INB_LOCAL_PHY_CONTROL; 4063 memset(&payload, 0, sizeof(payload)); 4064 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4065 payload.tag = 1; 4066 payload.phyop_phyid = 4067 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F)); 4068 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload); 4069 return ret; 4070 } 4071 4072 static u32 pm8001_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha) 4073 { 4074 u32 value; 4075 #ifdef PM8001_USE_MSIX 4076 return 1; 4077 #endif 4078 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR); 4079 if (value) 4080 return 1; 4081 return 0; 4082 4083 } 4084 4085 /** 4086 * pm8001_chip_isr - PM8001 isr handler. 4087 * @pm8001_ha: our hba card information. 4088 * @irq: irq number. 4089 * @stat: stat. 4090 */ 4091 static irqreturn_t 4092 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha) 4093 { 4094 unsigned long flags; 4095 spin_lock_irqsave(&pm8001_ha->lock, flags); 4096 pm8001_chip_interrupt_disable(pm8001_ha); 4097 process_oq(pm8001_ha); 4098 pm8001_chip_interrupt_enable(pm8001_ha); 4099 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 4100 return IRQ_HANDLED; 4101 } 4102 4103 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc, 4104 u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag) 4105 { 4106 struct task_abort_req task_abort; 4107 struct inbound_queue_table *circularQ; 4108 int ret; 4109 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4110 memset(&task_abort, 0, sizeof(task_abort)); 4111 if (ABORT_SINGLE == (flag & ABORT_MASK)) { 4112 task_abort.abort_all = 0; 4113 task_abort.device_id = cpu_to_le32(dev_id); 4114 task_abort.tag_to_abort = cpu_to_le32(task_tag); 4115 task_abort.tag = cpu_to_le32(cmd_tag); 4116 } else if (ABORT_ALL == (flag & ABORT_MASK)) { 4117 task_abort.abort_all = cpu_to_le32(1); 4118 task_abort.device_id = cpu_to_le32(dev_id); 4119 task_abort.tag = cpu_to_le32(cmd_tag); 4120 } 4121 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort); 4122 return ret; 4123 } 4124 4125 /** 4126 * pm8001_chip_abort_task - SAS abort task when error or exception happened. 4127 * @task: the task we wanted to aborted. 4128 * @flag: the abort flag. 4129 */ 4130 static int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha, 4131 struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag) 4132 { 4133 u32 opc, device_id; 4134 int rc = TMF_RESP_FUNC_FAILED; 4135 PM8001_EH_DBG(pm8001_ha, pm8001_printk("cmd_tag = %x, abort task tag" 4136 " = %x", cmd_tag, task_tag)); 4137 if (pm8001_dev->dev_type == SAS_END_DEV) 4138 opc = OPC_INB_SSP_ABORT; 4139 else if (pm8001_dev->dev_type == SATA_DEV) 4140 opc = OPC_INB_SATA_ABORT; 4141 else 4142 opc = OPC_INB_SMP_ABORT;/* SMP */ 4143 device_id = pm8001_dev->device_id; 4144 rc = send_task_abort(pm8001_ha, opc, device_id, flag, 4145 task_tag, cmd_tag); 4146 if (rc != TMF_RESP_FUNC_COMPLETE) 4147 PM8001_EH_DBG(pm8001_ha, pm8001_printk("rc= %d\n", rc)); 4148 return rc; 4149 } 4150 4151 /** 4152 * pm8001_chip_ssp_tm_req - built the task management command. 4153 * @pm8001_ha: our hba card information. 4154 * @ccb: the ccb information. 4155 * @tmf: task management function. 4156 */ 4157 static int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha, 4158 struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf) 4159 { 4160 struct sas_task *task = ccb->task; 4161 struct domain_device *dev = task->dev; 4162 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4163 u32 opc = OPC_INB_SSPINITMSTART; 4164 struct inbound_queue_table *circularQ; 4165 struct ssp_ini_tm_start_req sspTMCmd; 4166 int ret; 4167 4168 memset(&sspTMCmd, 0, sizeof(sspTMCmd)); 4169 sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id); 4170 sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed); 4171 sspTMCmd.tmf = cpu_to_le32(tmf->tmf); 4172 memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8); 4173 sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag); 4174 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4175 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd); 4176 return ret; 4177 } 4178 4179 static int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha, 4180 void *payload) 4181 { 4182 u32 opc = OPC_INB_GET_NVMD_DATA; 4183 u32 nvmd_type; 4184 int rc; 4185 u32 tag; 4186 struct pm8001_ccb_info *ccb; 4187 struct inbound_queue_table *circularQ; 4188 struct get_nvm_data_req nvmd_req; 4189 struct fw_control_ex *fw_control_context; 4190 struct pm8001_ioctl_payload *ioctl_payload = payload; 4191 4192 nvmd_type = ioctl_payload->minor_function; 4193 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); 4194 if (!fw_control_context) 4195 return -ENOMEM; 4196 fw_control_context->usrAddr = (u8 *)&ioctl_payload->func_specific[0]; 4197 fw_control_context->len = ioctl_payload->length; 4198 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4199 memset(&nvmd_req, 0, sizeof(nvmd_req)); 4200 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4201 if (rc) { 4202 kfree(fw_control_context); 4203 return rc; 4204 } 4205 ccb = &pm8001_ha->ccb_info[tag]; 4206 ccb->ccb_tag = tag; 4207 ccb->fw_control_context = fw_control_context; 4208 nvmd_req.tag = cpu_to_le32(tag); 4209 4210 switch (nvmd_type) { 4211 case TWI_DEVICE: { 4212 u32 twi_addr, twi_page_size; 4213 twi_addr = 0xa8; 4214 twi_page_size = 2; 4215 4216 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 | 4217 twi_page_size << 8 | TWI_DEVICE); 4218 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4219 nvmd_req.resp_addr_hi = 4220 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4221 nvmd_req.resp_addr_lo = 4222 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4223 break; 4224 } 4225 case C_SEEPROM: { 4226 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM); 4227 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4228 nvmd_req.resp_addr_hi = 4229 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4230 nvmd_req.resp_addr_lo = 4231 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4232 break; 4233 } 4234 case VPD_FLASH: { 4235 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH); 4236 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4237 nvmd_req.resp_addr_hi = 4238 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4239 nvmd_req.resp_addr_lo = 4240 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4241 break; 4242 } 4243 case EXPAN_ROM: { 4244 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM); 4245 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4246 nvmd_req.resp_addr_hi = 4247 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4248 nvmd_req.resp_addr_lo = 4249 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4250 break; 4251 } 4252 default: 4253 break; 4254 } 4255 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req); 4256 return rc; 4257 } 4258 4259 static int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha, 4260 void *payload) 4261 { 4262 u32 opc = OPC_INB_SET_NVMD_DATA; 4263 u32 nvmd_type; 4264 int rc; 4265 u32 tag; 4266 struct pm8001_ccb_info *ccb; 4267 struct inbound_queue_table *circularQ; 4268 struct set_nvm_data_req nvmd_req; 4269 struct fw_control_ex *fw_control_context; 4270 struct pm8001_ioctl_payload *ioctl_payload = payload; 4271 4272 nvmd_type = ioctl_payload->minor_function; 4273 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); 4274 if (!fw_control_context) 4275 return -ENOMEM; 4276 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4277 memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr, 4278 ioctl_payload->func_specific, 4279 ioctl_payload->length); 4280 memset(&nvmd_req, 0, sizeof(nvmd_req)); 4281 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4282 if (rc) { 4283 kfree(fw_control_context); 4284 return rc; 4285 } 4286 ccb = &pm8001_ha->ccb_info[tag]; 4287 ccb->fw_control_context = fw_control_context; 4288 ccb->ccb_tag = tag; 4289 nvmd_req.tag = cpu_to_le32(tag); 4290 switch (nvmd_type) { 4291 case TWI_DEVICE: { 4292 u32 twi_addr, twi_page_size; 4293 twi_addr = 0xa8; 4294 twi_page_size = 2; 4295 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4296 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 | 4297 twi_page_size << 8 | TWI_DEVICE); 4298 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4299 nvmd_req.resp_addr_hi = 4300 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4301 nvmd_req.resp_addr_lo = 4302 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4303 break; 4304 } 4305 case C_SEEPROM: 4306 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM); 4307 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4308 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4309 nvmd_req.resp_addr_hi = 4310 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4311 nvmd_req.resp_addr_lo = 4312 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4313 break; 4314 case VPD_FLASH: 4315 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH); 4316 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4317 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4318 nvmd_req.resp_addr_hi = 4319 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4320 nvmd_req.resp_addr_lo = 4321 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4322 break; 4323 case EXPAN_ROM: 4324 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM); 4325 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4326 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4327 nvmd_req.resp_addr_hi = 4328 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4329 nvmd_req.resp_addr_lo = 4330 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4331 break; 4332 default: 4333 break; 4334 } 4335 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req); 4336 return rc; 4337 } 4338 4339 /** 4340 * pm8001_chip_fw_flash_update_build - support the firmware update operation 4341 * @pm8001_ha: our hba card information. 4342 * @fw_flash_updata_info: firmware flash update param 4343 */ 4344 static int 4345 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha, 4346 void *fw_flash_updata_info, u32 tag) 4347 { 4348 struct fw_flash_Update_req payload; 4349 struct fw_flash_updata_info *info; 4350 struct inbound_queue_table *circularQ; 4351 int ret; 4352 u32 opc = OPC_INB_FW_FLASH_UPDATE; 4353 4354 memset(&payload, 0, sizeof(struct fw_flash_Update_req)); 4355 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4356 info = fw_flash_updata_info; 4357 payload.tag = cpu_to_le32(tag); 4358 payload.cur_image_len = cpu_to_le32(info->cur_image_len); 4359 payload.cur_image_offset = cpu_to_le32(info->cur_image_offset); 4360 payload.total_image_len = cpu_to_le32(info->total_image_len); 4361 payload.len = info->sgl.im_len.len ; 4362 payload.sgl_addr_lo = lower_32_bits(info->sgl.addr); 4363 payload.sgl_addr_hi = upper_32_bits(info->sgl.addr); 4364 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload); 4365 return ret; 4366 } 4367 4368 static int 4369 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha, 4370 void *payload) 4371 { 4372 struct fw_flash_updata_info flash_update_info; 4373 struct fw_control_info *fw_control; 4374 struct fw_control_ex *fw_control_context; 4375 int rc; 4376 u32 tag; 4377 struct pm8001_ccb_info *ccb; 4378 void *buffer = NULL; 4379 dma_addr_t phys_addr; 4380 u32 phys_addr_hi; 4381 u32 phys_addr_lo; 4382 struct pm8001_ioctl_payload *ioctl_payload = payload; 4383 4384 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); 4385 if (!fw_control_context) 4386 return -ENOMEM; 4387 fw_control = (struct fw_control_info *)&ioctl_payload->func_specific[0]; 4388 if (fw_control->len != 0) { 4389 if (pm8001_mem_alloc(pm8001_ha->pdev, 4390 (void **)&buffer, 4391 &phys_addr, 4392 &phys_addr_hi, 4393 &phys_addr_lo, 4394 fw_control->len, 0) != 0) { 4395 PM8001_FAIL_DBG(pm8001_ha, 4396 pm8001_printk("Mem alloc failure\n")); 4397 kfree(fw_control_context); 4398 return -ENOMEM; 4399 } 4400 } 4401 memcpy(buffer, fw_control->buffer, fw_control->len); 4402 flash_update_info.sgl.addr = cpu_to_le64(phys_addr); 4403 flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len); 4404 flash_update_info.sgl.im_len.e = 0; 4405 flash_update_info.cur_image_offset = fw_control->offset; 4406 flash_update_info.cur_image_len = fw_control->len; 4407 flash_update_info.total_image_len = fw_control->size; 4408 fw_control_context->fw_control = fw_control; 4409 fw_control_context->virtAddr = buffer; 4410 fw_control_context->len = fw_control->len; 4411 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4412 if (rc) { 4413 kfree(fw_control_context); 4414 return rc; 4415 } 4416 ccb = &pm8001_ha->ccb_info[tag]; 4417 ccb->fw_control_context = fw_control_context; 4418 ccb->ccb_tag = tag; 4419 rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info, 4420 tag); 4421 return rc; 4422 } 4423 4424 static int 4425 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha, 4426 struct pm8001_device *pm8001_dev, u32 state) 4427 { 4428 struct set_dev_state_req payload; 4429 struct inbound_queue_table *circularQ; 4430 struct pm8001_ccb_info *ccb; 4431 int rc; 4432 u32 tag; 4433 u32 opc = OPC_INB_SET_DEVICE_STATE; 4434 memset(&payload, 0, sizeof(payload)); 4435 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4436 if (rc) 4437 return -1; 4438 ccb = &pm8001_ha->ccb_info[tag]; 4439 ccb->ccb_tag = tag; 4440 ccb->device = pm8001_dev; 4441 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4442 payload.tag = cpu_to_le32(tag); 4443 payload.device_id = cpu_to_le32(pm8001_dev->device_id); 4444 payload.nds = cpu_to_le32(state); 4445 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload); 4446 return rc; 4447 4448 } 4449 4450 static int 4451 pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha) 4452 { 4453 struct sas_re_initialization_req payload; 4454 struct inbound_queue_table *circularQ; 4455 struct pm8001_ccb_info *ccb; 4456 int rc; 4457 u32 tag; 4458 u32 opc = OPC_INB_SAS_RE_INITIALIZE; 4459 memset(&payload, 0, sizeof(payload)); 4460 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4461 if (rc) 4462 return -1; 4463 ccb = &pm8001_ha->ccb_info[tag]; 4464 ccb->ccb_tag = tag; 4465 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4466 payload.tag = cpu_to_le32(tag); 4467 payload.SSAHOLT = cpu_to_le32(0xd << 25); 4468 payload.sata_hol_tmo = cpu_to_le32(80); 4469 payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff); 4470 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload); 4471 return rc; 4472 4473 } 4474 4475 const struct pm8001_dispatch pm8001_8001_dispatch = { 4476 .name = "pmc8001", 4477 .chip_init = pm8001_chip_init, 4478 .chip_soft_rst = pm8001_chip_soft_rst, 4479 .chip_rst = pm8001_hw_chip_rst, 4480 .chip_iounmap = pm8001_chip_iounmap, 4481 .isr = pm8001_chip_isr, 4482 .is_our_interupt = pm8001_chip_is_our_interupt, 4483 .isr_process_oq = process_oq, 4484 .interrupt_enable = pm8001_chip_interrupt_enable, 4485 .interrupt_disable = pm8001_chip_interrupt_disable, 4486 .make_prd = pm8001_chip_make_sg, 4487 .smp_req = pm8001_chip_smp_req, 4488 .ssp_io_req = pm8001_chip_ssp_io_req, 4489 .sata_req = pm8001_chip_sata_req, 4490 .phy_start_req = pm8001_chip_phy_start_req, 4491 .phy_stop_req = pm8001_chip_phy_stop_req, 4492 .reg_dev_req = pm8001_chip_reg_dev_req, 4493 .dereg_dev_req = pm8001_chip_dereg_dev_req, 4494 .phy_ctl_req = pm8001_chip_phy_ctl_req, 4495 .task_abort = pm8001_chip_abort_task, 4496 .ssp_tm_req = pm8001_chip_ssp_tm_req, 4497 .get_nvmd_req = pm8001_chip_get_nvmd_req, 4498 .set_nvmd_req = pm8001_chip_set_nvmd_req, 4499 .fw_flash_update_req = pm8001_chip_fw_flash_update_req, 4500 .set_dev_state_req = pm8001_chip_set_dev_state_req, 4501 .sas_re_init_req = pm8001_chip_sas_re_initialization, 4502 }; 4503 4504