1 /* 2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 USI Co., Ltd. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 #include <linux/slab.h> 41 #include "pm8001_sas.h" 42 #include "pm8001_hwi.h" 43 #include "pm8001_chips.h" 44 #include "pm8001_ctl.h" 45 #include "pm80xx_tracepoints.h" 46 47 /** 48 * read_main_config_table - read the configure table and save it. 49 * @pm8001_ha: our hba card information 50 */ 51 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha) 52 { 53 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 54 pm8001_ha->main_cfg_tbl.pm8001_tbl.signature = 55 pm8001_mr32(address, 0x00); 56 pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev = 57 pm8001_mr32(address, 0x04); 58 pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev = 59 pm8001_mr32(address, 0x08); 60 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io = 61 pm8001_mr32(address, 0x0C); 62 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl = 63 pm8001_mr32(address, 0x10); 64 pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag = 65 pm8001_mr32(address, 0x14); 66 pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset = 67 pm8001_mr32(address, 0x18); 68 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset = 69 pm8001_mr32(address, MAIN_IBQ_OFFSET); 70 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset = 71 pm8001_mr32(address, MAIN_OBQ_OFFSET); 72 pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag = 73 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET); 74 75 /* read analog Setting offset from the configuration table */ 76 pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset = 77 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET); 78 79 /* read Error Dump Offset and Length */ 80 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 = 81 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET); 82 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 = 83 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH); 84 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 = 85 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET); 86 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 = 87 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH); 88 } 89 90 /** 91 * read_general_status_table - read the general status table and save it. 92 * @pm8001_ha: our hba card information 93 */ 94 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha) 95 { 96 void __iomem *address = pm8001_ha->general_stat_tbl_addr; 97 pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate = 98 pm8001_mr32(address, 0x00); 99 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0 = 100 pm8001_mr32(address, 0x04); 101 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1 = 102 pm8001_mr32(address, 0x08); 103 pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt = 104 pm8001_mr32(address, 0x0C); 105 pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt = 106 pm8001_mr32(address, 0x10); 107 pm8001_ha->gs_tbl.pm8001_tbl.rsvd = 108 pm8001_mr32(address, 0x14); 109 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0] = 110 pm8001_mr32(address, 0x18); 111 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1] = 112 pm8001_mr32(address, 0x1C); 113 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2] = 114 pm8001_mr32(address, 0x20); 115 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3] = 116 pm8001_mr32(address, 0x24); 117 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4] = 118 pm8001_mr32(address, 0x28); 119 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5] = 120 pm8001_mr32(address, 0x2C); 121 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6] = 122 pm8001_mr32(address, 0x30); 123 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7] = 124 pm8001_mr32(address, 0x34); 125 pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val = 126 pm8001_mr32(address, 0x38); 127 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0] = 128 pm8001_mr32(address, 0x3C); 129 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1] = 130 pm8001_mr32(address, 0x40); 131 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0] = 132 pm8001_mr32(address, 0x44); 133 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1] = 134 pm8001_mr32(address, 0x48); 135 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2] = 136 pm8001_mr32(address, 0x4C); 137 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3] = 138 pm8001_mr32(address, 0x50); 139 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4] = 140 pm8001_mr32(address, 0x54); 141 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5] = 142 pm8001_mr32(address, 0x58); 143 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6] = 144 pm8001_mr32(address, 0x5C); 145 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7] = 146 pm8001_mr32(address, 0x60); 147 } 148 149 /** 150 * read_inbnd_queue_table - read the inbound queue table and save it. 151 * @pm8001_ha: our hba card information 152 */ 153 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 154 { 155 int i; 156 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 157 for (i = 0; i < PM8001_MAX_INB_NUM; i++) { 158 u32 offset = i * 0x20; 159 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 160 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14))); 161 pm8001_ha->inbnd_q_tbl[i].pi_offset = 162 pm8001_mr32(address, (offset + 0x18)); 163 } 164 } 165 166 /** 167 * read_outbnd_queue_table - read the outbound queue table and save it. 168 * @pm8001_ha: our hba card information 169 */ 170 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 171 { 172 int i; 173 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 174 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) { 175 u32 offset = i * 0x24; 176 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 177 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14))); 178 pm8001_ha->outbnd_q_tbl[i].ci_offset = 179 pm8001_mr32(address, (offset + 0x18)); 180 } 181 } 182 183 /** 184 * init_default_table_values - init the default table. 185 * @pm8001_ha: our hba card information 186 */ 187 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha) 188 { 189 int i; 190 u32 offsetib, offsetob; 191 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr; 192 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr; 193 u32 ib_offset = pm8001_ha->ib_offset; 194 u32 ob_offset = pm8001_ha->ob_offset; 195 u32 ci_offset = pm8001_ha->ci_offset; 196 u32 pi_offset = pm8001_ha->pi_offset; 197 198 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd = 0; 199 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3 = 0; 200 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7 = 0; 201 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3 = 0; 202 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7 = 0; 203 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 = 204 0; 205 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 = 206 0; 207 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0; 208 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0; 209 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0; 210 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0; 211 212 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr = 213 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi; 214 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr = 215 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo; 216 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size = 217 PM8001_EVENT_LOG_SIZE; 218 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option = 0x01; 219 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr = 220 pm8001_ha->memoryMap.region[IOP].phys_addr_hi; 221 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr = 222 pm8001_ha->memoryMap.region[IOP].phys_addr_lo; 223 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size = 224 PM8001_EVENT_LOG_SIZE; 225 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option = 0x01; 226 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt = 0x01; 227 for (i = 0; i < pm8001_ha->max_q_num; i++) { 228 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt = 229 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30); 230 pm8001_ha->inbnd_q_tbl[i].upper_base_addr = 231 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi; 232 pm8001_ha->inbnd_q_tbl[i].lower_base_addr = 233 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo; 234 pm8001_ha->inbnd_q_tbl[i].base_virt = 235 (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr; 236 pm8001_ha->inbnd_q_tbl[i].total_length = 237 pm8001_ha->memoryMap.region[ib_offset + i].total_len; 238 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr = 239 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi; 240 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr = 241 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo; 242 pm8001_ha->inbnd_q_tbl[i].ci_virt = 243 pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr; 244 pm8001_write_32(pm8001_ha->inbnd_q_tbl[i].ci_virt, 0, 0); 245 offsetib = i * 0x20; 246 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 247 get_pci_bar_index(pm8001_mr32(addressib, 248 (offsetib + 0x14))); 249 pm8001_ha->inbnd_q_tbl[i].pi_offset = 250 pm8001_mr32(addressib, (offsetib + 0x18)); 251 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0; 252 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0; 253 } 254 for (i = 0; i < pm8001_ha->max_q_num; i++) { 255 pm8001_ha->outbnd_q_tbl[i].element_size_cnt = 256 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30); 257 pm8001_ha->outbnd_q_tbl[i].upper_base_addr = 258 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi; 259 pm8001_ha->outbnd_q_tbl[i].lower_base_addr = 260 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo; 261 pm8001_ha->outbnd_q_tbl[i].base_virt = 262 (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr; 263 pm8001_ha->outbnd_q_tbl[i].total_length = 264 pm8001_ha->memoryMap.region[ob_offset + i].total_len; 265 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr = 266 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi; 267 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr = 268 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo; 269 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = 270 0 | (10 << 16) | (i << 24); 271 pm8001_ha->outbnd_q_tbl[i].pi_virt = 272 pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr; 273 pm8001_write_32(pm8001_ha->outbnd_q_tbl[i].pi_virt, 0, 0); 274 offsetob = i * 0x24; 275 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 276 get_pci_bar_index(pm8001_mr32(addressob, 277 offsetob + 0x14)); 278 pm8001_ha->outbnd_q_tbl[i].ci_offset = 279 pm8001_mr32(addressob, (offsetob + 0x18)); 280 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0; 281 pm8001_ha->outbnd_q_tbl[i].producer_index = 0; 282 } 283 } 284 285 /** 286 * update_main_config_table - update the main default table to the HBA. 287 * @pm8001_ha: our hba card information 288 */ 289 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha) 290 { 291 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 292 pm8001_mw32(address, 0x24, 293 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd); 294 pm8001_mw32(address, 0x28, 295 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3); 296 pm8001_mw32(address, 0x2C, 297 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7); 298 pm8001_mw32(address, 0x30, 299 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3); 300 pm8001_mw32(address, 0x34, 301 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7); 302 pm8001_mw32(address, 0x38, 303 pm8001_ha->main_cfg_tbl.pm8001_tbl. 304 outbound_tgt_ITNexus_event_pid0_3); 305 pm8001_mw32(address, 0x3C, 306 pm8001_ha->main_cfg_tbl.pm8001_tbl. 307 outbound_tgt_ITNexus_event_pid4_7); 308 pm8001_mw32(address, 0x40, 309 pm8001_ha->main_cfg_tbl.pm8001_tbl. 310 outbound_tgt_ssp_event_pid0_3); 311 pm8001_mw32(address, 0x44, 312 pm8001_ha->main_cfg_tbl.pm8001_tbl. 313 outbound_tgt_ssp_event_pid4_7); 314 pm8001_mw32(address, 0x48, 315 pm8001_ha->main_cfg_tbl.pm8001_tbl. 316 outbound_tgt_smp_event_pid0_3); 317 pm8001_mw32(address, 0x4C, 318 pm8001_ha->main_cfg_tbl.pm8001_tbl. 319 outbound_tgt_smp_event_pid4_7); 320 pm8001_mw32(address, 0x50, 321 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr); 322 pm8001_mw32(address, 0x54, 323 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr); 324 pm8001_mw32(address, 0x58, 325 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size); 326 pm8001_mw32(address, 0x5C, 327 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option); 328 pm8001_mw32(address, 0x60, 329 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr); 330 pm8001_mw32(address, 0x64, 331 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr); 332 pm8001_mw32(address, 0x68, 333 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size); 334 pm8001_mw32(address, 0x6C, 335 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option); 336 pm8001_mw32(address, 0x70, 337 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt); 338 } 339 340 /** 341 * update_inbnd_queue_table - update the inbound queue table to the HBA. 342 * @pm8001_ha: our hba card information 343 * @number: entry in the queue 344 */ 345 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 346 int number) 347 { 348 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 349 u16 offset = number * 0x20; 350 pm8001_mw32(address, offset + 0x00, 351 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); 352 pm8001_mw32(address, offset + 0x04, 353 pm8001_ha->inbnd_q_tbl[number].upper_base_addr); 354 pm8001_mw32(address, offset + 0x08, 355 pm8001_ha->inbnd_q_tbl[number].lower_base_addr); 356 pm8001_mw32(address, offset + 0x0C, 357 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr); 358 pm8001_mw32(address, offset + 0x10, 359 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); 360 } 361 362 /** 363 * update_outbnd_queue_table - update the outbound queue table to the HBA. 364 * @pm8001_ha: our hba card information 365 * @number: entry in the queue 366 */ 367 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 368 int number) 369 { 370 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 371 u16 offset = number * 0x24; 372 pm8001_mw32(address, offset + 0x00, 373 pm8001_ha->outbnd_q_tbl[number].element_size_cnt); 374 pm8001_mw32(address, offset + 0x04, 375 pm8001_ha->outbnd_q_tbl[number].upper_base_addr); 376 pm8001_mw32(address, offset + 0x08, 377 pm8001_ha->outbnd_q_tbl[number].lower_base_addr); 378 pm8001_mw32(address, offset + 0x0C, 379 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr); 380 pm8001_mw32(address, offset + 0x10, 381 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); 382 pm8001_mw32(address, offset + 0x1C, 383 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay); 384 } 385 386 /** 387 * pm8001_bar4_shift - function is called to shift BAR base address 388 * @pm8001_ha : our hba card information 389 * @shiftValue : shifting value in memory bar. 390 */ 391 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue) 392 { 393 u32 regVal; 394 unsigned long start; 395 396 /* program the inbound AXI translation Lower Address */ 397 pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue); 398 399 /* confirm the setting is written */ 400 start = jiffies + HZ; /* 1 sec */ 401 do { 402 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW); 403 } while ((regVal != shiftValue) && time_before(jiffies, start)); 404 405 if (regVal != shiftValue) { 406 pm8001_dbg(pm8001_ha, INIT, 407 "TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW = 0x%x\n", 408 regVal); 409 return -1; 410 } 411 return 0; 412 } 413 414 /** 415 * mpi_set_phys_g3_with_ssc 416 * @pm8001_ha: our hba card information 417 * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc. 418 */ 419 static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha, 420 u32 SSCbit) 421 { 422 u32 offset, i; 423 unsigned long flags; 424 425 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000 426 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000 427 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074 428 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074 429 #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12 430 #define PHY_G3_WITH_SSC_BIT_SHIFT 13 431 #define SNW3_PHY_CAPABILITIES_PARITY 31 432 433 /* 434 * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3) 435 * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7) 436 */ 437 spin_lock_irqsave(&pm8001_ha->lock, flags); 438 if (-1 == pm8001_bar4_shift(pm8001_ha, 439 SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) { 440 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 441 return; 442 } 443 444 for (i = 0; i < 4; i++) { 445 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i; 446 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501); 447 } 448 /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */ 449 if (-1 == pm8001_bar4_shift(pm8001_ha, 450 SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) { 451 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 452 return; 453 } 454 for (i = 4; i < 8; i++) { 455 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4); 456 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501); 457 } 458 /************************************************************* 459 Change the SSC upspreading value to 0x0 so that upspreading is disabled. 460 Device MABC SMOD0 Controls 461 Address: (via MEMBASE-III): 462 Using shifted destination address 0x0_0000: with Offset 0xD8 463 464 31:28 R/W Reserved Do not change 465 27:24 R/W SAS_SMOD_SPRDUP 0000 466 23:20 R/W SAS_SMOD_SPRDDN 0000 467 19:0 R/W Reserved Do not change 468 Upon power-up this register will read as 0x8990c016, 469 and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000 470 so that the written value will be 0x8090c016. 471 This will ensure only down-spreading SSC is enabled on the SPC. 472 *************************************************************/ 473 pm8001_cr32(pm8001_ha, 2, 0xd8); 474 pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016); 475 476 /*set the shifted destination address to 0x0 to avoid error operation */ 477 pm8001_bar4_shift(pm8001_ha, 0x0); 478 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 479 return; 480 } 481 482 /** 483 * mpi_set_open_retry_interval_reg 484 * @pm8001_ha: our hba card information 485 * @interval: interval time for each OPEN_REJECT (RETRY). The units are in 1us. 486 */ 487 static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha, 488 u32 interval) 489 { 490 u32 offset; 491 u32 value; 492 u32 i; 493 unsigned long flags; 494 495 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000 496 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000 497 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4 498 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4 499 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF 500 501 value = interval & OPEN_RETRY_INTERVAL_REG_MASK; 502 spin_lock_irqsave(&pm8001_ha->lock, flags); 503 /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/ 504 if (-1 == pm8001_bar4_shift(pm8001_ha, 505 OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) { 506 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 507 return; 508 } 509 for (i = 0; i < 4; i++) { 510 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i; 511 pm8001_cw32(pm8001_ha, 2, offset, value); 512 } 513 514 if (-1 == pm8001_bar4_shift(pm8001_ha, 515 OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) { 516 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 517 return; 518 } 519 for (i = 4; i < 8; i++) { 520 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4); 521 pm8001_cw32(pm8001_ha, 2, offset, value); 522 } 523 /*set the shifted destination address to 0x0 to avoid error operation */ 524 pm8001_bar4_shift(pm8001_ha, 0x0); 525 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 526 return; 527 } 528 529 /** 530 * mpi_init_check - check firmware initialization status. 531 * @pm8001_ha: our hba card information 532 */ 533 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha) 534 { 535 u32 max_wait_count; 536 u32 value; 537 u32 gst_len_mpistate; 538 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the 539 table is updated */ 540 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE); 541 /* wait until Inbound DoorBell Clear Register toggled */ 542 max_wait_count = 1 * 1000 * 1000;/* 1 sec */ 543 do { 544 udelay(1); 545 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 546 value &= SPC_MSGU_CFG_TABLE_UPDATE; 547 } while ((value != 0) && (--max_wait_count)); 548 549 if (!max_wait_count) 550 return -1; 551 /* check the MPI-State for initialization */ 552 gst_len_mpistate = 553 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 554 GST_GSTLEN_MPIS_OFFSET); 555 if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK)) 556 return -1; 557 /* check MPI Initialization error */ 558 gst_len_mpistate = gst_len_mpistate >> 16; 559 if (0x0000 != gst_len_mpistate) 560 return -1; 561 return 0; 562 } 563 564 /** 565 * check_fw_ready - The LLDD check if the FW is ready, if not, return error. 566 * @pm8001_ha: our hba card information 567 */ 568 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha) 569 { 570 u32 value, value1; 571 u32 max_wait_count; 572 /* check error state */ 573 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 574 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 575 /* check AAP error */ 576 if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) { 577 /* error state */ 578 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 579 return -1; 580 } 581 582 /* check IOP error */ 583 if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) { 584 /* error state */ 585 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 586 return -1; 587 } 588 589 /* bit 4-31 of scratch pad1 should be zeros if it is not 590 in error state*/ 591 if (value & SCRATCH_PAD1_STATE_MASK) { 592 /* error case */ 593 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 594 return -1; 595 } 596 597 /* bit 2, 4-31 of scratch pad2 should be zeros if it is not 598 in error state */ 599 if (value1 & SCRATCH_PAD2_STATE_MASK) { 600 /* error case */ 601 return -1; 602 } 603 604 max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */ 605 606 /* wait until scratch pad 1 and 2 registers in ready state */ 607 do { 608 udelay(1); 609 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) 610 & SCRATCH_PAD1_RDY; 611 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) 612 & SCRATCH_PAD2_RDY; 613 if ((--max_wait_count) == 0) 614 return -1; 615 } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY)); 616 return 0; 617 } 618 619 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha) 620 { 621 void __iomem *base_addr; 622 u32 value; 623 u32 offset; 624 u32 pcibar; 625 u32 pcilogic; 626 627 value = pm8001_cr32(pm8001_ha, 0, 0x44); 628 offset = value & 0x03FFFFFF; 629 pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 Offset: %x\n", offset); 630 pcilogic = (value & 0xFC000000) >> 26; 631 pcibar = get_pci_bar_index(pcilogic); 632 pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar); 633 pm8001_ha->main_cfg_tbl_addr = base_addr = 634 pm8001_ha->io_mem[pcibar].memvirtaddr + offset; 635 pm8001_ha->general_stat_tbl_addr = 636 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18); 637 pm8001_ha->inbnd_q_tbl_addr = 638 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C); 639 pm8001_ha->outbnd_q_tbl_addr = 640 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20); 641 } 642 643 /** 644 * pm8001_chip_init - the main init function that initialize whole PM8001 chip. 645 * @pm8001_ha: our hba card information 646 */ 647 static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha) 648 { 649 u32 i = 0; 650 u16 deviceid; 651 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid); 652 /* 8081 controllers need BAR shift to access MPI space 653 * as this is shared with BIOS data */ 654 if (deviceid == 0x8081 || deviceid == 0x0042) { 655 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) { 656 pm8001_dbg(pm8001_ha, FAIL, 657 "Shift Bar4 to 0x%x failed\n", 658 GSM_SM_BASE); 659 return -1; 660 } 661 } 662 /* check the firmware status */ 663 if (-1 == check_fw_ready(pm8001_ha)) { 664 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n"); 665 return -EBUSY; 666 } 667 668 /* Initialize pci space address eg: mpi offset */ 669 init_pci_device_addresses(pm8001_ha); 670 init_default_table_values(pm8001_ha); 671 read_main_config_table(pm8001_ha); 672 read_general_status_table(pm8001_ha); 673 read_inbnd_queue_table(pm8001_ha); 674 read_outbnd_queue_table(pm8001_ha); 675 /* update main config table ,inbound table and outbound table */ 676 update_main_config_table(pm8001_ha); 677 for (i = 0; i < pm8001_ha->max_q_num; i++) 678 update_inbnd_queue_table(pm8001_ha, i); 679 for (i = 0; i < pm8001_ha->max_q_num; i++) 680 update_outbnd_queue_table(pm8001_ha, i); 681 /* 8081 controller donot require these operations */ 682 if (deviceid != 0x8081 && deviceid != 0x0042) { 683 mpi_set_phys_g3_with_ssc(pm8001_ha, 0); 684 /* 7->130ms, 34->500ms, 119->1.5s */ 685 mpi_set_open_retry_interval_reg(pm8001_ha, 119); 686 } 687 /* notify firmware update finished and check initialization status */ 688 if (0 == mpi_init_check(pm8001_ha)) { 689 pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n"); 690 } else 691 return -EBUSY; 692 /*This register is a 16-bit timer with a resolution of 1us. This is the 693 timer used for interrupt delay/coalescing in the PCIe Application Layer. 694 Zero is not a valid value. A value of 1 in the register will cause the 695 interrupts to be normal. A value greater than 1 will cause coalescing 696 delays.*/ 697 pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1); 698 pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0); 699 return 0; 700 } 701 702 static void pm8001_chip_post_init(struct pm8001_hba_info *pm8001_ha) 703 { 704 } 705 706 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha) 707 { 708 u32 max_wait_count; 709 u32 value; 710 u32 gst_len_mpistate; 711 u16 deviceid; 712 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid); 713 if (deviceid == 0x8081 || deviceid == 0x0042) { 714 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) { 715 pm8001_dbg(pm8001_ha, FAIL, 716 "Shift Bar4 to 0x%x failed\n", 717 GSM_SM_BASE); 718 return -1; 719 } 720 } 721 init_pci_device_addresses(pm8001_ha); 722 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the 723 table is stop */ 724 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET); 725 726 /* wait until Inbound DoorBell Clear Register toggled */ 727 max_wait_count = 1 * 1000 * 1000;/* 1 sec */ 728 do { 729 udelay(1); 730 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 731 value &= SPC_MSGU_CFG_TABLE_RESET; 732 } while ((value != 0) && (--max_wait_count)); 733 734 if (!max_wait_count) { 735 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=0x%x\n", 736 value); 737 return -1; 738 } 739 740 /* check the MPI-State for termination in progress */ 741 /* wait until Inbound DoorBell Clear Register toggled */ 742 max_wait_count = 1 * 1000 * 1000; /* 1 sec */ 743 do { 744 udelay(1); 745 gst_len_mpistate = 746 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 747 GST_GSTLEN_MPIS_OFFSET); 748 if (GST_MPI_STATE_UNINIT == 749 (gst_len_mpistate & GST_MPI_STATE_MASK)) 750 break; 751 } while (--max_wait_count); 752 if (!max_wait_count) { 753 pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n", 754 gst_len_mpistate & GST_MPI_STATE_MASK); 755 return -1; 756 } 757 return 0; 758 } 759 760 /** 761 * soft_reset_ready_check - Function to check FW is ready for soft reset. 762 * @pm8001_ha: our hba card information 763 */ 764 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha) 765 { 766 u32 regVal, regVal1, regVal2; 767 if (mpi_uninit_check(pm8001_ha) != 0) { 768 pm8001_dbg(pm8001_ha, FAIL, "MPI state is not ready\n"); 769 return -1; 770 } 771 /* read the scratch pad 2 register bit 2 */ 772 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) 773 & SCRATCH_PAD2_FWRDY_RST; 774 if (regVal == SCRATCH_PAD2_FWRDY_RST) { 775 pm8001_dbg(pm8001_ha, INIT, "Firmware is ready for reset.\n"); 776 } else { 777 unsigned long flags; 778 /* Trigger NMI twice via RB6 */ 779 spin_lock_irqsave(&pm8001_ha->lock, flags); 780 if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) { 781 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 782 pm8001_dbg(pm8001_ha, FAIL, 783 "Shift Bar4 to 0x%x failed\n", 784 RB6_ACCESS_REG); 785 return -1; 786 } 787 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, 788 RB6_MAGIC_NUMBER_RST); 789 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST); 790 /* wait for 100 ms */ 791 mdelay(100); 792 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) & 793 SCRATCH_PAD2_FWRDY_RST; 794 if (regVal != SCRATCH_PAD2_FWRDY_RST) { 795 regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 796 regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 797 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MSGU_SCRATCH_PAD1=0x%x, MSGU_SCRATCH_PAD2=0x%x\n", 798 regVal1, regVal2); 799 pm8001_dbg(pm8001_ha, FAIL, 800 "SCRATCH_PAD0 value = 0x%x\n", 801 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)); 802 pm8001_dbg(pm8001_ha, FAIL, 803 "SCRATCH_PAD3 value = 0x%x\n", 804 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)); 805 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 806 return -1; 807 } 808 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 809 } 810 return 0; 811 } 812 813 /** 814 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all 815 * the FW register status to the originated status. 816 * @pm8001_ha: our hba card information 817 */ 818 static int 819 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha) 820 { 821 u32 regVal, toggleVal; 822 u32 max_wait_count; 823 u32 regVal1, regVal2, regVal3; 824 u32 signature = 0x252acbcd; /* for host scratch pad0 */ 825 unsigned long flags; 826 827 /* step1: Check FW is ready for soft reset */ 828 if (soft_reset_ready_check(pm8001_ha) != 0) { 829 pm8001_dbg(pm8001_ha, FAIL, "FW is not ready\n"); 830 return -1; 831 } 832 833 /* step 2: clear NMI status register on AAP1 and IOP, write the same 834 value to clear */ 835 /* map 0x60000 to BAR4(0x20), BAR2(win) */ 836 spin_lock_irqsave(&pm8001_ha->lock, flags); 837 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) { 838 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 839 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n", 840 MBIC_AAP1_ADDR_BASE); 841 return -1; 842 } 843 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP); 844 pm8001_dbg(pm8001_ha, INIT, "MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", 845 regVal); 846 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0); 847 /* map 0x70000 to BAR4(0x20), BAR2(win) */ 848 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) { 849 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 850 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n", 851 MBIC_IOP_ADDR_BASE); 852 return -1; 853 } 854 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1); 855 pm8001_dbg(pm8001_ha, INIT, "MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", 856 regVal); 857 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0); 858 859 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE); 860 pm8001_dbg(pm8001_ha, INIT, "PCIE -Event Interrupt Enable = 0x%x\n", 861 regVal); 862 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0); 863 864 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT); 865 pm8001_dbg(pm8001_ha, INIT, "PCIE - Event Interrupt = 0x%x\n", 866 regVal); 867 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal); 868 869 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE); 870 pm8001_dbg(pm8001_ha, INIT, "PCIE -Error Interrupt Enable = 0x%x\n", 871 regVal); 872 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0); 873 874 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT); 875 pm8001_dbg(pm8001_ha, INIT, "PCIE - Error Interrupt = 0x%x\n", regVal); 876 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal); 877 878 /* read the scratch pad 1 register bit 2 */ 879 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) 880 & SCRATCH_PAD1_RST; 881 toggleVal = regVal ^ SCRATCH_PAD1_RST; 882 883 /* set signature in host scratch pad0 register to tell SPC that the 884 host performs the soft reset */ 885 pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature); 886 887 /* read required registers for confirmming */ 888 /* map 0x0700000 to BAR4(0x20), BAR2(win) */ 889 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) { 890 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 891 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n", 892 GSM_ADDR_BASE); 893 return -1; 894 } 895 pm8001_dbg(pm8001_ha, INIT, 896 "GSM 0x0(0x00007b88)-GSM Configuration and Reset = 0x%x\n", 897 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)); 898 899 /* step 3: host read GSM Configuration and Reset register */ 900 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); 901 /* Put those bits to low */ 902 /* GSM XCBI offset = 0x70 0000 903 0x00 Bit 13 COM_SLV_SW_RSTB 1 904 0x00 Bit 12 QSSP_SW_RSTB 1 905 0x00 Bit 11 RAAE_SW_RSTB 1 906 0x00 Bit 9 RB_1_SW_RSTB 1 907 0x00 Bit 8 SM_SW_RSTB 1 908 */ 909 regVal &= ~(0x00003b00); 910 /* host write GSM Configuration and Reset register */ 911 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); 912 pm8001_dbg(pm8001_ha, INIT, 913 "GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM Configuration and Reset is set to = 0x%x\n", 914 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)); 915 916 /* step 4: */ 917 /* disable GSM - Read Address Parity Check */ 918 regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK); 919 pm8001_dbg(pm8001_ha, INIT, 920 "GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n", 921 regVal1); 922 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0); 923 pm8001_dbg(pm8001_ha, INIT, 924 "GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n", 925 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)); 926 927 /* disable GSM - Write Address Parity Check */ 928 regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK); 929 pm8001_dbg(pm8001_ha, INIT, 930 "GSM 0x700040 - Write Address Parity Check Enable = 0x%x\n", 931 regVal2); 932 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0); 933 pm8001_dbg(pm8001_ha, INIT, 934 "GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n", 935 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)); 936 937 /* disable GSM - Write Data Parity Check */ 938 regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK); 939 pm8001_dbg(pm8001_ha, INIT, "GSM 0x300048 - Write Data Parity Check Enable = 0x%x\n", 940 regVal3); 941 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0); 942 pm8001_dbg(pm8001_ha, INIT, 943 "GSM 0x300048 - Write Data Parity Check Enable is set to = 0x%x\n", 944 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)); 945 946 /* step 5: delay 10 usec */ 947 udelay(10); 948 /* step 5-b: set GPIO-0 output control to tristate anyway */ 949 if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) { 950 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 951 pm8001_dbg(pm8001_ha, INIT, "Shift Bar4 to 0x%x failed\n", 952 GPIO_ADDR_BASE); 953 return -1; 954 } 955 regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET); 956 pm8001_dbg(pm8001_ha, INIT, "GPIO Output Control Register: = 0x%x\n", 957 regVal); 958 /* set GPIO-0 output control to tri-state */ 959 regVal &= 0xFFFFFFFC; 960 pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal); 961 962 /* Step 6: Reset the IOP and AAP1 */ 963 /* map 0x00000 to BAR4(0x20), BAR2(win) */ 964 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) { 965 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 966 pm8001_dbg(pm8001_ha, FAIL, "SPC Shift Bar4 to 0x%x failed\n", 967 SPC_TOP_LEVEL_ADDR_BASE); 968 return -1; 969 } 970 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 971 pm8001_dbg(pm8001_ha, INIT, "Top Register before resetting IOP/AAP1:= 0x%x\n", 972 regVal); 973 regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS); 974 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 975 976 /* step 7: Reset the BDMA/OSSP */ 977 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 978 pm8001_dbg(pm8001_ha, INIT, "Top Register before resetting BDMA/OSSP: = 0x%x\n", 979 regVal); 980 regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP); 981 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 982 983 /* step 8: delay 10 usec */ 984 udelay(10); 985 986 /* step 9: bring the BDMA and OSSP out of reset */ 987 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 988 pm8001_dbg(pm8001_ha, INIT, 989 "Top Register before bringing up BDMA/OSSP:= 0x%x\n", 990 regVal); 991 regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP); 992 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 993 994 /* step 10: delay 10 usec */ 995 udelay(10); 996 997 /* step 11: reads and sets the GSM Configuration and Reset Register */ 998 /* map 0x0700000 to BAR4(0x20), BAR2(win) */ 999 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) { 1000 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1001 pm8001_dbg(pm8001_ha, FAIL, "SPC Shift Bar4 to 0x%x failed\n", 1002 GSM_ADDR_BASE); 1003 return -1; 1004 } 1005 pm8001_dbg(pm8001_ha, INIT, 1006 "GSM 0x0 (0x00007b88)-GSM Configuration and Reset = 0x%x\n", 1007 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)); 1008 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); 1009 /* Put those bits to high */ 1010 /* GSM XCBI offset = 0x70 0000 1011 0x00 Bit 13 COM_SLV_SW_RSTB 1 1012 0x00 Bit 12 QSSP_SW_RSTB 1 1013 0x00 Bit 11 RAAE_SW_RSTB 1 1014 0x00 Bit 9 RB_1_SW_RSTB 1 1015 0x00 Bit 8 SM_SW_RSTB 1 1016 */ 1017 regVal |= (GSM_CONFIG_RESET_VALUE); 1018 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); 1019 pm8001_dbg(pm8001_ha, INIT, "GSM (0x00004088 ==> 0x00007b88) - GSM Configuration and Reset is set to = 0x%x\n", 1020 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)); 1021 1022 /* step 12: Restore GSM - Read Address Parity Check */ 1023 regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK); 1024 /* just for debugging */ 1025 pm8001_dbg(pm8001_ha, INIT, 1026 "GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n", 1027 regVal); 1028 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1); 1029 pm8001_dbg(pm8001_ha, INIT, "GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n", 1030 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)); 1031 /* Restore GSM - Write Address Parity Check */ 1032 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK); 1033 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2); 1034 pm8001_dbg(pm8001_ha, INIT, 1035 "GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n", 1036 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)); 1037 /* Restore GSM - Write Data Parity Check */ 1038 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK); 1039 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3); 1040 pm8001_dbg(pm8001_ha, INIT, 1041 "GSM 0x700048 - Write Data Parity Check Enable is set to = 0x%x\n", 1042 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)); 1043 1044 /* step 13: bring the IOP and AAP1 out of reset */ 1045 /* map 0x00000 to BAR4(0x20), BAR2(win) */ 1046 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) { 1047 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1048 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n", 1049 SPC_TOP_LEVEL_ADDR_BASE); 1050 return -1; 1051 } 1052 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 1053 regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS); 1054 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 1055 1056 /* step 14: delay 10 usec - Normal Mode */ 1057 udelay(10); 1058 /* check Soft Reset Normal mode or Soft Reset HDA mode */ 1059 if (signature == SPC_SOFT_RESET_SIGNATURE) { 1060 /* step 15 (Normal Mode): wait until scratch pad1 register 1061 bit 2 toggled */ 1062 max_wait_count = 2 * 1000 * 1000;/* 2 sec */ 1063 do { 1064 udelay(1); 1065 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) & 1066 SCRATCH_PAD1_RST; 1067 } while ((regVal != toggleVal) && (--max_wait_count)); 1068 1069 if (!max_wait_count) { 1070 regVal = pm8001_cr32(pm8001_ha, 0, 1071 MSGU_SCRATCH_PAD_1); 1072 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT : ToggleVal 0x%x,MSGU_SCRATCH_PAD1 = 0x%x\n", 1073 toggleVal, regVal); 1074 pm8001_dbg(pm8001_ha, FAIL, 1075 "SCRATCH_PAD0 value = 0x%x\n", 1076 pm8001_cr32(pm8001_ha, 0, 1077 MSGU_SCRATCH_PAD_0)); 1078 pm8001_dbg(pm8001_ha, FAIL, 1079 "SCRATCH_PAD2 value = 0x%x\n", 1080 pm8001_cr32(pm8001_ha, 0, 1081 MSGU_SCRATCH_PAD_2)); 1082 pm8001_dbg(pm8001_ha, FAIL, 1083 "SCRATCH_PAD3 value = 0x%x\n", 1084 pm8001_cr32(pm8001_ha, 0, 1085 MSGU_SCRATCH_PAD_3)); 1086 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1087 return -1; 1088 } 1089 1090 /* step 16 (Normal) - Clear ODMR and ODCR */ 1091 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); 1092 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); 1093 1094 /* step 17 (Normal Mode): wait for the FW and IOP to get 1095 ready - 1 sec timeout */ 1096 /* Wait for the SPC Configuration Table to be ready */ 1097 if (check_fw_ready(pm8001_ha) == -1) { 1098 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1099 /* return error if MPI Configuration Table not ready */ 1100 pm8001_dbg(pm8001_ha, INIT, 1101 "FW not ready SCRATCH_PAD1 = 0x%x\n", 1102 regVal); 1103 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 1104 /* return error if MPI Configuration Table not ready */ 1105 pm8001_dbg(pm8001_ha, INIT, 1106 "FW not ready SCRATCH_PAD2 = 0x%x\n", 1107 regVal); 1108 pm8001_dbg(pm8001_ha, INIT, 1109 "SCRATCH_PAD0 value = 0x%x\n", 1110 pm8001_cr32(pm8001_ha, 0, 1111 MSGU_SCRATCH_PAD_0)); 1112 pm8001_dbg(pm8001_ha, INIT, 1113 "SCRATCH_PAD3 value = 0x%x\n", 1114 pm8001_cr32(pm8001_ha, 0, 1115 MSGU_SCRATCH_PAD_3)); 1116 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1117 return -1; 1118 } 1119 } 1120 pm8001_bar4_shift(pm8001_ha, 0); 1121 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1122 1123 pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n"); 1124 return 0; 1125 } 1126 1127 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha) 1128 { 1129 u32 i; 1130 u32 regVal; 1131 pm8001_dbg(pm8001_ha, INIT, "chip reset start\n"); 1132 1133 /* do SPC chip reset. */ 1134 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); 1135 regVal &= ~(SPC_REG_RESET_DEVICE); 1136 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); 1137 1138 /* delay 10 usec */ 1139 udelay(10); 1140 1141 /* bring chip reset out of reset */ 1142 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); 1143 regVal |= SPC_REG_RESET_DEVICE; 1144 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); 1145 1146 /* delay 10 usec */ 1147 udelay(10); 1148 1149 /* wait for 20 msec until the firmware gets reloaded */ 1150 i = 20; 1151 do { 1152 mdelay(1); 1153 } while ((--i) != 0); 1154 1155 pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n"); 1156 } 1157 1158 /** 1159 * pm8001_chip_iounmap - which mapped when initialized. 1160 * @pm8001_ha: our hba card information 1161 */ 1162 void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha) 1163 { 1164 s8 bar, logical = 0; 1165 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { 1166 /* 1167 ** logical BARs for SPC: 1168 ** bar 0 and 1 - logical BAR0 1169 ** bar 2 and 3 - logical BAR1 1170 ** bar4 - logical BAR2 1171 ** bar5 - logical BAR3 1172 ** Skip the appropriate assignments: 1173 */ 1174 if ((bar == 1) || (bar == 3)) 1175 continue; 1176 if (pm8001_ha->io_mem[logical].memvirtaddr) { 1177 iounmap(pm8001_ha->io_mem[logical].memvirtaddr); 1178 logical++; 1179 } 1180 } 1181 } 1182 1183 #ifndef PM8001_USE_MSIX 1184 /** 1185 * pm8001_chip_intx_interrupt_enable - enable PM8001 chip interrupt 1186 * @pm8001_ha: our hba card information 1187 */ 1188 static void 1189 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha) 1190 { 1191 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); 1192 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); 1193 } 1194 1195 /** 1196 * pm8001_chip_intx_interrupt_disable - disable PM8001 chip interrupt 1197 * @pm8001_ha: our hba card information 1198 */ 1199 static void 1200 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha) 1201 { 1202 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL); 1203 } 1204 1205 #else 1206 1207 /** 1208 * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt 1209 * @pm8001_ha: our hba card information 1210 * @int_vec_idx: interrupt number to enable 1211 */ 1212 static void 1213 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha, 1214 u32 int_vec_idx) 1215 { 1216 u32 msi_index; 1217 u32 value; 1218 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE; 1219 msi_index += MSIX_TABLE_BASE; 1220 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE); 1221 value = (1 << int_vec_idx); 1222 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, value); 1223 1224 } 1225 1226 /** 1227 * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt 1228 * @pm8001_ha: our hba card information 1229 * @int_vec_idx: interrupt number to disable 1230 */ 1231 static void 1232 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha, 1233 u32 int_vec_idx) 1234 { 1235 u32 msi_index; 1236 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE; 1237 msi_index += MSIX_TABLE_BASE; 1238 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE); 1239 } 1240 #endif 1241 1242 /** 1243 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt 1244 * @pm8001_ha: our hba card information 1245 * @vec: unused 1246 */ 1247 static void 1248 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1249 { 1250 #ifdef PM8001_USE_MSIX 1251 pm8001_chip_msix_interrupt_enable(pm8001_ha, 0); 1252 #else 1253 pm8001_chip_intx_interrupt_enable(pm8001_ha); 1254 #endif 1255 } 1256 1257 /** 1258 * pm8001_chip_interrupt_disable - disable PM8001 chip interrupt 1259 * @pm8001_ha: our hba card information 1260 * @vec: unused 1261 */ 1262 static void 1263 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1264 { 1265 #ifdef PM8001_USE_MSIX 1266 pm8001_chip_msix_interrupt_disable(pm8001_ha, 0); 1267 #else 1268 pm8001_chip_intx_interrupt_disable(pm8001_ha); 1269 #endif 1270 } 1271 1272 /** 1273 * pm8001_mpi_msg_free_get - get the free message buffer for transfer 1274 * inbound queue. 1275 * @circularQ: the inbound queue we want to transfer to HBA. 1276 * @messageSize: the message size of this transfer, normally it is 64 bytes 1277 * @messagePtr: the pointer to message. 1278 */ 1279 int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ, 1280 u16 messageSize, void **messagePtr) 1281 { 1282 u32 offset, consumer_index; 1283 struct mpi_msg_hdr *msgHeader; 1284 u8 bcCount = 1; /* only support single buffer */ 1285 1286 /* Checks is the requested message size can be allocated in this queue*/ 1287 if (messageSize > IOMB_SIZE_SPCV) { 1288 *messagePtr = NULL; 1289 return -1; 1290 } 1291 1292 /* Stores the new consumer index */ 1293 consumer_index = pm8001_read_32(circularQ->ci_virt); 1294 circularQ->consumer_index = cpu_to_le32(consumer_index); 1295 if (((circularQ->producer_idx + bcCount) % PM8001_MPI_QUEUE) == 1296 le32_to_cpu(circularQ->consumer_index)) { 1297 *messagePtr = NULL; 1298 return -1; 1299 } 1300 /* get memory IOMB buffer address */ 1301 offset = circularQ->producer_idx * messageSize; 1302 /* increment to next bcCount element */ 1303 circularQ->producer_idx = (circularQ->producer_idx + bcCount) 1304 % PM8001_MPI_QUEUE; 1305 /* Adds that distance to the base of the region virtual address plus 1306 the message header size*/ 1307 msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset); 1308 *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr); 1309 return 0; 1310 } 1311 1312 /** 1313 * pm8001_mpi_build_cmd- build the message queue for transfer, update the PI to 1314 * FW to tell the fw to get this message from IOMB. 1315 * @pm8001_ha: our hba card information 1316 * @q_index: the index in the inbound queue we want to transfer to HBA. 1317 * @opCode: the operation code represents commands which LLDD and fw recognized. 1318 * @payload: the command payload of each operation command. 1319 * @nb: size in bytes of the command payload 1320 * @responseQueue: queue to interrupt on w/ command response (if any) 1321 */ 1322 int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha, 1323 u32 q_index, u32 opCode, void *payload, size_t nb, 1324 u32 responseQueue) 1325 { 1326 u32 Header = 0, hpriority = 0, bc = 1, category = 0x02; 1327 void *pMessage; 1328 unsigned long flags; 1329 struct inbound_queue_table *circularQ = &pm8001_ha->inbnd_q_tbl[q_index]; 1330 int rv; 1331 u32 htag = le32_to_cpu(*(__le32 *)payload); 1332 1333 trace_pm80xx_mpi_build_cmd(pm8001_ha->id, opCode, htag, q_index, 1334 circularQ->producer_idx, le32_to_cpu(circularQ->consumer_index)); 1335 1336 if (WARN_ON(q_index >= pm8001_ha->max_q_num)) 1337 return -EINVAL; 1338 1339 spin_lock_irqsave(&circularQ->iq_lock, flags); 1340 rv = pm8001_mpi_msg_free_get(circularQ, pm8001_ha->iomb_size, 1341 &pMessage); 1342 if (rv < 0) { 1343 pm8001_dbg(pm8001_ha, IO, "No free mpi buffer\n"); 1344 rv = -ENOMEM; 1345 goto done; 1346 } 1347 1348 if (nb > (pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr))) 1349 nb = pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr); 1350 memcpy(pMessage, payload, nb); 1351 if (nb + sizeof(struct mpi_msg_hdr) < pm8001_ha->iomb_size) 1352 memset(pMessage + nb, 0, pm8001_ha->iomb_size - 1353 (nb + sizeof(struct mpi_msg_hdr))); 1354 1355 /*Build the header*/ 1356 Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24) 1357 | ((responseQueue & 0x3F) << 16) 1358 | ((category & 0xF) << 12) | (opCode & 0xFFF)); 1359 1360 pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header)); 1361 /*Update the PI to the firmware*/ 1362 pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar, 1363 circularQ->pi_offset, circularQ->producer_idx); 1364 pm8001_dbg(pm8001_ha, DEVIO, 1365 "INB Q %x OPCODE:%x , UPDATED PI=%d CI=%d\n", 1366 responseQueue, opCode, circularQ->producer_idx, 1367 circularQ->consumer_index); 1368 done: 1369 spin_unlock_irqrestore(&circularQ->iq_lock, flags); 1370 return rv; 1371 } 1372 1373 u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg, 1374 struct outbound_queue_table *circularQ, u8 bc) 1375 { 1376 u32 producer_index; 1377 struct mpi_msg_hdr *msgHeader; 1378 struct mpi_msg_hdr *pOutBoundMsgHeader; 1379 1380 msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr)); 1381 pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + 1382 circularQ->consumer_idx * pm8001_ha->iomb_size); 1383 if (pOutBoundMsgHeader != msgHeader) { 1384 pm8001_dbg(pm8001_ha, FAIL, 1385 "consumer_idx = %d msgHeader = %p\n", 1386 circularQ->consumer_idx, msgHeader); 1387 1388 /* Update the producer index from SPC */ 1389 producer_index = pm8001_read_32(circularQ->pi_virt); 1390 circularQ->producer_index = cpu_to_le32(producer_index); 1391 pm8001_dbg(pm8001_ha, FAIL, 1392 "consumer_idx = %d producer_index = %dmsgHeader = %p\n", 1393 circularQ->consumer_idx, 1394 circularQ->producer_index, msgHeader); 1395 return 0; 1396 } 1397 /* free the circular queue buffer elements associated with the message*/ 1398 circularQ->consumer_idx = (circularQ->consumer_idx + bc) 1399 % PM8001_MPI_QUEUE; 1400 /* update the CI of outbound queue */ 1401 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset, 1402 circularQ->consumer_idx); 1403 /* Update the producer index from SPC*/ 1404 producer_index = pm8001_read_32(circularQ->pi_virt); 1405 circularQ->producer_index = cpu_to_le32(producer_index); 1406 pm8001_dbg(pm8001_ha, IO, " CI=%d PI=%d\n", 1407 circularQ->consumer_idx, circularQ->producer_index); 1408 return 0; 1409 } 1410 1411 /** 1412 * pm8001_mpi_msg_consume- get the MPI message from outbound queue 1413 * message table. 1414 * @pm8001_ha: our hba card information 1415 * @circularQ: the outbound queue table. 1416 * @messagePtr1: the message contents of this outbound message. 1417 * @pBC: the message size. 1418 */ 1419 u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha, 1420 struct outbound_queue_table *circularQ, 1421 void **messagePtr1, u8 *pBC) 1422 { 1423 struct mpi_msg_hdr *msgHeader; 1424 __le32 msgHeader_tmp; 1425 u32 header_tmp; 1426 do { 1427 /* If there are not-yet-delivered messages ... */ 1428 if (le32_to_cpu(circularQ->producer_index) 1429 != circularQ->consumer_idx) { 1430 /*Get the pointer to the circular queue buffer element*/ 1431 msgHeader = (struct mpi_msg_hdr *) 1432 (circularQ->base_virt + 1433 circularQ->consumer_idx * pm8001_ha->iomb_size); 1434 /* read header */ 1435 header_tmp = pm8001_read_32(msgHeader); 1436 msgHeader_tmp = cpu_to_le32(header_tmp); 1437 pm8001_dbg(pm8001_ha, DEVIO, 1438 "outbound opcode msgheader:%x ci=%d pi=%d\n", 1439 msgHeader_tmp, circularQ->consumer_idx, 1440 circularQ->producer_index); 1441 if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) { 1442 if (OPC_OUB_SKIP_ENTRY != 1443 (le32_to_cpu(msgHeader_tmp) & 0xfff)) { 1444 *messagePtr1 = 1445 ((u8 *)msgHeader) + 1446 sizeof(struct mpi_msg_hdr); 1447 *pBC = (u8)((le32_to_cpu(msgHeader_tmp) 1448 >> 24) & 0x1f); 1449 pm8001_dbg(pm8001_ha, IO, 1450 ": CI=%d PI=%d msgHeader=%x\n", 1451 circularQ->consumer_idx, 1452 circularQ->producer_index, 1453 msgHeader_tmp); 1454 return MPI_IO_STATUS_SUCCESS; 1455 } else { 1456 circularQ->consumer_idx = 1457 (circularQ->consumer_idx + 1458 ((le32_to_cpu(msgHeader_tmp) 1459 >> 24) & 0x1f)) 1460 % PM8001_MPI_QUEUE; 1461 msgHeader_tmp = 0; 1462 pm8001_write_32(msgHeader, 0, 0); 1463 /* update the CI of outbound queue */ 1464 pm8001_cw32(pm8001_ha, 1465 circularQ->ci_pci_bar, 1466 circularQ->ci_offset, 1467 circularQ->consumer_idx); 1468 } 1469 } else { 1470 circularQ->consumer_idx = 1471 (circularQ->consumer_idx + 1472 ((le32_to_cpu(msgHeader_tmp) >> 24) & 1473 0x1f)) % PM8001_MPI_QUEUE; 1474 msgHeader_tmp = 0; 1475 pm8001_write_32(msgHeader, 0, 0); 1476 /* update the CI of outbound queue */ 1477 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, 1478 circularQ->ci_offset, 1479 circularQ->consumer_idx); 1480 return MPI_IO_STATUS_FAIL; 1481 } 1482 } else { 1483 u32 producer_index; 1484 void *pi_virt = circularQ->pi_virt; 1485 /* spurious interrupt during setup if 1486 * kexec-ing and driver doing a doorbell access 1487 * with the pre-kexec oq interrupt setup 1488 */ 1489 if (!pi_virt) 1490 break; 1491 /* Update the producer index from SPC */ 1492 producer_index = pm8001_read_32(pi_virt); 1493 circularQ->producer_index = cpu_to_le32(producer_index); 1494 } 1495 } while (le32_to_cpu(circularQ->producer_index) != 1496 circularQ->consumer_idx); 1497 /* while we don't have any more not-yet-delivered message */ 1498 /* report empty */ 1499 return MPI_IO_STATUS_BUSY; 1500 } 1501 1502 void pm8001_work_fn(struct work_struct *work) 1503 { 1504 struct pm8001_work *pw = container_of(work, struct pm8001_work, work); 1505 struct pm8001_device *pm8001_dev; 1506 struct domain_device *dev; 1507 1508 /* 1509 * So far, all users of this stash an associated structure here. 1510 * If we get here, and this pointer is null, then the action 1511 * was cancelled. This nullification happens when the device 1512 * goes away. 1513 */ 1514 if (pw->handler != IO_FATAL_ERROR) { 1515 pm8001_dev = pw->data; /* Most stash device structure */ 1516 if ((pm8001_dev == NULL) 1517 || ((pw->handler != IO_XFER_ERROR_BREAK) 1518 && (pm8001_dev->dev_type == SAS_PHY_UNUSED))) { 1519 kfree(pw); 1520 return; 1521 } 1522 } 1523 1524 switch (pw->handler) { 1525 case IO_XFER_ERROR_BREAK: 1526 { /* This one stashes the sas_task instead */ 1527 struct sas_task *t = (struct sas_task *)pm8001_dev; 1528 struct pm8001_ccb_info *ccb; 1529 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha; 1530 unsigned long flags, flags1; 1531 struct task_status_struct *ts; 1532 int i; 1533 1534 if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC) 1535 break; /* Task still on lu */ 1536 spin_lock_irqsave(&pm8001_ha->lock, flags); 1537 1538 spin_lock_irqsave(&t->task_state_lock, flags1); 1539 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) { 1540 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1541 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1542 break; /* Task got completed by another */ 1543 } 1544 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1545 1546 /* Search for a possible ccb that matches the task */ 1547 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) { 1548 ccb = &pm8001_ha->ccb_info[i]; 1549 if ((ccb->ccb_tag != PM8001_INVALID_TAG) && 1550 (ccb->task == t)) 1551 break; 1552 } 1553 if (!ccb) { 1554 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1555 break; /* Task got freed by another */ 1556 } 1557 ts = &t->task_status; 1558 ts->resp = SAS_TASK_COMPLETE; 1559 /* Force the midlayer to retry */ 1560 ts->stat = SAS_QUEUE_FULL; 1561 pm8001_dev = ccb->device; 1562 if (pm8001_dev) 1563 atomic_dec(&pm8001_dev->running_req); 1564 spin_lock_irqsave(&t->task_state_lock, flags1); 1565 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 1566 t->task_state_flags |= SAS_TASK_STATE_DONE; 1567 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 1568 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1569 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 1570 t, pw->handler, ts->resp, ts->stat); 1571 pm8001_ccb_task_free(pm8001_ha, ccb); 1572 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1573 } else { 1574 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1575 pm8001_ccb_task_free(pm8001_ha, ccb); 1576 mb();/* in order to force CPU ordering */ 1577 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1578 t->task_done(t); 1579 } 1580 } break; 1581 case IO_XFER_OPEN_RETRY_TIMEOUT: 1582 { /* This one stashes the sas_task instead */ 1583 struct sas_task *t = (struct sas_task *)pm8001_dev; 1584 struct pm8001_ccb_info *ccb; 1585 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha; 1586 unsigned long flags, flags1; 1587 int i, ret = 0; 1588 1589 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 1590 1591 ret = pm8001_query_task(t); 1592 1593 if (ret == TMF_RESP_FUNC_SUCC) 1594 pm8001_dbg(pm8001_ha, IO, "...Task on lu\n"); 1595 else if (ret == TMF_RESP_FUNC_COMPLETE) 1596 pm8001_dbg(pm8001_ha, IO, "...Task NOT on lu\n"); 1597 else 1598 pm8001_dbg(pm8001_ha, DEVIO, "...query task failed!!!\n"); 1599 1600 spin_lock_irqsave(&pm8001_ha->lock, flags); 1601 1602 spin_lock_irqsave(&t->task_state_lock, flags1); 1603 1604 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) { 1605 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1606 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1607 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */ 1608 (void)pm8001_abort_task(t); 1609 break; /* Task got completed by another */ 1610 } 1611 1612 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1613 1614 /* Search for a possible ccb that matches the task */ 1615 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) { 1616 ccb = &pm8001_ha->ccb_info[i]; 1617 if ((ccb->ccb_tag != PM8001_INVALID_TAG) && 1618 (ccb->task == t)) 1619 break; 1620 } 1621 if (!ccb) { 1622 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1623 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */ 1624 (void)pm8001_abort_task(t); 1625 break; /* Task got freed by another */ 1626 } 1627 1628 pm8001_dev = ccb->device; 1629 dev = pm8001_dev->sas_device; 1630 1631 switch (ret) { 1632 case TMF_RESP_FUNC_SUCC: /* task on lu */ 1633 ccb->open_retry = 1; /* Snub completion */ 1634 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1635 ret = pm8001_abort_task(t); 1636 ccb->open_retry = 0; 1637 switch (ret) { 1638 case TMF_RESP_FUNC_SUCC: 1639 case TMF_RESP_FUNC_COMPLETE: 1640 break; 1641 default: /* device misbehavior */ 1642 ret = TMF_RESP_FUNC_FAILED; 1643 pm8001_dbg(pm8001_ha, IO, "...Reset phy\n"); 1644 pm8001_I_T_nexus_reset(dev); 1645 break; 1646 } 1647 break; 1648 1649 case TMF_RESP_FUNC_COMPLETE: /* task not on lu */ 1650 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1651 /* Do we need to abort the task locally? */ 1652 break; 1653 1654 default: /* device misbehavior */ 1655 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1656 ret = TMF_RESP_FUNC_FAILED; 1657 pm8001_dbg(pm8001_ha, IO, "...Reset phy\n"); 1658 pm8001_I_T_nexus_reset(dev); 1659 } 1660 1661 if (ret == TMF_RESP_FUNC_FAILED) 1662 t = NULL; 1663 pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev); 1664 pm8001_dbg(pm8001_ha, IO, "...Complete\n"); 1665 } break; 1666 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1667 dev = pm8001_dev->sas_device; 1668 pm8001_I_T_nexus_event_handler(dev); 1669 break; 1670 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 1671 dev = pm8001_dev->sas_device; 1672 pm8001_I_T_nexus_reset(dev); 1673 break; 1674 case IO_DS_IN_ERROR: 1675 dev = pm8001_dev->sas_device; 1676 pm8001_I_T_nexus_reset(dev); 1677 break; 1678 case IO_DS_NON_OPERATIONAL: 1679 dev = pm8001_dev->sas_device; 1680 pm8001_I_T_nexus_reset(dev); 1681 break; 1682 case IO_FATAL_ERROR: 1683 { 1684 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha; 1685 struct pm8001_ccb_info *ccb; 1686 struct task_status_struct *ts; 1687 struct sas_task *task; 1688 int i; 1689 u32 device_id; 1690 1691 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) { 1692 ccb = &pm8001_ha->ccb_info[i]; 1693 task = ccb->task; 1694 ts = &task->task_status; 1695 1696 if (task != NULL) { 1697 dev = task->dev; 1698 if (!dev) { 1699 pm8001_dbg(pm8001_ha, FAIL, 1700 "dev is NULL\n"); 1701 continue; 1702 } 1703 /*complete sas task and update to top layer */ 1704 pm8001_ccb_task_free(pm8001_ha, ccb); 1705 ts->resp = SAS_TASK_COMPLETE; 1706 task->task_done(task); 1707 } else if (ccb->ccb_tag != PM8001_INVALID_TAG) { 1708 /* complete the internal commands/non-sas task */ 1709 pm8001_dev = ccb->device; 1710 if (pm8001_dev->dcompletion) { 1711 complete(pm8001_dev->dcompletion); 1712 pm8001_dev->dcompletion = NULL; 1713 } 1714 complete(pm8001_ha->nvmd_completion); 1715 pm8001_ccb_free(pm8001_ha, ccb); 1716 } 1717 } 1718 /* Deregister all the device ids */ 1719 for (i = 0; i < PM8001_MAX_DEVICES; i++) { 1720 pm8001_dev = &pm8001_ha->devices[i]; 1721 device_id = pm8001_dev->device_id; 1722 if (device_id) { 1723 PM8001_CHIP_DISP->dereg_dev_req(pm8001_ha, device_id); 1724 pm8001_free_dev(pm8001_dev); 1725 } 1726 } 1727 } 1728 break; 1729 case IO_XFER_ERROR_ABORTED_NCQ_MODE: 1730 { 1731 dev = pm8001_dev->sas_device; 1732 sas_ata_device_link_abort(dev, false); 1733 } 1734 break; 1735 } 1736 kfree(pw); 1737 } 1738 1739 int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data, 1740 int handler) 1741 { 1742 struct pm8001_work *pw; 1743 int ret = 0; 1744 1745 pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC); 1746 if (pw) { 1747 pw->pm8001_ha = pm8001_ha; 1748 pw->data = data; 1749 pw->handler = handler; 1750 INIT_WORK(&pw->work, pm8001_work_fn); 1751 queue_work(pm8001_wq, &pw->work); 1752 } else 1753 ret = -ENOMEM; 1754 1755 return ret; 1756 } 1757 1758 /** 1759 * mpi_ssp_completion- process the event that FW response to the SSP request. 1760 * @pm8001_ha: our hba card information 1761 * @piomb: the message contents of this outbound message. 1762 * 1763 * When FW has completed a ssp request for example a IO request, after it has 1764 * filled the SG data with the data, it will trigger this event representing 1765 * that he has finished the job; please check the corresponding buffer. 1766 * So we will tell the caller who maybe waiting the result to tell upper layer 1767 * that the task has been finished. 1768 */ 1769 static void 1770 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 1771 { 1772 struct sas_task *t; 1773 struct pm8001_ccb_info *ccb; 1774 unsigned long flags; 1775 u32 status; 1776 u32 param; 1777 u32 tag; 1778 struct ssp_completion_resp *psspPayload; 1779 struct task_status_struct *ts; 1780 struct ssp_response_iu *iu; 1781 struct pm8001_device *pm8001_dev; 1782 psspPayload = (struct ssp_completion_resp *)(piomb + 4); 1783 status = le32_to_cpu(psspPayload->status); 1784 tag = le32_to_cpu(psspPayload->tag); 1785 ccb = &pm8001_ha->ccb_info[tag]; 1786 if ((status == IO_ABORTED) && ccb->open_retry) { 1787 /* Being completed by another */ 1788 ccb->open_retry = 0; 1789 return; 1790 } 1791 pm8001_dev = ccb->device; 1792 param = le32_to_cpu(psspPayload->param); 1793 1794 t = ccb->task; 1795 1796 if (status && status != IO_UNDERFLOW) 1797 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status); 1798 if (unlikely(!t || !t->lldd_task || !t->dev)) 1799 return; 1800 ts = &t->task_status; 1801 /* Print sas address of IO failed device */ 1802 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 1803 (status != IO_UNDERFLOW)) 1804 pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n", 1805 SAS_ADDR(t->dev->sas_addr)); 1806 1807 if (status) 1808 pm8001_dbg(pm8001_ha, IOERR, 1809 "status:0x%x, tag:0x%x, task:0x%p\n", 1810 status, tag, t); 1811 1812 switch (status) { 1813 case IO_SUCCESS: 1814 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS,param = %d\n", 1815 param); 1816 if (param == 0) { 1817 ts->resp = SAS_TASK_COMPLETE; 1818 ts->stat = SAS_SAM_STAT_GOOD; 1819 } else { 1820 ts->resp = SAS_TASK_COMPLETE; 1821 ts->stat = SAS_PROTO_RESPONSE; 1822 ts->residual = param; 1823 iu = &psspPayload->ssp_resp_iu; 1824 sas_ssp_task_response(pm8001_ha->dev, t, iu); 1825 } 1826 if (pm8001_dev) 1827 atomic_dec(&pm8001_dev->running_req); 1828 break; 1829 case IO_ABORTED: 1830 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n"); 1831 ts->resp = SAS_TASK_COMPLETE; 1832 ts->stat = SAS_ABORTED_TASK; 1833 break; 1834 case IO_UNDERFLOW: 1835 /* SSP Completion with error */ 1836 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW,param = %d\n", 1837 param); 1838 ts->resp = SAS_TASK_COMPLETE; 1839 ts->stat = SAS_DATA_UNDERRUN; 1840 ts->residual = param; 1841 if (pm8001_dev) 1842 atomic_dec(&pm8001_dev->running_req); 1843 break; 1844 case IO_NO_DEVICE: 1845 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 1846 ts->resp = SAS_TASK_UNDELIVERED; 1847 ts->stat = SAS_PHY_DOWN; 1848 break; 1849 case IO_XFER_ERROR_BREAK: 1850 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 1851 ts->resp = SAS_TASK_COMPLETE; 1852 ts->stat = SAS_OPEN_REJECT; 1853 /* Force the midlayer to retry */ 1854 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1855 break; 1856 case IO_XFER_ERROR_PHY_NOT_READY: 1857 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 1858 ts->resp = SAS_TASK_COMPLETE; 1859 ts->stat = SAS_OPEN_REJECT; 1860 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1861 break; 1862 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 1863 pm8001_dbg(pm8001_ha, IO, 1864 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 1865 ts->resp = SAS_TASK_COMPLETE; 1866 ts->stat = SAS_OPEN_REJECT; 1867 ts->open_rej_reason = SAS_OREJ_EPROTO; 1868 break; 1869 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 1870 pm8001_dbg(pm8001_ha, IO, 1871 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 1872 ts->resp = SAS_TASK_COMPLETE; 1873 ts->stat = SAS_OPEN_REJECT; 1874 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1875 break; 1876 case IO_OPEN_CNX_ERROR_BREAK: 1877 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 1878 ts->resp = SAS_TASK_COMPLETE; 1879 ts->stat = SAS_OPEN_REJECT; 1880 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1881 break; 1882 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1883 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 1884 ts->resp = SAS_TASK_COMPLETE; 1885 ts->stat = SAS_OPEN_REJECT; 1886 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1887 if (!t->uldd_task) 1888 pm8001_handle_event(pm8001_ha, 1889 pm8001_dev, 1890 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 1891 break; 1892 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 1893 pm8001_dbg(pm8001_ha, IO, 1894 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 1895 ts->resp = SAS_TASK_COMPLETE; 1896 ts->stat = SAS_OPEN_REJECT; 1897 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 1898 break; 1899 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 1900 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 1901 ts->resp = SAS_TASK_COMPLETE; 1902 ts->stat = SAS_OPEN_REJECT; 1903 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 1904 break; 1905 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 1906 pm8001_dbg(pm8001_ha, IO, 1907 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 1908 ts->resp = SAS_TASK_UNDELIVERED; 1909 ts->stat = SAS_OPEN_REJECT; 1910 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 1911 break; 1912 case IO_XFER_ERROR_NAK_RECEIVED: 1913 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 1914 ts->resp = SAS_TASK_COMPLETE; 1915 ts->stat = SAS_OPEN_REJECT; 1916 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1917 break; 1918 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 1919 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 1920 ts->resp = SAS_TASK_COMPLETE; 1921 ts->stat = SAS_NAK_R_ERR; 1922 break; 1923 case IO_XFER_ERROR_DMA: 1924 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n"); 1925 ts->resp = SAS_TASK_COMPLETE; 1926 ts->stat = SAS_OPEN_REJECT; 1927 break; 1928 case IO_XFER_OPEN_RETRY_TIMEOUT: 1929 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 1930 ts->resp = SAS_TASK_COMPLETE; 1931 ts->stat = SAS_OPEN_REJECT; 1932 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1933 break; 1934 case IO_XFER_ERROR_OFFSET_MISMATCH: 1935 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 1936 ts->resp = SAS_TASK_COMPLETE; 1937 ts->stat = SAS_OPEN_REJECT; 1938 break; 1939 case IO_PORT_IN_RESET: 1940 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 1941 ts->resp = SAS_TASK_COMPLETE; 1942 ts->stat = SAS_OPEN_REJECT; 1943 break; 1944 case IO_DS_NON_OPERATIONAL: 1945 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 1946 ts->resp = SAS_TASK_COMPLETE; 1947 ts->stat = SAS_OPEN_REJECT; 1948 if (!t->uldd_task) 1949 pm8001_handle_event(pm8001_ha, 1950 pm8001_dev, 1951 IO_DS_NON_OPERATIONAL); 1952 break; 1953 case IO_DS_IN_RECOVERY: 1954 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n"); 1955 ts->resp = SAS_TASK_COMPLETE; 1956 ts->stat = SAS_OPEN_REJECT; 1957 break; 1958 case IO_TM_TAG_NOT_FOUND: 1959 pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n"); 1960 ts->resp = SAS_TASK_COMPLETE; 1961 ts->stat = SAS_OPEN_REJECT; 1962 break; 1963 case IO_SSP_EXT_IU_ZERO_LEN_ERROR: 1964 pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"); 1965 ts->resp = SAS_TASK_COMPLETE; 1966 ts->stat = SAS_OPEN_REJECT; 1967 break; 1968 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 1969 pm8001_dbg(pm8001_ha, IO, 1970 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 1971 ts->resp = SAS_TASK_COMPLETE; 1972 ts->stat = SAS_OPEN_REJECT; 1973 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1974 break; 1975 default: 1976 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status); 1977 /* not allowed case. Therefore, return failed status */ 1978 ts->resp = SAS_TASK_COMPLETE; 1979 ts->stat = SAS_OPEN_REJECT; 1980 break; 1981 } 1982 pm8001_dbg(pm8001_ha, IO, "scsi_status = %x\n", 1983 psspPayload->ssp_resp_iu.status); 1984 spin_lock_irqsave(&t->task_state_lock, flags); 1985 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 1986 t->task_state_flags |= SAS_TASK_STATE_DONE; 1987 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 1988 spin_unlock_irqrestore(&t->task_state_lock, flags); 1989 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 1990 t, status, ts->resp, ts->stat); 1991 pm8001_ccb_task_free(pm8001_ha, ccb); 1992 } else { 1993 spin_unlock_irqrestore(&t->task_state_lock, flags); 1994 pm8001_ccb_task_free(pm8001_ha, ccb); 1995 mb();/* in order to force CPU ordering */ 1996 t->task_done(t); 1997 } 1998 } 1999 2000 /*See the comments for mpi_ssp_completion */ 2001 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 2002 { 2003 struct sas_task *t; 2004 unsigned long flags; 2005 struct task_status_struct *ts; 2006 struct pm8001_ccb_info *ccb; 2007 struct pm8001_device *pm8001_dev; 2008 struct ssp_event_resp *psspPayload = 2009 (struct ssp_event_resp *)(piomb + 4); 2010 u32 event = le32_to_cpu(psspPayload->event); 2011 u32 tag = le32_to_cpu(psspPayload->tag); 2012 u32 port_id = le32_to_cpu(psspPayload->port_id); 2013 u32 dev_id = le32_to_cpu(psspPayload->device_id); 2014 2015 ccb = &pm8001_ha->ccb_info[tag]; 2016 t = ccb->task; 2017 pm8001_dev = ccb->device; 2018 if (event) 2019 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event); 2020 if (unlikely(!t || !t->lldd_task || !t->dev)) 2021 return; 2022 ts = &t->task_status; 2023 pm8001_dbg(pm8001_ha, DEVIO, "port_id = %x,device_id = %x\n", 2024 port_id, dev_id); 2025 switch (event) { 2026 case IO_OVERFLOW: 2027 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 2028 ts->resp = SAS_TASK_COMPLETE; 2029 ts->stat = SAS_DATA_OVERRUN; 2030 ts->residual = 0; 2031 if (pm8001_dev) 2032 atomic_dec(&pm8001_dev->running_req); 2033 break; 2034 case IO_XFER_ERROR_BREAK: 2035 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2036 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK); 2037 return; 2038 case IO_XFER_ERROR_PHY_NOT_READY: 2039 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2040 ts->resp = SAS_TASK_COMPLETE; 2041 ts->stat = SAS_OPEN_REJECT; 2042 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2043 break; 2044 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2045 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2046 ts->resp = SAS_TASK_COMPLETE; 2047 ts->stat = SAS_OPEN_REJECT; 2048 ts->open_rej_reason = SAS_OREJ_EPROTO; 2049 break; 2050 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2051 pm8001_dbg(pm8001_ha, IO, 2052 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2053 ts->resp = SAS_TASK_COMPLETE; 2054 ts->stat = SAS_OPEN_REJECT; 2055 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2056 break; 2057 case IO_OPEN_CNX_ERROR_BREAK: 2058 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2059 ts->resp = SAS_TASK_COMPLETE; 2060 ts->stat = SAS_OPEN_REJECT; 2061 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2062 break; 2063 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2064 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2065 ts->resp = SAS_TASK_COMPLETE; 2066 ts->stat = SAS_OPEN_REJECT; 2067 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2068 if (!t->uldd_task) 2069 pm8001_handle_event(pm8001_ha, 2070 pm8001_dev, 2071 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2072 break; 2073 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2074 pm8001_dbg(pm8001_ha, IO, 2075 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2076 ts->resp = SAS_TASK_COMPLETE; 2077 ts->stat = SAS_OPEN_REJECT; 2078 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2079 break; 2080 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2081 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2082 ts->resp = SAS_TASK_COMPLETE; 2083 ts->stat = SAS_OPEN_REJECT; 2084 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2085 break; 2086 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2087 pm8001_dbg(pm8001_ha, IO, 2088 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2089 ts->resp = SAS_TASK_COMPLETE; 2090 ts->stat = SAS_OPEN_REJECT; 2091 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2092 break; 2093 case IO_XFER_ERROR_NAK_RECEIVED: 2094 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2095 ts->resp = SAS_TASK_COMPLETE; 2096 ts->stat = SAS_OPEN_REJECT; 2097 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2098 break; 2099 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2100 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 2101 ts->resp = SAS_TASK_COMPLETE; 2102 ts->stat = SAS_NAK_R_ERR; 2103 break; 2104 case IO_XFER_OPEN_RETRY_TIMEOUT: 2105 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2106 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT); 2107 return; 2108 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2109 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n"); 2110 ts->resp = SAS_TASK_COMPLETE; 2111 ts->stat = SAS_DATA_OVERRUN; 2112 break; 2113 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2114 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n"); 2115 ts->resp = SAS_TASK_COMPLETE; 2116 ts->stat = SAS_DATA_OVERRUN; 2117 break; 2118 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2119 pm8001_dbg(pm8001_ha, IO, 2120 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"); 2121 ts->resp = SAS_TASK_COMPLETE; 2122 ts->stat = SAS_DATA_OVERRUN; 2123 break; 2124 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT: 2125 pm8001_dbg(pm8001_ha, IO, 2126 "IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"); 2127 ts->resp = SAS_TASK_COMPLETE; 2128 ts->stat = SAS_DATA_OVERRUN; 2129 break; 2130 case IO_XFER_ERROR_OFFSET_MISMATCH: 2131 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 2132 ts->resp = SAS_TASK_COMPLETE; 2133 ts->stat = SAS_DATA_OVERRUN; 2134 break; 2135 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2136 pm8001_dbg(pm8001_ha, IO, 2137 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"); 2138 ts->resp = SAS_TASK_COMPLETE; 2139 ts->stat = SAS_DATA_OVERRUN; 2140 break; 2141 case IO_XFER_CMD_FRAME_ISSUED: 2142 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n"); 2143 return; 2144 default: 2145 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event); 2146 /* not allowed case. Therefore, return failed status */ 2147 ts->resp = SAS_TASK_COMPLETE; 2148 ts->stat = SAS_DATA_OVERRUN; 2149 break; 2150 } 2151 spin_lock_irqsave(&t->task_state_lock, flags); 2152 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2153 t->task_state_flags |= SAS_TASK_STATE_DONE; 2154 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2155 spin_unlock_irqrestore(&t->task_state_lock, flags); 2156 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2157 t, event, ts->resp, ts->stat); 2158 pm8001_ccb_task_free(pm8001_ha, ccb); 2159 } else { 2160 spin_unlock_irqrestore(&t->task_state_lock, flags); 2161 pm8001_ccb_task_free(pm8001_ha, ccb); 2162 mb();/* in order to force CPU ordering */ 2163 t->task_done(t); 2164 } 2165 } 2166 2167 /*See the comments for mpi_ssp_completion */ 2168 static void 2169 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2170 { 2171 struct sas_task *t; 2172 struct pm8001_ccb_info *ccb; 2173 u32 param; 2174 u32 status; 2175 u32 tag; 2176 int i, j; 2177 u8 sata_addr_low[4]; 2178 u32 temp_sata_addr_low; 2179 u8 sata_addr_hi[4]; 2180 u32 temp_sata_addr_hi; 2181 struct sata_completion_resp *psataPayload; 2182 struct task_status_struct *ts; 2183 struct ata_task_resp *resp ; 2184 u32 *sata_resp; 2185 struct pm8001_device *pm8001_dev; 2186 unsigned long flags; 2187 2188 psataPayload = (struct sata_completion_resp *)(piomb + 4); 2189 status = le32_to_cpu(psataPayload->status); 2190 param = le32_to_cpu(psataPayload->param); 2191 tag = le32_to_cpu(psataPayload->tag); 2192 2193 ccb = &pm8001_ha->ccb_info[tag]; 2194 t = ccb->task; 2195 pm8001_dev = ccb->device; 2196 2197 if (t) { 2198 if (t->dev && (t->dev->lldd_dev)) 2199 pm8001_dev = t->dev->lldd_dev; 2200 } else { 2201 pm8001_dbg(pm8001_ha, FAIL, "task null, freeing CCB tag %d\n", 2202 ccb->ccb_tag); 2203 pm8001_ccb_free(pm8001_ha, ccb); 2204 return; 2205 } 2206 2207 if (pm8001_dev && unlikely(!t || !t->lldd_task || !t->dev)) { 2208 pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n"); 2209 return; 2210 } 2211 2212 ts = &t->task_status; 2213 2214 if (status) 2215 pm8001_dbg(pm8001_ha, IOERR, 2216 "status:0x%x, tag:0x%x, task::0x%p\n", 2217 status, tag, t); 2218 2219 /* Print sas address of IO failed device */ 2220 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 2221 (status != IO_UNDERFLOW)) { 2222 if (!((t->dev->parent) && 2223 (dev_is_expander(t->dev->parent->dev_type)))) { 2224 for (i = 0, j = 4; j <= 7 && i <= 3; i++, j++) 2225 sata_addr_low[i] = pm8001_ha->sas_addr[j]; 2226 for (i = 0, j = 0; j <= 3 && i <= 3; i++, j++) 2227 sata_addr_hi[i] = pm8001_ha->sas_addr[j]; 2228 memcpy(&temp_sata_addr_low, sata_addr_low, 2229 sizeof(sata_addr_low)); 2230 memcpy(&temp_sata_addr_hi, sata_addr_hi, 2231 sizeof(sata_addr_hi)); 2232 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff) 2233 |((temp_sata_addr_hi << 8) & 2234 0xff0000) | 2235 ((temp_sata_addr_hi >> 8) 2236 & 0xff00) | 2237 ((temp_sata_addr_hi << 24) & 2238 0xff000000)); 2239 temp_sata_addr_low = ((((temp_sata_addr_low >> 24) 2240 & 0xff) | 2241 ((temp_sata_addr_low << 8) 2242 & 0xff0000) | 2243 ((temp_sata_addr_low >> 8) 2244 & 0xff00) | 2245 ((temp_sata_addr_low << 24) 2246 & 0xff000000)) + 2247 pm8001_dev->attached_phy + 2248 0x10); 2249 pm8001_dbg(pm8001_ha, FAIL, 2250 "SAS Address of IO Failure Drive:%08x%08x\n", 2251 temp_sata_addr_hi, 2252 temp_sata_addr_low); 2253 } else { 2254 pm8001_dbg(pm8001_ha, FAIL, 2255 "SAS Address of IO Failure Drive:%016llx\n", 2256 SAS_ADDR(t->dev->sas_addr)); 2257 } 2258 } 2259 switch (status) { 2260 case IO_SUCCESS: 2261 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n"); 2262 if (param == 0) { 2263 ts->resp = SAS_TASK_COMPLETE; 2264 ts->stat = SAS_SAM_STAT_GOOD; 2265 } else { 2266 u8 len; 2267 ts->resp = SAS_TASK_COMPLETE; 2268 ts->stat = SAS_PROTO_RESPONSE; 2269 ts->residual = param; 2270 pm8001_dbg(pm8001_ha, IO, 2271 "SAS_PROTO_RESPONSE len = %d\n", 2272 param); 2273 sata_resp = &psataPayload->sata_resp[0]; 2274 resp = (struct ata_task_resp *)ts->buf; 2275 if (t->ata_task.dma_xfer == 0 && 2276 t->data_dir == DMA_FROM_DEVICE) { 2277 len = sizeof(struct pio_setup_fis); 2278 pm8001_dbg(pm8001_ha, IO, 2279 "PIO read len = %d\n", len); 2280 } else if (t->ata_task.use_ncq && 2281 t->data_dir != DMA_NONE) { 2282 len = sizeof(struct set_dev_bits_fis); 2283 pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n", 2284 len); 2285 } else { 2286 len = sizeof(struct dev_to_host_fis); 2287 pm8001_dbg(pm8001_ha, IO, "other len = %d\n", 2288 len); 2289 } 2290 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) { 2291 resp->frame_len = len; 2292 memcpy(&resp->ending_fis[0], sata_resp, len); 2293 ts->buf_valid_size = sizeof(*resp); 2294 } else 2295 pm8001_dbg(pm8001_ha, IO, 2296 "response too large\n"); 2297 } 2298 if (pm8001_dev) 2299 atomic_dec(&pm8001_dev->running_req); 2300 break; 2301 case IO_ABORTED: 2302 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n"); 2303 ts->resp = SAS_TASK_COMPLETE; 2304 ts->stat = SAS_ABORTED_TASK; 2305 if (pm8001_dev) 2306 atomic_dec(&pm8001_dev->running_req); 2307 break; 2308 /* following cases are to do cases */ 2309 case IO_UNDERFLOW: 2310 /* SATA Completion with error */ 2311 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param); 2312 ts->resp = SAS_TASK_COMPLETE; 2313 ts->stat = SAS_DATA_UNDERRUN; 2314 ts->residual = param; 2315 if (pm8001_dev) 2316 atomic_dec(&pm8001_dev->running_req); 2317 break; 2318 case IO_NO_DEVICE: 2319 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 2320 ts->resp = SAS_TASK_UNDELIVERED; 2321 ts->stat = SAS_PHY_DOWN; 2322 if (pm8001_dev) 2323 atomic_dec(&pm8001_dev->running_req); 2324 break; 2325 case IO_XFER_ERROR_BREAK: 2326 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2327 ts->resp = SAS_TASK_COMPLETE; 2328 ts->stat = SAS_INTERRUPTED; 2329 if (pm8001_dev) 2330 atomic_dec(&pm8001_dev->running_req); 2331 break; 2332 case IO_XFER_ERROR_PHY_NOT_READY: 2333 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2334 ts->resp = SAS_TASK_COMPLETE; 2335 ts->stat = SAS_OPEN_REJECT; 2336 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2337 if (pm8001_dev) 2338 atomic_dec(&pm8001_dev->running_req); 2339 break; 2340 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2341 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2342 ts->resp = SAS_TASK_COMPLETE; 2343 ts->stat = SAS_OPEN_REJECT; 2344 ts->open_rej_reason = SAS_OREJ_EPROTO; 2345 if (pm8001_dev) 2346 atomic_dec(&pm8001_dev->running_req); 2347 break; 2348 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2349 pm8001_dbg(pm8001_ha, IO, 2350 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2351 ts->resp = SAS_TASK_COMPLETE; 2352 ts->stat = SAS_OPEN_REJECT; 2353 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2354 if (pm8001_dev) 2355 atomic_dec(&pm8001_dev->running_req); 2356 break; 2357 case IO_OPEN_CNX_ERROR_BREAK: 2358 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2359 ts->resp = SAS_TASK_COMPLETE; 2360 ts->stat = SAS_OPEN_REJECT; 2361 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2362 if (pm8001_dev) 2363 atomic_dec(&pm8001_dev->running_req); 2364 break; 2365 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2366 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2367 ts->resp = SAS_TASK_COMPLETE; 2368 ts->stat = SAS_DEV_NO_RESPONSE; 2369 if (!t->uldd_task) { 2370 pm8001_handle_event(pm8001_ha, 2371 pm8001_dev, 2372 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2373 ts->resp = SAS_TASK_UNDELIVERED; 2374 ts->stat = SAS_QUEUE_FULL; 2375 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2376 return; 2377 } 2378 break; 2379 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2380 pm8001_dbg(pm8001_ha, IO, 2381 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2382 ts->resp = SAS_TASK_UNDELIVERED; 2383 ts->stat = SAS_OPEN_REJECT; 2384 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2385 if (!t->uldd_task) { 2386 pm8001_handle_event(pm8001_ha, 2387 pm8001_dev, 2388 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2389 ts->resp = SAS_TASK_UNDELIVERED; 2390 ts->stat = SAS_QUEUE_FULL; 2391 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2392 return; 2393 } 2394 break; 2395 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2396 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2397 ts->resp = SAS_TASK_COMPLETE; 2398 ts->stat = SAS_OPEN_REJECT; 2399 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2400 if (pm8001_dev) 2401 atomic_dec(&pm8001_dev->running_req); 2402 break; 2403 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 2404 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"); 2405 ts->resp = SAS_TASK_COMPLETE; 2406 ts->stat = SAS_DEV_NO_RESPONSE; 2407 if (!t->uldd_task) { 2408 pm8001_handle_event(pm8001_ha, 2409 pm8001_dev, 2410 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY); 2411 ts->resp = SAS_TASK_UNDELIVERED; 2412 ts->stat = SAS_QUEUE_FULL; 2413 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2414 return; 2415 } 2416 break; 2417 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2418 pm8001_dbg(pm8001_ha, IO, 2419 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2420 ts->resp = SAS_TASK_COMPLETE; 2421 ts->stat = SAS_OPEN_REJECT; 2422 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2423 if (pm8001_dev) 2424 atomic_dec(&pm8001_dev->running_req); 2425 break; 2426 case IO_XFER_ERROR_NAK_RECEIVED: 2427 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2428 ts->resp = SAS_TASK_COMPLETE; 2429 ts->stat = SAS_NAK_R_ERR; 2430 if (pm8001_dev) 2431 atomic_dec(&pm8001_dev->running_req); 2432 break; 2433 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2434 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 2435 ts->resp = SAS_TASK_COMPLETE; 2436 ts->stat = SAS_NAK_R_ERR; 2437 if (pm8001_dev) 2438 atomic_dec(&pm8001_dev->running_req); 2439 break; 2440 case IO_XFER_ERROR_DMA: 2441 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n"); 2442 ts->resp = SAS_TASK_COMPLETE; 2443 ts->stat = SAS_ABORTED_TASK; 2444 if (pm8001_dev) 2445 atomic_dec(&pm8001_dev->running_req); 2446 break; 2447 case IO_XFER_ERROR_SATA_LINK_TIMEOUT: 2448 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"); 2449 ts->resp = SAS_TASK_UNDELIVERED; 2450 ts->stat = SAS_DEV_NO_RESPONSE; 2451 if (pm8001_dev) 2452 atomic_dec(&pm8001_dev->running_req); 2453 break; 2454 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2455 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n"); 2456 ts->resp = SAS_TASK_COMPLETE; 2457 ts->stat = SAS_DATA_UNDERRUN; 2458 if (pm8001_dev) 2459 atomic_dec(&pm8001_dev->running_req); 2460 break; 2461 case IO_XFER_OPEN_RETRY_TIMEOUT: 2462 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2463 ts->resp = SAS_TASK_COMPLETE; 2464 ts->stat = SAS_OPEN_TO; 2465 if (pm8001_dev) 2466 atomic_dec(&pm8001_dev->running_req); 2467 break; 2468 case IO_PORT_IN_RESET: 2469 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 2470 ts->resp = SAS_TASK_COMPLETE; 2471 ts->stat = SAS_DEV_NO_RESPONSE; 2472 if (pm8001_dev) 2473 atomic_dec(&pm8001_dev->running_req); 2474 break; 2475 case IO_DS_NON_OPERATIONAL: 2476 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 2477 ts->resp = SAS_TASK_COMPLETE; 2478 ts->stat = SAS_DEV_NO_RESPONSE; 2479 if (!t->uldd_task) { 2480 pm8001_handle_event(pm8001_ha, pm8001_dev, 2481 IO_DS_NON_OPERATIONAL); 2482 ts->resp = SAS_TASK_UNDELIVERED; 2483 ts->stat = SAS_QUEUE_FULL; 2484 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2485 return; 2486 } 2487 break; 2488 case IO_DS_IN_RECOVERY: 2489 pm8001_dbg(pm8001_ha, IO, " IO_DS_IN_RECOVERY\n"); 2490 ts->resp = SAS_TASK_COMPLETE; 2491 ts->stat = SAS_DEV_NO_RESPONSE; 2492 if (pm8001_dev) 2493 atomic_dec(&pm8001_dev->running_req); 2494 break; 2495 case IO_DS_IN_ERROR: 2496 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n"); 2497 ts->resp = SAS_TASK_COMPLETE; 2498 ts->stat = SAS_DEV_NO_RESPONSE; 2499 if (!t->uldd_task) { 2500 pm8001_handle_event(pm8001_ha, pm8001_dev, 2501 IO_DS_IN_ERROR); 2502 ts->resp = SAS_TASK_UNDELIVERED; 2503 ts->stat = SAS_QUEUE_FULL; 2504 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2505 return; 2506 } 2507 break; 2508 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2509 pm8001_dbg(pm8001_ha, IO, 2510 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 2511 ts->resp = SAS_TASK_COMPLETE; 2512 ts->stat = SAS_OPEN_REJECT; 2513 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2514 if (pm8001_dev) 2515 atomic_dec(&pm8001_dev->running_req); 2516 break; 2517 default: 2518 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status); 2519 /* not allowed case. Therefore, return failed status */ 2520 ts->resp = SAS_TASK_COMPLETE; 2521 ts->stat = SAS_DEV_NO_RESPONSE; 2522 if (pm8001_dev) 2523 atomic_dec(&pm8001_dev->running_req); 2524 break; 2525 } 2526 spin_lock_irqsave(&t->task_state_lock, flags); 2527 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2528 t->task_state_flags |= SAS_TASK_STATE_DONE; 2529 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2530 spin_unlock_irqrestore(&t->task_state_lock, flags); 2531 pm8001_dbg(pm8001_ha, FAIL, 2532 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2533 t, status, ts->resp, ts->stat); 2534 pm8001_ccb_task_free(pm8001_ha, ccb); 2535 } else { 2536 spin_unlock_irqrestore(&t->task_state_lock, flags); 2537 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2538 } 2539 } 2540 2541 /*See the comments for mpi_ssp_completion */ 2542 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 2543 { 2544 struct sas_task *t; 2545 struct task_status_struct *ts; 2546 struct pm8001_ccb_info *ccb; 2547 struct pm8001_device *pm8001_dev; 2548 struct sata_event_resp *psataPayload = 2549 (struct sata_event_resp *)(piomb + 4); 2550 u32 event = le32_to_cpu(psataPayload->event); 2551 u32 tag = le32_to_cpu(psataPayload->tag); 2552 u32 port_id = le32_to_cpu(psataPayload->port_id); 2553 u32 dev_id = le32_to_cpu(psataPayload->device_id); 2554 2555 if (event) 2556 pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event); 2557 2558 /* Check if this is NCQ error */ 2559 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) { 2560 /* find device using device id */ 2561 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id); 2562 if (pm8001_dev) 2563 pm8001_handle_event(pm8001_ha, 2564 pm8001_dev, 2565 IO_XFER_ERROR_ABORTED_NCQ_MODE); 2566 return; 2567 } 2568 2569 ccb = &pm8001_ha->ccb_info[tag]; 2570 t = ccb->task; 2571 pm8001_dev = ccb->device; 2572 if (event) 2573 pm8001_dbg(pm8001_ha, FAIL, "sata IO status 0x%x\n", event); 2574 2575 if (unlikely(!t)) { 2576 pm8001_dbg(pm8001_ha, FAIL, "task null, freeing CCB tag %d\n", 2577 ccb->ccb_tag); 2578 pm8001_ccb_free(pm8001_ha, ccb); 2579 return; 2580 } 2581 2582 if (unlikely(!t->lldd_task || !t->dev)) 2583 return; 2584 2585 ts = &t->task_status; 2586 pm8001_dbg(pm8001_ha, DEVIO, 2587 "port_id:0x%x, device_id:0x%x, tag:0x%x, event:0x%x\n", 2588 port_id, dev_id, tag, event); 2589 switch (event) { 2590 case IO_OVERFLOW: 2591 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 2592 ts->resp = SAS_TASK_COMPLETE; 2593 ts->stat = SAS_DATA_OVERRUN; 2594 ts->residual = 0; 2595 break; 2596 case IO_XFER_ERROR_BREAK: 2597 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2598 ts->resp = SAS_TASK_COMPLETE; 2599 ts->stat = SAS_INTERRUPTED; 2600 break; 2601 case IO_XFER_ERROR_PHY_NOT_READY: 2602 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2603 ts->resp = SAS_TASK_COMPLETE; 2604 ts->stat = SAS_OPEN_REJECT; 2605 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2606 break; 2607 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2608 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2609 ts->resp = SAS_TASK_COMPLETE; 2610 ts->stat = SAS_OPEN_REJECT; 2611 ts->open_rej_reason = SAS_OREJ_EPROTO; 2612 break; 2613 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2614 pm8001_dbg(pm8001_ha, IO, 2615 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2616 ts->resp = SAS_TASK_COMPLETE; 2617 ts->stat = SAS_OPEN_REJECT; 2618 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2619 break; 2620 case IO_OPEN_CNX_ERROR_BREAK: 2621 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2622 ts->resp = SAS_TASK_COMPLETE; 2623 ts->stat = SAS_OPEN_REJECT; 2624 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2625 break; 2626 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2627 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2628 ts->resp = SAS_TASK_UNDELIVERED; 2629 ts->stat = SAS_DEV_NO_RESPONSE; 2630 if (!t->uldd_task) { 2631 pm8001_handle_event(pm8001_ha, 2632 pm8001_dev, 2633 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2634 ts->resp = SAS_TASK_COMPLETE; 2635 ts->stat = SAS_QUEUE_FULL; 2636 return; 2637 } 2638 break; 2639 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2640 pm8001_dbg(pm8001_ha, IO, 2641 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2642 ts->resp = SAS_TASK_UNDELIVERED; 2643 ts->stat = SAS_OPEN_REJECT; 2644 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2645 break; 2646 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2647 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2648 ts->resp = SAS_TASK_COMPLETE; 2649 ts->stat = SAS_OPEN_REJECT; 2650 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2651 break; 2652 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2653 pm8001_dbg(pm8001_ha, IO, 2654 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2655 ts->resp = SAS_TASK_COMPLETE; 2656 ts->stat = SAS_OPEN_REJECT; 2657 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2658 break; 2659 case IO_XFER_ERROR_NAK_RECEIVED: 2660 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2661 ts->resp = SAS_TASK_COMPLETE; 2662 ts->stat = SAS_NAK_R_ERR; 2663 break; 2664 case IO_XFER_ERROR_PEER_ABORTED: 2665 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n"); 2666 ts->resp = SAS_TASK_COMPLETE; 2667 ts->stat = SAS_NAK_R_ERR; 2668 break; 2669 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2670 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n"); 2671 ts->resp = SAS_TASK_COMPLETE; 2672 ts->stat = SAS_DATA_UNDERRUN; 2673 break; 2674 case IO_XFER_OPEN_RETRY_TIMEOUT: 2675 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2676 ts->resp = SAS_TASK_COMPLETE; 2677 ts->stat = SAS_OPEN_TO; 2678 break; 2679 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2680 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n"); 2681 ts->resp = SAS_TASK_COMPLETE; 2682 ts->stat = SAS_OPEN_TO; 2683 break; 2684 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2685 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n"); 2686 ts->resp = SAS_TASK_COMPLETE; 2687 ts->stat = SAS_OPEN_TO; 2688 break; 2689 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2690 pm8001_dbg(pm8001_ha, IO, 2691 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"); 2692 ts->resp = SAS_TASK_COMPLETE; 2693 ts->stat = SAS_OPEN_TO; 2694 break; 2695 case IO_XFER_ERROR_OFFSET_MISMATCH: 2696 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 2697 ts->resp = SAS_TASK_COMPLETE; 2698 ts->stat = SAS_OPEN_TO; 2699 break; 2700 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2701 pm8001_dbg(pm8001_ha, IO, 2702 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"); 2703 ts->resp = SAS_TASK_COMPLETE; 2704 ts->stat = SAS_OPEN_TO; 2705 break; 2706 case IO_XFER_CMD_FRAME_ISSUED: 2707 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n"); 2708 break; 2709 case IO_XFER_PIO_SETUP_ERROR: 2710 pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n"); 2711 ts->resp = SAS_TASK_COMPLETE; 2712 ts->stat = SAS_OPEN_TO; 2713 break; 2714 default: 2715 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event); 2716 /* not allowed case. Therefore, return failed status */ 2717 ts->resp = SAS_TASK_COMPLETE; 2718 ts->stat = SAS_OPEN_TO; 2719 break; 2720 } 2721 } 2722 2723 /*See the comments for mpi_ssp_completion */ 2724 static void 2725 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2726 { 2727 struct sas_task *t; 2728 struct pm8001_ccb_info *ccb; 2729 unsigned long flags; 2730 u32 status; 2731 u32 tag; 2732 struct smp_completion_resp *psmpPayload; 2733 struct task_status_struct *ts; 2734 struct pm8001_device *pm8001_dev; 2735 2736 psmpPayload = (struct smp_completion_resp *)(piomb + 4); 2737 status = le32_to_cpu(psmpPayload->status); 2738 tag = le32_to_cpu(psmpPayload->tag); 2739 2740 ccb = &pm8001_ha->ccb_info[tag]; 2741 t = ccb->task; 2742 ts = &t->task_status; 2743 pm8001_dev = ccb->device; 2744 if (status) { 2745 pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status); 2746 pm8001_dbg(pm8001_ha, IOERR, 2747 "status:0x%x, tag:0x%x, task:0x%p\n", 2748 status, tag, t); 2749 } 2750 if (unlikely(!t || !t->lldd_task || !t->dev)) 2751 return; 2752 2753 switch (status) { 2754 case IO_SUCCESS: 2755 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n"); 2756 ts->resp = SAS_TASK_COMPLETE; 2757 ts->stat = SAS_SAM_STAT_GOOD; 2758 if (pm8001_dev) 2759 atomic_dec(&pm8001_dev->running_req); 2760 break; 2761 case IO_ABORTED: 2762 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n"); 2763 ts->resp = SAS_TASK_COMPLETE; 2764 ts->stat = SAS_ABORTED_TASK; 2765 if (pm8001_dev) 2766 atomic_dec(&pm8001_dev->running_req); 2767 break; 2768 case IO_OVERFLOW: 2769 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 2770 ts->resp = SAS_TASK_COMPLETE; 2771 ts->stat = SAS_DATA_OVERRUN; 2772 ts->residual = 0; 2773 if (pm8001_dev) 2774 atomic_dec(&pm8001_dev->running_req); 2775 break; 2776 case IO_NO_DEVICE: 2777 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 2778 ts->resp = SAS_TASK_COMPLETE; 2779 ts->stat = SAS_PHY_DOWN; 2780 break; 2781 case IO_ERROR_HW_TIMEOUT: 2782 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n"); 2783 ts->resp = SAS_TASK_COMPLETE; 2784 ts->stat = SAS_SAM_STAT_BUSY; 2785 break; 2786 case IO_XFER_ERROR_BREAK: 2787 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2788 ts->resp = SAS_TASK_COMPLETE; 2789 ts->stat = SAS_SAM_STAT_BUSY; 2790 break; 2791 case IO_XFER_ERROR_PHY_NOT_READY: 2792 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2793 ts->resp = SAS_TASK_COMPLETE; 2794 ts->stat = SAS_SAM_STAT_BUSY; 2795 break; 2796 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2797 pm8001_dbg(pm8001_ha, IO, 2798 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2799 ts->resp = SAS_TASK_COMPLETE; 2800 ts->stat = SAS_OPEN_REJECT; 2801 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2802 break; 2803 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2804 pm8001_dbg(pm8001_ha, IO, 2805 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2806 ts->resp = SAS_TASK_COMPLETE; 2807 ts->stat = SAS_OPEN_REJECT; 2808 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2809 break; 2810 case IO_OPEN_CNX_ERROR_BREAK: 2811 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2812 ts->resp = SAS_TASK_COMPLETE; 2813 ts->stat = SAS_OPEN_REJECT; 2814 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2815 break; 2816 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2817 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2818 ts->resp = SAS_TASK_COMPLETE; 2819 ts->stat = SAS_OPEN_REJECT; 2820 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2821 pm8001_handle_event(pm8001_ha, 2822 pm8001_dev, 2823 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2824 break; 2825 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2826 pm8001_dbg(pm8001_ha, IO, 2827 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2828 ts->resp = SAS_TASK_COMPLETE; 2829 ts->stat = SAS_OPEN_REJECT; 2830 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2831 break; 2832 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2833 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2834 ts->resp = SAS_TASK_COMPLETE; 2835 ts->stat = SAS_OPEN_REJECT; 2836 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2837 break; 2838 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2839 pm8001_dbg(pm8001_ha, IO, 2840 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2841 ts->resp = SAS_TASK_COMPLETE; 2842 ts->stat = SAS_OPEN_REJECT; 2843 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2844 break; 2845 case IO_XFER_ERROR_RX_FRAME: 2846 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n"); 2847 ts->resp = SAS_TASK_COMPLETE; 2848 ts->stat = SAS_DEV_NO_RESPONSE; 2849 break; 2850 case IO_XFER_OPEN_RETRY_TIMEOUT: 2851 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2852 ts->resp = SAS_TASK_COMPLETE; 2853 ts->stat = SAS_OPEN_REJECT; 2854 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2855 break; 2856 case IO_ERROR_INTERNAL_SMP_RESOURCE: 2857 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n"); 2858 ts->resp = SAS_TASK_COMPLETE; 2859 ts->stat = SAS_QUEUE_FULL; 2860 break; 2861 case IO_PORT_IN_RESET: 2862 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 2863 ts->resp = SAS_TASK_COMPLETE; 2864 ts->stat = SAS_OPEN_REJECT; 2865 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2866 break; 2867 case IO_DS_NON_OPERATIONAL: 2868 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 2869 ts->resp = SAS_TASK_COMPLETE; 2870 ts->stat = SAS_DEV_NO_RESPONSE; 2871 break; 2872 case IO_DS_IN_RECOVERY: 2873 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n"); 2874 ts->resp = SAS_TASK_COMPLETE; 2875 ts->stat = SAS_OPEN_REJECT; 2876 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2877 break; 2878 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2879 pm8001_dbg(pm8001_ha, IO, 2880 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 2881 ts->resp = SAS_TASK_COMPLETE; 2882 ts->stat = SAS_OPEN_REJECT; 2883 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2884 break; 2885 default: 2886 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status); 2887 ts->resp = SAS_TASK_COMPLETE; 2888 ts->stat = SAS_DEV_NO_RESPONSE; 2889 /* not allowed case. Therefore, return failed status */ 2890 break; 2891 } 2892 spin_lock_irqsave(&t->task_state_lock, flags); 2893 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2894 t->task_state_flags |= SAS_TASK_STATE_DONE; 2895 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2896 spin_unlock_irqrestore(&t->task_state_lock, flags); 2897 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2898 t, status, ts->resp, ts->stat); 2899 pm8001_ccb_task_free(pm8001_ha, ccb); 2900 } else { 2901 spin_unlock_irqrestore(&t->task_state_lock, flags); 2902 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2903 } 2904 } 2905 2906 void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha, 2907 void *piomb) 2908 { 2909 struct set_dev_state_resp *pPayload = 2910 (struct set_dev_state_resp *)(piomb + 4); 2911 u32 tag = le32_to_cpu(pPayload->tag); 2912 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 2913 struct pm8001_device *pm8001_dev = ccb->device; 2914 u32 status = le32_to_cpu(pPayload->status); 2915 u32 device_id = le32_to_cpu(pPayload->device_id); 2916 u8 pds = le32_to_cpu(pPayload->pds_nds) & PDS_BITS; 2917 u8 nds = le32_to_cpu(pPayload->pds_nds) & NDS_BITS; 2918 2919 pm8001_dbg(pm8001_ha, MSG, 2920 "Set device id = 0x%x state from 0x%x to 0x%x status = 0x%x!\n", 2921 device_id, pds, nds, status); 2922 complete(pm8001_dev->setds_completion); 2923 pm8001_ccb_free(pm8001_ha, ccb); 2924 } 2925 2926 void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 2927 { 2928 struct get_nvm_data_resp *pPayload = 2929 (struct get_nvm_data_resp *)(piomb + 4); 2930 u32 tag = le32_to_cpu(pPayload->tag); 2931 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 2932 u32 dlen_status = le32_to_cpu(pPayload->dlen_status); 2933 2934 complete(pm8001_ha->nvmd_completion); 2935 pm8001_dbg(pm8001_ha, MSG, "Set nvm data complete!\n"); 2936 if ((dlen_status & NVMD_STAT) != 0) { 2937 pm8001_dbg(pm8001_ha, FAIL, "Set nvm data error %x\n", 2938 dlen_status); 2939 } 2940 pm8001_ccb_free(pm8001_ha, ccb); 2941 } 2942 2943 void 2944 pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 2945 { 2946 struct fw_control_ex *fw_control_context; 2947 struct get_nvm_data_resp *pPayload = 2948 (struct get_nvm_data_resp *)(piomb + 4); 2949 u32 tag = le32_to_cpu(pPayload->tag); 2950 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 2951 u32 dlen_status = le32_to_cpu(pPayload->dlen_status); 2952 u32 ir_tds_bn_dps_das_nvm = 2953 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm); 2954 void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr; 2955 fw_control_context = ccb->fw_control_context; 2956 2957 pm8001_dbg(pm8001_ha, MSG, "Get nvm data complete!\n"); 2958 if ((dlen_status & NVMD_STAT) != 0) { 2959 pm8001_dbg(pm8001_ha, FAIL, "Get nvm data error %x\n", 2960 dlen_status); 2961 complete(pm8001_ha->nvmd_completion); 2962 /* We should free tag during failure also, the tag is not being 2963 * freed by requesting path anywhere. 2964 */ 2965 pm8001_ccb_free(pm8001_ha, ccb); 2966 return; 2967 } 2968 if (ir_tds_bn_dps_das_nvm & IPMode) { 2969 /* indirect mode - IR bit set */ 2970 pm8001_dbg(pm8001_ha, MSG, "Get NVMD success, IR=1\n"); 2971 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) { 2972 if (ir_tds_bn_dps_das_nvm == 0x80a80200) { 2973 memcpy(pm8001_ha->sas_addr, 2974 ((u8 *)virt_addr + 4), 2975 SAS_ADDR_SIZE); 2976 pm8001_dbg(pm8001_ha, MSG, "Get SAS address from VPD successfully!\n"); 2977 } 2978 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM) 2979 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) || 2980 ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) { 2981 ; 2982 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP) 2983 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) { 2984 ; 2985 } else { 2986 /* Should not be happened*/ 2987 pm8001_dbg(pm8001_ha, MSG, 2988 "(IR=1)Wrong Device type 0x%x\n", 2989 ir_tds_bn_dps_das_nvm); 2990 } 2991 } else /* direct mode */{ 2992 pm8001_dbg(pm8001_ha, MSG, 2993 "Get NVMD success, IR=0, dataLen=%d\n", 2994 (dlen_status & NVMD_LEN) >> 24); 2995 } 2996 /* Though fw_control_context is freed below, usrAddr still needs 2997 * to be updated as this holds the response to the request function 2998 */ 2999 memcpy(fw_control_context->usrAddr, 3000 pm8001_ha->memoryMap.region[NVMD].virt_ptr, 3001 fw_control_context->len); 3002 kfree(ccb->fw_control_context); 3003 /* To avoid race condition, complete should be 3004 * called after the message is copied to 3005 * fw_control_context->usrAddr 3006 */ 3007 complete(pm8001_ha->nvmd_completion); 3008 pm8001_dbg(pm8001_ha, MSG, "Get nvmd data complete!\n"); 3009 pm8001_ccb_free(pm8001_ha, ccb); 3010 } 3011 3012 int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb) 3013 { 3014 u32 tag; 3015 struct local_phy_ctl_resp *pPayload = 3016 (struct local_phy_ctl_resp *)(piomb + 4); 3017 u32 status = le32_to_cpu(pPayload->status); 3018 u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS; 3019 u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS; 3020 tag = le32_to_cpu(pPayload->tag); 3021 if (status != 0) { 3022 pm8001_dbg(pm8001_ha, MSG, 3023 "%x phy execute %x phy op failed!\n", 3024 phy_id, phy_op); 3025 } else { 3026 pm8001_dbg(pm8001_ha, MSG, 3027 "%x phy execute %x phy op success!\n", 3028 phy_id, phy_op); 3029 pm8001_ha->phy[phy_id].reset_success = true; 3030 } 3031 if (pm8001_ha->phy[phy_id].enable_completion) { 3032 complete(pm8001_ha->phy[phy_id].enable_completion); 3033 pm8001_ha->phy[phy_id].enable_completion = NULL; 3034 } 3035 pm8001_tag_free(pm8001_ha, tag); 3036 return 0; 3037 } 3038 3039 /** 3040 * pm8001_bytes_dmaed - one of the interface function communication with libsas 3041 * @pm8001_ha: our hba card information 3042 * @i: which phy that received the event. 3043 * 3044 * when HBA driver received the identify done event or initiate FIS received 3045 * event(for SATA), it will invoke this function to notify the sas layer that 3046 * the sas toplogy has formed, please discover the whole sas domain, 3047 * while receive a broadcast(change) primitive just tell the sas 3048 * layer to discover the changed domain rather than the whole domain. 3049 */ 3050 void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i) 3051 { 3052 struct pm8001_phy *phy = &pm8001_ha->phy[i]; 3053 struct asd_sas_phy *sas_phy = &phy->sas_phy; 3054 if (!phy->phy_attached) 3055 return; 3056 3057 if (phy->phy_type & PORT_TYPE_SAS) { 3058 struct sas_identify_frame *id; 3059 id = (struct sas_identify_frame *)phy->frame_rcvd; 3060 id->dev_type = phy->identify.device_type; 3061 id->initiator_bits = SAS_PROTOCOL_ALL; 3062 id->target_bits = phy->identify.target_port_protocols; 3063 } else if (phy->phy_type & PORT_TYPE_SATA) { 3064 /*Nothing*/ 3065 } 3066 pm8001_dbg(pm8001_ha, MSG, "phy %d byte dmaded.\n", i); 3067 3068 sas_phy->frame_rcvd_size = phy->frame_rcvd_size; 3069 sas_notify_port_event(sas_phy, PORTE_BYTES_DMAED, GFP_ATOMIC); 3070 } 3071 3072 /* Get the link rate speed */ 3073 void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate) 3074 { 3075 struct sas_phy *sas_phy = phy->sas_phy.phy; 3076 3077 switch (link_rate) { 3078 case PHY_SPEED_120: 3079 phy->sas_phy.linkrate = SAS_LINK_RATE_12_0_GBPS; 3080 break; 3081 case PHY_SPEED_60: 3082 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS; 3083 break; 3084 case PHY_SPEED_30: 3085 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS; 3086 break; 3087 case PHY_SPEED_15: 3088 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS; 3089 break; 3090 } 3091 sas_phy->negotiated_linkrate = phy->sas_phy.linkrate; 3092 sas_phy->maximum_linkrate_hw = phy->maximum_linkrate; 3093 sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS; 3094 sas_phy->maximum_linkrate = phy->maximum_linkrate; 3095 sas_phy->minimum_linkrate = phy->minimum_linkrate; 3096 } 3097 3098 /** 3099 * pm8001_get_attached_sas_addr - extract/generate attached SAS address 3100 * @phy: pointer to asd_phy 3101 * @sas_addr: pointer to buffer where the SAS address is to be written 3102 * 3103 * This function extracts the SAS address from an IDENTIFY frame 3104 * received. If OOB is SATA, then a SAS address is generated from the 3105 * HA tables. 3106 * 3107 * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame 3108 * buffer. 3109 */ 3110 void pm8001_get_attached_sas_addr(struct pm8001_phy *phy, 3111 u8 *sas_addr) 3112 { 3113 if (phy->sas_phy.frame_rcvd[0] == 0x34 3114 && phy->sas_phy.oob_mode == SATA_OOB_MODE) { 3115 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha; 3116 /* FIS device-to-host */ 3117 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr); 3118 addr += phy->sas_phy.id; 3119 *(__be64 *)sas_addr = cpu_to_be64(addr); 3120 } else { 3121 struct sas_identify_frame *idframe = 3122 (void *) phy->sas_phy.frame_rcvd; 3123 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE); 3124 } 3125 } 3126 3127 /** 3128 * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW. 3129 * @pm8001_ha: our hba card information 3130 * @Qnum: the outbound queue message number. 3131 * @SEA: source of event to ack 3132 * @port_id: port id. 3133 * @phyId: phy id. 3134 * @param0: parameter 0. 3135 * @param1: parameter 1. 3136 */ 3137 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha, 3138 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1) 3139 { 3140 struct hw_event_ack_req payload; 3141 u32 opc = OPC_INB_SAS_HW_EVENT_ACK; 3142 3143 memset((u8 *)&payload, 0, sizeof(payload)); 3144 payload.tag = cpu_to_le32(1); 3145 payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) | 3146 ((phyId & 0x0F) << 4) | (port_id & 0x0F)); 3147 payload.param0 = cpu_to_le32(param0); 3148 payload.param1 = cpu_to_le32(param1); 3149 3150 pm8001_mpi_build_cmd(pm8001_ha, Qnum, opc, &payload, sizeof(payload), 0); 3151 } 3152 3153 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 3154 u32 phyId, u32 phy_op); 3155 3156 /** 3157 * hw_event_sas_phy_up -FW tells me a SAS phy up event. 3158 * @pm8001_ha: our hba card information 3159 * @piomb: IO message buffer 3160 */ 3161 static void 3162 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3163 { 3164 struct hw_event_resp *pPayload = 3165 (struct hw_event_resp *)(piomb + 4); 3166 u32 lr_evt_status_phyid_portid = 3167 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3168 u8 link_rate = 3169 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28); 3170 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3171 u8 phy_id = 3172 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3173 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate); 3174 u8 portstate = (u8)(npip_portstate & 0x0000000F); 3175 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3176 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3177 unsigned long flags; 3178 u8 deviceType = pPayload->sas_identify.dev_type; 3179 phy->port = port; 3180 port->port_id = port_id; 3181 port->port_state = portstate; 3182 phy->phy_state = PHY_STATE_LINK_UP_SPC; 3183 pm8001_dbg(pm8001_ha, MSG, 3184 "HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n", 3185 port_id, phy_id); 3186 3187 switch (deviceType) { 3188 case SAS_PHY_UNUSED: 3189 pm8001_dbg(pm8001_ha, MSG, "device type no device.\n"); 3190 break; 3191 case SAS_END_DEVICE: 3192 pm8001_dbg(pm8001_ha, MSG, "end device.\n"); 3193 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id, 3194 PHY_NOTIFY_ENABLE_SPINUP); 3195 port->port_attached = 1; 3196 pm8001_get_lrate_mode(phy, link_rate); 3197 break; 3198 case SAS_EDGE_EXPANDER_DEVICE: 3199 pm8001_dbg(pm8001_ha, MSG, "expander device.\n"); 3200 port->port_attached = 1; 3201 pm8001_get_lrate_mode(phy, link_rate); 3202 break; 3203 case SAS_FANOUT_EXPANDER_DEVICE: 3204 pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n"); 3205 port->port_attached = 1; 3206 pm8001_get_lrate_mode(phy, link_rate); 3207 break; 3208 default: 3209 pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n", 3210 deviceType); 3211 break; 3212 } 3213 phy->phy_type |= PORT_TYPE_SAS; 3214 phy->identify.device_type = deviceType; 3215 phy->phy_attached = 1; 3216 if (phy->identify.device_type == SAS_END_DEVICE) 3217 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP; 3218 else if (phy->identify.device_type != SAS_PHY_UNUSED) 3219 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP; 3220 phy->sas_phy.oob_mode = SAS_OOB_MODE; 3221 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC); 3222 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3223 memcpy(phy->frame_rcvd, &pPayload->sas_identify, 3224 sizeof(struct sas_identify_frame)-4); 3225 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4; 3226 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3227 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3228 if (pm8001_ha->flags == PM8001F_RUN_TIME) 3229 mdelay(200);/*delay a moment to wait disk to spinup*/ 3230 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3231 } 3232 3233 /** 3234 * hw_event_sata_phy_up -FW tells me a SATA phy up event. 3235 * @pm8001_ha: our hba card information 3236 * @piomb: IO message buffer 3237 */ 3238 static void 3239 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3240 { 3241 struct hw_event_resp *pPayload = 3242 (struct hw_event_resp *)(piomb + 4); 3243 u32 lr_evt_status_phyid_portid = 3244 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3245 u8 link_rate = 3246 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28); 3247 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3248 u8 phy_id = 3249 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3250 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate); 3251 u8 portstate = (u8)(npip_portstate & 0x0000000F); 3252 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3253 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3254 unsigned long flags; 3255 pm8001_dbg(pm8001_ha, DEVIO, "HW_EVENT_SATA_PHY_UP port id = %d, phy id = %d\n", 3256 port_id, phy_id); 3257 phy->port = port; 3258 port->port_id = port_id; 3259 port->port_state = portstate; 3260 phy->phy_state = PHY_STATE_LINK_UP_SPC; 3261 port->port_attached = 1; 3262 pm8001_get_lrate_mode(phy, link_rate); 3263 phy->phy_type |= PORT_TYPE_SATA; 3264 phy->phy_attached = 1; 3265 phy->sas_phy.oob_mode = SATA_OOB_MODE; 3266 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC); 3267 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3268 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4), 3269 sizeof(struct dev_to_host_fis)); 3270 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 3271 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 3272 phy->identify.device_type = SAS_SATA_DEV; 3273 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3274 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3275 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3276 } 3277 3278 /** 3279 * hw_event_phy_down -we should notify the libsas the phy is down. 3280 * @pm8001_ha: our hba card information 3281 * @piomb: IO message buffer 3282 */ 3283 static void 3284 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb) 3285 { 3286 struct hw_event_resp *pPayload = 3287 (struct hw_event_resp *)(piomb + 4); 3288 u32 lr_evt_status_phyid_portid = 3289 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3290 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3291 u8 phy_id = 3292 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3293 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate); 3294 u8 portstate = (u8)(npip_portstate & 0x0000000F); 3295 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3296 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3297 port->port_state = portstate; 3298 phy->phy_type = 0; 3299 phy->identify.device_type = 0; 3300 phy->phy_attached = 0; 3301 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE); 3302 switch (portstate) { 3303 case PORT_VALID: 3304 break; 3305 case PORT_INVALID: 3306 pm8001_dbg(pm8001_ha, MSG, " PortInvalid portID %d\n", 3307 port_id); 3308 pm8001_dbg(pm8001_ha, MSG, 3309 " Last phy Down and port invalid\n"); 3310 port->port_attached = 0; 3311 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3312 port_id, phy_id, 0, 0); 3313 break; 3314 case PORT_IN_RESET: 3315 pm8001_dbg(pm8001_ha, MSG, " Port In Reset portID %d\n", 3316 port_id); 3317 break; 3318 case PORT_NOT_ESTABLISHED: 3319 pm8001_dbg(pm8001_ha, MSG, 3320 " phy Down and PORT_NOT_ESTABLISHED\n"); 3321 port->port_attached = 0; 3322 break; 3323 case PORT_LOSTCOMM: 3324 pm8001_dbg(pm8001_ha, MSG, " phy Down and PORT_LOSTCOMM\n"); 3325 pm8001_dbg(pm8001_ha, MSG, 3326 " Last phy Down and port invalid\n"); 3327 port->port_attached = 0; 3328 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3329 port_id, phy_id, 0, 0); 3330 break; 3331 default: 3332 port->port_attached = 0; 3333 pm8001_dbg(pm8001_ha, DEVIO, " phy Down and(default) = %x\n", 3334 portstate); 3335 break; 3336 3337 } 3338 } 3339 3340 /** 3341 * pm8001_mpi_reg_resp -process register device ID response. 3342 * @pm8001_ha: our hba card information 3343 * @piomb: IO message buffer 3344 * 3345 * when sas layer find a device it will notify LLDD, then the driver register 3346 * the domain device to FW, this event is the return device ID which the FW 3347 * has assigned, from now, inter-communication with FW is no longer using the 3348 * SAS address, use device ID which FW assigned. 3349 */ 3350 int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3351 { 3352 u32 status; 3353 u32 device_id; 3354 u32 htag; 3355 struct pm8001_ccb_info *ccb; 3356 struct pm8001_device *pm8001_dev; 3357 struct dev_reg_resp *registerRespPayload = 3358 (struct dev_reg_resp *)(piomb + 4); 3359 3360 htag = le32_to_cpu(registerRespPayload->tag); 3361 ccb = &pm8001_ha->ccb_info[htag]; 3362 pm8001_dev = ccb->device; 3363 status = le32_to_cpu(registerRespPayload->status); 3364 device_id = le32_to_cpu(registerRespPayload->device_id); 3365 pm8001_dbg(pm8001_ha, INIT, 3366 "register device status %d phy_id 0x%x device_id %d\n", 3367 status, pm8001_dev->attached_phy, device_id); 3368 switch (status) { 3369 case DEVREG_SUCCESS: 3370 pm8001_dbg(pm8001_ha, MSG, "DEVREG_SUCCESS\n"); 3371 pm8001_dev->device_id = device_id; 3372 break; 3373 case DEVREG_FAILURE_OUT_OF_RESOURCE: 3374 pm8001_dbg(pm8001_ha, MSG, "DEVREG_FAILURE_OUT_OF_RESOURCE\n"); 3375 break; 3376 case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED: 3377 pm8001_dbg(pm8001_ha, MSG, 3378 "DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n"); 3379 break; 3380 case DEVREG_FAILURE_INVALID_PHY_ID: 3381 pm8001_dbg(pm8001_ha, MSG, "DEVREG_FAILURE_INVALID_PHY_ID\n"); 3382 break; 3383 case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED: 3384 pm8001_dbg(pm8001_ha, MSG, 3385 "DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n"); 3386 break; 3387 case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE: 3388 pm8001_dbg(pm8001_ha, MSG, 3389 "DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n"); 3390 break; 3391 case DEVREG_FAILURE_PORT_NOT_VALID_STATE: 3392 pm8001_dbg(pm8001_ha, MSG, 3393 "DEVREG_FAILURE_PORT_NOT_VALID_STATE\n"); 3394 break; 3395 case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID: 3396 pm8001_dbg(pm8001_ha, MSG, 3397 "DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n"); 3398 break; 3399 default: 3400 pm8001_dbg(pm8001_ha, MSG, 3401 "DEVREG_FAILURE_DEVICE_TYPE_NOT_SUPPORTED\n"); 3402 break; 3403 } 3404 complete(pm8001_dev->dcompletion); 3405 pm8001_ccb_free(pm8001_ha, ccb); 3406 return 0; 3407 } 3408 3409 int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3410 { 3411 u32 status; 3412 u32 device_id; 3413 struct dev_reg_resp *registerRespPayload = 3414 (struct dev_reg_resp *)(piomb + 4); 3415 3416 status = le32_to_cpu(registerRespPayload->status); 3417 device_id = le32_to_cpu(registerRespPayload->device_id); 3418 if (status != 0) 3419 pm8001_dbg(pm8001_ha, MSG, 3420 " deregister device failed ,status = %x, device_id = %x\n", 3421 status, device_id); 3422 return 0; 3423 } 3424 3425 /** 3426 * pm8001_mpi_fw_flash_update_resp - Response from FW for flash update command. 3427 * @pm8001_ha: our hba card information 3428 * @piomb: IO message buffer 3429 */ 3430 int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha, 3431 void *piomb) 3432 { 3433 u32 status; 3434 struct fw_flash_Update_resp *ppayload = 3435 (struct fw_flash_Update_resp *)(piomb + 4); 3436 u32 tag = le32_to_cpu(ppayload->tag); 3437 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 3438 3439 status = le32_to_cpu(ppayload->status); 3440 switch (status) { 3441 case FLASH_UPDATE_COMPLETE_PENDING_REBOOT: 3442 pm8001_dbg(pm8001_ha, MSG, 3443 ": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n"); 3444 break; 3445 case FLASH_UPDATE_IN_PROGRESS: 3446 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_IN_PROGRESS\n"); 3447 break; 3448 case FLASH_UPDATE_HDR_ERR: 3449 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_HDR_ERR\n"); 3450 break; 3451 case FLASH_UPDATE_OFFSET_ERR: 3452 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_OFFSET_ERR\n"); 3453 break; 3454 case FLASH_UPDATE_CRC_ERR: 3455 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_CRC_ERR\n"); 3456 break; 3457 case FLASH_UPDATE_LENGTH_ERR: 3458 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_LENGTH_ERR\n"); 3459 break; 3460 case FLASH_UPDATE_HW_ERR: 3461 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_HW_ERR\n"); 3462 break; 3463 case FLASH_UPDATE_DNLD_NOT_SUPPORTED: 3464 pm8001_dbg(pm8001_ha, MSG, 3465 ": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n"); 3466 break; 3467 case FLASH_UPDATE_DISABLED: 3468 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_DISABLED\n"); 3469 break; 3470 default: 3471 pm8001_dbg(pm8001_ha, DEVIO, "No matched status = %d\n", 3472 status); 3473 break; 3474 } 3475 kfree(ccb->fw_control_context); 3476 pm8001_ccb_free(pm8001_ha, ccb); 3477 complete(pm8001_ha->nvmd_completion); 3478 return 0; 3479 } 3480 3481 int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 3482 { 3483 u32 status; 3484 int i; 3485 struct general_event_resp *pPayload = 3486 (struct general_event_resp *)(piomb + 4); 3487 status = le32_to_cpu(pPayload->status); 3488 pm8001_dbg(pm8001_ha, MSG, " status = 0x%x\n", status); 3489 for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++) 3490 pm8001_dbg(pm8001_ha, MSG, "inb_IOMB_payload[0x%x] 0x%x,\n", 3491 i, 3492 pPayload->inb_IOMB_payload[i]); 3493 return 0; 3494 } 3495 3496 int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3497 { 3498 struct sas_task *t; 3499 struct pm8001_ccb_info *ccb; 3500 unsigned long flags; 3501 u32 status ; 3502 u32 tag, scp; 3503 struct task_status_struct *ts; 3504 struct pm8001_device *pm8001_dev; 3505 3506 struct task_abort_resp *pPayload = 3507 (struct task_abort_resp *)(piomb + 4); 3508 3509 status = le32_to_cpu(pPayload->status); 3510 tag = le32_to_cpu(pPayload->tag); 3511 3512 scp = le32_to_cpu(pPayload->scp); 3513 ccb = &pm8001_ha->ccb_info[tag]; 3514 t = ccb->task; 3515 pm8001_dev = ccb->device; /* retrieve device */ 3516 3517 if (!t) { 3518 pm8001_dbg(pm8001_ha, FAIL, " TASK NULL. RETURNING !!!\n"); 3519 return -1; 3520 } 3521 3522 if (t->task_proto == SAS_PROTOCOL_INTERNAL_ABORT) 3523 atomic_dec(&pm8001_dev->running_req); 3524 3525 ts = &t->task_status; 3526 if (status != 0) 3527 pm8001_dbg(pm8001_ha, FAIL, "task abort failed status 0x%x ,tag = 0x%x, scp= 0x%x\n", 3528 status, tag, scp); 3529 switch (status) { 3530 case IO_SUCCESS: 3531 pm8001_dbg(pm8001_ha, EH, "IO_SUCCESS\n"); 3532 ts->resp = SAS_TASK_COMPLETE; 3533 ts->stat = SAS_SAM_STAT_GOOD; 3534 break; 3535 case IO_NOT_VALID: 3536 pm8001_dbg(pm8001_ha, EH, "IO_NOT_VALID\n"); 3537 ts->resp = TMF_RESP_FUNC_FAILED; 3538 break; 3539 } 3540 spin_lock_irqsave(&t->task_state_lock, flags); 3541 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 3542 t->task_state_flags |= SAS_TASK_STATE_DONE; 3543 spin_unlock_irqrestore(&t->task_state_lock, flags); 3544 pm8001_ccb_task_free(pm8001_ha, ccb); 3545 mb(); 3546 3547 t->task_done(t); 3548 3549 return 0; 3550 } 3551 3552 /** 3553 * mpi_hw_event -The hw event has come. 3554 * @pm8001_ha: our hba card information 3555 * @piomb: IO message buffer 3556 */ 3557 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 3558 { 3559 unsigned long flags; 3560 struct hw_event_resp *pPayload = 3561 (struct hw_event_resp *)(piomb + 4); 3562 u32 lr_evt_status_phyid_portid = 3563 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3564 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3565 u8 phy_id = 3566 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3567 u16 eventType = 3568 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8); 3569 u8 status = 3570 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24); 3571 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3572 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3573 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id]; 3574 pm8001_dbg(pm8001_ha, DEVIO, 3575 "SPC HW event for portid:%d, phyid:%d, event:%x, status:%x\n", 3576 port_id, phy_id, eventType, status); 3577 switch (eventType) { 3578 case HW_EVENT_PHY_START_STATUS: 3579 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS status = %x\n", 3580 status); 3581 if (status == 0) 3582 phy->phy_state = 1; 3583 3584 if (pm8001_ha->flags == PM8001F_RUN_TIME && 3585 phy->enable_completion != NULL) { 3586 complete(phy->enable_completion); 3587 phy->enable_completion = NULL; 3588 } 3589 break; 3590 case HW_EVENT_SAS_PHY_UP: 3591 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS\n"); 3592 hw_event_sas_phy_up(pm8001_ha, piomb); 3593 break; 3594 case HW_EVENT_SATA_PHY_UP: 3595 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_PHY_UP\n"); 3596 hw_event_sata_phy_up(pm8001_ha, piomb); 3597 break; 3598 case HW_EVENT_PHY_STOP_STATUS: 3599 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_STOP_STATUS status = %x\n", 3600 status); 3601 if (status == 0) 3602 phy->phy_state = 0; 3603 break; 3604 case HW_EVENT_SATA_SPINUP_HOLD: 3605 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_SPINUP_HOLD\n"); 3606 sas_notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD, 3607 GFP_ATOMIC); 3608 break; 3609 case HW_EVENT_PHY_DOWN: 3610 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_DOWN\n"); 3611 sas_notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL, 3612 GFP_ATOMIC); 3613 phy->phy_attached = 0; 3614 phy->phy_state = 0; 3615 hw_event_phy_down(pm8001_ha, piomb); 3616 break; 3617 case HW_EVENT_PORT_INVALID: 3618 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_INVALID\n"); 3619 sas_phy_disconnected(sas_phy); 3620 phy->phy_attached = 0; 3621 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3622 GFP_ATOMIC); 3623 break; 3624 /* the broadcast change primitive received, tell the LIBSAS this event 3625 to revalidate the sas domain*/ 3626 case HW_EVENT_BROADCAST_CHANGE: 3627 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_CHANGE\n"); 3628 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE, 3629 port_id, phy_id, 1, 0); 3630 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3631 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE; 3632 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3633 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD, 3634 GFP_ATOMIC); 3635 break; 3636 case HW_EVENT_PHY_ERROR: 3637 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_ERROR\n"); 3638 sas_phy_disconnected(&phy->sas_phy); 3639 phy->phy_attached = 0; 3640 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR, GFP_ATOMIC); 3641 break; 3642 case HW_EVENT_BROADCAST_EXP: 3643 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_EXP\n"); 3644 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3645 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP; 3646 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3647 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD, 3648 GFP_ATOMIC); 3649 break; 3650 case HW_EVENT_LINK_ERR_INVALID_DWORD: 3651 pm8001_dbg(pm8001_ha, MSG, 3652 "HW_EVENT_LINK_ERR_INVALID_DWORD\n"); 3653 pm8001_hw_event_ack_req(pm8001_ha, 0, 3654 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0); 3655 sas_phy_disconnected(sas_phy); 3656 phy->phy_attached = 0; 3657 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3658 GFP_ATOMIC); 3659 break; 3660 case HW_EVENT_LINK_ERR_DISPARITY_ERROR: 3661 pm8001_dbg(pm8001_ha, MSG, 3662 "HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"); 3663 pm8001_hw_event_ack_req(pm8001_ha, 0, 3664 HW_EVENT_LINK_ERR_DISPARITY_ERROR, 3665 port_id, phy_id, 0, 0); 3666 sas_phy_disconnected(sas_phy); 3667 phy->phy_attached = 0; 3668 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3669 GFP_ATOMIC); 3670 break; 3671 case HW_EVENT_LINK_ERR_CODE_VIOLATION: 3672 pm8001_dbg(pm8001_ha, MSG, 3673 "HW_EVENT_LINK_ERR_CODE_VIOLATION\n"); 3674 pm8001_hw_event_ack_req(pm8001_ha, 0, 3675 HW_EVENT_LINK_ERR_CODE_VIOLATION, 3676 port_id, phy_id, 0, 0); 3677 sas_phy_disconnected(sas_phy); 3678 phy->phy_attached = 0; 3679 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3680 GFP_ATOMIC); 3681 break; 3682 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH: 3683 pm8001_dbg(pm8001_ha, MSG, 3684 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"); 3685 pm8001_hw_event_ack_req(pm8001_ha, 0, 3686 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH, 3687 port_id, phy_id, 0, 0); 3688 sas_phy_disconnected(sas_phy); 3689 phy->phy_attached = 0; 3690 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3691 GFP_ATOMIC); 3692 break; 3693 case HW_EVENT_MALFUNCTION: 3694 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_MALFUNCTION\n"); 3695 break; 3696 case HW_EVENT_BROADCAST_SES: 3697 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_SES\n"); 3698 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3699 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES; 3700 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3701 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD, 3702 GFP_ATOMIC); 3703 break; 3704 case HW_EVENT_INBOUND_CRC_ERROR: 3705 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_INBOUND_CRC_ERROR\n"); 3706 pm8001_hw_event_ack_req(pm8001_ha, 0, 3707 HW_EVENT_INBOUND_CRC_ERROR, 3708 port_id, phy_id, 0, 0); 3709 break; 3710 case HW_EVENT_HARD_RESET_RECEIVED: 3711 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_HARD_RESET_RECEIVED\n"); 3712 sas_notify_port_event(sas_phy, PORTE_HARD_RESET, GFP_ATOMIC); 3713 break; 3714 case HW_EVENT_ID_FRAME_TIMEOUT: 3715 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_ID_FRAME_TIMEOUT\n"); 3716 sas_phy_disconnected(sas_phy); 3717 phy->phy_attached = 0; 3718 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3719 GFP_ATOMIC); 3720 break; 3721 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED: 3722 pm8001_dbg(pm8001_ha, MSG, 3723 "HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"); 3724 pm8001_hw_event_ack_req(pm8001_ha, 0, 3725 HW_EVENT_LINK_ERR_PHY_RESET_FAILED, 3726 port_id, phy_id, 0, 0); 3727 sas_phy_disconnected(sas_phy); 3728 phy->phy_attached = 0; 3729 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3730 GFP_ATOMIC); 3731 break; 3732 case HW_EVENT_PORT_RESET_TIMER_TMO: 3733 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_TIMER_TMO\n"); 3734 sas_phy_disconnected(sas_phy); 3735 phy->phy_attached = 0; 3736 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3737 GFP_ATOMIC); 3738 break; 3739 case HW_EVENT_PORT_RECOVERY_TIMER_TMO: 3740 pm8001_dbg(pm8001_ha, MSG, 3741 "HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"); 3742 sas_phy_disconnected(sas_phy); 3743 phy->phy_attached = 0; 3744 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3745 GFP_ATOMIC); 3746 break; 3747 case HW_EVENT_PORT_RECOVER: 3748 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RECOVER\n"); 3749 break; 3750 case HW_EVENT_PORT_RESET_COMPLETE: 3751 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_COMPLETE\n"); 3752 break; 3753 case EVENT_BROADCAST_ASYNCH_EVENT: 3754 pm8001_dbg(pm8001_ha, MSG, "EVENT_BROADCAST_ASYNCH_EVENT\n"); 3755 break; 3756 default: 3757 pm8001_dbg(pm8001_ha, DEVIO, "Unknown event type = %x\n", 3758 eventType); 3759 break; 3760 } 3761 return 0; 3762 } 3763 3764 /** 3765 * process_one_iomb - process one outbound Queue memory block 3766 * @pm8001_ha: our hba card information 3767 * @piomb: IO message buffer 3768 */ 3769 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb) 3770 { 3771 __le32 pHeader = *(__le32 *)piomb; 3772 u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF); 3773 3774 pm8001_dbg(pm8001_ha, MSG, "process_one_iomb:\n"); 3775 3776 switch (opc) { 3777 case OPC_OUB_ECHO: 3778 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_ECHO\n"); 3779 break; 3780 case OPC_OUB_HW_EVENT: 3781 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_HW_EVENT\n"); 3782 mpi_hw_event(pm8001_ha, piomb); 3783 break; 3784 case OPC_OUB_SSP_COMP: 3785 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_COMP\n"); 3786 mpi_ssp_completion(pm8001_ha, piomb); 3787 break; 3788 case OPC_OUB_SMP_COMP: 3789 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_COMP\n"); 3790 mpi_smp_completion(pm8001_ha, piomb); 3791 break; 3792 case OPC_OUB_LOCAL_PHY_CNTRL: 3793 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_LOCAL_PHY_CNTRL\n"); 3794 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb); 3795 break; 3796 case OPC_OUB_DEV_REGIST: 3797 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_REGIST\n"); 3798 pm8001_mpi_reg_resp(pm8001_ha, piomb); 3799 break; 3800 case OPC_OUB_DEREG_DEV: 3801 pm8001_dbg(pm8001_ha, MSG, "unregister the device\n"); 3802 pm8001_mpi_dereg_resp(pm8001_ha, piomb); 3803 break; 3804 case OPC_OUB_GET_DEV_HANDLE: 3805 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEV_HANDLE\n"); 3806 break; 3807 case OPC_OUB_SATA_COMP: 3808 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_COMP\n"); 3809 mpi_sata_completion(pm8001_ha, piomb); 3810 break; 3811 case OPC_OUB_SATA_EVENT: 3812 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_EVENT\n"); 3813 mpi_sata_event(pm8001_ha, piomb); 3814 break; 3815 case OPC_OUB_SSP_EVENT: 3816 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_EVENT\n"); 3817 mpi_ssp_event(pm8001_ha, piomb); 3818 break; 3819 case OPC_OUB_DEV_HANDLE_ARRIV: 3820 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_HANDLE_ARRIV\n"); 3821 /*This is for target*/ 3822 break; 3823 case OPC_OUB_SSP_RECV_EVENT: 3824 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_RECV_EVENT\n"); 3825 /*This is for target*/ 3826 break; 3827 case OPC_OUB_DEV_INFO: 3828 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_INFO\n"); 3829 break; 3830 case OPC_OUB_FW_FLASH_UPDATE: 3831 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_FW_FLASH_UPDATE\n"); 3832 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb); 3833 break; 3834 case OPC_OUB_GPIO_RESPONSE: 3835 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_RESPONSE\n"); 3836 break; 3837 case OPC_OUB_GPIO_EVENT: 3838 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_EVENT\n"); 3839 break; 3840 case OPC_OUB_GENERAL_EVENT: 3841 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GENERAL_EVENT\n"); 3842 pm8001_mpi_general_event(pm8001_ha, piomb); 3843 break; 3844 case OPC_OUB_SSP_ABORT_RSP: 3845 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_ABORT_RSP\n"); 3846 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3847 break; 3848 case OPC_OUB_SATA_ABORT_RSP: 3849 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_ABORT_RSP\n"); 3850 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3851 break; 3852 case OPC_OUB_SAS_DIAG_MODE_START_END: 3853 pm8001_dbg(pm8001_ha, MSG, 3854 "OPC_OUB_SAS_DIAG_MODE_START_END\n"); 3855 break; 3856 case OPC_OUB_SAS_DIAG_EXECUTE: 3857 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_DIAG_EXECUTE\n"); 3858 break; 3859 case OPC_OUB_GET_TIME_STAMP: 3860 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_TIME_STAMP\n"); 3861 break; 3862 case OPC_OUB_SAS_HW_EVENT_ACK: 3863 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_HW_EVENT_ACK\n"); 3864 break; 3865 case OPC_OUB_PORT_CONTROL: 3866 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_PORT_CONTROL\n"); 3867 break; 3868 case OPC_OUB_SMP_ABORT_RSP: 3869 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_ABORT_RSP\n"); 3870 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3871 break; 3872 case OPC_OUB_GET_NVMD_DATA: 3873 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_NVMD_DATA\n"); 3874 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb); 3875 break; 3876 case OPC_OUB_SET_NVMD_DATA: 3877 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_NVMD_DATA\n"); 3878 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb); 3879 break; 3880 case OPC_OUB_DEVICE_HANDLE_REMOVAL: 3881 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEVICE_HANDLE_REMOVAL\n"); 3882 break; 3883 case OPC_OUB_SET_DEVICE_STATE: 3884 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEVICE_STATE\n"); 3885 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb); 3886 break; 3887 case OPC_OUB_GET_DEVICE_STATE: 3888 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEVICE_STATE\n"); 3889 break; 3890 case OPC_OUB_SET_DEV_INFO: 3891 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEV_INFO\n"); 3892 break; 3893 case OPC_OUB_SAS_RE_INITIALIZE: 3894 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_RE_INITIALIZE\n"); 3895 break; 3896 default: 3897 pm8001_dbg(pm8001_ha, DEVIO, 3898 "Unknown outbound Queue IOMB OPC = %x\n", 3899 opc); 3900 break; 3901 } 3902 } 3903 3904 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec) 3905 { 3906 struct outbound_queue_table *circularQ; 3907 void *pMsg1 = NULL; 3908 u8 bc; 3909 u32 ret = MPI_IO_STATUS_FAIL; 3910 unsigned long flags; 3911 3912 spin_lock_irqsave(&pm8001_ha->lock, flags); 3913 circularQ = &pm8001_ha->outbnd_q_tbl[vec]; 3914 do { 3915 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc); 3916 if (MPI_IO_STATUS_SUCCESS == ret) { 3917 /* process the outbound message */ 3918 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4)); 3919 /* free the message from the outbound circular buffer */ 3920 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1, 3921 circularQ, bc); 3922 } 3923 if (MPI_IO_STATUS_BUSY == ret) { 3924 /* Update the producer index from SPC */ 3925 circularQ->producer_index = 3926 cpu_to_le32(pm8001_read_32(circularQ->pi_virt)); 3927 if (le32_to_cpu(circularQ->producer_index) == 3928 circularQ->consumer_idx) 3929 /* OQ is empty */ 3930 break; 3931 } 3932 } while (1); 3933 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 3934 return ret; 3935 } 3936 3937 /* DMA_... to our direction translation. */ 3938 static const u8 data_dir_flags[] = { 3939 [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */ 3940 [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */ 3941 [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */ 3942 [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */ 3943 }; 3944 void 3945 pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd) 3946 { 3947 int i; 3948 struct scatterlist *sg; 3949 struct pm8001_prd *buf_prd = prd; 3950 3951 for_each_sg(scatter, sg, nr, i) { 3952 buf_prd->addr = cpu_to_le64(sg_dma_address(sg)); 3953 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg)); 3954 buf_prd->im_len.e = 0; 3955 buf_prd++; 3956 } 3957 } 3958 3959 static void build_smp_cmd(u32 deviceID, __le32 hTag, struct smp_req *psmp_cmd) 3960 { 3961 psmp_cmd->tag = hTag; 3962 psmp_cmd->device_id = cpu_to_le32(deviceID); 3963 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1)); 3964 } 3965 3966 /** 3967 * pm8001_chip_smp_req - send a SMP task to FW 3968 * @pm8001_ha: our hba card information. 3969 * @ccb: the ccb information this request used. 3970 */ 3971 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha, 3972 struct pm8001_ccb_info *ccb) 3973 { 3974 int elem, rc; 3975 struct sas_task *task = ccb->task; 3976 struct domain_device *dev = task->dev; 3977 struct pm8001_device *pm8001_dev = dev->lldd_dev; 3978 struct scatterlist *sg_req, *sg_resp; 3979 u32 req_len, resp_len; 3980 struct smp_req smp_cmd; 3981 u32 opc; 3982 3983 memset(&smp_cmd, 0, sizeof(smp_cmd)); 3984 /* 3985 * DMA-map SMP request, response buffers 3986 */ 3987 sg_req = &task->smp_task.smp_req; 3988 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE); 3989 if (!elem) 3990 return -ENOMEM; 3991 req_len = sg_dma_len(sg_req); 3992 3993 sg_resp = &task->smp_task.smp_resp; 3994 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE); 3995 if (!elem) { 3996 rc = -ENOMEM; 3997 goto err_out; 3998 } 3999 resp_len = sg_dma_len(sg_resp); 4000 /* must be in dwords */ 4001 if ((req_len & 0x3) || (resp_len & 0x3)) { 4002 rc = -EINVAL; 4003 goto err_out_2; 4004 } 4005 4006 opc = OPC_INB_SMP_REQUEST; 4007 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag); 4008 smp_cmd.long_smp_req.long_req_addr = 4009 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req)); 4010 smp_cmd.long_smp_req.long_req_size = 4011 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4); 4012 smp_cmd.long_smp_req.long_resp_addr = 4013 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp)); 4014 smp_cmd.long_smp_req.long_resp_size = 4015 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4); 4016 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd); 4017 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, 4018 &smp_cmd, sizeof(smp_cmd), 0); 4019 if (rc) 4020 goto err_out_2; 4021 4022 return 0; 4023 4024 err_out_2: 4025 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1, 4026 DMA_FROM_DEVICE); 4027 err_out: 4028 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1, 4029 DMA_TO_DEVICE); 4030 return rc; 4031 } 4032 4033 /** 4034 * pm8001_chip_ssp_io_req - send a SSP task to FW 4035 * @pm8001_ha: our hba card information. 4036 * @ccb: the ccb information this request used. 4037 */ 4038 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha, 4039 struct pm8001_ccb_info *ccb) 4040 { 4041 struct sas_task *task = ccb->task; 4042 struct domain_device *dev = task->dev; 4043 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4044 struct ssp_ini_io_start_req ssp_cmd; 4045 u32 tag = ccb->ccb_tag; 4046 u64 phys_addr; 4047 u32 opc = OPC_INB_SSPINIIOSTART; 4048 memset(&ssp_cmd, 0, sizeof(ssp_cmd)); 4049 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8); 4050 ssp_cmd.dir_m_tlr = 4051 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for 4052 SAS 1.1 compatible TLR*/ 4053 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4054 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id); 4055 ssp_cmd.tag = cpu_to_le32(tag); 4056 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7); 4057 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd, 4058 task->ssp_task.cmd->cmd_len); 4059 4060 /* fill in PRD (scatter/gather) table, if any */ 4061 if (task->num_scatter > 1) { 4062 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd); 4063 phys_addr = ccb->ccb_dma_handle; 4064 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(phys_addr)); 4065 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr)); 4066 ssp_cmd.esgl = cpu_to_le32(1<<31); 4067 } else if (task->num_scatter == 1) { 4068 u64 dma_addr = sg_dma_address(task->scatter); 4069 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr)); 4070 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr)); 4071 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4072 ssp_cmd.esgl = 0; 4073 } else if (task->num_scatter == 0) { 4074 ssp_cmd.addr_low = 0; 4075 ssp_cmd.addr_high = 0; 4076 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4077 ssp_cmd.esgl = 0; 4078 } 4079 4080 return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &ssp_cmd, 4081 sizeof(ssp_cmd), 0); 4082 } 4083 4084 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha, 4085 struct pm8001_ccb_info *ccb) 4086 { 4087 struct sas_task *task = ccb->task; 4088 struct domain_device *dev = task->dev; 4089 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev; 4090 u32 tag = ccb->ccb_tag; 4091 struct sata_start_req sata_cmd; 4092 u32 hdr_tag, ncg_tag = 0; 4093 u64 phys_addr; 4094 u32 ATAP = 0x0; 4095 u32 dir, retfis = 0; 4096 u32 opc = OPC_INB_SATA_HOST_OPSTART; 4097 4098 memset(&sata_cmd, 0, sizeof(sata_cmd)); 4099 4100 if (task->data_dir == DMA_NONE && !task->ata_task.use_ncq) { 4101 ATAP = 0x04; /* no data*/ 4102 pm8001_dbg(pm8001_ha, IO, "no data\n"); 4103 } else if (likely(!task->ata_task.device_control_reg_update)) { 4104 if (task->ata_task.use_ncq && 4105 dev->sata_dev.class != ATA_DEV_ATAPI) { 4106 ATAP = 0x07; /* FPDMA */ 4107 pm8001_dbg(pm8001_ha, IO, "FPDMA\n"); 4108 } else if (task->ata_task.dma_xfer) { 4109 ATAP = 0x06; /* DMA */ 4110 pm8001_dbg(pm8001_ha, IO, "DMA\n"); 4111 } else { 4112 ATAP = 0x05; /* PIO*/ 4113 pm8001_dbg(pm8001_ha, IO, "PIO\n"); 4114 } 4115 } 4116 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) { 4117 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 4118 ncg_tag = hdr_tag; 4119 } 4120 dir = data_dir_flags[task->data_dir] << 8; 4121 sata_cmd.tag = cpu_to_le32(tag); 4122 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 4123 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4124 if (task->ata_task.return_fis_on_success) 4125 retfis = 1; 4126 sata_cmd.retfis_ncqtag_atap_dir_m = 4127 cpu_to_le32((retfis << 24) | ((ncg_tag & 0xff) << 16) | 4128 ((ATAP & 0x3f) << 10) | dir); 4129 sata_cmd.sata_fis = task->ata_task.fis; 4130 if (likely(!task->ata_task.device_control_reg_update)) 4131 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */ 4132 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */ 4133 /* fill in PRD (scatter/gather) table, if any */ 4134 if (task->num_scatter > 1) { 4135 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd); 4136 phys_addr = ccb->ccb_dma_handle; 4137 sata_cmd.addr_low = lower_32_bits(phys_addr); 4138 sata_cmd.addr_high = upper_32_bits(phys_addr); 4139 sata_cmd.esgl = cpu_to_le32(1 << 31); 4140 } else if (task->num_scatter == 1) { 4141 u64 dma_addr = sg_dma_address(task->scatter); 4142 sata_cmd.addr_low = lower_32_bits(dma_addr); 4143 sata_cmd.addr_high = upper_32_bits(dma_addr); 4144 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4145 sata_cmd.esgl = 0; 4146 } else if (task->num_scatter == 0) { 4147 sata_cmd.addr_low = 0; 4148 sata_cmd.addr_high = 0; 4149 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4150 sata_cmd.esgl = 0; 4151 } 4152 4153 return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &sata_cmd, 4154 sizeof(sata_cmd), 0); 4155 } 4156 4157 /** 4158 * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND 4159 * @pm8001_ha: our hba card information. 4160 * @phy_id: the phy id which we wanted to start up. 4161 */ 4162 static int 4163 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id) 4164 { 4165 struct phy_start_req payload; 4166 u32 tag = 0x01; 4167 u32 opcode = OPC_INB_PHYSTART; 4168 4169 memset(&payload, 0, sizeof(payload)); 4170 payload.tag = cpu_to_le32(tag); 4171 /* 4172 ** [0:7] PHY Identifier 4173 ** [8:11] link rate 1.5G, 3G, 6G 4174 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both 4175 ** [14] 0b disable spin up hold; 1b enable spin up hold 4176 */ 4177 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE | 4178 LINKMODE_AUTO | LINKRATE_15 | 4179 LINKRATE_30 | LINKRATE_60 | phy_id); 4180 payload.sas_identify.dev_type = SAS_END_DEVICE; 4181 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL; 4182 memcpy(payload.sas_identify.sas_addr, 4183 &pm8001_ha->phy[phy_id].dev_sas_addr, SAS_ADDR_SIZE); 4184 payload.sas_identify.phy_id = phy_id; 4185 4186 return pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload, 4187 sizeof(payload), 0); 4188 } 4189 4190 /** 4191 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND 4192 * @pm8001_ha: our hba card information. 4193 * @phy_id: the phy id which we wanted to start up. 4194 */ 4195 static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha, 4196 u8 phy_id) 4197 { 4198 struct phy_stop_req payload; 4199 u32 tag = 0x01; 4200 u32 opcode = OPC_INB_PHYSTOP; 4201 4202 memset(&payload, 0, sizeof(payload)); 4203 payload.tag = cpu_to_le32(tag); 4204 payload.phy_id = cpu_to_le32(phy_id); 4205 4206 return pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload, 4207 sizeof(payload), 0); 4208 } 4209 4210 /* 4211 * see comments on pm8001_mpi_reg_resp. 4212 */ 4213 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha, 4214 struct pm8001_device *pm8001_dev, u32 flag) 4215 { 4216 struct reg_dev_req payload; 4217 u32 opc; 4218 u32 stp_sspsmp_sata = 0x4; 4219 u32 linkrate, phy_id; 4220 int rc; 4221 struct pm8001_ccb_info *ccb; 4222 u8 retryFlag = 0x1; 4223 u16 firstBurstSize = 0; 4224 u16 ITNT = 2000; 4225 struct domain_device *dev = pm8001_dev->sas_device; 4226 struct domain_device *parent_dev = dev->parent; 4227 struct pm8001_port *port = dev->port->lldd_port; 4228 4229 memset(&payload, 0, sizeof(payload)); 4230 ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_dev, NULL); 4231 if (!ccb) 4232 return -SAS_QUEUE_FULL; 4233 4234 payload.tag = cpu_to_le32(ccb->ccb_tag); 4235 if (flag == 1) 4236 stp_sspsmp_sata = 0x02; /*direct attached sata */ 4237 else { 4238 if (pm8001_dev->dev_type == SAS_SATA_DEV) 4239 stp_sspsmp_sata = 0x00; /* stp*/ 4240 else if (pm8001_dev->dev_type == SAS_END_DEVICE || 4241 dev_is_expander(pm8001_dev->dev_type)) 4242 stp_sspsmp_sata = 0x01; /*ssp or smp*/ 4243 } 4244 if (parent_dev && dev_is_expander(parent_dev->dev_type)) 4245 phy_id = parent_dev->ex_dev.ex_phy->phy_id; 4246 else 4247 phy_id = pm8001_dev->attached_phy; 4248 opc = OPC_INB_REG_DEV; 4249 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ? 4250 pm8001_dev->sas_device->linkrate : dev->port->linkrate; 4251 payload.phyid_portid = 4252 cpu_to_le32(((port->port_id) & 0x0F) | 4253 ((phy_id & 0x0F) << 4)); 4254 payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) | 4255 ((linkrate & 0x0F) * 0x1000000) | 4256 ((stp_sspsmp_sata & 0x03) * 0x10000000)); 4257 payload.firstburstsize_ITNexustimeout = 4258 cpu_to_le32(ITNT | (firstBurstSize * 0x10000)); 4259 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr, 4260 SAS_ADDR_SIZE); 4261 4262 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 4263 sizeof(payload), 0); 4264 if (rc) 4265 pm8001_ccb_free(pm8001_ha, ccb); 4266 4267 return rc; 4268 } 4269 4270 /* 4271 * see comments on pm8001_mpi_reg_resp. 4272 */ 4273 int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha, 4274 u32 device_id) 4275 { 4276 struct dereg_dev_req payload; 4277 u32 opc = OPC_INB_DEREG_DEV_HANDLE; 4278 4279 memset(&payload, 0, sizeof(payload)); 4280 payload.tag = cpu_to_le32(1); 4281 payload.device_id = cpu_to_le32(device_id); 4282 pm8001_dbg(pm8001_ha, INIT, "unregister device device_id %d\n", 4283 device_id); 4284 4285 return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 4286 sizeof(payload), 0); 4287 } 4288 4289 /** 4290 * pm8001_chip_phy_ctl_req - support the local phy operation 4291 * @pm8001_ha: our hba card information. 4292 * @phyId: the phy id which we wanted to operate 4293 * @phy_op: the phy operation to request 4294 */ 4295 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 4296 u32 phyId, u32 phy_op) 4297 { 4298 struct local_phy_ctl_req payload; 4299 u32 opc = OPC_INB_LOCAL_PHY_CONTROL; 4300 4301 memset(&payload, 0, sizeof(payload)); 4302 payload.tag = cpu_to_le32(1); 4303 payload.phyop_phyid = 4304 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F)); 4305 4306 return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 4307 sizeof(payload), 0); 4308 } 4309 4310 static u32 pm8001_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha) 4311 { 4312 #ifdef PM8001_USE_MSIX 4313 return 1; 4314 #else 4315 u32 value; 4316 4317 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR); 4318 if (value) 4319 return 1; 4320 return 0; 4321 #endif 4322 } 4323 4324 /** 4325 * pm8001_chip_isr - PM8001 isr handler. 4326 * @pm8001_ha: our hba card information. 4327 * @vec: IRQ number 4328 */ 4329 static irqreturn_t 4330 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec) 4331 { 4332 pm8001_chip_interrupt_disable(pm8001_ha, vec); 4333 pm8001_dbg(pm8001_ha, DEVIO, 4334 "irq vec %d, ODMR:0x%x\n", 4335 vec, pm8001_cr32(pm8001_ha, 0, 0x30)); 4336 process_oq(pm8001_ha, vec); 4337 pm8001_chip_interrupt_enable(pm8001_ha, vec); 4338 return IRQ_HANDLED; 4339 } 4340 4341 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc, 4342 u32 dev_id, enum sas_internal_abort type, u32 task_tag, u32 cmd_tag) 4343 { 4344 struct task_abort_req task_abort; 4345 4346 memset(&task_abort, 0, sizeof(task_abort)); 4347 if (type == SAS_INTERNAL_ABORT_SINGLE) { 4348 task_abort.abort_all = 0; 4349 task_abort.device_id = cpu_to_le32(dev_id); 4350 task_abort.tag_to_abort = cpu_to_le32(task_tag); 4351 } else if (type == SAS_INTERNAL_ABORT_DEV) { 4352 task_abort.abort_all = cpu_to_le32(1); 4353 task_abort.device_id = cpu_to_le32(dev_id); 4354 } else { 4355 pm8001_dbg(pm8001_ha, EH, "unknown type (%d)\n", type); 4356 return -EIO; 4357 } 4358 4359 task_abort.tag = cpu_to_le32(cmd_tag); 4360 4361 return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &task_abort, 4362 sizeof(task_abort), 0); 4363 } 4364 4365 /* 4366 * pm8001_chip_abort_task - SAS abort task when error or exception happened. 4367 */ 4368 int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha, 4369 struct pm8001_ccb_info *ccb) 4370 { 4371 struct sas_task *task = ccb->task; 4372 struct sas_internal_abort_task *abort = &task->abort_task; 4373 struct pm8001_device *pm8001_dev = ccb->device; 4374 int rc = TMF_RESP_FUNC_FAILED; 4375 u32 opc, device_id; 4376 4377 pm8001_dbg(pm8001_ha, EH, "cmd_tag = %x, abort task tag = 0x%x\n", 4378 ccb->ccb_tag, abort->tag); 4379 if (pm8001_dev->dev_type == SAS_END_DEVICE) 4380 opc = OPC_INB_SSP_ABORT; 4381 else if (pm8001_dev->dev_type == SAS_SATA_DEV) 4382 opc = OPC_INB_SATA_ABORT; 4383 else 4384 opc = OPC_INB_SMP_ABORT;/* SMP */ 4385 device_id = pm8001_dev->device_id; 4386 rc = send_task_abort(pm8001_ha, opc, device_id, abort->type, 4387 abort->tag, ccb->ccb_tag); 4388 if (rc != TMF_RESP_FUNC_COMPLETE) 4389 pm8001_dbg(pm8001_ha, EH, "rc= %d\n", rc); 4390 return rc; 4391 } 4392 4393 /** 4394 * pm8001_chip_ssp_tm_req - built the task management command. 4395 * @pm8001_ha: our hba card information. 4396 * @ccb: the ccb information. 4397 * @tmf: task management function. 4398 */ 4399 int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha, 4400 struct pm8001_ccb_info *ccb, struct sas_tmf_task *tmf) 4401 { 4402 struct sas_task *task = ccb->task; 4403 struct domain_device *dev = task->dev; 4404 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4405 u32 opc = OPC_INB_SSPINITMSTART; 4406 struct ssp_ini_tm_start_req sspTMCmd; 4407 4408 memset(&sspTMCmd, 0, sizeof(sspTMCmd)); 4409 sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id); 4410 sspTMCmd.relate_tag = cpu_to_le32((u32)tmf->tag_of_task_to_be_managed); 4411 sspTMCmd.tmf = cpu_to_le32(tmf->tmf); 4412 memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8); 4413 sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag); 4414 if (pm8001_ha->chip_id != chip_8001) 4415 sspTMCmd.ds_ads_m = cpu_to_le32(0x08); 4416 4417 return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &sspTMCmd, 4418 sizeof(sspTMCmd), 0); 4419 } 4420 4421 int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha, 4422 void *payload) 4423 { 4424 u32 opc = OPC_INB_GET_NVMD_DATA; 4425 u32 nvmd_type; 4426 int rc; 4427 struct pm8001_ccb_info *ccb; 4428 struct get_nvm_data_req nvmd_req; 4429 struct fw_control_ex *fw_control_context; 4430 struct pm8001_ioctl_payload *ioctl_payload = payload; 4431 4432 nvmd_type = ioctl_payload->minor_function; 4433 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); 4434 if (!fw_control_context) 4435 return -ENOMEM; 4436 fw_control_context->usrAddr = (u8 *)ioctl_payload->func_specific; 4437 fw_control_context->len = ioctl_payload->rd_length; 4438 memset(&nvmd_req, 0, sizeof(nvmd_req)); 4439 4440 ccb = pm8001_ccb_alloc(pm8001_ha, NULL, NULL); 4441 if (!ccb) { 4442 kfree(fw_control_context); 4443 return -SAS_QUEUE_FULL; 4444 } 4445 ccb->fw_control_context = fw_control_context; 4446 4447 nvmd_req.tag = cpu_to_le32(ccb->ccb_tag); 4448 4449 switch (nvmd_type) { 4450 case TWI_DEVICE: { 4451 u32 twi_addr, twi_page_size; 4452 twi_addr = 0xa8; 4453 twi_page_size = 2; 4454 4455 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 | 4456 twi_page_size << 8 | TWI_DEVICE); 4457 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length); 4458 nvmd_req.resp_addr_hi = 4459 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4460 nvmd_req.resp_addr_lo = 4461 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4462 break; 4463 } 4464 case C_SEEPROM: { 4465 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM); 4466 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length); 4467 nvmd_req.resp_addr_hi = 4468 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4469 nvmd_req.resp_addr_lo = 4470 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4471 break; 4472 } 4473 case VPD_FLASH: { 4474 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH); 4475 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length); 4476 nvmd_req.resp_addr_hi = 4477 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4478 nvmd_req.resp_addr_lo = 4479 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4480 break; 4481 } 4482 case EXPAN_ROM: { 4483 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM); 4484 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length); 4485 nvmd_req.resp_addr_hi = 4486 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4487 nvmd_req.resp_addr_lo = 4488 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4489 break; 4490 } 4491 case IOP_RDUMP: { 4492 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | IOP_RDUMP); 4493 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length); 4494 nvmd_req.vpd_offset = cpu_to_le32(ioctl_payload->offset); 4495 nvmd_req.resp_addr_hi = 4496 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4497 nvmd_req.resp_addr_lo = 4498 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4499 break; 4500 } 4501 default: 4502 break; 4503 } 4504 4505 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &nvmd_req, 4506 sizeof(nvmd_req), 0); 4507 if (rc) { 4508 kfree(fw_control_context); 4509 pm8001_ccb_free(pm8001_ha, ccb); 4510 } 4511 return rc; 4512 } 4513 4514 int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha, 4515 void *payload) 4516 { 4517 u32 opc = OPC_INB_SET_NVMD_DATA; 4518 u32 nvmd_type; 4519 int rc; 4520 struct pm8001_ccb_info *ccb; 4521 struct set_nvm_data_req nvmd_req; 4522 struct fw_control_ex *fw_control_context; 4523 struct pm8001_ioctl_payload *ioctl_payload = payload; 4524 4525 nvmd_type = ioctl_payload->minor_function; 4526 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); 4527 if (!fw_control_context) 4528 return -ENOMEM; 4529 4530 memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr, 4531 &ioctl_payload->func_specific, 4532 ioctl_payload->wr_length); 4533 memset(&nvmd_req, 0, sizeof(nvmd_req)); 4534 4535 ccb = pm8001_ccb_alloc(pm8001_ha, NULL, NULL); 4536 if (!ccb) { 4537 kfree(fw_control_context); 4538 return -SAS_QUEUE_FULL; 4539 } 4540 ccb->fw_control_context = fw_control_context; 4541 4542 nvmd_req.tag = cpu_to_le32(ccb->ccb_tag); 4543 switch (nvmd_type) { 4544 case TWI_DEVICE: { 4545 u32 twi_addr, twi_page_size; 4546 twi_addr = 0xa8; 4547 twi_page_size = 2; 4548 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4549 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 | 4550 twi_page_size << 8 | TWI_DEVICE); 4551 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length); 4552 nvmd_req.resp_addr_hi = 4553 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4554 nvmd_req.resp_addr_lo = 4555 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4556 break; 4557 } 4558 case C_SEEPROM: 4559 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM); 4560 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length); 4561 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4562 nvmd_req.resp_addr_hi = 4563 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4564 nvmd_req.resp_addr_lo = 4565 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4566 break; 4567 case VPD_FLASH: 4568 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH); 4569 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length); 4570 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4571 nvmd_req.resp_addr_hi = 4572 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4573 nvmd_req.resp_addr_lo = 4574 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4575 break; 4576 case EXPAN_ROM: 4577 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM); 4578 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length); 4579 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4580 nvmd_req.resp_addr_hi = 4581 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4582 nvmd_req.resp_addr_lo = 4583 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4584 break; 4585 default: 4586 break; 4587 } 4588 4589 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &nvmd_req, 4590 sizeof(nvmd_req), 0); 4591 if (rc) { 4592 kfree(fw_control_context); 4593 pm8001_ccb_free(pm8001_ha, ccb); 4594 } 4595 return rc; 4596 } 4597 4598 /** 4599 * pm8001_chip_fw_flash_update_build - support the firmware update operation 4600 * @pm8001_ha: our hba card information. 4601 * @fw_flash_updata_info: firmware flash update param 4602 * @tag: Tag to apply to the payload 4603 */ 4604 int 4605 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha, 4606 void *fw_flash_updata_info, u32 tag) 4607 { 4608 struct fw_flash_Update_req payload; 4609 struct fw_flash_updata_info *info; 4610 u32 opc = OPC_INB_FW_FLASH_UPDATE; 4611 4612 memset(&payload, 0, sizeof(struct fw_flash_Update_req)); 4613 info = fw_flash_updata_info; 4614 payload.tag = cpu_to_le32(tag); 4615 payload.cur_image_len = cpu_to_le32(info->cur_image_len); 4616 payload.cur_image_offset = cpu_to_le32(info->cur_image_offset); 4617 payload.total_image_len = cpu_to_le32(info->total_image_len); 4618 payload.len = info->sgl.im_len.len ; 4619 payload.sgl_addr_lo = 4620 cpu_to_le32(lower_32_bits(le64_to_cpu(info->sgl.addr))); 4621 payload.sgl_addr_hi = 4622 cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr))); 4623 4624 return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 4625 sizeof(payload), 0); 4626 } 4627 4628 int 4629 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha, 4630 void *payload) 4631 { 4632 struct fw_flash_updata_info flash_update_info; 4633 struct fw_control_info *fw_control; 4634 struct fw_control_ex *fw_control_context; 4635 int rc; 4636 struct pm8001_ccb_info *ccb; 4637 void *buffer = pm8001_ha->memoryMap.region[FW_FLASH].virt_ptr; 4638 dma_addr_t phys_addr = pm8001_ha->memoryMap.region[FW_FLASH].phys_addr; 4639 struct pm8001_ioctl_payload *ioctl_payload = payload; 4640 4641 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); 4642 if (!fw_control_context) 4643 return -ENOMEM; 4644 fw_control = (struct fw_control_info *)&ioctl_payload->func_specific; 4645 pm8001_dbg(pm8001_ha, DEVIO, 4646 "dma fw_control context input length :%x\n", 4647 fw_control->len); 4648 memcpy(buffer, fw_control->buffer, fw_control->len); 4649 flash_update_info.sgl.addr = cpu_to_le64(phys_addr); 4650 flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len); 4651 flash_update_info.sgl.im_len.e = 0; 4652 flash_update_info.cur_image_offset = fw_control->offset; 4653 flash_update_info.cur_image_len = fw_control->len; 4654 flash_update_info.total_image_len = fw_control->size; 4655 fw_control_context->fw_control = fw_control; 4656 fw_control_context->virtAddr = buffer; 4657 fw_control_context->phys_addr = phys_addr; 4658 fw_control_context->len = fw_control->len; 4659 4660 ccb = pm8001_ccb_alloc(pm8001_ha, NULL, NULL); 4661 if (!ccb) { 4662 kfree(fw_control_context); 4663 return -SAS_QUEUE_FULL; 4664 } 4665 ccb->fw_control_context = fw_control_context; 4666 4667 rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info, 4668 ccb->ccb_tag); 4669 if (rc) { 4670 kfree(fw_control_context); 4671 pm8001_ccb_free(pm8001_ha, ccb); 4672 } 4673 4674 return rc; 4675 } 4676 4677 ssize_t 4678 pm8001_get_gsm_dump(struct device *cdev, u32 length, char *buf) 4679 { 4680 u32 value, rem, offset = 0, bar = 0; 4681 u32 index, work_offset, dw_length; 4682 u32 shift_value, gsm_base, gsm_dump_offset; 4683 char *direct_data; 4684 struct Scsi_Host *shost = class_to_shost(cdev); 4685 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 4686 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 4687 4688 direct_data = buf; 4689 gsm_dump_offset = pm8001_ha->fatal_forensic_shift_offset; 4690 4691 /* check max is 1 Mbytes */ 4692 if ((length > 0x100000) || (gsm_dump_offset & 3) || 4693 ((gsm_dump_offset + length) > 0x1000000)) 4694 return -EINVAL; 4695 4696 if (pm8001_ha->chip_id == chip_8001) 4697 bar = 2; 4698 else 4699 bar = 1; 4700 4701 work_offset = gsm_dump_offset & 0xFFFF0000; 4702 offset = gsm_dump_offset & 0x0000FFFF; 4703 gsm_dump_offset = work_offset; 4704 /* adjust length to dword boundary */ 4705 rem = length & 3; 4706 dw_length = length >> 2; 4707 4708 for (index = 0; index < dw_length; index++) { 4709 if ((work_offset + offset) & 0xFFFF0000) { 4710 if (pm8001_ha->chip_id == chip_8001) 4711 shift_value = ((gsm_dump_offset + offset) & 4712 SHIFT_REG_64K_MASK); 4713 else 4714 shift_value = (((gsm_dump_offset + offset) & 4715 SHIFT_REG_64K_MASK) >> 4716 SHIFT_REG_BIT_SHIFT); 4717 4718 if (pm8001_ha->chip_id == chip_8001) { 4719 gsm_base = GSM_BASE; 4720 if (-1 == pm8001_bar4_shift(pm8001_ha, 4721 (gsm_base + shift_value))) 4722 return -EIO; 4723 } else { 4724 gsm_base = 0; 4725 if (-1 == pm80xx_bar4_shift(pm8001_ha, 4726 (gsm_base + shift_value))) 4727 return -EIO; 4728 } 4729 gsm_dump_offset = (gsm_dump_offset + offset) & 4730 0xFFFF0000; 4731 work_offset = 0; 4732 offset = offset & 0x0000FFFF; 4733 } 4734 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) & 4735 0x0000FFFF); 4736 direct_data += sprintf(direct_data, "%08x ", value); 4737 offset += 4; 4738 } 4739 if (rem != 0) { 4740 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) & 4741 0x0000FFFF); 4742 /* xfr for non_dw */ 4743 direct_data += sprintf(direct_data, "%08x ", value); 4744 } 4745 /* Shift back to BAR4 original address */ 4746 if (-1 == pm8001_bar4_shift(pm8001_ha, 0)) 4747 return -EIO; 4748 pm8001_ha->fatal_forensic_shift_offset += 1024; 4749 4750 if (pm8001_ha->fatal_forensic_shift_offset >= 0x100000) 4751 pm8001_ha->fatal_forensic_shift_offset = 0; 4752 return direct_data - buf; 4753 } 4754 4755 int 4756 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha, 4757 struct pm8001_device *pm8001_dev, u32 state) 4758 { 4759 struct set_dev_state_req payload; 4760 struct pm8001_ccb_info *ccb; 4761 int rc; 4762 u32 opc = OPC_INB_SET_DEVICE_STATE; 4763 4764 memset(&payload, 0, sizeof(payload)); 4765 4766 ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_dev, NULL); 4767 if (!ccb) 4768 return -SAS_QUEUE_FULL; 4769 4770 payload.tag = cpu_to_le32(ccb->ccb_tag); 4771 payload.device_id = cpu_to_le32(pm8001_dev->device_id); 4772 payload.nds = cpu_to_le32(state); 4773 4774 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 4775 sizeof(payload), 0); 4776 if (rc) 4777 pm8001_ccb_free(pm8001_ha, ccb); 4778 4779 return rc; 4780 } 4781 4782 static int 4783 pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha) 4784 { 4785 struct sas_re_initialization_req payload; 4786 struct pm8001_ccb_info *ccb; 4787 int rc; 4788 u32 opc = OPC_INB_SAS_RE_INITIALIZE; 4789 4790 memset(&payload, 0, sizeof(payload)); 4791 4792 ccb = pm8001_ccb_alloc(pm8001_ha, NULL, NULL); 4793 if (!ccb) 4794 return -SAS_QUEUE_FULL; 4795 4796 payload.tag = cpu_to_le32(ccb->ccb_tag); 4797 payload.SSAHOLT = cpu_to_le32(0xd << 25); 4798 payload.sata_hol_tmo = cpu_to_le32(80); 4799 payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff); 4800 4801 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 4802 sizeof(payload), 0); 4803 if (rc) 4804 pm8001_ccb_free(pm8001_ha, ccb); 4805 4806 return rc; 4807 } 4808 4809 const struct pm8001_dispatch pm8001_8001_dispatch = { 4810 .name = "pmc8001", 4811 .chip_init = pm8001_chip_init, 4812 .chip_post_init = pm8001_chip_post_init, 4813 .chip_soft_rst = pm8001_chip_soft_rst, 4814 .chip_rst = pm8001_hw_chip_rst, 4815 .chip_iounmap = pm8001_chip_iounmap, 4816 .isr = pm8001_chip_isr, 4817 .is_our_interrupt = pm8001_chip_is_our_interrupt, 4818 .isr_process_oq = process_oq, 4819 .interrupt_enable = pm8001_chip_interrupt_enable, 4820 .interrupt_disable = pm8001_chip_interrupt_disable, 4821 .make_prd = pm8001_chip_make_sg, 4822 .smp_req = pm8001_chip_smp_req, 4823 .ssp_io_req = pm8001_chip_ssp_io_req, 4824 .sata_req = pm8001_chip_sata_req, 4825 .phy_start_req = pm8001_chip_phy_start_req, 4826 .phy_stop_req = pm8001_chip_phy_stop_req, 4827 .reg_dev_req = pm8001_chip_reg_dev_req, 4828 .dereg_dev_req = pm8001_chip_dereg_dev_req, 4829 .phy_ctl_req = pm8001_chip_phy_ctl_req, 4830 .task_abort = pm8001_chip_abort_task, 4831 .ssp_tm_req = pm8001_chip_ssp_tm_req, 4832 .get_nvmd_req = pm8001_chip_get_nvmd_req, 4833 .set_nvmd_req = pm8001_chip_set_nvmd_req, 4834 .fw_flash_update_req = pm8001_chip_fw_flash_update_req, 4835 .set_dev_state_req = pm8001_chip_set_dev_state_req, 4836 .sas_re_init_req = pm8001_chip_sas_re_initialization, 4837 .fatal_errors = pm80xx_fatal_errors, 4838 }; 4839