1 /* 2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 USI Co., Ltd. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 #include <linux/slab.h> 41 #include "pm8001_sas.h" 42 #include "pm8001_hwi.h" 43 #include "pm8001_chips.h" 44 #include "pm8001_ctl.h" 45 46 /** 47 * read_main_config_table - read the configure table and save it. 48 * @pm8001_ha: our hba card information 49 */ 50 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha) 51 { 52 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 53 pm8001_ha->main_cfg_tbl.pm8001_tbl.signature = 54 pm8001_mr32(address, 0x00); 55 pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev = 56 pm8001_mr32(address, 0x04); 57 pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev = 58 pm8001_mr32(address, 0x08); 59 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io = 60 pm8001_mr32(address, 0x0C); 61 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl = 62 pm8001_mr32(address, 0x10); 63 pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag = 64 pm8001_mr32(address, 0x14); 65 pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset = 66 pm8001_mr32(address, 0x18); 67 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset = 68 pm8001_mr32(address, MAIN_IBQ_OFFSET); 69 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset = 70 pm8001_mr32(address, MAIN_OBQ_OFFSET); 71 pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag = 72 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET); 73 74 /* read analog Setting offset from the configuration table */ 75 pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset = 76 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET); 77 78 /* read Error Dump Offset and Length */ 79 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 = 80 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET); 81 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 = 82 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH); 83 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 = 84 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET); 85 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 = 86 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH); 87 } 88 89 /** 90 * read_general_status_table - read the general status table and save it. 91 * @pm8001_ha: our hba card information 92 */ 93 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha) 94 { 95 void __iomem *address = pm8001_ha->general_stat_tbl_addr; 96 pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate = 97 pm8001_mr32(address, 0x00); 98 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0 = 99 pm8001_mr32(address, 0x04); 100 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1 = 101 pm8001_mr32(address, 0x08); 102 pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt = 103 pm8001_mr32(address, 0x0C); 104 pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt = 105 pm8001_mr32(address, 0x10); 106 pm8001_ha->gs_tbl.pm8001_tbl.rsvd = 107 pm8001_mr32(address, 0x14); 108 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0] = 109 pm8001_mr32(address, 0x18); 110 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1] = 111 pm8001_mr32(address, 0x1C); 112 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2] = 113 pm8001_mr32(address, 0x20); 114 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3] = 115 pm8001_mr32(address, 0x24); 116 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4] = 117 pm8001_mr32(address, 0x28); 118 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5] = 119 pm8001_mr32(address, 0x2C); 120 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6] = 121 pm8001_mr32(address, 0x30); 122 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7] = 123 pm8001_mr32(address, 0x34); 124 pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val = 125 pm8001_mr32(address, 0x38); 126 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0] = 127 pm8001_mr32(address, 0x3C); 128 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1] = 129 pm8001_mr32(address, 0x40); 130 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0] = 131 pm8001_mr32(address, 0x44); 132 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1] = 133 pm8001_mr32(address, 0x48); 134 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2] = 135 pm8001_mr32(address, 0x4C); 136 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3] = 137 pm8001_mr32(address, 0x50); 138 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4] = 139 pm8001_mr32(address, 0x54); 140 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5] = 141 pm8001_mr32(address, 0x58); 142 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6] = 143 pm8001_mr32(address, 0x5C); 144 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7] = 145 pm8001_mr32(address, 0x60); 146 } 147 148 /** 149 * read_inbnd_queue_table - read the inbound queue table and save it. 150 * @pm8001_ha: our hba card information 151 */ 152 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 153 { 154 int i; 155 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 156 for (i = 0; i < PM8001_MAX_INB_NUM; i++) { 157 u32 offset = i * 0x20; 158 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 159 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14))); 160 pm8001_ha->inbnd_q_tbl[i].pi_offset = 161 pm8001_mr32(address, (offset + 0x18)); 162 } 163 } 164 165 /** 166 * read_outbnd_queue_table - read the outbound queue table and save it. 167 * @pm8001_ha: our hba card information 168 */ 169 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 170 { 171 int i; 172 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 173 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) { 174 u32 offset = i * 0x24; 175 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 176 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14))); 177 pm8001_ha->outbnd_q_tbl[i].ci_offset = 178 pm8001_mr32(address, (offset + 0x18)); 179 } 180 } 181 182 /** 183 * init_default_table_values - init the default table. 184 * @pm8001_ha: our hba card information 185 */ 186 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha) 187 { 188 int i; 189 u32 offsetib, offsetob; 190 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr; 191 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr; 192 u32 ib_offset = pm8001_ha->ib_offset; 193 u32 ob_offset = pm8001_ha->ob_offset; 194 u32 ci_offset = pm8001_ha->ci_offset; 195 u32 pi_offset = pm8001_ha->pi_offset; 196 197 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd = 0; 198 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3 = 0; 199 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7 = 0; 200 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3 = 0; 201 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7 = 0; 202 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 = 203 0; 204 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 = 205 0; 206 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0; 207 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0; 208 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0; 209 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0; 210 211 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr = 212 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi; 213 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr = 214 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo; 215 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size = 216 PM8001_EVENT_LOG_SIZE; 217 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option = 0x01; 218 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr = 219 pm8001_ha->memoryMap.region[IOP].phys_addr_hi; 220 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr = 221 pm8001_ha->memoryMap.region[IOP].phys_addr_lo; 222 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size = 223 PM8001_EVENT_LOG_SIZE; 224 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option = 0x01; 225 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt = 0x01; 226 for (i = 0; i < PM8001_MAX_INB_NUM; i++) { 227 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt = 228 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30); 229 pm8001_ha->inbnd_q_tbl[i].upper_base_addr = 230 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi; 231 pm8001_ha->inbnd_q_tbl[i].lower_base_addr = 232 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo; 233 pm8001_ha->inbnd_q_tbl[i].base_virt = 234 (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr; 235 pm8001_ha->inbnd_q_tbl[i].total_length = 236 pm8001_ha->memoryMap.region[ib_offset + i].total_len; 237 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr = 238 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi; 239 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr = 240 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo; 241 pm8001_ha->inbnd_q_tbl[i].ci_virt = 242 pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr; 243 offsetib = i * 0x20; 244 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 245 get_pci_bar_index(pm8001_mr32(addressib, 246 (offsetib + 0x14))); 247 pm8001_ha->inbnd_q_tbl[i].pi_offset = 248 pm8001_mr32(addressib, (offsetib + 0x18)); 249 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0; 250 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0; 251 } 252 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) { 253 pm8001_ha->outbnd_q_tbl[i].element_size_cnt = 254 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30); 255 pm8001_ha->outbnd_q_tbl[i].upper_base_addr = 256 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi; 257 pm8001_ha->outbnd_q_tbl[i].lower_base_addr = 258 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo; 259 pm8001_ha->outbnd_q_tbl[i].base_virt = 260 (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr; 261 pm8001_ha->outbnd_q_tbl[i].total_length = 262 pm8001_ha->memoryMap.region[ob_offset + i].total_len; 263 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr = 264 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi; 265 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr = 266 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo; 267 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = 268 0 | (10 << 16) | (i << 24); 269 pm8001_ha->outbnd_q_tbl[i].pi_virt = 270 pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr; 271 offsetob = i * 0x24; 272 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 273 get_pci_bar_index(pm8001_mr32(addressob, 274 offsetob + 0x14)); 275 pm8001_ha->outbnd_q_tbl[i].ci_offset = 276 pm8001_mr32(addressob, (offsetob + 0x18)); 277 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0; 278 pm8001_ha->outbnd_q_tbl[i].producer_index = 0; 279 } 280 } 281 282 /** 283 * update_main_config_table - update the main default table to the HBA. 284 * @pm8001_ha: our hba card information 285 */ 286 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha) 287 { 288 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 289 pm8001_mw32(address, 0x24, 290 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd); 291 pm8001_mw32(address, 0x28, 292 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3); 293 pm8001_mw32(address, 0x2C, 294 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7); 295 pm8001_mw32(address, 0x30, 296 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3); 297 pm8001_mw32(address, 0x34, 298 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7); 299 pm8001_mw32(address, 0x38, 300 pm8001_ha->main_cfg_tbl.pm8001_tbl. 301 outbound_tgt_ITNexus_event_pid0_3); 302 pm8001_mw32(address, 0x3C, 303 pm8001_ha->main_cfg_tbl.pm8001_tbl. 304 outbound_tgt_ITNexus_event_pid4_7); 305 pm8001_mw32(address, 0x40, 306 pm8001_ha->main_cfg_tbl.pm8001_tbl. 307 outbound_tgt_ssp_event_pid0_3); 308 pm8001_mw32(address, 0x44, 309 pm8001_ha->main_cfg_tbl.pm8001_tbl. 310 outbound_tgt_ssp_event_pid4_7); 311 pm8001_mw32(address, 0x48, 312 pm8001_ha->main_cfg_tbl.pm8001_tbl. 313 outbound_tgt_smp_event_pid0_3); 314 pm8001_mw32(address, 0x4C, 315 pm8001_ha->main_cfg_tbl.pm8001_tbl. 316 outbound_tgt_smp_event_pid4_7); 317 pm8001_mw32(address, 0x50, 318 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr); 319 pm8001_mw32(address, 0x54, 320 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr); 321 pm8001_mw32(address, 0x58, 322 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size); 323 pm8001_mw32(address, 0x5C, 324 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option); 325 pm8001_mw32(address, 0x60, 326 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr); 327 pm8001_mw32(address, 0x64, 328 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr); 329 pm8001_mw32(address, 0x68, 330 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size); 331 pm8001_mw32(address, 0x6C, 332 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option); 333 pm8001_mw32(address, 0x70, 334 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt); 335 } 336 337 /** 338 * update_inbnd_queue_table - update the inbound queue table to the HBA. 339 * @pm8001_ha: our hba card information 340 * @number: entry in the queue 341 */ 342 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 343 int number) 344 { 345 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 346 u16 offset = number * 0x20; 347 pm8001_mw32(address, offset + 0x00, 348 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); 349 pm8001_mw32(address, offset + 0x04, 350 pm8001_ha->inbnd_q_tbl[number].upper_base_addr); 351 pm8001_mw32(address, offset + 0x08, 352 pm8001_ha->inbnd_q_tbl[number].lower_base_addr); 353 pm8001_mw32(address, offset + 0x0C, 354 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr); 355 pm8001_mw32(address, offset + 0x10, 356 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); 357 } 358 359 /** 360 * update_outbnd_queue_table - update the outbound queue table to the HBA. 361 * @pm8001_ha: our hba card information 362 * @number: entry in the queue 363 */ 364 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 365 int number) 366 { 367 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 368 u16 offset = number * 0x24; 369 pm8001_mw32(address, offset + 0x00, 370 pm8001_ha->outbnd_q_tbl[number].element_size_cnt); 371 pm8001_mw32(address, offset + 0x04, 372 pm8001_ha->outbnd_q_tbl[number].upper_base_addr); 373 pm8001_mw32(address, offset + 0x08, 374 pm8001_ha->outbnd_q_tbl[number].lower_base_addr); 375 pm8001_mw32(address, offset + 0x0C, 376 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr); 377 pm8001_mw32(address, offset + 0x10, 378 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); 379 pm8001_mw32(address, offset + 0x1C, 380 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay); 381 } 382 383 /** 384 * pm8001_bar4_shift - function is called to shift BAR base address 385 * @pm8001_ha : our hba card infomation 386 * @shiftValue : shifting value in memory bar. 387 */ 388 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue) 389 { 390 u32 regVal; 391 unsigned long start; 392 393 /* program the inbound AXI translation Lower Address */ 394 pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue); 395 396 /* confirm the setting is written */ 397 start = jiffies + HZ; /* 1 sec */ 398 do { 399 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW); 400 } while ((regVal != shiftValue) && time_before(jiffies, start)); 401 402 if (regVal != shiftValue) { 403 PM8001_INIT_DBG(pm8001_ha, 404 pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW" 405 " = 0x%x\n", regVal)); 406 return -1; 407 } 408 return 0; 409 } 410 411 /** 412 * mpi_set_phys_g3_with_ssc 413 * @pm8001_ha: our hba card information 414 * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc. 415 */ 416 static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha, 417 u32 SSCbit) 418 { 419 u32 value, offset, i; 420 unsigned long flags; 421 422 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000 423 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000 424 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074 425 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074 426 #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12 427 #define PHY_G3_WITH_SSC_BIT_SHIFT 13 428 #define SNW3_PHY_CAPABILITIES_PARITY 31 429 430 /* 431 * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3) 432 * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7) 433 */ 434 spin_lock_irqsave(&pm8001_ha->lock, flags); 435 if (-1 == pm8001_bar4_shift(pm8001_ha, 436 SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) { 437 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 438 return; 439 } 440 441 for (i = 0; i < 4; i++) { 442 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i; 443 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501); 444 } 445 /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */ 446 if (-1 == pm8001_bar4_shift(pm8001_ha, 447 SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) { 448 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 449 return; 450 } 451 for (i = 4; i < 8; i++) { 452 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4); 453 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501); 454 } 455 /************************************************************* 456 Change the SSC upspreading value to 0x0 so that upspreading is disabled. 457 Device MABC SMOD0 Controls 458 Address: (via MEMBASE-III): 459 Using shifted destination address 0x0_0000: with Offset 0xD8 460 461 31:28 R/W Reserved Do not change 462 27:24 R/W SAS_SMOD_SPRDUP 0000 463 23:20 R/W SAS_SMOD_SPRDDN 0000 464 19:0 R/W Reserved Do not change 465 Upon power-up this register will read as 0x8990c016, 466 and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000 467 so that the written value will be 0x8090c016. 468 This will ensure only down-spreading SSC is enabled on the SPC. 469 *************************************************************/ 470 value = pm8001_cr32(pm8001_ha, 2, 0xd8); 471 pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016); 472 473 /*set the shifted destination address to 0x0 to avoid error operation */ 474 pm8001_bar4_shift(pm8001_ha, 0x0); 475 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 476 return; 477 } 478 479 /** 480 * mpi_set_open_retry_interval_reg 481 * @pm8001_ha: our hba card information 482 * @interval: interval time for each OPEN_REJECT (RETRY). The units are in 1us. 483 */ 484 static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha, 485 u32 interval) 486 { 487 u32 offset; 488 u32 value; 489 u32 i; 490 unsigned long flags; 491 492 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000 493 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000 494 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4 495 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4 496 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF 497 498 value = interval & OPEN_RETRY_INTERVAL_REG_MASK; 499 spin_lock_irqsave(&pm8001_ha->lock, flags); 500 /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/ 501 if (-1 == pm8001_bar4_shift(pm8001_ha, 502 OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) { 503 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 504 return; 505 } 506 for (i = 0; i < 4; i++) { 507 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i; 508 pm8001_cw32(pm8001_ha, 2, offset, value); 509 } 510 511 if (-1 == pm8001_bar4_shift(pm8001_ha, 512 OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) { 513 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 514 return; 515 } 516 for (i = 4; i < 8; i++) { 517 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4); 518 pm8001_cw32(pm8001_ha, 2, offset, value); 519 } 520 /*set the shifted destination address to 0x0 to avoid error operation */ 521 pm8001_bar4_shift(pm8001_ha, 0x0); 522 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 523 return; 524 } 525 526 /** 527 * mpi_init_check - check firmware initialization status. 528 * @pm8001_ha: our hba card information 529 */ 530 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha) 531 { 532 u32 max_wait_count; 533 u32 value; 534 u32 gst_len_mpistate; 535 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the 536 table is updated */ 537 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE); 538 /* wait until Inbound DoorBell Clear Register toggled */ 539 max_wait_count = 1 * 1000 * 1000;/* 1 sec */ 540 do { 541 udelay(1); 542 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 543 value &= SPC_MSGU_CFG_TABLE_UPDATE; 544 } while ((value != 0) && (--max_wait_count)); 545 546 if (!max_wait_count) 547 return -1; 548 /* check the MPI-State for initialization */ 549 gst_len_mpistate = 550 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 551 GST_GSTLEN_MPIS_OFFSET); 552 if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK)) 553 return -1; 554 /* check MPI Initialization error */ 555 gst_len_mpistate = gst_len_mpistate >> 16; 556 if (0x0000 != gst_len_mpistate) 557 return -1; 558 return 0; 559 } 560 561 /** 562 * check_fw_ready - The LLDD check if the FW is ready, if not, return error. 563 * @pm8001_ha: our hba card information 564 */ 565 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha) 566 { 567 u32 value, value1; 568 u32 max_wait_count; 569 /* check error state */ 570 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 571 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 572 /* check AAP error */ 573 if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) { 574 /* error state */ 575 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 576 return -1; 577 } 578 579 /* check IOP error */ 580 if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) { 581 /* error state */ 582 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 583 return -1; 584 } 585 586 /* bit 4-31 of scratch pad1 should be zeros if it is not 587 in error state*/ 588 if (value & SCRATCH_PAD1_STATE_MASK) { 589 /* error case */ 590 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 591 return -1; 592 } 593 594 /* bit 2, 4-31 of scratch pad2 should be zeros if it is not 595 in error state */ 596 if (value1 & SCRATCH_PAD2_STATE_MASK) { 597 /* error case */ 598 return -1; 599 } 600 601 max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */ 602 603 /* wait until scratch pad 1 and 2 registers in ready state */ 604 do { 605 udelay(1); 606 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) 607 & SCRATCH_PAD1_RDY; 608 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) 609 & SCRATCH_PAD2_RDY; 610 if ((--max_wait_count) == 0) 611 return -1; 612 } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY)); 613 return 0; 614 } 615 616 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha) 617 { 618 void __iomem *base_addr; 619 u32 value; 620 u32 offset; 621 u32 pcibar; 622 u32 pcilogic; 623 624 value = pm8001_cr32(pm8001_ha, 0, 0x44); 625 offset = value & 0x03FFFFFF; 626 PM8001_INIT_DBG(pm8001_ha, 627 pm8001_printk("Scratchpad 0 Offset: %x\n", offset)); 628 pcilogic = (value & 0xFC000000) >> 26; 629 pcibar = get_pci_bar_index(pcilogic); 630 PM8001_INIT_DBG(pm8001_ha, 631 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar)); 632 pm8001_ha->main_cfg_tbl_addr = base_addr = 633 pm8001_ha->io_mem[pcibar].memvirtaddr + offset; 634 pm8001_ha->general_stat_tbl_addr = 635 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18); 636 pm8001_ha->inbnd_q_tbl_addr = 637 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C); 638 pm8001_ha->outbnd_q_tbl_addr = 639 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20); 640 } 641 642 /** 643 * pm8001_chip_init - the main init function that initialize whole PM8001 chip. 644 * @pm8001_ha: our hba card information 645 */ 646 static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha) 647 { 648 u8 i = 0; 649 u16 deviceid; 650 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid); 651 /* 8081 controllers need BAR shift to access MPI space 652 * as this is shared with BIOS data */ 653 if (deviceid == 0x8081 || deviceid == 0x0042) { 654 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) { 655 PM8001_FAIL_DBG(pm8001_ha, 656 pm8001_printk("Shift Bar4 to 0x%x failed\n", 657 GSM_SM_BASE)); 658 return -1; 659 } 660 } 661 /* check the firmware status */ 662 if (-1 == check_fw_ready(pm8001_ha)) { 663 PM8001_FAIL_DBG(pm8001_ha, 664 pm8001_printk("Firmware is not ready!\n")); 665 return -EBUSY; 666 } 667 668 /* Initialize pci space address eg: mpi offset */ 669 init_pci_device_addresses(pm8001_ha); 670 init_default_table_values(pm8001_ha); 671 read_main_config_table(pm8001_ha); 672 read_general_status_table(pm8001_ha); 673 read_inbnd_queue_table(pm8001_ha); 674 read_outbnd_queue_table(pm8001_ha); 675 /* update main config table ,inbound table and outbound table */ 676 update_main_config_table(pm8001_ha); 677 for (i = 0; i < PM8001_MAX_INB_NUM; i++) 678 update_inbnd_queue_table(pm8001_ha, i); 679 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) 680 update_outbnd_queue_table(pm8001_ha, i); 681 /* 8081 controller donot require these operations */ 682 if (deviceid != 0x8081 && deviceid != 0x0042) { 683 mpi_set_phys_g3_with_ssc(pm8001_ha, 0); 684 /* 7->130ms, 34->500ms, 119->1.5s */ 685 mpi_set_open_retry_interval_reg(pm8001_ha, 119); 686 } 687 /* notify firmware update finished and check initialization status */ 688 if (0 == mpi_init_check(pm8001_ha)) { 689 PM8001_INIT_DBG(pm8001_ha, 690 pm8001_printk("MPI initialize successful!\n")); 691 } else 692 return -EBUSY; 693 /*This register is a 16-bit timer with a resolution of 1us. This is the 694 timer used for interrupt delay/coalescing in the PCIe Application Layer. 695 Zero is not a valid value. A value of 1 in the register will cause the 696 interrupts to be normal. A value greater than 1 will cause coalescing 697 delays.*/ 698 pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1); 699 pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0); 700 return 0; 701 } 702 703 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha) 704 { 705 u32 max_wait_count; 706 u32 value; 707 u32 gst_len_mpistate; 708 u16 deviceid; 709 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid); 710 if (deviceid == 0x8081 || deviceid == 0x0042) { 711 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) { 712 PM8001_FAIL_DBG(pm8001_ha, 713 pm8001_printk("Shift Bar4 to 0x%x failed\n", 714 GSM_SM_BASE)); 715 return -1; 716 } 717 } 718 init_pci_device_addresses(pm8001_ha); 719 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the 720 table is stop */ 721 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET); 722 723 /* wait until Inbound DoorBell Clear Register toggled */ 724 max_wait_count = 1 * 1000 * 1000;/* 1 sec */ 725 do { 726 udelay(1); 727 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 728 value &= SPC_MSGU_CFG_TABLE_RESET; 729 } while ((value != 0) && (--max_wait_count)); 730 731 if (!max_wait_count) { 732 PM8001_FAIL_DBG(pm8001_ha, 733 pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value)); 734 return -1; 735 } 736 737 /* check the MPI-State for termination in progress */ 738 /* wait until Inbound DoorBell Clear Register toggled */ 739 max_wait_count = 1 * 1000 * 1000; /* 1 sec */ 740 do { 741 udelay(1); 742 gst_len_mpistate = 743 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 744 GST_GSTLEN_MPIS_OFFSET); 745 if (GST_MPI_STATE_UNINIT == 746 (gst_len_mpistate & GST_MPI_STATE_MASK)) 747 break; 748 } while (--max_wait_count); 749 if (!max_wait_count) { 750 PM8001_FAIL_DBG(pm8001_ha, 751 pm8001_printk(" TIME OUT MPI State = 0x%x\n", 752 gst_len_mpistate & GST_MPI_STATE_MASK)); 753 return -1; 754 } 755 return 0; 756 } 757 758 /** 759 * soft_reset_ready_check - Function to check FW is ready for soft reset. 760 * @pm8001_ha: our hba card information 761 */ 762 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha) 763 { 764 u32 regVal, regVal1, regVal2; 765 if (mpi_uninit_check(pm8001_ha) != 0) { 766 PM8001_FAIL_DBG(pm8001_ha, 767 pm8001_printk("MPI state is not ready\n")); 768 return -1; 769 } 770 /* read the scratch pad 2 register bit 2 */ 771 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) 772 & SCRATCH_PAD2_FWRDY_RST; 773 if (regVal == SCRATCH_PAD2_FWRDY_RST) { 774 PM8001_INIT_DBG(pm8001_ha, 775 pm8001_printk("Firmware is ready for reset .\n")); 776 } else { 777 unsigned long flags; 778 /* Trigger NMI twice via RB6 */ 779 spin_lock_irqsave(&pm8001_ha->lock, flags); 780 if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) { 781 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 782 PM8001_FAIL_DBG(pm8001_ha, 783 pm8001_printk("Shift Bar4 to 0x%x failed\n", 784 RB6_ACCESS_REG)); 785 return -1; 786 } 787 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, 788 RB6_MAGIC_NUMBER_RST); 789 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST); 790 /* wait for 100 ms */ 791 mdelay(100); 792 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) & 793 SCRATCH_PAD2_FWRDY_RST; 794 if (regVal != SCRATCH_PAD2_FWRDY_RST) { 795 regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 796 regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 797 PM8001_FAIL_DBG(pm8001_ha, 798 pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1" 799 "=0x%x, MSGU_SCRATCH_PAD2=0x%x\n", 800 regVal1, regVal2)); 801 PM8001_FAIL_DBG(pm8001_ha, 802 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n", 803 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0))); 804 PM8001_FAIL_DBG(pm8001_ha, 805 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n", 806 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3))); 807 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 808 return -1; 809 } 810 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 811 } 812 return 0; 813 } 814 815 /** 816 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all 817 * the FW register status to the originated status. 818 * @pm8001_ha: our hba card information 819 */ 820 static int 821 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha) 822 { 823 u32 regVal, toggleVal; 824 u32 max_wait_count; 825 u32 regVal1, regVal2, regVal3; 826 u32 signature = 0x252acbcd; /* for host scratch pad0 */ 827 unsigned long flags; 828 829 /* step1: Check FW is ready for soft reset */ 830 if (soft_reset_ready_check(pm8001_ha) != 0) { 831 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("FW is not ready\n")); 832 return -1; 833 } 834 835 /* step 2: clear NMI status register on AAP1 and IOP, write the same 836 value to clear */ 837 /* map 0x60000 to BAR4(0x20), BAR2(win) */ 838 spin_lock_irqsave(&pm8001_ha->lock, flags); 839 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) { 840 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 841 PM8001_FAIL_DBG(pm8001_ha, 842 pm8001_printk("Shift Bar4 to 0x%x failed\n", 843 MBIC_AAP1_ADDR_BASE)); 844 return -1; 845 } 846 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP); 847 PM8001_INIT_DBG(pm8001_ha, 848 pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal)); 849 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0); 850 /* map 0x70000 to BAR4(0x20), BAR2(win) */ 851 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) { 852 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 853 PM8001_FAIL_DBG(pm8001_ha, 854 pm8001_printk("Shift Bar4 to 0x%x failed\n", 855 MBIC_IOP_ADDR_BASE)); 856 return -1; 857 } 858 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1); 859 PM8001_INIT_DBG(pm8001_ha, 860 pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal)); 861 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0); 862 863 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE); 864 PM8001_INIT_DBG(pm8001_ha, 865 pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal)); 866 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0); 867 868 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT); 869 PM8001_INIT_DBG(pm8001_ha, 870 pm8001_printk("PCIE - Event Interrupt = 0x%x\n", regVal)); 871 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal); 872 873 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE); 874 PM8001_INIT_DBG(pm8001_ha, 875 pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal)); 876 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0); 877 878 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT); 879 PM8001_INIT_DBG(pm8001_ha, 880 pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal)); 881 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal); 882 883 /* read the scratch pad 1 register bit 2 */ 884 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) 885 & SCRATCH_PAD1_RST; 886 toggleVal = regVal ^ SCRATCH_PAD1_RST; 887 888 /* set signature in host scratch pad0 register to tell SPC that the 889 host performs the soft reset */ 890 pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature); 891 892 /* read required registers for confirmming */ 893 /* map 0x0700000 to BAR4(0x20), BAR2(win) */ 894 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) { 895 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 896 PM8001_FAIL_DBG(pm8001_ha, 897 pm8001_printk("Shift Bar4 to 0x%x failed\n", 898 GSM_ADDR_BASE)); 899 return -1; 900 } 901 PM8001_INIT_DBG(pm8001_ha, 902 pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and" 903 " Reset = 0x%x\n", 904 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); 905 906 /* step 3: host read GSM Configuration and Reset register */ 907 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); 908 /* Put those bits to low */ 909 /* GSM XCBI offset = 0x70 0000 910 0x00 Bit 13 COM_SLV_SW_RSTB 1 911 0x00 Bit 12 QSSP_SW_RSTB 1 912 0x00 Bit 11 RAAE_SW_RSTB 1 913 0x00 Bit 9 RB_1_SW_RSTB 1 914 0x00 Bit 8 SM_SW_RSTB 1 915 */ 916 regVal &= ~(0x00003b00); 917 /* host write GSM Configuration and Reset register */ 918 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); 919 PM8001_INIT_DBG(pm8001_ha, 920 pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM " 921 "Configuration and Reset is set to = 0x%x\n", 922 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); 923 924 /* step 4: */ 925 /* disable GSM - Read Address Parity Check */ 926 regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK); 927 PM8001_INIT_DBG(pm8001_ha, 928 pm8001_printk("GSM 0x700038 - Read Address Parity Check " 929 "Enable = 0x%x\n", regVal1)); 930 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0); 931 PM8001_INIT_DBG(pm8001_ha, 932 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable" 933 "is set to = 0x%x\n", 934 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK))); 935 936 /* disable GSM - Write Address Parity Check */ 937 regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK); 938 PM8001_INIT_DBG(pm8001_ha, 939 pm8001_printk("GSM 0x700040 - Write Address Parity Check" 940 " Enable = 0x%x\n", regVal2)); 941 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0); 942 PM8001_INIT_DBG(pm8001_ha, 943 pm8001_printk("GSM 0x700040 - Write Address Parity Check " 944 "Enable is set to = 0x%x\n", 945 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK))); 946 947 /* disable GSM - Write Data Parity Check */ 948 regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK); 949 PM8001_INIT_DBG(pm8001_ha, 950 pm8001_printk("GSM 0x300048 - Write Data Parity Check" 951 " Enable = 0x%x\n", regVal3)); 952 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0); 953 PM8001_INIT_DBG(pm8001_ha, 954 pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable" 955 "is set to = 0x%x\n", 956 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK))); 957 958 /* step 5: delay 10 usec */ 959 udelay(10); 960 /* step 5-b: set GPIO-0 output control to tristate anyway */ 961 if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) { 962 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 963 PM8001_INIT_DBG(pm8001_ha, 964 pm8001_printk("Shift Bar4 to 0x%x failed\n", 965 GPIO_ADDR_BASE)); 966 return -1; 967 } 968 regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET); 969 PM8001_INIT_DBG(pm8001_ha, 970 pm8001_printk("GPIO Output Control Register:" 971 " = 0x%x\n", regVal)); 972 /* set GPIO-0 output control to tri-state */ 973 regVal &= 0xFFFFFFFC; 974 pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal); 975 976 /* Step 6: Reset the IOP and AAP1 */ 977 /* map 0x00000 to BAR4(0x20), BAR2(win) */ 978 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) { 979 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 980 PM8001_FAIL_DBG(pm8001_ha, 981 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n", 982 SPC_TOP_LEVEL_ADDR_BASE)); 983 return -1; 984 } 985 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 986 PM8001_INIT_DBG(pm8001_ha, 987 pm8001_printk("Top Register before resetting IOP/AAP1" 988 ":= 0x%x\n", regVal)); 989 regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS); 990 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 991 992 /* step 7: Reset the BDMA/OSSP */ 993 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 994 PM8001_INIT_DBG(pm8001_ha, 995 pm8001_printk("Top Register before resetting BDMA/OSSP" 996 ": = 0x%x\n", regVal)); 997 regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP); 998 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 999 1000 /* step 8: delay 10 usec */ 1001 udelay(10); 1002 1003 /* step 9: bring the BDMA and OSSP out of reset */ 1004 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 1005 PM8001_INIT_DBG(pm8001_ha, 1006 pm8001_printk("Top Register before bringing up BDMA/OSSP" 1007 ":= 0x%x\n", regVal)); 1008 regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP); 1009 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 1010 1011 /* step 10: delay 10 usec */ 1012 udelay(10); 1013 1014 /* step 11: reads and sets the GSM Configuration and Reset Register */ 1015 /* map 0x0700000 to BAR4(0x20), BAR2(win) */ 1016 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) { 1017 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1018 PM8001_FAIL_DBG(pm8001_ha, 1019 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n", 1020 GSM_ADDR_BASE)); 1021 return -1; 1022 } 1023 PM8001_INIT_DBG(pm8001_ha, 1024 pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and " 1025 "Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); 1026 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); 1027 /* Put those bits to high */ 1028 /* GSM XCBI offset = 0x70 0000 1029 0x00 Bit 13 COM_SLV_SW_RSTB 1 1030 0x00 Bit 12 QSSP_SW_RSTB 1 1031 0x00 Bit 11 RAAE_SW_RSTB 1 1032 0x00 Bit 9 RB_1_SW_RSTB 1 1033 0x00 Bit 8 SM_SW_RSTB 1 1034 */ 1035 regVal |= (GSM_CONFIG_RESET_VALUE); 1036 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); 1037 PM8001_INIT_DBG(pm8001_ha, 1038 pm8001_printk("GSM (0x00004088 ==> 0x00007b88) - GSM" 1039 " Configuration and Reset is set to = 0x%x\n", 1040 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); 1041 1042 /* step 12: Restore GSM - Read Address Parity Check */ 1043 regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK); 1044 /* just for debugging */ 1045 PM8001_INIT_DBG(pm8001_ha, 1046 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable" 1047 " = 0x%x\n", regVal)); 1048 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1); 1049 PM8001_INIT_DBG(pm8001_ha, 1050 pm8001_printk("GSM 0x700038 - Read Address Parity" 1051 " Check Enable is set to = 0x%x\n", 1052 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK))); 1053 /* Restore GSM - Write Address Parity Check */ 1054 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK); 1055 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2); 1056 PM8001_INIT_DBG(pm8001_ha, 1057 pm8001_printk("GSM 0x700040 - Write Address Parity Check" 1058 " Enable is set to = 0x%x\n", 1059 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK))); 1060 /* Restore GSM - Write Data Parity Check */ 1061 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK); 1062 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3); 1063 PM8001_INIT_DBG(pm8001_ha, 1064 pm8001_printk("GSM 0x700048 - Write Data Parity Check Enable" 1065 "is set to = 0x%x\n", 1066 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK))); 1067 1068 /* step 13: bring the IOP and AAP1 out of reset */ 1069 /* map 0x00000 to BAR4(0x20), BAR2(win) */ 1070 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) { 1071 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1072 PM8001_FAIL_DBG(pm8001_ha, 1073 pm8001_printk("Shift Bar4 to 0x%x failed\n", 1074 SPC_TOP_LEVEL_ADDR_BASE)); 1075 return -1; 1076 } 1077 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 1078 regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS); 1079 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 1080 1081 /* step 14: delay 10 usec - Normal Mode */ 1082 udelay(10); 1083 /* check Soft Reset Normal mode or Soft Reset HDA mode */ 1084 if (signature == SPC_SOFT_RESET_SIGNATURE) { 1085 /* step 15 (Normal Mode): wait until scratch pad1 register 1086 bit 2 toggled */ 1087 max_wait_count = 2 * 1000 * 1000;/* 2 sec */ 1088 do { 1089 udelay(1); 1090 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) & 1091 SCRATCH_PAD1_RST; 1092 } while ((regVal != toggleVal) && (--max_wait_count)); 1093 1094 if (!max_wait_count) { 1095 regVal = pm8001_cr32(pm8001_ha, 0, 1096 MSGU_SCRATCH_PAD_1); 1097 PM8001_FAIL_DBG(pm8001_ha, 1098 pm8001_printk("TIMEOUT : ToggleVal 0x%x," 1099 "MSGU_SCRATCH_PAD1 = 0x%x\n", 1100 toggleVal, regVal)); 1101 PM8001_FAIL_DBG(pm8001_ha, 1102 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n", 1103 pm8001_cr32(pm8001_ha, 0, 1104 MSGU_SCRATCH_PAD_0))); 1105 PM8001_FAIL_DBG(pm8001_ha, 1106 pm8001_printk("SCRATCH_PAD2 value = 0x%x\n", 1107 pm8001_cr32(pm8001_ha, 0, 1108 MSGU_SCRATCH_PAD_2))); 1109 PM8001_FAIL_DBG(pm8001_ha, 1110 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n", 1111 pm8001_cr32(pm8001_ha, 0, 1112 MSGU_SCRATCH_PAD_3))); 1113 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1114 return -1; 1115 } 1116 1117 /* step 16 (Normal) - Clear ODMR and ODCR */ 1118 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); 1119 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); 1120 1121 /* step 17 (Normal Mode): wait for the FW and IOP to get 1122 ready - 1 sec timeout */ 1123 /* Wait for the SPC Configuration Table to be ready */ 1124 if (check_fw_ready(pm8001_ha) == -1) { 1125 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1126 /* return error if MPI Configuration Table not ready */ 1127 PM8001_INIT_DBG(pm8001_ha, 1128 pm8001_printk("FW not ready SCRATCH_PAD1" 1129 " = 0x%x\n", regVal)); 1130 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 1131 /* return error if MPI Configuration Table not ready */ 1132 PM8001_INIT_DBG(pm8001_ha, 1133 pm8001_printk("FW not ready SCRATCH_PAD2" 1134 " = 0x%x\n", regVal)); 1135 PM8001_INIT_DBG(pm8001_ha, 1136 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n", 1137 pm8001_cr32(pm8001_ha, 0, 1138 MSGU_SCRATCH_PAD_0))); 1139 PM8001_INIT_DBG(pm8001_ha, 1140 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n", 1141 pm8001_cr32(pm8001_ha, 0, 1142 MSGU_SCRATCH_PAD_3))); 1143 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1144 return -1; 1145 } 1146 } 1147 pm8001_bar4_shift(pm8001_ha, 0); 1148 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1149 1150 PM8001_INIT_DBG(pm8001_ha, 1151 pm8001_printk("SPC soft reset Complete\n")); 1152 return 0; 1153 } 1154 1155 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha) 1156 { 1157 u32 i; 1158 u32 regVal; 1159 PM8001_INIT_DBG(pm8001_ha, 1160 pm8001_printk("chip reset start\n")); 1161 1162 /* do SPC chip reset. */ 1163 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); 1164 regVal &= ~(SPC_REG_RESET_DEVICE); 1165 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); 1166 1167 /* delay 10 usec */ 1168 udelay(10); 1169 1170 /* bring chip reset out of reset */ 1171 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); 1172 regVal |= SPC_REG_RESET_DEVICE; 1173 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); 1174 1175 /* delay 10 usec */ 1176 udelay(10); 1177 1178 /* wait for 20 msec until the firmware gets reloaded */ 1179 i = 20; 1180 do { 1181 mdelay(1); 1182 } while ((--i) != 0); 1183 1184 PM8001_INIT_DBG(pm8001_ha, 1185 pm8001_printk("chip reset finished\n")); 1186 } 1187 1188 /** 1189 * pm8001_chip_iounmap - which maped when initialized. 1190 * @pm8001_ha: our hba card information 1191 */ 1192 void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha) 1193 { 1194 s8 bar, logical = 0; 1195 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { 1196 /* 1197 ** logical BARs for SPC: 1198 ** bar 0 and 1 - logical BAR0 1199 ** bar 2 and 3 - logical BAR1 1200 ** bar4 - logical BAR2 1201 ** bar5 - logical BAR3 1202 ** Skip the appropriate assignments: 1203 */ 1204 if ((bar == 1) || (bar == 3)) 1205 continue; 1206 if (pm8001_ha->io_mem[logical].memvirtaddr) { 1207 iounmap(pm8001_ha->io_mem[logical].memvirtaddr); 1208 logical++; 1209 } 1210 } 1211 } 1212 1213 #ifndef PM8001_USE_MSIX 1214 /** 1215 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt 1216 * @pm8001_ha: our hba card information 1217 */ 1218 static void 1219 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha) 1220 { 1221 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); 1222 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); 1223 } 1224 1225 /** 1226 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt 1227 * @pm8001_ha: our hba card information 1228 */ 1229 static void 1230 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha) 1231 { 1232 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL); 1233 } 1234 1235 #else 1236 1237 /** 1238 * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt 1239 * @pm8001_ha: our hba card information 1240 * @int_vec_idx: interrupt number to enable 1241 */ 1242 static void 1243 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha, 1244 u32 int_vec_idx) 1245 { 1246 u32 msi_index; 1247 u32 value; 1248 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE; 1249 msi_index += MSIX_TABLE_BASE; 1250 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE); 1251 value = (1 << int_vec_idx); 1252 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, value); 1253 1254 } 1255 1256 /** 1257 * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt 1258 * @pm8001_ha: our hba card information 1259 * @int_vec_idx: interrupt number to disable 1260 */ 1261 static void 1262 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha, 1263 u32 int_vec_idx) 1264 { 1265 u32 msi_index; 1266 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE; 1267 msi_index += MSIX_TABLE_BASE; 1268 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE); 1269 } 1270 #endif 1271 1272 /** 1273 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt 1274 * @pm8001_ha: our hba card information 1275 * @vec: unused 1276 */ 1277 static void 1278 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1279 { 1280 #ifdef PM8001_USE_MSIX 1281 pm8001_chip_msix_interrupt_enable(pm8001_ha, 0); 1282 #else 1283 pm8001_chip_intx_interrupt_enable(pm8001_ha); 1284 #endif 1285 } 1286 1287 /** 1288 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt 1289 * @pm8001_ha: our hba card information 1290 * @vec: unused 1291 */ 1292 static void 1293 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1294 { 1295 #ifdef PM8001_USE_MSIX 1296 pm8001_chip_msix_interrupt_disable(pm8001_ha, 0); 1297 #else 1298 pm8001_chip_intx_interrupt_disable(pm8001_ha); 1299 #endif 1300 } 1301 1302 /** 1303 * pm8001_mpi_msg_free_get - get the free message buffer for transfer 1304 * inbound queue. 1305 * @circularQ: the inbound queue we want to transfer to HBA. 1306 * @messageSize: the message size of this transfer, normally it is 64 bytes 1307 * @messagePtr: the pointer to message. 1308 */ 1309 int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ, 1310 u16 messageSize, void **messagePtr) 1311 { 1312 u32 offset, consumer_index; 1313 struct mpi_msg_hdr *msgHeader; 1314 u8 bcCount = 1; /* only support single buffer */ 1315 1316 /* Checks is the requested message size can be allocated in this queue*/ 1317 if (messageSize > IOMB_SIZE_SPCV) { 1318 *messagePtr = NULL; 1319 return -1; 1320 } 1321 1322 /* Stores the new consumer index */ 1323 consumer_index = pm8001_read_32(circularQ->ci_virt); 1324 circularQ->consumer_index = cpu_to_le32(consumer_index); 1325 if (((circularQ->producer_idx + bcCount) % PM8001_MPI_QUEUE) == 1326 le32_to_cpu(circularQ->consumer_index)) { 1327 *messagePtr = NULL; 1328 return -1; 1329 } 1330 /* get memory IOMB buffer address */ 1331 offset = circularQ->producer_idx * messageSize; 1332 /* increment to next bcCount element */ 1333 circularQ->producer_idx = (circularQ->producer_idx + bcCount) 1334 % PM8001_MPI_QUEUE; 1335 /* Adds that distance to the base of the region virtual address plus 1336 the message header size*/ 1337 msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset); 1338 *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr); 1339 return 0; 1340 } 1341 1342 /** 1343 * pm8001_mpi_build_cmd- build the message queue for transfer, update the PI to 1344 * FW to tell the fw to get this message from IOMB. 1345 * @pm8001_ha: our hba card information 1346 * @circularQ: the inbound queue we want to transfer to HBA. 1347 * @opCode: the operation code represents commands which LLDD and fw recognized. 1348 * @payload: the command payload of each operation command. 1349 * @nb: size in bytes of the command payload 1350 * @responseQueue: queue to interrupt on w/ command response (if any) 1351 */ 1352 int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha, 1353 struct inbound_queue_table *circularQ, 1354 u32 opCode, void *payload, size_t nb, 1355 u32 responseQueue) 1356 { 1357 u32 Header = 0, hpriority = 0, bc = 1, category = 0x02; 1358 void *pMessage; 1359 1360 if (pm8001_mpi_msg_free_get(circularQ, pm8001_ha->iomb_size, 1361 &pMessage) < 0) { 1362 PM8001_IO_DBG(pm8001_ha, 1363 pm8001_printk("No free mpi buffer\n")); 1364 return -ENOMEM; 1365 } 1366 1367 if (nb > (pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr))) 1368 nb = pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr); 1369 memcpy(pMessage, payload, nb); 1370 if (nb + sizeof(struct mpi_msg_hdr) < pm8001_ha->iomb_size) 1371 memset(pMessage + nb, 0, pm8001_ha->iomb_size - 1372 (nb + sizeof(struct mpi_msg_hdr))); 1373 1374 /*Build the header*/ 1375 Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24) 1376 | ((responseQueue & 0x3F) << 16) 1377 | ((category & 0xF) << 12) | (opCode & 0xFFF)); 1378 1379 pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header)); 1380 /*Update the PI to the firmware*/ 1381 pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar, 1382 circularQ->pi_offset, circularQ->producer_idx); 1383 PM8001_DEVIO_DBG(pm8001_ha, 1384 pm8001_printk("INB Q %x OPCODE:%x , UPDATED PI=%d CI=%d\n", 1385 responseQueue, opCode, circularQ->producer_idx, 1386 circularQ->consumer_index)); 1387 return 0; 1388 } 1389 1390 u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg, 1391 struct outbound_queue_table *circularQ, u8 bc) 1392 { 1393 u32 producer_index; 1394 struct mpi_msg_hdr *msgHeader; 1395 struct mpi_msg_hdr *pOutBoundMsgHeader; 1396 1397 msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr)); 1398 pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + 1399 circularQ->consumer_idx * pm8001_ha->iomb_size); 1400 if (pOutBoundMsgHeader != msgHeader) { 1401 PM8001_FAIL_DBG(pm8001_ha, 1402 pm8001_printk("consumer_idx = %d msgHeader = %p\n", 1403 circularQ->consumer_idx, msgHeader)); 1404 1405 /* Update the producer index from SPC */ 1406 producer_index = pm8001_read_32(circularQ->pi_virt); 1407 circularQ->producer_index = cpu_to_le32(producer_index); 1408 PM8001_FAIL_DBG(pm8001_ha, 1409 pm8001_printk("consumer_idx = %d producer_index = %d" 1410 "msgHeader = %p\n", circularQ->consumer_idx, 1411 circularQ->producer_index, msgHeader)); 1412 return 0; 1413 } 1414 /* free the circular queue buffer elements associated with the message*/ 1415 circularQ->consumer_idx = (circularQ->consumer_idx + bc) 1416 % PM8001_MPI_QUEUE; 1417 /* update the CI of outbound queue */ 1418 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset, 1419 circularQ->consumer_idx); 1420 /* Update the producer index from SPC*/ 1421 producer_index = pm8001_read_32(circularQ->pi_virt); 1422 circularQ->producer_index = cpu_to_le32(producer_index); 1423 PM8001_IO_DBG(pm8001_ha, 1424 pm8001_printk(" CI=%d PI=%d\n", circularQ->consumer_idx, 1425 circularQ->producer_index)); 1426 return 0; 1427 } 1428 1429 /** 1430 * pm8001_mpi_msg_consume- get the MPI message from outbound queue 1431 * message table. 1432 * @pm8001_ha: our hba card information 1433 * @circularQ: the outbound queue table. 1434 * @messagePtr1: the message contents of this outbound message. 1435 * @pBC: the message size. 1436 */ 1437 u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha, 1438 struct outbound_queue_table *circularQ, 1439 void **messagePtr1, u8 *pBC) 1440 { 1441 struct mpi_msg_hdr *msgHeader; 1442 __le32 msgHeader_tmp; 1443 u32 header_tmp; 1444 do { 1445 /* If there are not-yet-delivered messages ... */ 1446 if (le32_to_cpu(circularQ->producer_index) 1447 != circularQ->consumer_idx) { 1448 /*Get the pointer to the circular queue buffer element*/ 1449 msgHeader = (struct mpi_msg_hdr *) 1450 (circularQ->base_virt + 1451 circularQ->consumer_idx * pm8001_ha->iomb_size); 1452 /* read header */ 1453 header_tmp = pm8001_read_32(msgHeader); 1454 msgHeader_tmp = cpu_to_le32(header_tmp); 1455 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk( 1456 "outbound opcode msgheader:%x ci=%d pi=%d\n", 1457 msgHeader_tmp, circularQ->consumer_idx, 1458 circularQ->producer_index)); 1459 if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) { 1460 if (OPC_OUB_SKIP_ENTRY != 1461 (le32_to_cpu(msgHeader_tmp) & 0xfff)) { 1462 *messagePtr1 = 1463 ((u8 *)msgHeader) + 1464 sizeof(struct mpi_msg_hdr); 1465 *pBC = (u8)((le32_to_cpu(msgHeader_tmp) 1466 >> 24) & 0x1f); 1467 PM8001_IO_DBG(pm8001_ha, 1468 pm8001_printk(": CI=%d PI=%d " 1469 "msgHeader=%x\n", 1470 circularQ->consumer_idx, 1471 circularQ->producer_index, 1472 msgHeader_tmp)); 1473 return MPI_IO_STATUS_SUCCESS; 1474 } else { 1475 circularQ->consumer_idx = 1476 (circularQ->consumer_idx + 1477 ((le32_to_cpu(msgHeader_tmp) 1478 >> 24) & 0x1f)) 1479 % PM8001_MPI_QUEUE; 1480 msgHeader_tmp = 0; 1481 pm8001_write_32(msgHeader, 0, 0); 1482 /* update the CI of outbound queue */ 1483 pm8001_cw32(pm8001_ha, 1484 circularQ->ci_pci_bar, 1485 circularQ->ci_offset, 1486 circularQ->consumer_idx); 1487 } 1488 } else { 1489 circularQ->consumer_idx = 1490 (circularQ->consumer_idx + 1491 ((le32_to_cpu(msgHeader_tmp) >> 24) & 1492 0x1f)) % PM8001_MPI_QUEUE; 1493 msgHeader_tmp = 0; 1494 pm8001_write_32(msgHeader, 0, 0); 1495 /* update the CI of outbound queue */ 1496 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, 1497 circularQ->ci_offset, 1498 circularQ->consumer_idx); 1499 return MPI_IO_STATUS_FAIL; 1500 } 1501 } else { 1502 u32 producer_index; 1503 void *pi_virt = circularQ->pi_virt; 1504 /* spurious interrupt during setup if 1505 * kexec-ing and driver doing a doorbell access 1506 * with the pre-kexec oq interrupt setup 1507 */ 1508 if (!pi_virt) 1509 break; 1510 /* Update the producer index from SPC */ 1511 producer_index = pm8001_read_32(pi_virt); 1512 circularQ->producer_index = cpu_to_le32(producer_index); 1513 } 1514 } while (le32_to_cpu(circularQ->producer_index) != 1515 circularQ->consumer_idx); 1516 /* while we don't have any more not-yet-delivered message */ 1517 /* report empty */ 1518 return MPI_IO_STATUS_BUSY; 1519 } 1520 1521 void pm8001_work_fn(struct work_struct *work) 1522 { 1523 struct pm8001_work *pw = container_of(work, struct pm8001_work, work); 1524 struct pm8001_device *pm8001_dev; 1525 struct domain_device *dev; 1526 1527 /* 1528 * So far, all users of this stash an associated structure here. 1529 * If we get here, and this pointer is null, then the action 1530 * was cancelled. This nullification happens when the device 1531 * goes away. 1532 */ 1533 pm8001_dev = pw->data; /* Most stash device structure */ 1534 if ((pm8001_dev == NULL) 1535 || ((pw->handler != IO_XFER_ERROR_BREAK) 1536 && (pm8001_dev->dev_type == SAS_PHY_UNUSED))) { 1537 kfree(pw); 1538 return; 1539 } 1540 1541 switch (pw->handler) { 1542 case IO_XFER_ERROR_BREAK: 1543 { /* This one stashes the sas_task instead */ 1544 struct sas_task *t = (struct sas_task *)pm8001_dev; 1545 u32 tag; 1546 struct pm8001_ccb_info *ccb; 1547 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha; 1548 unsigned long flags, flags1; 1549 struct task_status_struct *ts; 1550 int i; 1551 1552 if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC) 1553 break; /* Task still on lu */ 1554 spin_lock_irqsave(&pm8001_ha->lock, flags); 1555 1556 spin_lock_irqsave(&t->task_state_lock, flags1); 1557 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) { 1558 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1559 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1560 break; /* Task got completed by another */ 1561 } 1562 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1563 1564 /* Search for a possible ccb that matches the task */ 1565 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) { 1566 ccb = &pm8001_ha->ccb_info[i]; 1567 tag = ccb->ccb_tag; 1568 if ((tag != 0xFFFFFFFF) && (ccb->task == t)) 1569 break; 1570 } 1571 if (!ccb) { 1572 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1573 break; /* Task got freed by another */ 1574 } 1575 ts = &t->task_status; 1576 ts->resp = SAS_TASK_COMPLETE; 1577 /* Force the midlayer to retry */ 1578 ts->stat = SAS_QUEUE_FULL; 1579 pm8001_dev = ccb->device; 1580 if (pm8001_dev) 1581 pm8001_dev->running_req--; 1582 spin_lock_irqsave(&t->task_state_lock, flags1); 1583 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 1584 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 1585 t->task_state_flags |= SAS_TASK_STATE_DONE; 1586 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 1587 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1588 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p" 1589 " done with event 0x%x resp 0x%x stat 0x%x but" 1590 " aborted by upper layer!\n", 1591 t, pw->handler, ts->resp, ts->stat)); 1592 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1593 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1594 } else { 1595 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1596 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1597 mb();/* in order to force CPU ordering */ 1598 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1599 t->task_done(t); 1600 } 1601 } break; 1602 case IO_XFER_OPEN_RETRY_TIMEOUT: 1603 { /* This one stashes the sas_task instead */ 1604 struct sas_task *t = (struct sas_task *)pm8001_dev; 1605 u32 tag; 1606 struct pm8001_ccb_info *ccb; 1607 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha; 1608 unsigned long flags, flags1; 1609 int i, ret = 0; 1610 1611 PM8001_IO_DBG(pm8001_ha, 1612 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 1613 1614 ret = pm8001_query_task(t); 1615 1616 PM8001_IO_DBG(pm8001_ha, 1617 switch (ret) { 1618 case TMF_RESP_FUNC_SUCC: 1619 pm8001_printk("...Task on lu\n"); 1620 break; 1621 1622 case TMF_RESP_FUNC_COMPLETE: 1623 pm8001_printk("...Task NOT on lu\n"); 1624 break; 1625 1626 default: 1627 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk( 1628 "...query task failed!!!\n")); 1629 break; 1630 }); 1631 1632 spin_lock_irqsave(&pm8001_ha->lock, flags); 1633 1634 spin_lock_irqsave(&t->task_state_lock, flags1); 1635 1636 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) { 1637 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1638 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1639 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */ 1640 (void)pm8001_abort_task(t); 1641 break; /* Task got completed by another */ 1642 } 1643 1644 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1645 1646 /* Search for a possible ccb that matches the task */ 1647 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) { 1648 ccb = &pm8001_ha->ccb_info[i]; 1649 tag = ccb->ccb_tag; 1650 if ((tag != 0xFFFFFFFF) && (ccb->task == t)) 1651 break; 1652 } 1653 if (!ccb) { 1654 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1655 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */ 1656 (void)pm8001_abort_task(t); 1657 break; /* Task got freed by another */ 1658 } 1659 1660 pm8001_dev = ccb->device; 1661 dev = pm8001_dev->sas_device; 1662 1663 switch (ret) { 1664 case TMF_RESP_FUNC_SUCC: /* task on lu */ 1665 ccb->open_retry = 1; /* Snub completion */ 1666 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1667 ret = pm8001_abort_task(t); 1668 ccb->open_retry = 0; 1669 switch (ret) { 1670 case TMF_RESP_FUNC_SUCC: 1671 case TMF_RESP_FUNC_COMPLETE: 1672 break; 1673 default: /* device misbehavior */ 1674 ret = TMF_RESP_FUNC_FAILED; 1675 PM8001_IO_DBG(pm8001_ha, 1676 pm8001_printk("...Reset phy\n")); 1677 pm8001_I_T_nexus_reset(dev); 1678 break; 1679 } 1680 break; 1681 1682 case TMF_RESP_FUNC_COMPLETE: /* task not on lu */ 1683 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1684 /* Do we need to abort the task locally? */ 1685 break; 1686 1687 default: /* device misbehavior */ 1688 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1689 ret = TMF_RESP_FUNC_FAILED; 1690 PM8001_IO_DBG(pm8001_ha, 1691 pm8001_printk("...Reset phy\n")); 1692 pm8001_I_T_nexus_reset(dev); 1693 } 1694 1695 if (ret == TMF_RESP_FUNC_FAILED) 1696 t = NULL; 1697 pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev); 1698 PM8001_IO_DBG(pm8001_ha, pm8001_printk("...Complete\n")); 1699 } break; 1700 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1701 dev = pm8001_dev->sas_device; 1702 pm8001_I_T_nexus_event_handler(dev); 1703 break; 1704 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 1705 dev = pm8001_dev->sas_device; 1706 pm8001_I_T_nexus_reset(dev); 1707 break; 1708 case IO_DS_IN_ERROR: 1709 dev = pm8001_dev->sas_device; 1710 pm8001_I_T_nexus_reset(dev); 1711 break; 1712 case IO_DS_NON_OPERATIONAL: 1713 dev = pm8001_dev->sas_device; 1714 pm8001_I_T_nexus_reset(dev); 1715 break; 1716 } 1717 kfree(pw); 1718 } 1719 1720 int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data, 1721 int handler) 1722 { 1723 struct pm8001_work *pw; 1724 int ret = 0; 1725 1726 pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC); 1727 if (pw) { 1728 pw->pm8001_ha = pm8001_ha; 1729 pw->data = data; 1730 pw->handler = handler; 1731 INIT_WORK(&pw->work, pm8001_work_fn); 1732 queue_work(pm8001_wq, &pw->work); 1733 } else 1734 ret = -ENOMEM; 1735 1736 return ret; 1737 } 1738 1739 static void pm8001_send_abort_all(struct pm8001_hba_info *pm8001_ha, 1740 struct pm8001_device *pm8001_ha_dev) 1741 { 1742 int res; 1743 u32 ccb_tag; 1744 struct pm8001_ccb_info *ccb; 1745 struct sas_task *task = NULL; 1746 struct task_abort_req task_abort; 1747 struct inbound_queue_table *circularQ; 1748 u32 opc = OPC_INB_SATA_ABORT; 1749 int ret; 1750 1751 if (!pm8001_ha_dev) { 1752 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n")); 1753 return; 1754 } 1755 1756 task = sas_alloc_slow_task(GFP_ATOMIC); 1757 1758 if (!task) { 1759 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot " 1760 "allocate task\n")); 1761 return; 1762 } 1763 1764 task->task_done = pm8001_task_done; 1765 1766 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); 1767 if (res) 1768 return; 1769 1770 ccb = &pm8001_ha->ccb_info[ccb_tag]; 1771 ccb->device = pm8001_ha_dev; 1772 ccb->ccb_tag = ccb_tag; 1773 ccb->task = task; 1774 1775 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1776 1777 memset(&task_abort, 0, sizeof(task_abort)); 1778 task_abort.abort_all = cpu_to_le32(1); 1779 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 1780 task_abort.tag = cpu_to_le32(ccb_tag); 1781 1782 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 1783 sizeof(task_abort), 0); 1784 if (ret) 1785 pm8001_tag_free(pm8001_ha, ccb_tag); 1786 1787 } 1788 1789 static void pm8001_send_read_log(struct pm8001_hba_info *pm8001_ha, 1790 struct pm8001_device *pm8001_ha_dev) 1791 { 1792 struct sata_start_req sata_cmd; 1793 int res; 1794 u32 ccb_tag; 1795 struct pm8001_ccb_info *ccb; 1796 struct sas_task *task = NULL; 1797 struct host_to_dev_fis fis; 1798 struct domain_device *dev; 1799 struct inbound_queue_table *circularQ; 1800 u32 opc = OPC_INB_SATA_HOST_OPSTART; 1801 1802 task = sas_alloc_slow_task(GFP_ATOMIC); 1803 1804 if (!task) { 1805 PM8001_FAIL_DBG(pm8001_ha, 1806 pm8001_printk("cannot allocate task !!!\n")); 1807 return; 1808 } 1809 task->task_done = pm8001_task_done; 1810 1811 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); 1812 if (res) { 1813 sas_free_task(task); 1814 PM8001_FAIL_DBG(pm8001_ha, 1815 pm8001_printk("cannot allocate tag !!!\n")); 1816 return; 1817 } 1818 1819 /* allocate domain device by ourselves as libsas 1820 * is not going to provide any 1821 */ 1822 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC); 1823 if (!dev) { 1824 sas_free_task(task); 1825 pm8001_tag_free(pm8001_ha, ccb_tag); 1826 PM8001_FAIL_DBG(pm8001_ha, 1827 pm8001_printk("Domain device cannot be allocated\n")); 1828 return; 1829 } 1830 task->dev = dev; 1831 task->dev->lldd_dev = pm8001_ha_dev; 1832 1833 ccb = &pm8001_ha->ccb_info[ccb_tag]; 1834 ccb->device = pm8001_ha_dev; 1835 ccb->ccb_tag = ccb_tag; 1836 ccb->task = task; 1837 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG; 1838 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG; 1839 1840 memset(&sata_cmd, 0, sizeof(sata_cmd)); 1841 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1842 1843 /* construct read log FIS */ 1844 memset(&fis, 0, sizeof(struct host_to_dev_fis)); 1845 fis.fis_type = 0x27; 1846 fis.flags = 0x80; 1847 fis.command = ATA_CMD_READ_LOG_EXT; 1848 fis.lbal = 0x10; 1849 fis.sector_count = 0x1; 1850 1851 sata_cmd.tag = cpu_to_le32(ccb_tag); 1852 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 1853 sata_cmd.ncqtag_atap_dir_m |= ((0x1 << 7) | (0x5 << 9)); 1854 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis)); 1855 1856 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 1857 sizeof(sata_cmd), 0); 1858 if (res) { 1859 sas_free_task(task); 1860 pm8001_tag_free(pm8001_ha, ccb_tag); 1861 kfree(dev); 1862 } 1863 } 1864 1865 /** 1866 * mpi_ssp_completion- process the event that FW response to the SSP request. 1867 * @pm8001_ha: our hba card information 1868 * @piomb: the message contents of this outbound message. 1869 * 1870 * When FW has completed a ssp request for example a IO request, after it has 1871 * filled the SG data with the data, it will trigger this event represent 1872 * that he has finished the job,please check the coresponding buffer. 1873 * So we will tell the caller who maybe waiting the result to tell upper layer 1874 * that the task has been finished. 1875 */ 1876 static void 1877 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb) 1878 { 1879 struct sas_task *t; 1880 struct pm8001_ccb_info *ccb; 1881 unsigned long flags; 1882 u32 status; 1883 u32 param; 1884 u32 tag; 1885 struct ssp_completion_resp *psspPayload; 1886 struct task_status_struct *ts; 1887 struct ssp_response_iu *iu; 1888 struct pm8001_device *pm8001_dev; 1889 psspPayload = (struct ssp_completion_resp *)(piomb + 4); 1890 status = le32_to_cpu(psspPayload->status); 1891 tag = le32_to_cpu(psspPayload->tag); 1892 ccb = &pm8001_ha->ccb_info[tag]; 1893 if ((status == IO_ABORTED) && ccb->open_retry) { 1894 /* Being completed by another */ 1895 ccb->open_retry = 0; 1896 return; 1897 } 1898 pm8001_dev = ccb->device; 1899 param = le32_to_cpu(psspPayload->param); 1900 1901 t = ccb->task; 1902 1903 if (status && status != IO_UNDERFLOW) 1904 PM8001_FAIL_DBG(pm8001_ha, 1905 pm8001_printk("sas IO status 0x%x\n", status)); 1906 if (unlikely(!t || !t->lldd_task || !t->dev)) 1907 return; 1908 ts = &t->task_status; 1909 /* Print sas address of IO failed device */ 1910 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 1911 (status != IO_UNDERFLOW)) 1912 PM8001_FAIL_DBG(pm8001_ha, 1913 pm8001_printk("SAS Address of IO Failure Drive:" 1914 "%016llx", SAS_ADDR(t->dev->sas_addr))); 1915 1916 if (status) 1917 PM8001_IOERR_DBG(pm8001_ha, pm8001_printk( 1918 "status:0x%x, tag:0x%x, task:0x%p\n", 1919 status, tag, t)); 1920 1921 switch (status) { 1922 case IO_SUCCESS: 1923 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS" 1924 ",param = %d\n", param)); 1925 if (param == 0) { 1926 ts->resp = SAS_TASK_COMPLETE; 1927 ts->stat = SAM_STAT_GOOD; 1928 } else { 1929 ts->resp = SAS_TASK_COMPLETE; 1930 ts->stat = SAS_PROTO_RESPONSE; 1931 ts->residual = param; 1932 iu = &psspPayload->ssp_resp_iu; 1933 sas_ssp_task_response(pm8001_ha->dev, t, iu); 1934 } 1935 if (pm8001_dev) 1936 pm8001_dev->running_req--; 1937 break; 1938 case IO_ABORTED: 1939 PM8001_IO_DBG(pm8001_ha, 1940 pm8001_printk("IO_ABORTED IOMB Tag\n")); 1941 ts->resp = SAS_TASK_COMPLETE; 1942 ts->stat = SAS_ABORTED_TASK; 1943 break; 1944 case IO_UNDERFLOW: 1945 /* SSP Completion with error */ 1946 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW" 1947 ",param = %d\n", param)); 1948 ts->resp = SAS_TASK_COMPLETE; 1949 ts->stat = SAS_DATA_UNDERRUN; 1950 ts->residual = param; 1951 if (pm8001_dev) 1952 pm8001_dev->running_req--; 1953 break; 1954 case IO_NO_DEVICE: 1955 PM8001_IO_DBG(pm8001_ha, 1956 pm8001_printk("IO_NO_DEVICE\n")); 1957 ts->resp = SAS_TASK_UNDELIVERED; 1958 ts->stat = SAS_PHY_DOWN; 1959 break; 1960 case IO_XFER_ERROR_BREAK: 1961 PM8001_IO_DBG(pm8001_ha, 1962 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 1963 ts->resp = SAS_TASK_COMPLETE; 1964 ts->stat = SAS_OPEN_REJECT; 1965 /* Force the midlayer to retry */ 1966 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1967 break; 1968 case IO_XFER_ERROR_PHY_NOT_READY: 1969 PM8001_IO_DBG(pm8001_ha, 1970 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 1971 ts->resp = SAS_TASK_COMPLETE; 1972 ts->stat = SAS_OPEN_REJECT; 1973 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1974 break; 1975 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 1976 PM8001_IO_DBG(pm8001_ha, 1977 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 1978 ts->resp = SAS_TASK_COMPLETE; 1979 ts->stat = SAS_OPEN_REJECT; 1980 ts->open_rej_reason = SAS_OREJ_EPROTO; 1981 break; 1982 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 1983 PM8001_IO_DBG(pm8001_ha, 1984 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 1985 ts->resp = SAS_TASK_COMPLETE; 1986 ts->stat = SAS_OPEN_REJECT; 1987 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1988 break; 1989 case IO_OPEN_CNX_ERROR_BREAK: 1990 PM8001_IO_DBG(pm8001_ha, 1991 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 1992 ts->resp = SAS_TASK_COMPLETE; 1993 ts->stat = SAS_OPEN_REJECT; 1994 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1995 break; 1996 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1997 PM8001_IO_DBG(pm8001_ha, 1998 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 1999 ts->resp = SAS_TASK_COMPLETE; 2000 ts->stat = SAS_OPEN_REJECT; 2001 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2002 if (!t->uldd_task) 2003 pm8001_handle_event(pm8001_ha, 2004 pm8001_dev, 2005 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2006 break; 2007 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2008 PM8001_IO_DBG(pm8001_ha, 2009 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2010 ts->resp = SAS_TASK_COMPLETE; 2011 ts->stat = SAS_OPEN_REJECT; 2012 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2013 break; 2014 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2015 PM8001_IO_DBG(pm8001_ha, 2016 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 2017 "NOT_SUPPORTED\n")); 2018 ts->resp = SAS_TASK_COMPLETE; 2019 ts->stat = SAS_OPEN_REJECT; 2020 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2021 break; 2022 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2023 PM8001_IO_DBG(pm8001_ha, 2024 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2025 ts->resp = SAS_TASK_UNDELIVERED; 2026 ts->stat = SAS_OPEN_REJECT; 2027 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2028 break; 2029 case IO_XFER_ERROR_NAK_RECEIVED: 2030 PM8001_IO_DBG(pm8001_ha, 2031 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 2032 ts->resp = SAS_TASK_COMPLETE; 2033 ts->stat = SAS_OPEN_REJECT; 2034 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2035 break; 2036 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2037 PM8001_IO_DBG(pm8001_ha, 2038 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 2039 ts->resp = SAS_TASK_COMPLETE; 2040 ts->stat = SAS_NAK_R_ERR; 2041 break; 2042 case IO_XFER_ERROR_DMA: 2043 PM8001_IO_DBG(pm8001_ha, 2044 pm8001_printk("IO_XFER_ERROR_DMA\n")); 2045 ts->resp = SAS_TASK_COMPLETE; 2046 ts->stat = SAS_OPEN_REJECT; 2047 break; 2048 case IO_XFER_OPEN_RETRY_TIMEOUT: 2049 PM8001_IO_DBG(pm8001_ha, 2050 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2051 ts->resp = SAS_TASK_COMPLETE; 2052 ts->stat = SAS_OPEN_REJECT; 2053 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2054 break; 2055 case IO_XFER_ERROR_OFFSET_MISMATCH: 2056 PM8001_IO_DBG(pm8001_ha, 2057 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 2058 ts->resp = SAS_TASK_COMPLETE; 2059 ts->stat = SAS_OPEN_REJECT; 2060 break; 2061 case IO_PORT_IN_RESET: 2062 PM8001_IO_DBG(pm8001_ha, 2063 pm8001_printk("IO_PORT_IN_RESET\n")); 2064 ts->resp = SAS_TASK_COMPLETE; 2065 ts->stat = SAS_OPEN_REJECT; 2066 break; 2067 case IO_DS_NON_OPERATIONAL: 2068 PM8001_IO_DBG(pm8001_ha, 2069 pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 2070 ts->resp = SAS_TASK_COMPLETE; 2071 ts->stat = SAS_OPEN_REJECT; 2072 if (!t->uldd_task) 2073 pm8001_handle_event(pm8001_ha, 2074 pm8001_dev, 2075 IO_DS_NON_OPERATIONAL); 2076 break; 2077 case IO_DS_IN_RECOVERY: 2078 PM8001_IO_DBG(pm8001_ha, 2079 pm8001_printk("IO_DS_IN_RECOVERY\n")); 2080 ts->resp = SAS_TASK_COMPLETE; 2081 ts->stat = SAS_OPEN_REJECT; 2082 break; 2083 case IO_TM_TAG_NOT_FOUND: 2084 PM8001_IO_DBG(pm8001_ha, 2085 pm8001_printk("IO_TM_TAG_NOT_FOUND\n")); 2086 ts->resp = SAS_TASK_COMPLETE; 2087 ts->stat = SAS_OPEN_REJECT; 2088 break; 2089 case IO_SSP_EXT_IU_ZERO_LEN_ERROR: 2090 PM8001_IO_DBG(pm8001_ha, 2091 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n")); 2092 ts->resp = SAS_TASK_COMPLETE; 2093 ts->stat = SAS_OPEN_REJECT; 2094 break; 2095 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2096 PM8001_IO_DBG(pm8001_ha, 2097 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 2098 ts->resp = SAS_TASK_COMPLETE; 2099 ts->stat = SAS_OPEN_REJECT; 2100 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2101 break; 2102 default: 2103 PM8001_DEVIO_DBG(pm8001_ha, 2104 pm8001_printk("Unknown status 0x%x\n", status)); 2105 /* not allowed case. Therefore, return failed status */ 2106 ts->resp = SAS_TASK_COMPLETE; 2107 ts->stat = SAS_OPEN_REJECT; 2108 break; 2109 } 2110 PM8001_IO_DBG(pm8001_ha, 2111 pm8001_printk("scsi_status = %x\n ", 2112 psspPayload->ssp_resp_iu.status)); 2113 spin_lock_irqsave(&t->task_state_lock, flags); 2114 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2115 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2116 t->task_state_flags |= SAS_TASK_STATE_DONE; 2117 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2118 spin_unlock_irqrestore(&t->task_state_lock, flags); 2119 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with" 2120 " io_status 0x%x resp 0x%x " 2121 "stat 0x%x but aborted by upper layer!\n", 2122 t, status, ts->resp, ts->stat)); 2123 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2124 } else { 2125 spin_unlock_irqrestore(&t->task_state_lock, flags); 2126 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2127 mb();/* in order to force CPU ordering */ 2128 t->task_done(t); 2129 } 2130 } 2131 2132 /*See the comments for mpi_ssp_completion */ 2133 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 2134 { 2135 struct sas_task *t; 2136 unsigned long flags; 2137 struct task_status_struct *ts; 2138 struct pm8001_ccb_info *ccb; 2139 struct pm8001_device *pm8001_dev; 2140 struct ssp_event_resp *psspPayload = 2141 (struct ssp_event_resp *)(piomb + 4); 2142 u32 event = le32_to_cpu(psspPayload->event); 2143 u32 tag = le32_to_cpu(psspPayload->tag); 2144 u32 port_id = le32_to_cpu(psspPayload->port_id); 2145 u32 dev_id = le32_to_cpu(psspPayload->device_id); 2146 2147 ccb = &pm8001_ha->ccb_info[tag]; 2148 t = ccb->task; 2149 pm8001_dev = ccb->device; 2150 if (event) 2151 PM8001_FAIL_DBG(pm8001_ha, 2152 pm8001_printk("sas IO status 0x%x\n", event)); 2153 if (unlikely(!t || !t->lldd_task || !t->dev)) 2154 return; 2155 ts = &t->task_status; 2156 PM8001_DEVIO_DBG(pm8001_ha, 2157 pm8001_printk("port_id = %x,device_id = %x\n", 2158 port_id, dev_id)); 2159 switch (event) { 2160 case IO_OVERFLOW: 2161 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");) 2162 ts->resp = SAS_TASK_COMPLETE; 2163 ts->stat = SAS_DATA_OVERRUN; 2164 ts->residual = 0; 2165 if (pm8001_dev) 2166 pm8001_dev->running_req--; 2167 break; 2168 case IO_XFER_ERROR_BREAK: 2169 PM8001_IO_DBG(pm8001_ha, 2170 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2171 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK); 2172 return; 2173 case IO_XFER_ERROR_PHY_NOT_READY: 2174 PM8001_IO_DBG(pm8001_ha, 2175 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2176 ts->resp = SAS_TASK_COMPLETE; 2177 ts->stat = SAS_OPEN_REJECT; 2178 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2179 break; 2180 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2181 PM8001_IO_DBG(pm8001_ha, 2182 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT" 2183 "_SUPPORTED\n")); 2184 ts->resp = SAS_TASK_COMPLETE; 2185 ts->stat = SAS_OPEN_REJECT; 2186 ts->open_rej_reason = SAS_OREJ_EPROTO; 2187 break; 2188 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2189 PM8001_IO_DBG(pm8001_ha, 2190 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2191 ts->resp = SAS_TASK_COMPLETE; 2192 ts->stat = SAS_OPEN_REJECT; 2193 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2194 break; 2195 case IO_OPEN_CNX_ERROR_BREAK: 2196 PM8001_IO_DBG(pm8001_ha, 2197 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2198 ts->resp = SAS_TASK_COMPLETE; 2199 ts->stat = SAS_OPEN_REJECT; 2200 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2201 break; 2202 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2203 PM8001_IO_DBG(pm8001_ha, 2204 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2205 ts->resp = SAS_TASK_COMPLETE; 2206 ts->stat = SAS_OPEN_REJECT; 2207 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2208 if (!t->uldd_task) 2209 pm8001_handle_event(pm8001_ha, 2210 pm8001_dev, 2211 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2212 break; 2213 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2214 PM8001_IO_DBG(pm8001_ha, 2215 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2216 ts->resp = SAS_TASK_COMPLETE; 2217 ts->stat = SAS_OPEN_REJECT; 2218 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2219 break; 2220 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2221 PM8001_IO_DBG(pm8001_ha, 2222 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 2223 "NOT_SUPPORTED\n")); 2224 ts->resp = SAS_TASK_COMPLETE; 2225 ts->stat = SAS_OPEN_REJECT; 2226 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2227 break; 2228 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2229 PM8001_IO_DBG(pm8001_ha, 2230 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2231 ts->resp = SAS_TASK_COMPLETE; 2232 ts->stat = SAS_OPEN_REJECT; 2233 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2234 break; 2235 case IO_XFER_ERROR_NAK_RECEIVED: 2236 PM8001_IO_DBG(pm8001_ha, 2237 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 2238 ts->resp = SAS_TASK_COMPLETE; 2239 ts->stat = SAS_OPEN_REJECT; 2240 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2241 break; 2242 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2243 PM8001_IO_DBG(pm8001_ha, 2244 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 2245 ts->resp = SAS_TASK_COMPLETE; 2246 ts->stat = SAS_NAK_R_ERR; 2247 break; 2248 case IO_XFER_OPEN_RETRY_TIMEOUT: 2249 PM8001_IO_DBG(pm8001_ha, 2250 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2251 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT); 2252 return; 2253 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2254 PM8001_IO_DBG(pm8001_ha, 2255 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n")); 2256 ts->resp = SAS_TASK_COMPLETE; 2257 ts->stat = SAS_DATA_OVERRUN; 2258 break; 2259 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2260 PM8001_IO_DBG(pm8001_ha, 2261 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n")); 2262 ts->resp = SAS_TASK_COMPLETE; 2263 ts->stat = SAS_DATA_OVERRUN; 2264 break; 2265 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2266 PM8001_IO_DBG(pm8001_ha, 2267 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n")); 2268 ts->resp = SAS_TASK_COMPLETE; 2269 ts->stat = SAS_DATA_OVERRUN; 2270 break; 2271 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT: 2272 PM8001_IO_DBG(pm8001_ha, 2273 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n")); 2274 ts->resp = SAS_TASK_COMPLETE; 2275 ts->stat = SAS_DATA_OVERRUN; 2276 break; 2277 case IO_XFER_ERROR_OFFSET_MISMATCH: 2278 PM8001_IO_DBG(pm8001_ha, 2279 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 2280 ts->resp = SAS_TASK_COMPLETE; 2281 ts->stat = SAS_DATA_OVERRUN; 2282 break; 2283 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2284 PM8001_IO_DBG(pm8001_ha, 2285 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n")); 2286 ts->resp = SAS_TASK_COMPLETE; 2287 ts->stat = SAS_DATA_OVERRUN; 2288 break; 2289 case IO_XFER_CMD_FRAME_ISSUED: 2290 PM8001_IO_DBG(pm8001_ha, 2291 pm8001_printk(" IO_XFER_CMD_FRAME_ISSUED\n")); 2292 return; 2293 default: 2294 PM8001_DEVIO_DBG(pm8001_ha, 2295 pm8001_printk("Unknown status 0x%x\n", event)); 2296 /* not allowed case. Therefore, return failed status */ 2297 ts->resp = SAS_TASK_COMPLETE; 2298 ts->stat = SAS_DATA_OVERRUN; 2299 break; 2300 } 2301 spin_lock_irqsave(&t->task_state_lock, flags); 2302 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2303 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2304 t->task_state_flags |= SAS_TASK_STATE_DONE; 2305 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2306 spin_unlock_irqrestore(&t->task_state_lock, flags); 2307 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with" 2308 " event 0x%x resp 0x%x " 2309 "stat 0x%x but aborted by upper layer!\n", 2310 t, event, ts->resp, ts->stat)); 2311 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2312 } else { 2313 spin_unlock_irqrestore(&t->task_state_lock, flags); 2314 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2315 mb();/* in order to force CPU ordering */ 2316 t->task_done(t); 2317 } 2318 } 2319 2320 /*See the comments for mpi_ssp_completion */ 2321 static void 2322 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2323 { 2324 struct sas_task *t; 2325 struct pm8001_ccb_info *ccb; 2326 u32 param; 2327 u32 status; 2328 u32 tag; 2329 int i, j; 2330 u8 sata_addr_low[4]; 2331 u32 temp_sata_addr_low; 2332 u8 sata_addr_hi[4]; 2333 u32 temp_sata_addr_hi; 2334 struct sata_completion_resp *psataPayload; 2335 struct task_status_struct *ts; 2336 struct ata_task_resp *resp ; 2337 u32 *sata_resp; 2338 struct pm8001_device *pm8001_dev; 2339 unsigned long flags; 2340 2341 psataPayload = (struct sata_completion_resp *)(piomb + 4); 2342 status = le32_to_cpu(psataPayload->status); 2343 tag = le32_to_cpu(psataPayload->tag); 2344 2345 if (!tag) { 2346 PM8001_FAIL_DBG(pm8001_ha, 2347 pm8001_printk("tag null\n")); 2348 return; 2349 } 2350 ccb = &pm8001_ha->ccb_info[tag]; 2351 param = le32_to_cpu(psataPayload->param); 2352 if (ccb) { 2353 t = ccb->task; 2354 pm8001_dev = ccb->device; 2355 } else { 2356 PM8001_FAIL_DBG(pm8001_ha, 2357 pm8001_printk("ccb null\n")); 2358 return; 2359 } 2360 2361 if (t) { 2362 if (t->dev && (t->dev->lldd_dev)) 2363 pm8001_dev = t->dev->lldd_dev; 2364 } else { 2365 PM8001_FAIL_DBG(pm8001_ha, 2366 pm8001_printk("task null\n")); 2367 return; 2368 } 2369 2370 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG)) 2371 && unlikely(!t || !t->lldd_task || !t->dev)) { 2372 PM8001_FAIL_DBG(pm8001_ha, 2373 pm8001_printk("task or dev null\n")); 2374 return; 2375 } 2376 2377 ts = &t->task_status; 2378 if (!ts) { 2379 PM8001_FAIL_DBG(pm8001_ha, 2380 pm8001_printk("ts null\n")); 2381 return; 2382 } 2383 2384 if (status) 2385 PM8001_IOERR_DBG(pm8001_ha, pm8001_printk( 2386 "status:0x%x, tag:0x%x, task::0x%p\n", 2387 status, tag, t)); 2388 2389 /* Print sas address of IO failed device */ 2390 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 2391 (status != IO_UNDERFLOW)) { 2392 if (!((t->dev->parent) && 2393 (dev_is_expander(t->dev->parent->dev_type)))) { 2394 for (i = 0 , j = 4; j <= 7 && i <= 3; i++ , j++) 2395 sata_addr_low[i] = pm8001_ha->sas_addr[j]; 2396 for (i = 0 , j = 0; j <= 3 && i <= 3; i++ , j++) 2397 sata_addr_hi[i] = pm8001_ha->sas_addr[j]; 2398 memcpy(&temp_sata_addr_low, sata_addr_low, 2399 sizeof(sata_addr_low)); 2400 memcpy(&temp_sata_addr_hi, sata_addr_hi, 2401 sizeof(sata_addr_hi)); 2402 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff) 2403 |((temp_sata_addr_hi << 8) & 2404 0xff0000) | 2405 ((temp_sata_addr_hi >> 8) 2406 & 0xff00) | 2407 ((temp_sata_addr_hi << 24) & 2408 0xff000000)); 2409 temp_sata_addr_low = ((((temp_sata_addr_low >> 24) 2410 & 0xff) | 2411 ((temp_sata_addr_low << 8) 2412 & 0xff0000) | 2413 ((temp_sata_addr_low >> 8) 2414 & 0xff00) | 2415 ((temp_sata_addr_low << 24) 2416 & 0xff000000)) + 2417 pm8001_dev->attached_phy + 2418 0x10); 2419 PM8001_FAIL_DBG(pm8001_ha, 2420 pm8001_printk("SAS Address of IO Failure Drive:" 2421 "%08x%08x", temp_sata_addr_hi, 2422 temp_sata_addr_low)); 2423 } else { 2424 PM8001_FAIL_DBG(pm8001_ha, 2425 pm8001_printk("SAS Address of IO Failure Drive:" 2426 "%016llx", SAS_ADDR(t->dev->sas_addr))); 2427 } 2428 } 2429 switch (status) { 2430 case IO_SUCCESS: 2431 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); 2432 if (param == 0) { 2433 ts->resp = SAS_TASK_COMPLETE; 2434 ts->stat = SAM_STAT_GOOD; 2435 /* check if response is for SEND READ LOG */ 2436 if (pm8001_dev && 2437 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) { 2438 /* set new bit for abort_all */ 2439 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG; 2440 /* clear bit for read log */ 2441 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF; 2442 pm8001_send_abort_all(pm8001_ha, pm8001_dev); 2443 /* Free the tag */ 2444 pm8001_tag_free(pm8001_ha, tag); 2445 sas_free_task(t); 2446 return; 2447 } 2448 } else { 2449 u8 len; 2450 ts->resp = SAS_TASK_COMPLETE; 2451 ts->stat = SAS_PROTO_RESPONSE; 2452 ts->residual = param; 2453 PM8001_IO_DBG(pm8001_ha, 2454 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n", 2455 param)); 2456 sata_resp = &psataPayload->sata_resp[0]; 2457 resp = (struct ata_task_resp *)ts->buf; 2458 if (t->ata_task.dma_xfer == 0 && 2459 t->data_dir == DMA_FROM_DEVICE) { 2460 len = sizeof(struct pio_setup_fis); 2461 PM8001_IO_DBG(pm8001_ha, 2462 pm8001_printk("PIO read len = %d\n", len)); 2463 } else if (t->ata_task.use_ncq) { 2464 len = sizeof(struct set_dev_bits_fis); 2465 PM8001_IO_DBG(pm8001_ha, 2466 pm8001_printk("FPDMA len = %d\n", len)); 2467 } else { 2468 len = sizeof(struct dev_to_host_fis); 2469 PM8001_IO_DBG(pm8001_ha, 2470 pm8001_printk("other len = %d\n", len)); 2471 } 2472 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) { 2473 resp->frame_len = len; 2474 memcpy(&resp->ending_fis[0], sata_resp, len); 2475 ts->buf_valid_size = sizeof(*resp); 2476 } else 2477 PM8001_IO_DBG(pm8001_ha, 2478 pm8001_printk("response to large\n")); 2479 } 2480 if (pm8001_dev) 2481 pm8001_dev->running_req--; 2482 break; 2483 case IO_ABORTED: 2484 PM8001_IO_DBG(pm8001_ha, 2485 pm8001_printk("IO_ABORTED IOMB Tag\n")); 2486 ts->resp = SAS_TASK_COMPLETE; 2487 ts->stat = SAS_ABORTED_TASK; 2488 if (pm8001_dev) 2489 pm8001_dev->running_req--; 2490 break; 2491 /* following cases are to do cases */ 2492 case IO_UNDERFLOW: 2493 /* SATA Completion with error */ 2494 PM8001_IO_DBG(pm8001_ha, 2495 pm8001_printk("IO_UNDERFLOW param = %d\n", param)); 2496 ts->resp = SAS_TASK_COMPLETE; 2497 ts->stat = SAS_DATA_UNDERRUN; 2498 ts->residual = param; 2499 if (pm8001_dev) 2500 pm8001_dev->running_req--; 2501 break; 2502 case IO_NO_DEVICE: 2503 PM8001_IO_DBG(pm8001_ha, 2504 pm8001_printk("IO_NO_DEVICE\n")); 2505 ts->resp = SAS_TASK_UNDELIVERED; 2506 ts->stat = SAS_PHY_DOWN; 2507 break; 2508 case IO_XFER_ERROR_BREAK: 2509 PM8001_IO_DBG(pm8001_ha, 2510 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2511 ts->resp = SAS_TASK_COMPLETE; 2512 ts->stat = SAS_INTERRUPTED; 2513 break; 2514 case IO_XFER_ERROR_PHY_NOT_READY: 2515 PM8001_IO_DBG(pm8001_ha, 2516 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2517 ts->resp = SAS_TASK_COMPLETE; 2518 ts->stat = SAS_OPEN_REJECT; 2519 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2520 break; 2521 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2522 PM8001_IO_DBG(pm8001_ha, 2523 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT" 2524 "_SUPPORTED\n")); 2525 ts->resp = SAS_TASK_COMPLETE; 2526 ts->stat = SAS_OPEN_REJECT; 2527 ts->open_rej_reason = SAS_OREJ_EPROTO; 2528 break; 2529 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2530 PM8001_IO_DBG(pm8001_ha, 2531 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2532 ts->resp = SAS_TASK_COMPLETE; 2533 ts->stat = SAS_OPEN_REJECT; 2534 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2535 break; 2536 case IO_OPEN_CNX_ERROR_BREAK: 2537 PM8001_IO_DBG(pm8001_ha, 2538 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2539 ts->resp = SAS_TASK_COMPLETE; 2540 ts->stat = SAS_OPEN_REJECT; 2541 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2542 break; 2543 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2544 PM8001_IO_DBG(pm8001_ha, 2545 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2546 ts->resp = SAS_TASK_COMPLETE; 2547 ts->stat = SAS_DEV_NO_RESPONSE; 2548 if (!t->uldd_task) { 2549 pm8001_handle_event(pm8001_ha, 2550 pm8001_dev, 2551 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2552 ts->resp = SAS_TASK_UNDELIVERED; 2553 ts->stat = SAS_QUEUE_FULL; 2554 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2555 return; 2556 } 2557 break; 2558 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2559 PM8001_IO_DBG(pm8001_ha, 2560 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2561 ts->resp = SAS_TASK_UNDELIVERED; 2562 ts->stat = SAS_OPEN_REJECT; 2563 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2564 if (!t->uldd_task) { 2565 pm8001_handle_event(pm8001_ha, 2566 pm8001_dev, 2567 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2568 ts->resp = SAS_TASK_UNDELIVERED; 2569 ts->stat = SAS_QUEUE_FULL; 2570 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2571 return; 2572 } 2573 break; 2574 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2575 PM8001_IO_DBG(pm8001_ha, 2576 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 2577 "NOT_SUPPORTED\n")); 2578 ts->resp = SAS_TASK_COMPLETE; 2579 ts->stat = SAS_OPEN_REJECT; 2580 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2581 break; 2582 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 2583 PM8001_IO_DBG(pm8001_ha, 2584 pm8001_printk("IO_OPEN_CNX_ERROR_STP_RESOURCES" 2585 "_BUSY\n")); 2586 ts->resp = SAS_TASK_COMPLETE; 2587 ts->stat = SAS_DEV_NO_RESPONSE; 2588 if (!t->uldd_task) { 2589 pm8001_handle_event(pm8001_ha, 2590 pm8001_dev, 2591 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY); 2592 ts->resp = SAS_TASK_UNDELIVERED; 2593 ts->stat = SAS_QUEUE_FULL; 2594 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2595 return; 2596 } 2597 break; 2598 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2599 PM8001_IO_DBG(pm8001_ha, 2600 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2601 ts->resp = SAS_TASK_COMPLETE; 2602 ts->stat = SAS_OPEN_REJECT; 2603 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2604 break; 2605 case IO_XFER_ERROR_NAK_RECEIVED: 2606 PM8001_IO_DBG(pm8001_ha, 2607 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 2608 ts->resp = SAS_TASK_COMPLETE; 2609 ts->stat = SAS_NAK_R_ERR; 2610 break; 2611 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2612 PM8001_IO_DBG(pm8001_ha, 2613 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 2614 ts->resp = SAS_TASK_COMPLETE; 2615 ts->stat = SAS_NAK_R_ERR; 2616 break; 2617 case IO_XFER_ERROR_DMA: 2618 PM8001_IO_DBG(pm8001_ha, 2619 pm8001_printk("IO_XFER_ERROR_DMA\n")); 2620 ts->resp = SAS_TASK_COMPLETE; 2621 ts->stat = SAS_ABORTED_TASK; 2622 break; 2623 case IO_XFER_ERROR_SATA_LINK_TIMEOUT: 2624 PM8001_IO_DBG(pm8001_ha, 2625 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n")); 2626 ts->resp = SAS_TASK_UNDELIVERED; 2627 ts->stat = SAS_DEV_NO_RESPONSE; 2628 break; 2629 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2630 PM8001_IO_DBG(pm8001_ha, 2631 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n")); 2632 ts->resp = SAS_TASK_COMPLETE; 2633 ts->stat = SAS_DATA_UNDERRUN; 2634 break; 2635 case IO_XFER_OPEN_RETRY_TIMEOUT: 2636 PM8001_IO_DBG(pm8001_ha, 2637 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2638 ts->resp = SAS_TASK_COMPLETE; 2639 ts->stat = SAS_OPEN_TO; 2640 break; 2641 case IO_PORT_IN_RESET: 2642 PM8001_IO_DBG(pm8001_ha, 2643 pm8001_printk("IO_PORT_IN_RESET\n")); 2644 ts->resp = SAS_TASK_COMPLETE; 2645 ts->stat = SAS_DEV_NO_RESPONSE; 2646 break; 2647 case IO_DS_NON_OPERATIONAL: 2648 PM8001_IO_DBG(pm8001_ha, 2649 pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 2650 ts->resp = SAS_TASK_COMPLETE; 2651 ts->stat = SAS_DEV_NO_RESPONSE; 2652 if (!t->uldd_task) { 2653 pm8001_handle_event(pm8001_ha, pm8001_dev, 2654 IO_DS_NON_OPERATIONAL); 2655 ts->resp = SAS_TASK_UNDELIVERED; 2656 ts->stat = SAS_QUEUE_FULL; 2657 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2658 return; 2659 } 2660 break; 2661 case IO_DS_IN_RECOVERY: 2662 PM8001_IO_DBG(pm8001_ha, 2663 pm8001_printk(" IO_DS_IN_RECOVERY\n")); 2664 ts->resp = SAS_TASK_COMPLETE; 2665 ts->stat = SAS_DEV_NO_RESPONSE; 2666 break; 2667 case IO_DS_IN_ERROR: 2668 PM8001_IO_DBG(pm8001_ha, 2669 pm8001_printk("IO_DS_IN_ERROR\n")); 2670 ts->resp = SAS_TASK_COMPLETE; 2671 ts->stat = SAS_DEV_NO_RESPONSE; 2672 if (!t->uldd_task) { 2673 pm8001_handle_event(pm8001_ha, pm8001_dev, 2674 IO_DS_IN_ERROR); 2675 ts->resp = SAS_TASK_UNDELIVERED; 2676 ts->stat = SAS_QUEUE_FULL; 2677 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2678 return; 2679 } 2680 break; 2681 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2682 PM8001_IO_DBG(pm8001_ha, 2683 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 2684 ts->resp = SAS_TASK_COMPLETE; 2685 ts->stat = SAS_OPEN_REJECT; 2686 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2687 break; 2688 default: 2689 PM8001_DEVIO_DBG(pm8001_ha, 2690 pm8001_printk("Unknown status 0x%x\n", status)); 2691 /* not allowed case. Therefore, return failed status */ 2692 ts->resp = SAS_TASK_COMPLETE; 2693 ts->stat = SAS_DEV_NO_RESPONSE; 2694 break; 2695 } 2696 spin_lock_irqsave(&t->task_state_lock, flags); 2697 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2698 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2699 t->task_state_flags |= SAS_TASK_STATE_DONE; 2700 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2701 spin_unlock_irqrestore(&t->task_state_lock, flags); 2702 PM8001_FAIL_DBG(pm8001_ha, 2703 pm8001_printk("task 0x%p done with io_status 0x%x" 2704 " resp 0x%x stat 0x%x but aborted by upper layer!\n", 2705 t, status, ts->resp, ts->stat)); 2706 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2707 } else { 2708 spin_unlock_irqrestore(&t->task_state_lock, flags); 2709 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2710 } 2711 } 2712 2713 /*See the comments for mpi_ssp_completion */ 2714 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 2715 { 2716 struct sas_task *t; 2717 struct task_status_struct *ts; 2718 struct pm8001_ccb_info *ccb; 2719 struct pm8001_device *pm8001_dev; 2720 struct sata_event_resp *psataPayload = 2721 (struct sata_event_resp *)(piomb + 4); 2722 u32 event = le32_to_cpu(psataPayload->event); 2723 u32 tag = le32_to_cpu(psataPayload->tag); 2724 u32 port_id = le32_to_cpu(psataPayload->port_id); 2725 u32 dev_id = le32_to_cpu(psataPayload->device_id); 2726 unsigned long flags; 2727 2728 ccb = &pm8001_ha->ccb_info[tag]; 2729 2730 if (ccb) { 2731 t = ccb->task; 2732 pm8001_dev = ccb->device; 2733 } else { 2734 PM8001_FAIL_DBG(pm8001_ha, 2735 pm8001_printk("No CCB !!!. returning\n")); 2736 } 2737 if (event) 2738 PM8001_FAIL_DBG(pm8001_ha, 2739 pm8001_printk("SATA EVENT 0x%x\n", event)); 2740 2741 /* Check if this is NCQ error */ 2742 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) { 2743 /* find device using device id */ 2744 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id); 2745 /* send read log extension */ 2746 if (pm8001_dev) 2747 pm8001_send_read_log(pm8001_ha, pm8001_dev); 2748 return; 2749 } 2750 2751 ccb = &pm8001_ha->ccb_info[tag]; 2752 t = ccb->task; 2753 pm8001_dev = ccb->device; 2754 if (event) 2755 PM8001_FAIL_DBG(pm8001_ha, 2756 pm8001_printk("sata IO status 0x%x\n", event)); 2757 if (unlikely(!t || !t->lldd_task || !t->dev)) 2758 return; 2759 ts = &t->task_status; 2760 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk( 2761 "port_id:0x%x, device_id:0x%x, tag:0x%x, event:0x%x\n", 2762 port_id, dev_id, tag, event)); 2763 switch (event) { 2764 case IO_OVERFLOW: 2765 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n")); 2766 ts->resp = SAS_TASK_COMPLETE; 2767 ts->stat = SAS_DATA_OVERRUN; 2768 ts->residual = 0; 2769 if (pm8001_dev) 2770 pm8001_dev->running_req--; 2771 break; 2772 case IO_XFER_ERROR_BREAK: 2773 PM8001_IO_DBG(pm8001_ha, 2774 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2775 ts->resp = SAS_TASK_COMPLETE; 2776 ts->stat = SAS_INTERRUPTED; 2777 break; 2778 case IO_XFER_ERROR_PHY_NOT_READY: 2779 PM8001_IO_DBG(pm8001_ha, 2780 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2781 ts->resp = SAS_TASK_COMPLETE; 2782 ts->stat = SAS_OPEN_REJECT; 2783 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2784 break; 2785 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2786 PM8001_IO_DBG(pm8001_ha, 2787 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT" 2788 "_SUPPORTED\n")); 2789 ts->resp = SAS_TASK_COMPLETE; 2790 ts->stat = SAS_OPEN_REJECT; 2791 ts->open_rej_reason = SAS_OREJ_EPROTO; 2792 break; 2793 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2794 PM8001_IO_DBG(pm8001_ha, 2795 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2796 ts->resp = SAS_TASK_COMPLETE; 2797 ts->stat = SAS_OPEN_REJECT; 2798 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2799 break; 2800 case IO_OPEN_CNX_ERROR_BREAK: 2801 PM8001_IO_DBG(pm8001_ha, 2802 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2803 ts->resp = SAS_TASK_COMPLETE; 2804 ts->stat = SAS_OPEN_REJECT; 2805 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2806 break; 2807 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2808 PM8001_IO_DBG(pm8001_ha, 2809 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2810 ts->resp = SAS_TASK_UNDELIVERED; 2811 ts->stat = SAS_DEV_NO_RESPONSE; 2812 if (!t->uldd_task) { 2813 pm8001_handle_event(pm8001_ha, 2814 pm8001_dev, 2815 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2816 ts->resp = SAS_TASK_COMPLETE; 2817 ts->stat = SAS_QUEUE_FULL; 2818 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2819 return; 2820 } 2821 break; 2822 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2823 PM8001_IO_DBG(pm8001_ha, 2824 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2825 ts->resp = SAS_TASK_UNDELIVERED; 2826 ts->stat = SAS_OPEN_REJECT; 2827 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2828 break; 2829 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2830 PM8001_IO_DBG(pm8001_ha, 2831 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 2832 "NOT_SUPPORTED\n")); 2833 ts->resp = SAS_TASK_COMPLETE; 2834 ts->stat = SAS_OPEN_REJECT; 2835 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2836 break; 2837 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2838 PM8001_IO_DBG(pm8001_ha, 2839 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2840 ts->resp = SAS_TASK_COMPLETE; 2841 ts->stat = SAS_OPEN_REJECT; 2842 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2843 break; 2844 case IO_XFER_ERROR_NAK_RECEIVED: 2845 PM8001_IO_DBG(pm8001_ha, 2846 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 2847 ts->resp = SAS_TASK_COMPLETE; 2848 ts->stat = SAS_NAK_R_ERR; 2849 break; 2850 case IO_XFER_ERROR_PEER_ABORTED: 2851 PM8001_IO_DBG(pm8001_ha, 2852 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n")); 2853 ts->resp = SAS_TASK_COMPLETE; 2854 ts->stat = SAS_NAK_R_ERR; 2855 break; 2856 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2857 PM8001_IO_DBG(pm8001_ha, 2858 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n")); 2859 ts->resp = SAS_TASK_COMPLETE; 2860 ts->stat = SAS_DATA_UNDERRUN; 2861 break; 2862 case IO_XFER_OPEN_RETRY_TIMEOUT: 2863 PM8001_IO_DBG(pm8001_ha, 2864 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2865 ts->resp = SAS_TASK_COMPLETE; 2866 ts->stat = SAS_OPEN_TO; 2867 break; 2868 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2869 PM8001_IO_DBG(pm8001_ha, 2870 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n")); 2871 ts->resp = SAS_TASK_COMPLETE; 2872 ts->stat = SAS_OPEN_TO; 2873 break; 2874 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2875 PM8001_IO_DBG(pm8001_ha, 2876 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n")); 2877 ts->resp = SAS_TASK_COMPLETE; 2878 ts->stat = SAS_OPEN_TO; 2879 break; 2880 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2881 PM8001_IO_DBG(pm8001_ha, 2882 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n")); 2883 ts->resp = SAS_TASK_COMPLETE; 2884 ts->stat = SAS_OPEN_TO; 2885 break; 2886 case IO_XFER_ERROR_OFFSET_MISMATCH: 2887 PM8001_IO_DBG(pm8001_ha, 2888 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 2889 ts->resp = SAS_TASK_COMPLETE; 2890 ts->stat = SAS_OPEN_TO; 2891 break; 2892 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2893 PM8001_IO_DBG(pm8001_ha, 2894 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n")); 2895 ts->resp = SAS_TASK_COMPLETE; 2896 ts->stat = SAS_OPEN_TO; 2897 break; 2898 case IO_XFER_CMD_FRAME_ISSUED: 2899 PM8001_IO_DBG(pm8001_ha, 2900 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n")); 2901 break; 2902 case IO_XFER_PIO_SETUP_ERROR: 2903 PM8001_IO_DBG(pm8001_ha, 2904 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n")); 2905 ts->resp = SAS_TASK_COMPLETE; 2906 ts->stat = SAS_OPEN_TO; 2907 break; 2908 default: 2909 PM8001_DEVIO_DBG(pm8001_ha, 2910 pm8001_printk("Unknown status 0x%x\n", event)); 2911 /* not allowed case. Therefore, return failed status */ 2912 ts->resp = SAS_TASK_COMPLETE; 2913 ts->stat = SAS_OPEN_TO; 2914 break; 2915 } 2916 spin_lock_irqsave(&t->task_state_lock, flags); 2917 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2918 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2919 t->task_state_flags |= SAS_TASK_STATE_DONE; 2920 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2921 spin_unlock_irqrestore(&t->task_state_lock, flags); 2922 PM8001_FAIL_DBG(pm8001_ha, 2923 pm8001_printk("task 0x%p done with io_status 0x%x" 2924 " resp 0x%x stat 0x%x but aborted by upper layer!\n", 2925 t, event, ts->resp, ts->stat)); 2926 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2927 } else { 2928 spin_unlock_irqrestore(&t->task_state_lock, flags); 2929 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2930 } 2931 } 2932 2933 /*See the comments for mpi_ssp_completion */ 2934 static void 2935 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2936 { 2937 struct sas_task *t; 2938 struct pm8001_ccb_info *ccb; 2939 unsigned long flags; 2940 u32 status; 2941 u32 tag; 2942 struct smp_completion_resp *psmpPayload; 2943 struct task_status_struct *ts; 2944 struct pm8001_device *pm8001_dev; 2945 2946 psmpPayload = (struct smp_completion_resp *)(piomb + 4); 2947 status = le32_to_cpu(psmpPayload->status); 2948 tag = le32_to_cpu(psmpPayload->tag); 2949 2950 ccb = &pm8001_ha->ccb_info[tag]; 2951 t = ccb->task; 2952 ts = &t->task_status; 2953 pm8001_dev = ccb->device; 2954 if (status) { 2955 PM8001_FAIL_DBG(pm8001_ha, 2956 pm8001_printk("smp IO status 0x%x\n", status)); 2957 PM8001_IOERR_DBG(pm8001_ha, 2958 pm8001_printk("status:0x%x, tag:0x%x, task:0x%p\n", 2959 status, tag, t)); 2960 } 2961 if (unlikely(!t || !t->lldd_task || !t->dev)) 2962 return; 2963 2964 switch (status) { 2965 case IO_SUCCESS: 2966 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); 2967 ts->resp = SAS_TASK_COMPLETE; 2968 ts->stat = SAM_STAT_GOOD; 2969 if (pm8001_dev) 2970 pm8001_dev->running_req--; 2971 break; 2972 case IO_ABORTED: 2973 PM8001_IO_DBG(pm8001_ha, 2974 pm8001_printk("IO_ABORTED IOMB\n")); 2975 ts->resp = SAS_TASK_COMPLETE; 2976 ts->stat = SAS_ABORTED_TASK; 2977 if (pm8001_dev) 2978 pm8001_dev->running_req--; 2979 break; 2980 case IO_OVERFLOW: 2981 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n")); 2982 ts->resp = SAS_TASK_COMPLETE; 2983 ts->stat = SAS_DATA_OVERRUN; 2984 ts->residual = 0; 2985 if (pm8001_dev) 2986 pm8001_dev->running_req--; 2987 break; 2988 case IO_NO_DEVICE: 2989 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n")); 2990 ts->resp = SAS_TASK_COMPLETE; 2991 ts->stat = SAS_PHY_DOWN; 2992 break; 2993 case IO_ERROR_HW_TIMEOUT: 2994 PM8001_IO_DBG(pm8001_ha, 2995 pm8001_printk("IO_ERROR_HW_TIMEOUT\n")); 2996 ts->resp = SAS_TASK_COMPLETE; 2997 ts->stat = SAM_STAT_BUSY; 2998 break; 2999 case IO_XFER_ERROR_BREAK: 3000 PM8001_IO_DBG(pm8001_ha, 3001 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 3002 ts->resp = SAS_TASK_COMPLETE; 3003 ts->stat = SAM_STAT_BUSY; 3004 break; 3005 case IO_XFER_ERROR_PHY_NOT_READY: 3006 PM8001_IO_DBG(pm8001_ha, 3007 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 3008 ts->resp = SAS_TASK_COMPLETE; 3009 ts->stat = SAM_STAT_BUSY; 3010 break; 3011 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 3012 PM8001_IO_DBG(pm8001_ha, 3013 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 3014 ts->resp = SAS_TASK_COMPLETE; 3015 ts->stat = SAS_OPEN_REJECT; 3016 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 3017 break; 3018 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 3019 PM8001_IO_DBG(pm8001_ha, 3020 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 3021 ts->resp = SAS_TASK_COMPLETE; 3022 ts->stat = SAS_OPEN_REJECT; 3023 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 3024 break; 3025 case IO_OPEN_CNX_ERROR_BREAK: 3026 PM8001_IO_DBG(pm8001_ha, 3027 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 3028 ts->resp = SAS_TASK_COMPLETE; 3029 ts->stat = SAS_OPEN_REJECT; 3030 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 3031 break; 3032 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 3033 PM8001_IO_DBG(pm8001_ha, 3034 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 3035 ts->resp = SAS_TASK_COMPLETE; 3036 ts->stat = SAS_OPEN_REJECT; 3037 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 3038 pm8001_handle_event(pm8001_ha, 3039 pm8001_dev, 3040 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 3041 break; 3042 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 3043 PM8001_IO_DBG(pm8001_ha, 3044 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 3045 ts->resp = SAS_TASK_COMPLETE; 3046 ts->stat = SAS_OPEN_REJECT; 3047 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 3048 break; 3049 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 3050 PM8001_IO_DBG(pm8001_ha, 3051 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 3052 "NOT_SUPPORTED\n")); 3053 ts->resp = SAS_TASK_COMPLETE; 3054 ts->stat = SAS_OPEN_REJECT; 3055 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 3056 break; 3057 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 3058 PM8001_IO_DBG(pm8001_ha, 3059 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 3060 ts->resp = SAS_TASK_COMPLETE; 3061 ts->stat = SAS_OPEN_REJECT; 3062 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 3063 break; 3064 case IO_XFER_ERROR_RX_FRAME: 3065 PM8001_IO_DBG(pm8001_ha, 3066 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n")); 3067 ts->resp = SAS_TASK_COMPLETE; 3068 ts->stat = SAS_DEV_NO_RESPONSE; 3069 break; 3070 case IO_XFER_OPEN_RETRY_TIMEOUT: 3071 PM8001_IO_DBG(pm8001_ha, 3072 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 3073 ts->resp = SAS_TASK_COMPLETE; 3074 ts->stat = SAS_OPEN_REJECT; 3075 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3076 break; 3077 case IO_ERROR_INTERNAL_SMP_RESOURCE: 3078 PM8001_IO_DBG(pm8001_ha, 3079 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n")); 3080 ts->resp = SAS_TASK_COMPLETE; 3081 ts->stat = SAS_QUEUE_FULL; 3082 break; 3083 case IO_PORT_IN_RESET: 3084 PM8001_IO_DBG(pm8001_ha, 3085 pm8001_printk("IO_PORT_IN_RESET\n")); 3086 ts->resp = SAS_TASK_COMPLETE; 3087 ts->stat = SAS_OPEN_REJECT; 3088 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3089 break; 3090 case IO_DS_NON_OPERATIONAL: 3091 PM8001_IO_DBG(pm8001_ha, 3092 pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 3093 ts->resp = SAS_TASK_COMPLETE; 3094 ts->stat = SAS_DEV_NO_RESPONSE; 3095 break; 3096 case IO_DS_IN_RECOVERY: 3097 PM8001_IO_DBG(pm8001_ha, 3098 pm8001_printk("IO_DS_IN_RECOVERY\n")); 3099 ts->resp = SAS_TASK_COMPLETE; 3100 ts->stat = SAS_OPEN_REJECT; 3101 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3102 break; 3103 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 3104 PM8001_IO_DBG(pm8001_ha, 3105 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 3106 ts->resp = SAS_TASK_COMPLETE; 3107 ts->stat = SAS_OPEN_REJECT; 3108 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3109 break; 3110 default: 3111 PM8001_DEVIO_DBG(pm8001_ha, 3112 pm8001_printk("Unknown status 0x%x\n", status)); 3113 ts->resp = SAS_TASK_COMPLETE; 3114 ts->stat = SAS_DEV_NO_RESPONSE; 3115 /* not allowed case. Therefore, return failed status */ 3116 break; 3117 } 3118 spin_lock_irqsave(&t->task_state_lock, flags); 3119 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 3120 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 3121 t->task_state_flags |= SAS_TASK_STATE_DONE; 3122 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 3123 spin_unlock_irqrestore(&t->task_state_lock, flags); 3124 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with" 3125 " io_status 0x%x resp 0x%x " 3126 "stat 0x%x but aborted by upper layer!\n", 3127 t, status, ts->resp, ts->stat)); 3128 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 3129 } else { 3130 spin_unlock_irqrestore(&t->task_state_lock, flags); 3131 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 3132 mb();/* in order to force CPU ordering */ 3133 t->task_done(t); 3134 } 3135 } 3136 3137 void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha, 3138 void *piomb) 3139 { 3140 struct set_dev_state_resp *pPayload = 3141 (struct set_dev_state_resp *)(piomb + 4); 3142 u32 tag = le32_to_cpu(pPayload->tag); 3143 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 3144 struct pm8001_device *pm8001_dev = ccb->device; 3145 u32 status = le32_to_cpu(pPayload->status); 3146 u32 device_id = le32_to_cpu(pPayload->device_id); 3147 u8 pds = le32_to_cpu(pPayload->pds_nds) & PDS_BITS; 3148 u8 nds = le32_to_cpu(pPayload->pds_nds) & NDS_BITS; 3149 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set device id = 0x%x state " 3150 "from 0x%x to 0x%x status = 0x%x!\n", 3151 device_id, pds, nds, status)); 3152 complete(pm8001_dev->setds_completion); 3153 ccb->task = NULL; 3154 ccb->ccb_tag = 0xFFFFFFFF; 3155 pm8001_tag_free(pm8001_ha, tag); 3156 } 3157 3158 void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3159 { 3160 struct get_nvm_data_resp *pPayload = 3161 (struct get_nvm_data_resp *)(piomb + 4); 3162 u32 tag = le32_to_cpu(pPayload->tag); 3163 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 3164 u32 dlen_status = le32_to_cpu(pPayload->dlen_status); 3165 complete(pm8001_ha->nvmd_completion); 3166 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set nvm data complete!\n")); 3167 if ((dlen_status & NVMD_STAT) != 0) { 3168 PM8001_FAIL_DBG(pm8001_ha, 3169 pm8001_printk("Set nvm data error!\n")); 3170 return; 3171 } 3172 ccb->task = NULL; 3173 ccb->ccb_tag = 0xFFFFFFFF; 3174 pm8001_tag_free(pm8001_ha, tag); 3175 } 3176 3177 void 3178 pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3179 { 3180 struct fw_control_ex *fw_control_context; 3181 struct get_nvm_data_resp *pPayload = 3182 (struct get_nvm_data_resp *)(piomb + 4); 3183 u32 tag = le32_to_cpu(pPayload->tag); 3184 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 3185 u32 dlen_status = le32_to_cpu(pPayload->dlen_status); 3186 u32 ir_tds_bn_dps_das_nvm = 3187 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm); 3188 void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr; 3189 fw_control_context = ccb->fw_control_context; 3190 3191 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Get nvm data complete!\n")); 3192 if ((dlen_status & NVMD_STAT) != 0) { 3193 PM8001_FAIL_DBG(pm8001_ha, 3194 pm8001_printk("Get nvm data error!\n")); 3195 complete(pm8001_ha->nvmd_completion); 3196 return; 3197 } 3198 3199 if (ir_tds_bn_dps_das_nvm & IPMode) { 3200 /* indirect mode - IR bit set */ 3201 PM8001_MSG_DBG(pm8001_ha, 3202 pm8001_printk("Get NVMD success, IR=1\n")); 3203 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) { 3204 if (ir_tds_bn_dps_das_nvm == 0x80a80200) { 3205 memcpy(pm8001_ha->sas_addr, 3206 ((u8 *)virt_addr + 4), 3207 SAS_ADDR_SIZE); 3208 PM8001_MSG_DBG(pm8001_ha, 3209 pm8001_printk("Get SAS address" 3210 " from VPD successfully!\n")); 3211 } 3212 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM) 3213 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) || 3214 ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) { 3215 ; 3216 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP) 3217 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) { 3218 ; 3219 } else { 3220 /* Should not be happened*/ 3221 PM8001_MSG_DBG(pm8001_ha, 3222 pm8001_printk("(IR=1)Wrong Device type 0x%x\n", 3223 ir_tds_bn_dps_das_nvm)); 3224 } 3225 } else /* direct mode */{ 3226 PM8001_MSG_DBG(pm8001_ha, 3227 pm8001_printk("Get NVMD success, IR=0, dataLen=%d\n", 3228 (dlen_status & NVMD_LEN) >> 24)); 3229 } 3230 /* Though fw_control_context is freed below, usrAddr still needs 3231 * to be updated as this holds the response to the request function 3232 */ 3233 memcpy(fw_control_context->usrAddr, 3234 pm8001_ha->memoryMap.region[NVMD].virt_ptr, 3235 fw_control_context->len); 3236 kfree(ccb->fw_control_context); 3237 ccb->task = NULL; 3238 ccb->ccb_tag = 0xFFFFFFFF; 3239 pm8001_tag_free(pm8001_ha, tag); 3240 complete(pm8001_ha->nvmd_completion); 3241 } 3242 3243 int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb) 3244 { 3245 u32 tag; 3246 struct local_phy_ctl_resp *pPayload = 3247 (struct local_phy_ctl_resp *)(piomb + 4); 3248 u32 status = le32_to_cpu(pPayload->status); 3249 u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS; 3250 u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS; 3251 tag = le32_to_cpu(pPayload->tag); 3252 if (status != 0) { 3253 PM8001_MSG_DBG(pm8001_ha, 3254 pm8001_printk("%x phy execute %x phy op failed!\n", 3255 phy_id, phy_op)); 3256 } else { 3257 PM8001_MSG_DBG(pm8001_ha, 3258 pm8001_printk("%x phy execute %x phy op success!\n", 3259 phy_id, phy_op)); 3260 pm8001_ha->phy[phy_id].reset_success = true; 3261 } 3262 if (pm8001_ha->phy[phy_id].enable_completion) { 3263 complete(pm8001_ha->phy[phy_id].enable_completion); 3264 pm8001_ha->phy[phy_id].enable_completion = NULL; 3265 } 3266 pm8001_tag_free(pm8001_ha, tag); 3267 return 0; 3268 } 3269 3270 /** 3271 * pm8001_bytes_dmaed - one of the interface function communication with libsas 3272 * @pm8001_ha: our hba card information 3273 * @i: which phy that received the event. 3274 * 3275 * when HBA driver received the identify done event or initiate FIS received 3276 * event(for SATA), it will invoke this function to notify the sas layer that 3277 * the sas toplogy has formed, please discover the the whole sas domain, 3278 * while receive a broadcast(change) primitive just tell the sas 3279 * layer to discover the changed domain rather than the whole domain. 3280 */ 3281 void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i) 3282 { 3283 struct pm8001_phy *phy = &pm8001_ha->phy[i]; 3284 struct asd_sas_phy *sas_phy = &phy->sas_phy; 3285 if (!phy->phy_attached) 3286 return; 3287 3288 if (sas_phy->phy) { 3289 struct sas_phy *sphy = sas_phy->phy; 3290 sphy->negotiated_linkrate = sas_phy->linkrate; 3291 sphy->minimum_linkrate = phy->minimum_linkrate; 3292 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS; 3293 sphy->maximum_linkrate = phy->maximum_linkrate; 3294 sphy->maximum_linkrate_hw = phy->maximum_linkrate; 3295 } 3296 3297 if (phy->phy_type & PORT_TYPE_SAS) { 3298 struct sas_identify_frame *id; 3299 id = (struct sas_identify_frame *)phy->frame_rcvd; 3300 id->dev_type = phy->identify.device_type; 3301 id->initiator_bits = SAS_PROTOCOL_ALL; 3302 id->target_bits = phy->identify.target_port_protocols; 3303 } else if (phy->phy_type & PORT_TYPE_SATA) { 3304 /*Nothing*/ 3305 } 3306 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("phy %d byte dmaded.\n", i)); 3307 3308 sas_phy->frame_rcvd_size = phy->frame_rcvd_size; 3309 pm8001_ha->sas->notify_port_event(sas_phy, PORTE_BYTES_DMAED); 3310 } 3311 3312 /* Get the link rate speed */ 3313 void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate) 3314 { 3315 struct sas_phy *sas_phy = phy->sas_phy.phy; 3316 3317 switch (link_rate) { 3318 case PHY_SPEED_120: 3319 phy->sas_phy.linkrate = SAS_LINK_RATE_12_0_GBPS; 3320 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_12_0_GBPS; 3321 break; 3322 case PHY_SPEED_60: 3323 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS; 3324 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS; 3325 break; 3326 case PHY_SPEED_30: 3327 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS; 3328 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS; 3329 break; 3330 case PHY_SPEED_15: 3331 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS; 3332 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS; 3333 break; 3334 } 3335 sas_phy->negotiated_linkrate = phy->sas_phy.linkrate; 3336 sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS; 3337 sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS; 3338 sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS; 3339 sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS; 3340 } 3341 3342 /** 3343 * asd_get_attached_sas_addr -- extract/generate attached SAS address 3344 * @phy: pointer to asd_phy 3345 * @sas_addr: pointer to buffer where the SAS address is to be written 3346 * 3347 * This function extracts the SAS address from an IDENTIFY frame 3348 * received. If OOB is SATA, then a SAS address is generated from the 3349 * HA tables. 3350 * 3351 * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame 3352 * buffer. 3353 */ 3354 void pm8001_get_attached_sas_addr(struct pm8001_phy *phy, 3355 u8 *sas_addr) 3356 { 3357 if (phy->sas_phy.frame_rcvd[0] == 0x34 3358 && phy->sas_phy.oob_mode == SATA_OOB_MODE) { 3359 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha; 3360 /* FIS device-to-host */ 3361 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr); 3362 addr += phy->sas_phy.id; 3363 *(__be64 *)sas_addr = cpu_to_be64(addr); 3364 } else { 3365 struct sas_identify_frame *idframe = 3366 (void *) phy->sas_phy.frame_rcvd; 3367 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE); 3368 } 3369 } 3370 3371 /** 3372 * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW. 3373 * @pm8001_ha: our hba card information 3374 * @Qnum: the outbound queue message number. 3375 * @SEA: source of event to ack 3376 * @port_id: port id. 3377 * @phyId: phy id. 3378 * @param0: parameter 0. 3379 * @param1: parameter 1. 3380 */ 3381 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha, 3382 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1) 3383 { 3384 struct hw_event_ack_req payload; 3385 u32 opc = OPC_INB_SAS_HW_EVENT_ACK; 3386 3387 struct inbound_queue_table *circularQ; 3388 3389 memset((u8 *)&payload, 0, sizeof(payload)); 3390 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum]; 3391 payload.tag = cpu_to_le32(1); 3392 payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) | 3393 ((phyId & 0x0F) << 4) | (port_id & 0x0F)); 3394 payload.param0 = cpu_to_le32(param0); 3395 payload.param1 = cpu_to_le32(param1); 3396 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 3397 sizeof(payload), 0); 3398 } 3399 3400 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 3401 u32 phyId, u32 phy_op); 3402 3403 /** 3404 * hw_event_sas_phy_up -FW tells me a SAS phy up event. 3405 * @pm8001_ha: our hba card information 3406 * @piomb: IO message buffer 3407 */ 3408 static void 3409 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3410 { 3411 struct hw_event_resp *pPayload = 3412 (struct hw_event_resp *)(piomb + 4); 3413 u32 lr_evt_status_phyid_portid = 3414 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3415 u8 link_rate = 3416 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28); 3417 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3418 u8 phy_id = 3419 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3420 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate); 3421 u8 portstate = (u8)(npip_portstate & 0x0000000F); 3422 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3423 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3424 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3425 unsigned long flags; 3426 u8 deviceType = pPayload->sas_identify.dev_type; 3427 port->port_state = portstate; 3428 phy->phy_state = PHY_STATE_LINK_UP_SPC; 3429 PM8001_MSG_DBG(pm8001_ha, 3430 pm8001_printk("HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n", 3431 port_id, phy_id)); 3432 3433 switch (deviceType) { 3434 case SAS_PHY_UNUSED: 3435 PM8001_MSG_DBG(pm8001_ha, 3436 pm8001_printk("device type no device.\n")); 3437 break; 3438 case SAS_END_DEVICE: 3439 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n")); 3440 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id, 3441 PHY_NOTIFY_ENABLE_SPINUP); 3442 port->port_attached = 1; 3443 pm8001_get_lrate_mode(phy, link_rate); 3444 break; 3445 case SAS_EDGE_EXPANDER_DEVICE: 3446 PM8001_MSG_DBG(pm8001_ha, 3447 pm8001_printk("expander device.\n")); 3448 port->port_attached = 1; 3449 pm8001_get_lrate_mode(phy, link_rate); 3450 break; 3451 case SAS_FANOUT_EXPANDER_DEVICE: 3452 PM8001_MSG_DBG(pm8001_ha, 3453 pm8001_printk("fanout expander device.\n")); 3454 port->port_attached = 1; 3455 pm8001_get_lrate_mode(phy, link_rate); 3456 break; 3457 default: 3458 PM8001_DEVIO_DBG(pm8001_ha, 3459 pm8001_printk("unknown device type(%x)\n", deviceType)); 3460 break; 3461 } 3462 phy->phy_type |= PORT_TYPE_SAS; 3463 phy->identify.device_type = deviceType; 3464 phy->phy_attached = 1; 3465 if (phy->identify.device_type == SAS_END_DEVICE) 3466 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP; 3467 else if (phy->identify.device_type != SAS_PHY_UNUSED) 3468 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP; 3469 phy->sas_phy.oob_mode = SAS_OOB_MODE; 3470 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE); 3471 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3472 memcpy(phy->frame_rcvd, &pPayload->sas_identify, 3473 sizeof(struct sas_identify_frame)-4); 3474 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4; 3475 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3476 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3477 if (pm8001_ha->flags == PM8001F_RUN_TIME) 3478 mdelay(200);/*delay a moment to wait disk to spinup*/ 3479 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3480 } 3481 3482 /** 3483 * hw_event_sata_phy_up -FW tells me a SATA phy up event. 3484 * @pm8001_ha: our hba card information 3485 * @piomb: IO message buffer 3486 */ 3487 static void 3488 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3489 { 3490 struct hw_event_resp *pPayload = 3491 (struct hw_event_resp *)(piomb + 4); 3492 u32 lr_evt_status_phyid_portid = 3493 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3494 u8 link_rate = 3495 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28); 3496 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3497 u8 phy_id = 3498 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3499 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate); 3500 u8 portstate = (u8)(npip_portstate & 0x0000000F); 3501 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3502 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3503 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3504 unsigned long flags; 3505 PM8001_DEVIO_DBG(pm8001_ha, 3506 pm8001_printk("HW_EVENT_SATA_PHY_UP port id = %d," 3507 " phy id = %d\n", port_id, phy_id)); 3508 port->port_state = portstate; 3509 phy->phy_state = PHY_STATE_LINK_UP_SPC; 3510 port->port_attached = 1; 3511 pm8001_get_lrate_mode(phy, link_rate); 3512 phy->phy_type |= PORT_TYPE_SATA; 3513 phy->phy_attached = 1; 3514 phy->sas_phy.oob_mode = SATA_OOB_MODE; 3515 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE); 3516 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3517 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4), 3518 sizeof(struct dev_to_host_fis)); 3519 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 3520 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 3521 phy->identify.device_type = SAS_SATA_DEV; 3522 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3523 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3524 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3525 } 3526 3527 /** 3528 * hw_event_phy_down -we should notify the libsas the phy is down. 3529 * @pm8001_ha: our hba card information 3530 * @piomb: IO message buffer 3531 */ 3532 static void 3533 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb) 3534 { 3535 struct hw_event_resp *pPayload = 3536 (struct hw_event_resp *)(piomb + 4); 3537 u32 lr_evt_status_phyid_portid = 3538 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3539 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3540 u8 phy_id = 3541 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3542 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate); 3543 u8 portstate = (u8)(npip_portstate & 0x0000000F); 3544 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3545 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3546 port->port_state = portstate; 3547 phy->phy_type = 0; 3548 phy->identify.device_type = 0; 3549 phy->phy_attached = 0; 3550 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE); 3551 switch (portstate) { 3552 case PORT_VALID: 3553 break; 3554 case PORT_INVALID: 3555 PM8001_MSG_DBG(pm8001_ha, 3556 pm8001_printk(" PortInvalid portID %d\n", port_id)); 3557 PM8001_MSG_DBG(pm8001_ha, 3558 pm8001_printk(" Last phy Down and port invalid\n")); 3559 port->port_attached = 0; 3560 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3561 port_id, phy_id, 0, 0); 3562 break; 3563 case PORT_IN_RESET: 3564 PM8001_MSG_DBG(pm8001_ha, 3565 pm8001_printk(" Port In Reset portID %d\n", port_id)); 3566 break; 3567 case PORT_NOT_ESTABLISHED: 3568 PM8001_MSG_DBG(pm8001_ha, 3569 pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n")); 3570 port->port_attached = 0; 3571 break; 3572 case PORT_LOSTCOMM: 3573 PM8001_MSG_DBG(pm8001_ha, 3574 pm8001_printk(" phy Down and PORT_LOSTCOMM\n")); 3575 PM8001_MSG_DBG(pm8001_ha, 3576 pm8001_printk(" Last phy Down and port invalid\n")); 3577 port->port_attached = 0; 3578 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3579 port_id, phy_id, 0, 0); 3580 break; 3581 default: 3582 port->port_attached = 0; 3583 PM8001_DEVIO_DBG(pm8001_ha, 3584 pm8001_printk(" phy Down and(default) = %x\n", 3585 portstate)); 3586 break; 3587 3588 } 3589 } 3590 3591 /** 3592 * pm8001_mpi_reg_resp -process register device ID response. 3593 * @pm8001_ha: our hba card information 3594 * @piomb: IO message buffer 3595 * 3596 * when sas layer find a device it will notify LLDD, then the driver register 3597 * the domain device to FW, this event is the return device ID which the FW 3598 * has assigned, from now,inter-communication with FW is no longer using the 3599 * SAS address, use device ID which FW assigned. 3600 */ 3601 int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3602 { 3603 u32 status; 3604 u32 device_id; 3605 u32 htag; 3606 struct pm8001_ccb_info *ccb; 3607 struct pm8001_device *pm8001_dev; 3608 struct dev_reg_resp *registerRespPayload = 3609 (struct dev_reg_resp *)(piomb + 4); 3610 3611 htag = le32_to_cpu(registerRespPayload->tag); 3612 ccb = &pm8001_ha->ccb_info[htag]; 3613 pm8001_dev = ccb->device; 3614 status = le32_to_cpu(registerRespPayload->status); 3615 device_id = le32_to_cpu(registerRespPayload->device_id); 3616 PM8001_MSG_DBG(pm8001_ha, 3617 pm8001_printk(" register device is status = %d\n", status)); 3618 switch (status) { 3619 case DEVREG_SUCCESS: 3620 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("DEVREG_SUCCESS\n")); 3621 pm8001_dev->device_id = device_id; 3622 break; 3623 case DEVREG_FAILURE_OUT_OF_RESOURCE: 3624 PM8001_MSG_DBG(pm8001_ha, 3625 pm8001_printk("DEVREG_FAILURE_OUT_OF_RESOURCE\n")); 3626 break; 3627 case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED: 3628 PM8001_MSG_DBG(pm8001_ha, 3629 pm8001_printk("DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n")); 3630 break; 3631 case DEVREG_FAILURE_INVALID_PHY_ID: 3632 PM8001_MSG_DBG(pm8001_ha, 3633 pm8001_printk("DEVREG_FAILURE_INVALID_PHY_ID\n")); 3634 break; 3635 case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED: 3636 PM8001_MSG_DBG(pm8001_ha, 3637 pm8001_printk("DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n")); 3638 break; 3639 case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE: 3640 PM8001_MSG_DBG(pm8001_ha, 3641 pm8001_printk("DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n")); 3642 break; 3643 case DEVREG_FAILURE_PORT_NOT_VALID_STATE: 3644 PM8001_MSG_DBG(pm8001_ha, 3645 pm8001_printk("DEVREG_FAILURE_PORT_NOT_VALID_STATE\n")); 3646 break; 3647 case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID: 3648 PM8001_MSG_DBG(pm8001_ha, 3649 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n")); 3650 break; 3651 default: 3652 PM8001_MSG_DBG(pm8001_ha, 3653 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_SUPPORTED\n")); 3654 break; 3655 } 3656 complete(pm8001_dev->dcompletion); 3657 ccb->task = NULL; 3658 ccb->ccb_tag = 0xFFFFFFFF; 3659 pm8001_tag_free(pm8001_ha, htag); 3660 return 0; 3661 } 3662 3663 int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3664 { 3665 u32 status; 3666 u32 device_id; 3667 struct dev_reg_resp *registerRespPayload = 3668 (struct dev_reg_resp *)(piomb + 4); 3669 3670 status = le32_to_cpu(registerRespPayload->status); 3671 device_id = le32_to_cpu(registerRespPayload->device_id); 3672 if (status != 0) 3673 PM8001_MSG_DBG(pm8001_ha, 3674 pm8001_printk(" deregister device failed ,status = %x" 3675 ", device_id = %x\n", status, device_id)); 3676 return 0; 3677 } 3678 3679 /** 3680 * fw_flash_update_resp - Response from FW for flash update command. 3681 * @pm8001_ha: our hba card information 3682 * @piomb: IO message buffer 3683 */ 3684 int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha, 3685 void *piomb) 3686 { 3687 u32 status; 3688 struct fw_flash_Update_resp *ppayload = 3689 (struct fw_flash_Update_resp *)(piomb + 4); 3690 u32 tag = le32_to_cpu(ppayload->tag); 3691 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 3692 status = le32_to_cpu(ppayload->status); 3693 switch (status) { 3694 case FLASH_UPDATE_COMPLETE_PENDING_REBOOT: 3695 PM8001_MSG_DBG(pm8001_ha, 3696 pm8001_printk(": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n")); 3697 break; 3698 case FLASH_UPDATE_IN_PROGRESS: 3699 PM8001_MSG_DBG(pm8001_ha, 3700 pm8001_printk(": FLASH_UPDATE_IN_PROGRESS\n")); 3701 break; 3702 case FLASH_UPDATE_HDR_ERR: 3703 PM8001_MSG_DBG(pm8001_ha, 3704 pm8001_printk(": FLASH_UPDATE_HDR_ERR\n")); 3705 break; 3706 case FLASH_UPDATE_OFFSET_ERR: 3707 PM8001_MSG_DBG(pm8001_ha, 3708 pm8001_printk(": FLASH_UPDATE_OFFSET_ERR\n")); 3709 break; 3710 case FLASH_UPDATE_CRC_ERR: 3711 PM8001_MSG_DBG(pm8001_ha, 3712 pm8001_printk(": FLASH_UPDATE_CRC_ERR\n")); 3713 break; 3714 case FLASH_UPDATE_LENGTH_ERR: 3715 PM8001_MSG_DBG(pm8001_ha, 3716 pm8001_printk(": FLASH_UPDATE_LENGTH_ERR\n")); 3717 break; 3718 case FLASH_UPDATE_HW_ERR: 3719 PM8001_MSG_DBG(pm8001_ha, 3720 pm8001_printk(": FLASH_UPDATE_HW_ERR\n")); 3721 break; 3722 case FLASH_UPDATE_DNLD_NOT_SUPPORTED: 3723 PM8001_MSG_DBG(pm8001_ha, 3724 pm8001_printk(": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n")); 3725 break; 3726 case FLASH_UPDATE_DISABLED: 3727 PM8001_MSG_DBG(pm8001_ha, 3728 pm8001_printk(": FLASH_UPDATE_DISABLED\n")); 3729 break; 3730 default: 3731 PM8001_DEVIO_DBG(pm8001_ha, 3732 pm8001_printk("No matched status = %d\n", status)); 3733 break; 3734 } 3735 kfree(ccb->fw_control_context); 3736 ccb->task = NULL; 3737 ccb->ccb_tag = 0xFFFFFFFF; 3738 pm8001_tag_free(pm8001_ha, tag); 3739 complete(pm8001_ha->nvmd_completion); 3740 return 0; 3741 } 3742 3743 int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 3744 { 3745 u32 status; 3746 int i; 3747 struct general_event_resp *pPayload = 3748 (struct general_event_resp *)(piomb + 4); 3749 status = le32_to_cpu(pPayload->status); 3750 PM8001_MSG_DBG(pm8001_ha, 3751 pm8001_printk(" status = 0x%x\n", status)); 3752 for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++) 3753 PM8001_MSG_DBG(pm8001_ha, 3754 pm8001_printk("inb_IOMB_payload[0x%x] 0x%x,\n", i, 3755 pPayload->inb_IOMB_payload[i])); 3756 return 0; 3757 } 3758 3759 int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3760 { 3761 struct sas_task *t; 3762 struct pm8001_ccb_info *ccb; 3763 unsigned long flags; 3764 u32 status ; 3765 u32 tag, scp; 3766 struct task_status_struct *ts; 3767 struct pm8001_device *pm8001_dev; 3768 3769 struct task_abort_resp *pPayload = 3770 (struct task_abort_resp *)(piomb + 4); 3771 3772 status = le32_to_cpu(pPayload->status); 3773 tag = le32_to_cpu(pPayload->tag); 3774 if (!tag) { 3775 PM8001_FAIL_DBG(pm8001_ha, 3776 pm8001_printk(" TAG NULL. RETURNING !!!")); 3777 return -1; 3778 } 3779 3780 scp = le32_to_cpu(pPayload->scp); 3781 ccb = &pm8001_ha->ccb_info[tag]; 3782 t = ccb->task; 3783 pm8001_dev = ccb->device; /* retrieve device */ 3784 3785 if (!t) { 3786 PM8001_FAIL_DBG(pm8001_ha, 3787 pm8001_printk(" TASK NULL. RETURNING !!!")); 3788 return -1; 3789 } 3790 ts = &t->task_status; 3791 if (status != 0) 3792 PM8001_FAIL_DBG(pm8001_ha, 3793 pm8001_printk("task abort failed status 0x%x ," 3794 "tag = 0x%x, scp= 0x%x\n", status, tag, scp)); 3795 switch (status) { 3796 case IO_SUCCESS: 3797 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); 3798 ts->resp = SAS_TASK_COMPLETE; 3799 ts->stat = SAM_STAT_GOOD; 3800 break; 3801 case IO_NOT_VALID: 3802 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_NOT_VALID\n")); 3803 ts->resp = TMF_RESP_FUNC_FAILED; 3804 break; 3805 } 3806 spin_lock_irqsave(&t->task_state_lock, flags); 3807 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 3808 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 3809 t->task_state_flags |= SAS_TASK_STATE_DONE; 3810 spin_unlock_irqrestore(&t->task_state_lock, flags); 3811 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 3812 mb(); 3813 3814 if (pm8001_dev->id & NCQ_ABORT_ALL_FLAG) { 3815 pm8001_tag_free(pm8001_ha, tag); 3816 sas_free_task(t); 3817 /* clear the flag */ 3818 pm8001_dev->id &= 0xBFFFFFFF; 3819 } else 3820 t->task_done(t); 3821 3822 return 0; 3823 } 3824 3825 /** 3826 * mpi_hw_event -The hw event has come. 3827 * @pm8001_ha: our hba card information 3828 * @piomb: IO message buffer 3829 */ 3830 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb) 3831 { 3832 unsigned long flags; 3833 struct hw_event_resp *pPayload = 3834 (struct hw_event_resp *)(piomb + 4); 3835 u32 lr_evt_status_phyid_portid = 3836 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3837 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3838 u8 phy_id = 3839 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3840 u16 eventType = 3841 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8); 3842 u8 status = 3843 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24); 3844 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3845 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3846 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id]; 3847 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk( 3848 "SPC HW event for portid:%d, phyid:%d, event:%x, status:%x\n", 3849 port_id, phy_id, eventType, status)); 3850 switch (eventType) { 3851 case HW_EVENT_PHY_START_STATUS: 3852 PM8001_MSG_DBG(pm8001_ha, 3853 pm8001_printk("HW_EVENT_PHY_START_STATUS" 3854 " status = %x\n", status)); 3855 if (status == 0) { 3856 phy->phy_state = 1; 3857 if (pm8001_ha->flags == PM8001F_RUN_TIME && 3858 phy->enable_completion != NULL) 3859 complete(phy->enable_completion); 3860 } 3861 break; 3862 case HW_EVENT_SAS_PHY_UP: 3863 PM8001_MSG_DBG(pm8001_ha, 3864 pm8001_printk("HW_EVENT_PHY_START_STATUS\n")); 3865 hw_event_sas_phy_up(pm8001_ha, piomb); 3866 break; 3867 case HW_EVENT_SATA_PHY_UP: 3868 PM8001_MSG_DBG(pm8001_ha, 3869 pm8001_printk("HW_EVENT_SATA_PHY_UP\n")); 3870 hw_event_sata_phy_up(pm8001_ha, piomb); 3871 break; 3872 case HW_EVENT_PHY_STOP_STATUS: 3873 PM8001_MSG_DBG(pm8001_ha, 3874 pm8001_printk("HW_EVENT_PHY_STOP_STATUS " 3875 "status = %x\n", status)); 3876 if (status == 0) 3877 phy->phy_state = 0; 3878 break; 3879 case HW_EVENT_SATA_SPINUP_HOLD: 3880 PM8001_MSG_DBG(pm8001_ha, 3881 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n")); 3882 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD); 3883 break; 3884 case HW_EVENT_PHY_DOWN: 3885 PM8001_MSG_DBG(pm8001_ha, 3886 pm8001_printk("HW_EVENT_PHY_DOWN\n")); 3887 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL); 3888 phy->phy_attached = 0; 3889 phy->phy_state = 0; 3890 hw_event_phy_down(pm8001_ha, piomb); 3891 break; 3892 case HW_EVENT_PORT_INVALID: 3893 PM8001_MSG_DBG(pm8001_ha, 3894 pm8001_printk("HW_EVENT_PORT_INVALID\n")); 3895 sas_phy_disconnected(sas_phy); 3896 phy->phy_attached = 0; 3897 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3898 break; 3899 /* the broadcast change primitive received, tell the LIBSAS this event 3900 to revalidate the sas domain*/ 3901 case HW_EVENT_BROADCAST_CHANGE: 3902 PM8001_MSG_DBG(pm8001_ha, 3903 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n")); 3904 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE, 3905 port_id, phy_id, 1, 0); 3906 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3907 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE; 3908 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3909 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3910 break; 3911 case HW_EVENT_PHY_ERROR: 3912 PM8001_MSG_DBG(pm8001_ha, 3913 pm8001_printk("HW_EVENT_PHY_ERROR\n")); 3914 sas_phy_disconnected(&phy->sas_phy); 3915 phy->phy_attached = 0; 3916 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR); 3917 break; 3918 case HW_EVENT_BROADCAST_EXP: 3919 PM8001_MSG_DBG(pm8001_ha, 3920 pm8001_printk("HW_EVENT_BROADCAST_EXP\n")); 3921 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3922 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP; 3923 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3924 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3925 break; 3926 case HW_EVENT_LINK_ERR_INVALID_DWORD: 3927 PM8001_MSG_DBG(pm8001_ha, 3928 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n")); 3929 pm8001_hw_event_ack_req(pm8001_ha, 0, 3930 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0); 3931 sas_phy_disconnected(sas_phy); 3932 phy->phy_attached = 0; 3933 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3934 break; 3935 case HW_EVENT_LINK_ERR_DISPARITY_ERROR: 3936 PM8001_MSG_DBG(pm8001_ha, 3937 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n")); 3938 pm8001_hw_event_ack_req(pm8001_ha, 0, 3939 HW_EVENT_LINK_ERR_DISPARITY_ERROR, 3940 port_id, phy_id, 0, 0); 3941 sas_phy_disconnected(sas_phy); 3942 phy->phy_attached = 0; 3943 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3944 break; 3945 case HW_EVENT_LINK_ERR_CODE_VIOLATION: 3946 PM8001_MSG_DBG(pm8001_ha, 3947 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n")); 3948 pm8001_hw_event_ack_req(pm8001_ha, 0, 3949 HW_EVENT_LINK_ERR_CODE_VIOLATION, 3950 port_id, phy_id, 0, 0); 3951 sas_phy_disconnected(sas_phy); 3952 phy->phy_attached = 0; 3953 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3954 break; 3955 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH: 3956 PM8001_MSG_DBG(pm8001_ha, 3957 pm8001_printk("HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n")); 3958 pm8001_hw_event_ack_req(pm8001_ha, 0, 3959 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH, 3960 port_id, phy_id, 0, 0); 3961 sas_phy_disconnected(sas_phy); 3962 phy->phy_attached = 0; 3963 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3964 break; 3965 case HW_EVENT_MALFUNCTION: 3966 PM8001_MSG_DBG(pm8001_ha, 3967 pm8001_printk("HW_EVENT_MALFUNCTION\n")); 3968 break; 3969 case HW_EVENT_BROADCAST_SES: 3970 PM8001_MSG_DBG(pm8001_ha, 3971 pm8001_printk("HW_EVENT_BROADCAST_SES\n")); 3972 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3973 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES; 3974 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3975 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3976 break; 3977 case HW_EVENT_INBOUND_CRC_ERROR: 3978 PM8001_MSG_DBG(pm8001_ha, 3979 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n")); 3980 pm8001_hw_event_ack_req(pm8001_ha, 0, 3981 HW_EVENT_INBOUND_CRC_ERROR, 3982 port_id, phy_id, 0, 0); 3983 break; 3984 case HW_EVENT_HARD_RESET_RECEIVED: 3985 PM8001_MSG_DBG(pm8001_ha, 3986 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n")); 3987 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET); 3988 break; 3989 case HW_EVENT_ID_FRAME_TIMEOUT: 3990 PM8001_MSG_DBG(pm8001_ha, 3991 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n")); 3992 sas_phy_disconnected(sas_phy); 3993 phy->phy_attached = 0; 3994 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3995 break; 3996 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED: 3997 PM8001_MSG_DBG(pm8001_ha, 3998 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n")); 3999 pm8001_hw_event_ack_req(pm8001_ha, 0, 4000 HW_EVENT_LINK_ERR_PHY_RESET_FAILED, 4001 port_id, phy_id, 0, 0); 4002 sas_phy_disconnected(sas_phy); 4003 phy->phy_attached = 0; 4004 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 4005 break; 4006 case HW_EVENT_PORT_RESET_TIMER_TMO: 4007 PM8001_MSG_DBG(pm8001_ha, 4008 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n")); 4009 sas_phy_disconnected(sas_phy); 4010 phy->phy_attached = 0; 4011 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 4012 break; 4013 case HW_EVENT_PORT_RECOVERY_TIMER_TMO: 4014 PM8001_MSG_DBG(pm8001_ha, 4015 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n")); 4016 sas_phy_disconnected(sas_phy); 4017 phy->phy_attached = 0; 4018 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 4019 break; 4020 case HW_EVENT_PORT_RECOVER: 4021 PM8001_MSG_DBG(pm8001_ha, 4022 pm8001_printk("HW_EVENT_PORT_RECOVER\n")); 4023 break; 4024 case HW_EVENT_PORT_RESET_COMPLETE: 4025 PM8001_MSG_DBG(pm8001_ha, 4026 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n")); 4027 break; 4028 case EVENT_BROADCAST_ASYNCH_EVENT: 4029 PM8001_MSG_DBG(pm8001_ha, 4030 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n")); 4031 break; 4032 default: 4033 PM8001_DEVIO_DBG(pm8001_ha, 4034 pm8001_printk("Unknown event type = %x\n", eventType)); 4035 break; 4036 } 4037 return 0; 4038 } 4039 4040 /** 4041 * process_one_iomb - process one outbound Queue memory block 4042 * @pm8001_ha: our hba card information 4043 * @piomb: IO message buffer 4044 */ 4045 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb) 4046 { 4047 __le32 pHeader = *(__le32 *)piomb; 4048 u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF); 4049 4050 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("process_one_iomb:")); 4051 4052 switch (opc) { 4053 case OPC_OUB_ECHO: 4054 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n")); 4055 break; 4056 case OPC_OUB_HW_EVENT: 4057 PM8001_MSG_DBG(pm8001_ha, 4058 pm8001_printk("OPC_OUB_HW_EVENT\n")); 4059 mpi_hw_event(pm8001_ha, piomb); 4060 break; 4061 case OPC_OUB_SSP_COMP: 4062 PM8001_MSG_DBG(pm8001_ha, 4063 pm8001_printk("OPC_OUB_SSP_COMP\n")); 4064 mpi_ssp_completion(pm8001_ha, piomb); 4065 break; 4066 case OPC_OUB_SMP_COMP: 4067 PM8001_MSG_DBG(pm8001_ha, 4068 pm8001_printk("OPC_OUB_SMP_COMP\n")); 4069 mpi_smp_completion(pm8001_ha, piomb); 4070 break; 4071 case OPC_OUB_LOCAL_PHY_CNTRL: 4072 PM8001_MSG_DBG(pm8001_ha, 4073 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n")); 4074 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb); 4075 break; 4076 case OPC_OUB_DEV_REGIST: 4077 PM8001_MSG_DBG(pm8001_ha, 4078 pm8001_printk("OPC_OUB_DEV_REGIST\n")); 4079 pm8001_mpi_reg_resp(pm8001_ha, piomb); 4080 break; 4081 case OPC_OUB_DEREG_DEV: 4082 PM8001_MSG_DBG(pm8001_ha, 4083 pm8001_printk("unregister the device\n")); 4084 pm8001_mpi_dereg_resp(pm8001_ha, piomb); 4085 break; 4086 case OPC_OUB_GET_DEV_HANDLE: 4087 PM8001_MSG_DBG(pm8001_ha, 4088 pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n")); 4089 break; 4090 case OPC_OUB_SATA_COMP: 4091 PM8001_MSG_DBG(pm8001_ha, 4092 pm8001_printk("OPC_OUB_SATA_COMP\n")); 4093 mpi_sata_completion(pm8001_ha, piomb); 4094 break; 4095 case OPC_OUB_SATA_EVENT: 4096 PM8001_MSG_DBG(pm8001_ha, 4097 pm8001_printk("OPC_OUB_SATA_EVENT\n")); 4098 mpi_sata_event(pm8001_ha, piomb); 4099 break; 4100 case OPC_OUB_SSP_EVENT: 4101 PM8001_MSG_DBG(pm8001_ha, 4102 pm8001_printk("OPC_OUB_SSP_EVENT\n")); 4103 mpi_ssp_event(pm8001_ha, piomb); 4104 break; 4105 case OPC_OUB_DEV_HANDLE_ARRIV: 4106 PM8001_MSG_DBG(pm8001_ha, 4107 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n")); 4108 /*This is for target*/ 4109 break; 4110 case OPC_OUB_SSP_RECV_EVENT: 4111 PM8001_MSG_DBG(pm8001_ha, 4112 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n")); 4113 /*This is for target*/ 4114 break; 4115 case OPC_OUB_DEV_INFO: 4116 PM8001_MSG_DBG(pm8001_ha, 4117 pm8001_printk("OPC_OUB_DEV_INFO\n")); 4118 break; 4119 case OPC_OUB_FW_FLASH_UPDATE: 4120 PM8001_MSG_DBG(pm8001_ha, 4121 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n")); 4122 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb); 4123 break; 4124 case OPC_OUB_GPIO_RESPONSE: 4125 PM8001_MSG_DBG(pm8001_ha, 4126 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n")); 4127 break; 4128 case OPC_OUB_GPIO_EVENT: 4129 PM8001_MSG_DBG(pm8001_ha, 4130 pm8001_printk("OPC_OUB_GPIO_EVENT\n")); 4131 break; 4132 case OPC_OUB_GENERAL_EVENT: 4133 PM8001_MSG_DBG(pm8001_ha, 4134 pm8001_printk("OPC_OUB_GENERAL_EVENT\n")); 4135 pm8001_mpi_general_event(pm8001_ha, piomb); 4136 break; 4137 case OPC_OUB_SSP_ABORT_RSP: 4138 PM8001_MSG_DBG(pm8001_ha, 4139 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n")); 4140 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 4141 break; 4142 case OPC_OUB_SATA_ABORT_RSP: 4143 PM8001_MSG_DBG(pm8001_ha, 4144 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n")); 4145 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 4146 break; 4147 case OPC_OUB_SAS_DIAG_MODE_START_END: 4148 PM8001_MSG_DBG(pm8001_ha, 4149 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n")); 4150 break; 4151 case OPC_OUB_SAS_DIAG_EXECUTE: 4152 PM8001_MSG_DBG(pm8001_ha, 4153 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n")); 4154 break; 4155 case OPC_OUB_GET_TIME_STAMP: 4156 PM8001_MSG_DBG(pm8001_ha, 4157 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n")); 4158 break; 4159 case OPC_OUB_SAS_HW_EVENT_ACK: 4160 PM8001_MSG_DBG(pm8001_ha, 4161 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n")); 4162 break; 4163 case OPC_OUB_PORT_CONTROL: 4164 PM8001_MSG_DBG(pm8001_ha, 4165 pm8001_printk("OPC_OUB_PORT_CONTROL\n")); 4166 break; 4167 case OPC_OUB_SMP_ABORT_RSP: 4168 PM8001_MSG_DBG(pm8001_ha, 4169 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n")); 4170 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 4171 break; 4172 case OPC_OUB_GET_NVMD_DATA: 4173 PM8001_MSG_DBG(pm8001_ha, 4174 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n")); 4175 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb); 4176 break; 4177 case OPC_OUB_SET_NVMD_DATA: 4178 PM8001_MSG_DBG(pm8001_ha, 4179 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n")); 4180 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb); 4181 break; 4182 case OPC_OUB_DEVICE_HANDLE_REMOVAL: 4183 PM8001_MSG_DBG(pm8001_ha, 4184 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n")); 4185 break; 4186 case OPC_OUB_SET_DEVICE_STATE: 4187 PM8001_MSG_DBG(pm8001_ha, 4188 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n")); 4189 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb); 4190 break; 4191 case OPC_OUB_GET_DEVICE_STATE: 4192 PM8001_MSG_DBG(pm8001_ha, 4193 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n")); 4194 break; 4195 case OPC_OUB_SET_DEV_INFO: 4196 PM8001_MSG_DBG(pm8001_ha, 4197 pm8001_printk("OPC_OUB_SET_DEV_INFO\n")); 4198 break; 4199 case OPC_OUB_SAS_RE_INITIALIZE: 4200 PM8001_MSG_DBG(pm8001_ha, 4201 pm8001_printk("OPC_OUB_SAS_RE_INITIALIZE\n")); 4202 break; 4203 default: 4204 PM8001_DEVIO_DBG(pm8001_ha, 4205 pm8001_printk("Unknown outbound Queue IOMB OPC = %x\n", 4206 opc)); 4207 break; 4208 } 4209 } 4210 4211 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec) 4212 { 4213 struct outbound_queue_table *circularQ; 4214 void *pMsg1 = NULL; 4215 u8 bc; 4216 u32 ret = MPI_IO_STATUS_FAIL; 4217 unsigned long flags; 4218 4219 spin_lock_irqsave(&pm8001_ha->lock, flags); 4220 circularQ = &pm8001_ha->outbnd_q_tbl[vec]; 4221 do { 4222 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc); 4223 if (MPI_IO_STATUS_SUCCESS == ret) { 4224 /* process the outbound message */ 4225 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4)); 4226 /* free the message from the outbound circular buffer */ 4227 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1, 4228 circularQ, bc); 4229 } 4230 if (MPI_IO_STATUS_BUSY == ret) { 4231 /* Update the producer index from SPC */ 4232 circularQ->producer_index = 4233 cpu_to_le32(pm8001_read_32(circularQ->pi_virt)); 4234 if (le32_to_cpu(circularQ->producer_index) == 4235 circularQ->consumer_idx) 4236 /* OQ is empty */ 4237 break; 4238 } 4239 } while (1); 4240 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 4241 return ret; 4242 } 4243 4244 /* DMA_... to our direction translation. */ 4245 static const u8 data_dir_flags[] = { 4246 [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */ 4247 [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */ 4248 [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */ 4249 [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */ 4250 }; 4251 void 4252 pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd) 4253 { 4254 int i; 4255 struct scatterlist *sg; 4256 struct pm8001_prd *buf_prd = prd; 4257 4258 for_each_sg(scatter, sg, nr, i) { 4259 buf_prd->addr = cpu_to_le64(sg_dma_address(sg)); 4260 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg)); 4261 buf_prd->im_len.e = 0; 4262 buf_prd++; 4263 } 4264 } 4265 4266 static void build_smp_cmd(u32 deviceID, __le32 hTag, struct smp_req *psmp_cmd) 4267 { 4268 psmp_cmd->tag = hTag; 4269 psmp_cmd->device_id = cpu_to_le32(deviceID); 4270 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1)); 4271 } 4272 4273 /** 4274 * pm8001_chip_smp_req - send a SMP task to FW 4275 * @pm8001_ha: our hba card information. 4276 * @ccb: the ccb information this request used. 4277 */ 4278 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha, 4279 struct pm8001_ccb_info *ccb) 4280 { 4281 int elem, rc; 4282 struct sas_task *task = ccb->task; 4283 struct domain_device *dev = task->dev; 4284 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4285 struct scatterlist *sg_req, *sg_resp; 4286 u32 req_len, resp_len; 4287 struct smp_req smp_cmd; 4288 u32 opc; 4289 struct inbound_queue_table *circularQ; 4290 4291 memset(&smp_cmd, 0, sizeof(smp_cmd)); 4292 /* 4293 * DMA-map SMP request, response buffers 4294 */ 4295 sg_req = &task->smp_task.smp_req; 4296 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE); 4297 if (!elem) 4298 return -ENOMEM; 4299 req_len = sg_dma_len(sg_req); 4300 4301 sg_resp = &task->smp_task.smp_resp; 4302 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE); 4303 if (!elem) { 4304 rc = -ENOMEM; 4305 goto err_out; 4306 } 4307 resp_len = sg_dma_len(sg_resp); 4308 /* must be in dwords */ 4309 if ((req_len & 0x3) || (resp_len & 0x3)) { 4310 rc = -EINVAL; 4311 goto err_out_2; 4312 } 4313 4314 opc = OPC_INB_SMP_REQUEST; 4315 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4316 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag); 4317 smp_cmd.long_smp_req.long_req_addr = 4318 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req)); 4319 smp_cmd.long_smp_req.long_req_size = 4320 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4); 4321 smp_cmd.long_smp_req.long_resp_addr = 4322 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp)); 4323 smp_cmd.long_smp_req.long_resp_size = 4324 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4); 4325 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd); 4326 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, 4327 &smp_cmd, sizeof(smp_cmd), 0); 4328 if (rc) 4329 goto err_out_2; 4330 4331 return 0; 4332 4333 err_out_2: 4334 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1, 4335 DMA_FROM_DEVICE); 4336 err_out: 4337 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1, 4338 DMA_TO_DEVICE); 4339 return rc; 4340 } 4341 4342 /** 4343 * pm8001_chip_ssp_io_req - send a SSP task to FW 4344 * @pm8001_ha: our hba card information. 4345 * @ccb: the ccb information this request used. 4346 */ 4347 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha, 4348 struct pm8001_ccb_info *ccb) 4349 { 4350 struct sas_task *task = ccb->task; 4351 struct domain_device *dev = task->dev; 4352 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4353 struct ssp_ini_io_start_req ssp_cmd; 4354 u32 tag = ccb->ccb_tag; 4355 int ret; 4356 u64 phys_addr; 4357 struct inbound_queue_table *circularQ; 4358 u32 opc = OPC_INB_SSPINIIOSTART; 4359 memset(&ssp_cmd, 0, sizeof(ssp_cmd)); 4360 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8); 4361 ssp_cmd.dir_m_tlr = 4362 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for 4363 SAS 1.1 compatible TLR*/ 4364 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4365 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id); 4366 ssp_cmd.tag = cpu_to_le32(tag); 4367 if (task->ssp_task.enable_first_burst) 4368 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80; 4369 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3); 4370 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7); 4371 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd, 4372 task->ssp_task.cmd->cmd_len); 4373 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4374 4375 /* fill in PRD (scatter/gather) table, if any */ 4376 if (task->num_scatter > 1) { 4377 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd); 4378 phys_addr = ccb->ccb_dma_handle; 4379 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(phys_addr)); 4380 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr)); 4381 ssp_cmd.esgl = cpu_to_le32(1<<31); 4382 } else if (task->num_scatter == 1) { 4383 u64 dma_addr = sg_dma_address(task->scatter); 4384 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr)); 4385 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr)); 4386 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4387 ssp_cmd.esgl = 0; 4388 } else if (task->num_scatter == 0) { 4389 ssp_cmd.addr_low = 0; 4390 ssp_cmd.addr_high = 0; 4391 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4392 ssp_cmd.esgl = 0; 4393 } 4394 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd, 4395 sizeof(ssp_cmd), 0); 4396 return ret; 4397 } 4398 4399 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha, 4400 struct pm8001_ccb_info *ccb) 4401 { 4402 struct sas_task *task = ccb->task; 4403 struct domain_device *dev = task->dev; 4404 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev; 4405 u32 tag = ccb->ccb_tag; 4406 int ret; 4407 struct sata_start_req sata_cmd; 4408 u32 hdr_tag, ncg_tag = 0; 4409 u64 phys_addr; 4410 u32 ATAP = 0x0; 4411 u32 dir; 4412 struct inbound_queue_table *circularQ; 4413 unsigned long flags; 4414 u32 opc = OPC_INB_SATA_HOST_OPSTART; 4415 memset(&sata_cmd, 0, sizeof(sata_cmd)); 4416 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4417 if (task->data_dir == DMA_NONE) { 4418 ATAP = 0x04; /* no data*/ 4419 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n")); 4420 } else if (likely(!task->ata_task.device_control_reg_update)) { 4421 if (task->ata_task.dma_xfer) { 4422 ATAP = 0x06; /* DMA */ 4423 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n")); 4424 } else { 4425 ATAP = 0x05; /* PIO*/ 4426 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n")); 4427 } 4428 if (task->ata_task.use_ncq && 4429 dev->sata_dev.class != ATA_DEV_ATAPI) { 4430 ATAP = 0x07; /* FPDMA */ 4431 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n")); 4432 } 4433 } 4434 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) { 4435 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 4436 ncg_tag = hdr_tag; 4437 } 4438 dir = data_dir_flags[task->data_dir] << 8; 4439 sata_cmd.tag = cpu_to_le32(tag); 4440 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 4441 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4442 sata_cmd.ncqtag_atap_dir_m = 4443 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir); 4444 sata_cmd.sata_fis = task->ata_task.fis; 4445 if (likely(!task->ata_task.device_control_reg_update)) 4446 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */ 4447 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */ 4448 /* fill in PRD (scatter/gather) table, if any */ 4449 if (task->num_scatter > 1) { 4450 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd); 4451 phys_addr = ccb->ccb_dma_handle; 4452 sata_cmd.addr_low = lower_32_bits(phys_addr); 4453 sata_cmd.addr_high = upper_32_bits(phys_addr); 4454 sata_cmd.esgl = cpu_to_le32(1 << 31); 4455 } else if (task->num_scatter == 1) { 4456 u64 dma_addr = sg_dma_address(task->scatter); 4457 sata_cmd.addr_low = lower_32_bits(dma_addr); 4458 sata_cmd.addr_high = upper_32_bits(dma_addr); 4459 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4460 sata_cmd.esgl = 0; 4461 } else if (task->num_scatter == 0) { 4462 sata_cmd.addr_low = 0; 4463 sata_cmd.addr_high = 0; 4464 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4465 sata_cmd.esgl = 0; 4466 } 4467 4468 /* Check for read log for failed drive and return */ 4469 if (sata_cmd.sata_fis.command == 0x2f) { 4470 if (((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) || 4471 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) || 4472 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) { 4473 struct task_status_struct *ts; 4474 4475 pm8001_ha_dev->id &= 0xDFFFFFFF; 4476 ts = &task->task_status; 4477 4478 spin_lock_irqsave(&task->task_state_lock, flags); 4479 ts->resp = SAS_TASK_COMPLETE; 4480 ts->stat = SAM_STAT_GOOD; 4481 task->task_state_flags &= ~SAS_TASK_STATE_PENDING; 4482 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 4483 task->task_state_flags |= SAS_TASK_STATE_DONE; 4484 if (unlikely((task->task_state_flags & 4485 SAS_TASK_STATE_ABORTED))) { 4486 spin_unlock_irqrestore(&task->task_state_lock, 4487 flags); 4488 PM8001_FAIL_DBG(pm8001_ha, 4489 pm8001_printk("task 0x%p resp 0x%x " 4490 " stat 0x%x but aborted by upper layer " 4491 "\n", task, ts->resp, ts->stat)); 4492 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag); 4493 } else { 4494 spin_unlock_irqrestore(&task->task_state_lock, 4495 flags); 4496 pm8001_ccb_task_free_done(pm8001_ha, task, 4497 ccb, tag); 4498 return 0; 4499 } 4500 } 4501 } 4502 4503 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 4504 sizeof(sata_cmd), 0); 4505 return ret; 4506 } 4507 4508 /** 4509 * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND 4510 * @pm8001_ha: our hba card information. 4511 * @phy_id: the phy id which we wanted to start up. 4512 */ 4513 static int 4514 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id) 4515 { 4516 struct phy_start_req payload; 4517 struct inbound_queue_table *circularQ; 4518 int ret; 4519 u32 tag = 0x01; 4520 u32 opcode = OPC_INB_PHYSTART; 4521 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4522 memset(&payload, 0, sizeof(payload)); 4523 payload.tag = cpu_to_le32(tag); 4524 /* 4525 ** [0:7] PHY Identifier 4526 ** [8:11] link rate 1.5G, 3G, 6G 4527 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both 4528 ** [14] 0b disable spin up hold; 1b enable spin up hold 4529 */ 4530 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE | 4531 LINKMODE_AUTO | LINKRATE_15 | 4532 LINKRATE_30 | LINKRATE_60 | phy_id); 4533 payload.sas_identify.dev_type = SAS_END_DEVICE; 4534 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL; 4535 memcpy(payload.sas_identify.sas_addr, 4536 pm8001_ha->sas_addr, SAS_ADDR_SIZE); 4537 payload.sas_identify.phy_id = phy_id; 4538 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 4539 sizeof(payload), 0); 4540 return ret; 4541 } 4542 4543 /** 4544 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND 4545 * @pm8001_ha: our hba card information. 4546 * @phy_id: the phy id which we wanted to start up. 4547 */ 4548 static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha, 4549 u8 phy_id) 4550 { 4551 struct phy_stop_req payload; 4552 struct inbound_queue_table *circularQ; 4553 int ret; 4554 u32 tag = 0x01; 4555 u32 opcode = OPC_INB_PHYSTOP; 4556 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4557 memset(&payload, 0, sizeof(payload)); 4558 payload.tag = cpu_to_le32(tag); 4559 payload.phy_id = cpu_to_le32(phy_id); 4560 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 4561 sizeof(payload), 0); 4562 return ret; 4563 } 4564 4565 /* 4566 * see comments on pm8001_mpi_reg_resp. 4567 */ 4568 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha, 4569 struct pm8001_device *pm8001_dev, u32 flag) 4570 { 4571 struct reg_dev_req payload; 4572 u32 opc; 4573 u32 stp_sspsmp_sata = 0x4; 4574 struct inbound_queue_table *circularQ; 4575 u32 linkrate, phy_id; 4576 int rc, tag = 0xdeadbeef; 4577 struct pm8001_ccb_info *ccb; 4578 u8 retryFlag = 0x1; 4579 u16 firstBurstSize = 0; 4580 u16 ITNT = 2000; 4581 struct domain_device *dev = pm8001_dev->sas_device; 4582 struct domain_device *parent_dev = dev->parent; 4583 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4584 4585 memset(&payload, 0, sizeof(payload)); 4586 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4587 if (rc) 4588 return rc; 4589 ccb = &pm8001_ha->ccb_info[tag]; 4590 ccb->device = pm8001_dev; 4591 ccb->ccb_tag = tag; 4592 payload.tag = cpu_to_le32(tag); 4593 if (flag == 1) 4594 stp_sspsmp_sata = 0x02; /*direct attached sata */ 4595 else { 4596 if (pm8001_dev->dev_type == SAS_SATA_DEV) 4597 stp_sspsmp_sata = 0x00; /* stp*/ 4598 else if (pm8001_dev->dev_type == SAS_END_DEVICE || 4599 pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE || 4600 pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE) 4601 stp_sspsmp_sata = 0x01; /*ssp or smp*/ 4602 } 4603 if (parent_dev && dev_is_expander(parent_dev->dev_type)) 4604 phy_id = parent_dev->ex_dev.ex_phy->phy_id; 4605 else 4606 phy_id = pm8001_dev->attached_phy; 4607 opc = OPC_INB_REG_DEV; 4608 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ? 4609 pm8001_dev->sas_device->linkrate : dev->port->linkrate; 4610 payload.phyid_portid = 4611 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) | 4612 ((phy_id & 0x0F) << 4)); 4613 payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) | 4614 ((linkrate & 0x0F) * 0x1000000) | 4615 ((stp_sspsmp_sata & 0x03) * 0x10000000)); 4616 payload.firstburstsize_ITNexustimeout = 4617 cpu_to_le32(ITNT | (firstBurstSize * 0x10000)); 4618 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr, 4619 SAS_ADDR_SIZE); 4620 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4621 sizeof(payload), 0); 4622 return rc; 4623 } 4624 4625 /* 4626 * see comments on pm8001_mpi_reg_resp. 4627 */ 4628 int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha, 4629 u32 device_id) 4630 { 4631 struct dereg_dev_req payload; 4632 u32 opc = OPC_INB_DEREG_DEV_HANDLE; 4633 int ret; 4634 struct inbound_queue_table *circularQ; 4635 4636 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4637 memset(&payload, 0, sizeof(payload)); 4638 payload.tag = cpu_to_le32(1); 4639 payload.device_id = cpu_to_le32(device_id); 4640 PM8001_MSG_DBG(pm8001_ha, 4641 pm8001_printk("unregister device device_id = %d\n", device_id)); 4642 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4643 sizeof(payload), 0); 4644 return ret; 4645 } 4646 4647 /** 4648 * pm8001_chip_phy_ctl_req - support the local phy operation 4649 * @pm8001_ha: our hba card information. 4650 * @phyId: the phy id which we wanted to operate 4651 * @phy_op: the phy operation to request 4652 */ 4653 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 4654 u32 phyId, u32 phy_op) 4655 { 4656 struct local_phy_ctl_req payload; 4657 struct inbound_queue_table *circularQ; 4658 int ret; 4659 u32 opc = OPC_INB_LOCAL_PHY_CONTROL; 4660 memset(&payload, 0, sizeof(payload)); 4661 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4662 payload.tag = cpu_to_le32(1); 4663 payload.phyop_phyid = 4664 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F)); 4665 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4666 sizeof(payload), 0); 4667 return ret; 4668 } 4669 4670 static u32 pm8001_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha) 4671 { 4672 #ifdef PM8001_USE_MSIX 4673 return 1; 4674 #else 4675 u32 value; 4676 4677 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR); 4678 if (value) 4679 return 1; 4680 return 0; 4681 #endif 4682 } 4683 4684 /** 4685 * pm8001_chip_isr - PM8001 isr handler. 4686 * @pm8001_ha: our hba card information. 4687 * @vec: IRQ number 4688 */ 4689 static irqreturn_t 4690 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec) 4691 { 4692 pm8001_chip_interrupt_disable(pm8001_ha, vec); 4693 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk( 4694 "irq vec %d, ODMR:0x%x\n", 4695 vec, pm8001_cr32(pm8001_ha, 0, 0x30))); 4696 process_oq(pm8001_ha, vec); 4697 pm8001_chip_interrupt_enable(pm8001_ha, vec); 4698 return IRQ_HANDLED; 4699 } 4700 4701 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc, 4702 u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag) 4703 { 4704 struct task_abort_req task_abort; 4705 struct inbound_queue_table *circularQ; 4706 int ret; 4707 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4708 memset(&task_abort, 0, sizeof(task_abort)); 4709 if (ABORT_SINGLE == (flag & ABORT_MASK)) { 4710 task_abort.abort_all = 0; 4711 task_abort.device_id = cpu_to_le32(dev_id); 4712 task_abort.tag_to_abort = cpu_to_le32(task_tag); 4713 task_abort.tag = cpu_to_le32(cmd_tag); 4714 } else if (ABORT_ALL == (flag & ABORT_MASK)) { 4715 task_abort.abort_all = cpu_to_le32(1); 4716 task_abort.device_id = cpu_to_le32(dev_id); 4717 task_abort.tag = cpu_to_le32(cmd_tag); 4718 } 4719 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 4720 sizeof(task_abort), 0); 4721 return ret; 4722 } 4723 4724 /* 4725 * pm8001_chip_abort_task - SAS abort task when error or exception happened. 4726 */ 4727 int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha, 4728 struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag) 4729 { 4730 u32 opc, device_id; 4731 int rc = TMF_RESP_FUNC_FAILED; 4732 PM8001_EH_DBG(pm8001_ha, 4733 pm8001_printk("cmd_tag = %x, abort task tag = 0x%x", 4734 cmd_tag, task_tag)); 4735 if (pm8001_dev->dev_type == SAS_END_DEVICE) 4736 opc = OPC_INB_SSP_ABORT; 4737 else if (pm8001_dev->dev_type == SAS_SATA_DEV) 4738 opc = OPC_INB_SATA_ABORT; 4739 else 4740 opc = OPC_INB_SMP_ABORT;/* SMP */ 4741 device_id = pm8001_dev->device_id; 4742 rc = send_task_abort(pm8001_ha, opc, device_id, flag, 4743 task_tag, cmd_tag); 4744 if (rc != TMF_RESP_FUNC_COMPLETE) 4745 PM8001_EH_DBG(pm8001_ha, pm8001_printk("rc= %d\n", rc)); 4746 return rc; 4747 } 4748 4749 /** 4750 * pm8001_chip_ssp_tm_req - built the task management command. 4751 * @pm8001_ha: our hba card information. 4752 * @ccb: the ccb information. 4753 * @tmf: task management function. 4754 */ 4755 int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha, 4756 struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf) 4757 { 4758 struct sas_task *task = ccb->task; 4759 struct domain_device *dev = task->dev; 4760 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4761 u32 opc = OPC_INB_SSPINITMSTART; 4762 struct inbound_queue_table *circularQ; 4763 struct ssp_ini_tm_start_req sspTMCmd; 4764 int ret; 4765 4766 memset(&sspTMCmd, 0, sizeof(sspTMCmd)); 4767 sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id); 4768 sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed); 4769 sspTMCmd.tmf = cpu_to_le32(tmf->tmf); 4770 memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8); 4771 sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag); 4772 if (pm8001_ha->chip_id != chip_8001) 4773 sspTMCmd.ds_ads_m = 0x08; 4774 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4775 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd, 4776 sizeof(sspTMCmd), 0); 4777 return ret; 4778 } 4779 4780 int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha, 4781 void *payload) 4782 { 4783 u32 opc = OPC_INB_GET_NVMD_DATA; 4784 u32 nvmd_type; 4785 int rc; 4786 u32 tag; 4787 struct pm8001_ccb_info *ccb; 4788 struct inbound_queue_table *circularQ; 4789 struct get_nvm_data_req nvmd_req; 4790 struct fw_control_ex *fw_control_context; 4791 struct pm8001_ioctl_payload *ioctl_payload = payload; 4792 4793 nvmd_type = ioctl_payload->minor_function; 4794 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); 4795 if (!fw_control_context) 4796 return -ENOMEM; 4797 fw_control_context->usrAddr = (u8 *)ioctl_payload->func_specific; 4798 fw_control_context->len = ioctl_payload->rd_length; 4799 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4800 memset(&nvmd_req, 0, sizeof(nvmd_req)); 4801 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4802 if (rc) { 4803 kfree(fw_control_context); 4804 return rc; 4805 } 4806 ccb = &pm8001_ha->ccb_info[tag]; 4807 ccb->ccb_tag = tag; 4808 ccb->fw_control_context = fw_control_context; 4809 nvmd_req.tag = cpu_to_le32(tag); 4810 4811 switch (nvmd_type) { 4812 case TWI_DEVICE: { 4813 u32 twi_addr, twi_page_size; 4814 twi_addr = 0xa8; 4815 twi_page_size = 2; 4816 4817 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 | 4818 twi_page_size << 8 | TWI_DEVICE); 4819 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length); 4820 nvmd_req.resp_addr_hi = 4821 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4822 nvmd_req.resp_addr_lo = 4823 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4824 break; 4825 } 4826 case C_SEEPROM: { 4827 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM); 4828 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length); 4829 nvmd_req.resp_addr_hi = 4830 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4831 nvmd_req.resp_addr_lo = 4832 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4833 break; 4834 } 4835 case VPD_FLASH: { 4836 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH); 4837 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length); 4838 nvmd_req.resp_addr_hi = 4839 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4840 nvmd_req.resp_addr_lo = 4841 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4842 break; 4843 } 4844 case EXPAN_ROM: { 4845 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM); 4846 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length); 4847 nvmd_req.resp_addr_hi = 4848 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4849 nvmd_req.resp_addr_lo = 4850 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4851 break; 4852 } 4853 case IOP_RDUMP: { 4854 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | IOP_RDUMP); 4855 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length); 4856 nvmd_req.vpd_offset = cpu_to_le32(ioctl_payload->offset); 4857 nvmd_req.resp_addr_hi = 4858 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4859 nvmd_req.resp_addr_lo = 4860 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4861 break; 4862 } 4863 default: 4864 break; 4865 } 4866 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req, 4867 sizeof(nvmd_req), 0); 4868 if (rc) { 4869 kfree(fw_control_context); 4870 pm8001_tag_free(pm8001_ha, tag); 4871 } 4872 return rc; 4873 } 4874 4875 int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha, 4876 void *payload) 4877 { 4878 u32 opc = OPC_INB_SET_NVMD_DATA; 4879 u32 nvmd_type; 4880 int rc; 4881 u32 tag; 4882 struct pm8001_ccb_info *ccb; 4883 struct inbound_queue_table *circularQ; 4884 struct set_nvm_data_req nvmd_req; 4885 struct fw_control_ex *fw_control_context; 4886 struct pm8001_ioctl_payload *ioctl_payload = payload; 4887 4888 nvmd_type = ioctl_payload->minor_function; 4889 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); 4890 if (!fw_control_context) 4891 return -ENOMEM; 4892 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4893 memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr, 4894 &ioctl_payload->func_specific, 4895 ioctl_payload->wr_length); 4896 memset(&nvmd_req, 0, sizeof(nvmd_req)); 4897 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4898 if (rc) { 4899 kfree(fw_control_context); 4900 return -EBUSY; 4901 } 4902 ccb = &pm8001_ha->ccb_info[tag]; 4903 ccb->fw_control_context = fw_control_context; 4904 ccb->ccb_tag = tag; 4905 nvmd_req.tag = cpu_to_le32(tag); 4906 switch (nvmd_type) { 4907 case TWI_DEVICE: { 4908 u32 twi_addr, twi_page_size; 4909 twi_addr = 0xa8; 4910 twi_page_size = 2; 4911 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4912 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 | 4913 twi_page_size << 8 | TWI_DEVICE); 4914 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length); 4915 nvmd_req.resp_addr_hi = 4916 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4917 nvmd_req.resp_addr_lo = 4918 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4919 break; 4920 } 4921 case C_SEEPROM: 4922 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM); 4923 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length); 4924 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4925 nvmd_req.resp_addr_hi = 4926 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4927 nvmd_req.resp_addr_lo = 4928 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4929 break; 4930 case VPD_FLASH: 4931 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH); 4932 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length); 4933 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4934 nvmd_req.resp_addr_hi = 4935 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4936 nvmd_req.resp_addr_lo = 4937 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4938 break; 4939 case EXPAN_ROM: 4940 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM); 4941 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length); 4942 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4943 nvmd_req.resp_addr_hi = 4944 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4945 nvmd_req.resp_addr_lo = 4946 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4947 break; 4948 default: 4949 break; 4950 } 4951 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req, 4952 sizeof(nvmd_req), 0); 4953 if (rc) { 4954 kfree(fw_control_context); 4955 pm8001_tag_free(pm8001_ha, tag); 4956 } 4957 return rc; 4958 } 4959 4960 /** 4961 * pm8001_chip_fw_flash_update_build - support the firmware update operation 4962 * @pm8001_ha: our hba card information. 4963 * @fw_flash_updata_info: firmware flash update param 4964 * @tag: Tag to apply to the payload 4965 */ 4966 int 4967 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha, 4968 void *fw_flash_updata_info, u32 tag) 4969 { 4970 struct fw_flash_Update_req payload; 4971 struct fw_flash_updata_info *info; 4972 struct inbound_queue_table *circularQ; 4973 int ret; 4974 u32 opc = OPC_INB_FW_FLASH_UPDATE; 4975 4976 memset(&payload, 0, sizeof(struct fw_flash_Update_req)); 4977 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4978 info = fw_flash_updata_info; 4979 payload.tag = cpu_to_le32(tag); 4980 payload.cur_image_len = cpu_to_le32(info->cur_image_len); 4981 payload.cur_image_offset = cpu_to_le32(info->cur_image_offset); 4982 payload.total_image_len = cpu_to_le32(info->total_image_len); 4983 payload.len = info->sgl.im_len.len ; 4984 payload.sgl_addr_lo = 4985 cpu_to_le32(lower_32_bits(le64_to_cpu(info->sgl.addr))); 4986 payload.sgl_addr_hi = 4987 cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr))); 4988 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4989 sizeof(payload), 0); 4990 return ret; 4991 } 4992 4993 int 4994 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha, 4995 void *payload) 4996 { 4997 struct fw_flash_updata_info flash_update_info; 4998 struct fw_control_info *fw_control; 4999 struct fw_control_ex *fw_control_context; 5000 int rc; 5001 u32 tag; 5002 struct pm8001_ccb_info *ccb; 5003 void *buffer = pm8001_ha->memoryMap.region[FW_FLASH].virt_ptr; 5004 dma_addr_t phys_addr = pm8001_ha->memoryMap.region[FW_FLASH].phys_addr; 5005 struct pm8001_ioctl_payload *ioctl_payload = payload; 5006 5007 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); 5008 if (!fw_control_context) 5009 return -ENOMEM; 5010 fw_control = (struct fw_control_info *)&ioctl_payload->func_specific; 5011 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk( 5012 "dma fw_control context input length :%x\n", fw_control->len)); 5013 memcpy(buffer, fw_control->buffer, fw_control->len); 5014 flash_update_info.sgl.addr = cpu_to_le64(phys_addr); 5015 flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len); 5016 flash_update_info.sgl.im_len.e = 0; 5017 flash_update_info.cur_image_offset = fw_control->offset; 5018 flash_update_info.cur_image_len = fw_control->len; 5019 flash_update_info.total_image_len = fw_control->size; 5020 fw_control_context->fw_control = fw_control; 5021 fw_control_context->virtAddr = buffer; 5022 fw_control_context->phys_addr = phys_addr; 5023 fw_control_context->len = fw_control->len; 5024 rc = pm8001_tag_alloc(pm8001_ha, &tag); 5025 if (rc) { 5026 kfree(fw_control_context); 5027 return -EBUSY; 5028 } 5029 ccb = &pm8001_ha->ccb_info[tag]; 5030 ccb->fw_control_context = fw_control_context; 5031 ccb->ccb_tag = tag; 5032 rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info, 5033 tag); 5034 return rc; 5035 } 5036 5037 ssize_t 5038 pm8001_get_gsm_dump(struct device *cdev, u32 length, char *buf) 5039 { 5040 u32 value, rem, offset = 0, bar = 0; 5041 u32 index, work_offset, dw_length; 5042 u32 shift_value, gsm_base, gsm_dump_offset; 5043 char *direct_data; 5044 struct Scsi_Host *shost = class_to_shost(cdev); 5045 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 5046 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 5047 5048 direct_data = buf; 5049 gsm_dump_offset = pm8001_ha->fatal_forensic_shift_offset; 5050 5051 /* check max is 1 Mbytes */ 5052 if ((length > 0x100000) || (gsm_dump_offset & 3) || 5053 ((gsm_dump_offset + length) > 0x1000000)) 5054 return -EINVAL; 5055 5056 if (pm8001_ha->chip_id == chip_8001) 5057 bar = 2; 5058 else 5059 bar = 1; 5060 5061 work_offset = gsm_dump_offset & 0xFFFF0000; 5062 offset = gsm_dump_offset & 0x0000FFFF; 5063 gsm_dump_offset = work_offset; 5064 /* adjust length to dword boundary */ 5065 rem = length & 3; 5066 dw_length = length >> 2; 5067 5068 for (index = 0; index < dw_length; index++) { 5069 if ((work_offset + offset) & 0xFFFF0000) { 5070 if (pm8001_ha->chip_id == chip_8001) 5071 shift_value = ((gsm_dump_offset + offset) & 5072 SHIFT_REG_64K_MASK); 5073 else 5074 shift_value = (((gsm_dump_offset + offset) & 5075 SHIFT_REG_64K_MASK) >> 5076 SHIFT_REG_BIT_SHIFT); 5077 5078 if (pm8001_ha->chip_id == chip_8001) { 5079 gsm_base = GSM_BASE; 5080 if (-1 == pm8001_bar4_shift(pm8001_ha, 5081 (gsm_base + shift_value))) 5082 return -EIO; 5083 } else { 5084 gsm_base = 0; 5085 if (-1 == pm80xx_bar4_shift(pm8001_ha, 5086 (gsm_base + shift_value))) 5087 return -EIO; 5088 } 5089 gsm_dump_offset = (gsm_dump_offset + offset) & 5090 0xFFFF0000; 5091 work_offset = 0; 5092 offset = offset & 0x0000FFFF; 5093 } 5094 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) & 5095 0x0000FFFF); 5096 direct_data += sprintf(direct_data, "%08x ", value); 5097 offset += 4; 5098 } 5099 if (rem != 0) { 5100 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) & 5101 0x0000FFFF); 5102 /* xfr for non_dw */ 5103 direct_data += sprintf(direct_data, "%08x ", value); 5104 } 5105 /* Shift back to BAR4 original address */ 5106 if (-1 == pm8001_bar4_shift(pm8001_ha, 0)) 5107 return -EIO; 5108 pm8001_ha->fatal_forensic_shift_offset += 1024; 5109 5110 if (pm8001_ha->fatal_forensic_shift_offset >= 0x100000) 5111 pm8001_ha->fatal_forensic_shift_offset = 0; 5112 return direct_data - buf; 5113 } 5114 5115 int 5116 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha, 5117 struct pm8001_device *pm8001_dev, u32 state) 5118 { 5119 struct set_dev_state_req payload; 5120 struct inbound_queue_table *circularQ; 5121 struct pm8001_ccb_info *ccb; 5122 int rc; 5123 u32 tag; 5124 u32 opc = OPC_INB_SET_DEVICE_STATE; 5125 memset(&payload, 0, sizeof(payload)); 5126 rc = pm8001_tag_alloc(pm8001_ha, &tag); 5127 if (rc) 5128 return -1; 5129 ccb = &pm8001_ha->ccb_info[tag]; 5130 ccb->ccb_tag = tag; 5131 ccb->device = pm8001_dev; 5132 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 5133 payload.tag = cpu_to_le32(tag); 5134 payload.device_id = cpu_to_le32(pm8001_dev->device_id); 5135 payload.nds = cpu_to_le32(state); 5136 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 5137 sizeof(payload), 0); 5138 return rc; 5139 5140 } 5141 5142 static int 5143 pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha) 5144 { 5145 struct sas_re_initialization_req payload; 5146 struct inbound_queue_table *circularQ; 5147 struct pm8001_ccb_info *ccb; 5148 int rc; 5149 u32 tag; 5150 u32 opc = OPC_INB_SAS_RE_INITIALIZE; 5151 memset(&payload, 0, sizeof(payload)); 5152 rc = pm8001_tag_alloc(pm8001_ha, &tag); 5153 if (rc) 5154 return -ENOMEM; 5155 ccb = &pm8001_ha->ccb_info[tag]; 5156 ccb->ccb_tag = tag; 5157 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 5158 payload.tag = cpu_to_le32(tag); 5159 payload.SSAHOLT = cpu_to_le32(0xd << 25); 5160 payload.sata_hol_tmo = cpu_to_le32(80); 5161 payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff); 5162 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 5163 sizeof(payload), 0); 5164 if (rc) 5165 pm8001_tag_free(pm8001_ha, tag); 5166 return rc; 5167 5168 } 5169 5170 const struct pm8001_dispatch pm8001_8001_dispatch = { 5171 .name = "pmc8001", 5172 .chip_init = pm8001_chip_init, 5173 .chip_soft_rst = pm8001_chip_soft_rst, 5174 .chip_rst = pm8001_hw_chip_rst, 5175 .chip_iounmap = pm8001_chip_iounmap, 5176 .isr = pm8001_chip_isr, 5177 .is_our_interrupt = pm8001_chip_is_our_interrupt, 5178 .isr_process_oq = process_oq, 5179 .interrupt_enable = pm8001_chip_interrupt_enable, 5180 .interrupt_disable = pm8001_chip_interrupt_disable, 5181 .make_prd = pm8001_chip_make_sg, 5182 .smp_req = pm8001_chip_smp_req, 5183 .ssp_io_req = pm8001_chip_ssp_io_req, 5184 .sata_req = pm8001_chip_sata_req, 5185 .phy_start_req = pm8001_chip_phy_start_req, 5186 .phy_stop_req = pm8001_chip_phy_stop_req, 5187 .reg_dev_req = pm8001_chip_reg_dev_req, 5188 .dereg_dev_req = pm8001_chip_dereg_dev_req, 5189 .phy_ctl_req = pm8001_chip_phy_ctl_req, 5190 .task_abort = pm8001_chip_abort_task, 5191 .ssp_tm_req = pm8001_chip_ssp_tm_req, 5192 .get_nvmd_req = pm8001_chip_get_nvmd_req, 5193 .set_nvmd_req = pm8001_chip_set_nvmd_req, 5194 .fw_flash_update_req = pm8001_chip_fw_flash_update_req, 5195 .set_dev_state_req = pm8001_chip_set_dev_state_req, 5196 .sas_re_init_req = pm8001_chip_sas_re_initialization, 5197 }; 5198