1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * NinjaSCSI-32Bi Cardbus, NinjaSCSI-32UDE PCI/CardBus SCSI driver 4 * Copyright (C) 2001, 2002, 2003 5 * YOKOTA Hiroshi <yokota@netlab.is.tsukuba.ac.jp> 6 * GOTO Masanori <gotom@debian.or.jp>, <gotom@debian.org> 7 * 8 * Revision History: 9 * 1.0: Initial Release. 10 * 1.1: Add /proc SDTR status. 11 * Remove obsolete error handler nsp32_reset. 12 * Some clean up. 13 * 1.2: PowerPC (big endian) support. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/init.h> 18 #include <linux/kernel.h> 19 #include <linux/string.h> 20 #include <linux/timer.h> 21 #include <linux/ioport.h> 22 #include <linux/major.h> 23 #include <linux/blkdev.h> 24 #include <linux/interrupt.h> 25 #include <linux/pci.h> 26 #include <linux/delay.h> 27 #include <linux/ctype.h> 28 #include <linux/dma-mapping.h> 29 30 #include <asm/dma.h> 31 #include <asm/io.h> 32 33 #include <scsi/scsi.h> 34 #include <scsi/scsi_cmnd.h> 35 #include <scsi/scsi_device.h> 36 #include <scsi/scsi_host.h> 37 #include <scsi/scsi_ioctl.h> 38 39 #include "nsp32.h" 40 41 42 /*********************************************************************** 43 * Module parameters 44 */ 45 static int trans_mode = 0; /* default: BIOS */ 46 module_param (trans_mode, int, 0); 47 MODULE_PARM_DESC(trans_mode, "transfer mode (0: BIOS(default) 1: Async 2: Ultra20M"); 48 #define ASYNC_MODE 1 49 #define ULTRA20M_MODE 2 50 51 static bool auto_param = 0; /* default: ON */ 52 module_param (auto_param, bool, 0); 53 MODULE_PARM_DESC(auto_param, "AutoParameter mode (0: ON(default) 1: OFF)"); 54 55 static bool disc_priv = 1; /* default: OFF */ 56 module_param (disc_priv, bool, 0); 57 MODULE_PARM_DESC(disc_priv, "disconnection privilege mode (0: ON 1: OFF(default))"); 58 59 MODULE_AUTHOR("YOKOTA Hiroshi <yokota@netlab.is.tsukuba.ac.jp>, GOTO Masanori <gotom@debian.or.jp>"); 60 MODULE_DESCRIPTION("Workbit NinjaSCSI-32Bi/UDE CardBus/PCI SCSI host bus adapter module"); 61 MODULE_LICENSE("GPL"); 62 63 static const char *nsp32_release_version = "1.2"; 64 65 66 /**************************************************************************** 67 * Supported hardware 68 */ 69 static struct pci_device_id nsp32_pci_table[] = { 70 { 71 .vendor = PCI_VENDOR_ID_IODATA, 72 .device = PCI_DEVICE_ID_NINJASCSI_32BI_CBSC_II, 73 .subvendor = PCI_ANY_ID, 74 .subdevice = PCI_ANY_ID, 75 .driver_data = MODEL_IODATA, 76 }, 77 { 78 .vendor = PCI_VENDOR_ID_WORKBIT, 79 .device = PCI_DEVICE_ID_NINJASCSI_32BI_KME, 80 .subvendor = PCI_ANY_ID, 81 .subdevice = PCI_ANY_ID, 82 .driver_data = MODEL_KME, 83 }, 84 { 85 .vendor = PCI_VENDOR_ID_WORKBIT, 86 .device = PCI_DEVICE_ID_NINJASCSI_32BI_WBT, 87 .subvendor = PCI_ANY_ID, 88 .subdevice = PCI_ANY_ID, 89 .driver_data = MODEL_WORKBIT, 90 }, 91 { 92 .vendor = PCI_VENDOR_ID_WORKBIT, 93 .device = PCI_DEVICE_ID_WORKBIT_STANDARD, 94 .subvendor = PCI_ANY_ID, 95 .subdevice = PCI_ANY_ID, 96 .driver_data = MODEL_PCI_WORKBIT, 97 }, 98 { 99 .vendor = PCI_VENDOR_ID_WORKBIT, 100 .device = PCI_DEVICE_ID_NINJASCSI_32BI_LOGITEC, 101 .subvendor = PCI_ANY_ID, 102 .subdevice = PCI_ANY_ID, 103 .driver_data = MODEL_LOGITEC, 104 }, 105 { 106 .vendor = PCI_VENDOR_ID_WORKBIT, 107 .device = PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC, 108 .subvendor = PCI_ANY_ID, 109 .subdevice = PCI_ANY_ID, 110 .driver_data = MODEL_PCI_LOGITEC, 111 }, 112 { 113 .vendor = PCI_VENDOR_ID_WORKBIT, 114 .device = PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO, 115 .subvendor = PCI_ANY_ID, 116 .subdevice = PCI_ANY_ID, 117 .driver_data = MODEL_PCI_MELCO, 118 }, 119 { 120 .vendor = PCI_VENDOR_ID_WORKBIT, 121 .device = PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO_II, 122 .subvendor = PCI_ANY_ID, 123 .subdevice = PCI_ANY_ID, 124 .driver_data = MODEL_PCI_MELCO, 125 }, 126 {0,0,}, 127 }; 128 MODULE_DEVICE_TABLE(pci, nsp32_pci_table); 129 130 static nsp32_hw_data nsp32_data_base; /* probe <-> detect glue */ 131 132 133 /* 134 * Period/AckWidth speed conversion table 135 * 136 * Note: This period/ackwidth speed table must be in descending order. 137 */ 138 static nsp32_sync_table nsp32_sync_table_40M[] = { 139 /* {PNo, AW, SP, EP, SREQ smpl} Speed(MB/s) Period AckWidth */ 140 {0x1, 0, 0x0c, 0x0c, SMPL_40M}, /* 20.0 : 50ns, 25ns */ 141 {0x2, 0, 0x0d, 0x18, SMPL_40M}, /* 13.3 : 75ns, 25ns */ 142 {0x3, 1, 0x19, 0x19, SMPL_40M}, /* 10.0 : 100ns, 50ns */ 143 {0x4, 1, 0x1a, 0x1f, SMPL_20M}, /* 8.0 : 125ns, 50ns */ 144 {0x5, 2, 0x20, 0x25, SMPL_20M}, /* 6.7 : 150ns, 75ns */ 145 {0x6, 2, 0x26, 0x31, SMPL_20M}, /* 5.7 : 175ns, 75ns */ 146 {0x7, 3, 0x32, 0x32, SMPL_20M}, /* 5.0 : 200ns, 100ns */ 147 {0x8, 3, 0x33, 0x38, SMPL_10M}, /* 4.4 : 225ns, 100ns */ 148 {0x9, 3, 0x39, 0x3e, SMPL_10M}, /* 4.0 : 250ns, 100ns */ 149 }; 150 151 static nsp32_sync_table nsp32_sync_table_20M[] = { 152 {0x1, 0, 0x19, 0x19, SMPL_40M}, /* 10.0 : 100ns, 50ns */ 153 {0x2, 0, 0x1a, 0x25, SMPL_20M}, /* 6.7 : 150ns, 50ns */ 154 {0x3, 1, 0x26, 0x32, SMPL_20M}, /* 5.0 : 200ns, 100ns */ 155 {0x4, 1, 0x33, 0x3e, SMPL_10M}, /* 4.0 : 250ns, 100ns */ 156 {0x5, 2, 0x3f, 0x4b, SMPL_10M}, /* 3.3 : 300ns, 150ns */ 157 {0x6, 2, 0x4c, 0x57, SMPL_10M}, /* 2.8 : 350ns, 150ns */ 158 {0x7, 3, 0x58, 0x64, SMPL_10M}, /* 2.5 : 400ns, 200ns */ 159 {0x8, 3, 0x65, 0x70, SMPL_10M}, /* 2.2 : 450ns, 200ns */ 160 {0x9, 3, 0x71, 0x7d, SMPL_10M}, /* 2.0 : 500ns, 200ns */ 161 }; 162 163 static nsp32_sync_table nsp32_sync_table_pci[] = { 164 {0x1, 0, 0x0c, 0x0f, SMPL_40M}, /* 16.6 : 60ns, 30ns */ 165 {0x2, 0, 0x10, 0x16, SMPL_40M}, /* 11.1 : 90ns, 30ns */ 166 {0x3, 1, 0x17, 0x1e, SMPL_20M}, /* 8.3 : 120ns, 60ns */ 167 {0x4, 1, 0x1f, 0x25, SMPL_20M}, /* 6.7 : 150ns, 60ns */ 168 {0x5, 2, 0x26, 0x2d, SMPL_20M}, /* 5.6 : 180ns, 90ns */ 169 {0x6, 2, 0x2e, 0x34, SMPL_10M}, /* 4.8 : 210ns, 90ns */ 170 {0x7, 3, 0x35, 0x3c, SMPL_10M}, /* 4.2 : 240ns, 120ns */ 171 {0x8, 3, 0x3d, 0x43, SMPL_10M}, /* 3.7 : 270ns, 120ns */ 172 {0x9, 3, 0x44, 0x4b, SMPL_10M}, /* 3.3 : 300ns, 120ns */ 173 }; 174 175 /* 176 * function declaration 177 */ 178 /* module entry point */ 179 static int nsp32_probe (struct pci_dev *, const struct pci_device_id *); 180 static void nsp32_remove(struct pci_dev *); 181 static int __init init_nsp32 (void); 182 static void __exit exit_nsp32 (void); 183 184 /* struct struct scsi_host_template */ 185 static int nsp32_show_info (struct seq_file *, struct Scsi_Host *); 186 187 static int nsp32_detect (struct pci_dev *pdev); 188 static int nsp32_queuecommand(struct Scsi_Host *, struct scsi_cmnd *); 189 static const char *nsp32_info (struct Scsi_Host *); 190 static int nsp32_release (struct Scsi_Host *); 191 192 /* SCSI error handler */ 193 static int nsp32_eh_abort (struct scsi_cmnd *); 194 static int nsp32_eh_host_reset(struct scsi_cmnd *); 195 196 /* generate SCSI message */ 197 static void nsp32_build_identify(struct scsi_cmnd *); 198 static void nsp32_build_nop (struct scsi_cmnd *); 199 static void nsp32_build_reject (struct scsi_cmnd *); 200 static void nsp32_build_sdtr (struct scsi_cmnd *, unsigned char, 201 unsigned char); 202 203 /* SCSI message handler */ 204 static int nsp32_busfree_occur(struct scsi_cmnd *, unsigned short); 205 static void nsp32_msgout_occur (struct scsi_cmnd *); 206 static void nsp32_msgin_occur (struct scsi_cmnd *, unsigned long, 207 unsigned short); 208 209 static int nsp32_setup_sg_table (struct scsi_cmnd *); 210 static int nsp32_selection_autopara(struct scsi_cmnd *); 211 static int nsp32_selection_autoscsi(struct scsi_cmnd *); 212 static void nsp32_scsi_done (struct scsi_cmnd *); 213 static int nsp32_arbitration (struct scsi_cmnd *, unsigned int); 214 static int nsp32_reselection (struct scsi_cmnd *, unsigned char); 215 static void nsp32_adjust_busfree (struct scsi_cmnd *, unsigned int); 216 static void nsp32_restart_autoscsi (struct scsi_cmnd *, unsigned short); 217 218 /* SCSI SDTR */ 219 static void nsp32_analyze_sdtr (struct scsi_cmnd *); 220 static int nsp32_search_period_entry(nsp32_hw_data *, nsp32_target *, 221 unsigned char); 222 static void nsp32_set_async (nsp32_hw_data *, nsp32_target *); 223 static void nsp32_set_max_sync (nsp32_hw_data *, nsp32_target *, 224 unsigned char *, unsigned char *); 225 static void nsp32_set_sync_entry (nsp32_hw_data *, nsp32_target *, 226 int, unsigned char); 227 228 /* SCSI bus status handler */ 229 static void nsp32_wait_req (nsp32_hw_data *, int); 230 static void nsp32_wait_sack (nsp32_hw_data *, int); 231 static void nsp32_sack_assert (nsp32_hw_data *); 232 static void nsp32_sack_negate (nsp32_hw_data *); 233 static void nsp32_do_bus_reset(nsp32_hw_data *); 234 235 /* hardware interrupt handler */ 236 static irqreturn_t do_nsp32_isr(int, void *); 237 238 /* initialize hardware */ 239 static int nsp32hw_init(nsp32_hw_data *); 240 241 /* EEPROM handler */ 242 static int nsp32_getprom_param (nsp32_hw_data *); 243 static int nsp32_getprom_at24 (nsp32_hw_data *); 244 static int nsp32_getprom_c16 (nsp32_hw_data *); 245 static void nsp32_prom_start (nsp32_hw_data *); 246 static void nsp32_prom_stop (nsp32_hw_data *); 247 static int nsp32_prom_read (nsp32_hw_data *, int); 248 static int nsp32_prom_read_bit (nsp32_hw_data *); 249 static void nsp32_prom_write_bit(nsp32_hw_data *, int); 250 static void nsp32_prom_set (nsp32_hw_data *, int, int); 251 static int nsp32_prom_get (nsp32_hw_data *, int); 252 253 /* debug/warning/info message */ 254 static void nsp32_message (const char *, int, char *, char *, ...); 255 #ifdef NSP32_DEBUG 256 static void nsp32_dmessage(const char *, int, int, char *, ...); 257 #endif 258 259 /* 260 * max_sectors is currently limited up to 128. 261 */ 262 static struct scsi_host_template nsp32_template = { 263 .proc_name = "nsp32", 264 .name = "Workbit NinjaSCSI-32Bi/UDE", 265 .show_info = nsp32_show_info, 266 .info = nsp32_info, 267 .queuecommand = nsp32_queuecommand, 268 .can_queue = 1, 269 .sg_tablesize = NSP32_SG_SIZE, 270 .max_sectors = 128, 271 .this_id = NSP32_HOST_SCSIID, 272 .dma_boundary = PAGE_SIZE - 1, 273 .eh_abort_handler = nsp32_eh_abort, 274 .eh_host_reset_handler = nsp32_eh_host_reset, 275 /* .highmem_io = 1, */ 276 }; 277 278 #include "nsp32_io.h" 279 280 /*********************************************************************** 281 * debug, error print 282 */ 283 #ifndef NSP32_DEBUG 284 # define NSP32_DEBUG_MASK 0x000000 285 # define nsp32_msg(type, args...) nsp32_message ("", 0, (type), args) 286 # define nsp32_dbg(mask, args...) /* */ 287 #else 288 # define NSP32_DEBUG_MASK 0xffffff 289 # define nsp32_msg(type, args...) \ 290 nsp32_message (__func__, __LINE__, (type), args) 291 # define nsp32_dbg(mask, args...) \ 292 nsp32_dmessage(__func__, __LINE__, (mask), args) 293 #endif 294 295 #define NSP32_DEBUG_QUEUECOMMAND BIT(0) 296 #define NSP32_DEBUG_REGISTER BIT(1) 297 #define NSP32_DEBUG_AUTOSCSI BIT(2) 298 #define NSP32_DEBUG_INTR BIT(3) 299 #define NSP32_DEBUG_SGLIST BIT(4) 300 #define NSP32_DEBUG_BUSFREE BIT(5) 301 #define NSP32_DEBUG_CDB_CONTENTS BIT(6) 302 #define NSP32_DEBUG_RESELECTION BIT(7) 303 #define NSP32_DEBUG_MSGINOCCUR BIT(8) 304 #define NSP32_DEBUG_EEPROM BIT(9) 305 #define NSP32_DEBUG_MSGOUTOCCUR BIT(10) 306 #define NSP32_DEBUG_BUSRESET BIT(11) 307 #define NSP32_DEBUG_RESTART BIT(12) 308 #define NSP32_DEBUG_SYNC BIT(13) 309 #define NSP32_DEBUG_WAIT BIT(14) 310 #define NSP32_DEBUG_TARGETFLAG BIT(15) 311 #define NSP32_DEBUG_PROC BIT(16) 312 #define NSP32_DEBUG_INIT BIT(17) 313 #define NSP32_SPECIAL_PRINT_REGISTER BIT(20) 314 315 #define NSP32_DEBUG_BUF_LEN 100 316 317 __printf(4, 5) 318 static void nsp32_message(const char *func, int line, char *type, char *fmt, ...) 319 { 320 va_list args; 321 char buf[NSP32_DEBUG_BUF_LEN]; 322 323 va_start(args, fmt); 324 vsnprintf(buf, sizeof(buf), fmt, args); 325 va_end(args); 326 327 #ifndef NSP32_DEBUG 328 printk("%snsp32: %s\n", type, buf); 329 #else 330 printk("%snsp32: %s (%d): %s\n", type, func, line, buf); 331 #endif 332 } 333 334 #ifdef NSP32_DEBUG 335 static void nsp32_dmessage(const char *func, int line, int mask, char *fmt, ...) 336 { 337 va_list args; 338 char buf[NSP32_DEBUG_BUF_LEN]; 339 340 va_start(args, fmt); 341 vsnprintf(buf, sizeof(buf), fmt, args); 342 va_end(args); 343 344 if (mask & NSP32_DEBUG_MASK) { 345 printk("nsp32-debug: 0x%x %s (%d): %s\n", mask, func, line, buf); 346 } 347 } 348 #endif 349 350 #ifdef NSP32_DEBUG 351 # include "nsp32_debug.c" 352 #else 353 # define show_command(arg) /* */ 354 # define show_busphase(arg) /* */ 355 # define show_autophase(arg) /* */ 356 #endif 357 358 /* 359 * IDENTIFY Message 360 */ 361 static void nsp32_build_identify(struct scsi_cmnd *SCpnt) 362 { 363 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 364 int pos = data->msgout_len; 365 int mode = FALSE; 366 367 /* XXX: Auto DiscPriv detection is progressing... */ 368 if (disc_priv == 0) { 369 /* mode = TRUE; */ 370 } 371 372 data->msgoutbuf[pos] = IDENTIFY(mode, SCpnt->device->lun); pos++; 373 374 data->msgout_len = pos; 375 } 376 377 /* 378 * SDTR Message Routine 379 */ 380 static void nsp32_build_sdtr(struct scsi_cmnd *SCpnt, 381 unsigned char period, 382 unsigned char offset) 383 { 384 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 385 int pos = data->msgout_len; 386 387 data->msgoutbuf[pos] = EXTENDED_MESSAGE; pos++; 388 data->msgoutbuf[pos] = EXTENDED_SDTR_LEN; pos++; 389 data->msgoutbuf[pos] = EXTENDED_SDTR; pos++; 390 data->msgoutbuf[pos] = period; pos++; 391 data->msgoutbuf[pos] = offset; pos++; 392 393 data->msgout_len = pos; 394 } 395 396 /* 397 * No Operation Message 398 */ 399 static void nsp32_build_nop(struct scsi_cmnd *SCpnt) 400 { 401 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 402 int pos = data->msgout_len; 403 404 if (pos != 0) { 405 nsp32_msg(KERN_WARNING, 406 "Some messages are already contained!"); 407 return; 408 } 409 410 data->msgoutbuf[pos] = NOP; pos++; 411 data->msgout_len = pos; 412 } 413 414 /* 415 * Reject Message 416 */ 417 static void nsp32_build_reject(struct scsi_cmnd *SCpnt) 418 { 419 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 420 int pos = data->msgout_len; 421 422 data->msgoutbuf[pos] = MESSAGE_REJECT; pos++; 423 data->msgout_len = pos; 424 } 425 426 /* 427 * timer 428 */ 429 #if 0 430 static void nsp32_start_timer(struct scsi_cmnd *SCpnt, int time) 431 { 432 unsigned int base = SCpnt->host->io_port; 433 434 nsp32_dbg(NSP32_DEBUG_INTR, "timer=%d", time); 435 436 if (time & (~TIMER_CNT_MASK)) { 437 nsp32_dbg(NSP32_DEBUG_INTR, "timer set overflow"); 438 } 439 440 nsp32_write2(base, TIMER_SET, time & TIMER_CNT_MASK); 441 } 442 #endif 443 444 445 /* 446 * set SCSI command and other parameter to asic, and start selection phase 447 */ 448 static int nsp32_selection_autopara(struct scsi_cmnd *SCpnt) 449 { 450 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 451 unsigned int base = SCpnt->device->host->io_port; 452 unsigned int host_id = SCpnt->device->host->this_id; 453 unsigned char target = scmd_id(SCpnt); 454 nsp32_autoparam *param = data->autoparam; 455 unsigned char phase; 456 int i, ret; 457 unsigned int msgout; 458 u16_le s; 459 460 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "in"); 461 462 /* 463 * check bus free 464 */ 465 phase = nsp32_read1(base, SCSI_BUS_MONITOR); 466 if (phase != BUSMON_BUS_FREE) { 467 nsp32_msg(KERN_WARNING, "bus busy"); 468 show_busphase(phase & BUSMON_PHASE_MASK); 469 SCpnt->result = DID_BUS_BUSY << 16; 470 return FALSE; 471 } 472 473 /* 474 * message out 475 * 476 * Note: If the range of msgout_len is 1 - 3, fill scsi_msgout. 477 * over 3 messages needs another routine. 478 */ 479 if (data->msgout_len == 0) { 480 nsp32_msg(KERN_ERR, "SCSI MsgOut without any message!"); 481 SCpnt->result = DID_ERROR << 16; 482 return FALSE; 483 } else if (data->msgout_len > 0 && data->msgout_len <= 3) { 484 msgout = 0; 485 for (i = 0; i < data->msgout_len; i++) { 486 /* 487 * the sending order of the message is: 488 * MCNT 3: MSG#0 -> MSG#1 -> MSG#2 489 * MCNT 2: MSG#1 -> MSG#2 490 * MCNT 1: MSG#2 491 */ 492 msgout >>= 8; 493 msgout |= ((unsigned int)(data->msgoutbuf[i]) << 24); 494 } 495 msgout |= MV_VALID; /* MV valid */ 496 msgout |= (unsigned int)data->msgout_len; /* len */ 497 } else { 498 /* data->msgout_len > 3 */ 499 msgout = 0; 500 } 501 502 // nsp_dbg(NSP32_DEBUG_AUTOSCSI, "sel time out=0x%x\n", 503 // nsp32_read2(base, SEL_TIME_OUT)); 504 // nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME); 505 506 /* 507 * setup asic parameter 508 */ 509 memset(param, 0, sizeof(nsp32_autoparam)); 510 511 /* cdb */ 512 for (i = 0; i < SCpnt->cmd_len; i++) { 513 param->cdb[4 * i] = SCpnt->cmnd[i]; 514 } 515 516 /* outgoing messages */ 517 param->msgout = cpu_to_le32(msgout); 518 519 /* syncreg, ackwidth, target id, SREQ sampling rate */ 520 param->syncreg = data->cur_target->syncreg; 521 param->ackwidth = data->cur_target->ackwidth; 522 param->target_id = BIT(host_id) | BIT(target); 523 param->sample_reg = data->cur_target->sample_reg; 524 525 // nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "sample rate=0x%x\n", data->cur_target->sample_reg); 526 527 /* command control */ 528 param->command_control = cpu_to_le16(CLEAR_CDB_FIFO_POINTER | 529 AUTOSCSI_START | 530 AUTO_MSGIN_00_OR_04 | 531 AUTO_MSGIN_02 | 532 AUTO_ATN ); 533 534 535 /* transfer control */ 536 s = 0; 537 switch (data->trans_method) { 538 case NSP32_TRANSFER_BUSMASTER: 539 s |= BM_START; 540 break; 541 case NSP32_TRANSFER_MMIO: 542 s |= CB_MMIO_MODE; 543 break; 544 case NSP32_TRANSFER_PIO: 545 s |= CB_IO_MODE; 546 break; 547 default: 548 nsp32_msg(KERN_ERR, "unknown trans_method"); 549 break; 550 } 551 /* 552 * OR-ed BLIEND_MODE, FIFO intr is decreased, instead of PCI bus waits. 553 * For bus master transfer, it's taken off. 554 */ 555 s |= (TRANSFER_GO | ALL_COUNTER_CLR); 556 param->transfer_control = cpu_to_le16(s); 557 558 /* sg table addr */ 559 param->sgt_pointer = cpu_to_le32(data->cur_lunt->sglun_paddr); 560 561 /* 562 * transfer parameter to ASIC 563 */ 564 nsp32_write4(base, SGT_ADR, data->auto_paddr); 565 nsp32_write2(base, COMMAND_CONTROL, 566 CLEAR_CDB_FIFO_POINTER | AUTO_PARAMETER ); 567 568 /* 569 * Check arbitration 570 */ 571 ret = nsp32_arbitration(SCpnt, base); 572 573 return ret; 574 } 575 576 577 /* 578 * Selection with AUTO SCSI (without AUTO PARAMETER) 579 */ 580 static int nsp32_selection_autoscsi(struct scsi_cmnd *SCpnt) 581 { 582 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 583 unsigned int base = SCpnt->device->host->io_port; 584 unsigned int host_id = SCpnt->device->host->this_id; 585 unsigned char target = scmd_id(SCpnt); 586 unsigned char phase; 587 int status; 588 unsigned short command = 0; 589 unsigned int msgout = 0; 590 int i; 591 592 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "in"); 593 594 /* 595 * IRQ disable 596 */ 597 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK); 598 599 /* 600 * check bus line 601 */ 602 phase = nsp32_read1(base, SCSI_BUS_MONITOR); 603 if ((phase & BUSMON_BSY) || (phase & BUSMON_SEL)) { 604 nsp32_msg(KERN_WARNING, "bus busy"); 605 SCpnt->result = DID_BUS_BUSY << 16; 606 status = 1; 607 goto out; 608 } 609 610 /* 611 * clear execph 612 */ 613 nsp32_read2(base, SCSI_EXECUTE_PHASE); 614 615 /* 616 * clear FIFO counter to set CDBs 617 */ 618 nsp32_write2(base, COMMAND_CONTROL, CLEAR_CDB_FIFO_POINTER); 619 620 /* 621 * set CDB0 - CDB15 622 */ 623 for (i = 0; i < SCpnt->cmd_len; i++) { 624 nsp32_write1(base, COMMAND_DATA, SCpnt->cmnd[i]); 625 } 626 nsp32_dbg(NSP32_DEBUG_CDB_CONTENTS, "CDB[0]=[0x%x]", SCpnt->cmnd[0]); 627 628 /* 629 * set SCSIOUT LATCH(initiator)/TARGET(target) (OR-ed) ID 630 */ 631 nsp32_write1(base, SCSI_OUT_LATCH_TARGET_ID, 632 BIT(host_id) | BIT(target)); 633 634 /* 635 * set SCSI MSGOUT REG 636 * 637 * Note: If the range of msgout_len is 1 - 3, fill scsi_msgout. 638 * over 3 messages needs another routine. 639 */ 640 if (data->msgout_len == 0) { 641 nsp32_msg(KERN_ERR, "SCSI MsgOut without any message!"); 642 SCpnt->result = DID_ERROR << 16; 643 status = 1; 644 goto out; 645 } else if (data->msgout_len > 0 && data->msgout_len <= 3) { 646 msgout = 0; 647 for (i = 0; i < data->msgout_len; i++) { 648 /* 649 * the sending order of the message is: 650 * MCNT 3: MSG#0 -> MSG#1 -> MSG#2 651 * MCNT 2: MSG#1 -> MSG#2 652 * MCNT 1: MSG#2 653 */ 654 msgout >>= 8; 655 msgout |= ((unsigned int)(data->msgoutbuf[i]) << 24); 656 } 657 msgout |= MV_VALID; /* MV valid */ 658 msgout |= (unsigned int)data->msgout_len; /* len */ 659 nsp32_write4(base, SCSI_MSG_OUT, msgout); 660 } else { 661 /* data->msgout_len > 3 */ 662 nsp32_write4(base, SCSI_MSG_OUT, 0); 663 } 664 665 /* 666 * set selection timeout(= 250ms) 667 */ 668 nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME); 669 670 /* 671 * set SREQ hazard killer sampling rate 672 * 673 * TODO: sample_rate (BASE+0F) is 0 when internal clock = 40MHz. 674 * check other internal clock! 675 */ 676 nsp32_write1(base, SREQ_SMPL_RATE, data->cur_target->sample_reg); 677 678 /* 679 * clear Arbit 680 */ 681 nsp32_write1(base, SET_ARBIT, ARBIT_CLEAR); 682 683 /* 684 * set SYNCREG 685 * Don't set BM_START_ADR before setting this register. 686 */ 687 nsp32_write1(base, SYNC_REG, data->cur_target->syncreg); 688 689 /* 690 * set ACKWIDTH 691 */ 692 nsp32_write1(base, ACK_WIDTH, data->cur_target->ackwidth); 693 694 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, 695 "syncreg=0x%x, ackwidth=0x%x, sgtpaddr=0x%x, id=0x%x", 696 nsp32_read1(base, SYNC_REG), nsp32_read1(base, ACK_WIDTH), 697 nsp32_read4(base, SGT_ADR), 698 nsp32_read1(base, SCSI_OUT_LATCH_TARGET_ID)); 699 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "msgout_len=%d, msgout=0x%x", 700 data->msgout_len, msgout); 701 702 /* 703 * set SGT ADDR (physical address) 704 */ 705 nsp32_write4(base, SGT_ADR, data->cur_lunt->sglun_paddr); 706 707 /* 708 * set TRANSFER CONTROL REG 709 */ 710 command = 0; 711 command |= (TRANSFER_GO | ALL_COUNTER_CLR); 712 if (data->trans_method & NSP32_TRANSFER_BUSMASTER) { 713 if (scsi_bufflen(SCpnt) > 0) { 714 command |= BM_START; 715 } 716 } else if (data->trans_method & NSP32_TRANSFER_MMIO) { 717 command |= CB_MMIO_MODE; 718 } else if (data->trans_method & NSP32_TRANSFER_PIO) { 719 command |= CB_IO_MODE; 720 } 721 nsp32_write2(base, TRANSFER_CONTROL, command); 722 723 /* 724 * start AUTO SCSI, kick off arbitration 725 */ 726 command = (CLEAR_CDB_FIFO_POINTER | 727 AUTOSCSI_START | 728 AUTO_MSGIN_00_OR_04 | 729 AUTO_MSGIN_02 | 730 AUTO_ATN); 731 nsp32_write2(base, COMMAND_CONTROL, command); 732 733 /* 734 * Check arbitration 735 */ 736 status = nsp32_arbitration(SCpnt, base); 737 738 out: 739 /* 740 * IRQ enable 741 */ 742 nsp32_write2(base, IRQ_CONTROL, 0); 743 744 return status; 745 } 746 747 748 /* 749 * Arbitration Status Check 750 * 751 * Note: Arbitration counter is waited during ARBIT_GO is not lifting. 752 * Using udelay(1) consumes CPU time and system time, but 753 * arbitration delay time is defined minimal 2.4us in SCSI 754 * specification, thus udelay works as coarse grained wait timer. 755 */ 756 static int nsp32_arbitration(struct scsi_cmnd *SCpnt, unsigned int base) 757 { 758 unsigned char arbit; 759 int status = TRUE; 760 int time = 0; 761 762 do { 763 arbit = nsp32_read1(base, ARBIT_STATUS); 764 time++; 765 } while ((arbit & (ARBIT_WIN | ARBIT_FAIL)) == 0 && 766 (time <= ARBIT_TIMEOUT_TIME)); 767 768 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, 769 "arbit: 0x%x, delay time: %d", arbit, time); 770 771 if (arbit & ARBIT_WIN) { 772 /* Arbitration succeeded */ 773 SCpnt->result = DID_OK << 16; 774 nsp32_index_write1(base, EXT_PORT, LED_ON); /* PCI LED on */ 775 } else if (arbit & ARBIT_FAIL) { 776 /* Arbitration failed */ 777 SCpnt->result = DID_BUS_BUSY << 16; 778 status = FALSE; 779 } else { 780 /* 781 * unknown error or ARBIT_GO timeout, 782 * something lock up! guess no connection. 783 */ 784 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "arbit timeout"); 785 SCpnt->result = DID_NO_CONNECT << 16; 786 status = FALSE; 787 } 788 789 /* 790 * clear Arbit 791 */ 792 nsp32_write1(base, SET_ARBIT, ARBIT_CLEAR); 793 794 return status; 795 } 796 797 798 /* 799 * reselection 800 * 801 * Note: This reselection routine is called from msgin_occur, 802 * reselection target id&lun must be already set. 803 * SCSI-2 says IDENTIFY implies RESTORE_POINTER operation. 804 */ 805 static int nsp32_reselection(struct scsi_cmnd *SCpnt, unsigned char newlun) 806 { 807 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 808 unsigned int host_id = SCpnt->device->host->this_id; 809 unsigned int base = SCpnt->device->host->io_port; 810 unsigned char tmpid, newid; 811 812 nsp32_dbg(NSP32_DEBUG_RESELECTION, "enter"); 813 814 /* 815 * calculate reselected SCSI ID 816 */ 817 tmpid = nsp32_read1(base, RESELECT_ID); 818 tmpid &= (~BIT(host_id)); 819 newid = 0; 820 while (tmpid) { 821 if (tmpid & 1) { 822 break; 823 } 824 tmpid >>= 1; 825 newid++; 826 } 827 828 /* 829 * If reselected New ID:LUN is not existed 830 * or current nexus is not existed, unexpected 831 * reselection is occurred. Send reject message. 832 */ 833 if (newid >= ARRAY_SIZE(data->lunt) || 834 newlun >= ARRAY_SIZE(data->lunt[0])) { 835 nsp32_msg(KERN_WARNING, "unknown id/lun"); 836 return FALSE; 837 } else if(data->lunt[newid][newlun].SCpnt == NULL) { 838 nsp32_msg(KERN_WARNING, "no SCSI command is processing"); 839 return FALSE; 840 } 841 842 data->cur_id = newid; 843 data->cur_lun = newlun; 844 data->cur_target = &(data->target[newid]); 845 data->cur_lunt = &(data->lunt[newid][newlun]); 846 847 /* reset SACK/SavedACK counter (or ALL clear?) */ 848 nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK); 849 850 return TRUE; 851 } 852 853 854 /* 855 * nsp32_setup_sg_table - build scatter gather list for transfer data 856 * with bus master. 857 * 858 * Note: NinjaSCSI-32Bi/UDE bus master can not transfer over 64KB at a time. 859 */ 860 static int nsp32_setup_sg_table(struct scsi_cmnd *SCpnt) 861 { 862 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 863 struct scatterlist *sg; 864 nsp32_sgtable *sgt = data->cur_lunt->sglun->sgt; 865 int num, i; 866 u32_le l; 867 868 if (sgt == NULL) { 869 nsp32_dbg(NSP32_DEBUG_SGLIST, "SGT == null"); 870 return FALSE; 871 } 872 873 num = scsi_dma_map(SCpnt); 874 if (!num) 875 return TRUE; 876 else if (num < 0) 877 return FALSE; 878 else { 879 scsi_for_each_sg(SCpnt, sg, num, i) { 880 /* 881 * Build nsp32_sglist, substitute sg dma addresses. 882 */ 883 sgt[i].addr = cpu_to_le32(sg_dma_address(sg)); 884 sgt[i].len = cpu_to_le32(sg_dma_len(sg)); 885 886 if (le32_to_cpu(sgt[i].len) > 0x10000) { 887 nsp32_msg(KERN_ERR, 888 "can't transfer over 64KB at a time, " 889 "size=0x%x", le32_to_cpu(sgt[i].len)); 890 return FALSE; 891 } 892 nsp32_dbg(NSP32_DEBUG_SGLIST, 893 "num 0x%x : addr 0x%lx len 0x%lx", 894 i, 895 le32_to_cpu(sgt[i].addr), 896 le32_to_cpu(sgt[i].len )); 897 } 898 899 /* set end mark */ 900 l = le32_to_cpu(sgt[num-1].len); 901 sgt[num-1].len = cpu_to_le32(l | SGTEND); 902 } 903 904 return TRUE; 905 } 906 907 static int nsp32_queuecommand_lck(struct scsi_cmnd *SCpnt, 908 void (*done)(struct scsi_cmnd *)) 909 { 910 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 911 nsp32_target *target; 912 nsp32_lunt *cur_lunt; 913 int ret; 914 915 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, 916 "enter. target: 0x%x LUN: 0x%llx cmnd: 0x%x cmndlen: 0x%x " 917 "use_sg: 0x%x reqbuf: 0x%lx reqlen: 0x%x", 918 SCpnt->device->id, SCpnt->device->lun, SCpnt->cmnd[0], 919 SCpnt->cmd_len, scsi_sg_count(SCpnt), scsi_sglist(SCpnt), 920 scsi_bufflen(SCpnt)); 921 922 if (data->CurrentSC != NULL) { 923 nsp32_msg(KERN_ERR, "Currentsc != NULL. Cancel this command request"); 924 data->CurrentSC = NULL; 925 SCpnt->result = DID_NO_CONNECT << 16; 926 done(SCpnt); 927 return 0; 928 } 929 930 /* check target ID is not same as this initiator ID */ 931 if (scmd_id(SCpnt) == SCpnt->device->host->this_id) { 932 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, "target==host???"); 933 SCpnt->result = DID_BAD_TARGET << 16; 934 done(SCpnt); 935 return 0; 936 } 937 938 /* check target LUN is allowable value */ 939 if (SCpnt->device->lun >= MAX_LUN) { 940 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, "no more lun"); 941 SCpnt->result = DID_BAD_TARGET << 16; 942 done(SCpnt); 943 return 0; 944 } 945 946 show_command(SCpnt); 947 948 SCpnt->scsi_done = done; 949 data->CurrentSC = SCpnt; 950 SCpnt->SCp.Status = SAM_STAT_CHECK_CONDITION; 951 SCpnt->SCp.Message = 0; 952 scsi_set_resid(SCpnt, scsi_bufflen(SCpnt)); 953 954 SCpnt->SCp.ptr = (char *)scsi_sglist(SCpnt); 955 SCpnt->SCp.this_residual = scsi_bufflen(SCpnt); 956 SCpnt->SCp.buffer = NULL; 957 SCpnt->SCp.buffers_residual = 0; 958 959 /* initialize data */ 960 data->msgout_len = 0; 961 data->msgin_len = 0; 962 cur_lunt = &(data->lunt[SCpnt->device->id][SCpnt->device->lun]); 963 cur_lunt->SCpnt = SCpnt; 964 cur_lunt->save_datp = 0; 965 cur_lunt->msgin03 = FALSE; 966 data->cur_lunt = cur_lunt; 967 data->cur_id = SCpnt->device->id; 968 data->cur_lun = SCpnt->device->lun; 969 970 ret = nsp32_setup_sg_table(SCpnt); 971 if (ret == FALSE) { 972 nsp32_msg(KERN_ERR, "SGT fail"); 973 SCpnt->result = DID_ERROR << 16; 974 nsp32_scsi_done(SCpnt); 975 return 0; 976 } 977 978 /* Build IDENTIFY */ 979 nsp32_build_identify(SCpnt); 980 981 /* 982 * If target is the first time to transfer after the reset 983 * (target don't have SDTR_DONE and SDTR_INITIATOR), sync 984 * message SDTR is needed to do synchronous transfer. 985 */ 986 target = &data->target[scmd_id(SCpnt)]; 987 data->cur_target = target; 988 989 if (!(target->sync_flag & (SDTR_DONE | SDTR_INITIATOR | SDTR_TARGET))) { 990 unsigned char period, offset; 991 992 if (trans_mode != ASYNC_MODE) { 993 nsp32_set_max_sync(data, target, &period, &offset); 994 nsp32_build_sdtr(SCpnt, period, offset); 995 target->sync_flag |= SDTR_INITIATOR; 996 } else { 997 nsp32_set_async(data, target); 998 target->sync_flag |= SDTR_DONE; 999 } 1000 1001 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, 1002 "SDTR: entry: %d start_period: 0x%x offset: 0x%x\n", 1003 target->limit_entry, period, offset); 1004 } else if (target->sync_flag & SDTR_INITIATOR) { 1005 /* 1006 * It was negotiating SDTR with target, sending from the 1007 * initiator, but there are no chance to remove this flag. 1008 * Set async because we don't get proper negotiation. 1009 */ 1010 nsp32_set_async(data, target); 1011 target->sync_flag &= ~SDTR_INITIATOR; 1012 target->sync_flag |= SDTR_DONE; 1013 1014 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, 1015 "SDTR_INITIATOR: fall back to async"); 1016 } else if (target->sync_flag & SDTR_TARGET) { 1017 /* 1018 * It was negotiating SDTR with target, sending from target, 1019 * but there are no chance to remove this flag. Set async 1020 * because we don't get proper negotiation. 1021 */ 1022 nsp32_set_async(data, target); 1023 target->sync_flag &= ~SDTR_TARGET; 1024 target->sync_flag |= SDTR_DONE; 1025 1026 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, 1027 "Unknown SDTR from target is reached, fall back to async."); 1028 } 1029 1030 nsp32_dbg(NSP32_DEBUG_TARGETFLAG, 1031 "target: %d sync_flag: 0x%x syncreg: 0x%x ackwidth: 0x%x", 1032 SCpnt->device->id, target->sync_flag, target->syncreg, 1033 target->ackwidth); 1034 1035 /* Selection */ 1036 if (auto_param == 0) { 1037 ret = nsp32_selection_autopara(SCpnt); 1038 } else { 1039 ret = nsp32_selection_autoscsi(SCpnt); 1040 } 1041 1042 if (ret != TRUE) { 1043 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, "selection fail"); 1044 nsp32_scsi_done(SCpnt); 1045 } 1046 1047 return 0; 1048 } 1049 1050 static DEF_SCSI_QCMD(nsp32_queuecommand) 1051 1052 /* initialize asic */ 1053 static int nsp32hw_init(nsp32_hw_data *data) 1054 { 1055 unsigned int base = data->BaseAddress; 1056 unsigned short irq_stat; 1057 unsigned long lc_reg; 1058 unsigned char power; 1059 1060 lc_reg = nsp32_index_read4(base, CFG_LATE_CACHE); 1061 if ((lc_reg & 0xff00) == 0) { 1062 lc_reg |= (0x20 << 8); 1063 nsp32_index_write2(base, CFG_LATE_CACHE, lc_reg & 0xffff); 1064 } 1065 1066 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK); 1067 nsp32_write2(base, TRANSFER_CONTROL, 0); 1068 nsp32_write4(base, BM_CNT, 0); 1069 nsp32_write2(base, SCSI_EXECUTE_PHASE, 0); 1070 1071 do { 1072 irq_stat = nsp32_read2(base, IRQ_STATUS); 1073 nsp32_dbg(NSP32_DEBUG_INIT, "irq_stat 0x%x", irq_stat); 1074 } while (irq_stat & IRQSTATUS_ANY_IRQ); 1075 1076 /* 1077 * Fill FIFO_FULL_SHLD, FIFO_EMPTY_SHLD. Below parameter is 1078 * designated by specification. 1079 */ 1080 if ((data->trans_method & NSP32_TRANSFER_PIO) || 1081 (data->trans_method & NSP32_TRANSFER_MMIO)) { 1082 nsp32_index_write1(base, FIFO_FULL_SHLD_COUNT, 0x40); 1083 nsp32_index_write1(base, FIFO_EMPTY_SHLD_COUNT, 0x40); 1084 } else if (data->trans_method & NSP32_TRANSFER_BUSMASTER) { 1085 nsp32_index_write1(base, FIFO_FULL_SHLD_COUNT, 0x10); 1086 nsp32_index_write1(base, FIFO_EMPTY_SHLD_COUNT, 0x60); 1087 } else { 1088 nsp32_dbg(NSP32_DEBUG_INIT, "unknown transfer mode"); 1089 } 1090 1091 nsp32_dbg(NSP32_DEBUG_INIT, "full 0x%x emp 0x%x", 1092 nsp32_index_read1(base, FIFO_FULL_SHLD_COUNT), 1093 nsp32_index_read1(base, FIFO_EMPTY_SHLD_COUNT)); 1094 1095 nsp32_index_write1(base, CLOCK_DIV, data->clock); 1096 nsp32_index_write1(base, BM_CYCLE, 1097 MEMRD_CMD1 | SGT_AUTO_PARA_MEMED_CMD); 1098 nsp32_write1(base, PARITY_CONTROL, 0); /* parity check is disable */ 1099 1100 /* 1101 * initialize MISC_WRRD register 1102 * 1103 * Note: Designated parameters is obeyed as following: 1104 * MISC_SCSI_DIRECTION_DETECTOR_SELECT: It must be set. 1105 * MISC_MASTER_TERMINATION_SELECT: It must be set. 1106 * MISC_BMREQ_NEGATE_TIMING_SEL: It should be set. 1107 * MISC_AUTOSEL_TIMING_SEL: It should be set. 1108 * MISC_BMSTOP_CHANGE2_NONDATA_PHASE: It should be set. 1109 * MISC_DELAYED_BMSTART: It's selected for safety. 1110 * 1111 * Note: If MISC_BMSTOP_CHANGE2_NONDATA_PHASE is set, then 1112 * we have to set TRANSFERCONTROL_BM_START as 0 and set 1113 * appropriate value before restarting bus master transfer. 1114 */ 1115 nsp32_index_write2(base, MISC_WR, 1116 (SCSI_DIRECTION_DETECTOR_SELECT | 1117 DELAYED_BMSTART | 1118 MASTER_TERMINATION_SELECT | 1119 BMREQ_NEGATE_TIMING_SEL | 1120 AUTOSEL_TIMING_SEL | 1121 BMSTOP_CHANGE2_NONDATA_PHASE)); 1122 1123 nsp32_index_write1(base, TERM_PWR_CONTROL, 0); 1124 power = nsp32_index_read1(base, TERM_PWR_CONTROL); 1125 if (!(power & SENSE)) { 1126 nsp32_msg(KERN_INFO, "term power on"); 1127 nsp32_index_write1(base, TERM_PWR_CONTROL, BPWR); 1128 } 1129 1130 nsp32_write2(base, TIMER_SET, TIMER_STOP); 1131 nsp32_write2(base, TIMER_SET, TIMER_STOP); /* Required 2 times */ 1132 1133 nsp32_write1(base, SYNC_REG, 0); 1134 nsp32_write1(base, ACK_WIDTH, 0); 1135 nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME); 1136 1137 /* 1138 * enable to select designated IRQ (except for 1139 * IRQSELECT_SERR, IRQSELECT_PERR, IRQSELECT_BMCNTERR) 1140 */ 1141 nsp32_index_write2(base, IRQ_SELECT, 1142 IRQSELECT_TIMER_IRQ | 1143 IRQSELECT_SCSIRESET_IRQ | 1144 IRQSELECT_FIFO_SHLD_IRQ | 1145 IRQSELECT_RESELECT_IRQ | 1146 IRQSELECT_PHASE_CHANGE_IRQ | 1147 IRQSELECT_AUTO_SCSI_SEQ_IRQ | 1148 // IRQSELECT_BMCNTERR_IRQ | 1149 IRQSELECT_TARGET_ABORT_IRQ | 1150 IRQSELECT_MASTER_ABORT_IRQ ); 1151 nsp32_write2(base, IRQ_CONTROL, 0); 1152 1153 /* PCI LED off */ 1154 nsp32_index_write1(base, EXT_PORT_DDR, LED_OFF); 1155 nsp32_index_write1(base, EXT_PORT, LED_OFF); 1156 1157 return TRUE; 1158 } 1159 1160 1161 /* interrupt routine */ 1162 static irqreturn_t do_nsp32_isr(int irq, void *dev_id) 1163 { 1164 nsp32_hw_data *data = dev_id; 1165 unsigned int base = data->BaseAddress; 1166 struct scsi_cmnd *SCpnt = data->CurrentSC; 1167 unsigned short auto_stat, irq_stat, trans_stat; 1168 unsigned char busmon, busphase; 1169 unsigned long flags; 1170 int ret; 1171 int handled = 0; 1172 struct Scsi_Host *host = data->Host; 1173 1174 spin_lock_irqsave(host->host_lock, flags); 1175 1176 /* 1177 * IRQ check, then enable IRQ mask 1178 */ 1179 irq_stat = nsp32_read2(base, IRQ_STATUS); 1180 nsp32_dbg(NSP32_DEBUG_INTR, 1181 "enter IRQ: %d, IRQstatus: 0x%x", irq, irq_stat); 1182 /* is this interrupt comes from Ninja asic? */ 1183 if ((irq_stat & IRQSTATUS_ANY_IRQ) == 0) { 1184 nsp32_dbg(NSP32_DEBUG_INTR, 1185 "shared interrupt: irq other 0x%x", irq_stat); 1186 goto out2; 1187 } 1188 handled = 1; 1189 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK); 1190 1191 busmon = nsp32_read1(base, SCSI_BUS_MONITOR); 1192 busphase = busmon & BUSMON_PHASE_MASK; 1193 1194 trans_stat = nsp32_read2(base, TRANSFER_STATUS); 1195 if ((irq_stat == 0xffff) && (trans_stat == 0xffff)) { 1196 nsp32_msg(KERN_INFO, "card disconnect"); 1197 if (data->CurrentSC != NULL) { 1198 nsp32_msg(KERN_INFO, "clean up current SCSI command"); 1199 SCpnt->result = DID_BAD_TARGET << 16; 1200 nsp32_scsi_done(SCpnt); 1201 } 1202 goto out; 1203 } 1204 1205 /* Timer IRQ */ 1206 if (irq_stat & IRQSTATUS_TIMER_IRQ) { 1207 nsp32_dbg(NSP32_DEBUG_INTR, "timer stop"); 1208 nsp32_write2(base, TIMER_SET, TIMER_STOP); 1209 goto out; 1210 } 1211 1212 /* SCSI reset */ 1213 if (irq_stat & IRQSTATUS_SCSIRESET_IRQ) { 1214 nsp32_msg(KERN_INFO, "detected someone do bus reset"); 1215 nsp32_do_bus_reset(data); 1216 if (SCpnt != NULL) { 1217 SCpnt->result = DID_RESET << 16; 1218 nsp32_scsi_done(SCpnt); 1219 } 1220 goto out; 1221 } 1222 1223 if (SCpnt == NULL) { 1224 nsp32_msg(KERN_WARNING, "SCpnt==NULL this can't be happened"); 1225 nsp32_msg(KERN_WARNING, "irq_stat=0x%x trans_stat=0x%x", 1226 irq_stat, trans_stat); 1227 goto out; 1228 } 1229 1230 /* 1231 * AutoSCSI Interrupt. 1232 * Note: This interrupt is occurred when AutoSCSI is finished. Then 1233 * check SCSIEXECUTEPHASE, and do appropriate action. Each phases are 1234 * recorded when AutoSCSI sequencer has been processed. 1235 */ 1236 if(irq_stat & IRQSTATUS_AUTOSCSI_IRQ) { 1237 /* getting SCSI executed phase */ 1238 auto_stat = nsp32_read2(base, SCSI_EXECUTE_PHASE); 1239 nsp32_write2(base, SCSI_EXECUTE_PHASE, 0); 1240 1241 /* Selection Timeout, go busfree phase. */ 1242 if (auto_stat & SELECTION_TIMEOUT) { 1243 nsp32_dbg(NSP32_DEBUG_INTR, 1244 "selection timeout occurred"); 1245 1246 SCpnt->result = DID_TIME_OUT << 16; 1247 nsp32_scsi_done(SCpnt); 1248 goto out; 1249 } 1250 1251 if (auto_stat & MSGOUT_PHASE) { 1252 /* 1253 * MsgOut phase was processed. 1254 * If MSG_IN_OCCUER is not set, then MsgOut phase is 1255 * completed. Thus, msgout_len must reset. Otherwise, 1256 * nothing to do here. If MSG_OUT_OCCUER is occurred, 1257 * then we will encounter the condition and check. 1258 */ 1259 if (!(auto_stat & MSG_IN_OCCUER) && 1260 (data->msgout_len <= 3)) { 1261 /* 1262 * !MSG_IN_OCCUER && msgout_len <=3 1263 * ---> AutoSCSI with MSGOUTreg is processed. 1264 */ 1265 data->msgout_len = 0; 1266 } 1267 1268 nsp32_dbg(NSP32_DEBUG_INTR, "MsgOut phase processed"); 1269 } 1270 1271 if ((auto_stat & DATA_IN_PHASE) && 1272 (scsi_get_resid(SCpnt) > 0) && 1273 ((nsp32_read2(base, FIFO_REST_CNT) & FIFO_REST_MASK) != 0)) { 1274 printk( "auto+fifo\n"); 1275 //nsp32_pio_read(SCpnt); 1276 } 1277 1278 if (auto_stat & (DATA_IN_PHASE | DATA_OUT_PHASE)) { 1279 /* DATA_IN_PHASE/DATA_OUT_PHASE was processed. */ 1280 nsp32_dbg(NSP32_DEBUG_INTR, 1281 "Data in/out phase processed"); 1282 1283 /* read BMCNT, SGT pointer addr */ 1284 nsp32_dbg(NSP32_DEBUG_INTR, "BMCNT=0x%lx", 1285 nsp32_read4(base, BM_CNT)); 1286 nsp32_dbg(NSP32_DEBUG_INTR, "addr=0x%lx", 1287 nsp32_read4(base, SGT_ADR)); 1288 nsp32_dbg(NSP32_DEBUG_INTR, "SACK=0x%lx", 1289 nsp32_read4(base, SACK_CNT)); 1290 nsp32_dbg(NSP32_DEBUG_INTR, "SSACK=0x%lx", 1291 nsp32_read4(base, SAVED_SACK_CNT)); 1292 1293 scsi_set_resid(SCpnt, 0); /* all data transferred! */ 1294 } 1295 1296 /* 1297 * MsgIn Occur 1298 */ 1299 if (auto_stat & MSG_IN_OCCUER) { 1300 nsp32_msgin_occur(SCpnt, irq_stat, auto_stat); 1301 } 1302 1303 /* 1304 * MsgOut Occur 1305 */ 1306 if (auto_stat & MSG_OUT_OCCUER) { 1307 nsp32_msgout_occur(SCpnt); 1308 } 1309 1310 /* 1311 * Bus Free Occur 1312 */ 1313 if (auto_stat & BUS_FREE_OCCUER) { 1314 ret = nsp32_busfree_occur(SCpnt, auto_stat); 1315 if (ret == TRUE) { 1316 goto out; 1317 } 1318 } 1319 1320 if (auto_stat & STATUS_PHASE) { 1321 /* 1322 * Read CSB and substitute CSB for SCpnt->result 1323 * to save status phase stutas byte. 1324 * scsi error handler checks host_byte (DID_*: 1325 * low level driver to indicate status), then checks 1326 * status_byte (SCSI status byte). 1327 */ 1328 SCpnt->result = (int)nsp32_read1(base, SCSI_CSB_IN); 1329 } 1330 1331 if (auto_stat & ILLEGAL_PHASE) { 1332 /* Illegal phase is detected. SACK is not back. */ 1333 nsp32_msg(KERN_WARNING, 1334 "AUTO SCSI ILLEGAL PHASE OCCUR!!!!"); 1335 1336 /* TODO: currently we don't have any action... bus reset? */ 1337 1338 /* 1339 * To send back SACK, assert, wait, and negate. 1340 */ 1341 nsp32_sack_assert(data); 1342 nsp32_wait_req(data, NEGATE); 1343 nsp32_sack_negate(data); 1344 1345 } 1346 1347 if (auto_stat & COMMAND_PHASE) { 1348 /* nothing to do */ 1349 nsp32_dbg(NSP32_DEBUG_INTR, "Command phase processed"); 1350 } 1351 1352 if (auto_stat & AUTOSCSI_BUSY) { 1353 /* AutoSCSI is running */ 1354 } 1355 1356 show_autophase(auto_stat); 1357 } 1358 1359 /* FIFO_SHLD_IRQ */ 1360 if (irq_stat & IRQSTATUS_FIFO_SHLD_IRQ) { 1361 nsp32_dbg(NSP32_DEBUG_INTR, "FIFO IRQ"); 1362 1363 switch(busphase) { 1364 case BUSPHASE_DATA_OUT: 1365 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/write"); 1366 1367 //nsp32_pio_write(SCpnt); 1368 1369 break; 1370 1371 case BUSPHASE_DATA_IN: 1372 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/read"); 1373 1374 //nsp32_pio_read(SCpnt); 1375 1376 break; 1377 1378 case BUSPHASE_STATUS: 1379 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/status"); 1380 1381 SCpnt->SCp.Status = nsp32_read1(base, SCSI_CSB_IN); 1382 1383 break; 1384 default: 1385 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/other phase"); 1386 nsp32_dbg(NSP32_DEBUG_INTR, "irq_stat=0x%x trans_stat=0x%x", 1387 irq_stat, trans_stat); 1388 show_busphase(busphase); 1389 break; 1390 } 1391 1392 goto out; 1393 } 1394 1395 /* Phase Change IRQ */ 1396 if (irq_stat & IRQSTATUS_PHASE_CHANGE_IRQ) { 1397 nsp32_dbg(NSP32_DEBUG_INTR, "phase change IRQ"); 1398 1399 switch(busphase) { 1400 case BUSPHASE_MESSAGE_IN: 1401 nsp32_dbg(NSP32_DEBUG_INTR, "phase chg/msg in"); 1402 nsp32_msgin_occur(SCpnt, irq_stat, 0); 1403 break; 1404 default: 1405 nsp32_msg(KERN_WARNING, "phase chg/other phase?"); 1406 nsp32_msg(KERN_WARNING, "irq_stat=0x%x trans_stat=0x%x\n", 1407 irq_stat, trans_stat); 1408 show_busphase(busphase); 1409 break; 1410 } 1411 goto out; 1412 } 1413 1414 /* PCI_IRQ */ 1415 if (irq_stat & IRQSTATUS_PCI_IRQ) { 1416 nsp32_dbg(NSP32_DEBUG_INTR, "PCI IRQ occurred"); 1417 /* Do nothing */ 1418 } 1419 1420 /* BMCNTERR_IRQ */ 1421 if (irq_stat & IRQSTATUS_BMCNTERR_IRQ) { 1422 nsp32_msg(KERN_ERR, "Received unexpected BMCNTERR IRQ! "); 1423 /* 1424 * TODO: To be implemented improving bus master 1425 * transfer reliability when BMCNTERR is occurred in 1426 * AutoSCSI phase described in specification. 1427 */ 1428 } 1429 1430 #if 0 1431 nsp32_dbg(NSP32_DEBUG_INTR, 1432 "irq_stat=0x%x trans_stat=0x%x", irq_stat, trans_stat); 1433 show_busphase(busphase); 1434 #endif 1435 1436 out: 1437 /* disable IRQ mask */ 1438 nsp32_write2(base, IRQ_CONTROL, 0); 1439 1440 out2: 1441 spin_unlock_irqrestore(host->host_lock, flags); 1442 1443 nsp32_dbg(NSP32_DEBUG_INTR, "exit"); 1444 1445 return IRQ_RETVAL(handled); 1446 } 1447 1448 1449 static int nsp32_show_info(struct seq_file *m, struct Scsi_Host *host) 1450 { 1451 unsigned long flags; 1452 nsp32_hw_data *data; 1453 int hostno; 1454 unsigned int base; 1455 unsigned char mode_reg; 1456 int id, speed; 1457 long model; 1458 1459 hostno = host->host_no; 1460 data = (nsp32_hw_data *)host->hostdata; 1461 base = host->io_port; 1462 1463 seq_puts(m, "NinjaSCSI-32 status\n\n"); 1464 seq_printf(m, "Driver version: %s, $Revision: 1.33 $\n", 1465 nsp32_release_version); 1466 seq_printf(m, "SCSI host No.: %d\n", hostno); 1467 seq_printf(m, "IRQ: %d\n", host->irq); 1468 seq_printf(m, "IO: 0x%lx-0x%lx\n", 1469 host->io_port, host->io_port + host->n_io_port - 1); 1470 seq_printf(m, "MMIO(virtual address): 0x%lx-0x%lx\n", 1471 host->base, host->base + data->MmioLength - 1); 1472 seq_printf(m, "sg_tablesize: %d\n", 1473 host->sg_tablesize); 1474 seq_printf(m, "Chip revision: 0x%x\n", 1475 (nsp32_read2(base, INDEX_REG) >> 8) & 0xff); 1476 1477 mode_reg = nsp32_index_read1(base, CHIP_MODE); 1478 model = data->pci_devid->driver_data; 1479 1480 #ifdef CONFIG_PM 1481 seq_printf(m, "Power Management: %s\n", 1482 (mode_reg & OPTF) ? "yes" : "no"); 1483 #endif 1484 seq_printf(m, "OEM: %ld, %s\n", 1485 (mode_reg & (OEM0|OEM1)), nsp32_model[model]); 1486 1487 spin_lock_irqsave(&(data->Lock), flags); 1488 seq_printf(m, "CurrentSC: 0x%p\n\n", data->CurrentSC); 1489 spin_unlock_irqrestore(&(data->Lock), flags); 1490 1491 1492 seq_puts(m, "SDTR status\n"); 1493 for (id = 0; id < ARRAY_SIZE(data->target); id++) { 1494 1495 seq_printf(m, "id %d: ", id); 1496 1497 if (id == host->this_id) { 1498 seq_puts(m, "----- NinjaSCSI-32 host adapter\n"); 1499 continue; 1500 } 1501 1502 if (data->target[id].sync_flag == SDTR_DONE) { 1503 if (data->target[id].period == 0 && 1504 data->target[id].offset == ASYNC_OFFSET ) { 1505 seq_puts(m, "async"); 1506 } else { 1507 seq_puts(m, " sync"); 1508 } 1509 } else { 1510 seq_puts(m, " none"); 1511 } 1512 1513 if (data->target[id].period != 0) { 1514 1515 speed = 1000000 / (data->target[id].period * 4); 1516 1517 seq_printf(m, " transfer %d.%dMB/s, offset %d", 1518 speed / 1000, 1519 speed % 1000, 1520 data->target[id].offset 1521 ); 1522 } 1523 seq_putc(m, '\n'); 1524 } 1525 return 0; 1526 } 1527 1528 1529 1530 /* 1531 * Reset parameters and call scsi_done for data->cur_lunt. 1532 * Be careful setting SCpnt->result = DID_* before calling this function. 1533 */ 1534 static void nsp32_scsi_done(struct scsi_cmnd *SCpnt) 1535 { 1536 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 1537 unsigned int base = SCpnt->device->host->io_port; 1538 1539 scsi_dma_unmap(SCpnt); 1540 1541 /* 1542 * clear TRANSFERCONTROL_BM_START 1543 */ 1544 nsp32_write2(base, TRANSFER_CONTROL, 0); 1545 nsp32_write4(base, BM_CNT, 0); 1546 1547 /* 1548 * call scsi_done 1549 */ 1550 (*SCpnt->scsi_done)(SCpnt); 1551 1552 /* 1553 * reset parameters 1554 */ 1555 data->cur_lunt->SCpnt = NULL; 1556 data->cur_lunt = NULL; 1557 data->cur_target = NULL; 1558 data->CurrentSC = NULL; 1559 } 1560 1561 1562 /* 1563 * Bus Free Occur 1564 * 1565 * Current Phase is BUSFREE. AutoSCSI is automatically execute BUSFREE phase 1566 * with ACK reply when below condition is matched: 1567 * MsgIn 00: Command Complete. 1568 * MsgIn 02: Save Data Pointer. 1569 * MsgIn 04: Disconnect. 1570 * In other case, unexpected BUSFREE is detected. 1571 */ 1572 static int nsp32_busfree_occur(struct scsi_cmnd *SCpnt, unsigned short execph) 1573 { 1574 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 1575 unsigned int base = SCpnt->device->host->io_port; 1576 1577 nsp32_dbg(NSP32_DEBUG_BUSFREE, "enter execph=0x%x", execph); 1578 show_autophase(execph); 1579 1580 nsp32_write4(base, BM_CNT, 0); 1581 nsp32_write2(base, TRANSFER_CONTROL, 0); 1582 1583 /* 1584 * MsgIn 02: Save Data Pointer 1585 * 1586 * VALID: 1587 * Save Data Pointer is received. Adjust pointer. 1588 * 1589 * NO-VALID: 1590 * SCSI-3 says if Save Data Pointer is not received, then we restart 1591 * processing and we can't adjust any SCSI data pointer in next data 1592 * phase. 1593 */ 1594 if (execph & MSGIN_02_VALID) { 1595 nsp32_dbg(NSP32_DEBUG_BUSFREE, "MsgIn02_Valid"); 1596 1597 /* 1598 * Check sack_cnt/saved_sack_cnt, then adjust sg table if 1599 * needed. 1600 */ 1601 if (!(execph & MSGIN_00_VALID) && 1602 ((execph & DATA_IN_PHASE) || (execph & DATA_OUT_PHASE))) { 1603 unsigned int sacklen, s_sacklen; 1604 1605 /* 1606 * Read SACK count and SAVEDSACK count, then compare. 1607 */ 1608 sacklen = nsp32_read4(base, SACK_CNT ); 1609 s_sacklen = nsp32_read4(base, SAVED_SACK_CNT); 1610 1611 /* 1612 * If SAVEDSACKCNT == 0, it means SavedDataPointer is 1613 * come after data transferring. 1614 */ 1615 if (s_sacklen > 0) { 1616 /* 1617 * Comparing between sack and savedsack to 1618 * check the condition of AutoMsgIn03. 1619 * 1620 * If they are same, set msgin03 == TRUE, 1621 * COMMANDCONTROL_AUTO_MSGIN_03 is enabled at 1622 * reselection. On the other hand, if they 1623 * aren't same, set msgin03 == FALSE, and 1624 * COMMANDCONTROL_AUTO_MSGIN_03 is disabled at 1625 * reselection. 1626 */ 1627 if (sacklen != s_sacklen) { 1628 data->cur_lunt->msgin03 = FALSE; 1629 } else { 1630 data->cur_lunt->msgin03 = TRUE; 1631 } 1632 1633 nsp32_adjust_busfree(SCpnt, s_sacklen); 1634 } 1635 } 1636 1637 /* This value has not substitude with valid value yet... */ 1638 //data->cur_lunt->save_datp = data->cur_datp; 1639 } else { 1640 /* 1641 * no processing. 1642 */ 1643 } 1644 1645 if (execph & MSGIN_03_VALID) { 1646 /* MsgIn03 was valid to be processed. No need processing. */ 1647 } 1648 1649 /* 1650 * target SDTR check 1651 */ 1652 if (data->cur_target->sync_flag & SDTR_INITIATOR) { 1653 /* 1654 * SDTR negotiation pulled by the initiator has not 1655 * finished yet. Fall back to ASYNC mode. 1656 */ 1657 nsp32_set_async(data, data->cur_target); 1658 data->cur_target->sync_flag &= ~SDTR_INITIATOR; 1659 data->cur_target->sync_flag |= SDTR_DONE; 1660 } else if (data->cur_target->sync_flag & SDTR_TARGET) { 1661 /* 1662 * SDTR negotiation pulled by the target has been 1663 * negotiating. 1664 */ 1665 if (execph & (MSGIN_00_VALID | MSGIN_04_VALID)) { 1666 /* 1667 * If valid message is received, then 1668 * negotiation is succeeded. 1669 */ 1670 } else { 1671 /* 1672 * On the contrary, if unexpected bus free is 1673 * occurred, then negotiation is failed. Fall 1674 * back to ASYNC mode. 1675 */ 1676 nsp32_set_async(data, data->cur_target); 1677 } 1678 data->cur_target->sync_flag &= ~SDTR_TARGET; 1679 data->cur_target->sync_flag |= SDTR_DONE; 1680 } 1681 1682 /* 1683 * It is always ensured by SCSI standard that initiator 1684 * switches into Bus Free Phase after 1685 * receiving message 00 (Command Complete), 04 (Disconnect). 1686 * It's the reason that processing here is valid. 1687 */ 1688 if (execph & MSGIN_00_VALID) { 1689 /* MsgIn 00: Command Complete */ 1690 nsp32_dbg(NSP32_DEBUG_BUSFREE, "command complete"); 1691 1692 SCpnt->SCp.Status = nsp32_read1(base, SCSI_CSB_IN); 1693 SCpnt->SCp.Message = 0; 1694 nsp32_dbg(NSP32_DEBUG_BUSFREE, 1695 "normal end stat=0x%x resid=0x%x\n", 1696 SCpnt->SCp.Status, scsi_get_resid(SCpnt)); 1697 SCpnt->result = (DID_OK << 16) | 1698 (SCpnt->SCp.Message << 8) | 1699 (SCpnt->SCp.Status << 0); 1700 nsp32_scsi_done(SCpnt); 1701 /* All operation is done */ 1702 return TRUE; 1703 } else if (execph & MSGIN_04_VALID) { 1704 /* MsgIn 04: Disconnect */ 1705 SCpnt->SCp.Status = nsp32_read1(base, SCSI_CSB_IN); 1706 SCpnt->SCp.Message = 4; 1707 1708 nsp32_dbg(NSP32_DEBUG_BUSFREE, "disconnect"); 1709 return TRUE; 1710 } else { 1711 /* Unexpected bus free */ 1712 nsp32_msg(KERN_WARNING, "unexpected bus free occurred"); 1713 1714 /* DID_ERROR? */ 1715 //SCpnt->result = (DID_OK << 16) | (SCpnt->SCp.Message << 8) | (SCpnt->SCp.Status << 0); 1716 SCpnt->result = DID_ERROR << 16; 1717 nsp32_scsi_done(SCpnt); 1718 return TRUE; 1719 } 1720 return FALSE; 1721 } 1722 1723 1724 /* 1725 * nsp32_adjust_busfree - adjusting SG table 1726 * 1727 * Note: This driver adjust the SG table using SCSI ACK 1728 * counter instead of BMCNT counter! 1729 */ 1730 static void nsp32_adjust_busfree(struct scsi_cmnd *SCpnt, unsigned int s_sacklen) 1731 { 1732 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 1733 int old_entry = data->cur_entry; 1734 int new_entry; 1735 int sg_num = data->cur_lunt->sg_num; 1736 nsp32_sgtable *sgt = data->cur_lunt->sglun->sgt; 1737 unsigned int restlen, sentlen; 1738 u32_le len, addr; 1739 1740 nsp32_dbg(NSP32_DEBUG_SGLIST, "old resid=0x%x", scsi_get_resid(SCpnt)); 1741 1742 /* adjust saved SACK count with 4 byte start address boundary */ 1743 s_sacklen -= le32_to_cpu(sgt[old_entry].addr) & 3; 1744 1745 /* 1746 * calculate new_entry from sack count and each sgt[].len 1747 * calculate the byte which is intent to send 1748 */ 1749 sentlen = 0; 1750 for (new_entry = old_entry; new_entry < sg_num; new_entry++) { 1751 sentlen += (le32_to_cpu(sgt[new_entry].len) & ~SGTEND); 1752 if (sentlen > s_sacklen) { 1753 break; 1754 } 1755 } 1756 1757 /* all sgt is processed */ 1758 if (new_entry == sg_num) { 1759 goto last; 1760 } 1761 1762 if (sentlen == s_sacklen) { 1763 /* XXX: confirm it's ok or not */ 1764 /* In this case, it's ok because we are at 1765 * the head element of the sg. restlen is correctly 1766 * calculated. 1767 */ 1768 } 1769 1770 /* calculate the rest length for transferring */ 1771 restlen = sentlen - s_sacklen; 1772 1773 /* update adjusting current SG table entry */ 1774 len = le32_to_cpu(sgt[new_entry].len); 1775 addr = le32_to_cpu(sgt[new_entry].addr); 1776 addr += (len - restlen); 1777 sgt[new_entry].addr = cpu_to_le32(addr); 1778 sgt[new_entry].len = cpu_to_le32(restlen); 1779 1780 /* set cur_entry with new_entry */ 1781 data->cur_entry = new_entry; 1782 1783 return; 1784 1785 last: 1786 if (scsi_get_resid(SCpnt) < sentlen) { 1787 nsp32_msg(KERN_ERR, "resid underflow"); 1788 } 1789 1790 scsi_set_resid(SCpnt, scsi_get_resid(SCpnt) - sentlen); 1791 nsp32_dbg(NSP32_DEBUG_SGLIST, "new resid=0x%x", scsi_get_resid(SCpnt)); 1792 1793 /* update hostdata and lun */ 1794 1795 return; 1796 } 1797 1798 1799 /* 1800 * It's called MsgOut phase occur. 1801 * NinjaSCSI-32Bi/UDE automatically processes up to 3 messages in 1802 * message out phase. It, however, has more than 3 messages, 1803 * HBA creates the interrupt and we have to process by hand. 1804 */ 1805 static void nsp32_msgout_occur(struct scsi_cmnd *SCpnt) 1806 { 1807 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 1808 unsigned int base = SCpnt->device->host->io_port; 1809 int i; 1810 1811 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR, 1812 "enter: msgout_len: 0x%x", data->msgout_len); 1813 1814 /* 1815 * If MsgOut phase is occurred without having any 1816 * message, then No_Operation is sent (SCSI-2). 1817 */ 1818 if (data->msgout_len == 0) { 1819 nsp32_build_nop(SCpnt); 1820 } 1821 1822 /* 1823 * send messages 1824 */ 1825 for (i = 0; i < data->msgout_len; i++) { 1826 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR, 1827 "%d : 0x%x", i, data->msgoutbuf[i]); 1828 1829 /* 1830 * Check REQ is asserted. 1831 */ 1832 nsp32_wait_req(data, ASSERT); 1833 1834 if (i == (data->msgout_len - 1)) { 1835 /* 1836 * If the last message, set the AutoSCSI restart 1837 * before send back the ack message. AutoSCSI 1838 * restart automatically negate ATN signal. 1839 */ 1840 //command = (AUTO_MSGIN_00_OR_04 | AUTO_MSGIN_02); 1841 //nsp32_restart_autoscsi(SCpnt, command); 1842 nsp32_write2(base, COMMAND_CONTROL, 1843 (CLEAR_CDB_FIFO_POINTER | 1844 AUTO_COMMAND_PHASE | 1845 AUTOSCSI_RESTART | 1846 AUTO_MSGIN_00_OR_04 | 1847 AUTO_MSGIN_02 )); 1848 } 1849 /* 1850 * Write data with SACK, then wait sack is 1851 * automatically negated. 1852 */ 1853 nsp32_write1(base, SCSI_DATA_WITH_ACK, data->msgoutbuf[i]); 1854 nsp32_wait_sack(data, NEGATE); 1855 1856 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR, "bus: 0x%x\n", 1857 nsp32_read1(base, SCSI_BUS_MONITOR)); 1858 } 1859 1860 data->msgout_len = 0; 1861 1862 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR, "exit"); 1863 } 1864 1865 /* 1866 * Restart AutoSCSI 1867 * 1868 * Note: Restarting AutoSCSI needs set: 1869 * SYNC_REG, ACK_WIDTH, SGT_ADR, TRANSFER_CONTROL 1870 */ 1871 static void nsp32_restart_autoscsi(struct scsi_cmnd *SCpnt, unsigned short command) 1872 { 1873 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 1874 unsigned int base = data->BaseAddress; 1875 unsigned short transfer = 0; 1876 1877 nsp32_dbg(NSP32_DEBUG_RESTART, "enter"); 1878 1879 if (data->cur_target == NULL || data->cur_lunt == NULL) { 1880 nsp32_msg(KERN_ERR, "Target or Lun is invalid"); 1881 } 1882 1883 /* 1884 * set SYNC_REG 1885 * Don't set BM_START_ADR before setting this register. 1886 */ 1887 nsp32_write1(base, SYNC_REG, data->cur_target->syncreg); 1888 1889 /* 1890 * set ACKWIDTH 1891 */ 1892 nsp32_write1(base, ACK_WIDTH, data->cur_target->ackwidth); 1893 1894 /* 1895 * set SREQ hazard killer sampling rate 1896 */ 1897 nsp32_write1(base, SREQ_SMPL_RATE, data->cur_target->sample_reg); 1898 1899 /* 1900 * set SGT ADDR (physical address) 1901 */ 1902 nsp32_write4(base, SGT_ADR, data->cur_lunt->sglun_paddr); 1903 1904 /* 1905 * set TRANSFER CONTROL REG 1906 */ 1907 transfer = 0; 1908 transfer |= (TRANSFER_GO | ALL_COUNTER_CLR); 1909 if (data->trans_method & NSP32_TRANSFER_BUSMASTER) { 1910 if (scsi_bufflen(SCpnt) > 0) { 1911 transfer |= BM_START; 1912 } 1913 } else if (data->trans_method & NSP32_TRANSFER_MMIO) { 1914 transfer |= CB_MMIO_MODE; 1915 } else if (data->trans_method & NSP32_TRANSFER_PIO) { 1916 transfer |= CB_IO_MODE; 1917 } 1918 nsp32_write2(base, TRANSFER_CONTROL, transfer); 1919 1920 /* 1921 * restart AutoSCSI 1922 * 1923 * TODO: COMMANDCONTROL_AUTO_COMMAND_PHASE is needed ? 1924 */ 1925 command |= (CLEAR_CDB_FIFO_POINTER | 1926 AUTO_COMMAND_PHASE | 1927 AUTOSCSI_RESTART ); 1928 nsp32_write2(base, COMMAND_CONTROL, command); 1929 1930 nsp32_dbg(NSP32_DEBUG_RESTART, "exit"); 1931 } 1932 1933 1934 /* 1935 * cannot run automatically message in occur 1936 */ 1937 static void nsp32_msgin_occur(struct scsi_cmnd *SCpnt, 1938 unsigned long irq_status, 1939 unsigned short execph) 1940 { 1941 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 1942 unsigned int base = SCpnt->device->host->io_port; 1943 unsigned char msg; 1944 unsigned char msgtype; 1945 unsigned char newlun; 1946 unsigned short command = 0; 1947 int msgclear = TRUE; 1948 long new_sgtp; 1949 int ret; 1950 1951 /* 1952 * read first message 1953 * Use SCSIDATA_W_ACK instead of SCSIDATAIN, because the procedure 1954 * of Message-In have to be processed before sending back SCSI ACK. 1955 */ 1956 msg = nsp32_read1(base, SCSI_DATA_IN); 1957 data->msginbuf[(unsigned char)data->msgin_len] = msg; 1958 msgtype = data->msginbuf[0]; 1959 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, 1960 "enter: msglen: 0x%x msgin: 0x%x msgtype: 0x%x", 1961 data->msgin_len, msg, msgtype); 1962 1963 /* 1964 * TODO: We need checking whether bus phase is message in? 1965 */ 1966 1967 /* 1968 * assert SCSI ACK 1969 */ 1970 nsp32_sack_assert(data); 1971 1972 /* 1973 * processing IDENTIFY 1974 */ 1975 if (msgtype & 0x80) { 1976 if (!(irq_status & IRQSTATUS_RESELECT_OCCUER)) { 1977 /* Invalid (non reselect) phase */ 1978 goto reject; 1979 } 1980 1981 newlun = msgtype & 0x1f; /* TODO: SPI-3 compliant? */ 1982 ret = nsp32_reselection(SCpnt, newlun); 1983 if (ret == TRUE) { 1984 goto restart; 1985 } else { 1986 goto reject; 1987 } 1988 } 1989 1990 /* 1991 * processing messages except for IDENTIFY 1992 * 1993 * TODO: Messages are all SCSI-2 terminology. SCSI-3 compliance is TODO. 1994 */ 1995 switch (msgtype) { 1996 /* 1997 * 1-byte message 1998 */ 1999 case COMMAND_COMPLETE: 2000 case DISCONNECT: 2001 /* 2002 * These messages should not be occurred. 2003 * They should be processed on AutoSCSI sequencer. 2004 */ 2005 nsp32_msg(KERN_WARNING, 2006 "unexpected message of AutoSCSI MsgIn: 0x%x", msg); 2007 break; 2008 2009 case RESTORE_POINTERS: 2010 /* 2011 * AutoMsgIn03 is disabled, and HBA gets this message. 2012 */ 2013 2014 if ((execph & DATA_IN_PHASE) || (execph & DATA_OUT_PHASE)) { 2015 unsigned int s_sacklen; 2016 2017 s_sacklen = nsp32_read4(base, SAVED_SACK_CNT); 2018 if ((execph & MSGIN_02_VALID) && (s_sacklen > 0)) { 2019 nsp32_adjust_busfree(SCpnt, s_sacklen); 2020 } else { 2021 /* No need to rewrite SGT */ 2022 } 2023 } 2024 data->cur_lunt->msgin03 = FALSE; 2025 2026 /* Update with the new value */ 2027 2028 /* reset SACK/SavedACK counter (or ALL clear?) */ 2029 nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK); 2030 2031 /* 2032 * set new sg pointer 2033 */ 2034 new_sgtp = data->cur_lunt->sglun_paddr + 2035 (data->cur_lunt->cur_entry * sizeof(nsp32_sgtable)); 2036 nsp32_write4(base, SGT_ADR, new_sgtp); 2037 2038 break; 2039 2040 case SAVE_POINTERS: 2041 /* 2042 * These messages should not be occurred. 2043 * They should be processed on AutoSCSI sequencer. 2044 */ 2045 nsp32_msg (KERN_WARNING, 2046 "unexpected message of AutoSCSI MsgIn: SAVE_POINTERS"); 2047 2048 break; 2049 2050 case MESSAGE_REJECT: 2051 /* If previous message_out is sending SDTR, and get 2052 message_reject from target, SDTR negotiation is failed */ 2053 if (data->cur_target->sync_flag & 2054 (SDTR_INITIATOR | SDTR_TARGET)) { 2055 /* 2056 * Current target is negotiating SDTR, but it's 2057 * failed. Fall back to async transfer mode, and set 2058 * SDTR_DONE. 2059 */ 2060 nsp32_set_async(data, data->cur_target); 2061 data->cur_target->sync_flag &= ~SDTR_INITIATOR; 2062 data->cur_target->sync_flag |= SDTR_DONE; 2063 2064 } 2065 break; 2066 2067 case LINKED_CMD_COMPLETE: 2068 case LINKED_FLG_CMD_COMPLETE: 2069 /* queue tag is not supported currently */ 2070 nsp32_msg (KERN_WARNING, 2071 "unsupported message: 0x%x", msgtype); 2072 break; 2073 2074 case INITIATE_RECOVERY: 2075 /* staring ECA (Extended Contingent Allegiance) state. */ 2076 /* This message is declined in SPI2 or later. */ 2077 2078 goto reject; 2079 2080 /* 2081 * 2-byte message 2082 */ 2083 case SIMPLE_QUEUE_TAG: 2084 case 0x23: 2085 /* 2086 * 0x23: Ignore_Wide_Residue is not declared in scsi.h. 2087 * No support is needed. 2088 */ 2089 if (data->msgin_len >= 1) { 2090 goto reject; 2091 } 2092 2093 /* current position is 1-byte of 2 byte */ 2094 msgclear = FALSE; 2095 2096 break; 2097 2098 /* 2099 * extended message 2100 */ 2101 case EXTENDED_MESSAGE: 2102 if (data->msgin_len < 1) { 2103 /* 2104 * Current position does not reach 2-byte 2105 * (2-byte is extended message length). 2106 */ 2107 msgclear = FALSE; 2108 break; 2109 } 2110 2111 if ((data->msginbuf[1] + 1) > data->msgin_len) { 2112 /* 2113 * Current extended message has msginbuf[1] + 2 2114 * (msgin_len starts counting from 0, so buf[1] + 1). 2115 * If current message position is not finished, 2116 * continue receiving message. 2117 */ 2118 msgclear = FALSE; 2119 break; 2120 } 2121 2122 /* 2123 * Reach here means regular length of each type of 2124 * extended messages. 2125 */ 2126 switch (data->msginbuf[2]) { 2127 case EXTENDED_MODIFY_DATA_POINTER: 2128 /* TODO */ 2129 goto reject; /* not implemented yet */ 2130 break; 2131 2132 case EXTENDED_SDTR: 2133 /* 2134 * Exchange this message between initiator and target. 2135 */ 2136 if (data->msgin_len != EXTENDED_SDTR_LEN + 1) { 2137 /* 2138 * received inappropriate message. 2139 */ 2140 goto reject; 2141 break; 2142 } 2143 2144 nsp32_analyze_sdtr(SCpnt); 2145 2146 break; 2147 2148 case EXTENDED_EXTENDED_IDENTIFY: 2149 /* SCSI-I only, not supported. */ 2150 goto reject; /* not implemented yet */ 2151 2152 break; 2153 2154 case EXTENDED_WDTR: 2155 goto reject; /* not implemented yet */ 2156 2157 break; 2158 2159 default: 2160 goto reject; 2161 } 2162 break; 2163 2164 default: 2165 goto reject; 2166 } 2167 2168 restart: 2169 if (msgclear == TRUE) { 2170 data->msgin_len = 0; 2171 2172 /* 2173 * If restarting AutoSCSI, but there are some message to out 2174 * (msgout_len > 0), set AutoATN, and set SCSIMSGOUT as 0 2175 * (MV_VALID = 0). When commandcontrol is written with 2176 * AutoSCSI restart, at the same time MsgOutOccur should be 2177 * happened (however, such situation is really possible...?). 2178 */ 2179 if (data->msgout_len > 0) { 2180 nsp32_write4(base, SCSI_MSG_OUT, 0); 2181 command |= AUTO_ATN; 2182 } 2183 2184 /* 2185 * restart AutoSCSI 2186 * If it's failed, COMMANDCONTROL_AUTO_COMMAND_PHASE is needed. 2187 */ 2188 command |= (AUTO_MSGIN_00_OR_04 | AUTO_MSGIN_02); 2189 2190 /* 2191 * If current msgin03 is TRUE, then flag on. 2192 */ 2193 if (data->cur_lunt->msgin03 == TRUE) { 2194 command |= AUTO_MSGIN_03; 2195 } 2196 data->cur_lunt->msgin03 = FALSE; 2197 } else { 2198 data->msgin_len++; 2199 } 2200 2201 /* 2202 * restart AutoSCSI 2203 */ 2204 nsp32_restart_autoscsi(SCpnt, command); 2205 2206 /* 2207 * wait SCSI REQ negate for REQ-ACK handshake 2208 */ 2209 nsp32_wait_req(data, NEGATE); 2210 2211 /* 2212 * negate SCSI ACK 2213 */ 2214 nsp32_sack_negate(data); 2215 2216 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "exit"); 2217 2218 return; 2219 2220 reject: 2221 nsp32_msg(KERN_WARNING, 2222 "invalid or unsupported MessageIn, rejected. " 2223 "current msg: 0x%x (len: 0x%x), processing msg: 0x%x", 2224 msg, data->msgin_len, msgtype); 2225 nsp32_build_reject(SCpnt); 2226 data->msgin_len = 0; 2227 2228 goto restart; 2229 } 2230 2231 /* 2232 * 2233 */ 2234 static void nsp32_analyze_sdtr(struct scsi_cmnd *SCpnt) 2235 { 2236 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 2237 nsp32_target *target = data->cur_target; 2238 unsigned char get_period = data->msginbuf[3]; 2239 unsigned char get_offset = data->msginbuf[4]; 2240 int entry; 2241 2242 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "enter"); 2243 2244 /* 2245 * If this inititor sent the SDTR message, then target responds SDTR, 2246 * initiator SYNCREG, ACKWIDTH from SDTR parameter. 2247 * Messages are not appropriate, then send back reject message. 2248 * If initiator did not send the SDTR, but target sends SDTR, 2249 * initiator calculator the appropriate parameter and send back SDTR. 2250 */ 2251 if (target->sync_flag & SDTR_INITIATOR) { 2252 /* 2253 * Initiator sent SDTR, the target responds and 2254 * send back negotiation SDTR. 2255 */ 2256 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "target responds SDTR"); 2257 2258 target->sync_flag &= ~SDTR_INITIATOR; 2259 target->sync_flag |= SDTR_DONE; 2260 2261 /* 2262 * offset: 2263 */ 2264 if (get_offset > SYNC_OFFSET) { 2265 /* 2266 * Negotiation is failed, the target send back 2267 * unexpected offset value. 2268 */ 2269 goto reject; 2270 } 2271 2272 if (get_offset == ASYNC_OFFSET) { 2273 /* 2274 * Negotiation is succeeded, the target want 2275 * to fall back into asynchronous transfer mode. 2276 */ 2277 goto async; 2278 } 2279 2280 /* 2281 * period: 2282 * Check whether sync period is too short. If too short, 2283 * fall back to async mode. If it's ok, then investigate 2284 * the received sync period. If sync period is acceptable 2285 * between sync table start_period and end_period, then 2286 * set this I_T nexus as sent offset and period. 2287 * If it's not acceptable, send back reject and fall back 2288 * to async mode. 2289 */ 2290 if (get_period < data->synct[0].period_num) { 2291 /* 2292 * Negotiation is failed, the target send back 2293 * unexpected period value. 2294 */ 2295 goto reject; 2296 } 2297 2298 entry = nsp32_search_period_entry(data, target, get_period); 2299 2300 if (entry < 0) { 2301 /* 2302 * Target want to use long period which is not 2303 * acceptable NinjaSCSI-32Bi/UDE. 2304 */ 2305 goto reject; 2306 } 2307 2308 /* 2309 * Set new sync table and offset in this I_T nexus. 2310 */ 2311 nsp32_set_sync_entry(data, target, entry, get_offset); 2312 } else { 2313 /* Target send SDTR to initiator. */ 2314 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "target send SDTR"); 2315 2316 target->sync_flag |= SDTR_INITIATOR; 2317 2318 /* offset: */ 2319 if (get_offset > SYNC_OFFSET) { 2320 /* send back as SYNC_OFFSET */ 2321 get_offset = SYNC_OFFSET; 2322 } 2323 2324 /* period: */ 2325 if (get_period < data->synct[0].period_num) { 2326 get_period = data->synct[0].period_num; 2327 } 2328 2329 entry = nsp32_search_period_entry(data, target, get_period); 2330 2331 if (get_offset == ASYNC_OFFSET || entry < 0) { 2332 nsp32_set_async(data, target); 2333 nsp32_build_sdtr(SCpnt, 0, ASYNC_OFFSET); 2334 } else { 2335 nsp32_set_sync_entry(data, target, entry, get_offset); 2336 nsp32_build_sdtr(SCpnt, get_period, get_offset); 2337 } 2338 } 2339 2340 target->period = get_period; 2341 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "exit"); 2342 return; 2343 2344 reject: 2345 /* 2346 * If the current message is unacceptable, send back to the target 2347 * with reject message. 2348 */ 2349 nsp32_build_reject(SCpnt); 2350 2351 async: 2352 nsp32_set_async(data, target); /* set as ASYNC transfer mode */ 2353 2354 target->period = 0; 2355 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "exit: set async"); 2356 return; 2357 } 2358 2359 2360 /* 2361 * Search config entry number matched in sync_table from given 2362 * target and speed period value. If failed to search, return negative value. 2363 */ 2364 static int nsp32_search_period_entry(nsp32_hw_data *data, 2365 nsp32_target *target, 2366 unsigned char period) 2367 { 2368 int i; 2369 2370 if (target->limit_entry >= data->syncnum) { 2371 nsp32_msg(KERN_ERR, "limit_entry exceeds syncnum!"); 2372 target->limit_entry = 0; 2373 } 2374 2375 for (i = target->limit_entry; i < data->syncnum; i++) { 2376 if (period >= data->synct[i].start_period && 2377 period <= data->synct[i].end_period) { 2378 break; 2379 } 2380 } 2381 2382 /* 2383 * Check given period value is over the sync_table value. 2384 * If so, return max value. 2385 */ 2386 if (i == data->syncnum) { 2387 i = -1; 2388 } 2389 2390 return i; 2391 } 2392 2393 2394 /* 2395 * target <-> initiator use ASYNC transfer 2396 */ 2397 static void nsp32_set_async(nsp32_hw_data *data, nsp32_target *target) 2398 { 2399 unsigned char period = data->synct[target->limit_entry].period_num; 2400 2401 target->offset = ASYNC_OFFSET; 2402 target->period = 0; 2403 target->syncreg = TO_SYNCREG(period, ASYNC_OFFSET); 2404 target->ackwidth = 0; 2405 target->sample_reg = 0; 2406 2407 nsp32_dbg(NSP32_DEBUG_SYNC, "set async"); 2408 } 2409 2410 2411 /* 2412 * target <-> initiator use maximum SYNC transfer 2413 */ 2414 static void nsp32_set_max_sync(nsp32_hw_data *data, 2415 nsp32_target *target, 2416 unsigned char *period, 2417 unsigned char *offset) 2418 { 2419 unsigned char period_num, ackwidth; 2420 2421 period_num = data->synct[target->limit_entry].period_num; 2422 *period = data->synct[target->limit_entry].start_period; 2423 ackwidth = data->synct[target->limit_entry].ackwidth; 2424 *offset = SYNC_OFFSET; 2425 2426 target->syncreg = TO_SYNCREG(period_num, *offset); 2427 target->ackwidth = ackwidth; 2428 target->offset = *offset; 2429 target->sample_reg = 0; /* disable SREQ sampling */ 2430 } 2431 2432 2433 /* 2434 * target <-> initiator use entry number speed 2435 */ 2436 static void nsp32_set_sync_entry(nsp32_hw_data *data, 2437 nsp32_target *target, 2438 int entry, 2439 unsigned char offset) 2440 { 2441 unsigned char period, ackwidth, sample_rate; 2442 2443 period = data->synct[entry].period_num; 2444 ackwidth = data->synct[entry].ackwidth; 2445 sample_rate = data->synct[entry].sample_rate; 2446 2447 target->syncreg = TO_SYNCREG(period, offset); 2448 target->ackwidth = ackwidth; 2449 target->offset = offset; 2450 target->sample_reg = sample_rate | SAMPLING_ENABLE; 2451 2452 nsp32_dbg(NSP32_DEBUG_SYNC, "set sync"); 2453 } 2454 2455 2456 /* 2457 * It waits until SCSI REQ becomes assertion or negation state. 2458 * 2459 * Note: If nsp32_msgin_occur is called, we asserts SCSI ACK. Then 2460 * connected target responds SCSI REQ negation. We have to wait 2461 * SCSI REQ becomes negation in order to negate SCSI ACK signal for 2462 * REQ-ACK handshake. 2463 */ 2464 static void nsp32_wait_req(nsp32_hw_data *data, int state) 2465 { 2466 unsigned int base = data->BaseAddress; 2467 int wait_time = 0; 2468 unsigned char bus, req_bit; 2469 2470 if (!((state == ASSERT) || (state == NEGATE))) { 2471 nsp32_msg(KERN_ERR, "unknown state designation"); 2472 } 2473 /* REQ is BIT(5) */ 2474 req_bit = (state == ASSERT ? BUSMON_REQ : 0); 2475 2476 do { 2477 bus = nsp32_read1(base, SCSI_BUS_MONITOR); 2478 if ((bus & BUSMON_REQ) == req_bit) { 2479 nsp32_dbg(NSP32_DEBUG_WAIT, 2480 "wait_time: %d", wait_time); 2481 return; 2482 } 2483 udelay(1); 2484 wait_time++; 2485 } while (wait_time < REQSACK_TIMEOUT_TIME); 2486 2487 nsp32_msg(KERN_WARNING, "wait REQ timeout, req_bit: 0x%x", req_bit); 2488 } 2489 2490 /* 2491 * It waits until SCSI SACK becomes assertion or negation state. 2492 */ 2493 static void nsp32_wait_sack(nsp32_hw_data *data, int state) 2494 { 2495 unsigned int base = data->BaseAddress; 2496 int wait_time = 0; 2497 unsigned char bus, ack_bit; 2498 2499 if (!((state == ASSERT) || (state == NEGATE))) { 2500 nsp32_msg(KERN_ERR, "unknown state designation"); 2501 } 2502 /* ACK is BIT(4) */ 2503 ack_bit = (state == ASSERT ? BUSMON_ACK : 0); 2504 2505 do { 2506 bus = nsp32_read1(base, SCSI_BUS_MONITOR); 2507 if ((bus & BUSMON_ACK) == ack_bit) { 2508 nsp32_dbg(NSP32_DEBUG_WAIT, 2509 "wait_time: %d", wait_time); 2510 return; 2511 } 2512 udelay(1); 2513 wait_time++; 2514 } while (wait_time < REQSACK_TIMEOUT_TIME); 2515 2516 nsp32_msg(KERN_WARNING, "wait SACK timeout, ack_bit: 0x%x", ack_bit); 2517 } 2518 2519 /* 2520 * assert SCSI ACK 2521 * 2522 * Note: SCSI ACK assertion needs with ACKENB=1, AUTODIRECTION=1. 2523 */ 2524 static void nsp32_sack_assert(nsp32_hw_data *data) 2525 { 2526 unsigned int base = data->BaseAddress; 2527 unsigned char busctrl; 2528 2529 busctrl = nsp32_read1(base, SCSI_BUS_CONTROL); 2530 busctrl |= (BUSCTL_ACK | AUTODIRECTION | ACKENB); 2531 nsp32_write1(base, SCSI_BUS_CONTROL, busctrl); 2532 } 2533 2534 /* 2535 * negate SCSI ACK 2536 */ 2537 static void nsp32_sack_negate(nsp32_hw_data *data) 2538 { 2539 unsigned int base = data->BaseAddress; 2540 unsigned char busctrl; 2541 2542 busctrl = nsp32_read1(base, SCSI_BUS_CONTROL); 2543 busctrl &= ~BUSCTL_ACK; 2544 nsp32_write1(base, SCSI_BUS_CONTROL, busctrl); 2545 } 2546 2547 2548 2549 /* 2550 * Note: n_io_port is defined as 0x7f because I/O register port is 2551 * assigned as: 2552 * 0x800-0x8ff: memory mapped I/O port 2553 * 0x900-0xbff: (map same 0x800-0x8ff I/O port image repeatedly) 2554 * 0xc00-0xfff: CardBus status registers 2555 */ 2556 static int nsp32_detect(struct pci_dev *pdev) 2557 { 2558 struct Scsi_Host *host; /* registered host structure */ 2559 struct resource *res; 2560 nsp32_hw_data *data; 2561 int ret; 2562 int i, j; 2563 2564 nsp32_dbg(NSP32_DEBUG_REGISTER, "enter"); 2565 2566 /* 2567 * register this HBA as SCSI device 2568 */ 2569 host = scsi_host_alloc(&nsp32_template, sizeof(nsp32_hw_data)); 2570 if (host == NULL) { 2571 nsp32_msg (KERN_ERR, "failed to scsi register"); 2572 goto err; 2573 } 2574 2575 /* 2576 * set nsp32_hw_data 2577 */ 2578 data = (nsp32_hw_data *)host->hostdata; 2579 2580 memcpy(data, &nsp32_data_base, sizeof(nsp32_hw_data)); 2581 2582 host->irq = data->IrqNumber; 2583 host->io_port = data->BaseAddress; 2584 host->unique_id = data->BaseAddress; 2585 host->n_io_port = data->NumAddress; 2586 host->base = (unsigned long)data->MmioAddress; 2587 2588 data->Host = host; 2589 spin_lock_init(&(data->Lock)); 2590 2591 data->cur_lunt = NULL; 2592 data->cur_target = NULL; 2593 2594 /* 2595 * Bus master transfer mode is supported currently. 2596 */ 2597 data->trans_method = NSP32_TRANSFER_BUSMASTER; 2598 2599 /* 2600 * Set clock div, CLOCK_4 (HBA has own external clock, and 2601 * dividing * 100ns/4). 2602 * Currently CLOCK_4 has only tested, not for CLOCK_2/PCICLK yet. 2603 */ 2604 data->clock = CLOCK_4; 2605 2606 /* 2607 * Select appropriate nsp32_sync_table and set I_CLOCKDIV. 2608 */ 2609 switch (data->clock) { 2610 case CLOCK_4: 2611 /* If data->clock is CLOCK_4, then select 40M sync table. */ 2612 data->synct = nsp32_sync_table_40M; 2613 data->syncnum = ARRAY_SIZE(nsp32_sync_table_40M); 2614 break; 2615 case CLOCK_2: 2616 /* If data->clock is CLOCK_2, then select 20M sync table. */ 2617 data->synct = nsp32_sync_table_20M; 2618 data->syncnum = ARRAY_SIZE(nsp32_sync_table_20M); 2619 break; 2620 case PCICLK: 2621 /* If data->clock is PCICLK, then select pci sync table. */ 2622 data->synct = nsp32_sync_table_pci; 2623 data->syncnum = ARRAY_SIZE(nsp32_sync_table_pci); 2624 break; 2625 default: 2626 nsp32_msg(KERN_WARNING, 2627 "Invalid clock div is selected, set CLOCK_4."); 2628 /* Use default value CLOCK_4 */ 2629 data->clock = CLOCK_4; 2630 data->synct = nsp32_sync_table_40M; 2631 data->syncnum = ARRAY_SIZE(nsp32_sync_table_40M); 2632 } 2633 2634 /* 2635 * setup nsp32_lunt 2636 */ 2637 2638 /* 2639 * setup DMA 2640 */ 2641 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)) != 0) { 2642 nsp32_msg (KERN_ERR, "failed to set PCI DMA mask"); 2643 goto scsi_unregister; 2644 } 2645 2646 /* 2647 * allocate autoparam DMA resource. 2648 */ 2649 data->autoparam = dma_alloc_coherent(&pdev->dev, 2650 sizeof(nsp32_autoparam), &(data->auto_paddr), 2651 GFP_KERNEL); 2652 if (data->autoparam == NULL) { 2653 nsp32_msg(KERN_ERR, "failed to allocate DMA memory"); 2654 goto scsi_unregister; 2655 } 2656 2657 /* 2658 * allocate scatter-gather DMA resource. 2659 */ 2660 data->sg_list = dma_alloc_coherent(&pdev->dev, NSP32_SG_TABLE_SIZE, 2661 &data->sg_paddr, GFP_KERNEL); 2662 if (data->sg_list == NULL) { 2663 nsp32_msg(KERN_ERR, "failed to allocate DMA memory"); 2664 goto free_autoparam; 2665 } 2666 2667 for (i = 0; i < ARRAY_SIZE(data->lunt); i++) { 2668 for (j = 0; j < ARRAY_SIZE(data->lunt[0]); j++) { 2669 int offset = i * ARRAY_SIZE(data->lunt[0]) + j; 2670 nsp32_lunt tmp = { 2671 .SCpnt = NULL, 2672 .save_datp = 0, 2673 .msgin03 = FALSE, 2674 .sg_num = 0, 2675 .cur_entry = 0, 2676 .sglun = &(data->sg_list[offset]), 2677 .sglun_paddr = data->sg_paddr + (offset * sizeof(nsp32_sglun)), 2678 }; 2679 2680 data->lunt[i][j] = tmp; 2681 } 2682 } 2683 2684 /* 2685 * setup target 2686 */ 2687 for (i = 0; i < ARRAY_SIZE(data->target); i++) { 2688 nsp32_target *target = &(data->target[i]); 2689 2690 target->limit_entry = 0; 2691 target->sync_flag = 0; 2692 nsp32_set_async(data, target); 2693 } 2694 2695 /* 2696 * EEPROM check 2697 */ 2698 ret = nsp32_getprom_param(data); 2699 if (ret == FALSE) { 2700 data->resettime = 3; /* default 3 */ 2701 } 2702 2703 /* 2704 * setup HBA 2705 */ 2706 nsp32hw_init(data); 2707 2708 snprintf(data->info_str, sizeof(data->info_str), 2709 "NinjaSCSI-32Bi/UDE: irq %d, io 0x%lx+0x%x", 2710 host->irq, host->io_port, host->n_io_port); 2711 2712 /* 2713 * SCSI bus reset 2714 * 2715 * Note: It's important to reset SCSI bus in initialization phase. 2716 * NinjaSCSI-32Bi/UDE HBA EEPROM seems to exchange SDTR when 2717 * system is coming up, so SCSI devices connected to HBA is set as 2718 * un-asynchronous mode. It brings the merit that this HBA is 2719 * ready to start synchronous transfer without any preparation, 2720 * but we are difficult to control transfer speed. In addition, 2721 * it prevents device transfer speed from effecting EEPROM start-up 2722 * SDTR. NinjaSCSI-32Bi/UDE has the feature if EEPROM is set as 2723 * Auto Mode, then FAST-10M is selected when SCSI devices are 2724 * connected same or more than 4 devices. It should be avoided 2725 * depending on this specification. Thus, resetting the SCSI bus 2726 * restores all connected SCSI devices to asynchronous mode, then 2727 * this driver set SDTR safely later, and we can control all SCSI 2728 * device transfer mode. 2729 */ 2730 nsp32_do_bus_reset(data); 2731 2732 ret = request_irq(host->irq, do_nsp32_isr, IRQF_SHARED, "nsp32", data); 2733 if (ret < 0) { 2734 nsp32_msg(KERN_ERR, "Unable to allocate IRQ for NinjaSCSI32 " 2735 "SCSI PCI controller. Interrupt: %d", host->irq); 2736 goto free_sg_list; 2737 } 2738 2739 /* 2740 * PCI IO register 2741 */ 2742 res = request_region(host->io_port, host->n_io_port, "nsp32"); 2743 if (res == NULL) { 2744 nsp32_msg(KERN_ERR, 2745 "I/O region 0x%x+0x%x is already used", 2746 data->BaseAddress, data->NumAddress); 2747 goto free_irq; 2748 } 2749 2750 ret = scsi_add_host(host, &pdev->dev); 2751 if (ret) { 2752 nsp32_msg(KERN_ERR, "failed to add scsi host"); 2753 goto free_region; 2754 } 2755 scsi_scan_host(host); 2756 pci_set_drvdata(pdev, host); 2757 return 0; 2758 2759 free_region: 2760 release_region(host->io_port, host->n_io_port); 2761 2762 free_irq: 2763 free_irq(host->irq, data); 2764 2765 free_sg_list: 2766 dma_free_coherent(&pdev->dev, NSP32_SG_TABLE_SIZE, 2767 data->sg_list, data->sg_paddr); 2768 2769 free_autoparam: 2770 dma_free_coherent(&pdev->dev, sizeof(nsp32_autoparam), 2771 data->autoparam, data->auto_paddr); 2772 2773 scsi_unregister: 2774 scsi_host_put(host); 2775 2776 err: 2777 return 1; 2778 } 2779 2780 static int nsp32_release(struct Scsi_Host *host) 2781 { 2782 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata; 2783 2784 if (data->autoparam) { 2785 dma_free_coherent(&data->Pci->dev, sizeof(nsp32_autoparam), 2786 data->autoparam, data->auto_paddr); 2787 } 2788 2789 if (data->sg_list) { 2790 dma_free_coherent(&data->Pci->dev, NSP32_SG_TABLE_SIZE, 2791 data->sg_list, data->sg_paddr); 2792 } 2793 2794 if (host->irq) { 2795 free_irq(host->irq, data); 2796 } 2797 2798 if (host->io_port && host->n_io_port) { 2799 release_region(host->io_port, host->n_io_port); 2800 } 2801 2802 if (data->MmioAddress) { 2803 iounmap(data->MmioAddress); 2804 } 2805 2806 return 0; 2807 } 2808 2809 static const char *nsp32_info(struct Scsi_Host *shpnt) 2810 { 2811 nsp32_hw_data *data = (nsp32_hw_data *)shpnt->hostdata; 2812 2813 return data->info_str; 2814 } 2815 2816 2817 /**************************************************************************** 2818 * error handler 2819 */ 2820 static int nsp32_eh_abort(struct scsi_cmnd *SCpnt) 2821 { 2822 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 2823 unsigned int base = SCpnt->device->host->io_port; 2824 2825 nsp32_msg(KERN_WARNING, "abort"); 2826 2827 if (data->cur_lunt->SCpnt == NULL) { 2828 nsp32_dbg(NSP32_DEBUG_BUSRESET, "abort failed"); 2829 return FAILED; 2830 } 2831 2832 if (data->cur_target->sync_flag & (SDTR_INITIATOR | SDTR_TARGET)) { 2833 /* reset SDTR negotiation */ 2834 data->cur_target->sync_flag = 0; 2835 nsp32_set_async(data, data->cur_target); 2836 } 2837 2838 nsp32_write2(base, TRANSFER_CONTROL, 0); 2839 nsp32_write2(base, BM_CNT, 0); 2840 2841 SCpnt->result = DID_ABORT << 16; 2842 nsp32_scsi_done(SCpnt); 2843 2844 nsp32_dbg(NSP32_DEBUG_BUSRESET, "abort success"); 2845 return SUCCESS; 2846 } 2847 2848 static void nsp32_do_bus_reset(nsp32_hw_data *data) 2849 { 2850 unsigned int base = data->BaseAddress; 2851 int i; 2852 unsigned short __maybe_unused intrdat; 2853 2854 nsp32_dbg(NSP32_DEBUG_BUSRESET, "in"); 2855 2856 /* 2857 * stop all transfer 2858 * clear TRANSFERCONTROL_BM_START 2859 * clear counter 2860 */ 2861 nsp32_write2(base, TRANSFER_CONTROL, 0); 2862 nsp32_write4(base, BM_CNT, 0); 2863 nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK); 2864 2865 /* 2866 * fall back to asynchronous transfer mode 2867 * initialize SDTR negotiation flag 2868 */ 2869 for (i = 0; i < ARRAY_SIZE(data->target); i++) { 2870 nsp32_target *target = &data->target[i]; 2871 2872 target->sync_flag = 0; 2873 nsp32_set_async(data, target); 2874 } 2875 2876 /* 2877 * reset SCSI bus 2878 */ 2879 nsp32_write1(base, SCSI_BUS_CONTROL, BUSCTL_RST); 2880 mdelay(RESET_HOLD_TIME / 1000); 2881 nsp32_write1(base, SCSI_BUS_CONTROL, 0); 2882 for(i = 0; i < 5; i++) { 2883 intrdat = nsp32_read2(base, IRQ_STATUS); /* dummy read */ 2884 nsp32_dbg(NSP32_DEBUG_BUSRESET, "irq:1: 0x%x", intrdat); 2885 } 2886 2887 data->CurrentSC = NULL; 2888 } 2889 2890 static int nsp32_eh_host_reset(struct scsi_cmnd *SCpnt) 2891 { 2892 struct Scsi_Host *host = SCpnt->device->host; 2893 unsigned int base = SCpnt->device->host->io_port; 2894 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata; 2895 2896 nsp32_msg(KERN_INFO, "Host Reset"); 2897 nsp32_dbg(NSP32_DEBUG_BUSRESET, "SCpnt=0x%x", SCpnt); 2898 2899 spin_lock_irq(SCpnt->device->host->host_lock); 2900 2901 nsp32hw_init(data); 2902 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK); 2903 nsp32_do_bus_reset(data); 2904 nsp32_write2(base, IRQ_CONTROL, 0); 2905 2906 spin_unlock_irq(SCpnt->device->host->host_lock); 2907 return SUCCESS; /* Host reset is succeeded at any time. */ 2908 } 2909 2910 2911 /************************************************************************** 2912 * EEPROM handler 2913 */ 2914 2915 /* 2916 * getting EEPROM parameter 2917 */ 2918 static int nsp32_getprom_param(nsp32_hw_data *data) 2919 { 2920 int vendor = data->pci_devid->vendor; 2921 int device = data->pci_devid->device; 2922 int ret, i; 2923 int __maybe_unused val; 2924 2925 /* 2926 * EEPROM checking. 2927 */ 2928 ret = nsp32_prom_read(data, 0x7e); 2929 if (ret != 0x55) { 2930 nsp32_msg(KERN_INFO, "No EEPROM detected: 0x%x", ret); 2931 return FALSE; 2932 } 2933 ret = nsp32_prom_read(data, 0x7f); 2934 if (ret != 0xaa) { 2935 nsp32_msg(KERN_INFO, "Invalid number: 0x%x", ret); 2936 return FALSE; 2937 } 2938 2939 /* 2940 * check EEPROM type 2941 */ 2942 if (vendor == PCI_VENDOR_ID_WORKBIT && 2943 device == PCI_DEVICE_ID_WORKBIT_STANDARD) { 2944 ret = nsp32_getprom_c16(data); 2945 } else if (vendor == PCI_VENDOR_ID_WORKBIT && 2946 device == PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC) { 2947 ret = nsp32_getprom_at24(data); 2948 } else if (vendor == PCI_VENDOR_ID_WORKBIT && 2949 device == PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO ) { 2950 ret = nsp32_getprom_at24(data); 2951 } else { 2952 nsp32_msg(KERN_WARNING, "Unknown EEPROM"); 2953 ret = FALSE; 2954 } 2955 2956 /* for debug : SPROM data full checking */ 2957 for (i = 0; i <= 0x1f; i++) { 2958 val = nsp32_prom_read(data, i); 2959 nsp32_dbg(NSP32_DEBUG_EEPROM, 2960 "rom address 0x%x : 0x%x", i, val); 2961 } 2962 2963 return ret; 2964 } 2965 2966 2967 /* 2968 * AT24C01A (Logitec: LHA-600S), AT24C02 (Melco Buffalo: IFC-USLP) data map: 2969 * 2970 * ROMADDR 2971 * 0x00 - 0x06 : Device Synchronous Transfer Period (SCSI ID 0 - 6) 2972 * Value 0x0: ASYNC, 0x0c: Ultra-20M, 0x19: Fast-10M 2973 * 0x07 : HBA Synchronous Transfer Period 2974 * Value 0: AutoSync, 1: Manual Setting 2975 * 0x08 - 0x0f : Not Used? (0x0) 2976 * 0x10 : Bus Termination 2977 * Value 0: Auto[ON], 1: ON, 2: OFF 2978 * 0x11 : Not Used? (0) 2979 * 0x12 : Bus Reset Delay Time (0x03) 2980 * 0x13 : Bootable CD Support 2981 * Value 0: Disable, 1: Enable 2982 * 0x14 : Device Scan 2983 * Bit 7 6 5 4 3 2 1 0 2984 * | <-----------------> 2985 * | SCSI ID: Value 0: Skip, 1: YES 2986 * |-> Value 0: ALL scan, Value 1: Manual 2987 * 0x15 - 0x1b : Not Used? (0) 2988 * 0x1c : Constant? (0x01) (clock div?) 2989 * 0x1d - 0x7c : Not Used (0xff) 2990 * 0x7d : Not Used? (0xff) 2991 * 0x7e : Constant (0x55), Validity signature 2992 * 0x7f : Constant (0xaa), Validity signature 2993 */ 2994 static int nsp32_getprom_at24(nsp32_hw_data *data) 2995 { 2996 int ret, i; 2997 int auto_sync; 2998 nsp32_target *target; 2999 int entry; 3000 3001 /* 3002 * Reset time which is designated by EEPROM. 3003 * 3004 * TODO: Not used yet. 3005 */ 3006 data->resettime = nsp32_prom_read(data, 0x12); 3007 3008 /* 3009 * HBA Synchronous Transfer Period 3010 * 3011 * Note: auto_sync = 0: auto, 1: manual. Ninja SCSI HBA spec says 3012 * that if auto_sync is 0 (auto), and connected SCSI devices are 3013 * same or lower than 3, then transfer speed is set as ULTRA-20M. 3014 * On the contrary if connected SCSI devices are same or higher 3015 * than 4, then transfer speed is set as FAST-10M. 3016 * 3017 * I break this rule. The number of connected SCSI devices are 3018 * only ignored. If auto_sync is 0 (auto), then transfer speed is 3019 * forced as ULTRA-20M. 3020 */ 3021 ret = nsp32_prom_read(data, 0x07); 3022 switch (ret) { 3023 case 0: 3024 auto_sync = TRUE; 3025 break; 3026 case 1: 3027 auto_sync = FALSE; 3028 break; 3029 default: 3030 nsp32_msg(KERN_WARNING, 3031 "Unsupported Auto Sync mode. Fall back to manual mode."); 3032 auto_sync = TRUE; 3033 } 3034 3035 if (trans_mode == ULTRA20M_MODE) { 3036 auto_sync = TRUE; 3037 } 3038 3039 /* 3040 * each device Synchronous Transfer Period 3041 */ 3042 for (i = 0; i < NSP32_HOST_SCSIID; i++) { 3043 target = &data->target[i]; 3044 if (auto_sync == TRUE) { 3045 target->limit_entry = 0; /* set as ULTRA20M */ 3046 } else { 3047 ret = nsp32_prom_read(data, i); 3048 entry = nsp32_search_period_entry(data, target, ret); 3049 if (entry < 0) { 3050 /* search failed... set maximum speed */ 3051 entry = 0; 3052 } 3053 target->limit_entry = entry; 3054 } 3055 } 3056 3057 return TRUE; 3058 } 3059 3060 3061 /* 3062 * C16 110 (I-O Data: SC-NBD) data map: 3063 * 3064 * ROMADDR 3065 * 0x00 - 0x06 : Device Synchronous Transfer Period (SCSI ID 0 - 6) 3066 * Value 0x0: 20MB/S, 0x1: 10MB/S, 0x2: 5MB/S, 0x3: ASYNC 3067 * 0x07 : 0 (HBA Synchronous Transfer Period: Auto Sync) 3068 * 0x08 - 0x0f : Not Used? (0x0) 3069 * 0x10 : Transfer Mode 3070 * Value 0: PIO, 1: Busmater 3071 * 0x11 : Bus Reset Delay Time (0x00-0x20) 3072 * 0x12 : Bus Termination 3073 * Value 0: Disable, 1: Enable 3074 * 0x13 - 0x19 : Disconnection 3075 * Value 0: Disable, 1: Enable 3076 * 0x1a - 0x7c : Not Used? (0) 3077 * 0x7d : Not Used? (0xf8) 3078 * 0x7e : Constant (0x55), Validity signature 3079 * 0x7f : Constant (0xaa), Validity signature 3080 */ 3081 static int nsp32_getprom_c16(nsp32_hw_data *data) 3082 { 3083 int ret, i; 3084 nsp32_target *target; 3085 int entry, val; 3086 3087 /* 3088 * Reset time which is designated by EEPROM. 3089 * 3090 * TODO: Not used yet. 3091 */ 3092 data->resettime = nsp32_prom_read(data, 0x11); 3093 3094 /* 3095 * each device Synchronous Transfer Period 3096 */ 3097 for (i = 0; i < NSP32_HOST_SCSIID; i++) { 3098 target = &data->target[i]; 3099 ret = nsp32_prom_read(data, i); 3100 switch (ret) { 3101 case 0: /* 20MB/s */ 3102 val = 0x0c; 3103 break; 3104 case 1: /* 10MB/s */ 3105 val = 0x19; 3106 break; 3107 case 2: /* 5MB/s */ 3108 val = 0x32; 3109 break; 3110 case 3: /* ASYNC */ 3111 val = 0x00; 3112 break; 3113 default: /* default 20MB/s */ 3114 val = 0x0c; 3115 break; 3116 } 3117 entry = nsp32_search_period_entry(data, target, val); 3118 if (entry < 0 || trans_mode == ULTRA20M_MODE) { 3119 /* search failed... set maximum speed */ 3120 entry = 0; 3121 } 3122 target->limit_entry = entry; 3123 } 3124 3125 return TRUE; 3126 } 3127 3128 3129 /* 3130 * Atmel AT24C01A (drived in 5V) serial EEPROM routines 3131 */ 3132 static int nsp32_prom_read(nsp32_hw_data *data, int romaddr) 3133 { 3134 int i, val; 3135 3136 /* start condition */ 3137 nsp32_prom_start(data); 3138 3139 /* device address */ 3140 nsp32_prom_write_bit(data, 1); /* 1 */ 3141 nsp32_prom_write_bit(data, 0); /* 0 */ 3142 nsp32_prom_write_bit(data, 1); /* 1 */ 3143 nsp32_prom_write_bit(data, 0); /* 0 */ 3144 nsp32_prom_write_bit(data, 0); /* A2: 0 (GND) */ 3145 nsp32_prom_write_bit(data, 0); /* A1: 0 (GND) */ 3146 nsp32_prom_write_bit(data, 0); /* A0: 0 (GND) */ 3147 3148 /* R/W: W for dummy write */ 3149 nsp32_prom_write_bit(data, 0); 3150 3151 /* ack */ 3152 nsp32_prom_write_bit(data, 0); 3153 3154 /* word address */ 3155 for (i = 7; i >= 0; i--) { 3156 nsp32_prom_write_bit(data, ((romaddr >> i) & 1)); 3157 } 3158 3159 /* ack */ 3160 nsp32_prom_write_bit(data, 0); 3161 3162 /* start condition */ 3163 nsp32_prom_start(data); 3164 3165 /* device address */ 3166 nsp32_prom_write_bit(data, 1); /* 1 */ 3167 nsp32_prom_write_bit(data, 0); /* 0 */ 3168 nsp32_prom_write_bit(data, 1); /* 1 */ 3169 nsp32_prom_write_bit(data, 0); /* 0 */ 3170 nsp32_prom_write_bit(data, 0); /* A2: 0 (GND) */ 3171 nsp32_prom_write_bit(data, 0); /* A1: 0 (GND) */ 3172 nsp32_prom_write_bit(data, 0); /* A0: 0 (GND) */ 3173 3174 /* R/W: R */ 3175 nsp32_prom_write_bit(data, 1); 3176 3177 /* ack */ 3178 nsp32_prom_write_bit(data, 0); 3179 3180 /* data... */ 3181 val = 0; 3182 for (i = 7; i >= 0; i--) { 3183 val += (nsp32_prom_read_bit(data) << i); 3184 } 3185 3186 /* no ack */ 3187 nsp32_prom_write_bit(data, 1); 3188 3189 /* stop condition */ 3190 nsp32_prom_stop(data); 3191 3192 return val; 3193 } 3194 3195 static void nsp32_prom_set(nsp32_hw_data *data, int bit, int val) 3196 { 3197 int base = data->BaseAddress; 3198 int tmp; 3199 3200 tmp = nsp32_index_read1(base, SERIAL_ROM_CTL); 3201 3202 if (val == 0) { 3203 tmp &= ~bit; 3204 } else { 3205 tmp |= bit; 3206 } 3207 3208 nsp32_index_write1(base, SERIAL_ROM_CTL, tmp); 3209 3210 udelay(10); 3211 } 3212 3213 static int nsp32_prom_get(nsp32_hw_data *data, int bit) 3214 { 3215 int base = data->BaseAddress; 3216 int tmp, ret; 3217 3218 if (bit != SDA) { 3219 nsp32_msg(KERN_ERR, "return value is not appropriate"); 3220 return 0; 3221 } 3222 3223 3224 tmp = nsp32_index_read1(base, SERIAL_ROM_CTL) & bit; 3225 3226 if (tmp == 0) { 3227 ret = 0; 3228 } else { 3229 ret = 1; 3230 } 3231 3232 udelay(10); 3233 3234 return ret; 3235 } 3236 3237 static void nsp32_prom_start (nsp32_hw_data *data) 3238 { 3239 /* start condition */ 3240 nsp32_prom_set(data, SCL, 1); 3241 nsp32_prom_set(data, SDA, 1); 3242 nsp32_prom_set(data, ENA, 1); /* output mode */ 3243 nsp32_prom_set(data, SDA, 0); /* keeping SCL=1 and transiting 3244 * SDA 1->0 is start condition */ 3245 nsp32_prom_set(data, SCL, 0); 3246 } 3247 3248 static void nsp32_prom_stop (nsp32_hw_data *data) 3249 { 3250 /* stop condition */ 3251 nsp32_prom_set(data, SCL, 1); 3252 nsp32_prom_set(data, SDA, 0); 3253 nsp32_prom_set(data, ENA, 1); /* output mode */ 3254 nsp32_prom_set(data, SDA, 1); 3255 nsp32_prom_set(data, SCL, 0); 3256 } 3257 3258 static void nsp32_prom_write_bit(nsp32_hw_data *data, int val) 3259 { 3260 /* write */ 3261 nsp32_prom_set(data, SDA, val); 3262 nsp32_prom_set(data, SCL, 1 ); 3263 nsp32_prom_set(data, SCL, 0 ); 3264 } 3265 3266 static int nsp32_prom_read_bit(nsp32_hw_data *data) 3267 { 3268 int val; 3269 3270 /* read */ 3271 nsp32_prom_set(data, ENA, 0); /* input mode */ 3272 nsp32_prom_set(data, SCL, 1); 3273 3274 val = nsp32_prom_get(data, SDA); 3275 3276 nsp32_prom_set(data, SCL, 0); 3277 nsp32_prom_set(data, ENA, 1); /* output mode */ 3278 3279 return val; 3280 } 3281 3282 3283 /************************************************************************** 3284 * Power Management 3285 */ 3286 #ifdef CONFIG_PM 3287 3288 /* Device suspended */ 3289 static int nsp32_suspend(struct pci_dev *pdev, pm_message_t state) 3290 { 3291 struct Scsi_Host *host = pci_get_drvdata(pdev); 3292 3293 nsp32_msg(KERN_INFO, "pci-suspend: pdev=0x%p, state.event=%x, slot=%s, host=0x%p", 3294 pdev, state.event, pci_name(pdev), host); 3295 3296 pci_save_state (pdev); 3297 pci_disable_device (pdev); 3298 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 3299 3300 return 0; 3301 } 3302 3303 /* Device woken up */ 3304 static int nsp32_resume(struct pci_dev *pdev) 3305 { 3306 struct Scsi_Host *host = pci_get_drvdata(pdev); 3307 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata; 3308 unsigned short reg; 3309 3310 nsp32_msg(KERN_INFO, "pci-resume: pdev=0x%p, slot=%s, host=0x%p", 3311 pdev, pci_name(pdev), host); 3312 3313 pci_set_power_state(pdev, PCI_D0); 3314 pci_enable_wake (pdev, PCI_D0, 0); 3315 pci_restore_state (pdev); 3316 3317 reg = nsp32_read2(data->BaseAddress, INDEX_REG); 3318 3319 nsp32_msg(KERN_INFO, "io=0x%x reg=0x%x", data->BaseAddress, reg); 3320 3321 if (reg == 0xffff) { 3322 nsp32_msg(KERN_INFO, "missing device. abort resume."); 3323 return 0; 3324 } 3325 3326 nsp32hw_init (data); 3327 nsp32_do_bus_reset(data); 3328 3329 nsp32_msg(KERN_INFO, "resume success"); 3330 3331 return 0; 3332 } 3333 3334 #endif 3335 3336 /************************************************************************ 3337 * PCI/Cardbus probe/remove routine 3338 */ 3339 static int nsp32_probe(struct pci_dev *pdev, const struct pci_device_id *id) 3340 { 3341 int ret; 3342 nsp32_hw_data *data = &nsp32_data_base; 3343 3344 nsp32_dbg(NSP32_DEBUG_REGISTER, "enter"); 3345 3346 ret = pci_enable_device(pdev); 3347 if (ret) { 3348 nsp32_msg(KERN_ERR, "failed to enable pci device"); 3349 return ret; 3350 } 3351 3352 data->Pci = pdev; 3353 data->pci_devid = id; 3354 data->IrqNumber = pdev->irq; 3355 data->BaseAddress = pci_resource_start(pdev, 0); 3356 data->NumAddress = pci_resource_len (pdev, 0); 3357 data->MmioAddress = pci_ioremap_bar(pdev, 1); 3358 data->MmioLength = pci_resource_len (pdev, 1); 3359 3360 pci_set_master(pdev); 3361 3362 ret = nsp32_detect(pdev); 3363 3364 nsp32_msg(KERN_INFO, "irq: %i mmio: %p+0x%lx slot: %s model: %s", 3365 pdev->irq, 3366 data->MmioAddress, data->MmioLength, 3367 pci_name(pdev), 3368 nsp32_model[id->driver_data]); 3369 3370 nsp32_dbg(NSP32_DEBUG_REGISTER, "exit %d", ret); 3371 3372 return ret; 3373 } 3374 3375 static void nsp32_remove(struct pci_dev *pdev) 3376 { 3377 struct Scsi_Host *host = pci_get_drvdata(pdev); 3378 3379 nsp32_dbg(NSP32_DEBUG_REGISTER, "enter"); 3380 3381 scsi_remove_host(host); 3382 3383 nsp32_release(host); 3384 3385 scsi_host_put(host); 3386 } 3387 3388 static struct pci_driver nsp32_driver = { 3389 .name = "nsp32", 3390 .id_table = nsp32_pci_table, 3391 .probe = nsp32_probe, 3392 .remove = nsp32_remove, 3393 #ifdef CONFIG_PM 3394 .suspend = nsp32_suspend, 3395 .resume = nsp32_resume, 3396 #endif 3397 }; 3398 3399 /********************************************************************* 3400 * Moule entry point 3401 */ 3402 static int __init init_nsp32(void) { 3403 nsp32_msg(KERN_INFO, "loading..."); 3404 return pci_register_driver(&nsp32_driver); 3405 } 3406 3407 static void __exit exit_nsp32(void) { 3408 nsp32_msg(KERN_INFO, "unloading..."); 3409 pci_unregister_driver(&nsp32_driver); 3410 } 3411 3412 module_init(init_nsp32); 3413 module_exit(exit_nsp32); 3414 3415 /* end */ 3416