1 /* 2 * NinjaSCSI-32Bi Cardbus, NinjaSCSI-32UDE PCI/CardBus SCSI driver 3 * Copyright (C) 2001, 2002, 2003 4 * YOKOTA Hiroshi <yokota@netlab.is.tsukuba.ac.jp> 5 * GOTO Masanori <gotom@debian.or.jp>, <gotom@debian.org> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2, or (at your option) 10 * any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * 18 * Revision History: 19 * 1.0: Initial Release. 20 * 1.1: Add /proc SDTR status. 21 * Remove obsolete error handler nsp32_reset. 22 * Some clean up. 23 * 1.2: PowerPC (big endian) support. 24 */ 25 26 #include <linux/module.h> 27 #include <linux/init.h> 28 #include <linux/kernel.h> 29 #include <linux/string.h> 30 #include <linux/timer.h> 31 #include <linux/ioport.h> 32 #include <linux/major.h> 33 #include <linux/blkdev.h> 34 #include <linux/interrupt.h> 35 #include <linux/pci.h> 36 #include <linux/delay.h> 37 #include <linux/ctype.h> 38 #include <linux/dma-mapping.h> 39 40 #include <asm/dma.h> 41 #include <asm/io.h> 42 43 #include <scsi/scsi.h> 44 #include <scsi/scsi_cmnd.h> 45 #include <scsi/scsi_device.h> 46 #include <scsi/scsi_host.h> 47 #include <scsi/scsi_ioctl.h> 48 49 #include "nsp32.h" 50 51 52 /*********************************************************************** 53 * Module parameters 54 */ 55 static int trans_mode = 0; /* default: BIOS */ 56 module_param (trans_mode, int, 0); 57 MODULE_PARM_DESC(trans_mode, "transfer mode (0: BIOS(default) 1: Async 2: Ultra20M"); 58 #define ASYNC_MODE 1 59 #define ULTRA20M_MODE 2 60 61 static bool auto_param = 0; /* default: ON */ 62 module_param (auto_param, bool, 0); 63 MODULE_PARM_DESC(auto_param, "AutoParameter mode (0: ON(default) 1: OFF)"); 64 65 static bool disc_priv = 1; /* default: OFF */ 66 module_param (disc_priv, bool, 0); 67 MODULE_PARM_DESC(disc_priv, "disconnection privilege mode (0: ON 1: OFF(default))"); 68 69 MODULE_AUTHOR("YOKOTA Hiroshi <yokota@netlab.is.tsukuba.ac.jp>, GOTO Masanori <gotom@debian.or.jp>"); 70 MODULE_DESCRIPTION("Workbit NinjaSCSI-32Bi/UDE CardBus/PCI SCSI host bus adapter module"); 71 MODULE_LICENSE("GPL"); 72 73 static const char *nsp32_release_version = "1.2"; 74 75 76 /**************************************************************************** 77 * Supported hardware 78 */ 79 static struct pci_device_id nsp32_pci_table[] = { 80 { 81 .vendor = PCI_VENDOR_ID_IODATA, 82 .device = PCI_DEVICE_ID_NINJASCSI_32BI_CBSC_II, 83 .subvendor = PCI_ANY_ID, 84 .subdevice = PCI_ANY_ID, 85 .driver_data = MODEL_IODATA, 86 }, 87 { 88 .vendor = PCI_VENDOR_ID_WORKBIT, 89 .device = PCI_DEVICE_ID_NINJASCSI_32BI_KME, 90 .subvendor = PCI_ANY_ID, 91 .subdevice = PCI_ANY_ID, 92 .driver_data = MODEL_KME, 93 }, 94 { 95 .vendor = PCI_VENDOR_ID_WORKBIT, 96 .device = PCI_DEVICE_ID_NINJASCSI_32BI_WBT, 97 .subvendor = PCI_ANY_ID, 98 .subdevice = PCI_ANY_ID, 99 .driver_data = MODEL_WORKBIT, 100 }, 101 { 102 .vendor = PCI_VENDOR_ID_WORKBIT, 103 .device = PCI_DEVICE_ID_WORKBIT_STANDARD, 104 .subvendor = PCI_ANY_ID, 105 .subdevice = PCI_ANY_ID, 106 .driver_data = MODEL_PCI_WORKBIT, 107 }, 108 { 109 .vendor = PCI_VENDOR_ID_WORKBIT, 110 .device = PCI_DEVICE_ID_NINJASCSI_32BI_LOGITEC, 111 .subvendor = PCI_ANY_ID, 112 .subdevice = PCI_ANY_ID, 113 .driver_data = MODEL_LOGITEC, 114 }, 115 { 116 .vendor = PCI_VENDOR_ID_WORKBIT, 117 .device = PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC, 118 .subvendor = PCI_ANY_ID, 119 .subdevice = PCI_ANY_ID, 120 .driver_data = MODEL_PCI_LOGITEC, 121 }, 122 { 123 .vendor = PCI_VENDOR_ID_WORKBIT, 124 .device = PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO, 125 .subvendor = PCI_ANY_ID, 126 .subdevice = PCI_ANY_ID, 127 .driver_data = MODEL_PCI_MELCO, 128 }, 129 { 130 .vendor = PCI_VENDOR_ID_WORKBIT, 131 .device = PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO_II, 132 .subvendor = PCI_ANY_ID, 133 .subdevice = PCI_ANY_ID, 134 .driver_data = MODEL_PCI_MELCO, 135 }, 136 {0,0,}, 137 }; 138 MODULE_DEVICE_TABLE(pci, nsp32_pci_table); 139 140 static nsp32_hw_data nsp32_data_base; /* probe <-> detect glue */ 141 142 143 /* 144 * Period/AckWidth speed conversion table 145 * 146 * Note: This period/ackwidth speed table must be in descending order. 147 */ 148 static nsp32_sync_table nsp32_sync_table_40M[] = { 149 /* {PNo, AW, SP, EP, SREQ smpl} Speed(MB/s) Period AckWidth */ 150 {0x1, 0, 0x0c, 0x0c, SMPL_40M}, /* 20.0 : 50ns, 25ns */ 151 {0x2, 0, 0x0d, 0x18, SMPL_40M}, /* 13.3 : 75ns, 25ns */ 152 {0x3, 1, 0x19, 0x19, SMPL_40M}, /* 10.0 : 100ns, 50ns */ 153 {0x4, 1, 0x1a, 0x1f, SMPL_20M}, /* 8.0 : 125ns, 50ns */ 154 {0x5, 2, 0x20, 0x25, SMPL_20M}, /* 6.7 : 150ns, 75ns */ 155 {0x6, 2, 0x26, 0x31, SMPL_20M}, /* 5.7 : 175ns, 75ns */ 156 {0x7, 3, 0x32, 0x32, SMPL_20M}, /* 5.0 : 200ns, 100ns */ 157 {0x8, 3, 0x33, 0x38, SMPL_10M}, /* 4.4 : 225ns, 100ns */ 158 {0x9, 3, 0x39, 0x3e, SMPL_10M}, /* 4.0 : 250ns, 100ns */ 159 }; 160 161 static nsp32_sync_table nsp32_sync_table_20M[] = { 162 {0x1, 0, 0x19, 0x19, SMPL_40M}, /* 10.0 : 100ns, 50ns */ 163 {0x2, 0, 0x1a, 0x25, SMPL_20M}, /* 6.7 : 150ns, 50ns */ 164 {0x3, 1, 0x26, 0x32, SMPL_20M}, /* 5.0 : 200ns, 100ns */ 165 {0x4, 1, 0x33, 0x3e, SMPL_10M}, /* 4.0 : 250ns, 100ns */ 166 {0x5, 2, 0x3f, 0x4b, SMPL_10M}, /* 3.3 : 300ns, 150ns */ 167 {0x6, 2, 0x4c, 0x57, SMPL_10M}, /* 2.8 : 350ns, 150ns */ 168 {0x7, 3, 0x58, 0x64, SMPL_10M}, /* 2.5 : 400ns, 200ns */ 169 {0x8, 3, 0x65, 0x70, SMPL_10M}, /* 2.2 : 450ns, 200ns */ 170 {0x9, 3, 0x71, 0x7d, SMPL_10M}, /* 2.0 : 500ns, 200ns */ 171 }; 172 173 static nsp32_sync_table nsp32_sync_table_pci[] = { 174 {0x1, 0, 0x0c, 0x0f, SMPL_40M}, /* 16.6 : 60ns, 30ns */ 175 {0x2, 0, 0x10, 0x16, SMPL_40M}, /* 11.1 : 90ns, 30ns */ 176 {0x3, 1, 0x17, 0x1e, SMPL_20M}, /* 8.3 : 120ns, 60ns */ 177 {0x4, 1, 0x1f, 0x25, SMPL_20M}, /* 6.7 : 150ns, 60ns */ 178 {0x5, 2, 0x26, 0x2d, SMPL_20M}, /* 5.6 : 180ns, 90ns */ 179 {0x6, 2, 0x2e, 0x34, SMPL_10M}, /* 4.8 : 210ns, 90ns */ 180 {0x7, 3, 0x35, 0x3c, SMPL_10M}, /* 4.2 : 240ns, 120ns */ 181 {0x8, 3, 0x3d, 0x43, SMPL_10M}, /* 3.7 : 270ns, 120ns */ 182 {0x9, 3, 0x44, 0x4b, SMPL_10M}, /* 3.3 : 300ns, 120ns */ 183 }; 184 185 /* 186 * function declaration 187 */ 188 /* module entry point */ 189 static int nsp32_probe (struct pci_dev *, const struct pci_device_id *); 190 static void nsp32_remove(struct pci_dev *); 191 static int __init init_nsp32 (void); 192 static void __exit exit_nsp32 (void); 193 194 /* struct struct scsi_host_template */ 195 static int nsp32_show_info (struct seq_file *, struct Scsi_Host *); 196 197 static int nsp32_detect (struct pci_dev *pdev); 198 static int nsp32_queuecommand(struct Scsi_Host *, struct scsi_cmnd *); 199 static const char *nsp32_info (struct Scsi_Host *); 200 static int nsp32_release (struct Scsi_Host *); 201 202 /* SCSI error handler */ 203 static int nsp32_eh_abort (struct scsi_cmnd *); 204 static int nsp32_eh_host_reset(struct scsi_cmnd *); 205 206 /* generate SCSI message */ 207 static void nsp32_build_identify(struct scsi_cmnd *); 208 static void nsp32_build_nop (struct scsi_cmnd *); 209 static void nsp32_build_reject (struct scsi_cmnd *); 210 static void nsp32_build_sdtr (struct scsi_cmnd *, unsigned char, unsigned char); 211 212 /* SCSI message handler */ 213 static int nsp32_busfree_occur(struct scsi_cmnd *, unsigned short); 214 static void nsp32_msgout_occur (struct scsi_cmnd *); 215 static void nsp32_msgin_occur (struct scsi_cmnd *, unsigned long, unsigned short); 216 217 static int nsp32_setup_sg_table (struct scsi_cmnd *); 218 static int nsp32_selection_autopara(struct scsi_cmnd *); 219 static int nsp32_selection_autoscsi(struct scsi_cmnd *); 220 static void nsp32_scsi_done (struct scsi_cmnd *); 221 static int nsp32_arbitration (struct scsi_cmnd *, unsigned int); 222 static int nsp32_reselection (struct scsi_cmnd *, unsigned char); 223 static void nsp32_adjust_busfree (struct scsi_cmnd *, unsigned int); 224 static void nsp32_restart_autoscsi (struct scsi_cmnd *, unsigned short); 225 226 /* SCSI SDTR */ 227 static void nsp32_analyze_sdtr (struct scsi_cmnd *); 228 static int nsp32_search_period_entry(nsp32_hw_data *, nsp32_target *, unsigned char); 229 static void nsp32_set_async (nsp32_hw_data *, nsp32_target *); 230 static void nsp32_set_max_sync (nsp32_hw_data *, nsp32_target *, unsigned char *, unsigned char *); 231 static void nsp32_set_sync_entry (nsp32_hw_data *, nsp32_target *, int, unsigned char); 232 233 /* SCSI bus status handler */ 234 static void nsp32_wait_req (nsp32_hw_data *, int); 235 static void nsp32_wait_sack (nsp32_hw_data *, int); 236 static void nsp32_sack_assert (nsp32_hw_data *); 237 static void nsp32_sack_negate (nsp32_hw_data *); 238 static void nsp32_do_bus_reset(nsp32_hw_data *); 239 240 /* hardware interrupt handler */ 241 static irqreturn_t do_nsp32_isr(int, void *); 242 243 /* initialize hardware */ 244 static int nsp32hw_init(nsp32_hw_data *); 245 246 /* EEPROM handler */ 247 static int nsp32_getprom_param (nsp32_hw_data *); 248 static int nsp32_getprom_at24 (nsp32_hw_data *); 249 static int nsp32_getprom_c16 (nsp32_hw_data *); 250 static void nsp32_prom_start (nsp32_hw_data *); 251 static void nsp32_prom_stop (nsp32_hw_data *); 252 static int nsp32_prom_read (nsp32_hw_data *, int); 253 static int nsp32_prom_read_bit (nsp32_hw_data *); 254 static void nsp32_prom_write_bit(nsp32_hw_data *, int); 255 static void nsp32_prom_set (nsp32_hw_data *, int, int); 256 static int nsp32_prom_get (nsp32_hw_data *, int); 257 258 /* debug/warning/info message */ 259 static void nsp32_message (const char *, int, char *, char *, ...); 260 #ifdef NSP32_DEBUG 261 static void nsp32_dmessage(const char *, int, int, char *, ...); 262 #endif 263 264 /* 265 * max_sectors is currently limited up to 128. 266 */ 267 static struct scsi_host_template nsp32_template = { 268 .proc_name = "nsp32", 269 .name = "Workbit NinjaSCSI-32Bi/UDE", 270 .show_info = nsp32_show_info, 271 .info = nsp32_info, 272 .queuecommand = nsp32_queuecommand, 273 .can_queue = 1, 274 .sg_tablesize = NSP32_SG_SIZE, 275 .max_sectors = 128, 276 .this_id = NSP32_HOST_SCSIID, 277 .dma_boundary = PAGE_SIZE - 1, 278 .eh_abort_handler = nsp32_eh_abort, 279 .eh_host_reset_handler = nsp32_eh_host_reset, 280 /* .highmem_io = 1, */ 281 }; 282 283 #include "nsp32_io.h" 284 285 /*********************************************************************** 286 * debug, error print 287 */ 288 #ifndef NSP32_DEBUG 289 # define NSP32_DEBUG_MASK 0x000000 290 # define nsp32_msg(type, args...) nsp32_message ("", 0, (type), args) 291 # define nsp32_dbg(mask, args...) /* */ 292 #else 293 # define NSP32_DEBUG_MASK 0xffffff 294 # define nsp32_msg(type, args...) \ 295 nsp32_message (__func__, __LINE__, (type), args) 296 # define nsp32_dbg(mask, args...) \ 297 nsp32_dmessage(__func__, __LINE__, (mask), args) 298 #endif 299 300 #define NSP32_DEBUG_QUEUECOMMAND BIT(0) 301 #define NSP32_DEBUG_REGISTER BIT(1) 302 #define NSP32_DEBUG_AUTOSCSI BIT(2) 303 #define NSP32_DEBUG_INTR BIT(3) 304 #define NSP32_DEBUG_SGLIST BIT(4) 305 #define NSP32_DEBUG_BUSFREE BIT(5) 306 #define NSP32_DEBUG_CDB_CONTENTS BIT(6) 307 #define NSP32_DEBUG_RESELECTION BIT(7) 308 #define NSP32_DEBUG_MSGINOCCUR BIT(8) 309 #define NSP32_DEBUG_EEPROM BIT(9) 310 #define NSP32_DEBUG_MSGOUTOCCUR BIT(10) 311 #define NSP32_DEBUG_BUSRESET BIT(11) 312 #define NSP32_DEBUG_RESTART BIT(12) 313 #define NSP32_DEBUG_SYNC BIT(13) 314 #define NSP32_DEBUG_WAIT BIT(14) 315 #define NSP32_DEBUG_TARGETFLAG BIT(15) 316 #define NSP32_DEBUG_PROC BIT(16) 317 #define NSP32_DEBUG_INIT BIT(17) 318 #define NSP32_SPECIAL_PRINT_REGISTER BIT(20) 319 320 #define NSP32_DEBUG_BUF_LEN 100 321 322 static void nsp32_message(const char *func, int line, char *type, char *fmt, ...) 323 { 324 va_list args; 325 char buf[NSP32_DEBUG_BUF_LEN]; 326 327 va_start(args, fmt); 328 vsnprintf(buf, sizeof(buf), fmt, args); 329 va_end(args); 330 331 #ifndef NSP32_DEBUG 332 printk("%snsp32: %s\n", type, buf); 333 #else 334 printk("%snsp32: %s (%d): %s\n", type, func, line, buf); 335 #endif 336 } 337 338 #ifdef NSP32_DEBUG 339 static void nsp32_dmessage(const char *func, int line, int mask, char *fmt, ...) 340 { 341 va_list args; 342 char buf[NSP32_DEBUG_BUF_LEN]; 343 344 va_start(args, fmt); 345 vsnprintf(buf, sizeof(buf), fmt, args); 346 va_end(args); 347 348 if (mask & NSP32_DEBUG_MASK) { 349 printk("nsp32-debug: 0x%x %s (%d): %s\n", mask, func, line, buf); 350 } 351 } 352 #endif 353 354 #ifdef NSP32_DEBUG 355 # include "nsp32_debug.c" 356 #else 357 # define show_command(arg) /* */ 358 # define show_busphase(arg) /* */ 359 # define show_autophase(arg) /* */ 360 #endif 361 362 /* 363 * IDENTIFY Message 364 */ 365 static void nsp32_build_identify(struct scsi_cmnd *SCpnt) 366 { 367 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 368 int pos = data->msgout_len; 369 int mode = FALSE; 370 371 /* XXX: Auto DiscPriv detection is progressing... */ 372 if (disc_priv == 0) { 373 /* mode = TRUE; */ 374 } 375 376 data->msgoutbuf[pos] = IDENTIFY(mode, SCpnt->device->lun); pos++; 377 378 data->msgout_len = pos; 379 } 380 381 /* 382 * SDTR Message Routine 383 */ 384 static void nsp32_build_sdtr(struct scsi_cmnd *SCpnt, 385 unsigned char period, 386 unsigned char offset) 387 { 388 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 389 int pos = data->msgout_len; 390 391 data->msgoutbuf[pos] = EXTENDED_MESSAGE; pos++; 392 data->msgoutbuf[pos] = EXTENDED_SDTR_LEN; pos++; 393 data->msgoutbuf[pos] = EXTENDED_SDTR; pos++; 394 data->msgoutbuf[pos] = period; pos++; 395 data->msgoutbuf[pos] = offset; pos++; 396 397 data->msgout_len = pos; 398 } 399 400 /* 401 * No Operation Message 402 */ 403 static void nsp32_build_nop(struct scsi_cmnd *SCpnt) 404 { 405 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 406 int pos = data->msgout_len; 407 408 if (pos != 0) { 409 nsp32_msg(KERN_WARNING, 410 "Some messages are already contained!"); 411 return; 412 } 413 414 data->msgoutbuf[pos] = NOP; pos++; 415 data->msgout_len = pos; 416 } 417 418 /* 419 * Reject Message 420 */ 421 static void nsp32_build_reject(struct scsi_cmnd *SCpnt) 422 { 423 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 424 int pos = data->msgout_len; 425 426 data->msgoutbuf[pos] = MESSAGE_REJECT; pos++; 427 data->msgout_len = pos; 428 } 429 430 /* 431 * timer 432 */ 433 #if 0 434 static void nsp32_start_timer(struct scsi_cmnd *SCpnt, int time) 435 { 436 unsigned int base = SCpnt->host->io_port; 437 438 nsp32_dbg(NSP32_DEBUG_INTR, "timer=%d", time); 439 440 if (time & (~TIMER_CNT_MASK)) { 441 nsp32_dbg(NSP32_DEBUG_INTR, "timer set overflow"); 442 } 443 444 nsp32_write2(base, TIMER_SET, time & TIMER_CNT_MASK); 445 } 446 #endif 447 448 449 /* 450 * set SCSI command and other parameter to asic, and start selection phase 451 */ 452 static int nsp32_selection_autopara(struct scsi_cmnd *SCpnt) 453 { 454 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 455 unsigned int base = SCpnt->device->host->io_port; 456 unsigned int host_id = SCpnt->device->host->this_id; 457 unsigned char target = scmd_id(SCpnt); 458 nsp32_autoparam *param = data->autoparam; 459 unsigned char phase; 460 int i, ret; 461 unsigned int msgout; 462 u16_le s; 463 464 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "in"); 465 466 /* 467 * check bus free 468 */ 469 phase = nsp32_read1(base, SCSI_BUS_MONITOR); 470 if (phase != BUSMON_BUS_FREE) { 471 nsp32_msg(KERN_WARNING, "bus busy"); 472 show_busphase(phase & BUSMON_PHASE_MASK); 473 SCpnt->result = DID_BUS_BUSY << 16; 474 return FALSE; 475 } 476 477 /* 478 * message out 479 * 480 * Note: If the range of msgout_len is 1 - 3, fill scsi_msgout. 481 * over 3 messages needs another routine. 482 */ 483 if (data->msgout_len == 0) { 484 nsp32_msg(KERN_ERR, "SCSI MsgOut without any message!"); 485 SCpnt->result = DID_ERROR << 16; 486 return FALSE; 487 } else if (data->msgout_len > 0 && data->msgout_len <= 3) { 488 msgout = 0; 489 for (i = 0; i < data->msgout_len; i++) { 490 /* 491 * the sending order of the message is: 492 * MCNT 3: MSG#0 -> MSG#1 -> MSG#2 493 * MCNT 2: MSG#1 -> MSG#2 494 * MCNT 1: MSG#2 495 */ 496 msgout >>= 8; 497 msgout |= ((unsigned int)(data->msgoutbuf[i]) << 24); 498 } 499 msgout |= MV_VALID; /* MV valid */ 500 msgout |= (unsigned int)data->msgout_len; /* len */ 501 } else { 502 /* data->msgout_len > 3 */ 503 msgout = 0; 504 } 505 506 // nsp_dbg(NSP32_DEBUG_AUTOSCSI, "sel time out=0x%x\n", nsp32_read2(base, SEL_TIME_OUT)); 507 // nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME); 508 509 /* 510 * setup asic parameter 511 */ 512 memset(param, 0, sizeof(nsp32_autoparam)); 513 514 /* cdb */ 515 for (i = 0; i < SCpnt->cmd_len; i++) { 516 param->cdb[4 * i] = SCpnt->cmnd[i]; 517 } 518 519 /* outgoing messages */ 520 param->msgout = cpu_to_le32(msgout); 521 522 /* syncreg, ackwidth, target id, SREQ sampling rate */ 523 param->syncreg = data->cur_target->syncreg; 524 param->ackwidth = data->cur_target->ackwidth; 525 param->target_id = BIT(host_id) | BIT(target); 526 param->sample_reg = data->cur_target->sample_reg; 527 528 // nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "sample rate=0x%x\n", data->cur_target->sample_reg); 529 530 /* command control */ 531 param->command_control = cpu_to_le16(CLEAR_CDB_FIFO_POINTER | 532 AUTOSCSI_START | 533 AUTO_MSGIN_00_OR_04 | 534 AUTO_MSGIN_02 | 535 AUTO_ATN ); 536 537 538 /* transfer control */ 539 s = 0; 540 switch (data->trans_method) { 541 case NSP32_TRANSFER_BUSMASTER: 542 s |= BM_START; 543 break; 544 case NSP32_TRANSFER_MMIO: 545 s |= CB_MMIO_MODE; 546 break; 547 case NSP32_TRANSFER_PIO: 548 s |= CB_IO_MODE; 549 break; 550 default: 551 nsp32_msg(KERN_ERR, "unknown trans_method"); 552 break; 553 } 554 /* 555 * OR-ed BLIEND_MODE, FIFO intr is decreased, instead of PCI bus waits. 556 * For bus master transfer, it's taken off. 557 */ 558 s |= (TRANSFER_GO | ALL_COUNTER_CLR); 559 param->transfer_control = cpu_to_le16(s); 560 561 /* sg table addr */ 562 param->sgt_pointer = cpu_to_le32(data->cur_lunt->sglun_paddr); 563 564 /* 565 * transfer parameter to ASIC 566 */ 567 nsp32_write4(base, SGT_ADR, data->auto_paddr); 568 nsp32_write2(base, COMMAND_CONTROL, CLEAR_CDB_FIFO_POINTER | 569 AUTO_PARAMETER ); 570 571 /* 572 * Check arbitration 573 */ 574 ret = nsp32_arbitration(SCpnt, base); 575 576 return ret; 577 } 578 579 580 /* 581 * Selection with AUTO SCSI (without AUTO PARAMETER) 582 */ 583 static int nsp32_selection_autoscsi(struct scsi_cmnd *SCpnt) 584 { 585 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 586 unsigned int base = SCpnt->device->host->io_port; 587 unsigned int host_id = SCpnt->device->host->this_id; 588 unsigned char target = scmd_id(SCpnt); 589 unsigned char phase; 590 int status; 591 unsigned short command = 0; 592 unsigned int msgout = 0; 593 unsigned short execph; 594 int i; 595 596 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "in"); 597 598 /* 599 * IRQ disable 600 */ 601 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK); 602 603 /* 604 * check bus line 605 */ 606 phase = nsp32_read1(base, SCSI_BUS_MONITOR); 607 if ((phase & BUSMON_BSY) || (phase & BUSMON_SEL)) { 608 nsp32_msg(KERN_WARNING, "bus busy"); 609 SCpnt->result = DID_BUS_BUSY << 16; 610 status = 1; 611 goto out; 612 } 613 614 /* 615 * clear execph 616 */ 617 execph = nsp32_read2(base, SCSI_EXECUTE_PHASE); 618 619 /* 620 * clear FIFO counter to set CDBs 621 */ 622 nsp32_write2(base, COMMAND_CONTROL, CLEAR_CDB_FIFO_POINTER); 623 624 /* 625 * set CDB0 - CDB15 626 */ 627 for (i = 0; i < SCpnt->cmd_len; i++) { 628 nsp32_write1(base, COMMAND_DATA, SCpnt->cmnd[i]); 629 } 630 nsp32_dbg(NSP32_DEBUG_CDB_CONTENTS, "CDB[0]=[0x%x]", SCpnt->cmnd[0]); 631 632 /* 633 * set SCSIOUT LATCH(initiator)/TARGET(target) (OR-ed) ID 634 */ 635 nsp32_write1(base, SCSI_OUT_LATCH_TARGET_ID, BIT(host_id) | BIT(target)); 636 637 /* 638 * set SCSI MSGOUT REG 639 * 640 * Note: If the range of msgout_len is 1 - 3, fill scsi_msgout. 641 * over 3 messages needs another routine. 642 */ 643 if (data->msgout_len == 0) { 644 nsp32_msg(KERN_ERR, "SCSI MsgOut without any message!"); 645 SCpnt->result = DID_ERROR << 16; 646 status = 1; 647 goto out; 648 } else if (data->msgout_len > 0 && data->msgout_len <= 3) { 649 msgout = 0; 650 for (i = 0; i < data->msgout_len; i++) { 651 /* 652 * the sending order of the message is: 653 * MCNT 3: MSG#0 -> MSG#1 -> MSG#2 654 * MCNT 2: MSG#1 -> MSG#2 655 * MCNT 1: MSG#2 656 */ 657 msgout >>= 8; 658 msgout |= ((unsigned int)(data->msgoutbuf[i]) << 24); 659 } 660 msgout |= MV_VALID; /* MV valid */ 661 msgout |= (unsigned int)data->msgout_len; /* len */ 662 nsp32_write4(base, SCSI_MSG_OUT, msgout); 663 } else { 664 /* data->msgout_len > 3 */ 665 nsp32_write4(base, SCSI_MSG_OUT, 0); 666 } 667 668 /* 669 * set selection timeout(= 250ms) 670 */ 671 nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME); 672 673 /* 674 * set SREQ hazard killer sampling rate 675 * 676 * TODO: sample_rate (BASE+0F) is 0 when internal clock = 40MHz. 677 * check other internal clock! 678 */ 679 nsp32_write1(base, SREQ_SMPL_RATE, data->cur_target->sample_reg); 680 681 /* 682 * clear Arbit 683 */ 684 nsp32_write1(base, SET_ARBIT, ARBIT_CLEAR); 685 686 /* 687 * set SYNCREG 688 * Don't set BM_START_ADR before setting this register. 689 */ 690 nsp32_write1(base, SYNC_REG, data->cur_target->syncreg); 691 692 /* 693 * set ACKWIDTH 694 */ 695 nsp32_write1(base, ACK_WIDTH, data->cur_target->ackwidth); 696 697 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, 698 "syncreg=0x%x, ackwidth=0x%x, sgtpaddr=0x%x, id=0x%x", 699 nsp32_read1(base, SYNC_REG), nsp32_read1(base, ACK_WIDTH), 700 nsp32_read4(base, SGT_ADR), nsp32_read1(base, SCSI_OUT_LATCH_TARGET_ID)); 701 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "msgout_len=%d, msgout=0x%x", 702 data->msgout_len, msgout); 703 704 /* 705 * set SGT ADDR (physical address) 706 */ 707 nsp32_write4(base, SGT_ADR, data->cur_lunt->sglun_paddr); 708 709 /* 710 * set TRANSFER CONTROL REG 711 */ 712 command = 0; 713 command |= (TRANSFER_GO | ALL_COUNTER_CLR); 714 if (data->trans_method & NSP32_TRANSFER_BUSMASTER) { 715 if (scsi_bufflen(SCpnt) > 0) { 716 command |= BM_START; 717 } 718 } else if (data->trans_method & NSP32_TRANSFER_MMIO) { 719 command |= CB_MMIO_MODE; 720 } else if (data->trans_method & NSP32_TRANSFER_PIO) { 721 command |= CB_IO_MODE; 722 } 723 nsp32_write2(base, TRANSFER_CONTROL, command); 724 725 /* 726 * start AUTO SCSI, kick off arbitration 727 */ 728 command = (CLEAR_CDB_FIFO_POINTER | 729 AUTOSCSI_START | 730 AUTO_MSGIN_00_OR_04 | 731 AUTO_MSGIN_02 | 732 AUTO_ATN ); 733 nsp32_write2(base, COMMAND_CONTROL, command); 734 735 /* 736 * Check arbitration 737 */ 738 status = nsp32_arbitration(SCpnt, base); 739 740 out: 741 /* 742 * IRQ enable 743 */ 744 nsp32_write2(base, IRQ_CONTROL, 0); 745 746 return status; 747 } 748 749 750 /* 751 * Arbitration Status Check 752 * 753 * Note: Arbitration counter is waited during ARBIT_GO is not lifting. 754 * Using udelay(1) consumes CPU time and system time, but 755 * arbitration delay time is defined minimal 2.4us in SCSI 756 * specification, thus udelay works as coarse grained wait timer. 757 */ 758 static int nsp32_arbitration(struct scsi_cmnd *SCpnt, unsigned int base) 759 { 760 unsigned char arbit; 761 int status = TRUE; 762 int time = 0; 763 764 do { 765 arbit = nsp32_read1(base, ARBIT_STATUS); 766 time++; 767 } while ((arbit & (ARBIT_WIN | ARBIT_FAIL)) == 0 && 768 (time <= ARBIT_TIMEOUT_TIME)); 769 770 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, 771 "arbit: 0x%x, delay time: %d", arbit, time); 772 773 if (arbit & ARBIT_WIN) { 774 /* Arbitration succeeded */ 775 SCpnt->result = DID_OK << 16; 776 nsp32_index_write1(base, EXT_PORT, LED_ON); /* PCI LED on */ 777 } else if (arbit & ARBIT_FAIL) { 778 /* Arbitration failed */ 779 SCpnt->result = DID_BUS_BUSY << 16; 780 status = FALSE; 781 } else { 782 /* 783 * unknown error or ARBIT_GO timeout, 784 * something lock up! guess no connection. 785 */ 786 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "arbit timeout"); 787 SCpnt->result = DID_NO_CONNECT << 16; 788 status = FALSE; 789 } 790 791 /* 792 * clear Arbit 793 */ 794 nsp32_write1(base, SET_ARBIT, ARBIT_CLEAR); 795 796 return status; 797 } 798 799 800 /* 801 * reselection 802 * 803 * Note: This reselection routine is called from msgin_occur, 804 * reselection target id&lun must be already set. 805 * SCSI-2 says IDENTIFY implies RESTORE_POINTER operation. 806 */ 807 static int nsp32_reselection(struct scsi_cmnd *SCpnt, unsigned char newlun) 808 { 809 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 810 unsigned int host_id = SCpnt->device->host->this_id; 811 unsigned int base = SCpnt->device->host->io_port; 812 unsigned char tmpid, newid; 813 814 nsp32_dbg(NSP32_DEBUG_RESELECTION, "enter"); 815 816 /* 817 * calculate reselected SCSI ID 818 */ 819 tmpid = nsp32_read1(base, RESELECT_ID); 820 tmpid &= (~BIT(host_id)); 821 newid = 0; 822 while (tmpid) { 823 if (tmpid & 1) { 824 break; 825 } 826 tmpid >>= 1; 827 newid++; 828 } 829 830 /* 831 * If reselected New ID:LUN is not existed 832 * or current nexus is not existed, unexpected 833 * reselection is occurred. Send reject message. 834 */ 835 if (newid >= ARRAY_SIZE(data->lunt) || newlun >= ARRAY_SIZE(data->lunt[0])) { 836 nsp32_msg(KERN_WARNING, "unknown id/lun"); 837 return FALSE; 838 } else if(data->lunt[newid][newlun].SCpnt == NULL) { 839 nsp32_msg(KERN_WARNING, "no SCSI command is processing"); 840 return FALSE; 841 } 842 843 data->cur_id = newid; 844 data->cur_lun = newlun; 845 data->cur_target = &(data->target[newid]); 846 data->cur_lunt = &(data->lunt[newid][newlun]); 847 848 /* reset SACK/SavedACK counter (or ALL clear?) */ 849 nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK); 850 851 return TRUE; 852 } 853 854 855 /* 856 * nsp32_setup_sg_table - build scatter gather list for transfer data 857 * with bus master. 858 * 859 * Note: NinjaSCSI-32Bi/UDE bus master can not transfer over 64KB at a time. 860 */ 861 static int nsp32_setup_sg_table(struct scsi_cmnd *SCpnt) 862 { 863 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 864 struct scatterlist *sg; 865 nsp32_sgtable *sgt = data->cur_lunt->sglun->sgt; 866 int num, i; 867 u32_le l; 868 869 if (sgt == NULL) { 870 nsp32_dbg(NSP32_DEBUG_SGLIST, "SGT == null"); 871 return FALSE; 872 } 873 874 num = scsi_dma_map(SCpnt); 875 if (!num) 876 return TRUE; 877 else if (num < 0) 878 return FALSE; 879 else { 880 scsi_for_each_sg(SCpnt, sg, num, i) { 881 /* 882 * Build nsp32_sglist, substitute sg dma addresses. 883 */ 884 sgt[i].addr = cpu_to_le32(sg_dma_address(sg)); 885 sgt[i].len = cpu_to_le32(sg_dma_len(sg)); 886 887 if (le32_to_cpu(sgt[i].len) > 0x10000) { 888 nsp32_msg(KERN_ERR, 889 "can't transfer over 64KB at a time, size=0x%lx", le32_to_cpu(sgt[i].len)); 890 return FALSE; 891 } 892 nsp32_dbg(NSP32_DEBUG_SGLIST, 893 "num 0x%x : addr 0x%lx len 0x%lx", 894 i, 895 le32_to_cpu(sgt[i].addr), 896 le32_to_cpu(sgt[i].len )); 897 } 898 899 /* set end mark */ 900 l = le32_to_cpu(sgt[num-1].len); 901 sgt[num-1].len = cpu_to_le32(l | SGTEND); 902 } 903 904 return TRUE; 905 } 906 907 static int nsp32_queuecommand_lck(struct scsi_cmnd *SCpnt, void (*done)(struct scsi_cmnd *)) 908 { 909 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 910 nsp32_target *target; 911 nsp32_lunt *cur_lunt; 912 int ret; 913 914 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, 915 "enter. target: 0x%x LUN: 0x%llx cmnd: 0x%x cmndlen: 0x%x " 916 "use_sg: 0x%x reqbuf: 0x%lx reqlen: 0x%x", 917 SCpnt->device->id, SCpnt->device->lun, SCpnt->cmnd[0], SCpnt->cmd_len, 918 scsi_sg_count(SCpnt), scsi_sglist(SCpnt), scsi_bufflen(SCpnt)); 919 920 if (data->CurrentSC != NULL) { 921 nsp32_msg(KERN_ERR, "Currentsc != NULL. Cancel this command request"); 922 data->CurrentSC = NULL; 923 SCpnt->result = DID_NO_CONNECT << 16; 924 done(SCpnt); 925 return 0; 926 } 927 928 /* check target ID is not same as this initiator ID */ 929 if (scmd_id(SCpnt) == SCpnt->device->host->this_id) { 930 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, "target==host???"); 931 SCpnt->result = DID_BAD_TARGET << 16; 932 done(SCpnt); 933 return 0; 934 } 935 936 /* check target LUN is allowable value */ 937 if (SCpnt->device->lun >= MAX_LUN) { 938 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, "no more lun"); 939 SCpnt->result = DID_BAD_TARGET << 16; 940 done(SCpnt); 941 return 0; 942 } 943 944 show_command(SCpnt); 945 946 SCpnt->scsi_done = done; 947 data->CurrentSC = SCpnt; 948 SCpnt->SCp.Status = CHECK_CONDITION; 949 SCpnt->SCp.Message = 0; 950 scsi_set_resid(SCpnt, scsi_bufflen(SCpnt)); 951 952 SCpnt->SCp.ptr = (char *)scsi_sglist(SCpnt); 953 SCpnt->SCp.this_residual = scsi_bufflen(SCpnt); 954 SCpnt->SCp.buffer = NULL; 955 SCpnt->SCp.buffers_residual = 0; 956 957 /* initialize data */ 958 data->msgout_len = 0; 959 data->msgin_len = 0; 960 cur_lunt = &(data->lunt[SCpnt->device->id][SCpnt->device->lun]); 961 cur_lunt->SCpnt = SCpnt; 962 cur_lunt->save_datp = 0; 963 cur_lunt->msgin03 = FALSE; 964 data->cur_lunt = cur_lunt; 965 data->cur_id = SCpnt->device->id; 966 data->cur_lun = SCpnt->device->lun; 967 968 ret = nsp32_setup_sg_table(SCpnt); 969 if (ret == FALSE) { 970 nsp32_msg(KERN_ERR, "SGT fail"); 971 SCpnt->result = DID_ERROR << 16; 972 nsp32_scsi_done(SCpnt); 973 return 0; 974 } 975 976 /* Build IDENTIFY */ 977 nsp32_build_identify(SCpnt); 978 979 /* 980 * If target is the first time to transfer after the reset 981 * (target don't have SDTR_DONE and SDTR_INITIATOR), sync 982 * message SDTR is needed to do synchronous transfer. 983 */ 984 target = &data->target[scmd_id(SCpnt)]; 985 data->cur_target = target; 986 987 if (!(target->sync_flag & (SDTR_DONE | SDTR_INITIATOR | SDTR_TARGET))) { 988 unsigned char period, offset; 989 990 if (trans_mode != ASYNC_MODE) { 991 nsp32_set_max_sync(data, target, &period, &offset); 992 nsp32_build_sdtr(SCpnt, period, offset); 993 target->sync_flag |= SDTR_INITIATOR; 994 } else { 995 nsp32_set_async(data, target); 996 target->sync_flag |= SDTR_DONE; 997 } 998 999 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, 1000 "SDTR: entry: %d start_period: 0x%x offset: 0x%x\n", 1001 target->limit_entry, period, offset); 1002 } else if (target->sync_flag & SDTR_INITIATOR) { 1003 /* 1004 * It was negotiating SDTR with target, sending from the 1005 * initiator, but there are no chance to remove this flag. 1006 * Set async because we don't get proper negotiation. 1007 */ 1008 nsp32_set_async(data, target); 1009 target->sync_flag &= ~SDTR_INITIATOR; 1010 target->sync_flag |= SDTR_DONE; 1011 1012 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, 1013 "SDTR_INITIATOR: fall back to async"); 1014 } else if (target->sync_flag & SDTR_TARGET) { 1015 /* 1016 * It was negotiating SDTR with target, sending from target, 1017 * but there are no chance to remove this flag. Set async 1018 * because we don't get proper negotiation. 1019 */ 1020 nsp32_set_async(data, target); 1021 target->sync_flag &= ~SDTR_TARGET; 1022 target->sync_flag |= SDTR_DONE; 1023 1024 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, 1025 "Unknown SDTR from target is reached, fall back to async."); 1026 } 1027 1028 nsp32_dbg(NSP32_DEBUG_TARGETFLAG, 1029 "target: %d sync_flag: 0x%x syncreg: 0x%x ackwidth: 0x%x", 1030 SCpnt->device->id, target->sync_flag, target->syncreg, 1031 target->ackwidth); 1032 1033 /* Selection */ 1034 if (auto_param == 0) { 1035 ret = nsp32_selection_autopara(SCpnt); 1036 } else { 1037 ret = nsp32_selection_autoscsi(SCpnt); 1038 } 1039 1040 if (ret != TRUE) { 1041 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, "selection fail"); 1042 nsp32_scsi_done(SCpnt); 1043 } 1044 1045 return 0; 1046 } 1047 1048 static DEF_SCSI_QCMD(nsp32_queuecommand) 1049 1050 /* initialize asic */ 1051 static int nsp32hw_init(nsp32_hw_data *data) 1052 { 1053 unsigned int base = data->BaseAddress; 1054 unsigned short irq_stat; 1055 unsigned long lc_reg; 1056 unsigned char power; 1057 1058 lc_reg = nsp32_index_read4(base, CFG_LATE_CACHE); 1059 if ((lc_reg & 0xff00) == 0) { 1060 lc_reg |= (0x20 << 8); 1061 nsp32_index_write2(base, CFG_LATE_CACHE, lc_reg & 0xffff); 1062 } 1063 1064 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK); 1065 nsp32_write2(base, TRANSFER_CONTROL, 0); 1066 nsp32_write4(base, BM_CNT, 0); 1067 nsp32_write2(base, SCSI_EXECUTE_PHASE, 0); 1068 1069 do { 1070 irq_stat = nsp32_read2(base, IRQ_STATUS); 1071 nsp32_dbg(NSP32_DEBUG_INIT, "irq_stat 0x%x", irq_stat); 1072 } while (irq_stat & IRQSTATUS_ANY_IRQ); 1073 1074 /* 1075 * Fill FIFO_FULL_SHLD, FIFO_EMPTY_SHLD. Below parameter is 1076 * designated by specification. 1077 */ 1078 if ((data->trans_method & NSP32_TRANSFER_PIO) || 1079 (data->trans_method & NSP32_TRANSFER_MMIO)) { 1080 nsp32_index_write1(base, FIFO_FULL_SHLD_COUNT, 0x40); 1081 nsp32_index_write1(base, FIFO_EMPTY_SHLD_COUNT, 0x40); 1082 } else if (data->trans_method & NSP32_TRANSFER_BUSMASTER) { 1083 nsp32_index_write1(base, FIFO_FULL_SHLD_COUNT, 0x10); 1084 nsp32_index_write1(base, FIFO_EMPTY_SHLD_COUNT, 0x60); 1085 } else { 1086 nsp32_dbg(NSP32_DEBUG_INIT, "unknown transfer mode"); 1087 } 1088 1089 nsp32_dbg(NSP32_DEBUG_INIT, "full 0x%x emp 0x%x", 1090 nsp32_index_read1(base, FIFO_FULL_SHLD_COUNT), 1091 nsp32_index_read1(base, FIFO_EMPTY_SHLD_COUNT)); 1092 1093 nsp32_index_write1(base, CLOCK_DIV, data->clock); 1094 nsp32_index_write1(base, BM_CYCLE, MEMRD_CMD1 | SGT_AUTO_PARA_MEMED_CMD); 1095 nsp32_write1(base, PARITY_CONTROL, 0); /* parity check is disable */ 1096 1097 /* 1098 * initialize MISC_WRRD register 1099 * 1100 * Note: Designated parameters is obeyed as following: 1101 * MISC_SCSI_DIRECTION_DETECTOR_SELECT: It must be set. 1102 * MISC_MASTER_TERMINATION_SELECT: It must be set. 1103 * MISC_BMREQ_NEGATE_TIMING_SEL: It should be set. 1104 * MISC_AUTOSEL_TIMING_SEL: It should be set. 1105 * MISC_BMSTOP_CHANGE2_NONDATA_PHASE: It should be set. 1106 * MISC_DELAYED_BMSTART: It's selected for safety. 1107 * 1108 * Note: If MISC_BMSTOP_CHANGE2_NONDATA_PHASE is set, then 1109 * we have to set TRANSFERCONTROL_BM_START as 0 and set 1110 * appropriate value before restarting bus master transfer. 1111 */ 1112 nsp32_index_write2(base, MISC_WR, 1113 (SCSI_DIRECTION_DETECTOR_SELECT | 1114 DELAYED_BMSTART | 1115 MASTER_TERMINATION_SELECT | 1116 BMREQ_NEGATE_TIMING_SEL | 1117 AUTOSEL_TIMING_SEL | 1118 BMSTOP_CHANGE2_NONDATA_PHASE)); 1119 1120 nsp32_index_write1(base, TERM_PWR_CONTROL, 0); 1121 power = nsp32_index_read1(base, TERM_PWR_CONTROL); 1122 if (!(power & SENSE)) { 1123 nsp32_msg(KERN_INFO, "term power on"); 1124 nsp32_index_write1(base, TERM_PWR_CONTROL, BPWR); 1125 } 1126 1127 nsp32_write2(base, TIMER_SET, TIMER_STOP); 1128 nsp32_write2(base, TIMER_SET, TIMER_STOP); /* Required 2 times */ 1129 1130 nsp32_write1(base, SYNC_REG, 0); 1131 nsp32_write1(base, ACK_WIDTH, 0); 1132 nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME); 1133 1134 /* 1135 * enable to select designated IRQ (except for 1136 * IRQSELECT_SERR, IRQSELECT_PERR, IRQSELECT_BMCNTERR) 1137 */ 1138 nsp32_index_write2(base, IRQ_SELECT, IRQSELECT_TIMER_IRQ | 1139 IRQSELECT_SCSIRESET_IRQ | 1140 IRQSELECT_FIFO_SHLD_IRQ | 1141 IRQSELECT_RESELECT_IRQ | 1142 IRQSELECT_PHASE_CHANGE_IRQ | 1143 IRQSELECT_AUTO_SCSI_SEQ_IRQ | 1144 // IRQSELECT_BMCNTERR_IRQ | 1145 IRQSELECT_TARGET_ABORT_IRQ | 1146 IRQSELECT_MASTER_ABORT_IRQ ); 1147 nsp32_write2(base, IRQ_CONTROL, 0); 1148 1149 /* PCI LED off */ 1150 nsp32_index_write1(base, EXT_PORT_DDR, LED_OFF); 1151 nsp32_index_write1(base, EXT_PORT, LED_OFF); 1152 1153 return TRUE; 1154 } 1155 1156 1157 /* interrupt routine */ 1158 static irqreturn_t do_nsp32_isr(int irq, void *dev_id) 1159 { 1160 nsp32_hw_data *data = dev_id; 1161 unsigned int base = data->BaseAddress; 1162 struct scsi_cmnd *SCpnt = data->CurrentSC; 1163 unsigned short auto_stat, irq_stat, trans_stat; 1164 unsigned char busmon, busphase; 1165 unsigned long flags; 1166 int ret; 1167 int handled = 0; 1168 struct Scsi_Host *host = data->Host; 1169 1170 spin_lock_irqsave(host->host_lock, flags); 1171 1172 /* 1173 * IRQ check, then enable IRQ mask 1174 */ 1175 irq_stat = nsp32_read2(base, IRQ_STATUS); 1176 nsp32_dbg(NSP32_DEBUG_INTR, 1177 "enter IRQ: %d, IRQstatus: 0x%x", irq, irq_stat); 1178 /* is this interrupt comes from Ninja asic? */ 1179 if ((irq_stat & IRQSTATUS_ANY_IRQ) == 0) { 1180 nsp32_dbg(NSP32_DEBUG_INTR, "shared interrupt: irq other 0x%x", irq_stat); 1181 goto out2; 1182 } 1183 handled = 1; 1184 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK); 1185 1186 busmon = nsp32_read1(base, SCSI_BUS_MONITOR); 1187 busphase = busmon & BUSMON_PHASE_MASK; 1188 1189 trans_stat = nsp32_read2(base, TRANSFER_STATUS); 1190 if ((irq_stat == 0xffff) && (trans_stat == 0xffff)) { 1191 nsp32_msg(KERN_INFO, "card disconnect"); 1192 if (data->CurrentSC != NULL) { 1193 nsp32_msg(KERN_INFO, "clean up current SCSI command"); 1194 SCpnt->result = DID_BAD_TARGET << 16; 1195 nsp32_scsi_done(SCpnt); 1196 } 1197 goto out; 1198 } 1199 1200 /* Timer IRQ */ 1201 if (irq_stat & IRQSTATUS_TIMER_IRQ) { 1202 nsp32_dbg(NSP32_DEBUG_INTR, "timer stop"); 1203 nsp32_write2(base, TIMER_SET, TIMER_STOP); 1204 goto out; 1205 } 1206 1207 /* SCSI reset */ 1208 if (irq_stat & IRQSTATUS_SCSIRESET_IRQ) { 1209 nsp32_msg(KERN_INFO, "detected someone do bus reset"); 1210 nsp32_do_bus_reset(data); 1211 if (SCpnt != NULL) { 1212 SCpnt->result = DID_RESET << 16; 1213 nsp32_scsi_done(SCpnt); 1214 } 1215 goto out; 1216 } 1217 1218 if (SCpnt == NULL) { 1219 nsp32_msg(KERN_WARNING, "SCpnt==NULL this can't be happened"); 1220 nsp32_msg(KERN_WARNING, "irq_stat=0x%x trans_stat=0x%x", irq_stat, trans_stat); 1221 goto out; 1222 } 1223 1224 /* 1225 * AutoSCSI Interrupt. 1226 * Note: This interrupt is occurred when AutoSCSI is finished. Then 1227 * check SCSIEXECUTEPHASE, and do appropriate action. Each phases are 1228 * recorded when AutoSCSI sequencer has been processed. 1229 */ 1230 if(irq_stat & IRQSTATUS_AUTOSCSI_IRQ) { 1231 /* getting SCSI executed phase */ 1232 auto_stat = nsp32_read2(base, SCSI_EXECUTE_PHASE); 1233 nsp32_write2(base, SCSI_EXECUTE_PHASE, 0); 1234 1235 /* Selection Timeout, go busfree phase. */ 1236 if (auto_stat & SELECTION_TIMEOUT) { 1237 nsp32_dbg(NSP32_DEBUG_INTR, 1238 "selection timeout occurred"); 1239 1240 SCpnt->result = DID_TIME_OUT << 16; 1241 nsp32_scsi_done(SCpnt); 1242 goto out; 1243 } 1244 1245 if (auto_stat & MSGOUT_PHASE) { 1246 /* 1247 * MsgOut phase was processed. 1248 * If MSG_IN_OCCUER is not set, then MsgOut phase is 1249 * completed. Thus, msgout_len must reset. Otherwise, 1250 * nothing to do here. If MSG_OUT_OCCUER is occurred, 1251 * then we will encounter the condition and check. 1252 */ 1253 if (!(auto_stat & MSG_IN_OCCUER) && 1254 (data->msgout_len <= 3)) { 1255 /* 1256 * !MSG_IN_OCCUER && msgout_len <=3 1257 * ---> AutoSCSI with MSGOUTreg is processed. 1258 */ 1259 data->msgout_len = 0; 1260 }; 1261 1262 nsp32_dbg(NSP32_DEBUG_INTR, "MsgOut phase processed"); 1263 } 1264 1265 if ((auto_stat & DATA_IN_PHASE) && 1266 (scsi_get_resid(SCpnt) > 0) && 1267 ((nsp32_read2(base, FIFO_REST_CNT) & FIFO_REST_MASK) != 0)) { 1268 printk( "auto+fifo\n"); 1269 //nsp32_pio_read(SCpnt); 1270 } 1271 1272 if (auto_stat & (DATA_IN_PHASE | DATA_OUT_PHASE)) { 1273 /* DATA_IN_PHASE/DATA_OUT_PHASE was processed. */ 1274 nsp32_dbg(NSP32_DEBUG_INTR, 1275 "Data in/out phase processed"); 1276 1277 /* read BMCNT, SGT pointer addr */ 1278 nsp32_dbg(NSP32_DEBUG_INTR, "BMCNT=0x%lx", 1279 nsp32_read4(base, BM_CNT)); 1280 nsp32_dbg(NSP32_DEBUG_INTR, "addr=0x%lx", 1281 nsp32_read4(base, SGT_ADR)); 1282 nsp32_dbg(NSP32_DEBUG_INTR, "SACK=0x%lx", 1283 nsp32_read4(base, SACK_CNT)); 1284 nsp32_dbg(NSP32_DEBUG_INTR, "SSACK=0x%lx", 1285 nsp32_read4(base, SAVED_SACK_CNT)); 1286 1287 scsi_set_resid(SCpnt, 0); /* all data transferred! */ 1288 } 1289 1290 /* 1291 * MsgIn Occur 1292 */ 1293 if (auto_stat & MSG_IN_OCCUER) { 1294 nsp32_msgin_occur(SCpnt, irq_stat, auto_stat); 1295 } 1296 1297 /* 1298 * MsgOut Occur 1299 */ 1300 if (auto_stat & MSG_OUT_OCCUER) { 1301 nsp32_msgout_occur(SCpnt); 1302 } 1303 1304 /* 1305 * Bus Free Occur 1306 */ 1307 if (auto_stat & BUS_FREE_OCCUER) { 1308 ret = nsp32_busfree_occur(SCpnt, auto_stat); 1309 if (ret == TRUE) { 1310 goto out; 1311 } 1312 } 1313 1314 if (auto_stat & STATUS_PHASE) { 1315 /* 1316 * Read CSB and substitute CSB for SCpnt->result 1317 * to save status phase stutas byte. 1318 * scsi error handler checks host_byte (DID_*: 1319 * low level driver to indicate status), then checks 1320 * status_byte (SCSI status byte). 1321 */ 1322 SCpnt->result = (int)nsp32_read1(base, SCSI_CSB_IN); 1323 } 1324 1325 if (auto_stat & ILLEGAL_PHASE) { 1326 /* Illegal phase is detected. SACK is not back. */ 1327 nsp32_msg(KERN_WARNING, 1328 "AUTO SCSI ILLEGAL PHASE OCCUR!!!!"); 1329 1330 /* TODO: currently we don't have any action... bus reset? */ 1331 1332 /* 1333 * To send back SACK, assert, wait, and negate. 1334 */ 1335 nsp32_sack_assert(data); 1336 nsp32_wait_req(data, NEGATE); 1337 nsp32_sack_negate(data); 1338 1339 } 1340 1341 if (auto_stat & COMMAND_PHASE) { 1342 /* nothing to do */ 1343 nsp32_dbg(NSP32_DEBUG_INTR, "Command phase processed"); 1344 } 1345 1346 if (auto_stat & AUTOSCSI_BUSY) { 1347 /* AutoSCSI is running */ 1348 } 1349 1350 show_autophase(auto_stat); 1351 } 1352 1353 /* FIFO_SHLD_IRQ */ 1354 if (irq_stat & IRQSTATUS_FIFO_SHLD_IRQ) { 1355 nsp32_dbg(NSP32_DEBUG_INTR, "FIFO IRQ"); 1356 1357 switch(busphase) { 1358 case BUSPHASE_DATA_OUT: 1359 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/write"); 1360 1361 //nsp32_pio_write(SCpnt); 1362 1363 break; 1364 1365 case BUSPHASE_DATA_IN: 1366 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/read"); 1367 1368 //nsp32_pio_read(SCpnt); 1369 1370 break; 1371 1372 case BUSPHASE_STATUS: 1373 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/status"); 1374 1375 SCpnt->SCp.Status = nsp32_read1(base, SCSI_CSB_IN); 1376 1377 break; 1378 default: 1379 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/other phase"); 1380 nsp32_dbg(NSP32_DEBUG_INTR, "irq_stat=0x%x trans_stat=0x%x", irq_stat, trans_stat); 1381 show_busphase(busphase); 1382 break; 1383 } 1384 1385 goto out; 1386 } 1387 1388 /* Phase Change IRQ */ 1389 if (irq_stat & IRQSTATUS_PHASE_CHANGE_IRQ) { 1390 nsp32_dbg(NSP32_DEBUG_INTR, "phase change IRQ"); 1391 1392 switch(busphase) { 1393 case BUSPHASE_MESSAGE_IN: 1394 nsp32_dbg(NSP32_DEBUG_INTR, "phase chg/msg in"); 1395 nsp32_msgin_occur(SCpnt, irq_stat, 0); 1396 break; 1397 default: 1398 nsp32_msg(KERN_WARNING, "phase chg/other phase?"); 1399 nsp32_msg(KERN_WARNING, "irq_stat=0x%x trans_stat=0x%x\n", 1400 irq_stat, trans_stat); 1401 show_busphase(busphase); 1402 break; 1403 } 1404 goto out; 1405 } 1406 1407 /* PCI_IRQ */ 1408 if (irq_stat & IRQSTATUS_PCI_IRQ) { 1409 nsp32_dbg(NSP32_DEBUG_INTR, "PCI IRQ occurred"); 1410 /* Do nothing */ 1411 } 1412 1413 /* BMCNTERR_IRQ */ 1414 if (irq_stat & IRQSTATUS_BMCNTERR_IRQ) { 1415 nsp32_msg(KERN_ERR, "Received unexpected BMCNTERR IRQ! "); 1416 /* 1417 * TODO: To be implemented improving bus master 1418 * transfer reliability when BMCNTERR is occurred in 1419 * AutoSCSI phase described in specification. 1420 */ 1421 } 1422 1423 #if 0 1424 nsp32_dbg(NSP32_DEBUG_INTR, 1425 "irq_stat=0x%x trans_stat=0x%x", irq_stat, trans_stat); 1426 show_busphase(busphase); 1427 #endif 1428 1429 out: 1430 /* disable IRQ mask */ 1431 nsp32_write2(base, IRQ_CONTROL, 0); 1432 1433 out2: 1434 spin_unlock_irqrestore(host->host_lock, flags); 1435 1436 nsp32_dbg(NSP32_DEBUG_INTR, "exit"); 1437 1438 return IRQ_RETVAL(handled); 1439 } 1440 1441 1442 static int nsp32_show_info(struct seq_file *m, struct Scsi_Host *host) 1443 { 1444 unsigned long flags; 1445 nsp32_hw_data *data; 1446 int hostno; 1447 unsigned int base; 1448 unsigned char mode_reg; 1449 int id, speed; 1450 long model; 1451 1452 hostno = host->host_no; 1453 data = (nsp32_hw_data *)host->hostdata; 1454 base = host->io_port; 1455 1456 seq_puts(m, "NinjaSCSI-32 status\n\n"); 1457 seq_printf(m, "Driver version: %s, $Revision: 1.33 $\n", nsp32_release_version); 1458 seq_printf(m, "SCSI host No.: %d\n", hostno); 1459 seq_printf(m, "IRQ: %d\n", host->irq); 1460 seq_printf(m, "IO: 0x%lx-0x%lx\n", host->io_port, host->io_port + host->n_io_port - 1); 1461 seq_printf(m, "MMIO(virtual address): 0x%lx-0x%lx\n", host->base, host->base + data->MmioLength - 1); 1462 seq_printf(m, "sg_tablesize: %d\n", host->sg_tablesize); 1463 seq_printf(m, "Chip revision: 0x%x\n", (nsp32_read2(base, INDEX_REG) >> 8) & 0xff); 1464 1465 mode_reg = nsp32_index_read1(base, CHIP_MODE); 1466 model = data->pci_devid->driver_data; 1467 1468 #ifdef CONFIG_PM 1469 seq_printf(m, "Power Management: %s\n", (mode_reg & OPTF) ? "yes" : "no"); 1470 #endif 1471 seq_printf(m, "OEM: %ld, %s\n", (mode_reg & (OEM0|OEM1)), nsp32_model[model]); 1472 1473 spin_lock_irqsave(&(data->Lock), flags); 1474 seq_printf(m, "CurrentSC: 0x%p\n\n", data->CurrentSC); 1475 spin_unlock_irqrestore(&(data->Lock), flags); 1476 1477 1478 seq_puts(m, "SDTR status\n"); 1479 for (id = 0; id < ARRAY_SIZE(data->target); id++) { 1480 1481 seq_printf(m, "id %d: ", id); 1482 1483 if (id == host->this_id) { 1484 seq_puts(m, "----- NinjaSCSI-32 host adapter\n"); 1485 continue; 1486 } 1487 1488 if (data->target[id].sync_flag == SDTR_DONE) { 1489 if (data->target[id].period == 0 && 1490 data->target[id].offset == ASYNC_OFFSET ) { 1491 seq_puts(m, "async"); 1492 } else { 1493 seq_puts(m, " sync"); 1494 } 1495 } else { 1496 seq_puts(m, " none"); 1497 } 1498 1499 if (data->target[id].period != 0) { 1500 1501 speed = 1000000 / (data->target[id].period * 4); 1502 1503 seq_printf(m, " transfer %d.%dMB/s, offset %d", 1504 speed / 1000, 1505 speed % 1000, 1506 data->target[id].offset 1507 ); 1508 } 1509 seq_putc(m, '\n'); 1510 } 1511 return 0; 1512 } 1513 1514 1515 1516 /* 1517 * Reset parameters and call scsi_done for data->cur_lunt. 1518 * Be careful setting SCpnt->result = DID_* before calling this function. 1519 */ 1520 static void nsp32_scsi_done(struct scsi_cmnd *SCpnt) 1521 { 1522 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 1523 unsigned int base = SCpnt->device->host->io_port; 1524 1525 scsi_dma_unmap(SCpnt); 1526 1527 /* 1528 * clear TRANSFERCONTROL_BM_START 1529 */ 1530 nsp32_write2(base, TRANSFER_CONTROL, 0); 1531 nsp32_write4(base, BM_CNT, 0); 1532 1533 /* 1534 * call scsi_done 1535 */ 1536 (*SCpnt->scsi_done)(SCpnt); 1537 1538 /* 1539 * reset parameters 1540 */ 1541 data->cur_lunt->SCpnt = NULL; 1542 data->cur_lunt = NULL; 1543 data->cur_target = NULL; 1544 data->CurrentSC = NULL; 1545 } 1546 1547 1548 /* 1549 * Bus Free Occur 1550 * 1551 * Current Phase is BUSFREE. AutoSCSI is automatically execute BUSFREE phase 1552 * with ACK reply when below condition is matched: 1553 * MsgIn 00: Command Complete. 1554 * MsgIn 02: Save Data Pointer. 1555 * MsgIn 04: Diconnect. 1556 * In other case, unexpected BUSFREE is detected. 1557 */ 1558 static int nsp32_busfree_occur(struct scsi_cmnd *SCpnt, unsigned short execph) 1559 { 1560 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 1561 unsigned int base = SCpnt->device->host->io_port; 1562 1563 nsp32_dbg(NSP32_DEBUG_BUSFREE, "enter execph=0x%x", execph); 1564 show_autophase(execph); 1565 1566 nsp32_write4(base, BM_CNT, 0); 1567 nsp32_write2(base, TRANSFER_CONTROL, 0); 1568 1569 /* 1570 * MsgIn 02: Save Data Pointer 1571 * 1572 * VALID: 1573 * Save Data Pointer is received. Adjust pointer. 1574 * 1575 * NO-VALID: 1576 * SCSI-3 says if Save Data Pointer is not received, then we restart 1577 * processing and we can't adjust any SCSI data pointer in next data 1578 * phase. 1579 */ 1580 if (execph & MSGIN_02_VALID) { 1581 nsp32_dbg(NSP32_DEBUG_BUSFREE, "MsgIn02_Valid"); 1582 1583 /* 1584 * Check sack_cnt/saved_sack_cnt, then adjust sg table if 1585 * needed. 1586 */ 1587 if (!(execph & MSGIN_00_VALID) && 1588 ((execph & DATA_IN_PHASE) || (execph & DATA_OUT_PHASE))) { 1589 unsigned int sacklen, s_sacklen; 1590 1591 /* 1592 * Read SACK count and SAVEDSACK count, then compare. 1593 */ 1594 sacklen = nsp32_read4(base, SACK_CNT ); 1595 s_sacklen = nsp32_read4(base, SAVED_SACK_CNT); 1596 1597 /* 1598 * If SAVEDSACKCNT == 0, it means SavedDataPointer is 1599 * come after data transferring. 1600 */ 1601 if (s_sacklen > 0) { 1602 /* 1603 * Comparing between sack and savedsack to 1604 * check the condition of AutoMsgIn03. 1605 * 1606 * If they are same, set msgin03 == TRUE, 1607 * COMMANDCONTROL_AUTO_MSGIN_03 is enabled at 1608 * reselection. On the other hand, if they 1609 * aren't same, set msgin03 == FALSE, and 1610 * COMMANDCONTROL_AUTO_MSGIN_03 is disabled at 1611 * reselection. 1612 */ 1613 if (sacklen != s_sacklen) { 1614 data->cur_lunt->msgin03 = FALSE; 1615 } else { 1616 data->cur_lunt->msgin03 = TRUE; 1617 } 1618 1619 nsp32_adjust_busfree(SCpnt, s_sacklen); 1620 } 1621 } 1622 1623 /* This value has not substitude with valid value yet... */ 1624 //data->cur_lunt->save_datp = data->cur_datp; 1625 } else { 1626 /* 1627 * no processing. 1628 */ 1629 } 1630 1631 if (execph & MSGIN_03_VALID) { 1632 /* MsgIn03 was valid to be processed. No need processing. */ 1633 } 1634 1635 /* 1636 * target SDTR check 1637 */ 1638 if (data->cur_target->sync_flag & SDTR_INITIATOR) { 1639 /* 1640 * SDTR negotiation pulled by the initiator has not 1641 * finished yet. Fall back to ASYNC mode. 1642 */ 1643 nsp32_set_async(data, data->cur_target); 1644 data->cur_target->sync_flag &= ~SDTR_INITIATOR; 1645 data->cur_target->sync_flag |= SDTR_DONE; 1646 } else if (data->cur_target->sync_flag & SDTR_TARGET) { 1647 /* 1648 * SDTR negotiation pulled by the target has been 1649 * negotiating. 1650 */ 1651 if (execph & (MSGIN_00_VALID | MSGIN_04_VALID)) { 1652 /* 1653 * If valid message is received, then 1654 * negotiation is succeeded. 1655 */ 1656 } else { 1657 /* 1658 * On the contrary, if unexpected bus free is 1659 * occurred, then negotiation is failed. Fall 1660 * back to ASYNC mode. 1661 */ 1662 nsp32_set_async(data, data->cur_target); 1663 } 1664 data->cur_target->sync_flag &= ~SDTR_TARGET; 1665 data->cur_target->sync_flag |= SDTR_DONE; 1666 } 1667 1668 /* 1669 * It is always ensured by SCSI standard that initiator 1670 * switches into Bus Free Phase after 1671 * receiving message 00 (Command Complete), 04 (Disconnect). 1672 * It's the reason that processing here is valid. 1673 */ 1674 if (execph & MSGIN_00_VALID) { 1675 /* MsgIn 00: Command Complete */ 1676 nsp32_dbg(NSP32_DEBUG_BUSFREE, "command complete"); 1677 1678 SCpnt->SCp.Status = nsp32_read1(base, SCSI_CSB_IN); 1679 SCpnt->SCp.Message = 0; 1680 nsp32_dbg(NSP32_DEBUG_BUSFREE, 1681 "normal end stat=0x%x resid=0x%x\n", 1682 SCpnt->SCp.Status, scsi_get_resid(SCpnt)); 1683 SCpnt->result = (DID_OK << 16) | 1684 (SCpnt->SCp.Message << 8) | 1685 (SCpnt->SCp.Status << 0); 1686 nsp32_scsi_done(SCpnt); 1687 /* All operation is done */ 1688 return TRUE; 1689 } else if (execph & MSGIN_04_VALID) { 1690 /* MsgIn 04: Disconnect */ 1691 SCpnt->SCp.Status = nsp32_read1(base, SCSI_CSB_IN); 1692 SCpnt->SCp.Message = 4; 1693 1694 nsp32_dbg(NSP32_DEBUG_BUSFREE, "disconnect"); 1695 return TRUE; 1696 } else { 1697 /* Unexpected bus free */ 1698 nsp32_msg(KERN_WARNING, "unexpected bus free occurred"); 1699 1700 /* DID_ERROR? */ 1701 //SCpnt->result = (DID_OK << 16) | (SCpnt->SCp.Message << 8) | (SCpnt->SCp.Status << 0); 1702 SCpnt->result = DID_ERROR << 16; 1703 nsp32_scsi_done(SCpnt); 1704 return TRUE; 1705 } 1706 return FALSE; 1707 } 1708 1709 1710 /* 1711 * nsp32_adjust_busfree - adjusting SG table 1712 * 1713 * Note: This driver adjust the SG table using SCSI ACK 1714 * counter instead of BMCNT counter! 1715 */ 1716 static void nsp32_adjust_busfree(struct scsi_cmnd *SCpnt, unsigned int s_sacklen) 1717 { 1718 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 1719 int old_entry = data->cur_entry; 1720 int new_entry; 1721 int sg_num = data->cur_lunt->sg_num; 1722 nsp32_sgtable *sgt = data->cur_lunt->sglun->sgt; 1723 unsigned int restlen, sentlen; 1724 u32_le len, addr; 1725 1726 nsp32_dbg(NSP32_DEBUG_SGLIST, "old resid=0x%x", scsi_get_resid(SCpnt)); 1727 1728 /* adjust saved SACK count with 4 byte start address boundary */ 1729 s_sacklen -= le32_to_cpu(sgt[old_entry].addr) & 3; 1730 1731 /* 1732 * calculate new_entry from sack count and each sgt[].len 1733 * calculate the byte which is intent to send 1734 */ 1735 sentlen = 0; 1736 for (new_entry = old_entry; new_entry < sg_num; new_entry++) { 1737 sentlen += (le32_to_cpu(sgt[new_entry].len) & ~SGTEND); 1738 if (sentlen > s_sacklen) { 1739 break; 1740 } 1741 } 1742 1743 /* all sgt is processed */ 1744 if (new_entry == sg_num) { 1745 goto last; 1746 } 1747 1748 if (sentlen == s_sacklen) { 1749 /* XXX: confirm it's ok or not */ 1750 /* In this case, it's ok because we are at 1751 the head element of the sg. restlen is correctly calculated. */ 1752 } 1753 1754 /* calculate the rest length for transferring */ 1755 restlen = sentlen - s_sacklen; 1756 1757 /* update adjusting current SG table entry */ 1758 len = le32_to_cpu(sgt[new_entry].len); 1759 addr = le32_to_cpu(sgt[new_entry].addr); 1760 addr += (len - restlen); 1761 sgt[new_entry].addr = cpu_to_le32(addr); 1762 sgt[new_entry].len = cpu_to_le32(restlen); 1763 1764 /* set cur_entry with new_entry */ 1765 data->cur_entry = new_entry; 1766 1767 return; 1768 1769 last: 1770 if (scsi_get_resid(SCpnt) < sentlen) { 1771 nsp32_msg(KERN_ERR, "resid underflow"); 1772 } 1773 1774 scsi_set_resid(SCpnt, scsi_get_resid(SCpnt) - sentlen); 1775 nsp32_dbg(NSP32_DEBUG_SGLIST, "new resid=0x%x", scsi_get_resid(SCpnt)); 1776 1777 /* update hostdata and lun */ 1778 1779 return; 1780 } 1781 1782 1783 /* 1784 * It's called MsgOut phase occur. 1785 * NinjaSCSI-32Bi/UDE automatically processes up to 3 messages in 1786 * message out phase. It, however, has more than 3 messages, 1787 * HBA creates the interrupt and we have to process by hand. 1788 */ 1789 static void nsp32_msgout_occur(struct scsi_cmnd *SCpnt) 1790 { 1791 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 1792 unsigned int base = SCpnt->device->host->io_port; 1793 //unsigned short command; 1794 long new_sgtp; 1795 int i; 1796 1797 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR, 1798 "enter: msgout_len: 0x%x", data->msgout_len); 1799 1800 /* 1801 * If MsgOut phase is occurred without having any 1802 * message, then No_Operation is sent (SCSI-2). 1803 */ 1804 if (data->msgout_len == 0) { 1805 nsp32_build_nop(SCpnt); 1806 } 1807 1808 /* 1809 * Set SGTP ADDR current entry for restarting AUTOSCSI, 1810 * because SGTP is incremented next point. 1811 * There is few statement in the specification... 1812 */ 1813 new_sgtp = data->cur_lunt->sglun_paddr + 1814 (data->cur_lunt->cur_entry * sizeof(nsp32_sgtable)); 1815 1816 /* 1817 * send messages 1818 */ 1819 for (i = 0; i < data->msgout_len; i++) { 1820 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR, 1821 "%d : 0x%x", i, data->msgoutbuf[i]); 1822 1823 /* 1824 * Check REQ is asserted. 1825 */ 1826 nsp32_wait_req(data, ASSERT); 1827 1828 if (i == (data->msgout_len - 1)) { 1829 /* 1830 * If the last message, set the AutoSCSI restart 1831 * before send back the ack message. AutoSCSI 1832 * restart automatically negate ATN signal. 1833 */ 1834 //command = (AUTO_MSGIN_00_OR_04 | AUTO_MSGIN_02); 1835 //nsp32_restart_autoscsi(SCpnt, command); 1836 nsp32_write2(base, COMMAND_CONTROL, 1837 (CLEAR_CDB_FIFO_POINTER | 1838 AUTO_COMMAND_PHASE | 1839 AUTOSCSI_RESTART | 1840 AUTO_MSGIN_00_OR_04 | 1841 AUTO_MSGIN_02 )); 1842 } 1843 /* 1844 * Write data with SACK, then wait sack is 1845 * automatically negated. 1846 */ 1847 nsp32_write1(base, SCSI_DATA_WITH_ACK, data->msgoutbuf[i]); 1848 nsp32_wait_sack(data, NEGATE); 1849 1850 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR, "bus: 0x%x\n", 1851 nsp32_read1(base, SCSI_BUS_MONITOR)); 1852 }; 1853 1854 data->msgout_len = 0; 1855 1856 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR, "exit"); 1857 } 1858 1859 /* 1860 * Restart AutoSCSI 1861 * 1862 * Note: Restarting AutoSCSI needs set: 1863 * SYNC_REG, ACK_WIDTH, SGT_ADR, TRANSFER_CONTROL 1864 */ 1865 static void nsp32_restart_autoscsi(struct scsi_cmnd *SCpnt, unsigned short command) 1866 { 1867 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 1868 unsigned int base = data->BaseAddress; 1869 unsigned short transfer = 0; 1870 1871 nsp32_dbg(NSP32_DEBUG_RESTART, "enter"); 1872 1873 if (data->cur_target == NULL || data->cur_lunt == NULL) { 1874 nsp32_msg(KERN_ERR, "Target or Lun is invalid"); 1875 } 1876 1877 /* 1878 * set SYNC_REG 1879 * Don't set BM_START_ADR before setting this register. 1880 */ 1881 nsp32_write1(base, SYNC_REG, data->cur_target->syncreg); 1882 1883 /* 1884 * set ACKWIDTH 1885 */ 1886 nsp32_write1(base, ACK_WIDTH, data->cur_target->ackwidth); 1887 1888 /* 1889 * set SREQ hazard killer sampling rate 1890 */ 1891 nsp32_write1(base, SREQ_SMPL_RATE, data->cur_target->sample_reg); 1892 1893 /* 1894 * set SGT ADDR (physical address) 1895 */ 1896 nsp32_write4(base, SGT_ADR, data->cur_lunt->sglun_paddr); 1897 1898 /* 1899 * set TRANSFER CONTROL REG 1900 */ 1901 transfer = 0; 1902 transfer |= (TRANSFER_GO | ALL_COUNTER_CLR); 1903 if (data->trans_method & NSP32_TRANSFER_BUSMASTER) { 1904 if (scsi_bufflen(SCpnt) > 0) { 1905 transfer |= BM_START; 1906 } 1907 } else if (data->trans_method & NSP32_TRANSFER_MMIO) { 1908 transfer |= CB_MMIO_MODE; 1909 } else if (data->trans_method & NSP32_TRANSFER_PIO) { 1910 transfer |= CB_IO_MODE; 1911 } 1912 nsp32_write2(base, TRANSFER_CONTROL, transfer); 1913 1914 /* 1915 * restart AutoSCSI 1916 * 1917 * TODO: COMMANDCONTROL_AUTO_COMMAND_PHASE is needed ? 1918 */ 1919 command |= (CLEAR_CDB_FIFO_POINTER | 1920 AUTO_COMMAND_PHASE | 1921 AUTOSCSI_RESTART ); 1922 nsp32_write2(base, COMMAND_CONTROL, command); 1923 1924 nsp32_dbg(NSP32_DEBUG_RESTART, "exit"); 1925 } 1926 1927 1928 /* 1929 * cannot run automatically message in occur 1930 */ 1931 static void nsp32_msgin_occur(struct scsi_cmnd *SCpnt, 1932 unsigned long irq_status, 1933 unsigned short execph) 1934 { 1935 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 1936 unsigned int base = SCpnt->device->host->io_port; 1937 unsigned char msg; 1938 unsigned char msgtype; 1939 unsigned char newlun; 1940 unsigned short command = 0; 1941 int msgclear = TRUE; 1942 long new_sgtp; 1943 int ret; 1944 1945 /* 1946 * read first message 1947 * Use SCSIDATA_W_ACK instead of SCSIDATAIN, because the procedure 1948 * of Message-In have to be processed before sending back SCSI ACK. 1949 */ 1950 msg = nsp32_read1(base, SCSI_DATA_IN); 1951 data->msginbuf[(unsigned char)data->msgin_len] = msg; 1952 msgtype = data->msginbuf[0]; 1953 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, 1954 "enter: msglen: 0x%x msgin: 0x%x msgtype: 0x%x", 1955 data->msgin_len, msg, msgtype); 1956 1957 /* 1958 * TODO: We need checking whether bus phase is message in? 1959 */ 1960 1961 /* 1962 * assert SCSI ACK 1963 */ 1964 nsp32_sack_assert(data); 1965 1966 /* 1967 * processing IDENTIFY 1968 */ 1969 if (msgtype & 0x80) { 1970 if (!(irq_status & IRQSTATUS_RESELECT_OCCUER)) { 1971 /* Invalid (non reselect) phase */ 1972 goto reject; 1973 } 1974 1975 newlun = msgtype & 0x1f; /* TODO: SPI-3 compliant? */ 1976 ret = nsp32_reselection(SCpnt, newlun); 1977 if (ret == TRUE) { 1978 goto restart; 1979 } else { 1980 goto reject; 1981 } 1982 } 1983 1984 /* 1985 * processing messages except for IDENTIFY 1986 * 1987 * TODO: Messages are all SCSI-2 terminology. SCSI-3 compliance is TODO. 1988 */ 1989 switch (msgtype) { 1990 /* 1991 * 1-byte message 1992 */ 1993 case COMMAND_COMPLETE: 1994 case DISCONNECT: 1995 /* 1996 * These messages should not be occurred. 1997 * They should be processed on AutoSCSI sequencer. 1998 */ 1999 nsp32_msg(KERN_WARNING, 2000 "unexpected message of AutoSCSI MsgIn: 0x%x", msg); 2001 break; 2002 2003 case RESTORE_POINTERS: 2004 /* 2005 * AutoMsgIn03 is disabled, and HBA gets this message. 2006 */ 2007 2008 if ((execph & DATA_IN_PHASE) || (execph & DATA_OUT_PHASE)) { 2009 unsigned int s_sacklen; 2010 2011 s_sacklen = nsp32_read4(base, SAVED_SACK_CNT); 2012 if ((execph & MSGIN_02_VALID) && (s_sacklen > 0)) { 2013 nsp32_adjust_busfree(SCpnt, s_sacklen); 2014 } else { 2015 /* No need to rewrite SGT */ 2016 } 2017 } 2018 data->cur_lunt->msgin03 = FALSE; 2019 2020 /* Update with the new value */ 2021 2022 /* reset SACK/SavedACK counter (or ALL clear?) */ 2023 nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK); 2024 2025 /* 2026 * set new sg pointer 2027 */ 2028 new_sgtp = data->cur_lunt->sglun_paddr + 2029 (data->cur_lunt->cur_entry * sizeof(nsp32_sgtable)); 2030 nsp32_write4(base, SGT_ADR, new_sgtp); 2031 2032 break; 2033 2034 case SAVE_POINTERS: 2035 /* 2036 * These messages should not be occurred. 2037 * They should be processed on AutoSCSI sequencer. 2038 */ 2039 nsp32_msg (KERN_WARNING, 2040 "unexpected message of AutoSCSI MsgIn: SAVE_POINTERS"); 2041 2042 break; 2043 2044 case MESSAGE_REJECT: 2045 /* If previous message_out is sending SDTR, and get 2046 message_reject from target, SDTR negotiation is failed */ 2047 if (data->cur_target->sync_flag & 2048 (SDTR_INITIATOR | SDTR_TARGET)) { 2049 /* 2050 * Current target is negotiating SDTR, but it's 2051 * failed. Fall back to async transfer mode, and set 2052 * SDTR_DONE. 2053 */ 2054 nsp32_set_async(data, data->cur_target); 2055 data->cur_target->sync_flag &= ~SDTR_INITIATOR; 2056 data->cur_target->sync_flag |= SDTR_DONE; 2057 2058 } 2059 break; 2060 2061 case LINKED_CMD_COMPLETE: 2062 case LINKED_FLG_CMD_COMPLETE: 2063 /* queue tag is not supported currently */ 2064 nsp32_msg (KERN_WARNING, 2065 "unsupported message: 0x%x", msgtype); 2066 break; 2067 2068 case INITIATE_RECOVERY: 2069 /* staring ECA (Extended Contingent Allegiance) state. */ 2070 /* This message is declined in SPI2 or later. */ 2071 2072 goto reject; 2073 2074 /* 2075 * 2-byte message 2076 */ 2077 case SIMPLE_QUEUE_TAG: 2078 case 0x23: 2079 /* 2080 * 0x23: Ignore_Wide_Residue is not declared in scsi.h. 2081 * No support is needed. 2082 */ 2083 if (data->msgin_len >= 1) { 2084 goto reject; 2085 } 2086 2087 /* current position is 1-byte of 2 byte */ 2088 msgclear = FALSE; 2089 2090 break; 2091 2092 /* 2093 * extended message 2094 */ 2095 case EXTENDED_MESSAGE: 2096 if (data->msgin_len < 1) { 2097 /* 2098 * Current position does not reach 2-byte 2099 * (2-byte is extended message length). 2100 */ 2101 msgclear = FALSE; 2102 break; 2103 } 2104 2105 if ((data->msginbuf[1] + 1) > data->msgin_len) { 2106 /* 2107 * Current extended message has msginbuf[1] + 2 2108 * (msgin_len starts counting from 0, so buf[1] + 1). 2109 * If current message position is not finished, 2110 * continue receiving message. 2111 */ 2112 msgclear = FALSE; 2113 break; 2114 } 2115 2116 /* 2117 * Reach here means regular length of each type of 2118 * extended messages. 2119 */ 2120 switch (data->msginbuf[2]) { 2121 case EXTENDED_MODIFY_DATA_POINTER: 2122 /* TODO */ 2123 goto reject; /* not implemented yet */ 2124 break; 2125 2126 case EXTENDED_SDTR: 2127 /* 2128 * Exchange this message between initiator and target. 2129 */ 2130 if (data->msgin_len != EXTENDED_SDTR_LEN + 1) { 2131 /* 2132 * received inappropriate message. 2133 */ 2134 goto reject; 2135 break; 2136 } 2137 2138 nsp32_analyze_sdtr(SCpnt); 2139 2140 break; 2141 2142 case EXTENDED_EXTENDED_IDENTIFY: 2143 /* SCSI-I only, not supported. */ 2144 goto reject; /* not implemented yet */ 2145 2146 break; 2147 2148 case EXTENDED_WDTR: 2149 goto reject; /* not implemented yet */ 2150 2151 break; 2152 2153 default: 2154 goto reject; 2155 } 2156 break; 2157 2158 default: 2159 goto reject; 2160 } 2161 2162 restart: 2163 if (msgclear == TRUE) { 2164 data->msgin_len = 0; 2165 2166 /* 2167 * If restarting AutoSCSI, but there are some message to out 2168 * (msgout_len > 0), set AutoATN, and set SCSIMSGOUT as 0 2169 * (MV_VALID = 0). When commandcontrol is written with 2170 * AutoSCSI restart, at the same time MsgOutOccur should be 2171 * happened (however, such situation is really possible...?). 2172 */ 2173 if (data->msgout_len > 0) { 2174 nsp32_write4(base, SCSI_MSG_OUT, 0); 2175 command |= AUTO_ATN; 2176 } 2177 2178 /* 2179 * restart AutoSCSI 2180 * If it's failed, COMMANDCONTROL_AUTO_COMMAND_PHASE is needed. 2181 */ 2182 command |= (AUTO_MSGIN_00_OR_04 | AUTO_MSGIN_02); 2183 2184 /* 2185 * If current msgin03 is TRUE, then flag on. 2186 */ 2187 if (data->cur_lunt->msgin03 == TRUE) { 2188 command |= AUTO_MSGIN_03; 2189 } 2190 data->cur_lunt->msgin03 = FALSE; 2191 } else { 2192 data->msgin_len++; 2193 } 2194 2195 /* 2196 * restart AutoSCSI 2197 */ 2198 nsp32_restart_autoscsi(SCpnt, command); 2199 2200 /* 2201 * wait SCSI REQ negate for REQ-ACK handshake 2202 */ 2203 nsp32_wait_req(data, NEGATE); 2204 2205 /* 2206 * negate SCSI ACK 2207 */ 2208 nsp32_sack_negate(data); 2209 2210 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "exit"); 2211 2212 return; 2213 2214 reject: 2215 nsp32_msg(KERN_WARNING, 2216 "invalid or unsupported MessageIn, rejected. " 2217 "current msg: 0x%x (len: 0x%x), processing msg: 0x%x", 2218 msg, data->msgin_len, msgtype); 2219 nsp32_build_reject(SCpnt); 2220 data->msgin_len = 0; 2221 2222 goto restart; 2223 } 2224 2225 /* 2226 * 2227 */ 2228 static void nsp32_analyze_sdtr(struct scsi_cmnd *SCpnt) 2229 { 2230 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 2231 nsp32_target *target = data->cur_target; 2232 nsp32_sync_table *synct; 2233 unsigned char get_period = data->msginbuf[3]; 2234 unsigned char get_offset = data->msginbuf[4]; 2235 int entry; 2236 int syncnum; 2237 2238 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "enter"); 2239 2240 synct = data->synct; 2241 syncnum = data->syncnum; 2242 2243 /* 2244 * If this inititor sent the SDTR message, then target responds SDTR, 2245 * initiator SYNCREG, ACKWIDTH from SDTR parameter. 2246 * Messages are not appropriate, then send back reject message. 2247 * If initiator did not send the SDTR, but target sends SDTR, 2248 * initiator calculator the appropriate parameter and send back SDTR. 2249 */ 2250 if (target->sync_flag & SDTR_INITIATOR) { 2251 /* 2252 * Initiator sent SDTR, the target responds and 2253 * send back negotiation SDTR. 2254 */ 2255 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "target responds SDTR"); 2256 2257 target->sync_flag &= ~SDTR_INITIATOR; 2258 target->sync_flag |= SDTR_DONE; 2259 2260 /* 2261 * offset: 2262 */ 2263 if (get_offset > SYNC_OFFSET) { 2264 /* 2265 * Negotiation is failed, the target send back 2266 * unexpected offset value. 2267 */ 2268 goto reject; 2269 } 2270 2271 if (get_offset == ASYNC_OFFSET) { 2272 /* 2273 * Negotiation is succeeded, the target want 2274 * to fall back into asynchronous transfer mode. 2275 */ 2276 goto async; 2277 } 2278 2279 /* 2280 * period: 2281 * Check whether sync period is too short. If too short, 2282 * fall back to async mode. If it's ok, then investigate 2283 * the received sync period. If sync period is acceptable 2284 * between sync table start_period and end_period, then 2285 * set this I_T nexus as sent offset and period. 2286 * If it's not acceptable, send back reject and fall back 2287 * to async mode. 2288 */ 2289 if (get_period < data->synct[0].period_num) { 2290 /* 2291 * Negotiation is failed, the target send back 2292 * unexpected period value. 2293 */ 2294 goto reject; 2295 } 2296 2297 entry = nsp32_search_period_entry(data, target, get_period); 2298 2299 if (entry < 0) { 2300 /* 2301 * Target want to use long period which is not 2302 * acceptable NinjaSCSI-32Bi/UDE. 2303 */ 2304 goto reject; 2305 } 2306 2307 /* 2308 * Set new sync table and offset in this I_T nexus. 2309 */ 2310 nsp32_set_sync_entry(data, target, entry, get_offset); 2311 } else { 2312 /* Target send SDTR to initiator. */ 2313 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "target send SDTR"); 2314 2315 target->sync_flag |= SDTR_INITIATOR; 2316 2317 /* offset: */ 2318 if (get_offset > SYNC_OFFSET) { 2319 /* send back as SYNC_OFFSET */ 2320 get_offset = SYNC_OFFSET; 2321 } 2322 2323 /* period: */ 2324 if (get_period < data->synct[0].period_num) { 2325 get_period = data->synct[0].period_num; 2326 } 2327 2328 entry = nsp32_search_period_entry(data, target, get_period); 2329 2330 if (get_offset == ASYNC_OFFSET || entry < 0) { 2331 nsp32_set_async(data, target); 2332 nsp32_build_sdtr(SCpnt, 0, ASYNC_OFFSET); 2333 } else { 2334 nsp32_set_sync_entry(data, target, entry, get_offset); 2335 nsp32_build_sdtr(SCpnt, get_period, get_offset); 2336 } 2337 } 2338 2339 target->period = get_period; 2340 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "exit"); 2341 return; 2342 2343 reject: 2344 /* 2345 * If the current message is unacceptable, send back to the target 2346 * with reject message. 2347 */ 2348 nsp32_build_reject(SCpnt); 2349 2350 async: 2351 nsp32_set_async(data, target); /* set as ASYNC transfer mode */ 2352 2353 target->period = 0; 2354 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "exit: set async"); 2355 return; 2356 } 2357 2358 2359 /* 2360 * Search config entry number matched in sync_table from given 2361 * target and speed period value. If failed to search, return negative value. 2362 */ 2363 static int nsp32_search_period_entry(nsp32_hw_data *data, 2364 nsp32_target *target, 2365 unsigned char period) 2366 { 2367 int i; 2368 2369 if (target->limit_entry >= data->syncnum) { 2370 nsp32_msg(KERN_ERR, "limit_entry exceeds syncnum!"); 2371 target->limit_entry = 0; 2372 } 2373 2374 for (i = target->limit_entry; i < data->syncnum; i++) { 2375 if (period >= data->synct[i].start_period && 2376 period <= data->synct[i].end_period) { 2377 break; 2378 } 2379 } 2380 2381 /* 2382 * Check given period value is over the sync_table value. 2383 * If so, return max value. 2384 */ 2385 if (i == data->syncnum) { 2386 i = -1; 2387 } 2388 2389 return i; 2390 } 2391 2392 2393 /* 2394 * target <-> initiator use ASYNC transfer 2395 */ 2396 static void nsp32_set_async(nsp32_hw_data *data, nsp32_target *target) 2397 { 2398 unsigned char period = data->synct[target->limit_entry].period_num; 2399 2400 target->offset = ASYNC_OFFSET; 2401 target->period = 0; 2402 target->syncreg = TO_SYNCREG(period, ASYNC_OFFSET); 2403 target->ackwidth = 0; 2404 target->sample_reg = 0; 2405 2406 nsp32_dbg(NSP32_DEBUG_SYNC, "set async"); 2407 } 2408 2409 2410 /* 2411 * target <-> initiator use maximum SYNC transfer 2412 */ 2413 static void nsp32_set_max_sync(nsp32_hw_data *data, 2414 nsp32_target *target, 2415 unsigned char *period, 2416 unsigned char *offset) 2417 { 2418 unsigned char period_num, ackwidth; 2419 2420 period_num = data->synct[target->limit_entry].period_num; 2421 *period = data->synct[target->limit_entry].start_period; 2422 ackwidth = data->synct[target->limit_entry].ackwidth; 2423 *offset = SYNC_OFFSET; 2424 2425 target->syncreg = TO_SYNCREG(period_num, *offset); 2426 target->ackwidth = ackwidth; 2427 target->offset = *offset; 2428 target->sample_reg = 0; /* disable SREQ sampling */ 2429 } 2430 2431 2432 /* 2433 * target <-> initiator use entry number speed 2434 */ 2435 static void nsp32_set_sync_entry(nsp32_hw_data *data, 2436 nsp32_target *target, 2437 int entry, 2438 unsigned char offset) 2439 { 2440 unsigned char period, ackwidth, sample_rate; 2441 2442 period = data->synct[entry].period_num; 2443 ackwidth = data->synct[entry].ackwidth; 2444 offset = offset; 2445 sample_rate = data->synct[entry].sample_rate; 2446 2447 target->syncreg = TO_SYNCREG(period, offset); 2448 target->ackwidth = ackwidth; 2449 target->offset = offset; 2450 target->sample_reg = sample_rate | SAMPLING_ENABLE; 2451 2452 nsp32_dbg(NSP32_DEBUG_SYNC, "set sync"); 2453 } 2454 2455 2456 /* 2457 * It waits until SCSI REQ becomes assertion or negation state. 2458 * 2459 * Note: If nsp32_msgin_occur is called, we asserts SCSI ACK. Then 2460 * connected target responds SCSI REQ negation. We have to wait 2461 * SCSI REQ becomes negation in order to negate SCSI ACK signal for 2462 * REQ-ACK handshake. 2463 */ 2464 static void nsp32_wait_req(nsp32_hw_data *data, int state) 2465 { 2466 unsigned int base = data->BaseAddress; 2467 int wait_time = 0; 2468 unsigned char bus, req_bit; 2469 2470 if (!((state == ASSERT) || (state == NEGATE))) { 2471 nsp32_msg(KERN_ERR, "unknown state designation"); 2472 } 2473 /* REQ is BIT(5) */ 2474 req_bit = (state == ASSERT ? BUSMON_REQ : 0); 2475 2476 do { 2477 bus = nsp32_read1(base, SCSI_BUS_MONITOR); 2478 if ((bus & BUSMON_REQ) == req_bit) { 2479 nsp32_dbg(NSP32_DEBUG_WAIT, 2480 "wait_time: %d", wait_time); 2481 return; 2482 } 2483 udelay(1); 2484 wait_time++; 2485 } while (wait_time < REQSACK_TIMEOUT_TIME); 2486 2487 nsp32_msg(KERN_WARNING, "wait REQ timeout, req_bit: 0x%x", req_bit); 2488 } 2489 2490 /* 2491 * It waits until SCSI SACK becomes assertion or negation state. 2492 */ 2493 static void nsp32_wait_sack(nsp32_hw_data *data, int state) 2494 { 2495 unsigned int base = data->BaseAddress; 2496 int wait_time = 0; 2497 unsigned char bus, ack_bit; 2498 2499 if (!((state == ASSERT) || (state == NEGATE))) { 2500 nsp32_msg(KERN_ERR, "unknown state designation"); 2501 } 2502 /* ACK is BIT(4) */ 2503 ack_bit = (state == ASSERT ? BUSMON_ACK : 0); 2504 2505 do { 2506 bus = nsp32_read1(base, SCSI_BUS_MONITOR); 2507 if ((bus & BUSMON_ACK) == ack_bit) { 2508 nsp32_dbg(NSP32_DEBUG_WAIT, 2509 "wait_time: %d", wait_time); 2510 return; 2511 } 2512 udelay(1); 2513 wait_time++; 2514 } while (wait_time < REQSACK_TIMEOUT_TIME); 2515 2516 nsp32_msg(KERN_WARNING, "wait SACK timeout, ack_bit: 0x%x", ack_bit); 2517 } 2518 2519 /* 2520 * assert SCSI ACK 2521 * 2522 * Note: SCSI ACK assertion needs with ACKENB=1, AUTODIRECTION=1. 2523 */ 2524 static void nsp32_sack_assert(nsp32_hw_data *data) 2525 { 2526 unsigned int base = data->BaseAddress; 2527 unsigned char busctrl; 2528 2529 busctrl = nsp32_read1(base, SCSI_BUS_CONTROL); 2530 busctrl |= (BUSCTL_ACK | AUTODIRECTION | ACKENB); 2531 nsp32_write1(base, SCSI_BUS_CONTROL, busctrl); 2532 } 2533 2534 /* 2535 * negate SCSI ACK 2536 */ 2537 static void nsp32_sack_negate(nsp32_hw_data *data) 2538 { 2539 unsigned int base = data->BaseAddress; 2540 unsigned char busctrl; 2541 2542 busctrl = nsp32_read1(base, SCSI_BUS_CONTROL); 2543 busctrl &= ~BUSCTL_ACK; 2544 nsp32_write1(base, SCSI_BUS_CONTROL, busctrl); 2545 } 2546 2547 2548 2549 /* 2550 * Note: n_io_port is defined as 0x7f because I/O register port is 2551 * assigned as: 2552 * 0x800-0x8ff: memory mapped I/O port 2553 * 0x900-0xbff: (map same 0x800-0x8ff I/O port image repeatedly) 2554 * 0xc00-0xfff: CardBus status registers 2555 */ 2556 static int nsp32_detect(struct pci_dev *pdev) 2557 { 2558 struct Scsi_Host *host; /* registered host structure */ 2559 struct resource *res; 2560 nsp32_hw_data *data; 2561 int ret; 2562 int i, j; 2563 2564 nsp32_dbg(NSP32_DEBUG_REGISTER, "enter"); 2565 2566 /* 2567 * register this HBA as SCSI device 2568 */ 2569 host = scsi_host_alloc(&nsp32_template, sizeof(nsp32_hw_data)); 2570 if (host == NULL) { 2571 nsp32_msg (KERN_ERR, "failed to scsi register"); 2572 goto err; 2573 } 2574 2575 /* 2576 * set nsp32_hw_data 2577 */ 2578 data = (nsp32_hw_data *)host->hostdata; 2579 2580 memcpy(data, &nsp32_data_base, sizeof(nsp32_hw_data)); 2581 2582 host->irq = data->IrqNumber; 2583 host->io_port = data->BaseAddress; 2584 host->unique_id = data->BaseAddress; 2585 host->n_io_port = data->NumAddress; 2586 host->base = (unsigned long)data->MmioAddress; 2587 2588 data->Host = host; 2589 spin_lock_init(&(data->Lock)); 2590 2591 data->cur_lunt = NULL; 2592 data->cur_target = NULL; 2593 2594 /* 2595 * Bus master transfer mode is supported currently. 2596 */ 2597 data->trans_method = NSP32_TRANSFER_BUSMASTER; 2598 2599 /* 2600 * Set clock div, CLOCK_4 (HBA has own external clock, and 2601 * dividing * 100ns/4). 2602 * Currently CLOCK_4 has only tested, not for CLOCK_2/PCICLK yet. 2603 */ 2604 data->clock = CLOCK_4; 2605 2606 /* 2607 * Select appropriate nsp32_sync_table and set I_CLOCKDIV. 2608 */ 2609 switch (data->clock) { 2610 case CLOCK_4: 2611 /* If data->clock is CLOCK_4, then select 40M sync table. */ 2612 data->synct = nsp32_sync_table_40M; 2613 data->syncnum = ARRAY_SIZE(nsp32_sync_table_40M); 2614 break; 2615 case CLOCK_2: 2616 /* If data->clock is CLOCK_2, then select 20M sync table. */ 2617 data->synct = nsp32_sync_table_20M; 2618 data->syncnum = ARRAY_SIZE(nsp32_sync_table_20M); 2619 break; 2620 case PCICLK: 2621 /* If data->clock is PCICLK, then select pci sync table. */ 2622 data->synct = nsp32_sync_table_pci; 2623 data->syncnum = ARRAY_SIZE(nsp32_sync_table_pci); 2624 break; 2625 default: 2626 nsp32_msg(KERN_WARNING, 2627 "Invalid clock div is selected, set CLOCK_4."); 2628 /* Use default value CLOCK_4 */ 2629 data->clock = CLOCK_4; 2630 data->synct = nsp32_sync_table_40M; 2631 data->syncnum = ARRAY_SIZE(nsp32_sync_table_40M); 2632 } 2633 2634 /* 2635 * setup nsp32_lunt 2636 */ 2637 2638 /* 2639 * setup DMA 2640 */ 2641 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)) != 0) { 2642 nsp32_msg (KERN_ERR, "failed to set PCI DMA mask"); 2643 goto scsi_unregister; 2644 } 2645 2646 /* 2647 * allocate autoparam DMA resource. 2648 */ 2649 data->autoparam = dma_alloc_coherent(&pdev->dev, 2650 sizeof(nsp32_autoparam), &(data->auto_paddr), 2651 GFP_KERNEL); 2652 if (data->autoparam == NULL) { 2653 nsp32_msg(KERN_ERR, "failed to allocate DMA memory"); 2654 goto scsi_unregister; 2655 } 2656 2657 /* 2658 * allocate scatter-gather DMA resource. 2659 */ 2660 data->sg_list = dma_alloc_coherent(&pdev->dev, NSP32_SG_TABLE_SIZE, 2661 &data->sg_paddr, GFP_KERNEL); 2662 if (data->sg_list == NULL) { 2663 nsp32_msg(KERN_ERR, "failed to allocate DMA memory"); 2664 goto free_autoparam; 2665 } 2666 2667 for (i = 0; i < ARRAY_SIZE(data->lunt); i++) { 2668 for (j = 0; j < ARRAY_SIZE(data->lunt[0]); j++) { 2669 int offset = i * ARRAY_SIZE(data->lunt[0]) + j; 2670 nsp32_lunt tmp = { 2671 .SCpnt = NULL, 2672 .save_datp = 0, 2673 .msgin03 = FALSE, 2674 .sg_num = 0, 2675 .cur_entry = 0, 2676 .sglun = &(data->sg_list[offset]), 2677 .sglun_paddr = data->sg_paddr + (offset * sizeof(nsp32_sglun)), 2678 }; 2679 2680 data->lunt[i][j] = tmp; 2681 } 2682 } 2683 2684 /* 2685 * setup target 2686 */ 2687 for (i = 0; i < ARRAY_SIZE(data->target); i++) { 2688 nsp32_target *target = &(data->target[i]); 2689 2690 target->limit_entry = 0; 2691 target->sync_flag = 0; 2692 nsp32_set_async(data, target); 2693 } 2694 2695 /* 2696 * EEPROM check 2697 */ 2698 ret = nsp32_getprom_param(data); 2699 if (ret == FALSE) { 2700 data->resettime = 3; /* default 3 */ 2701 } 2702 2703 /* 2704 * setup HBA 2705 */ 2706 nsp32hw_init(data); 2707 2708 snprintf(data->info_str, sizeof(data->info_str), 2709 "NinjaSCSI-32Bi/UDE: irq %d, io 0x%lx+0x%x", 2710 host->irq, host->io_port, host->n_io_port); 2711 2712 /* 2713 * SCSI bus reset 2714 * 2715 * Note: It's important to reset SCSI bus in initialization phase. 2716 * NinjaSCSI-32Bi/UDE HBA EEPROM seems to exchange SDTR when 2717 * system is coming up, so SCSI devices connected to HBA is set as 2718 * un-asynchronous mode. It brings the merit that this HBA is 2719 * ready to start synchronous transfer without any preparation, 2720 * but we are difficult to control transfer speed. In addition, 2721 * it prevents device transfer speed from effecting EEPROM start-up 2722 * SDTR. NinjaSCSI-32Bi/UDE has the feature if EEPROM is set as 2723 * Auto Mode, then FAST-10M is selected when SCSI devices are 2724 * connected same or more than 4 devices. It should be avoided 2725 * depending on this specification. Thus, resetting the SCSI bus 2726 * restores all connected SCSI devices to asynchronous mode, then 2727 * this driver set SDTR safely later, and we can control all SCSI 2728 * device transfer mode. 2729 */ 2730 nsp32_do_bus_reset(data); 2731 2732 ret = request_irq(host->irq, do_nsp32_isr, IRQF_SHARED, "nsp32", data); 2733 if (ret < 0) { 2734 nsp32_msg(KERN_ERR, "Unable to allocate IRQ for NinjaSCSI32 " 2735 "SCSI PCI controller. Interrupt: %d", host->irq); 2736 goto free_sg_list; 2737 } 2738 2739 /* 2740 * PCI IO register 2741 */ 2742 res = request_region(host->io_port, host->n_io_port, "nsp32"); 2743 if (res == NULL) { 2744 nsp32_msg(KERN_ERR, 2745 "I/O region 0x%lx+0x%lx is already used", 2746 data->BaseAddress, data->NumAddress); 2747 goto free_irq; 2748 } 2749 2750 ret = scsi_add_host(host, &pdev->dev); 2751 if (ret) { 2752 nsp32_msg(KERN_ERR, "failed to add scsi host"); 2753 goto free_region; 2754 } 2755 scsi_scan_host(host); 2756 pci_set_drvdata(pdev, host); 2757 return 0; 2758 2759 free_region: 2760 release_region(host->io_port, host->n_io_port); 2761 2762 free_irq: 2763 free_irq(host->irq, data); 2764 2765 free_sg_list: 2766 dma_free_coherent(&pdev->dev, NSP32_SG_TABLE_SIZE, 2767 data->sg_list, data->sg_paddr); 2768 2769 free_autoparam: 2770 dma_free_coherent(&pdev->dev, sizeof(nsp32_autoparam), 2771 data->autoparam, data->auto_paddr); 2772 2773 scsi_unregister: 2774 scsi_host_put(host); 2775 2776 err: 2777 return 1; 2778 } 2779 2780 static int nsp32_release(struct Scsi_Host *host) 2781 { 2782 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata; 2783 2784 if (data->autoparam) { 2785 dma_free_coherent(&data->Pci->dev, sizeof(nsp32_autoparam), 2786 data->autoparam, data->auto_paddr); 2787 } 2788 2789 if (data->sg_list) { 2790 dma_free_coherent(&data->Pci->dev, NSP32_SG_TABLE_SIZE, 2791 data->sg_list, data->sg_paddr); 2792 } 2793 2794 if (host->irq) { 2795 free_irq(host->irq, data); 2796 } 2797 2798 if (host->io_port && host->n_io_port) { 2799 release_region(host->io_port, host->n_io_port); 2800 } 2801 2802 if (data->MmioAddress) { 2803 iounmap(data->MmioAddress); 2804 } 2805 2806 return 0; 2807 } 2808 2809 static const char *nsp32_info(struct Scsi_Host *shpnt) 2810 { 2811 nsp32_hw_data *data = (nsp32_hw_data *)shpnt->hostdata; 2812 2813 return data->info_str; 2814 } 2815 2816 2817 /**************************************************************************** 2818 * error handler 2819 */ 2820 static int nsp32_eh_abort(struct scsi_cmnd *SCpnt) 2821 { 2822 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata; 2823 unsigned int base = SCpnt->device->host->io_port; 2824 2825 nsp32_msg(KERN_WARNING, "abort"); 2826 2827 if (data->cur_lunt->SCpnt == NULL) { 2828 nsp32_dbg(NSP32_DEBUG_BUSRESET, "abort failed"); 2829 return FAILED; 2830 } 2831 2832 if (data->cur_target->sync_flag & (SDTR_INITIATOR | SDTR_TARGET)) { 2833 /* reset SDTR negotiation */ 2834 data->cur_target->sync_flag = 0; 2835 nsp32_set_async(data, data->cur_target); 2836 } 2837 2838 nsp32_write2(base, TRANSFER_CONTROL, 0); 2839 nsp32_write2(base, BM_CNT, 0); 2840 2841 SCpnt->result = DID_ABORT << 16; 2842 nsp32_scsi_done(SCpnt); 2843 2844 nsp32_dbg(NSP32_DEBUG_BUSRESET, "abort success"); 2845 return SUCCESS; 2846 } 2847 2848 static void nsp32_do_bus_reset(nsp32_hw_data *data) 2849 { 2850 unsigned int base = data->BaseAddress; 2851 unsigned short intrdat; 2852 int i; 2853 2854 nsp32_dbg(NSP32_DEBUG_BUSRESET, "in"); 2855 2856 /* 2857 * stop all transfer 2858 * clear TRANSFERCONTROL_BM_START 2859 * clear counter 2860 */ 2861 nsp32_write2(base, TRANSFER_CONTROL, 0); 2862 nsp32_write4(base, BM_CNT, 0); 2863 nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK); 2864 2865 /* 2866 * fall back to asynchronous transfer mode 2867 * initialize SDTR negotiation flag 2868 */ 2869 for (i = 0; i < ARRAY_SIZE(data->target); i++) { 2870 nsp32_target *target = &data->target[i]; 2871 2872 target->sync_flag = 0; 2873 nsp32_set_async(data, target); 2874 } 2875 2876 /* 2877 * reset SCSI bus 2878 */ 2879 nsp32_write1(base, SCSI_BUS_CONTROL, BUSCTL_RST); 2880 mdelay(RESET_HOLD_TIME / 1000); 2881 nsp32_write1(base, SCSI_BUS_CONTROL, 0); 2882 for(i = 0; i < 5; i++) { 2883 intrdat = nsp32_read2(base, IRQ_STATUS); /* dummy read */ 2884 nsp32_dbg(NSP32_DEBUG_BUSRESET, "irq:1: 0x%x", intrdat); 2885 } 2886 2887 data->CurrentSC = NULL; 2888 } 2889 2890 static int nsp32_eh_host_reset(struct scsi_cmnd *SCpnt) 2891 { 2892 struct Scsi_Host *host = SCpnt->device->host; 2893 unsigned int base = SCpnt->device->host->io_port; 2894 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata; 2895 2896 nsp32_msg(KERN_INFO, "Host Reset"); 2897 nsp32_dbg(NSP32_DEBUG_BUSRESET, "SCpnt=0x%x", SCpnt); 2898 2899 spin_lock_irq(SCpnt->device->host->host_lock); 2900 2901 nsp32hw_init(data); 2902 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK); 2903 nsp32_do_bus_reset(data); 2904 nsp32_write2(base, IRQ_CONTROL, 0); 2905 2906 spin_unlock_irq(SCpnt->device->host->host_lock); 2907 return SUCCESS; /* Host reset is succeeded at any time. */ 2908 } 2909 2910 2911 /************************************************************************** 2912 * EEPROM handler 2913 */ 2914 2915 /* 2916 * getting EEPROM parameter 2917 */ 2918 static int nsp32_getprom_param(nsp32_hw_data *data) 2919 { 2920 int vendor = data->pci_devid->vendor; 2921 int device = data->pci_devid->device; 2922 int ret, val, i; 2923 2924 /* 2925 * EEPROM checking. 2926 */ 2927 ret = nsp32_prom_read(data, 0x7e); 2928 if (ret != 0x55) { 2929 nsp32_msg(KERN_INFO, "No EEPROM detected: 0x%x", ret); 2930 return FALSE; 2931 } 2932 ret = nsp32_prom_read(data, 0x7f); 2933 if (ret != 0xaa) { 2934 nsp32_msg(KERN_INFO, "Invalid number: 0x%x", ret); 2935 return FALSE; 2936 } 2937 2938 /* 2939 * check EEPROM type 2940 */ 2941 if (vendor == PCI_VENDOR_ID_WORKBIT && 2942 device == PCI_DEVICE_ID_WORKBIT_STANDARD) { 2943 ret = nsp32_getprom_c16(data); 2944 } else if (vendor == PCI_VENDOR_ID_WORKBIT && 2945 device == PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC) { 2946 ret = nsp32_getprom_at24(data); 2947 } else if (vendor == PCI_VENDOR_ID_WORKBIT && 2948 device == PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO ) { 2949 ret = nsp32_getprom_at24(data); 2950 } else { 2951 nsp32_msg(KERN_WARNING, "Unknown EEPROM"); 2952 ret = FALSE; 2953 } 2954 2955 /* for debug : SPROM data full checking */ 2956 for (i = 0; i <= 0x1f; i++) { 2957 val = nsp32_prom_read(data, i); 2958 nsp32_dbg(NSP32_DEBUG_EEPROM, 2959 "rom address 0x%x : 0x%x", i, val); 2960 } 2961 2962 return ret; 2963 } 2964 2965 2966 /* 2967 * AT24C01A (Logitec: LHA-600S), AT24C02 (Melco Buffalo: IFC-USLP) data map: 2968 * 2969 * ROMADDR 2970 * 0x00 - 0x06 : Device Synchronous Transfer Period (SCSI ID 0 - 6) 2971 * Value 0x0: ASYNC, 0x0c: Ultra-20M, 0x19: Fast-10M 2972 * 0x07 : HBA Synchronous Transfer Period 2973 * Value 0: AutoSync, 1: Manual Setting 2974 * 0x08 - 0x0f : Not Used? (0x0) 2975 * 0x10 : Bus Termination 2976 * Value 0: Auto[ON], 1: ON, 2: OFF 2977 * 0x11 : Not Used? (0) 2978 * 0x12 : Bus Reset Delay Time (0x03) 2979 * 0x13 : Bootable CD Support 2980 * Value 0: Disable, 1: Enable 2981 * 0x14 : Device Scan 2982 * Bit 7 6 5 4 3 2 1 0 2983 * | <-----------------> 2984 * | SCSI ID: Value 0: Skip, 1: YES 2985 * |-> Value 0: ALL scan, Value 1: Manual 2986 * 0x15 - 0x1b : Not Used? (0) 2987 * 0x1c : Constant? (0x01) (clock div?) 2988 * 0x1d - 0x7c : Not Used (0xff) 2989 * 0x7d : Not Used? (0xff) 2990 * 0x7e : Constant (0x55), Validity signature 2991 * 0x7f : Constant (0xaa), Validity signature 2992 */ 2993 static int nsp32_getprom_at24(nsp32_hw_data *data) 2994 { 2995 int ret, i; 2996 int auto_sync; 2997 nsp32_target *target; 2998 int entry; 2999 3000 /* 3001 * Reset time which is designated by EEPROM. 3002 * 3003 * TODO: Not used yet. 3004 */ 3005 data->resettime = nsp32_prom_read(data, 0x12); 3006 3007 /* 3008 * HBA Synchronous Transfer Period 3009 * 3010 * Note: auto_sync = 0: auto, 1: manual. Ninja SCSI HBA spec says 3011 * that if auto_sync is 0 (auto), and connected SCSI devices are 3012 * same or lower than 3, then transfer speed is set as ULTRA-20M. 3013 * On the contrary if connected SCSI devices are same or higher 3014 * than 4, then transfer speed is set as FAST-10M. 3015 * 3016 * I break this rule. The number of connected SCSI devices are 3017 * only ignored. If auto_sync is 0 (auto), then transfer speed is 3018 * forced as ULTRA-20M. 3019 */ 3020 ret = nsp32_prom_read(data, 0x07); 3021 switch (ret) { 3022 case 0: 3023 auto_sync = TRUE; 3024 break; 3025 case 1: 3026 auto_sync = FALSE; 3027 break; 3028 default: 3029 nsp32_msg(KERN_WARNING, 3030 "Unsupported Auto Sync mode. Fall back to manual mode."); 3031 auto_sync = TRUE; 3032 } 3033 3034 if (trans_mode == ULTRA20M_MODE) { 3035 auto_sync = TRUE; 3036 } 3037 3038 /* 3039 * each device Synchronous Transfer Period 3040 */ 3041 for (i = 0; i < NSP32_HOST_SCSIID; i++) { 3042 target = &data->target[i]; 3043 if (auto_sync == TRUE) { 3044 target->limit_entry = 0; /* set as ULTRA20M */ 3045 } else { 3046 ret = nsp32_prom_read(data, i); 3047 entry = nsp32_search_period_entry(data, target, ret); 3048 if (entry < 0) { 3049 /* search failed... set maximum speed */ 3050 entry = 0; 3051 } 3052 target->limit_entry = entry; 3053 } 3054 } 3055 3056 return TRUE; 3057 } 3058 3059 3060 /* 3061 * C16 110 (I-O Data: SC-NBD) data map: 3062 * 3063 * ROMADDR 3064 * 0x00 - 0x06 : Device Synchronous Transfer Period (SCSI ID 0 - 6) 3065 * Value 0x0: 20MB/S, 0x1: 10MB/S, 0x2: 5MB/S, 0x3: ASYNC 3066 * 0x07 : 0 (HBA Synchronous Transfer Period: Auto Sync) 3067 * 0x08 - 0x0f : Not Used? (0x0) 3068 * 0x10 : Transfer Mode 3069 * Value 0: PIO, 1: Busmater 3070 * 0x11 : Bus Reset Delay Time (0x00-0x20) 3071 * 0x12 : Bus Termination 3072 * Value 0: Disable, 1: Enable 3073 * 0x13 - 0x19 : Disconnection 3074 * Value 0: Disable, 1: Enable 3075 * 0x1a - 0x7c : Not Used? (0) 3076 * 0x7d : Not Used? (0xf8) 3077 * 0x7e : Constant (0x55), Validity signature 3078 * 0x7f : Constant (0xaa), Validity signature 3079 */ 3080 static int nsp32_getprom_c16(nsp32_hw_data *data) 3081 { 3082 int ret, i; 3083 nsp32_target *target; 3084 int entry, val; 3085 3086 /* 3087 * Reset time which is designated by EEPROM. 3088 * 3089 * TODO: Not used yet. 3090 */ 3091 data->resettime = nsp32_prom_read(data, 0x11); 3092 3093 /* 3094 * each device Synchronous Transfer Period 3095 */ 3096 for (i = 0; i < NSP32_HOST_SCSIID; i++) { 3097 target = &data->target[i]; 3098 ret = nsp32_prom_read(data, i); 3099 switch (ret) { 3100 case 0: /* 20MB/s */ 3101 val = 0x0c; 3102 break; 3103 case 1: /* 10MB/s */ 3104 val = 0x19; 3105 break; 3106 case 2: /* 5MB/s */ 3107 val = 0x32; 3108 break; 3109 case 3: /* ASYNC */ 3110 val = 0x00; 3111 break; 3112 default: /* default 20MB/s */ 3113 val = 0x0c; 3114 break; 3115 } 3116 entry = nsp32_search_period_entry(data, target, val); 3117 if (entry < 0 || trans_mode == ULTRA20M_MODE) { 3118 /* search failed... set maximum speed */ 3119 entry = 0; 3120 } 3121 target->limit_entry = entry; 3122 } 3123 3124 return TRUE; 3125 } 3126 3127 3128 /* 3129 * Atmel AT24C01A (drived in 5V) serial EEPROM routines 3130 */ 3131 static int nsp32_prom_read(nsp32_hw_data *data, int romaddr) 3132 { 3133 int i, val; 3134 3135 /* start condition */ 3136 nsp32_prom_start(data); 3137 3138 /* device address */ 3139 nsp32_prom_write_bit(data, 1); /* 1 */ 3140 nsp32_prom_write_bit(data, 0); /* 0 */ 3141 nsp32_prom_write_bit(data, 1); /* 1 */ 3142 nsp32_prom_write_bit(data, 0); /* 0 */ 3143 nsp32_prom_write_bit(data, 0); /* A2: 0 (GND) */ 3144 nsp32_prom_write_bit(data, 0); /* A1: 0 (GND) */ 3145 nsp32_prom_write_bit(data, 0); /* A0: 0 (GND) */ 3146 3147 /* R/W: W for dummy write */ 3148 nsp32_prom_write_bit(data, 0); 3149 3150 /* ack */ 3151 nsp32_prom_write_bit(data, 0); 3152 3153 /* word address */ 3154 for (i = 7; i >= 0; i--) { 3155 nsp32_prom_write_bit(data, ((romaddr >> i) & 1)); 3156 } 3157 3158 /* ack */ 3159 nsp32_prom_write_bit(data, 0); 3160 3161 /* start condition */ 3162 nsp32_prom_start(data); 3163 3164 /* device address */ 3165 nsp32_prom_write_bit(data, 1); /* 1 */ 3166 nsp32_prom_write_bit(data, 0); /* 0 */ 3167 nsp32_prom_write_bit(data, 1); /* 1 */ 3168 nsp32_prom_write_bit(data, 0); /* 0 */ 3169 nsp32_prom_write_bit(data, 0); /* A2: 0 (GND) */ 3170 nsp32_prom_write_bit(data, 0); /* A1: 0 (GND) */ 3171 nsp32_prom_write_bit(data, 0); /* A0: 0 (GND) */ 3172 3173 /* R/W: R */ 3174 nsp32_prom_write_bit(data, 1); 3175 3176 /* ack */ 3177 nsp32_prom_write_bit(data, 0); 3178 3179 /* data... */ 3180 val = 0; 3181 for (i = 7; i >= 0; i--) { 3182 val += (nsp32_prom_read_bit(data) << i); 3183 } 3184 3185 /* no ack */ 3186 nsp32_prom_write_bit(data, 1); 3187 3188 /* stop condition */ 3189 nsp32_prom_stop(data); 3190 3191 return val; 3192 } 3193 3194 static void nsp32_prom_set(nsp32_hw_data *data, int bit, int val) 3195 { 3196 int base = data->BaseAddress; 3197 int tmp; 3198 3199 tmp = nsp32_index_read1(base, SERIAL_ROM_CTL); 3200 3201 if (val == 0) { 3202 tmp &= ~bit; 3203 } else { 3204 tmp |= bit; 3205 } 3206 3207 nsp32_index_write1(base, SERIAL_ROM_CTL, tmp); 3208 3209 udelay(10); 3210 } 3211 3212 static int nsp32_prom_get(nsp32_hw_data *data, int bit) 3213 { 3214 int base = data->BaseAddress; 3215 int tmp, ret; 3216 3217 if (bit != SDA) { 3218 nsp32_msg(KERN_ERR, "return value is not appropriate"); 3219 return 0; 3220 } 3221 3222 3223 tmp = nsp32_index_read1(base, SERIAL_ROM_CTL) & bit; 3224 3225 if (tmp == 0) { 3226 ret = 0; 3227 } else { 3228 ret = 1; 3229 } 3230 3231 udelay(10); 3232 3233 return ret; 3234 } 3235 3236 static void nsp32_prom_start (nsp32_hw_data *data) 3237 { 3238 /* start condition */ 3239 nsp32_prom_set(data, SCL, 1); 3240 nsp32_prom_set(data, SDA, 1); 3241 nsp32_prom_set(data, ENA, 1); /* output mode */ 3242 nsp32_prom_set(data, SDA, 0); /* keeping SCL=1 and transiting 3243 * SDA 1->0 is start condition */ 3244 nsp32_prom_set(data, SCL, 0); 3245 } 3246 3247 static void nsp32_prom_stop (nsp32_hw_data *data) 3248 { 3249 /* stop condition */ 3250 nsp32_prom_set(data, SCL, 1); 3251 nsp32_prom_set(data, SDA, 0); 3252 nsp32_prom_set(data, ENA, 1); /* output mode */ 3253 nsp32_prom_set(data, SDA, 1); 3254 nsp32_prom_set(data, SCL, 0); 3255 } 3256 3257 static void nsp32_prom_write_bit(nsp32_hw_data *data, int val) 3258 { 3259 /* write */ 3260 nsp32_prom_set(data, SDA, val); 3261 nsp32_prom_set(data, SCL, 1 ); 3262 nsp32_prom_set(data, SCL, 0 ); 3263 } 3264 3265 static int nsp32_prom_read_bit(nsp32_hw_data *data) 3266 { 3267 int val; 3268 3269 /* read */ 3270 nsp32_prom_set(data, ENA, 0); /* input mode */ 3271 nsp32_prom_set(data, SCL, 1); 3272 3273 val = nsp32_prom_get(data, SDA); 3274 3275 nsp32_prom_set(data, SCL, 0); 3276 nsp32_prom_set(data, ENA, 1); /* output mode */ 3277 3278 return val; 3279 } 3280 3281 3282 /************************************************************************** 3283 * Power Management 3284 */ 3285 #ifdef CONFIG_PM 3286 3287 /* Device suspended */ 3288 static int nsp32_suspend(struct pci_dev *pdev, pm_message_t state) 3289 { 3290 struct Scsi_Host *host = pci_get_drvdata(pdev); 3291 3292 nsp32_msg(KERN_INFO, "pci-suspend: pdev=0x%p, state=%ld, slot=%s, host=0x%p", pdev, state, pci_name(pdev), host); 3293 3294 pci_save_state (pdev); 3295 pci_disable_device (pdev); 3296 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 3297 3298 return 0; 3299 } 3300 3301 /* Device woken up */ 3302 static int nsp32_resume(struct pci_dev *pdev) 3303 { 3304 struct Scsi_Host *host = pci_get_drvdata(pdev); 3305 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata; 3306 unsigned short reg; 3307 3308 nsp32_msg(KERN_INFO, "pci-resume: pdev=0x%p, slot=%s, host=0x%p", pdev, pci_name(pdev), host); 3309 3310 pci_set_power_state(pdev, PCI_D0); 3311 pci_enable_wake (pdev, PCI_D0, 0); 3312 pci_restore_state (pdev); 3313 3314 reg = nsp32_read2(data->BaseAddress, INDEX_REG); 3315 3316 nsp32_msg(KERN_INFO, "io=0x%x reg=0x%x", data->BaseAddress, reg); 3317 3318 if (reg == 0xffff) { 3319 nsp32_msg(KERN_INFO, "missing device. abort resume."); 3320 return 0; 3321 } 3322 3323 nsp32hw_init (data); 3324 nsp32_do_bus_reset(data); 3325 3326 nsp32_msg(KERN_INFO, "resume success"); 3327 3328 return 0; 3329 } 3330 3331 #endif 3332 3333 /************************************************************************ 3334 * PCI/Cardbus probe/remove routine 3335 */ 3336 static int nsp32_probe(struct pci_dev *pdev, const struct pci_device_id *id) 3337 { 3338 int ret; 3339 nsp32_hw_data *data = &nsp32_data_base; 3340 3341 nsp32_dbg(NSP32_DEBUG_REGISTER, "enter"); 3342 3343 ret = pci_enable_device(pdev); 3344 if (ret) { 3345 nsp32_msg(KERN_ERR, "failed to enable pci device"); 3346 return ret; 3347 } 3348 3349 data->Pci = pdev; 3350 data->pci_devid = id; 3351 data->IrqNumber = pdev->irq; 3352 data->BaseAddress = pci_resource_start(pdev, 0); 3353 data->NumAddress = pci_resource_len (pdev, 0); 3354 data->MmioAddress = pci_ioremap_bar(pdev, 1); 3355 data->MmioLength = pci_resource_len (pdev, 1); 3356 3357 pci_set_master(pdev); 3358 3359 ret = nsp32_detect(pdev); 3360 3361 nsp32_msg(KERN_INFO, "irq: %i mmio: %p+0x%lx slot: %s model: %s", 3362 pdev->irq, 3363 data->MmioAddress, data->MmioLength, 3364 pci_name(pdev), 3365 nsp32_model[id->driver_data]); 3366 3367 nsp32_dbg(NSP32_DEBUG_REGISTER, "exit %d", ret); 3368 3369 return ret; 3370 } 3371 3372 static void nsp32_remove(struct pci_dev *pdev) 3373 { 3374 struct Scsi_Host *host = pci_get_drvdata(pdev); 3375 3376 nsp32_dbg(NSP32_DEBUG_REGISTER, "enter"); 3377 3378 scsi_remove_host(host); 3379 3380 nsp32_release(host); 3381 3382 scsi_host_put(host); 3383 } 3384 3385 static struct pci_driver nsp32_driver = { 3386 .name = "nsp32", 3387 .id_table = nsp32_pci_table, 3388 .probe = nsp32_probe, 3389 .remove = nsp32_remove, 3390 #ifdef CONFIG_PM 3391 .suspend = nsp32_suspend, 3392 .resume = nsp32_resume, 3393 #endif 3394 }; 3395 3396 /********************************************************************* 3397 * Moule entry point 3398 */ 3399 static int __init init_nsp32(void) { 3400 nsp32_msg(KERN_INFO, "loading..."); 3401 return pci_register_driver(&nsp32_driver); 3402 } 3403 3404 static void __exit exit_nsp32(void) { 3405 nsp32_msg(KERN_INFO, "unloading..."); 3406 pci_unregister_driver(&nsp32_driver); 3407 } 3408 3409 module_init(init_nsp32); 3410 module_exit(exit_nsp32); 3411 3412 /* end */ 3413