1 /* 2 * Marvell 88SE64xx/88SE94xx main function head file 3 * 4 * Copyright 2007 Red Hat, Inc. 5 * Copyright 2008 Marvell. <kewei@marvell.com> 6 * 7 * This file is licensed under GPLv2. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; version 2 of the 12 * License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 22 * USA 23 */ 24 25 #ifndef _MV_SAS_H_ 26 #define _MV_SAS_H_ 27 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/spinlock.h> 31 #include <linux/delay.h> 32 #include <linux/types.h> 33 #include <linux/ctype.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/pci.h> 36 #include <linux/platform_device.h> 37 #include <linux/interrupt.h> 38 #include <linux/irq.h> 39 #include <linux/vmalloc.h> 40 #include <scsi/libsas.h> 41 #include <scsi/scsi_tcq.h> 42 #include <scsi/sas_ata.h> 43 #include <linux/version.h> 44 #include "mv_defs.h" 45 46 #define DRV_NAME "mvsas" 47 #define DRV_VERSION "0.8.2" 48 #define _MV_DUMP 0 49 #define MVS_ID_NOT_MAPPED 0x7f 50 /* #define DISABLE_HOTPLUG_DMA_FIX */ 51 #define MAX_EXP_RUNNING_REQ 2 52 #define WIDE_PORT_MAX_PHY 4 53 #define MV_DISABLE_NCQ 0 54 #define mv_printk(fmt, arg ...) \ 55 printk(KERN_DEBUG"%s %d:" fmt, __FILE__, __LINE__, ## arg) 56 #ifdef MV_DEBUG 57 #define mv_dprintk(format, arg...) \ 58 printk(KERN_DEBUG"%s %d:" format, __FILE__, __LINE__, ## arg) 59 #else 60 #define mv_dprintk(format, arg...) 61 #endif 62 #define MV_MAX_U32 0xffffffff 63 64 extern struct mvs_tgt_initiator mvs_tgt; 65 extern struct mvs_info *tgt_mvi; 66 extern const struct mvs_dispatch mvs_64xx_dispatch; 67 extern const struct mvs_dispatch mvs_94xx_dispatch; 68 69 #define DEV_IS_EXPANDER(type) \ 70 ((type == EDGE_DEV) || (type == FANOUT_DEV)) 71 72 #define bit(n) ((u32)1 << n) 73 74 #define for_each_phy(__lseq_mask, __mc, __lseq) \ 75 for ((__mc) = (__lseq_mask), (__lseq) = 0; \ 76 (__mc) != 0 ; \ 77 (++__lseq), (__mc) >>= 1) 78 79 #define MV_INIT_DELAYED_WORK(w, f, d) INIT_DELAYED_WORK(w, f) 80 #define UNASSOC_D2H_FIS(id) \ 81 ((void *) mvi->rx_fis + 0x100 * id) 82 #define SATA_RECEIVED_FIS_LIST(reg_set) \ 83 ((void *) mvi->rx_fis + mvi->chip->fis_offs + 0x100 * reg_set) 84 #define SATA_RECEIVED_SDB_FIS(reg_set) \ 85 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x58) 86 #define SATA_RECEIVED_D2H_FIS(reg_set) \ 87 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x40) 88 #define SATA_RECEIVED_PIO_FIS(reg_set) \ 89 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x20) 90 #define SATA_RECEIVED_DMA_FIS(reg_set) \ 91 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x00) 92 93 enum dev_status { 94 MVS_DEV_NORMAL = 0x0, 95 MVS_DEV_EH = 0x1, 96 }; 97 98 99 struct mvs_info; 100 101 struct mvs_dispatch { 102 char *name; 103 int (*chip_init)(struct mvs_info *mvi); 104 int (*spi_init)(struct mvs_info *mvi); 105 int (*chip_ioremap)(struct mvs_info *mvi); 106 void (*chip_iounmap)(struct mvs_info *mvi); 107 irqreturn_t (*isr)(struct mvs_info *mvi, int irq, u32 stat); 108 u32 (*isr_status)(struct mvs_info *mvi, int irq); 109 void (*interrupt_enable)(struct mvs_info *mvi); 110 void (*interrupt_disable)(struct mvs_info *mvi); 111 112 u32 (*read_phy_ctl)(struct mvs_info *mvi, u32 port); 113 void (*write_phy_ctl)(struct mvs_info *mvi, u32 port, u32 val); 114 115 u32 (*read_port_cfg_data)(struct mvs_info *mvi, u32 port); 116 void (*write_port_cfg_data)(struct mvs_info *mvi, u32 port, u32 val); 117 void (*write_port_cfg_addr)(struct mvs_info *mvi, u32 port, u32 addr); 118 119 u32 (*read_port_vsr_data)(struct mvs_info *mvi, u32 port); 120 void (*write_port_vsr_data)(struct mvs_info *mvi, u32 port, u32 val); 121 void (*write_port_vsr_addr)(struct mvs_info *mvi, u32 port, u32 addr); 122 123 u32 (*read_port_irq_stat)(struct mvs_info *mvi, u32 port); 124 void (*write_port_irq_stat)(struct mvs_info *mvi, u32 port, u32 val); 125 126 u32 (*read_port_irq_mask)(struct mvs_info *mvi, u32 port); 127 void (*write_port_irq_mask)(struct mvs_info *mvi, u32 port, u32 val); 128 129 void (*get_sas_addr)(void *buf, u32 buflen); 130 void (*command_active)(struct mvs_info *mvi, u32 slot_idx); 131 void (*issue_stop)(struct mvs_info *mvi, enum mvs_port_type type, 132 u32 tfs); 133 void (*start_delivery)(struct mvs_info *mvi, u32 tx); 134 u32 (*rx_update)(struct mvs_info *mvi); 135 void (*int_full)(struct mvs_info *mvi); 136 u8 (*assign_reg_set)(struct mvs_info *mvi, u8 *tfs); 137 void (*free_reg_set)(struct mvs_info *mvi, u8 *tfs); 138 u32 (*prd_size)(void); 139 u32 (*prd_count)(void); 140 void (*make_prd)(struct scatterlist *scatter, int nr, void *prd); 141 void (*detect_porttype)(struct mvs_info *mvi, int i); 142 int (*oob_done)(struct mvs_info *mvi, int i); 143 void (*fix_phy_info)(struct mvs_info *mvi, int i, 144 struct sas_identify_frame *id); 145 void (*phy_work_around)(struct mvs_info *mvi, int i); 146 void (*phy_set_link_rate)(struct mvs_info *mvi, u32 phy_id, 147 struct sas_phy_linkrates *rates); 148 u32 (*phy_max_link_rate)(void); 149 void (*phy_disable)(struct mvs_info *mvi, u32 phy_id); 150 void (*phy_enable)(struct mvs_info *mvi, u32 phy_id); 151 void (*phy_reset)(struct mvs_info *mvi, u32 phy_id, int hard); 152 void (*stp_reset)(struct mvs_info *mvi, u32 phy_id); 153 void (*clear_active_cmds)(struct mvs_info *mvi); 154 u32 (*spi_read_data)(struct mvs_info *mvi); 155 void (*spi_write_data)(struct mvs_info *mvi, u32 data); 156 int (*spi_buildcmd)(struct mvs_info *mvi, 157 u32 *dwCmd, 158 u8 cmd, 159 u8 read, 160 u8 length, 161 u32 addr 162 ); 163 int (*spi_issuecmd)(struct mvs_info *mvi, u32 cmd); 164 int (*spi_waitdataready)(struct mvs_info *mvi, u32 timeout); 165 #ifndef DISABLE_HOTPLUG_DMA_FIX 166 void (*dma_fix)(dma_addr_t buf_dma, int buf_len, int from, void *prd); 167 #endif 168 169 }; 170 171 struct mvs_chip_info { 172 u32 n_host; 173 u32 n_phy; 174 u32 fis_offs; 175 u32 fis_count; 176 u32 srs_sz; 177 u32 slot_width; 178 const struct mvs_dispatch *dispatch; 179 }; 180 #define MVS_CHIP_SLOT_SZ (1U << mvi->chip->slot_width) 181 #define MVS_RX_FISL_SZ \ 182 (mvi->chip->fis_offs + (mvi->chip->fis_count * 0x100)) 183 #define MVS_CHIP_DISP (mvi->chip->dispatch) 184 185 struct mvs_err_info { 186 __le32 flags; 187 __le32 flags2; 188 }; 189 190 struct mvs_cmd_hdr { 191 __le32 flags; /* PRD tbl len; SAS, SATA ctl */ 192 __le32 lens; /* cmd, max resp frame len */ 193 __le32 tags; /* targ port xfer tag; tag */ 194 __le32 data_len; /* data xfer len */ 195 __le64 cmd_tbl; /* command table address */ 196 __le64 open_frame; /* open addr frame address */ 197 __le64 status_buf; /* status buffer address */ 198 __le64 prd_tbl; /* PRD tbl address */ 199 __le32 reserved[4]; 200 }; 201 202 struct mvs_port { 203 struct asd_sas_port sas_port; 204 u8 port_attached; 205 u8 wide_port_phymap; 206 struct list_head list; 207 }; 208 209 struct mvs_phy { 210 struct mvs_info *mvi; 211 struct mvs_port *port; 212 struct asd_sas_phy sas_phy; 213 struct sas_identify identify; 214 struct scsi_device *sdev; 215 struct timer_list timer; 216 u64 dev_sas_addr; 217 u64 att_dev_sas_addr; 218 u32 att_dev_info; 219 u32 dev_info; 220 u32 phy_type; 221 u32 phy_status; 222 u32 irq_status; 223 u32 frame_rcvd_size; 224 u8 frame_rcvd[32]; 225 u8 phy_attached; 226 u8 phy_mode; 227 u8 reserved[2]; 228 u32 phy_event; 229 enum sas_linkrate minimum_linkrate; 230 enum sas_linkrate maximum_linkrate; 231 }; 232 233 struct mvs_device { 234 struct list_head dev_entry; 235 enum sas_dev_type dev_type; 236 struct mvs_info *mvi_info; 237 struct domain_device *sas_device; 238 u32 attached_phy; 239 u32 device_id; 240 u32 runing_req; 241 u8 taskfileset; 242 u8 dev_status; 243 u16 reserved; 244 }; 245 246 struct mvs_slot_info { 247 struct list_head entry; 248 union { 249 struct sas_task *task; 250 void *tdata; 251 }; 252 u32 n_elem; 253 u32 tx; 254 u32 slot_tag; 255 256 /* DMA buffer for storing cmd tbl, open addr frame, status buffer, 257 * and PRD table 258 */ 259 void *buf; 260 dma_addr_t buf_dma; 261 #if _MV_DUMP 262 u32 cmd_size; 263 #endif 264 void *response; 265 struct mvs_port *port; 266 struct mvs_device *device; 267 void *open_frame; 268 }; 269 270 struct mvs_info { 271 unsigned long flags; 272 273 /* host-wide lock */ 274 spinlock_t lock; 275 276 /* our device */ 277 struct pci_dev *pdev; 278 struct device *dev; 279 280 /* enhanced mode registers */ 281 void __iomem *regs; 282 283 /* peripheral or soc registers */ 284 void __iomem *regs_ex; 285 u8 sas_addr[SAS_ADDR_SIZE]; 286 287 /* SCSI/SAS glue */ 288 struct sas_ha_struct *sas; 289 struct Scsi_Host *shost; 290 291 /* TX (delivery) DMA ring */ 292 __le32 *tx; 293 dma_addr_t tx_dma; 294 295 /* cached next-producer idx */ 296 u32 tx_prod; 297 298 /* RX (completion) DMA ring */ 299 __le32 *rx; 300 dma_addr_t rx_dma; 301 302 /* RX consumer idx */ 303 u32 rx_cons; 304 305 /* RX'd FIS area */ 306 __le32 *rx_fis; 307 dma_addr_t rx_fis_dma; 308 309 /* DMA command header slots */ 310 struct mvs_cmd_hdr *slot; 311 dma_addr_t slot_dma; 312 313 u32 chip_id; 314 const struct mvs_chip_info *chip; 315 316 int tags_num; 317 DECLARE_BITMAP(tags, MVS_SLOTS); 318 /* further per-slot information */ 319 struct mvs_phy phy[MVS_MAX_PHYS]; 320 struct mvs_port port[MVS_MAX_PHYS]; 321 u32 irq; 322 u32 exp_req; 323 u32 id; 324 u64 sata_reg_set; 325 struct list_head *hba_list; 326 struct list_head soc_entry; 327 struct list_head wq_list; 328 unsigned long instance; 329 u16 flashid; 330 u32 flashsize; 331 u32 flashsectSize; 332 333 void *addon; 334 struct mvs_device devices[MVS_MAX_DEVICES]; 335 #ifndef DISABLE_HOTPLUG_DMA_FIX 336 void *bulk_buffer; 337 dma_addr_t bulk_buffer_dma; 338 #define TRASH_BUCKET_SIZE 0x20000 339 #endif 340 struct mvs_slot_info slot_info[0]; 341 }; 342 343 struct mvs_prv_info{ 344 u8 n_host; 345 u8 n_phy; 346 u16 reserve; 347 struct mvs_info *mvi[2]; 348 }; 349 350 struct mvs_wq { 351 struct delayed_work work_q; 352 struct mvs_info *mvi; 353 void *data; 354 int handler; 355 struct list_head entry; 356 }; 357 358 struct mvs_task_exec_info { 359 struct sas_task *task; 360 struct mvs_cmd_hdr *hdr; 361 struct mvs_port *port; 362 u32 tag; 363 int n_elem; 364 }; 365 366 367 /******************** function prototype *********************/ 368 void mvs_get_sas_addr(void *buf, u32 buflen); 369 void mvs_tag_clear(struct mvs_info *mvi, u32 tag); 370 void mvs_tag_free(struct mvs_info *mvi, u32 tag); 371 void mvs_tag_set(struct mvs_info *mvi, unsigned int tag); 372 int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out); 373 void mvs_tag_init(struct mvs_info *mvi); 374 void mvs_iounmap(void __iomem *regs); 375 int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex); 376 void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard); 377 int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func, 378 void *funcdata); 379 void __devinit mvs_set_sas_addr(struct mvs_info *mvi, int port_id, 380 u32 off_lo, u32 off_hi, u64 sas_addr); 381 int mvs_slave_alloc(struct scsi_device *scsi_dev); 382 int mvs_slave_configure(struct scsi_device *sdev); 383 void mvs_scan_start(struct Scsi_Host *shost); 384 int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time); 385 int mvs_queue_command(struct sas_task *task, const int num, 386 gfp_t gfp_flags); 387 int mvs_abort_task(struct sas_task *task); 388 int mvs_abort_task_set(struct domain_device *dev, u8 *lun); 389 int mvs_clear_aca(struct domain_device *dev, u8 *lun); 390 int mvs_clear_task_set(struct domain_device *dev, u8 * lun); 391 void mvs_port_formed(struct asd_sas_phy *sas_phy); 392 void mvs_port_deformed(struct asd_sas_phy *sas_phy); 393 int mvs_dev_found(struct domain_device *dev); 394 void mvs_dev_gone(struct domain_device *dev); 395 int mvs_lu_reset(struct domain_device *dev, u8 *lun); 396 int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags); 397 int mvs_I_T_nexus_reset(struct domain_device *dev); 398 int mvs_query_task(struct sas_task *task); 399 void mvs_release_task(struct mvs_info *mvi, int phy_no, 400 struct domain_device *dev); 401 void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events); 402 void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st); 403 int mvs_int_rx(struct mvs_info *mvi, bool self_clear); 404 void mvs_hexdump(u32 size, u8 *data, u32 baseaddr); 405 #endif 406 407