1 /* 2 * Marvell 88SE64xx/88SE94xx main function head file 3 * 4 * Copyright 2007 Red Hat, Inc. 5 * Copyright 2008 Marvell. <kewei@marvell.com> 6 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com> 7 * 8 * This file is licensed under GPLv2. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; version 2 of the 13 * License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 23 * USA 24 */ 25 26 #ifndef _MV_SAS_H_ 27 #define _MV_SAS_H_ 28 29 #include <linux/kernel.h> 30 #include <linux/module.h> 31 #include <linux/spinlock.h> 32 #include <linux/delay.h> 33 #include <linux/types.h> 34 #include <linux/ctype.h> 35 #include <linux/dma-mapping.h> 36 #include <linux/pci.h> 37 #include <linux/platform_device.h> 38 #include <linux/interrupt.h> 39 #include <linux/irq.h> 40 #include <linux/slab.h> 41 #include <linux/vmalloc.h> 42 #include <scsi/libsas.h> 43 #include <scsi/scsi.h> 44 #include <scsi/scsi_tcq.h> 45 #include <scsi/sas_ata.h> 46 #include "mv_defs.h" 47 48 #define DRV_NAME "mvsas" 49 #define DRV_VERSION "0.8.16" 50 #define MVS_ID_NOT_MAPPED 0x7f 51 #define WIDE_PORT_MAX_PHY 4 52 #define mv_printk(fmt, arg ...) \ 53 printk(KERN_DEBUG"%s %d:" fmt, __FILE__, __LINE__, ## arg) 54 #ifdef MV_DEBUG 55 #define mv_dprintk(format, arg...) \ 56 printk(KERN_DEBUG"%s %d:" format, __FILE__, __LINE__, ## arg) 57 #else 58 #define mv_dprintk(format, arg...) 59 #endif 60 #define MV_MAX_U32 0xffffffff 61 62 extern int interrupt_coalescing; 63 extern struct mvs_tgt_initiator mvs_tgt; 64 extern struct mvs_info *tgt_mvi; 65 extern const struct mvs_dispatch mvs_64xx_dispatch; 66 extern const struct mvs_dispatch mvs_94xx_dispatch; 67 extern struct kmem_cache *mvs_task_list_cache; 68 69 #define DEV_IS_EXPANDER(type) \ 70 ((type == EDGE_DEV) || (type == FANOUT_DEV)) 71 72 #define bit(n) ((u64)1 << n) 73 74 #define for_each_phy(__lseq_mask, __mc, __lseq) \ 75 for ((__mc) = (__lseq_mask), (__lseq) = 0; \ 76 (__mc) != 0 ; \ 77 (++__lseq), (__mc) >>= 1) 78 79 #define MV_INIT_DELAYED_WORK(w, f, d) INIT_DELAYED_WORK(w, f) 80 #define UNASSOC_D2H_FIS(id) \ 81 ((void *) mvi->rx_fis + 0x100 * id) 82 #define SATA_RECEIVED_FIS_LIST(reg_set) \ 83 ((void *) mvi->rx_fis + mvi->chip->fis_offs + 0x100 * reg_set) 84 #define SATA_RECEIVED_SDB_FIS(reg_set) \ 85 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x58) 86 #define SATA_RECEIVED_D2H_FIS(reg_set) \ 87 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x40) 88 #define SATA_RECEIVED_PIO_FIS(reg_set) \ 89 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x20) 90 #define SATA_RECEIVED_DMA_FIS(reg_set) \ 91 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x00) 92 93 enum dev_status { 94 MVS_DEV_NORMAL = 0x0, 95 MVS_DEV_EH = 0x1, 96 }; 97 98 enum dev_reset { 99 MVS_SOFT_RESET = 0, 100 MVS_HARD_RESET = 1, 101 MVS_PHY_TUNE = 2, 102 }; 103 104 struct mvs_info; 105 106 struct mvs_dispatch { 107 char *name; 108 int (*chip_init)(struct mvs_info *mvi); 109 int (*spi_init)(struct mvs_info *mvi); 110 int (*chip_ioremap)(struct mvs_info *mvi); 111 void (*chip_iounmap)(struct mvs_info *mvi); 112 irqreturn_t (*isr)(struct mvs_info *mvi, int irq, u32 stat); 113 u32 (*isr_status)(struct mvs_info *mvi, int irq); 114 void (*interrupt_enable)(struct mvs_info *mvi); 115 void (*interrupt_disable)(struct mvs_info *mvi); 116 117 u32 (*read_phy_ctl)(struct mvs_info *mvi, u32 port); 118 void (*write_phy_ctl)(struct mvs_info *mvi, u32 port, u32 val); 119 120 u32 (*read_port_cfg_data)(struct mvs_info *mvi, u32 port); 121 void (*write_port_cfg_data)(struct mvs_info *mvi, u32 port, u32 val); 122 void (*write_port_cfg_addr)(struct mvs_info *mvi, u32 port, u32 addr); 123 124 u32 (*read_port_vsr_data)(struct mvs_info *mvi, u32 port); 125 void (*write_port_vsr_data)(struct mvs_info *mvi, u32 port, u32 val); 126 void (*write_port_vsr_addr)(struct mvs_info *mvi, u32 port, u32 addr); 127 128 u32 (*read_port_irq_stat)(struct mvs_info *mvi, u32 port); 129 void (*write_port_irq_stat)(struct mvs_info *mvi, u32 port, u32 val); 130 131 u32 (*read_port_irq_mask)(struct mvs_info *mvi, u32 port); 132 void (*write_port_irq_mask)(struct mvs_info *mvi, u32 port, u32 val); 133 134 void (*command_active)(struct mvs_info *mvi, u32 slot_idx); 135 void (*clear_srs_irq)(struct mvs_info *mvi, u8 reg_set, u8 clear_all); 136 void (*issue_stop)(struct mvs_info *mvi, enum mvs_port_type type, 137 u32 tfs); 138 void (*start_delivery)(struct mvs_info *mvi, u32 tx); 139 u32 (*rx_update)(struct mvs_info *mvi); 140 void (*int_full)(struct mvs_info *mvi); 141 u8 (*assign_reg_set)(struct mvs_info *mvi, u8 *tfs); 142 void (*free_reg_set)(struct mvs_info *mvi, u8 *tfs); 143 u32 (*prd_size)(void); 144 u32 (*prd_count)(void); 145 void (*make_prd)(struct scatterlist *scatter, int nr, void *prd); 146 void (*detect_porttype)(struct mvs_info *mvi, int i); 147 int (*oob_done)(struct mvs_info *mvi, int i); 148 void (*fix_phy_info)(struct mvs_info *mvi, int i, 149 struct sas_identify_frame *id); 150 void (*phy_work_around)(struct mvs_info *mvi, int i); 151 void (*phy_set_link_rate)(struct mvs_info *mvi, u32 phy_id, 152 struct sas_phy_linkrates *rates); 153 u32 (*phy_max_link_rate)(void); 154 void (*phy_disable)(struct mvs_info *mvi, u32 phy_id); 155 void (*phy_enable)(struct mvs_info *mvi, u32 phy_id); 156 void (*phy_reset)(struct mvs_info *mvi, u32 phy_id, int hard); 157 void (*stp_reset)(struct mvs_info *mvi, u32 phy_id); 158 void (*clear_active_cmds)(struct mvs_info *mvi); 159 u32 (*spi_read_data)(struct mvs_info *mvi); 160 void (*spi_write_data)(struct mvs_info *mvi, u32 data); 161 int (*spi_buildcmd)(struct mvs_info *mvi, 162 u32 *dwCmd, 163 u8 cmd, 164 u8 read, 165 u8 length, 166 u32 addr 167 ); 168 int (*spi_issuecmd)(struct mvs_info *mvi, u32 cmd); 169 int (*spi_waitdataready)(struct mvs_info *mvi, u32 timeout); 170 void (*dma_fix)(struct mvs_info *mvi, u32 phy_mask, 171 int buf_len, int from, void *prd); 172 void (*tune_interrupt)(struct mvs_info *mvi, u32 time); 173 void (*non_spec_ncq_error)(struct mvs_info *mvi); 174 175 }; 176 177 struct mvs_chip_info { 178 u32 n_host; 179 u32 n_phy; 180 u32 fis_offs; 181 u32 fis_count; 182 u32 srs_sz; 183 u32 sg_width; 184 u32 slot_width; 185 const struct mvs_dispatch *dispatch; 186 }; 187 #define MVS_MAX_SG (1U << mvi->chip->sg_width) 188 #define MVS_CHIP_SLOT_SZ (1U << mvi->chip->slot_width) 189 #define MVS_RX_FISL_SZ \ 190 (mvi->chip->fis_offs + (mvi->chip->fis_count * 0x100)) 191 #define MVS_CHIP_DISP (mvi->chip->dispatch) 192 193 struct mvs_err_info { 194 __le32 flags; 195 __le32 flags2; 196 }; 197 198 struct mvs_cmd_hdr { 199 __le32 flags; /* PRD tbl len; SAS, SATA ctl */ 200 __le32 lens; /* cmd, max resp frame len */ 201 __le32 tags; /* targ port xfer tag; tag */ 202 __le32 data_len; /* data xfer len */ 203 __le64 cmd_tbl; /* command table address */ 204 __le64 open_frame; /* open addr frame address */ 205 __le64 status_buf; /* status buffer address */ 206 __le64 prd_tbl; /* PRD tbl address */ 207 __le32 reserved[4]; 208 }; 209 210 struct mvs_port { 211 struct asd_sas_port sas_port; 212 u8 port_attached; 213 u8 wide_port_phymap; 214 struct list_head list; 215 }; 216 217 struct mvs_phy { 218 struct mvs_info *mvi; 219 struct mvs_port *port; 220 struct asd_sas_phy sas_phy; 221 struct sas_identify identify; 222 struct scsi_device *sdev; 223 struct timer_list timer; 224 u64 dev_sas_addr; 225 u64 att_dev_sas_addr; 226 u32 att_dev_info; 227 u32 dev_info; 228 u32 phy_type; 229 u32 phy_status; 230 u32 irq_status; 231 u32 frame_rcvd_size; 232 u8 frame_rcvd[32]; 233 u8 phy_attached; 234 u8 phy_mode; 235 u8 reserved[2]; 236 u32 phy_event; 237 enum sas_linkrate minimum_linkrate; 238 enum sas_linkrate maximum_linkrate; 239 }; 240 241 struct mvs_device { 242 struct list_head dev_entry; 243 enum sas_dev_type dev_type; 244 struct mvs_info *mvi_info; 245 struct domain_device *sas_device; 246 struct timer_list timer; 247 u32 attached_phy; 248 u32 device_id; 249 u32 running_req; 250 u8 taskfileset; 251 u8 dev_status; 252 u16 reserved; 253 }; 254 255 /* Generate PHY tunning parameters */ 256 struct phy_tuning { 257 /* 1 bit, transmitter emphasis enable */ 258 u8 trans_emp_en:1; 259 /* 4 bits, transmitter emphasis amplitude */ 260 u8 trans_emp_amp:4; 261 /* 3 bits, reserved space */ 262 u8 Reserved_2bit_1:3; 263 /* 5 bits, transmitter amplitude */ 264 u8 trans_amp:5; 265 /* 2 bits, transmitter amplitude adjust */ 266 u8 trans_amp_adj:2; 267 /* 1 bit, reserved space */ 268 u8 resv_2bit_2:1; 269 /* 2 bytes, reserved space */ 270 u8 reserved[2]; 271 }; 272 273 struct ffe_control { 274 /* 4 bits, FFE Capacitor Select (value range 0~F) */ 275 u8 ffe_cap_sel:4; 276 /* 3 bits, FFE Resistor Select (value range 0~7) */ 277 u8 ffe_rss_sel:3; 278 /* 1 bit reserve*/ 279 u8 reserved:1; 280 }; 281 282 /* 283 * HBA_Info_Page is saved in Flash/NVRAM, total 256 bytes. 284 * The data area is valid only Signature="MRVL". 285 * If any member fills with 0xFF, the member is invalid. 286 */ 287 struct hba_info_page { 288 /* Dword 0 */ 289 /* 4 bytes, structure signature,should be "MRVL" at first initial */ 290 u8 signature[4]; 291 292 /* Dword 1-13 */ 293 u32 reserved1[13]; 294 295 /* Dword 14-29 */ 296 /* 64 bytes, SAS address for each port */ 297 u64 sas_addr[8]; 298 299 /* Dword 30-31 */ 300 /* 8 bytes for vanir 8 port PHY FFE seeting 301 * BIT 0~3 : FFE Capacitor select(value range 0~F) 302 * BIT 4~6 : FFE Resistor select(value range 0~7) 303 * BIT 7: reserve. 304 */ 305 306 struct ffe_control ffe_ctl[8]; 307 /* Dword 32 -43 */ 308 u32 reserved2[12]; 309 310 /* Dword 44-45 */ 311 /* 8 bytes, 0: 1.5G, 1: 3.0G, should be 0x01 at first initial */ 312 u8 phy_rate[8]; 313 314 /* Dword 46-53 */ 315 /* 32 bytes, PHY tuning parameters for each PHY*/ 316 struct phy_tuning phy_tuning[8]; 317 318 /* Dword 54-63 */ 319 u32 reserved3[10]; 320 }; /* total 256 bytes */ 321 322 struct mvs_slot_info { 323 struct list_head entry; 324 union { 325 struct sas_task *task; 326 void *tdata; 327 }; 328 u32 n_elem; 329 u32 tx; 330 u32 slot_tag; 331 332 /* DMA buffer for storing cmd tbl, open addr frame, status buffer, 333 * and PRD table 334 */ 335 void *buf; 336 dma_addr_t buf_dma; 337 void *response; 338 struct mvs_port *port; 339 struct mvs_device *device; 340 void *open_frame; 341 }; 342 343 struct mvs_info { 344 unsigned long flags; 345 346 /* host-wide lock */ 347 spinlock_t lock; 348 349 /* our device */ 350 struct pci_dev *pdev; 351 struct device *dev; 352 353 /* enhanced mode registers */ 354 void __iomem *regs; 355 356 /* peripheral or soc registers */ 357 void __iomem *regs_ex; 358 u8 sas_addr[SAS_ADDR_SIZE]; 359 360 /* SCSI/SAS glue */ 361 struct sas_ha_struct *sas; 362 struct Scsi_Host *shost; 363 364 /* TX (delivery) DMA ring */ 365 __le32 *tx; 366 dma_addr_t tx_dma; 367 368 /* cached next-producer idx */ 369 u32 tx_prod; 370 371 /* RX (completion) DMA ring */ 372 __le32 *rx; 373 dma_addr_t rx_dma; 374 375 /* RX consumer idx */ 376 u32 rx_cons; 377 378 /* RX'd FIS area */ 379 __le32 *rx_fis; 380 dma_addr_t rx_fis_dma; 381 382 /* DMA command header slots */ 383 struct mvs_cmd_hdr *slot; 384 dma_addr_t slot_dma; 385 386 u32 chip_id; 387 const struct mvs_chip_info *chip; 388 389 int tags_num; 390 unsigned long *tags; 391 /* further per-slot information */ 392 struct mvs_phy phy[MVS_MAX_PHYS]; 393 struct mvs_port port[MVS_MAX_PHYS]; 394 u32 id; 395 u64 sata_reg_set; 396 struct list_head *hba_list; 397 struct list_head soc_entry; 398 struct list_head wq_list; 399 unsigned long instance; 400 u16 flashid; 401 u32 flashsize; 402 u32 flashsectSize; 403 404 void *addon; 405 struct hba_info_page hba_info_param; 406 struct mvs_device devices[MVS_MAX_DEVICES]; 407 void *bulk_buffer; 408 dma_addr_t bulk_buffer_dma; 409 void *bulk_buffer1; 410 dma_addr_t bulk_buffer_dma1; 411 #define TRASH_BUCKET_SIZE 0x20000 412 void *dma_pool; 413 struct mvs_slot_info slot_info[0]; 414 }; 415 416 struct mvs_prv_info{ 417 u8 n_host; 418 u8 n_phy; 419 u8 scan_finished; 420 u8 reserve; 421 struct mvs_info *mvi[2]; 422 struct tasklet_struct mv_tasklet; 423 }; 424 425 struct mvs_wq { 426 struct delayed_work work_q; 427 struct mvs_info *mvi; 428 void *data; 429 int handler; 430 struct list_head entry; 431 }; 432 433 struct mvs_task_exec_info { 434 struct sas_task *task; 435 struct mvs_cmd_hdr *hdr; 436 struct mvs_port *port; 437 u32 tag; 438 int n_elem; 439 }; 440 441 struct mvs_task_list { 442 struct sas_task *task; 443 struct list_head list; 444 }; 445 446 447 /******************** function prototype *********************/ 448 void mvs_get_sas_addr(void *buf, u32 buflen); 449 void mvs_tag_clear(struct mvs_info *mvi, u32 tag); 450 void mvs_tag_free(struct mvs_info *mvi, u32 tag); 451 void mvs_tag_set(struct mvs_info *mvi, unsigned int tag); 452 int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out); 453 void mvs_tag_init(struct mvs_info *mvi); 454 void mvs_iounmap(void __iomem *regs); 455 int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex); 456 void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard); 457 int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func, 458 void *funcdata); 459 void mvs_set_sas_addr(struct mvs_info *mvi, int port_id, u32 off_lo, 460 u32 off_hi, u64 sas_addr); 461 void mvs_scan_start(struct Scsi_Host *shost); 462 int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time); 463 int mvs_queue_command(struct sas_task *task, const int num, 464 gfp_t gfp_flags); 465 int mvs_abort_task(struct sas_task *task); 466 int mvs_abort_task_set(struct domain_device *dev, u8 *lun); 467 int mvs_clear_aca(struct domain_device *dev, u8 *lun); 468 int mvs_clear_task_set(struct domain_device *dev, u8 * lun); 469 void mvs_port_formed(struct asd_sas_phy *sas_phy); 470 void mvs_port_deformed(struct asd_sas_phy *sas_phy); 471 int mvs_dev_found(struct domain_device *dev); 472 void mvs_dev_gone(struct domain_device *dev); 473 int mvs_lu_reset(struct domain_device *dev, u8 *lun); 474 int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags); 475 int mvs_I_T_nexus_reset(struct domain_device *dev); 476 int mvs_query_task(struct sas_task *task); 477 void mvs_release_task(struct mvs_info *mvi, 478 struct domain_device *dev); 479 void mvs_do_release_task(struct mvs_info *mvi, int phy_no, 480 struct domain_device *dev); 481 void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events); 482 void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st); 483 int mvs_int_rx(struct mvs_info *mvi, bool self_clear); 484 struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi, u8 reg_set); 485 #endif 486 487