1 /* 2 * Marvell 88SE64xx/88SE94xx main function head file 3 * 4 * Copyright 2007 Red Hat, Inc. 5 * Copyright 2008 Marvell. <kewei@marvell.com> 6 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com> 7 * 8 * This file is licensed under GPLv2. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; version 2 of the 13 * License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 23 * USA 24 */ 25 26 #ifndef _MV_SAS_H_ 27 #define _MV_SAS_H_ 28 29 #include <linux/kernel.h> 30 #include <linux/module.h> 31 #include <linux/spinlock.h> 32 #include <linux/delay.h> 33 #include <linux/types.h> 34 #include <linux/ctype.h> 35 #include <linux/dma-mapping.h> 36 #include <linux/pci.h> 37 #include <linux/platform_device.h> 38 #include <linux/interrupt.h> 39 #include <linux/irq.h> 40 #include <linux/slab.h> 41 #include <linux/vmalloc.h> 42 #include <scsi/libsas.h> 43 #include <scsi/scsi.h> 44 #include <scsi/scsi_tcq.h> 45 #include <scsi/sas_ata.h> 46 #include <linux/version.h> 47 #include "mv_defs.h" 48 49 #define DRV_NAME "mvsas" 50 #define DRV_VERSION "0.8.2" 51 #define _MV_DUMP 0 52 #define MVS_ID_NOT_MAPPED 0x7f 53 /* #define DISABLE_HOTPLUG_DMA_FIX */ 54 // #define MAX_EXP_RUNNING_REQ 2 55 #define WIDE_PORT_MAX_PHY 4 56 #define MV_DISABLE_NCQ 0 57 #define mv_printk(fmt, arg ...) \ 58 printk(KERN_DEBUG"%s %d:" fmt, __FILE__, __LINE__, ## arg) 59 #ifdef MV_DEBUG 60 #define mv_dprintk(format, arg...) \ 61 printk(KERN_DEBUG"%s %d:" format, __FILE__, __LINE__, ## arg) 62 #else 63 #define mv_dprintk(format, arg...) 64 #endif 65 #define MV_MAX_U32 0xffffffff 66 67 extern struct mvs_tgt_initiator mvs_tgt; 68 extern struct mvs_info *tgt_mvi; 69 extern const struct mvs_dispatch mvs_64xx_dispatch; 70 extern const struct mvs_dispatch mvs_94xx_dispatch; 71 extern struct kmem_cache *mvs_task_list_cache; 72 73 #define DEV_IS_EXPANDER(type) \ 74 ((type == EDGE_DEV) || (type == FANOUT_DEV)) 75 76 #define bit(n) ((u32)1 << n) 77 78 #define for_each_phy(__lseq_mask, __mc, __lseq) \ 79 for ((__mc) = (__lseq_mask), (__lseq) = 0; \ 80 (__mc) != 0 ; \ 81 (++__lseq), (__mc) >>= 1) 82 83 #define MV_INIT_DELAYED_WORK(w, f, d) INIT_DELAYED_WORK(w, f) 84 #define UNASSOC_D2H_FIS(id) \ 85 ((void *) mvi->rx_fis + 0x100 * id) 86 #define SATA_RECEIVED_FIS_LIST(reg_set) \ 87 ((void *) mvi->rx_fis + mvi->chip->fis_offs + 0x100 * reg_set) 88 #define SATA_RECEIVED_SDB_FIS(reg_set) \ 89 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x58) 90 #define SATA_RECEIVED_D2H_FIS(reg_set) \ 91 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x40) 92 #define SATA_RECEIVED_PIO_FIS(reg_set) \ 93 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x20) 94 #define SATA_RECEIVED_DMA_FIS(reg_set) \ 95 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x00) 96 97 enum dev_status { 98 MVS_DEV_NORMAL = 0x0, 99 MVS_DEV_EH = 0x1, 100 }; 101 102 103 struct mvs_info; 104 105 struct mvs_dispatch { 106 char *name; 107 int (*chip_init)(struct mvs_info *mvi); 108 int (*spi_init)(struct mvs_info *mvi); 109 int (*chip_ioremap)(struct mvs_info *mvi); 110 void (*chip_iounmap)(struct mvs_info *mvi); 111 irqreturn_t (*isr)(struct mvs_info *mvi, int irq, u32 stat); 112 u32 (*isr_status)(struct mvs_info *mvi, int irq); 113 void (*interrupt_enable)(struct mvs_info *mvi); 114 void (*interrupt_disable)(struct mvs_info *mvi); 115 116 u32 (*read_phy_ctl)(struct mvs_info *mvi, u32 port); 117 void (*write_phy_ctl)(struct mvs_info *mvi, u32 port, u32 val); 118 119 u32 (*read_port_cfg_data)(struct mvs_info *mvi, u32 port); 120 void (*write_port_cfg_data)(struct mvs_info *mvi, u32 port, u32 val); 121 void (*write_port_cfg_addr)(struct mvs_info *mvi, u32 port, u32 addr); 122 123 u32 (*read_port_vsr_data)(struct mvs_info *mvi, u32 port); 124 void (*write_port_vsr_data)(struct mvs_info *mvi, u32 port, u32 val); 125 void (*write_port_vsr_addr)(struct mvs_info *mvi, u32 port, u32 addr); 126 127 u32 (*read_port_irq_stat)(struct mvs_info *mvi, u32 port); 128 void (*write_port_irq_stat)(struct mvs_info *mvi, u32 port, u32 val); 129 130 u32 (*read_port_irq_mask)(struct mvs_info *mvi, u32 port); 131 void (*write_port_irq_mask)(struct mvs_info *mvi, u32 port, u32 val); 132 133 void (*get_sas_addr)(void *buf, u32 buflen); 134 void (*command_active)(struct mvs_info *mvi, u32 slot_idx); 135 void (*clear_srs_irq)(struct mvs_info *mvi, u8 reg_set, u8 clear_all); 136 void (*issue_stop)(struct mvs_info *mvi, enum mvs_port_type type, 137 u32 tfs); 138 void (*start_delivery)(struct mvs_info *mvi, u32 tx); 139 u32 (*rx_update)(struct mvs_info *mvi); 140 void (*int_full)(struct mvs_info *mvi); 141 u8 (*assign_reg_set)(struct mvs_info *mvi, u8 *tfs); 142 void (*free_reg_set)(struct mvs_info *mvi, u8 *tfs); 143 u32 (*prd_size)(void); 144 u32 (*prd_count)(void); 145 void (*make_prd)(struct scatterlist *scatter, int nr, void *prd); 146 void (*detect_porttype)(struct mvs_info *mvi, int i); 147 int (*oob_done)(struct mvs_info *mvi, int i); 148 void (*fix_phy_info)(struct mvs_info *mvi, int i, 149 struct sas_identify_frame *id); 150 void (*phy_work_around)(struct mvs_info *mvi, int i); 151 void (*phy_set_link_rate)(struct mvs_info *mvi, u32 phy_id, 152 struct sas_phy_linkrates *rates); 153 u32 (*phy_max_link_rate)(void); 154 void (*phy_disable)(struct mvs_info *mvi, u32 phy_id); 155 void (*phy_enable)(struct mvs_info *mvi, u32 phy_id); 156 void (*phy_reset)(struct mvs_info *mvi, u32 phy_id, int hard); 157 void (*stp_reset)(struct mvs_info *mvi, u32 phy_id); 158 void (*clear_active_cmds)(struct mvs_info *mvi); 159 u32 (*spi_read_data)(struct mvs_info *mvi); 160 void (*spi_write_data)(struct mvs_info *mvi, u32 data); 161 int (*spi_buildcmd)(struct mvs_info *mvi, 162 u32 *dwCmd, 163 u8 cmd, 164 u8 read, 165 u8 length, 166 u32 addr 167 ); 168 int (*spi_issuecmd)(struct mvs_info *mvi, u32 cmd); 169 int (*spi_waitdataready)(struct mvs_info *mvi, u32 timeout); 170 #ifndef DISABLE_HOTPLUG_DMA_FIX 171 void (*dma_fix)(dma_addr_t buf_dma, int buf_len, int from, void *prd); 172 #endif 173 174 }; 175 176 struct mvs_chip_info { 177 u32 n_host; 178 u32 n_phy; 179 u32 fis_offs; 180 u32 fis_count; 181 u32 srs_sz; 182 u32 slot_width; 183 const struct mvs_dispatch *dispatch; 184 }; 185 #define MVS_CHIP_SLOT_SZ (1U << mvi->chip->slot_width) 186 #define MVS_RX_FISL_SZ \ 187 (mvi->chip->fis_offs + (mvi->chip->fis_count * 0x100)) 188 #define MVS_CHIP_DISP (mvi->chip->dispatch) 189 190 struct mvs_err_info { 191 __le32 flags; 192 __le32 flags2; 193 }; 194 195 struct mvs_cmd_hdr { 196 __le32 flags; /* PRD tbl len; SAS, SATA ctl */ 197 __le32 lens; /* cmd, max resp frame len */ 198 __le32 tags; /* targ port xfer tag; tag */ 199 __le32 data_len; /* data xfer len */ 200 __le64 cmd_tbl; /* command table address */ 201 __le64 open_frame; /* open addr frame address */ 202 __le64 status_buf; /* status buffer address */ 203 __le64 prd_tbl; /* PRD tbl address */ 204 __le32 reserved[4]; 205 }; 206 207 struct mvs_port { 208 struct asd_sas_port sas_port; 209 u8 port_attached; 210 u8 wide_port_phymap; 211 struct list_head list; 212 }; 213 214 struct mvs_phy { 215 struct mvs_info *mvi; 216 struct mvs_port *port; 217 struct asd_sas_phy sas_phy; 218 struct sas_identify identify; 219 struct scsi_device *sdev; 220 struct timer_list timer; 221 u64 dev_sas_addr; 222 u64 att_dev_sas_addr; 223 u32 att_dev_info; 224 u32 dev_info; 225 u32 phy_type; 226 u32 phy_status; 227 u32 irq_status; 228 u32 frame_rcvd_size; 229 u8 frame_rcvd[32]; 230 u8 phy_attached; 231 u8 phy_mode; 232 u8 reserved[2]; 233 u32 phy_event; 234 enum sas_linkrate minimum_linkrate; 235 enum sas_linkrate maximum_linkrate; 236 }; 237 238 struct mvs_device { 239 struct list_head dev_entry; 240 enum sas_dev_type dev_type; 241 struct mvs_info *mvi_info; 242 struct domain_device *sas_device; 243 struct timer_list timer; 244 u32 attached_phy; 245 u32 device_id; 246 u32 running_req; 247 u8 taskfileset; 248 u8 dev_status; 249 u16 reserved; 250 }; 251 252 struct mvs_slot_info { 253 struct list_head entry; 254 union { 255 struct sas_task *task; 256 void *tdata; 257 }; 258 u32 n_elem; 259 u32 tx; 260 u32 slot_tag; 261 262 /* DMA buffer for storing cmd tbl, open addr frame, status buffer, 263 * and PRD table 264 */ 265 void *buf; 266 dma_addr_t buf_dma; 267 #if _MV_DUMP 268 u32 cmd_size; 269 #endif 270 void *response; 271 struct mvs_port *port; 272 struct mvs_device *device; 273 void *open_frame; 274 }; 275 276 struct mvs_info { 277 unsigned long flags; 278 279 /* host-wide lock */ 280 spinlock_t lock; 281 282 /* our device */ 283 struct pci_dev *pdev; 284 struct device *dev; 285 286 /* enhanced mode registers */ 287 void __iomem *regs; 288 289 /* peripheral or soc registers */ 290 void __iomem *regs_ex; 291 u8 sas_addr[SAS_ADDR_SIZE]; 292 293 /* SCSI/SAS glue */ 294 struct sas_ha_struct *sas; 295 struct Scsi_Host *shost; 296 297 /* TX (delivery) DMA ring */ 298 __le32 *tx; 299 dma_addr_t tx_dma; 300 301 /* cached next-producer idx */ 302 u32 tx_prod; 303 304 /* RX (completion) DMA ring */ 305 __le32 *rx; 306 dma_addr_t rx_dma; 307 308 /* RX consumer idx */ 309 u32 rx_cons; 310 311 /* RX'd FIS area */ 312 __le32 *rx_fis; 313 dma_addr_t rx_fis_dma; 314 315 /* DMA command header slots */ 316 struct mvs_cmd_hdr *slot; 317 dma_addr_t slot_dma; 318 319 u32 chip_id; 320 const struct mvs_chip_info *chip; 321 322 int tags_num; 323 DECLARE_BITMAP(tags, MVS_SLOTS); 324 /* further per-slot information */ 325 struct mvs_phy phy[MVS_MAX_PHYS]; 326 struct mvs_port port[MVS_MAX_PHYS]; 327 u32 irq; 328 u32 exp_req; 329 u32 id; 330 u64 sata_reg_set; 331 struct list_head *hba_list; 332 struct list_head soc_entry; 333 struct list_head wq_list; 334 unsigned long instance; 335 u16 flashid; 336 u32 flashsize; 337 u32 flashsectSize; 338 339 void *addon; 340 struct mvs_device devices[MVS_MAX_DEVICES]; 341 #ifndef DISABLE_HOTPLUG_DMA_FIX 342 void *bulk_buffer; 343 dma_addr_t bulk_buffer_dma; 344 #define TRASH_BUCKET_SIZE 0x20000 345 #endif 346 void *dma_pool; 347 struct mvs_slot_info slot_info[0]; 348 }; 349 350 struct mvs_prv_info{ 351 u8 n_host; 352 u8 n_phy; 353 u16 reserve; 354 struct mvs_info *mvi[2]; 355 }; 356 357 struct mvs_wq { 358 struct delayed_work work_q; 359 struct mvs_info *mvi; 360 void *data; 361 int handler; 362 struct list_head entry; 363 }; 364 365 struct mvs_task_exec_info { 366 struct sas_task *task; 367 struct mvs_cmd_hdr *hdr; 368 struct mvs_port *port; 369 u32 tag; 370 int n_elem; 371 }; 372 373 struct mvs_task_list { 374 struct sas_task *task; 375 struct list_head list; 376 }; 377 378 379 /******************** function prototype *********************/ 380 void mvs_get_sas_addr(void *buf, u32 buflen); 381 void mvs_tag_clear(struct mvs_info *mvi, u32 tag); 382 void mvs_tag_free(struct mvs_info *mvi, u32 tag); 383 void mvs_tag_set(struct mvs_info *mvi, unsigned int tag); 384 int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out); 385 void mvs_tag_init(struct mvs_info *mvi); 386 void mvs_iounmap(void __iomem *regs); 387 int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex); 388 void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard); 389 int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func, 390 void *funcdata); 391 void __devinit mvs_set_sas_addr(struct mvs_info *mvi, int port_id, 392 u32 off_lo, u32 off_hi, u64 sas_addr); 393 int mvs_slave_alloc(struct scsi_device *scsi_dev); 394 int mvs_slave_configure(struct scsi_device *sdev); 395 void mvs_scan_start(struct Scsi_Host *shost); 396 int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time); 397 int mvs_queue_command(struct sas_task *task, const int num, 398 gfp_t gfp_flags); 399 int mvs_abort_task(struct sas_task *task); 400 int mvs_abort_task_set(struct domain_device *dev, u8 *lun); 401 int mvs_clear_aca(struct domain_device *dev, u8 *lun); 402 int mvs_clear_task_set(struct domain_device *dev, u8 * lun); 403 void mvs_port_formed(struct asd_sas_phy *sas_phy); 404 void mvs_port_deformed(struct asd_sas_phy *sas_phy); 405 int mvs_dev_found(struct domain_device *dev); 406 void mvs_dev_gone(struct domain_device *dev); 407 int mvs_lu_reset(struct domain_device *dev, u8 *lun); 408 int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags); 409 int mvs_I_T_nexus_reset(struct domain_device *dev); 410 int mvs_query_task(struct sas_task *task); 411 void mvs_release_task(struct mvs_info *mvi, 412 struct domain_device *dev); 413 void mvs_do_release_task(struct mvs_info *mvi, int phy_no, 414 struct domain_device *dev); 415 void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events); 416 void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st); 417 int mvs_int_rx(struct mvs_info *mvi, bool self_clear); 418 void mvs_hexdump(u32 size, u8 *data, u32 baseaddr); 419 #endif 420 421