1 /* 2 * Marvell 88SE64xx/88SE94xx pci init 3 * 4 * Copyright 2007 Red Hat, Inc. 5 * Copyright 2008 Marvell. <kewei@marvell.com> 6 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com> 7 * 8 * This file is licensed under GPLv2. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; version 2 of the 13 * License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 23 * USA 24 */ 25 26 27 #include "mv_sas.h" 28 29 int interrupt_coalescing = 0x80; 30 31 static struct scsi_transport_template *mvs_stt; 32 static const struct mvs_chip_info mvs_chips[] = { 33 [chip_6320] = { 1, 2, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, }, 34 [chip_6440] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, }, 35 [chip_6485] = { 1, 8, 0x800, 33, 32, 6, 10, &mvs_64xx_dispatch, }, 36 [chip_9180] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, }, 37 [chip_9480] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, }, 38 [chip_9445] = { 1, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, }, 39 [chip_9485] = { 2, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, }, 40 [chip_1300] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, }, 41 [chip_1320] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, }, 42 }; 43 44 struct device_attribute *mvst_host_attrs[]; 45 46 #define SOC_SAS_NUM 2 47 48 static struct scsi_host_template mvs_sht = { 49 .module = THIS_MODULE, 50 .name = DRV_NAME, 51 .queuecommand = sas_queuecommand, 52 .target_alloc = sas_target_alloc, 53 .slave_configure = sas_slave_configure, 54 .scan_finished = mvs_scan_finished, 55 .scan_start = mvs_scan_start, 56 .change_queue_depth = sas_change_queue_depth, 57 .bios_param = sas_bios_param, 58 .can_queue = 1, 59 .this_id = -1, 60 .sg_tablesize = SG_ALL, 61 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 62 .use_clustering = ENABLE_CLUSTERING, 63 .eh_device_reset_handler = sas_eh_device_reset_handler, 64 .eh_bus_reset_handler = sas_eh_bus_reset_handler, 65 .target_destroy = sas_target_destroy, 66 .ioctl = sas_ioctl, 67 .shost_attrs = mvst_host_attrs, 68 .track_queue_depth = 1, 69 }; 70 71 static struct sas_domain_function_template mvs_transport_ops = { 72 .lldd_dev_found = mvs_dev_found, 73 .lldd_dev_gone = mvs_dev_gone, 74 .lldd_execute_task = mvs_queue_command, 75 .lldd_control_phy = mvs_phy_control, 76 77 .lldd_abort_task = mvs_abort_task, 78 .lldd_abort_task_set = mvs_abort_task_set, 79 .lldd_clear_aca = mvs_clear_aca, 80 .lldd_clear_task_set = mvs_clear_task_set, 81 .lldd_I_T_nexus_reset = mvs_I_T_nexus_reset, 82 .lldd_lu_reset = mvs_lu_reset, 83 .lldd_query_task = mvs_query_task, 84 .lldd_port_formed = mvs_port_formed, 85 .lldd_port_deformed = mvs_port_deformed, 86 87 .lldd_write_gpio = mvs_gpio_write, 88 89 }; 90 91 static void mvs_phy_init(struct mvs_info *mvi, int phy_id) 92 { 93 struct mvs_phy *phy = &mvi->phy[phy_id]; 94 struct asd_sas_phy *sas_phy = &phy->sas_phy; 95 96 phy->mvi = mvi; 97 phy->port = NULL; 98 init_timer(&phy->timer); 99 sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0; 100 sas_phy->class = SAS; 101 sas_phy->iproto = SAS_PROTOCOL_ALL; 102 sas_phy->tproto = 0; 103 sas_phy->type = PHY_TYPE_PHYSICAL; 104 sas_phy->role = PHY_ROLE_INITIATOR; 105 sas_phy->oob_mode = OOB_NOT_CONNECTED; 106 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN; 107 108 sas_phy->id = phy_id; 109 sas_phy->sas_addr = &mvi->sas_addr[0]; 110 sas_phy->frame_rcvd = &phy->frame_rcvd[0]; 111 sas_phy->ha = (struct sas_ha_struct *)mvi->shost->hostdata; 112 sas_phy->lldd_phy = phy; 113 } 114 115 static void mvs_free(struct mvs_info *mvi) 116 { 117 struct mvs_wq *mwq; 118 int slot_nr; 119 120 if (!mvi) 121 return; 122 123 if (mvi->flags & MVF_FLAG_SOC) 124 slot_nr = MVS_SOC_SLOTS; 125 else 126 slot_nr = MVS_CHIP_SLOT_SZ; 127 128 if (mvi->dma_pool) 129 pci_pool_destroy(mvi->dma_pool); 130 131 if (mvi->tx) 132 dma_free_coherent(mvi->dev, 133 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ, 134 mvi->tx, mvi->tx_dma); 135 if (mvi->rx_fis) 136 dma_free_coherent(mvi->dev, MVS_RX_FISL_SZ, 137 mvi->rx_fis, mvi->rx_fis_dma); 138 if (mvi->rx) 139 dma_free_coherent(mvi->dev, 140 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1), 141 mvi->rx, mvi->rx_dma); 142 if (mvi->slot) 143 dma_free_coherent(mvi->dev, 144 sizeof(*mvi->slot) * slot_nr, 145 mvi->slot, mvi->slot_dma); 146 147 if (mvi->bulk_buffer) 148 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE, 149 mvi->bulk_buffer, mvi->bulk_buffer_dma); 150 if (mvi->bulk_buffer1) 151 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE, 152 mvi->bulk_buffer1, mvi->bulk_buffer_dma1); 153 154 MVS_CHIP_DISP->chip_iounmap(mvi); 155 if (mvi->shost) 156 scsi_host_put(mvi->shost); 157 list_for_each_entry(mwq, &mvi->wq_list, entry) 158 cancel_delayed_work(&mwq->work_q); 159 kfree(mvi->tags); 160 kfree(mvi); 161 } 162 163 #ifdef CONFIG_SCSI_MVSAS_TASKLET 164 static void mvs_tasklet(unsigned long opaque) 165 { 166 u32 stat; 167 u16 core_nr, i = 0; 168 169 struct mvs_info *mvi; 170 struct sas_ha_struct *sha = (struct sas_ha_struct *)opaque; 171 172 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 173 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; 174 175 if (unlikely(!mvi)) 176 BUG_ON(1); 177 178 stat = MVS_CHIP_DISP->isr_status(mvi, mvi->pdev->irq); 179 if (!stat) 180 goto out; 181 182 for (i = 0; i < core_nr; i++) { 183 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; 184 MVS_CHIP_DISP->isr(mvi, mvi->pdev->irq, stat); 185 } 186 out: 187 MVS_CHIP_DISP->interrupt_enable(mvi); 188 189 } 190 #endif 191 192 static irqreturn_t mvs_interrupt(int irq, void *opaque) 193 { 194 u32 core_nr; 195 u32 stat; 196 struct mvs_info *mvi; 197 struct sas_ha_struct *sha = opaque; 198 #ifndef CONFIG_SCSI_MVSAS_TASKLET 199 u32 i; 200 #endif 201 202 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 203 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; 204 205 if (unlikely(!mvi)) 206 return IRQ_NONE; 207 #ifdef CONFIG_SCSI_MVSAS_TASKLET 208 MVS_CHIP_DISP->interrupt_disable(mvi); 209 #endif 210 211 stat = MVS_CHIP_DISP->isr_status(mvi, irq); 212 if (!stat) { 213 #ifdef CONFIG_SCSI_MVSAS_TASKLET 214 MVS_CHIP_DISP->interrupt_enable(mvi); 215 #endif 216 return IRQ_NONE; 217 } 218 219 #ifdef CONFIG_SCSI_MVSAS_TASKLET 220 tasklet_schedule(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet); 221 #else 222 for (i = 0; i < core_nr; i++) { 223 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; 224 MVS_CHIP_DISP->isr(mvi, irq, stat); 225 } 226 #endif 227 return IRQ_HANDLED; 228 } 229 230 static int mvs_alloc(struct mvs_info *mvi, struct Scsi_Host *shost) 231 { 232 int i = 0, slot_nr; 233 char pool_name[32]; 234 235 if (mvi->flags & MVF_FLAG_SOC) 236 slot_nr = MVS_SOC_SLOTS; 237 else 238 slot_nr = MVS_CHIP_SLOT_SZ; 239 240 spin_lock_init(&mvi->lock); 241 for (i = 0; i < mvi->chip->n_phy; i++) { 242 mvs_phy_init(mvi, i); 243 mvi->port[i].wide_port_phymap = 0; 244 mvi->port[i].port_attached = 0; 245 INIT_LIST_HEAD(&mvi->port[i].list); 246 } 247 for (i = 0; i < MVS_MAX_DEVICES; i++) { 248 mvi->devices[i].taskfileset = MVS_ID_NOT_MAPPED; 249 mvi->devices[i].dev_type = SAS_PHY_UNUSED; 250 mvi->devices[i].device_id = i; 251 mvi->devices[i].dev_status = MVS_DEV_NORMAL; 252 init_timer(&mvi->devices[i].timer); 253 } 254 255 /* 256 * alloc and init our DMA areas 257 */ 258 mvi->tx = dma_alloc_coherent(mvi->dev, 259 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ, 260 &mvi->tx_dma, GFP_KERNEL); 261 if (!mvi->tx) 262 goto err_out; 263 memset(mvi->tx, 0, sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ); 264 mvi->rx_fis = dma_alloc_coherent(mvi->dev, MVS_RX_FISL_SZ, 265 &mvi->rx_fis_dma, GFP_KERNEL); 266 if (!mvi->rx_fis) 267 goto err_out; 268 memset(mvi->rx_fis, 0, MVS_RX_FISL_SZ); 269 270 mvi->rx = dma_alloc_coherent(mvi->dev, 271 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1), 272 &mvi->rx_dma, GFP_KERNEL); 273 if (!mvi->rx) 274 goto err_out; 275 memset(mvi->rx, 0, sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1)); 276 mvi->rx[0] = cpu_to_le32(0xfff); 277 mvi->rx_cons = 0xfff; 278 279 mvi->slot = dma_alloc_coherent(mvi->dev, 280 sizeof(*mvi->slot) * slot_nr, 281 &mvi->slot_dma, GFP_KERNEL); 282 if (!mvi->slot) 283 goto err_out; 284 memset(mvi->slot, 0, sizeof(*mvi->slot) * slot_nr); 285 286 mvi->bulk_buffer = dma_alloc_coherent(mvi->dev, 287 TRASH_BUCKET_SIZE, 288 &mvi->bulk_buffer_dma, GFP_KERNEL); 289 if (!mvi->bulk_buffer) 290 goto err_out; 291 292 mvi->bulk_buffer1 = dma_alloc_coherent(mvi->dev, 293 TRASH_BUCKET_SIZE, 294 &mvi->bulk_buffer_dma1, GFP_KERNEL); 295 if (!mvi->bulk_buffer1) 296 goto err_out; 297 298 sprintf(pool_name, "%s%d", "mvs_dma_pool", mvi->id); 299 mvi->dma_pool = pci_pool_create(pool_name, mvi->pdev, MVS_SLOT_BUF_SZ, 16, 0); 300 if (!mvi->dma_pool) { 301 printk(KERN_DEBUG "failed to create dma pool %s.\n", pool_name); 302 goto err_out; 303 } 304 mvi->tags_num = slot_nr; 305 306 /* Initialize tags */ 307 mvs_tag_init(mvi); 308 return 0; 309 err_out: 310 return 1; 311 } 312 313 314 int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex) 315 { 316 unsigned long res_start, res_len, res_flag, res_flag_ex = 0; 317 struct pci_dev *pdev = mvi->pdev; 318 if (bar_ex != -1) { 319 /* 320 * ioremap main and peripheral registers 321 */ 322 res_start = pci_resource_start(pdev, bar_ex); 323 res_len = pci_resource_len(pdev, bar_ex); 324 if (!res_start || !res_len) 325 goto err_out; 326 327 res_flag_ex = pci_resource_flags(pdev, bar_ex); 328 if (res_flag_ex & IORESOURCE_MEM) 329 mvi->regs_ex = ioremap(res_start, res_len); 330 else 331 mvi->regs_ex = (void *)res_start; 332 if (!mvi->regs_ex) 333 goto err_out; 334 } 335 336 res_start = pci_resource_start(pdev, bar); 337 res_len = pci_resource_len(pdev, bar); 338 if (!res_start || !res_len) { 339 iounmap(mvi->regs_ex); 340 mvi->regs_ex = NULL; 341 goto err_out; 342 } 343 344 res_flag = pci_resource_flags(pdev, bar); 345 mvi->regs = ioremap(res_start, res_len); 346 347 if (!mvi->regs) { 348 if (mvi->regs_ex && (res_flag_ex & IORESOURCE_MEM)) 349 iounmap(mvi->regs_ex); 350 mvi->regs_ex = NULL; 351 goto err_out; 352 } 353 354 return 0; 355 err_out: 356 return -1; 357 } 358 359 void mvs_iounmap(void __iomem *regs) 360 { 361 iounmap(regs); 362 } 363 364 static struct mvs_info *mvs_pci_alloc(struct pci_dev *pdev, 365 const struct pci_device_id *ent, 366 struct Scsi_Host *shost, unsigned int id) 367 { 368 struct mvs_info *mvi = NULL; 369 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 370 371 mvi = kzalloc(sizeof(*mvi) + 372 (1L << mvs_chips[ent->driver_data].slot_width) * 373 sizeof(struct mvs_slot_info), GFP_KERNEL); 374 if (!mvi) 375 return NULL; 376 377 mvi->pdev = pdev; 378 mvi->dev = &pdev->dev; 379 mvi->chip_id = ent->driver_data; 380 mvi->chip = &mvs_chips[mvi->chip_id]; 381 INIT_LIST_HEAD(&mvi->wq_list); 382 383 ((struct mvs_prv_info *)sha->lldd_ha)->mvi[id] = mvi; 384 ((struct mvs_prv_info *)sha->lldd_ha)->n_phy = mvi->chip->n_phy; 385 386 mvi->id = id; 387 mvi->sas = sha; 388 mvi->shost = shost; 389 390 mvi->tags = kzalloc(MVS_CHIP_SLOT_SZ>>3, GFP_KERNEL); 391 if (!mvi->tags) 392 goto err_out; 393 394 if (MVS_CHIP_DISP->chip_ioremap(mvi)) 395 goto err_out; 396 if (!mvs_alloc(mvi, shost)) 397 return mvi; 398 err_out: 399 mvs_free(mvi); 400 return NULL; 401 } 402 403 static int pci_go_64(struct pci_dev *pdev) 404 { 405 int rc; 406 407 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 408 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 409 if (rc) { 410 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 411 if (rc) { 412 dev_printk(KERN_ERR, &pdev->dev, 413 "64-bit DMA enable failed\n"); 414 return rc; 415 } 416 } 417 } else { 418 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 419 if (rc) { 420 dev_printk(KERN_ERR, &pdev->dev, 421 "32-bit DMA enable failed\n"); 422 return rc; 423 } 424 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 425 if (rc) { 426 dev_printk(KERN_ERR, &pdev->dev, 427 "32-bit consistent DMA enable failed\n"); 428 return rc; 429 } 430 } 431 432 return rc; 433 } 434 435 static int mvs_prep_sas_ha_init(struct Scsi_Host *shost, 436 const struct mvs_chip_info *chip_info) 437 { 438 int phy_nr, port_nr; unsigned short core_nr; 439 struct asd_sas_phy **arr_phy; 440 struct asd_sas_port **arr_port; 441 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 442 443 core_nr = chip_info->n_host; 444 phy_nr = core_nr * chip_info->n_phy; 445 port_nr = phy_nr; 446 447 memset(sha, 0x00, sizeof(struct sas_ha_struct)); 448 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL); 449 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL); 450 if (!arr_phy || !arr_port) 451 goto exit_free; 452 453 sha->sas_phy = arr_phy; 454 sha->sas_port = arr_port; 455 sha->core.shost = shost; 456 457 sha->lldd_ha = kzalloc(sizeof(struct mvs_prv_info), GFP_KERNEL); 458 if (!sha->lldd_ha) 459 goto exit_free; 460 461 ((struct mvs_prv_info *)sha->lldd_ha)->n_host = core_nr; 462 463 shost->transportt = mvs_stt; 464 shost->max_id = MVS_MAX_DEVICES; 465 shost->max_lun = ~0; 466 shost->max_channel = 1; 467 shost->max_cmd_len = 16; 468 469 return 0; 470 exit_free: 471 kfree(arr_phy); 472 kfree(arr_port); 473 return -1; 474 475 } 476 477 static void mvs_post_sas_ha_init(struct Scsi_Host *shost, 478 const struct mvs_chip_info *chip_info) 479 { 480 int can_queue, i = 0, j = 0; 481 struct mvs_info *mvi = NULL; 482 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 483 unsigned short nr_core = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 484 485 for (j = 0; j < nr_core; j++) { 486 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j]; 487 for (i = 0; i < chip_info->n_phy; i++) { 488 sha->sas_phy[j * chip_info->n_phy + i] = 489 &mvi->phy[i].sas_phy; 490 sha->sas_port[j * chip_info->n_phy + i] = 491 &mvi->port[i].sas_port; 492 } 493 } 494 495 sha->sas_ha_name = DRV_NAME; 496 sha->dev = mvi->dev; 497 sha->lldd_module = THIS_MODULE; 498 sha->sas_addr = &mvi->sas_addr[0]; 499 500 sha->num_phys = nr_core * chip_info->n_phy; 501 502 if (mvi->flags & MVF_FLAG_SOC) 503 can_queue = MVS_SOC_CAN_QUEUE; 504 else 505 can_queue = MVS_CHIP_SLOT_SZ; 506 507 shost->sg_tablesize = min_t(u16, SG_ALL, MVS_MAX_SG); 508 shost->can_queue = can_queue; 509 mvi->shost->cmd_per_lun = MVS_QUEUE_SIZE; 510 sha->core.shost = mvi->shost; 511 } 512 513 static void mvs_init_sas_add(struct mvs_info *mvi) 514 { 515 u8 i; 516 for (i = 0; i < mvi->chip->n_phy; i++) { 517 mvi->phy[i].dev_sas_addr = 0x5005043011ab0000ULL; 518 mvi->phy[i].dev_sas_addr = 519 cpu_to_be64((u64)(*(u64 *)&mvi->phy[i].dev_sas_addr)); 520 } 521 522 memcpy(mvi->sas_addr, &mvi->phy[0].dev_sas_addr, SAS_ADDR_SIZE); 523 } 524 525 static int mvs_pci_init(struct pci_dev *pdev, const struct pci_device_id *ent) 526 { 527 unsigned int rc, nhost = 0; 528 struct mvs_info *mvi; 529 struct mvs_prv_info *mpi; 530 irq_handler_t irq_handler = mvs_interrupt; 531 struct Scsi_Host *shost = NULL; 532 const struct mvs_chip_info *chip; 533 534 dev_printk(KERN_INFO, &pdev->dev, 535 "mvsas: driver version %s\n", DRV_VERSION); 536 rc = pci_enable_device(pdev); 537 if (rc) 538 goto err_out_enable; 539 540 pci_set_master(pdev); 541 542 rc = pci_request_regions(pdev, DRV_NAME); 543 if (rc) 544 goto err_out_disable; 545 546 rc = pci_go_64(pdev); 547 if (rc) 548 goto err_out_regions; 549 550 shost = scsi_host_alloc(&mvs_sht, sizeof(void *)); 551 if (!shost) { 552 rc = -ENOMEM; 553 goto err_out_regions; 554 } 555 556 chip = &mvs_chips[ent->driver_data]; 557 SHOST_TO_SAS_HA(shost) = 558 kcalloc(1, sizeof(struct sas_ha_struct), GFP_KERNEL); 559 if (!SHOST_TO_SAS_HA(shost)) { 560 kfree(shost); 561 rc = -ENOMEM; 562 goto err_out_regions; 563 } 564 565 rc = mvs_prep_sas_ha_init(shost, chip); 566 if (rc) { 567 kfree(shost); 568 rc = -ENOMEM; 569 goto err_out_regions; 570 } 571 572 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost)); 573 574 do { 575 mvi = mvs_pci_alloc(pdev, ent, shost, nhost); 576 if (!mvi) { 577 rc = -ENOMEM; 578 goto err_out_regions; 579 } 580 581 memset(&mvi->hba_info_param, 0xFF, 582 sizeof(struct hba_info_page)); 583 584 mvs_init_sas_add(mvi); 585 586 mvi->instance = nhost; 587 rc = MVS_CHIP_DISP->chip_init(mvi); 588 if (rc) { 589 mvs_free(mvi); 590 goto err_out_regions; 591 } 592 nhost++; 593 } while (nhost < chip->n_host); 594 mpi = (struct mvs_prv_info *)(SHOST_TO_SAS_HA(shost)->lldd_ha); 595 #ifdef CONFIG_SCSI_MVSAS_TASKLET 596 tasklet_init(&(mpi->mv_tasklet), mvs_tasklet, 597 (unsigned long)SHOST_TO_SAS_HA(shost)); 598 #endif 599 600 mvs_post_sas_ha_init(shost, chip); 601 602 rc = scsi_add_host(shost, &pdev->dev); 603 if (rc) 604 goto err_out_shost; 605 606 rc = sas_register_ha(SHOST_TO_SAS_HA(shost)); 607 if (rc) 608 goto err_out_shost; 609 rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED, 610 DRV_NAME, SHOST_TO_SAS_HA(shost)); 611 if (rc) 612 goto err_not_sas; 613 614 MVS_CHIP_DISP->interrupt_enable(mvi); 615 616 scsi_scan_host(mvi->shost); 617 618 return 0; 619 620 err_not_sas: 621 sas_unregister_ha(SHOST_TO_SAS_HA(shost)); 622 err_out_shost: 623 scsi_remove_host(mvi->shost); 624 err_out_regions: 625 pci_release_regions(pdev); 626 err_out_disable: 627 pci_disable_device(pdev); 628 err_out_enable: 629 return rc; 630 } 631 632 static void mvs_pci_remove(struct pci_dev *pdev) 633 { 634 unsigned short core_nr, i = 0; 635 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 636 struct mvs_info *mvi = NULL; 637 638 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 639 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; 640 641 #ifdef CONFIG_SCSI_MVSAS_TASKLET 642 tasklet_kill(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet); 643 #endif 644 645 scsi_remove_host(mvi->shost); 646 sas_unregister_ha(sha); 647 sas_remove_host(mvi->shost); 648 649 MVS_CHIP_DISP->interrupt_disable(mvi); 650 free_irq(mvi->pdev->irq, sha); 651 for (i = 0; i < core_nr; i++) { 652 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; 653 mvs_free(mvi); 654 } 655 kfree(sha->sas_phy); 656 kfree(sha->sas_port); 657 kfree(sha); 658 pci_release_regions(pdev); 659 pci_disable_device(pdev); 660 return; 661 } 662 663 static struct pci_device_id mvs_pci_table[] = { 664 { PCI_VDEVICE(MARVELL, 0x6320), chip_6320 }, 665 { PCI_VDEVICE(MARVELL, 0x6340), chip_6440 }, 666 { 667 .vendor = PCI_VENDOR_ID_MARVELL, 668 .device = 0x6440, 669 .subvendor = PCI_ANY_ID, 670 .subdevice = 0x6480, 671 .class = 0, 672 .class_mask = 0, 673 .driver_data = chip_6485, 674 }, 675 { PCI_VDEVICE(MARVELL, 0x6440), chip_6440 }, 676 { PCI_VDEVICE(MARVELL, 0x6485), chip_6485 }, 677 { PCI_VDEVICE(MARVELL, 0x9480), chip_9480 }, 678 { PCI_VDEVICE(MARVELL, 0x9180), chip_9180 }, 679 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1300), chip_1300 }, 680 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1320), chip_1320 }, 681 { PCI_VDEVICE(ADAPTEC2, 0x0450), chip_6440 }, 682 { PCI_VDEVICE(TTI, 0x2710), chip_9480 }, 683 { PCI_VDEVICE(TTI, 0x2720), chip_9480 }, 684 { PCI_VDEVICE(TTI, 0x2721), chip_9480 }, 685 { PCI_VDEVICE(TTI, 0x2722), chip_9480 }, 686 { PCI_VDEVICE(TTI, 0x2740), chip_9480 }, 687 { PCI_VDEVICE(TTI, 0x2744), chip_9480 }, 688 { PCI_VDEVICE(TTI, 0x2760), chip_9480 }, 689 { 690 .vendor = PCI_VENDOR_ID_MARVELL_EXT, 691 .device = 0x9480, 692 .subvendor = PCI_ANY_ID, 693 .subdevice = 0x9480, 694 .class = 0, 695 .class_mask = 0, 696 .driver_data = chip_9480, 697 }, 698 { 699 .vendor = PCI_VENDOR_ID_MARVELL_EXT, 700 .device = 0x9445, 701 .subvendor = PCI_ANY_ID, 702 .subdevice = 0x9480, 703 .class = 0, 704 .class_mask = 0, 705 .driver_data = chip_9445, 706 }, 707 { PCI_VDEVICE(MARVELL_EXT, 0x9485), chip_9485 }, /* Marvell 9480/9485 (any vendor/model) */ 708 { PCI_VDEVICE(OCZ, 0x1021), chip_9485}, /* OCZ RevoDrive3 */ 709 { PCI_VDEVICE(OCZ, 0x1022), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 710 { PCI_VDEVICE(OCZ, 0x1040), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 711 { PCI_VDEVICE(OCZ, 0x1041), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 712 { PCI_VDEVICE(OCZ, 0x1042), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 713 { PCI_VDEVICE(OCZ, 0x1043), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 714 { PCI_VDEVICE(OCZ, 0x1044), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 715 { PCI_VDEVICE(OCZ, 0x1080), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 716 { PCI_VDEVICE(OCZ, 0x1083), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 717 { PCI_VDEVICE(OCZ, 0x1084), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 718 719 { } /* terminate list */ 720 }; 721 722 static struct pci_driver mvs_pci_driver = { 723 .name = DRV_NAME, 724 .id_table = mvs_pci_table, 725 .probe = mvs_pci_init, 726 .remove = mvs_pci_remove, 727 }; 728 729 static ssize_t 730 mvs_show_driver_version(struct device *cdev, 731 struct device_attribute *attr, char *buffer) 732 { 733 return snprintf(buffer, PAGE_SIZE, "%s\n", DRV_VERSION); 734 } 735 736 static DEVICE_ATTR(driver_version, 737 S_IRUGO, 738 mvs_show_driver_version, 739 NULL); 740 741 static ssize_t 742 mvs_store_interrupt_coalescing(struct device *cdev, 743 struct device_attribute *attr, 744 const char *buffer, size_t size) 745 { 746 unsigned int val = 0; 747 struct mvs_info *mvi = NULL; 748 struct Scsi_Host *shost = class_to_shost(cdev); 749 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 750 u8 i, core_nr; 751 if (buffer == NULL) 752 return size; 753 754 if (sscanf(buffer, "%u", &val) != 1) 755 return -EINVAL; 756 757 if (val >= 0x10000) { 758 mv_dprintk("interrupt coalescing timer %d us is" 759 "too long\n", val); 760 return strlen(buffer); 761 } 762 763 interrupt_coalescing = val; 764 765 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 766 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; 767 768 if (unlikely(!mvi)) 769 return -EINVAL; 770 771 for (i = 0; i < core_nr; i++) { 772 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; 773 if (MVS_CHIP_DISP->tune_interrupt) 774 MVS_CHIP_DISP->tune_interrupt(mvi, 775 interrupt_coalescing); 776 } 777 mv_dprintk("set interrupt coalescing time to %d us\n", 778 interrupt_coalescing); 779 return strlen(buffer); 780 } 781 782 static ssize_t mvs_show_interrupt_coalescing(struct device *cdev, 783 struct device_attribute *attr, char *buffer) 784 { 785 return snprintf(buffer, PAGE_SIZE, "%d\n", interrupt_coalescing); 786 } 787 788 static DEVICE_ATTR(interrupt_coalescing, 789 S_IRUGO|S_IWUSR, 790 mvs_show_interrupt_coalescing, 791 mvs_store_interrupt_coalescing); 792 793 /* task handler */ 794 struct task_struct *mvs_th; 795 static int __init mvs_init(void) 796 { 797 int rc; 798 mvs_stt = sas_domain_attach_transport(&mvs_transport_ops); 799 if (!mvs_stt) 800 return -ENOMEM; 801 802 rc = pci_register_driver(&mvs_pci_driver); 803 if (rc) 804 goto err_out; 805 806 return 0; 807 808 err_out: 809 sas_release_transport(mvs_stt); 810 return rc; 811 } 812 813 static void __exit mvs_exit(void) 814 { 815 pci_unregister_driver(&mvs_pci_driver); 816 sas_release_transport(mvs_stt); 817 } 818 819 struct device_attribute *mvst_host_attrs[] = { 820 &dev_attr_driver_version, 821 &dev_attr_interrupt_coalescing, 822 NULL, 823 }; 824 825 module_init(mvs_init); 826 module_exit(mvs_exit); 827 828 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>"); 829 MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver"); 830 MODULE_VERSION(DRV_VERSION); 831 MODULE_LICENSE("GPL"); 832 #ifdef CONFIG_PCI 833 MODULE_DEVICE_TABLE(pci, mvs_pci_table); 834 #endif 835