1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Marvell 88SE64xx/88SE94xx pci init 4 * 5 * Copyright 2007 Red Hat, Inc. 6 * Copyright 2008 Marvell. <kewei@marvell.com> 7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com> 8 */ 9 10 11 #include "mv_sas.h" 12 13 int interrupt_coalescing = 0x80; 14 15 static struct scsi_transport_template *mvs_stt; 16 static const struct mvs_chip_info mvs_chips[] = { 17 [chip_6320] = { 1, 2, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, }, 18 [chip_6440] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, }, 19 [chip_6485] = { 1, 8, 0x800, 33, 32, 6, 10, &mvs_64xx_dispatch, }, 20 [chip_9180] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, }, 21 [chip_9480] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, }, 22 [chip_9445] = { 1, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, }, 23 [chip_9485] = { 2, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, }, 24 [chip_1300] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, }, 25 [chip_1320] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, }, 26 }; 27 28 static struct device_attribute *mvst_host_attrs[]; 29 30 #define SOC_SAS_NUM 2 31 32 static struct scsi_host_template mvs_sht = { 33 .module = THIS_MODULE, 34 .name = DRV_NAME, 35 .queuecommand = sas_queuecommand, 36 .dma_need_drain = ata_scsi_dma_need_drain, 37 .target_alloc = sas_target_alloc, 38 .slave_configure = sas_slave_configure, 39 .scan_finished = mvs_scan_finished, 40 .scan_start = mvs_scan_start, 41 .change_queue_depth = sas_change_queue_depth, 42 .bios_param = sas_bios_param, 43 .can_queue = 1, 44 .this_id = -1, 45 .sg_tablesize = SG_ALL, 46 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 47 .eh_device_reset_handler = sas_eh_device_reset_handler, 48 .eh_target_reset_handler = sas_eh_target_reset_handler, 49 .target_destroy = sas_target_destroy, 50 .ioctl = sas_ioctl, 51 #ifdef CONFIG_COMPAT 52 .compat_ioctl = sas_ioctl, 53 #endif 54 .shost_attrs = mvst_host_attrs, 55 .track_queue_depth = 1, 56 }; 57 58 static struct sas_domain_function_template mvs_transport_ops = { 59 .lldd_dev_found = mvs_dev_found, 60 .lldd_dev_gone = mvs_dev_gone, 61 .lldd_execute_task = mvs_queue_command, 62 .lldd_control_phy = mvs_phy_control, 63 64 .lldd_abort_task = mvs_abort_task, 65 .lldd_abort_task_set = mvs_abort_task_set, 66 .lldd_clear_aca = mvs_clear_aca, 67 .lldd_clear_task_set = mvs_clear_task_set, 68 .lldd_I_T_nexus_reset = mvs_I_T_nexus_reset, 69 .lldd_lu_reset = mvs_lu_reset, 70 .lldd_query_task = mvs_query_task, 71 .lldd_port_formed = mvs_port_formed, 72 .lldd_port_deformed = mvs_port_deformed, 73 74 .lldd_write_gpio = mvs_gpio_write, 75 76 }; 77 78 static void mvs_phy_init(struct mvs_info *mvi, int phy_id) 79 { 80 struct mvs_phy *phy = &mvi->phy[phy_id]; 81 struct asd_sas_phy *sas_phy = &phy->sas_phy; 82 83 phy->mvi = mvi; 84 phy->port = NULL; 85 timer_setup(&phy->timer, NULL, 0); 86 sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0; 87 sas_phy->class = SAS; 88 sas_phy->iproto = SAS_PROTOCOL_ALL; 89 sas_phy->tproto = 0; 90 sas_phy->type = PHY_TYPE_PHYSICAL; 91 sas_phy->role = PHY_ROLE_INITIATOR; 92 sas_phy->oob_mode = OOB_NOT_CONNECTED; 93 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN; 94 95 sas_phy->id = phy_id; 96 sas_phy->sas_addr = &mvi->sas_addr[0]; 97 sas_phy->frame_rcvd = &phy->frame_rcvd[0]; 98 sas_phy->ha = (struct sas_ha_struct *)mvi->shost->hostdata; 99 sas_phy->lldd_phy = phy; 100 } 101 102 static void mvs_free(struct mvs_info *mvi) 103 { 104 struct mvs_wq *mwq; 105 int slot_nr; 106 107 if (!mvi) 108 return; 109 110 if (mvi->flags & MVF_FLAG_SOC) 111 slot_nr = MVS_SOC_SLOTS; 112 else 113 slot_nr = MVS_CHIP_SLOT_SZ; 114 115 dma_pool_destroy(mvi->dma_pool); 116 117 if (mvi->tx) 118 dma_free_coherent(mvi->dev, 119 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ, 120 mvi->tx, mvi->tx_dma); 121 if (mvi->rx_fis) 122 dma_free_coherent(mvi->dev, MVS_RX_FISL_SZ, 123 mvi->rx_fis, mvi->rx_fis_dma); 124 if (mvi->rx) 125 dma_free_coherent(mvi->dev, 126 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1), 127 mvi->rx, mvi->rx_dma); 128 if (mvi->slot) 129 dma_free_coherent(mvi->dev, 130 sizeof(*mvi->slot) * slot_nr, 131 mvi->slot, mvi->slot_dma); 132 133 if (mvi->bulk_buffer) 134 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE, 135 mvi->bulk_buffer, mvi->bulk_buffer_dma); 136 if (mvi->bulk_buffer1) 137 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE, 138 mvi->bulk_buffer1, mvi->bulk_buffer_dma1); 139 140 MVS_CHIP_DISP->chip_iounmap(mvi); 141 if (mvi->shost) 142 scsi_host_put(mvi->shost); 143 list_for_each_entry(mwq, &mvi->wq_list, entry) 144 cancel_delayed_work(&mwq->work_q); 145 kfree(mvi->tags); 146 kfree(mvi); 147 } 148 149 #ifdef CONFIG_SCSI_MVSAS_TASKLET 150 static void mvs_tasklet(unsigned long opaque) 151 { 152 u32 stat; 153 u16 core_nr, i = 0; 154 155 struct mvs_info *mvi; 156 struct sas_ha_struct *sha = (struct sas_ha_struct *)opaque; 157 158 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 159 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; 160 161 if (unlikely(!mvi)) 162 BUG_ON(1); 163 164 stat = MVS_CHIP_DISP->isr_status(mvi, mvi->pdev->irq); 165 if (!stat) 166 goto out; 167 168 for (i = 0; i < core_nr; i++) { 169 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; 170 MVS_CHIP_DISP->isr(mvi, mvi->pdev->irq, stat); 171 } 172 out: 173 MVS_CHIP_DISP->interrupt_enable(mvi); 174 175 } 176 #endif 177 178 static irqreturn_t mvs_interrupt(int irq, void *opaque) 179 { 180 u32 stat; 181 struct mvs_info *mvi; 182 struct sas_ha_struct *sha = opaque; 183 #ifndef CONFIG_SCSI_MVSAS_TASKLET 184 u32 i; 185 u32 core_nr; 186 187 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 188 #endif 189 190 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; 191 192 if (unlikely(!mvi)) 193 return IRQ_NONE; 194 #ifdef CONFIG_SCSI_MVSAS_TASKLET 195 MVS_CHIP_DISP->interrupt_disable(mvi); 196 #endif 197 198 stat = MVS_CHIP_DISP->isr_status(mvi, irq); 199 if (!stat) { 200 #ifdef CONFIG_SCSI_MVSAS_TASKLET 201 MVS_CHIP_DISP->interrupt_enable(mvi); 202 #endif 203 return IRQ_NONE; 204 } 205 206 #ifdef CONFIG_SCSI_MVSAS_TASKLET 207 tasklet_schedule(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet); 208 #else 209 for (i = 0; i < core_nr; i++) { 210 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; 211 MVS_CHIP_DISP->isr(mvi, irq, stat); 212 } 213 #endif 214 return IRQ_HANDLED; 215 } 216 217 static int mvs_alloc(struct mvs_info *mvi, struct Scsi_Host *shost) 218 { 219 int i = 0, slot_nr; 220 char pool_name[32]; 221 222 if (mvi->flags & MVF_FLAG_SOC) 223 slot_nr = MVS_SOC_SLOTS; 224 else 225 slot_nr = MVS_CHIP_SLOT_SZ; 226 227 spin_lock_init(&mvi->lock); 228 for (i = 0; i < mvi->chip->n_phy; i++) { 229 mvs_phy_init(mvi, i); 230 mvi->port[i].wide_port_phymap = 0; 231 mvi->port[i].port_attached = 0; 232 INIT_LIST_HEAD(&mvi->port[i].list); 233 } 234 for (i = 0; i < MVS_MAX_DEVICES; i++) { 235 mvi->devices[i].taskfileset = MVS_ID_NOT_MAPPED; 236 mvi->devices[i].dev_type = SAS_PHY_UNUSED; 237 mvi->devices[i].device_id = i; 238 mvi->devices[i].dev_status = MVS_DEV_NORMAL; 239 } 240 241 /* 242 * alloc and init our DMA areas 243 */ 244 mvi->tx = dma_alloc_coherent(mvi->dev, 245 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ, 246 &mvi->tx_dma, GFP_KERNEL); 247 if (!mvi->tx) 248 goto err_out; 249 memset(mvi->tx, 0, sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ); 250 mvi->rx_fis = dma_alloc_coherent(mvi->dev, MVS_RX_FISL_SZ, 251 &mvi->rx_fis_dma, GFP_KERNEL); 252 if (!mvi->rx_fis) 253 goto err_out; 254 memset(mvi->rx_fis, 0, MVS_RX_FISL_SZ); 255 256 mvi->rx = dma_alloc_coherent(mvi->dev, 257 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1), 258 &mvi->rx_dma, GFP_KERNEL); 259 if (!mvi->rx) 260 goto err_out; 261 memset(mvi->rx, 0, sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1)); 262 mvi->rx[0] = cpu_to_le32(0xfff); 263 mvi->rx_cons = 0xfff; 264 265 mvi->slot = dma_alloc_coherent(mvi->dev, 266 sizeof(*mvi->slot) * slot_nr, 267 &mvi->slot_dma, GFP_KERNEL); 268 if (!mvi->slot) 269 goto err_out; 270 memset(mvi->slot, 0, sizeof(*mvi->slot) * slot_nr); 271 272 mvi->bulk_buffer = dma_alloc_coherent(mvi->dev, 273 TRASH_BUCKET_SIZE, 274 &mvi->bulk_buffer_dma, GFP_KERNEL); 275 if (!mvi->bulk_buffer) 276 goto err_out; 277 278 mvi->bulk_buffer1 = dma_alloc_coherent(mvi->dev, 279 TRASH_BUCKET_SIZE, 280 &mvi->bulk_buffer_dma1, GFP_KERNEL); 281 if (!mvi->bulk_buffer1) 282 goto err_out; 283 284 sprintf(pool_name, "%s%d", "mvs_dma_pool", mvi->id); 285 mvi->dma_pool = dma_pool_create(pool_name, &mvi->pdev->dev, 286 MVS_SLOT_BUF_SZ, 16, 0); 287 if (!mvi->dma_pool) { 288 printk(KERN_DEBUG "failed to create dma pool %s.\n", pool_name); 289 goto err_out; 290 } 291 mvi->tags_num = slot_nr; 292 293 /* Initialize tags */ 294 mvs_tag_init(mvi); 295 return 0; 296 err_out: 297 return 1; 298 } 299 300 301 int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex) 302 { 303 unsigned long res_start, res_len, res_flag_ex = 0; 304 struct pci_dev *pdev = mvi->pdev; 305 if (bar_ex != -1) { 306 /* 307 * ioremap main and peripheral registers 308 */ 309 res_start = pci_resource_start(pdev, bar_ex); 310 res_len = pci_resource_len(pdev, bar_ex); 311 if (!res_start || !res_len) 312 goto err_out; 313 314 res_flag_ex = pci_resource_flags(pdev, bar_ex); 315 if (res_flag_ex & IORESOURCE_MEM) 316 mvi->regs_ex = ioremap(res_start, res_len); 317 else 318 mvi->regs_ex = (void *)res_start; 319 if (!mvi->regs_ex) 320 goto err_out; 321 } 322 323 res_start = pci_resource_start(pdev, bar); 324 res_len = pci_resource_len(pdev, bar); 325 if (!res_start || !res_len) { 326 iounmap(mvi->regs_ex); 327 mvi->regs_ex = NULL; 328 goto err_out; 329 } 330 331 mvi->regs = ioremap(res_start, res_len); 332 333 if (!mvi->regs) { 334 if (mvi->regs_ex && (res_flag_ex & IORESOURCE_MEM)) 335 iounmap(mvi->regs_ex); 336 mvi->regs_ex = NULL; 337 goto err_out; 338 } 339 340 return 0; 341 err_out: 342 return -1; 343 } 344 345 void mvs_iounmap(void __iomem *regs) 346 { 347 iounmap(regs); 348 } 349 350 static struct mvs_info *mvs_pci_alloc(struct pci_dev *pdev, 351 const struct pci_device_id *ent, 352 struct Scsi_Host *shost, unsigned int id) 353 { 354 struct mvs_info *mvi = NULL; 355 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 356 357 mvi = kzalloc(sizeof(*mvi) + 358 (1L << mvs_chips[ent->driver_data].slot_width) * 359 sizeof(struct mvs_slot_info), GFP_KERNEL); 360 if (!mvi) 361 return NULL; 362 363 mvi->pdev = pdev; 364 mvi->dev = &pdev->dev; 365 mvi->chip_id = ent->driver_data; 366 mvi->chip = &mvs_chips[mvi->chip_id]; 367 INIT_LIST_HEAD(&mvi->wq_list); 368 369 ((struct mvs_prv_info *)sha->lldd_ha)->mvi[id] = mvi; 370 ((struct mvs_prv_info *)sha->lldd_ha)->n_phy = mvi->chip->n_phy; 371 372 mvi->id = id; 373 mvi->sas = sha; 374 mvi->shost = shost; 375 376 mvi->tags = kzalloc(MVS_CHIP_SLOT_SZ>>3, GFP_KERNEL); 377 if (!mvi->tags) 378 goto err_out; 379 380 if (MVS_CHIP_DISP->chip_ioremap(mvi)) 381 goto err_out; 382 if (!mvs_alloc(mvi, shost)) 383 return mvi; 384 err_out: 385 mvs_free(mvi); 386 return NULL; 387 } 388 389 static int pci_go_64(struct pci_dev *pdev) 390 { 391 int rc; 392 393 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 394 if (rc) { 395 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 396 if (rc) { 397 dev_printk(KERN_ERR, &pdev->dev, 398 "32-bit DMA enable failed\n"); 399 return rc; 400 } 401 } 402 403 return rc; 404 } 405 406 static int mvs_prep_sas_ha_init(struct Scsi_Host *shost, 407 const struct mvs_chip_info *chip_info) 408 { 409 int phy_nr, port_nr; unsigned short core_nr; 410 struct asd_sas_phy **arr_phy; 411 struct asd_sas_port **arr_port; 412 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 413 414 core_nr = chip_info->n_host; 415 phy_nr = core_nr * chip_info->n_phy; 416 port_nr = phy_nr; 417 418 memset(sha, 0x00, sizeof(struct sas_ha_struct)); 419 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL); 420 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL); 421 if (!arr_phy || !arr_port) 422 goto exit_free; 423 424 sha->sas_phy = arr_phy; 425 sha->sas_port = arr_port; 426 sha->core.shost = shost; 427 428 sha->lldd_ha = kzalloc(sizeof(struct mvs_prv_info), GFP_KERNEL); 429 if (!sha->lldd_ha) 430 goto exit_free; 431 432 ((struct mvs_prv_info *)sha->lldd_ha)->n_host = core_nr; 433 434 shost->transportt = mvs_stt; 435 shost->max_id = MVS_MAX_DEVICES; 436 shost->max_lun = ~0; 437 shost->max_channel = 1; 438 shost->max_cmd_len = 16; 439 440 return 0; 441 exit_free: 442 kfree(arr_phy); 443 kfree(arr_port); 444 return -1; 445 446 } 447 448 static void mvs_post_sas_ha_init(struct Scsi_Host *shost, 449 const struct mvs_chip_info *chip_info) 450 { 451 int can_queue, i = 0, j = 0; 452 struct mvs_info *mvi = NULL; 453 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 454 unsigned short nr_core = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 455 456 for (j = 0; j < nr_core; j++) { 457 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j]; 458 for (i = 0; i < chip_info->n_phy; i++) { 459 sha->sas_phy[j * chip_info->n_phy + i] = 460 &mvi->phy[i].sas_phy; 461 sha->sas_port[j * chip_info->n_phy + i] = 462 &mvi->port[i].sas_port; 463 } 464 } 465 466 sha->sas_ha_name = DRV_NAME; 467 sha->dev = mvi->dev; 468 sha->lldd_module = THIS_MODULE; 469 sha->sas_addr = &mvi->sas_addr[0]; 470 471 sha->num_phys = nr_core * chip_info->n_phy; 472 473 if (mvi->flags & MVF_FLAG_SOC) 474 can_queue = MVS_SOC_CAN_QUEUE; 475 else 476 can_queue = MVS_CHIP_SLOT_SZ; 477 478 shost->sg_tablesize = min_t(u16, SG_ALL, MVS_MAX_SG); 479 shost->can_queue = can_queue; 480 mvi->shost->cmd_per_lun = MVS_QUEUE_SIZE; 481 sha->core.shost = mvi->shost; 482 } 483 484 static void mvs_init_sas_add(struct mvs_info *mvi) 485 { 486 u8 i; 487 for (i = 0; i < mvi->chip->n_phy; i++) { 488 mvi->phy[i].dev_sas_addr = 0x5005043011ab0000ULL; 489 mvi->phy[i].dev_sas_addr = 490 cpu_to_be64((u64)(*(u64 *)&mvi->phy[i].dev_sas_addr)); 491 } 492 493 memcpy(mvi->sas_addr, &mvi->phy[0].dev_sas_addr, SAS_ADDR_SIZE); 494 } 495 496 static int mvs_pci_init(struct pci_dev *pdev, const struct pci_device_id *ent) 497 { 498 unsigned int rc, nhost = 0; 499 struct mvs_info *mvi; 500 struct mvs_prv_info *mpi; 501 irq_handler_t irq_handler = mvs_interrupt; 502 struct Scsi_Host *shost = NULL; 503 const struct mvs_chip_info *chip; 504 505 dev_printk(KERN_INFO, &pdev->dev, 506 "mvsas: driver version %s\n", DRV_VERSION); 507 rc = pci_enable_device(pdev); 508 if (rc) 509 goto err_out_enable; 510 511 pci_set_master(pdev); 512 513 rc = pci_request_regions(pdev, DRV_NAME); 514 if (rc) 515 goto err_out_disable; 516 517 rc = pci_go_64(pdev); 518 if (rc) 519 goto err_out_regions; 520 521 shost = scsi_host_alloc(&mvs_sht, sizeof(void *)); 522 if (!shost) { 523 rc = -ENOMEM; 524 goto err_out_regions; 525 } 526 527 chip = &mvs_chips[ent->driver_data]; 528 SHOST_TO_SAS_HA(shost) = 529 kcalloc(1, sizeof(struct sas_ha_struct), GFP_KERNEL); 530 if (!SHOST_TO_SAS_HA(shost)) { 531 scsi_host_put(shost); 532 rc = -ENOMEM; 533 goto err_out_regions; 534 } 535 536 rc = mvs_prep_sas_ha_init(shost, chip); 537 if (rc) { 538 scsi_host_put(shost); 539 rc = -ENOMEM; 540 goto err_out_regions; 541 } 542 543 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost)); 544 545 do { 546 mvi = mvs_pci_alloc(pdev, ent, shost, nhost); 547 if (!mvi) { 548 rc = -ENOMEM; 549 goto err_out_regions; 550 } 551 552 memset(&mvi->hba_info_param, 0xFF, 553 sizeof(struct hba_info_page)); 554 555 mvs_init_sas_add(mvi); 556 557 mvi->instance = nhost; 558 rc = MVS_CHIP_DISP->chip_init(mvi); 559 if (rc) { 560 mvs_free(mvi); 561 goto err_out_regions; 562 } 563 nhost++; 564 } while (nhost < chip->n_host); 565 mpi = (struct mvs_prv_info *)(SHOST_TO_SAS_HA(shost)->lldd_ha); 566 #ifdef CONFIG_SCSI_MVSAS_TASKLET 567 tasklet_init(&(mpi->mv_tasklet), mvs_tasklet, 568 (unsigned long)SHOST_TO_SAS_HA(shost)); 569 #endif 570 571 mvs_post_sas_ha_init(shost, chip); 572 573 rc = scsi_add_host(shost, &pdev->dev); 574 if (rc) 575 goto err_out_shost; 576 577 rc = sas_register_ha(SHOST_TO_SAS_HA(shost)); 578 if (rc) 579 goto err_out_shost; 580 rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED, 581 DRV_NAME, SHOST_TO_SAS_HA(shost)); 582 if (rc) 583 goto err_not_sas; 584 585 MVS_CHIP_DISP->interrupt_enable(mvi); 586 587 scsi_scan_host(mvi->shost); 588 589 return 0; 590 591 err_not_sas: 592 sas_unregister_ha(SHOST_TO_SAS_HA(shost)); 593 err_out_shost: 594 scsi_remove_host(mvi->shost); 595 err_out_regions: 596 pci_release_regions(pdev); 597 err_out_disable: 598 pci_disable_device(pdev); 599 err_out_enable: 600 return rc; 601 } 602 603 static void mvs_pci_remove(struct pci_dev *pdev) 604 { 605 unsigned short core_nr, i = 0; 606 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 607 struct mvs_info *mvi = NULL; 608 609 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 610 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; 611 612 #ifdef CONFIG_SCSI_MVSAS_TASKLET 613 tasklet_kill(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet); 614 #endif 615 616 sas_unregister_ha(sha); 617 sas_remove_host(mvi->shost); 618 619 MVS_CHIP_DISP->interrupt_disable(mvi); 620 free_irq(mvi->pdev->irq, sha); 621 for (i = 0; i < core_nr; i++) { 622 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; 623 mvs_free(mvi); 624 } 625 kfree(sha->sas_phy); 626 kfree(sha->sas_port); 627 kfree(sha); 628 pci_release_regions(pdev); 629 pci_disable_device(pdev); 630 return; 631 } 632 633 static struct pci_device_id mvs_pci_table[] = { 634 { PCI_VDEVICE(MARVELL, 0x6320), chip_6320 }, 635 { PCI_VDEVICE(MARVELL, 0x6340), chip_6440 }, 636 { 637 .vendor = PCI_VENDOR_ID_MARVELL, 638 .device = 0x6440, 639 .subvendor = PCI_ANY_ID, 640 .subdevice = 0x6480, 641 .class = 0, 642 .class_mask = 0, 643 .driver_data = chip_6485, 644 }, 645 { PCI_VDEVICE(MARVELL, 0x6440), chip_6440 }, 646 { PCI_VDEVICE(MARVELL, 0x6485), chip_6485 }, 647 { PCI_VDEVICE(MARVELL, 0x9480), chip_9480 }, 648 { PCI_VDEVICE(MARVELL, 0x9180), chip_9180 }, 649 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1300), chip_1300 }, 650 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1320), chip_1320 }, 651 { PCI_VDEVICE(ADAPTEC2, 0x0450), chip_6440 }, 652 { PCI_VDEVICE(TTI, 0x2710), chip_9480 }, 653 { PCI_VDEVICE(TTI, 0x2720), chip_9480 }, 654 { PCI_VDEVICE(TTI, 0x2721), chip_9480 }, 655 { PCI_VDEVICE(TTI, 0x2722), chip_9480 }, 656 { PCI_VDEVICE(TTI, 0x2740), chip_9480 }, 657 { PCI_VDEVICE(TTI, 0x2744), chip_9480 }, 658 { PCI_VDEVICE(TTI, 0x2760), chip_9480 }, 659 { 660 .vendor = PCI_VENDOR_ID_MARVELL_EXT, 661 .device = 0x9480, 662 .subvendor = PCI_ANY_ID, 663 .subdevice = 0x9480, 664 .class = 0, 665 .class_mask = 0, 666 .driver_data = chip_9480, 667 }, 668 { 669 .vendor = PCI_VENDOR_ID_MARVELL_EXT, 670 .device = 0x9445, 671 .subvendor = PCI_ANY_ID, 672 .subdevice = 0x9480, 673 .class = 0, 674 .class_mask = 0, 675 .driver_data = chip_9445, 676 }, 677 { PCI_VDEVICE(MARVELL_EXT, 0x9485), chip_9485 }, /* Marvell 9480/9485 (any vendor/model) */ 678 { PCI_VDEVICE(OCZ, 0x1021), chip_9485}, /* OCZ RevoDrive3 */ 679 { PCI_VDEVICE(OCZ, 0x1022), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 680 { PCI_VDEVICE(OCZ, 0x1040), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 681 { PCI_VDEVICE(OCZ, 0x1041), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 682 { PCI_VDEVICE(OCZ, 0x1042), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 683 { PCI_VDEVICE(OCZ, 0x1043), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 684 { PCI_VDEVICE(OCZ, 0x1044), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 685 { PCI_VDEVICE(OCZ, 0x1080), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 686 { PCI_VDEVICE(OCZ, 0x1083), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 687 { PCI_VDEVICE(OCZ, 0x1084), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 688 689 { } /* terminate list */ 690 }; 691 692 static struct pci_driver mvs_pci_driver = { 693 .name = DRV_NAME, 694 .id_table = mvs_pci_table, 695 .probe = mvs_pci_init, 696 .remove = mvs_pci_remove, 697 }; 698 699 static ssize_t 700 mvs_show_driver_version(struct device *cdev, 701 struct device_attribute *attr, char *buffer) 702 { 703 return snprintf(buffer, PAGE_SIZE, "%s\n", DRV_VERSION); 704 } 705 706 static DEVICE_ATTR(driver_version, 707 S_IRUGO, 708 mvs_show_driver_version, 709 NULL); 710 711 static ssize_t 712 mvs_store_interrupt_coalescing(struct device *cdev, 713 struct device_attribute *attr, 714 const char *buffer, size_t size) 715 { 716 unsigned int val = 0; 717 struct mvs_info *mvi = NULL; 718 struct Scsi_Host *shost = class_to_shost(cdev); 719 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 720 u8 i, core_nr; 721 if (buffer == NULL) 722 return size; 723 724 if (sscanf(buffer, "%u", &val) != 1) 725 return -EINVAL; 726 727 if (val >= 0x10000) { 728 mv_dprintk("interrupt coalescing timer %d us is" 729 "too long\n", val); 730 return strlen(buffer); 731 } 732 733 interrupt_coalescing = val; 734 735 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 736 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; 737 738 if (unlikely(!mvi)) 739 return -EINVAL; 740 741 for (i = 0; i < core_nr; i++) { 742 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; 743 if (MVS_CHIP_DISP->tune_interrupt) 744 MVS_CHIP_DISP->tune_interrupt(mvi, 745 interrupt_coalescing); 746 } 747 mv_dprintk("set interrupt coalescing time to %d us\n", 748 interrupt_coalescing); 749 return strlen(buffer); 750 } 751 752 static ssize_t mvs_show_interrupt_coalescing(struct device *cdev, 753 struct device_attribute *attr, char *buffer) 754 { 755 return snprintf(buffer, PAGE_SIZE, "%d\n", interrupt_coalescing); 756 } 757 758 static DEVICE_ATTR(interrupt_coalescing, 759 S_IRUGO|S_IWUSR, 760 mvs_show_interrupt_coalescing, 761 mvs_store_interrupt_coalescing); 762 763 static int __init mvs_init(void) 764 { 765 int rc; 766 mvs_stt = sas_domain_attach_transport(&mvs_transport_ops); 767 if (!mvs_stt) 768 return -ENOMEM; 769 770 rc = pci_register_driver(&mvs_pci_driver); 771 if (rc) 772 goto err_out; 773 774 return 0; 775 776 err_out: 777 sas_release_transport(mvs_stt); 778 return rc; 779 } 780 781 static void __exit mvs_exit(void) 782 { 783 pci_unregister_driver(&mvs_pci_driver); 784 sas_release_transport(mvs_stt); 785 } 786 787 static struct device_attribute *mvst_host_attrs[] = { 788 &dev_attr_driver_version, 789 &dev_attr_interrupt_coalescing, 790 NULL, 791 }; 792 793 module_init(mvs_init); 794 module_exit(mvs_exit); 795 796 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>"); 797 MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver"); 798 MODULE_VERSION(DRV_VERSION); 799 MODULE_LICENSE("GPL"); 800 #ifdef CONFIG_PCI 801 MODULE_DEVICE_TABLE(pci, mvs_pci_table); 802 #endif 803