1 /* 2 * Marvell 88SE64xx/88SE94xx pci init 3 * 4 * Copyright 2007 Red Hat, Inc. 5 * Copyright 2008 Marvell. <kewei@marvell.com> 6 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com> 7 * 8 * This file is licensed under GPLv2. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; version 2 of the 13 * License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 23 * USA 24 */ 25 26 27 #include "mv_sas.h" 28 29 int interrupt_coalescing = 0x80; 30 31 static struct scsi_transport_template *mvs_stt; 32 static const struct mvs_chip_info mvs_chips[] = { 33 [chip_6320] = { 1, 2, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, }, 34 [chip_6440] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, }, 35 [chip_6485] = { 1, 8, 0x800, 33, 32, 6, 10, &mvs_64xx_dispatch, }, 36 [chip_9180] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, }, 37 [chip_9480] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, }, 38 [chip_9445] = { 1, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, }, 39 [chip_9485] = { 2, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, }, 40 [chip_1300] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, }, 41 [chip_1320] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, }, 42 }; 43 44 struct device_attribute *mvst_host_attrs[]; 45 46 #define SOC_SAS_NUM 2 47 48 static struct scsi_host_template mvs_sht = { 49 .module = THIS_MODULE, 50 .name = DRV_NAME, 51 .queuecommand = sas_queuecommand, 52 .target_alloc = sas_target_alloc, 53 .slave_configure = sas_slave_configure, 54 .scan_finished = mvs_scan_finished, 55 .scan_start = mvs_scan_start, 56 .change_queue_depth = sas_change_queue_depth, 57 .bios_param = sas_bios_param, 58 .can_queue = 1, 59 .this_id = -1, 60 .sg_tablesize = SG_ALL, 61 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 62 .use_clustering = ENABLE_CLUSTERING, 63 .eh_device_reset_handler = sas_eh_device_reset_handler, 64 .eh_target_reset_handler = sas_eh_target_reset_handler, 65 .target_destroy = sas_target_destroy, 66 .ioctl = sas_ioctl, 67 .shost_attrs = mvst_host_attrs, 68 .track_queue_depth = 1, 69 }; 70 71 static struct sas_domain_function_template mvs_transport_ops = { 72 .lldd_dev_found = mvs_dev_found, 73 .lldd_dev_gone = mvs_dev_gone, 74 .lldd_execute_task = mvs_queue_command, 75 .lldd_control_phy = mvs_phy_control, 76 77 .lldd_abort_task = mvs_abort_task, 78 .lldd_abort_task_set = mvs_abort_task_set, 79 .lldd_clear_aca = mvs_clear_aca, 80 .lldd_clear_task_set = mvs_clear_task_set, 81 .lldd_I_T_nexus_reset = mvs_I_T_nexus_reset, 82 .lldd_lu_reset = mvs_lu_reset, 83 .lldd_query_task = mvs_query_task, 84 .lldd_port_formed = mvs_port_formed, 85 .lldd_port_deformed = mvs_port_deformed, 86 87 .lldd_write_gpio = mvs_gpio_write, 88 89 }; 90 91 static void mvs_phy_init(struct mvs_info *mvi, int phy_id) 92 { 93 struct mvs_phy *phy = &mvi->phy[phy_id]; 94 struct asd_sas_phy *sas_phy = &phy->sas_phy; 95 96 phy->mvi = mvi; 97 phy->port = NULL; 98 timer_setup(&phy->timer, NULL, 0); 99 sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0; 100 sas_phy->class = SAS; 101 sas_phy->iproto = SAS_PROTOCOL_ALL; 102 sas_phy->tproto = 0; 103 sas_phy->type = PHY_TYPE_PHYSICAL; 104 sas_phy->role = PHY_ROLE_INITIATOR; 105 sas_phy->oob_mode = OOB_NOT_CONNECTED; 106 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN; 107 108 sas_phy->id = phy_id; 109 sas_phy->sas_addr = &mvi->sas_addr[0]; 110 sas_phy->frame_rcvd = &phy->frame_rcvd[0]; 111 sas_phy->ha = (struct sas_ha_struct *)mvi->shost->hostdata; 112 sas_phy->lldd_phy = phy; 113 } 114 115 static void mvs_free(struct mvs_info *mvi) 116 { 117 struct mvs_wq *mwq; 118 int slot_nr; 119 120 if (!mvi) 121 return; 122 123 if (mvi->flags & MVF_FLAG_SOC) 124 slot_nr = MVS_SOC_SLOTS; 125 else 126 slot_nr = MVS_CHIP_SLOT_SZ; 127 128 dma_pool_destroy(mvi->dma_pool); 129 130 if (mvi->tx) 131 dma_free_coherent(mvi->dev, 132 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ, 133 mvi->tx, mvi->tx_dma); 134 if (mvi->rx_fis) 135 dma_free_coherent(mvi->dev, MVS_RX_FISL_SZ, 136 mvi->rx_fis, mvi->rx_fis_dma); 137 if (mvi->rx) 138 dma_free_coherent(mvi->dev, 139 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1), 140 mvi->rx, mvi->rx_dma); 141 if (mvi->slot) 142 dma_free_coherent(mvi->dev, 143 sizeof(*mvi->slot) * slot_nr, 144 mvi->slot, mvi->slot_dma); 145 146 if (mvi->bulk_buffer) 147 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE, 148 mvi->bulk_buffer, mvi->bulk_buffer_dma); 149 if (mvi->bulk_buffer1) 150 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE, 151 mvi->bulk_buffer1, mvi->bulk_buffer_dma1); 152 153 MVS_CHIP_DISP->chip_iounmap(mvi); 154 if (mvi->shost) 155 scsi_host_put(mvi->shost); 156 list_for_each_entry(mwq, &mvi->wq_list, entry) 157 cancel_delayed_work(&mwq->work_q); 158 kfree(mvi->tags); 159 kfree(mvi); 160 } 161 162 #ifdef CONFIG_SCSI_MVSAS_TASKLET 163 static void mvs_tasklet(unsigned long opaque) 164 { 165 u32 stat; 166 u16 core_nr, i = 0; 167 168 struct mvs_info *mvi; 169 struct sas_ha_struct *sha = (struct sas_ha_struct *)opaque; 170 171 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 172 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; 173 174 if (unlikely(!mvi)) 175 BUG_ON(1); 176 177 stat = MVS_CHIP_DISP->isr_status(mvi, mvi->pdev->irq); 178 if (!stat) 179 goto out; 180 181 for (i = 0; i < core_nr; i++) { 182 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; 183 MVS_CHIP_DISP->isr(mvi, mvi->pdev->irq, stat); 184 } 185 out: 186 MVS_CHIP_DISP->interrupt_enable(mvi); 187 188 } 189 #endif 190 191 static irqreturn_t mvs_interrupt(int irq, void *opaque) 192 { 193 u32 core_nr; 194 u32 stat; 195 struct mvs_info *mvi; 196 struct sas_ha_struct *sha = opaque; 197 #ifndef CONFIG_SCSI_MVSAS_TASKLET 198 u32 i; 199 #endif 200 201 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 202 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; 203 204 if (unlikely(!mvi)) 205 return IRQ_NONE; 206 #ifdef CONFIG_SCSI_MVSAS_TASKLET 207 MVS_CHIP_DISP->interrupt_disable(mvi); 208 #endif 209 210 stat = MVS_CHIP_DISP->isr_status(mvi, irq); 211 if (!stat) { 212 #ifdef CONFIG_SCSI_MVSAS_TASKLET 213 MVS_CHIP_DISP->interrupt_enable(mvi); 214 #endif 215 return IRQ_NONE; 216 } 217 218 #ifdef CONFIG_SCSI_MVSAS_TASKLET 219 tasklet_schedule(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet); 220 #else 221 for (i = 0; i < core_nr; i++) { 222 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; 223 MVS_CHIP_DISP->isr(mvi, irq, stat); 224 } 225 #endif 226 return IRQ_HANDLED; 227 } 228 229 static int mvs_alloc(struct mvs_info *mvi, struct Scsi_Host *shost) 230 { 231 int i = 0, slot_nr; 232 char pool_name[32]; 233 234 if (mvi->flags & MVF_FLAG_SOC) 235 slot_nr = MVS_SOC_SLOTS; 236 else 237 slot_nr = MVS_CHIP_SLOT_SZ; 238 239 spin_lock_init(&mvi->lock); 240 for (i = 0; i < mvi->chip->n_phy; i++) { 241 mvs_phy_init(mvi, i); 242 mvi->port[i].wide_port_phymap = 0; 243 mvi->port[i].port_attached = 0; 244 INIT_LIST_HEAD(&mvi->port[i].list); 245 } 246 for (i = 0; i < MVS_MAX_DEVICES; i++) { 247 mvi->devices[i].taskfileset = MVS_ID_NOT_MAPPED; 248 mvi->devices[i].dev_type = SAS_PHY_UNUSED; 249 mvi->devices[i].device_id = i; 250 mvi->devices[i].dev_status = MVS_DEV_NORMAL; 251 } 252 253 /* 254 * alloc and init our DMA areas 255 */ 256 mvi->tx = dma_alloc_coherent(mvi->dev, 257 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ, 258 &mvi->tx_dma, GFP_KERNEL); 259 if (!mvi->tx) 260 goto err_out; 261 memset(mvi->tx, 0, sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ); 262 mvi->rx_fis = dma_alloc_coherent(mvi->dev, MVS_RX_FISL_SZ, 263 &mvi->rx_fis_dma, GFP_KERNEL); 264 if (!mvi->rx_fis) 265 goto err_out; 266 memset(mvi->rx_fis, 0, MVS_RX_FISL_SZ); 267 268 mvi->rx = dma_alloc_coherent(mvi->dev, 269 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1), 270 &mvi->rx_dma, GFP_KERNEL); 271 if (!mvi->rx) 272 goto err_out; 273 memset(mvi->rx, 0, sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1)); 274 mvi->rx[0] = cpu_to_le32(0xfff); 275 mvi->rx_cons = 0xfff; 276 277 mvi->slot = dma_alloc_coherent(mvi->dev, 278 sizeof(*mvi->slot) * slot_nr, 279 &mvi->slot_dma, GFP_KERNEL); 280 if (!mvi->slot) 281 goto err_out; 282 memset(mvi->slot, 0, sizeof(*mvi->slot) * slot_nr); 283 284 mvi->bulk_buffer = dma_alloc_coherent(mvi->dev, 285 TRASH_BUCKET_SIZE, 286 &mvi->bulk_buffer_dma, GFP_KERNEL); 287 if (!mvi->bulk_buffer) 288 goto err_out; 289 290 mvi->bulk_buffer1 = dma_alloc_coherent(mvi->dev, 291 TRASH_BUCKET_SIZE, 292 &mvi->bulk_buffer_dma1, GFP_KERNEL); 293 if (!mvi->bulk_buffer1) 294 goto err_out; 295 296 sprintf(pool_name, "%s%d", "mvs_dma_pool", mvi->id); 297 mvi->dma_pool = dma_pool_create(pool_name, &mvi->pdev->dev, 298 MVS_SLOT_BUF_SZ, 16, 0); 299 if (!mvi->dma_pool) { 300 printk(KERN_DEBUG "failed to create dma pool %s.\n", pool_name); 301 goto err_out; 302 } 303 mvi->tags_num = slot_nr; 304 305 /* Initialize tags */ 306 mvs_tag_init(mvi); 307 return 0; 308 err_out: 309 return 1; 310 } 311 312 313 int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex) 314 { 315 unsigned long res_start, res_len, res_flag, res_flag_ex = 0; 316 struct pci_dev *pdev = mvi->pdev; 317 if (bar_ex != -1) { 318 /* 319 * ioremap main and peripheral registers 320 */ 321 res_start = pci_resource_start(pdev, bar_ex); 322 res_len = pci_resource_len(pdev, bar_ex); 323 if (!res_start || !res_len) 324 goto err_out; 325 326 res_flag_ex = pci_resource_flags(pdev, bar_ex); 327 if (res_flag_ex & IORESOURCE_MEM) 328 mvi->regs_ex = ioremap(res_start, res_len); 329 else 330 mvi->regs_ex = (void *)res_start; 331 if (!mvi->regs_ex) 332 goto err_out; 333 } 334 335 res_start = pci_resource_start(pdev, bar); 336 res_len = pci_resource_len(pdev, bar); 337 if (!res_start || !res_len) { 338 iounmap(mvi->regs_ex); 339 mvi->regs_ex = NULL; 340 goto err_out; 341 } 342 343 res_flag = pci_resource_flags(pdev, bar); 344 mvi->regs = ioremap(res_start, res_len); 345 346 if (!mvi->regs) { 347 if (mvi->regs_ex && (res_flag_ex & IORESOURCE_MEM)) 348 iounmap(mvi->regs_ex); 349 mvi->regs_ex = NULL; 350 goto err_out; 351 } 352 353 return 0; 354 err_out: 355 return -1; 356 } 357 358 void mvs_iounmap(void __iomem *regs) 359 { 360 iounmap(regs); 361 } 362 363 static struct mvs_info *mvs_pci_alloc(struct pci_dev *pdev, 364 const struct pci_device_id *ent, 365 struct Scsi_Host *shost, unsigned int id) 366 { 367 struct mvs_info *mvi = NULL; 368 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 369 370 mvi = kzalloc(sizeof(*mvi) + 371 (1L << mvs_chips[ent->driver_data].slot_width) * 372 sizeof(struct mvs_slot_info), GFP_KERNEL); 373 if (!mvi) 374 return NULL; 375 376 mvi->pdev = pdev; 377 mvi->dev = &pdev->dev; 378 mvi->chip_id = ent->driver_data; 379 mvi->chip = &mvs_chips[mvi->chip_id]; 380 INIT_LIST_HEAD(&mvi->wq_list); 381 382 ((struct mvs_prv_info *)sha->lldd_ha)->mvi[id] = mvi; 383 ((struct mvs_prv_info *)sha->lldd_ha)->n_phy = mvi->chip->n_phy; 384 385 mvi->id = id; 386 mvi->sas = sha; 387 mvi->shost = shost; 388 389 mvi->tags = kzalloc(MVS_CHIP_SLOT_SZ>>3, GFP_KERNEL); 390 if (!mvi->tags) 391 goto err_out; 392 393 if (MVS_CHIP_DISP->chip_ioremap(mvi)) 394 goto err_out; 395 if (!mvs_alloc(mvi, shost)) 396 return mvi; 397 err_out: 398 mvs_free(mvi); 399 return NULL; 400 } 401 402 static int pci_go_64(struct pci_dev *pdev) 403 { 404 int rc; 405 406 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 407 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 408 if (rc) { 409 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 410 if (rc) { 411 dev_printk(KERN_ERR, &pdev->dev, 412 "64-bit DMA enable failed\n"); 413 return rc; 414 } 415 } 416 } else { 417 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 418 if (rc) { 419 dev_printk(KERN_ERR, &pdev->dev, 420 "32-bit DMA enable failed\n"); 421 return rc; 422 } 423 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 424 if (rc) { 425 dev_printk(KERN_ERR, &pdev->dev, 426 "32-bit consistent DMA enable failed\n"); 427 return rc; 428 } 429 } 430 431 return rc; 432 } 433 434 static int mvs_prep_sas_ha_init(struct Scsi_Host *shost, 435 const struct mvs_chip_info *chip_info) 436 { 437 int phy_nr, port_nr; unsigned short core_nr; 438 struct asd_sas_phy **arr_phy; 439 struct asd_sas_port **arr_port; 440 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 441 442 core_nr = chip_info->n_host; 443 phy_nr = core_nr * chip_info->n_phy; 444 port_nr = phy_nr; 445 446 memset(sha, 0x00, sizeof(struct sas_ha_struct)); 447 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL); 448 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL); 449 if (!arr_phy || !arr_port) 450 goto exit_free; 451 452 sha->sas_phy = arr_phy; 453 sha->sas_port = arr_port; 454 sha->core.shost = shost; 455 456 sha->lldd_ha = kzalloc(sizeof(struct mvs_prv_info), GFP_KERNEL); 457 if (!sha->lldd_ha) 458 goto exit_free; 459 460 ((struct mvs_prv_info *)sha->lldd_ha)->n_host = core_nr; 461 462 shost->transportt = mvs_stt; 463 shost->max_id = MVS_MAX_DEVICES; 464 shost->max_lun = ~0; 465 shost->max_channel = 1; 466 shost->max_cmd_len = 16; 467 468 return 0; 469 exit_free: 470 kfree(arr_phy); 471 kfree(arr_port); 472 return -1; 473 474 } 475 476 static void mvs_post_sas_ha_init(struct Scsi_Host *shost, 477 const struct mvs_chip_info *chip_info) 478 { 479 int can_queue, i = 0, j = 0; 480 struct mvs_info *mvi = NULL; 481 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 482 unsigned short nr_core = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 483 484 for (j = 0; j < nr_core; j++) { 485 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j]; 486 for (i = 0; i < chip_info->n_phy; i++) { 487 sha->sas_phy[j * chip_info->n_phy + i] = 488 &mvi->phy[i].sas_phy; 489 sha->sas_port[j * chip_info->n_phy + i] = 490 &mvi->port[i].sas_port; 491 } 492 } 493 494 sha->sas_ha_name = DRV_NAME; 495 sha->dev = mvi->dev; 496 sha->lldd_module = THIS_MODULE; 497 sha->sas_addr = &mvi->sas_addr[0]; 498 499 sha->num_phys = nr_core * chip_info->n_phy; 500 501 if (mvi->flags & MVF_FLAG_SOC) 502 can_queue = MVS_SOC_CAN_QUEUE; 503 else 504 can_queue = MVS_CHIP_SLOT_SZ; 505 506 shost->sg_tablesize = min_t(u16, SG_ALL, MVS_MAX_SG); 507 shost->can_queue = can_queue; 508 mvi->shost->cmd_per_lun = MVS_QUEUE_SIZE; 509 sha->core.shost = mvi->shost; 510 } 511 512 static void mvs_init_sas_add(struct mvs_info *mvi) 513 { 514 u8 i; 515 for (i = 0; i < mvi->chip->n_phy; i++) { 516 mvi->phy[i].dev_sas_addr = 0x5005043011ab0000ULL; 517 mvi->phy[i].dev_sas_addr = 518 cpu_to_be64((u64)(*(u64 *)&mvi->phy[i].dev_sas_addr)); 519 } 520 521 memcpy(mvi->sas_addr, &mvi->phy[0].dev_sas_addr, SAS_ADDR_SIZE); 522 } 523 524 static int mvs_pci_init(struct pci_dev *pdev, const struct pci_device_id *ent) 525 { 526 unsigned int rc, nhost = 0; 527 struct mvs_info *mvi; 528 struct mvs_prv_info *mpi; 529 irq_handler_t irq_handler = mvs_interrupt; 530 struct Scsi_Host *shost = NULL; 531 const struct mvs_chip_info *chip; 532 533 dev_printk(KERN_INFO, &pdev->dev, 534 "mvsas: driver version %s\n", DRV_VERSION); 535 rc = pci_enable_device(pdev); 536 if (rc) 537 goto err_out_enable; 538 539 pci_set_master(pdev); 540 541 rc = pci_request_regions(pdev, DRV_NAME); 542 if (rc) 543 goto err_out_disable; 544 545 rc = pci_go_64(pdev); 546 if (rc) 547 goto err_out_regions; 548 549 shost = scsi_host_alloc(&mvs_sht, sizeof(void *)); 550 if (!shost) { 551 rc = -ENOMEM; 552 goto err_out_regions; 553 } 554 555 chip = &mvs_chips[ent->driver_data]; 556 SHOST_TO_SAS_HA(shost) = 557 kcalloc(1, sizeof(struct sas_ha_struct), GFP_KERNEL); 558 if (!SHOST_TO_SAS_HA(shost)) { 559 scsi_host_put(shost); 560 rc = -ENOMEM; 561 goto err_out_regions; 562 } 563 564 rc = mvs_prep_sas_ha_init(shost, chip); 565 if (rc) { 566 scsi_host_put(shost); 567 rc = -ENOMEM; 568 goto err_out_regions; 569 } 570 571 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost)); 572 573 do { 574 mvi = mvs_pci_alloc(pdev, ent, shost, nhost); 575 if (!mvi) { 576 rc = -ENOMEM; 577 goto err_out_regions; 578 } 579 580 memset(&mvi->hba_info_param, 0xFF, 581 sizeof(struct hba_info_page)); 582 583 mvs_init_sas_add(mvi); 584 585 mvi->instance = nhost; 586 rc = MVS_CHIP_DISP->chip_init(mvi); 587 if (rc) { 588 mvs_free(mvi); 589 goto err_out_regions; 590 } 591 nhost++; 592 } while (nhost < chip->n_host); 593 mpi = (struct mvs_prv_info *)(SHOST_TO_SAS_HA(shost)->lldd_ha); 594 #ifdef CONFIG_SCSI_MVSAS_TASKLET 595 tasklet_init(&(mpi->mv_tasklet), mvs_tasklet, 596 (unsigned long)SHOST_TO_SAS_HA(shost)); 597 #endif 598 599 mvs_post_sas_ha_init(shost, chip); 600 601 rc = scsi_add_host(shost, &pdev->dev); 602 if (rc) 603 goto err_out_shost; 604 605 rc = sas_register_ha(SHOST_TO_SAS_HA(shost)); 606 if (rc) 607 goto err_out_shost; 608 rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED, 609 DRV_NAME, SHOST_TO_SAS_HA(shost)); 610 if (rc) 611 goto err_not_sas; 612 613 MVS_CHIP_DISP->interrupt_enable(mvi); 614 615 scsi_scan_host(mvi->shost); 616 617 return 0; 618 619 err_not_sas: 620 sas_unregister_ha(SHOST_TO_SAS_HA(shost)); 621 err_out_shost: 622 scsi_remove_host(mvi->shost); 623 err_out_regions: 624 pci_release_regions(pdev); 625 err_out_disable: 626 pci_disable_device(pdev); 627 err_out_enable: 628 return rc; 629 } 630 631 static void mvs_pci_remove(struct pci_dev *pdev) 632 { 633 unsigned short core_nr, i = 0; 634 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 635 struct mvs_info *mvi = NULL; 636 637 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 638 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; 639 640 #ifdef CONFIG_SCSI_MVSAS_TASKLET 641 tasklet_kill(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet); 642 #endif 643 644 sas_unregister_ha(sha); 645 sas_remove_host(mvi->shost); 646 647 MVS_CHIP_DISP->interrupt_disable(mvi); 648 free_irq(mvi->pdev->irq, sha); 649 for (i = 0; i < core_nr; i++) { 650 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; 651 mvs_free(mvi); 652 } 653 kfree(sha->sas_phy); 654 kfree(sha->sas_port); 655 kfree(sha); 656 pci_release_regions(pdev); 657 pci_disable_device(pdev); 658 return; 659 } 660 661 static struct pci_device_id mvs_pci_table[] = { 662 { PCI_VDEVICE(MARVELL, 0x6320), chip_6320 }, 663 { PCI_VDEVICE(MARVELL, 0x6340), chip_6440 }, 664 { 665 .vendor = PCI_VENDOR_ID_MARVELL, 666 .device = 0x6440, 667 .subvendor = PCI_ANY_ID, 668 .subdevice = 0x6480, 669 .class = 0, 670 .class_mask = 0, 671 .driver_data = chip_6485, 672 }, 673 { PCI_VDEVICE(MARVELL, 0x6440), chip_6440 }, 674 { PCI_VDEVICE(MARVELL, 0x6485), chip_6485 }, 675 { PCI_VDEVICE(MARVELL, 0x9480), chip_9480 }, 676 { PCI_VDEVICE(MARVELL, 0x9180), chip_9180 }, 677 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1300), chip_1300 }, 678 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1320), chip_1320 }, 679 { PCI_VDEVICE(ADAPTEC2, 0x0450), chip_6440 }, 680 { PCI_VDEVICE(TTI, 0x2710), chip_9480 }, 681 { PCI_VDEVICE(TTI, 0x2720), chip_9480 }, 682 { PCI_VDEVICE(TTI, 0x2721), chip_9480 }, 683 { PCI_VDEVICE(TTI, 0x2722), chip_9480 }, 684 { PCI_VDEVICE(TTI, 0x2740), chip_9480 }, 685 { PCI_VDEVICE(TTI, 0x2744), chip_9480 }, 686 { PCI_VDEVICE(TTI, 0x2760), chip_9480 }, 687 { 688 .vendor = PCI_VENDOR_ID_MARVELL_EXT, 689 .device = 0x9480, 690 .subvendor = PCI_ANY_ID, 691 .subdevice = 0x9480, 692 .class = 0, 693 .class_mask = 0, 694 .driver_data = chip_9480, 695 }, 696 { 697 .vendor = PCI_VENDOR_ID_MARVELL_EXT, 698 .device = 0x9445, 699 .subvendor = PCI_ANY_ID, 700 .subdevice = 0x9480, 701 .class = 0, 702 .class_mask = 0, 703 .driver_data = chip_9445, 704 }, 705 { PCI_VDEVICE(MARVELL_EXT, 0x9485), chip_9485 }, /* Marvell 9480/9485 (any vendor/model) */ 706 { PCI_VDEVICE(OCZ, 0x1021), chip_9485}, /* OCZ RevoDrive3 */ 707 { PCI_VDEVICE(OCZ, 0x1022), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 708 { PCI_VDEVICE(OCZ, 0x1040), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 709 { PCI_VDEVICE(OCZ, 0x1041), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 710 { PCI_VDEVICE(OCZ, 0x1042), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 711 { PCI_VDEVICE(OCZ, 0x1043), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 712 { PCI_VDEVICE(OCZ, 0x1044), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 713 { PCI_VDEVICE(OCZ, 0x1080), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 714 { PCI_VDEVICE(OCZ, 0x1083), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 715 { PCI_VDEVICE(OCZ, 0x1084), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 716 717 { } /* terminate list */ 718 }; 719 720 static struct pci_driver mvs_pci_driver = { 721 .name = DRV_NAME, 722 .id_table = mvs_pci_table, 723 .probe = mvs_pci_init, 724 .remove = mvs_pci_remove, 725 }; 726 727 static ssize_t 728 mvs_show_driver_version(struct device *cdev, 729 struct device_attribute *attr, char *buffer) 730 { 731 return snprintf(buffer, PAGE_SIZE, "%s\n", DRV_VERSION); 732 } 733 734 static DEVICE_ATTR(driver_version, 735 S_IRUGO, 736 mvs_show_driver_version, 737 NULL); 738 739 static ssize_t 740 mvs_store_interrupt_coalescing(struct device *cdev, 741 struct device_attribute *attr, 742 const char *buffer, size_t size) 743 { 744 unsigned int val = 0; 745 struct mvs_info *mvi = NULL; 746 struct Scsi_Host *shost = class_to_shost(cdev); 747 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 748 u8 i, core_nr; 749 if (buffer == NULL) 750 return size; 751 752 if (sscanf(buffer, "%u", &val) != 1) 753 return -EINVAL; 754 755 if (val >= 0x10000) { 756 mv_dprintk("interrupt coalescing timer %d us is" 757 "too long\n", val); 758 return strlen(buffer); 759 } 760 761 interrupt_coalescing = val; 762 763 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 764 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; 765 766 if (unlikely(!mvi)) 767 return -EINVAL; 768 769 for (i = 0; i < core_nr; i++) { 770 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; 771 if (MVS_CHIP_DISP->tune_interrupt) 772 MVS_CHIP_DISP->tune_interrupt(mvi, 773 interrupt_coalescing); 774 } 775 mv_dprintk("set interrupt coalescing time to %d us\n", 776 interrupt_coalescing); 777 return strlen(buffer); 778 } 779 780 static ssize_t mvs_show_interrupt_coalescing(struct device *cdev, 781 struct device_attribute *attr, char *buffer) 782 { 783 return snprintf(buffer, PAGE_SIZE, "%d\n", interrupt_coalescing); 784 } 785 786 static DEVICE_ATTR(interrupt_coalescing, 787 S_IRUGO|S_IWUSR, 788 mvs_show_interrupt_coalescing, 789 mvs_store_interrupt_coalescing); 790 791 /* task handler */ 792 struct task_struct *mvs_th; 793 static int __init mvs_init(void) 794 { 795 int rc; 796 mvs_stt = sas_domain_attach_transport(&mvs_transport_ops); 797 if (!mvs_stt) 798 return -ENOMEM; 799 800 rc = pci_register_driver(&mvs_pci_driver); 801 if (rc) 802 goto err_out; 803 804 return 0; 805 806 err_out: 807 sas_release_transport(mvs_stt); 808 return rc; 809 } 810 811 static void __exit mvs_exit(void) 812 { 813 pci_unregister_driver(&mvs_pci_driver); 814 sas_release_transport(mvs_stt); 815 } 816 817 struct device_attribute *mvst_host_attrs[] = { 818 &dev_attr_driver_version, 819 &dev_attr_interrupt_coalescing, 820 NULL, 821 }; 822 823 module_init(mvs_init); 824 module_exit(mvs_exit); 825 826 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>"); 827 MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver"); 828 MODULE_VERSION(DRV_VERSION); 829 MODULE_LICENSE("GPL"); 830 #ifdef CONFIG_PCI 831 MODULE_DEVICE_TABLE(pci, mvs_pci_table); 832 #endif 833