1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Marvell 88SE64xx/88SE94xx pci init 4 * 5 * Copyright 2007 Red Hat, Inc. 6 * Copyright 2008 Marvell. <kewei@marvell.com> 7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com> 8 */ 9 10 11 #include "mv_sas.h" 12 13 int interrupt_coalescing = 0x80; 14 15 static struct scsi_transport_template *mvs_stt; 16 static const struct mvs_chip_info mvs_chips[] = { 17 [chip_6320] = { 1, 2, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, }, 18 [chip_6440] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, }, 19 [chip_6485] = { 1, 8, 0x800, 33, 32, 6, 10, &mvs_64xx_dispatch, }, 20 [chip_9180] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, }, 21 [chip_9480] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, }, 22 [chip_9445] = { 1, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, }, 23 [chip_9485] = { 2, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, }, 24 [chip_1300] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, }, 25 [chip_1320] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, }, 26 }; 27 28 struct device_attribute *mvst_host_attrs[]; 29 30 #define SOC_SAS_NUM 2 31 32 static struct scsi_host_template mvs_sht = { 33 .module = THIS_MODULE, 34 .name = DRV_NAME, 35 .queuecommand = sas_queuecommand, 36 .target_alloc = sas_target_alloc, 37 .slave_configure = sas_slave_configure, 38 .scan_finished = mvs_scan_finished, 39 .scan_start = mvs_scan_start, 40 .change_queue_depth = sas_change_queue_depth, 41 .bios_param = sas_bios_param, 42 .can_queue = 1, 43 .this_id = -1, 44 .sg_tablesize = SG_ALL, 45 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 46 .eh_device_reset_handler = sas_eh_device_reset_handler, 47 .eh_target_reset_handler = sas_eh_target_reset_handler, 48 .target_destroy = sas_target_destroy, 49 .ioctl = sas_ioctl, 50 #ifdef CONFIG_COMPAT 51 .compat_ioctl = sas_ioctl, 52 #endif 53 .shost_attrs = mvst_host_attrs, 54 .track_queue_depth = 1, 55 }; 56 57 static struct sas_domain_function_template mvs_transport_ops = { 58 .lldd_dev_found = mvs_dev_found, 59 .lldd_dev_gone = mvs_dev_gone, 60 .lldd_execute_task = mvs_queue_command, 61 .lldd_control_phy = mvs_phy_control, 62 63 .lldd_abort_task = mvs_abort_task, 64 .lldd_abort_task_set = mvs_abort_task_set, 65 .lldd_clear_aca = mvs_clear_aca, 66 .lldd_clear_task_set = mvs_clear_task_set, 67 .lldd_I_T_nexus_reset = mvs_I_T_nexus_reset, 68 .lldd_lu_reset = mvs_lu_reset, 69 .lldd_query_task = mvs_query_task, 70 .lldd_port_formed = mvs_port_formed, 71 .lldd_port_deformed = mvs_port_deformed, 72 73 .lldd_write_gpio = mvs_gpio_write, 74 75 }; 76 77 static void mvs_phy_init(struct mvs_info *mvi, int phy_id) 78 { 79 struct mvs_phy *phy = &mvi->phy[phy_id]; 80 struct asd_sas_phy *sas_phy = &phy->sas_phy; 81 82 phy->mvi = mvi; 83 phy->port = NULL; 84 timer_setup(&phy->timer, NULL, 0); 85 sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0; 86 sas_phy->class = SAS; 87 sas_phy->iproto = SAS_PROTOCOL_ALL; 88 sas_phy->tproto = 0; 89 sas_phy->type = PHY_TYPE_PHYSICAL; 90 sas_phy->role = PHY_ROLE_INITIATOR; 91 sas_phy->oob_mode = OOB_NOT_CONNECTED; 92 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN; 93 94 sas_phy->id = phy_id; 95 sas_phy->sas_addr = &mvi->sas_addr[0]; 96 sas_phy->frame_rcvd = &phy->frame_rcvd[0]; 97 sas_phy->ha = (struct sas_ha_struct *)mvi->shost->hostdata; 98 sas_phy->lldd_phy = phy; 99 } 100 101 static void mvs_free(struct mvs_info *mvi) 102 { 103 struct mvs_wq *mwq; 104 int slot_nr; 105 106 if (!mvi) 107 return; 108 109 if (mvi->flags & MVF_FLAG_SOC) 110 slot_nr = MVS_SOC_SLOTS; 111 else 112 slot_nr = MVS_CHIP_SLOT_SZ; 113 114 dma_pool_destroy(mvi->dma_pool); 115 116 if (mvi->tx) 117 dma_free_coherent(mvi->dev, 118 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ, 119 mvi->tx, mvi->tx_dma); 120 if (mvi->rx_fis) 121 dma_free_coherent(mvi->dev, MVS_RX_FISL_SZ, 122 mvi->rx_fis, mvi->rx_fis_dma); 123 if (mvi->rx) 124 dma_free_coherent(mvi->dev, 125 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1), 126 mvi->rx, mvi->rx_dma); 127 if (mvi->slot) 128 dma_free_coherent(mvi->dev, 129 sizeof(*mvi->slot) * slot_nr, 130 mvi->slot, mvi->slot_dma); 131 132 if (mvi->bulk_buffer) 133 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE, 134 mvi->bulk_buffer, mvi->bulk_buffer_dma); 135 if (mvi->bulk_buffer1) 136 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE, 137 mvi->bulk_buffer1, mvi->bulk_buffer_dma1); 138 139 MVS_CHIP_DISP->chip_iounmap(mvi); 140 if (mvi->shost) 141 scsi_host_put(mvi->shost); 142 list_for_each_entry(mwq, &mvi->wq_list, entry) 143 cancel_delayed_work(&mwq->work_q); 144 kfree(mvi->tags); 145 kfree(mvi); 146 } 147 148 #ifdef CONFIG_SCSI_MVSAS_TASKLET 149 static void mvs_tasklet(unsigned long opaque) 150 { 151 u32 stat; 152 u16 core_nr, i = 0; 153 154 struct mvs_info *mvi; 155 struct sas_ha_struct *sha = (struct sas_ha_struct *)opaque; 156 157 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 158 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; 159 160 if (unlikely(!mvi)) 161 BUG_ON(1); 162 163 stat = MVS_CHIP_DISP->isr_status(mvi, mvi->pdev->irq); 164 if (!stat) 165 goto out; 166 167 for (i = 0; i < core_nr; i++) { 168 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; 169 MVS_CHIP_DISP->isr(mvi, mvi->pdev->irq, stat); 170 } 171 out: 172 MVS_CHIP_DISP->interrupt_enable(mvi); 173 174 } 175 #endif 176 177 static irqreturn_t mvs_interrupt(int irq, void *opaque) 178 { 179 u32 core_nr; 180 u32 stat; 181 struct mvs_info *mvi; 182 struct sas_ha_struct *sha = opaque; 183 #ifndef CONFIG_SCSI_MVSAS_TASKLET 184 u32 i; 185 #endif 186 187 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 188 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; 189 190 if (unlikely(!mvi)) 191 return IRQ_NONE; 192 #ifdef CONFIG_SCSI_MVSAS_TASKLET 193 MVS_CHIP_DISP->interrupt_disable(mvi); 194 #endif 195 196 stat = MVS_CHIP_DISP->isr_status(mvi, irq); 197 if (!stat) { 198 #ifdef CONFIG_SCSI_MVSAS_TASKLET 199 MVS_CHIP_DISP->interrupt_enable(mvi); 200 #endif 201 return IRQ_NONE; 202 } 203 204 #ifdef CONFIG_SCSI_MVSAS_TASKLET 205 tasklet_schedule(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet); 206 #else 207 for (i = 0; i < core_nr; i++) { 208 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; 209 MVS_CHIP_DISP->isr(mvi, irq, stat); 210 } 211 #endif 212 return IRQ_HANDLED; 213 } 214 215 static int mvs_alloc(struct mvs_info *mvi, struct Scsi_Host *shost) 216 { 217 int i = 0, slot_nr; 218 char pool_name[32]; 219 220 if (mvi->flags & MVF_FLAG_SOC) 221 slot_nr = MVS_SOC_SLOTS; 222 else 223 slot_nr = MVS_CHIP_SLOT_SZ; 224 225 spin_lock_init(&mvi->lock); 226 for (i = 0; i < mvi->chip->n_phy; i++) { 227 mvs_phy_init(mvi, i); 228 mvi->port[i].wide_port_phymap = 0; 229 mvi->port[i].port_attached = 0; 230 INIT_LIST_HEAD(&mvi->port[i].list); 231 } 232 for (i = 0; i < MVS_MAX_DEVICES; i++) { 233 mvi->devices[i].taskfileset = MVS_ID_NOT_MAPPED; 234 mvi->devices[i].dev_type = SAS_PHY_UNUSED; 235 mvi->devices[i].device_id = i; 236 mvi->devices[i].dev_status = MVS_DEV_NORMAL; 237 } 238 239 /* 240 * alloc and init our DMA areas 241 */ 242 mvi->tx = dma_alloc_coherent(mvi->dev, 243 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ, 244 &mvi->tx_dma, GFP_KERNEL); 245 if (!mvi->tx) 246 goto err_out; 247 memset(mvi->tx, 0, sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ); 248 mvi->rx_fis = dma_alloc_coherent(mvi->dev, MVS_RX_FISL_SZ, 249 &mvi->rx_fis_dma, GFP_KERNEL); 250 if (!mvi->rx_fis) 251 goto err_out; 252 memset(mvi->rx_fis, 0, MVS_RX_FISL_SZ); 253 254 mvi->rx = dma_alloc_coherent(mvi->dev, 255 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1), 256 &mvi->rx_dma, GFP_KERNEL); 257 if (!mvi->rx) 258 goto err_out; 259 memset(mvi->rx, 0, sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1)); 260 mvi->rx[0] = cpu_to_le32(0xfff); 261 mvi->rx_cons = 0xfff; 262 263 mvi->slot = dma_alloc_coherent(mvi->dev, 264 sizeof(*mvi->slot) * slot_nr, 265 &mvi->slot_dma, GFP_KERNEL); 266 if (!mvi->slot) 267 goto err_out; 268 memset(mvi->slot, 0, sizeof(*mvi->slot) * slot_nr); 269 270 mvi->bulk_buffer = dma_alloc_coherent(mvi->dev, 271 TRASH_BUCKET_SIZE, 272 &mvi->bulk_buffer_dma, GFP_KERNEL); 273 if (!mvi->bulk_buffer) 274 goto err_out; 275 276 mvi->bulk_buffer1 = dma_alloc_coherent(mvi->dev, 277 TRASH_BUCKET_SIZE, 278 &mvi->bulk_buffer_dma1, GFP_KERNEL); 279 if (!mvi->bulk_buffer1) 280 goto err_out; 281 282 sprintf(pool_name, "%s%d", "mvs_dma_pool", mvi->id); 283 mvi->dma_pool = dma_pool_create(pool_name, &mvi->pdev->dev, 284 MVS_SLOT_BUF_SZ, 16, 0); 285 if (!mvi->dma_pool) { 286 printk(KERN_DEBUG "failed to create dma pool %s.\n", pool_name); 287 goto err_out; 288 } 289 mvi->tags_num = slot_nr; 290 291 /* Initialize tags */ 292 mvs_tag_init(mvi); 293 return 0; 294 err_out: 295 return 1; 296 } 297 298 299 int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex) 300 { 301 unsigned long res_start, res_len, res_flag, res_flag_ex = 0; 302 struct pci_dev *pdev = mvi->pdev; 303 if (bar_ex != -1) { 304 /* 305 * ioremap main and peripheral registers 306 */ 307 res_start = pci_resource_start(pdev, bar_ex); 308 res_len = pci_resource_len(pdev, bar_ex); 309 if (!res_start || !res_len) 310 goto err_out; 311 312 res_flag_ex = pci_resource_flags(pdev, bar_ex); 313 if (res_flag_ex & IORESOURCE_MEM) 314 mvi->regs_ex = ioremap(res_start, res_len); 315 else 316 mvi->regs_ex = (void *)res_start; 317 if (!mvi->regs_ex) 318 goto err_out; 319 } 320 321 res_start = pci_resource_start(pdev, bar); 322 res_len = pci_resource_len(pdev, bar); 323 if (!res_start || !res_len) { 324 iounmap(mvi->regs_ex); 325 mvi->regs_ex = NULL; 326 goto err_out; 327 } 328 329 res_flag = pci_resource_flags(pdev, bar); 330 mvi->regs = ioremap(res_start, res_len); 331 332 if (!mvi->regs) { 333 if (mvi->regs_ex && (res_flag_ex & IORESOURCE_MEM)) 334 iounmap(mvi->regs_ex); 335 mvi->regs_ex = NULL; 336 goto err_out; 337 } 338 339 return 0; 340 err_out: 341 return -1; 342 } 343 344 void mvs_iounmap(void __iomem *regs) 345 { 346 iounmap(regs); 347 } 348 349 static struct mvs_info *mvs_pci_alloc(struct pci_dev *pdev, 350 const struct pci_device_id *ent, 351 struct Scsi_Host *shost, unsigned int id) 352 { 353 struct mvs_info *mvi = NULL; 354 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 355 356 mvi = kzalloc(sizeof(*mvi) + 357 (1L << mvs_chips[ent->driver_data].slot_width) * 358 sizeof(struct mvs_slot_info), GFP_KERNEL); 359 if (!mvi) 360 return NULL; 361 362 mvi->pdev = pdev; 363 mvi->dev = &pdev->dev; 364 mvi->chip_id = ent->driver_data; 365 mvi->chip = &mvs_chips[mvi->chip_id]; 366 INIT_LIST_HEAD(&mvi->wq_list); 367 368 ((struct mvs_prv_info *)sha->lldd_ha)->mvi[id] = mvi; 369 ((struct mvs_prv_info *)sha->lldd_ha)->n_phy = mvi->chip->n_phy; 370 371 mvi->id = id; 372 mvi->sas = sha; 373 mvi->shost = shost; 374 375 mvi->tags = kzalloc(MVS_CHIP_SLOT_SZ>>3, GFP_KERNEL); 376 if (!mvi->tags) 377 goto err_out; 378 379 if (MVS_CHIP_DISP->chip_ioremap(mvi)) 380 goto err_out; 381 if (!mvs_alloc(mvi, shost)) 382 return mvi; 383 err_out: 384 mvs_free(mvi); 385 return NULL; 386 } 387 388 static int pci_go_64(struct pci_dev *pdev) 389 { 390 int rc; 391 392 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 393 if (rc) { 394 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 395 if (rc) { 396 dev_printk(KERN_ERR, &pdev->dev, 397 "32-bit DMA enable failed\n"); 398 return rc; 399 } 400 } 401 402 return rc; 403 } 404 405 static int mvs_prep_sas_ha_init(struct Scsi_Host *shost, 406 const struct mvs_chip_info *chip_info) 407 { 408 int phy_nr, port_nr; unsigned short core_nr; 409 struct asd_sas_phy **arr_phy; 410 struct asd_sas_port **arr_port; 411 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 412 413 core_nr = chip_info->n_host; 414 phy_nr = core_nr * chip_info->n_phy; 415 port_nr = phy_nr; 416 417 memset(sha, 0x00, sizeof(struct sas_ha_struct)); 418 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL); 419 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL); 420 if (!arr_phy || !arr_port) 421 goto exit_free; 422 423 sha->sas_phy = arr_phy; 424 sha->sas_port = arr_port; 425 sha->core.shost = shost; 426 427 sha->lldd_ha = kzalloc(sizeof(struct mvs_prv_info), GFP_KERNEL); 428 if (!sha->lldd_ha) 429 goto exit_free; 430 431 ((struct mvs_prv_info *)sha->lldd_ha)->n_host = core_nr; 432 433 shost->transportt = mvs_stt; 434 shost->max_id = MVS_MAX_DEVICES; 435 shost->max_lun = ~0; 436 shost->max_channel = 1; 437 shost->max_cmd_len = 16; 438 439 return 0; 440 exit_free: 441 kfree(arr_phy); 442 kfree(arr_port); 443 return -1; 444 445 } 446 447 static void mvs_post_sas_ha_init(struct Scsi_Host *shost, 448 const struct mvs_chip_info *chip_info) 449 { 450 int can_queue, i = 0, j = 0; 451 struct mvs_info *mvi = NULL; 452 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 453 unsigned short nr_core = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 454 455 for (j = 0; j < nr_core; j++) { 456 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j]; 457 for (i = 0; i < chip_info->n_phy; i++) { 458 sha->sas_phy[j * chip_info->n_phy + i] = 459 &mvi->phy[i].sas_phy; 460 sha->sas_port[j * chip_info->n_phy + i] = 461 &mvi->port[i].sas_port; 462 } 463 } 464 465 sha->sas_ha_name = DRV_NAME; 466 sha->dev = mvi->dev; 467 sha->lldd_module = THIS_MODULE; 468 sha->sas_addr = &mvi->sas_addr[0]; 469 470 sha->num_phys = nr_core * chip_info->n_phy; 471 472 if (mvi->flags & MVF_FLAG_SOC) 473 can_queue = MVS_SOC_CAN_QUEUE; 474 else 475 can_queue = MVS_CHIP_SLOT_SZ; 476 477 shost->sg_tablesize = min_t(u16, SG_ALL, MVS_MAX_SG); 478 shost->can_queue = can_queue; 479 mvi->shost->cmd_per_lun = MVS_QUEUE_SIZE; 480 sha->core.shost = mvi->shost; 481 } 482 483 static void mvs_init_sas_add(struct mvs_info *mvi) 484 { 485 u8 i; 486 for (i = 0; i < mvi->chip->n_phy; i++) { 487 mvi->phy[i].dev_sas_addr = 0x5005043011ab0000ULL; 488 mvi->phy[i].dev_sas_addr = 489 cpu_to_be64((u64)(*(u64 *)&mvi->phy[i].dev_sas_addr)); 490 } 491 492 memcpy(mvi->sas_addr, &mvi->phy[0].dev_sas_addr, SAS_ADDR_SIZE); 493 } 494 495 static int mvs_pci_init(struct pci_dev *pdev, const struct pci_device_id *ent) 496 { 497 unsigned int rc, nhost = 0; 498 struct mvs_info *mvi; 499 struct mvs_prv_info *mpi; 500 irq_handler_t irq_handler = mvs_interrupt; 501 struct Scsi_Host *shost = NULL; 502 const struct mvs_chip_info *chip; 503 504 dev_printk(KERN_INFO, &pdev->dev, 505 "mvsas: driver version %s\n", DRV_VERSION); 506 rc = pci_enable_device(pdev); 507 if (rc) 508 goto err_out_enable; 509 510 pci_set_master(pdev); 511 512 rc = pci_request_regions(pdev, DRV_NAME); 513 if (rc) 514 goto err_out_disable; 515 516 rc = pci_go_64(pdev); 517 if (rc) 518 goto err_out_regions; 519 520 shost = scsi_host_alloc(&mvs_sht, sizeof(void *)); 521 if (!shost) { 522 rc = -ENOMEM; 523 goto err_out_regions; 524 } 525 526 chip = &mvs_chips[ent->driver_data]; 527 SHOST_TO_SAS_HA(shost) = 528 kcalloc(1, sizeof(struct sas_ha_struct), GFP_KERNEL); 529 if (!SHOST_TO_SAS_HA(shost)) { 530 scsi_host_put(shost); 531 rc = -ENOMEM; 532 goto err_out_regions; 533 } 534 535 rc = mvs_prep_sas_ha_init(shost, chip); 536 if (rc) { 537 scsi_host_put(shost); 538 rc = -ENOMEM; 539 goto err_out_regions; 540 } 541 542 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost)); 543 544 do { 545 mvi = mvs_pci_alloc(pdev, ent, shost, nhost); 546 if (!mvi) { 547 rc = -ENOMEM; 548 goto err_out_regions; 549 } 550 551 memset(&mvi->hba_info_param, 0xFF, 552 sizeof(struct hba_info_page)); 553 554 mvs_init_sas_add(mvi); 555 556 mvi->instance = nhost; 557 rc = MVS_CHIP_DISP->chip_init(mvi); 558 if (rc) { 559 mvs_free(mvi); 560 goto err_out_regions; 561 } 562 nhost++; 563 } while (nhost < chip->n_host); 564 mpi = (struct mvs_prv_info *)(SHOST_TO_SAS_HA(shost)->lldd_ha); 565 #ifdef CONFIG_SCSI_MVSAS_TASKLET 566 tasklet_init(&(mpi->mv_tasklet), mvs_tasklet, 567 (unsigned long)SHOST_TO_SAS_HA(shost)); 568 #endif 569 570 mvs_post_sas_ha_init(shost, chip); 571 572 rc = scsi_add_host(shost, &pdev->dev); 573 if (rc) 574 goto err_out_shost; 575 576 rc = sas_register_ha(SHOST_TO_SAS_HA(shost)); 577 if (rc) 578 goto err_out_shost; 579 rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED, 580 DRV_NAME, SHOST_TO_SAS_HA(shost)); 581 if (rc) 582 goto err_not_sas; 583 584 MVS_CHIP_DISP->interrupt_enable(mvi); 585 586 scsi_scan_host(mvi->shost); 587 588 return 0; 589 590 err_not_sas: 591 sas_unregister_ha(SHOST_TO_SAS_HA(shost)); 592 err_out_shost: 593 scsi_remove_host(mvi->shost); 594 err_out_regions: 595 pci_release_regions(pdev); 596 err_out_disable: 597 pci_disable_device(pdev); 598 err_out_enable: 599 return rc; 600 } 601 602 static void mvs_pci_remove(struct pci_dev *pdev) 603 { 604 unsigned short core_nr, i = 0; 605 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 606 struct mvs_info *mvi = NULL; 607 608 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 609 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; 610 611 #ifdef CONFIG_SCSI_MVSAS_TASKLET 612 tasklet_kill(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet); 613 #endif 614 615 sas_unregister_ha(sha); 616 sas_remove_host(mvi->shost); 617 618 MVS_CHIP_DISP->interrupt_disable(mvi); 619 free_irq(mvi->pdev->irq, sha); 620 for (i = 0; i < core_nr; i++) { 621 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; 622 mvs_free(mvi); 623 } 624 kfree(sha->sas_phy); 625 kfree(sha->sas_port); 626 kfree(sha); 627 pci_release_regions(pdev); 628 pci_disable_device(pdev); 629 return; 630 } 631 632 static struct pci_device_id mvs_pci_table[] = { 633 { PCI_VDEVICE(MARVELL, 0x6320), chip_6320 }, 634 { PCI_VDEVICE(MARVELL, 0x6340), chip_6440 }, 635 { 636 .vendor = PCI_VENDOR_ID_MARVELL, 637 .device = 0x6440, 638 .subvendor = PCI_ANY_ID, 639 .subdevice = 0x6480, 640 .class = 0, 641 .class_mask = 0, 642 .driver_data = chip_6485, 643 }, 644 { PCI_VDEVICE(MARVELL, 0x6440), chip_6440 }, 645 { PCI_VDEVICE(MARVELL, 0x6485), chip_6485 }, 646 { PCI_VDEVICE(MARVELL, 0x9480), chip_9480 }, 647 { PCI_VDEVICE(MARVELL, 0x9180), chip_9180 }, 648 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1300), chip_1300 }, 649 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1320), chip_1320 }, 650 { PCI_VDEVICE(ADAPTEC2, 0x0450), chip_6440 }, 651 { PCI_VDEVICE(TTI, 0x2710), chip_9480 }, 652 { PCI_VDEVICE(TTI, 0x2720), chip_9480 }, 653 { PCI_VDEVICE(TTI, 0x2721), chip_9480 }, 654 { PCI_VDEVICE(TTI, 0x2722), chip_9480 }, 655 { PCI_VDEVICE(TTI, 0x2740), chip_9480 }, 656 { PCI_VDEVICE(TTI, 0x2744), chip_9480 }, 657 { PCI_VDEVICE(TTI, 0x2760), chip_9480 }, 658 { 659 .vendor = PCI_VENDOR_ID_MARVELL_EXT, 660 .device = 0x9480, 661 .subvendor = PCI_ANY_ID, 662 .subdevice = 0x9480, 663 .class = 0, 664 .class_mask = 0, 665 .driver_data = chip_9480, 666 }, 667 { 668 .vendor = PCI_VENDOR_ID_MARVELL_EXT, 669 .device = 0x9445, 670 .subvendor = PCI_ANY_ID, 671 .subdevice = 0x9480, 672 .class = 0, 673 .class_mask = 0, 674 .driver_data = chip_9445, 675 }, 676 { PCI_VDEVICE(MARVELL_EXT, 0x9485), chip_9485 }, /* Marvell 9480/9485 (any vendor/model) */ 677 { PCI_VDEVICE(OCZ, 0x1021), chip_9485}, /* OCZ RevoDrive3 */ 678 { PCI_VDEVICE(OCZ, 0x1022), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 679 { PCI_VDEVICE(OCZ, 0x1040), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 680 { PCI_VDEVICE(OCZ, 0x1041), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 681 { PCI_VDEVICE(OCZ, 0x1042), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 682 { PCI_VDEVICE(OCZ, 0x1043), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 683 { PCI_VDEVICE(OCZ, 0x1044), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 684 { PCI_VDEVICE(OCZ, 0x1080), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 685 { PCI_VDEVICE(OCZ, 0x1083), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 686 { PCI_VDEVICE(OCZ, 0x1084), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 687 688 { } /* terminate list */ 689 }; 690 691 static struct pci_driver mvs_pci_driver = { 692 .name = DRV_NAME, 693 .id_table = mvs_pci_table, 694 .probe = mvs_pci_init, 695 .remove = mvs_pci_remove, 696 }; 697 698 static ssize_t 699 mvs_show_driver_version(struct device *cdev, 700 struct device_attribute *attr, char *buffer) 701 { 702 return snprintf(buffer, PAGE_SIZE, "%s\n", DRV_VERSION); 703 } 704 705 static DEVICE_ATTR(driver_version, 706 S_IRUGO, 707 mvs_show_driver_version, 708 NULL); 709 710 static ssize_t 711 mvs_store_interrupt_coalescing(struct device *cdev, 712 struct device_attribute *attr, 713 const char *buffer, size_t size) 714 { 715 unsigned int val = 0; 716 struct mvs_info *mvi = NULL; 717 struct Scsi_Host *shost = class_to_shost(cdev); 718 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 719 u8 i, core_nr; 720 if (buffer == NULL) 721 return size; 722 723 if (sscanf(buffer, "%u", &val) != 1) 724 return -EINVAL; 725 726 if (val >= 0x10000) { 727 mv_dprintk("interrupt coalescing timer %d us is" 728 "too long\n", val); 729 return strlen(buffer); 730 } 731 732 interrupt_coalescing = val; 733 734 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 735 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; 736 737 if (unlikely(!mvi)) 738 return -EINVAL; 739 740 for (i = 0; i < core_nr; i++) { 741 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; 742 if (MVS_CHIP_DISP->tune_interrupt) 743 MVS_CHIP_DISP->tune_interrupt(mvi, 744 interrupt_coalescing); 745 } 746 mv_dprintk("set interrupt coalescing time to %d us\n", 747 interrupt_coalescing); 748 return strlen(buffer); 749 } 750 751 static ssize_t mvs_show_interrupt_coalescing(struct device *cdev, 752 struct device_attribute *attr, char *buffer) 753 { 754 return snprintf(buffer, PAGE_SIZE, "%d\n", interrupt_coalescing); 755 } 756 757 static DEVICE_ATTR(interrupt_coalescing, 758 S_IRUGO|S_IWUSR, 759 mvs_show_interrupt_coalescing, 760 mvs_store_interrupt_coalescing); 761 762 /* task handler */ 763 struct task_struct *mvs_th; 764 static int __init mvs_init(void) 765 { 766 int rc; 767 mvs_stt = sas_domain_attach_transport(&mvs_transport_ops); 768 if (!mvs_stt) 769 return -ENOMEM; 770 771 rc = pci_register_driver(&mvs_pci_driver); 772 if (rc) 773 goto err_out; 774 775 return 0; 776 777 err_out: 778 sas_release_transport(mvs_stt); 779 return rc; 780 } 781 782 static void __exit mvs_exit(void) 783 { 784 pci_unregister_driver(&mvs_pci_driver); 785 sas_release_transport(mvs_stt); 786 } 787 788 struct device_attribute *mvst_host_attrs[] = { 789 &dev_attr_driver_version, 790 &dev_attr_interrupt_coalescing, 791 NULL, 792 }; 793 794 module_init(mvs_init); 795 module_exit(mvs_exit); 796 797 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>"); 798 MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver"); 799 MODULE_VERSION(DRV_VERSION); 800 MODULE_LICENSE("GPL"); 801 #ifdef CONFIG_PCI 802 MODULE_DEVICE_TABLE(pci, mvs_pci_table); 803 #endif 804