1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Marvell 88SE64xx/88SE94xx const head file 4 * 5 * Copyright 2007 Red Hat, Inc. 6 * Copyright 2008 Marvell. <kewei@marvell.com> 7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com> 8 */ 9 10 #ifndef _MV_DEFS_H_ 11 #define _MV_DEFS_H_ 12 13 #define PCI_DEVICE_ID_ARECA_1300 0x1300 14 #define PCI_DEVICE_ID_ARECA_1320 0x1320 15 16 enum chip_flavors { 17 chip_6320, 18 chip_6440, 19 chip_6485, 20 chip_9480, 21 chip_9180, 22 chip_9445, 23 chip_9485, 24 chip_1300, 25 chip_1320 26 }; 27 28 /* driver compile-time configuration */ 29 enum driver_configuration { 30 MVS_TX_RING_SZ = 1024, /* TX ring size (12-bit) */ 31 MVS_RX_RING_SZ = 1024, /* RX ring size (12-bit) */ 32 /* software requires power-of-2 33 ring size */ 34 MVS_SOC_SLOTS = 64, 35 MVS_SOC_TX_RING_SZ = MVS_SOC_SLOTS * 2, 36 MVS_SOC_RX_RING_SZ = MVS_SOC_SLOTS * 2, 37 38 MVS_SLOT_BUF_SZ = 8192, /* cmd tbl + IU + status + PRD */ 39 MVS_SSP_CMD_SZ = 64, /* SSP command table buffer size */ 40 MVS_ATA_CMD_SZ = 96, /* SATA command table buffer size */ 41 MVS_OAF_SZ = 64, /* Open address frame buffer size */ 42 MVS_QUEUE_SIZE = 64, /* Support Queue depth */ 43 MVS_SOC_CAN_QUEUE = MVS_SOC_SLOTS - 2, 44 }; 45 46 /* unchangeable hardware details */ 47 enum hardware_details { 48 MVS_MAX_PHYS = 8, /* max. possible phys */ 49 MVS_MAX_PORTS = 8, /* max. possible ports */ 50 MVS_SOC_PHYS = 4, /* soc phys */ 51 MVS_SOC_PORTS = 4, /* soc phys */ 52 MVS_MAX_DEVICES = 1024, /* max supported device */ 53 }; 54 55 /* peripheral registers (BAR2) */ 56 enum peripheral_registers { 57 SPI_CTL = 0x10, /* EEPROM control */ 58 SPI_CMD = 0x14, /* EEPROM command */ 59 SPI_DATA = 0x18, /* EEPROM data */ 60 }; 61 62 enum peripheral_register_bits { 63 TWSI_RDY = (1U << 7), /* EEPROM interface ready */ 64 TWSI_RD = (1U << 4), /* EEPROM read access */ 65 66 SPI_ADDR_MASK = 0x3ffff, /* bits 17:0 */ 67 }; 68 69 enum hw_register_bits { 70 /* MVS_GBL_CTL */ 71 INT_EN = (1U << 1), /* Global int enable */ 72 HBA_RST = (1U << 0), /* HBA reset */ 73 74 /* MVS_GBL_INT_STAT */ 75 INT_XOR = (1U << 4), /* XOR engine event */ 76 INT_SAS_SATA = (1U << 0), /* SAS/SATA event */ 77 78 /* MVS_GBL_PORT_TYPE */ /* shl for ports 1-3 */ 79 SATA_TARGET = (1U << 16), /* port0 SATA target enable */ 80 MODE_AUTO_DET_PORT7 = (1U << 15), /* port0 SAS/SATA autodetect */ 81 MODE_AUTO_DET_PORT6 = (1U << 14), 82 MODE_AUTO_DET_PORT5 = (1U << 13), 83 MODE_AUTO_DET_PORT4 = (1U << 12), 84 MODE_AUTO_DET_PORT3 = (1U << 11), 85 MODE_AUTO_DET_PORT2 = (1U << 10), 86 MODE_AUTO_DET_PORT1 = (1U << 9), 87 MODE_AUTO_DET_PORT0 = (1U << 8), 88 MODE_AUTO_DET_EN = MODE_AUTO_DET_PORT0 | MODE_AUTO_DET_PORT1 | 89 MODE_AUTO_DET_PORT2 | MODE_AUTO_DET_PORT3 | 90 MODE_AUTO_DET_PORT4 | MODE_AUTO_DET_PORT5 | 91 MODE_AUTO_DET_PORT6 | MODE_AUTO_DET_PORT7, 92 MODE_SAS_PORT7_MASK = (1U << 7), /* port0 SAS(1), SATA(0) mode */ 93 MODE_SAS_PORT6_MASK = (1U << 6), 94 MODE_SAS_PORT5_MASK = (1U << 5), 95 MODE_SAS_PORT4_MASK = (1U << 4), 96 MODE_SAS_PORT3_MASK = (1U << 3), 97 MODE_SAS_PORT2_MASK = (1U << 2), 98 MODE_SAS_PORT1_MASK = (1U << 1), 99 MODE_SAS_PORT0_MASK = (1U << 0), 100 MODE_SAS_SATA = MODE_SAS_PORT0_MASK | MODE_SAS_PORT1_MASK | 101 MODE_SAS_PORT2_MASK | MODE_SAS_PORT3_MASK | 102 MODE_SAS_PORT4_MASK | MODE_SAS_PORT5_MASK | 103 MODE_SAS_PORT6_MASK | MODE_SAS_PORT7_MASK, 104 105 /* SAS_MODE value may be 106 * dictated (in hw) by values 107 * of SATA_TARGET & AUTO_DET 108 */ 109 110 /* MVS_TX_CFG */ 111 TX_EN = (1U << 16), /* Enable TX */ 112 TX_RING_SZ_MASK = 0xfff, /* TX ring size, bits 11:0 */ 113 114 /* MVS_RX_CFG */ 115 RX_EN = (1U << 16), /* Enable RX */ 116 RX_RING_SZ_MASK = 0xfff, /* RX ring size, bits 11:0 */ 117 118 /* MVS_INT_COAL */ 119 COAL_EN = (1U << 16), /* Enable int coalescing */ 120 121 /* MVS_INT_STAT, MVS_INT_MASK */ 122 CINT_I2C = (1U << 31), /* I2C event */ 123 CINT_SW0 = (1U << 30), /* software event 0 */ 124 CINT_SW1 = (1U << 29), /* software event 1 */ 125 CINT_PRD_BC = (1U << 28), /* PRD BC err for read cmd */ 126 CINT_DMA_PCIE = (1U << 27), /* DMA to PCIE timeout */ 127 CINT_MEM = (1U << 26), /* int mem parity err */ 128 CINT_I2C_SLAVE = (1U << 25), /* slave I2C event */ 129 CINT_NON_SPEC_NCQ_ERROR = (1U << 25), /* Non specific NCQ error */ 130 CINT_SRS = (1U << 3), /* SRS event */ 131 CINT_CI_STOP = (1U << 1), /* cmd issue stopped */ 132 CINT_DONE = (1U << 0), /* cmd completion */ 133 134 /* shl for ports 1-3 */ 135 CINT_PORT_STOPPED = (1U << 16), /* port0 stopped */ 136 CINT_PORT = (1U << 8), /* port0 event */ 137 CINT_PORT_MASK_OFFSET = 8, 138 CINT_PORT_MASK = (0xFF << CINT_PORT_MASK_OFFSET), 139 CINT_PHY_MASK_OFFSET = 4, 140 CINT_PHY_MASK = (0x0F << CINT_PHY_MASK_OFFSET), 141 142 /* TX (delivery) ring bits */ 143 TXQ_CMD_SHIFT = 29, 144 TXQ_CMD_SSP = 1, /* SSP protocol */ 145 TXQ_CMD_SMP = 2, /* SMP protocol */ 146 TXQ_CMD_STP = 3, /* STP/SATA protocol */ 147 TXQ_CMD_SSP_FREE_LIST = 4, /* add to SSP target free list */ 148 TXQ_CMD_SLOT_RESET = 7, /* reset command slot */ 149 TXQ_MODE_I = (1U << 28), /* mode: 0=target,1=initiator */ 150 TXQ_MODE_TARGET = 0, 151 TXQ_MODE_INITIATOR = 1, 152 TXQ_PRIO_HI = (1U << 27), /* priority: 0=normal, 1=high */ 153 TXQ_PRI_NORMAL = 0, 154 TXQ_PRI_HIGH = 1, 155 TXQ_SRS_SHIFT = 20, /* SATA register set */ 156 TXQ_SRS_MASK = 0x7f, 157 TXQ_PHY_SHIFT = 12, /* PHY bitmap */ 158 TXQ_PHY_MASK = 0xff, 159 TXQ_SLOT_MASK = 0xfff, /* slot number */ 160 161 /* RX (completion) ring bits */ 162 RXQ_GOOD = (1U << 23), /* Response good */ 163 RXQ_SLOT_RESET = (1U << 21), /* Slot reset complete */ 164 RXQ_CMD_RX = (1U << 20), /* target cmd received */ 165 RXQ_ATTN = (1U << 19), /* attention */ 166 RXQ_RSP = (1U << 18), /* response frame xfer'd */ 167 RXQ_ERR = (1U << 17), /* err info rec xfer'd */ 168 RXQ_DONE = (1U << 16), /* cmd complete */ 169 RXQ_SLOT_MASK = 0xfff, /* slot number */ 170 171 /* mvs_cmd_hdr bits */ 172 MCH_PRD_LEN_SHIFT = 16, /* 16-bit PRD table len */ 173 MCH_SSP_FR_TYPE_SHIFT = 13, /* SSP frame type */ 174 175 /* SSP initiator only */ 176 MCH_SSP_FR_CMD = 0x0, /* COMMAND frame */ 177 178 /* SSP initiator or target */ 179 MCH_SSP_FR_TASK = 0x1, /* TASK frame */ 180 181 /* SSP target only */ 182 MCH_SSP_FR_XFER_RDY = 0x4, /* XFER_RDY frame */ 183 MCH_SSP_FR_RESP = 0x5, /* RESPONSE frame */ 184 MCH_SSP_FR_READ = 0x6, /* Read DATA frame(s) */ 185 MCH_SSP_FR_READ_RESP = 0x7, /* ditto, plus RESPONSE */ 186 187 MCH_SSP_MODE_PASSTHRU = 1, 188 MCH_SSP_MODE_NORMAL = 0, 189 MCH_PASSTHRU = (1U << 12), /* pass-through (SSP) */ 190 MCH_FBURST = (1U << 11), /* first burst (SSP) */ 191 MCH_CHK_LEN = (1U << 10), /* chk xfer len (SSP) */ 192 MCH_RETRY = (1U << 9), /* tport layer retry (SSP) */ 193 MCH_PROTECTION = (1U << 8), /* protection info rec (SSP) */ 194 MCH_RESET = (1U << 7), /* Reset (STP/SATA) */ 195 MCH_FPDMA = (1U << 6), /* First party DMA (STP/SATA) */ 196 MCH_ATAPI = (1U << 5), /* ATAPI (STP/SATA) */ 197 MCH_BIST = (1U << 4), /* BIST activate (STP/SATA) */ 198 MCH_PMP_MASK = 0xf, /* PMP from cmd FIS (STP/SATA)*/ 199 200 CCTL_RST = (1U << 5), /* port logic reset */ 201 202 /* 0(LSB first), 1(MSB first) */ 203 CCTL_ENDIAN_DATA = (1U << 3), /* PRD data */ 204 CCTL_ENDIAN_RSP = (1U << 2), /* response frame */ 205 CCTL_ENDIAN_OPEN = (1U << 1), /* open address frame */ 206 CCTL_ENDIAN_CMD = (1U << 0), /* command table */ 207 208 /* MVS_Px_SER_CTLSTAT (per-phy control) */ 209 PHY_SSP_RST = (1U << 3), /* reset SSP link layer */ 210 PHY_BCAST_CHG = (1U << 2), /* broadcast(change) notif */ 211 PHY_RST_HARD = (1U << 1), /* hard reset + phy reset */ 212 PHY_RST = (1U << 0), /* phy reset */ 213 PHY_READY_MASK = (1U << 20), 214 215 /* MVS_Px_INT_STAT, MVS_Px_INT_MASK (per-phy events) */ 216 PHYEV_DEC_ERR = (1U << 24), /* Phy Decoding Error */ 217 PHYEV_DCDR_ERR = (1U << 23), /* STP Deocder Error */ 218 PHYEV_CRC_ERR = (1U << 22), /* STP CRC Error */ 219 PHYEV_UNASSOC_FIS = (1U << 19), /* unassociated FIS rx'd */ 220 PHYEV_AN = (1U << 18), /* SATA async notification */ 221 PHYEV_BIST_ACT = (1U << 17), /* BIST activate FIS */ 222 PHYEV_SIG_FIS = (1U << 16), /* signature FIS */ 223 PHYEV_POOF = (1U << 12), /* phy ready from 1 -> 0 */ 224 PHYEV_IU_BIG = (1U << 11), /* IU too long err */ 225 PHYEV_IU_SMALL = (1U << 10), /* IU too short err */ 226 PHYEV_UNK_TAG = (1U << 9), /* unknown tag */ 227 PHYEV_BROAD_CH = (1U << 8), /* broadcast(CHANGE) */ 228 PHYEV_COMWAKE = (1U << 7), /* COMWAKE rx'd */ 229 PHYEV_PORT_SEL = (1U << 6), /* port selector present */ 230 PHYEV_HARD_RST = (1U << 5), /* hard reset rx'd */ 231 PHYEV_ID_TMOUT = (1U << 4), /* identify timeout */ 232 PHYEV_ID_FAIL = (1U << 3), /* identify failed */ 233 PHYEV_ID_DONE = (1U << 2), /* identify done */ 234 PHYEV_HARD_RST_DONE = (1U << 1), /* hard reset done */ 235 PHYEV_RDY_CH = (1U << 0), /* phy ready changed state */ 236 237 /* MVS_PCS */ 238 PCS_EN_SATA_REG_SHIFT = (16), /* Enable SATA Register Set */ 239 PCS_EN_PORT_XMT_SHIFT = (12), /* Enable Port Transmit */ 240 PCS_EN_PORT_XMT_SHIFT2 = (8), /* For 6485 */ 241 PCS_SATA_RETRY = (1U << 8), /* retry ctl FIS on R_ERR */ 242 PCS_RSP_RX_EN = (1U << 7), /* raw response rx */ 243 PCS_SATA_RETRY_2 = (1U << 6), /* For 9180 */ 244 PCS_SELF_CLEAR = (1U << 5), /* self-clearing int mode */ 245 PCS_FIS_RX_EN = (1U << 4), /* FIS rx enable */ 246 PCS_CMD_STOP_ERR = (1U << 3), /* cmd stop-on-err enable */ 247 PCS_CMD_RST = (1U << 1), /* reset cmd issue */ 248 PCS_CMD_EN = (1U << 0), /* enable cmd issue */ 249 250 /* Port n Attached Device Info */ 251 PORT_DEV_SSP_TRGT = (1U << 19), 252 PORT_DEV_SMP_TRGT = (1U << 18), 253 PORT_DEV_STP_TRGT = (1U << 17), 254 PORT_DEV_SSP_INIT = (1U << 11), 255 PORT_DEV_SMP_INIT = (1U << 10), 256 PORT_DEV_STP_INIT = (1U << 9), 257 PORT_PHY_ID_MASK = (0xFFU << 24), 258 PORT_SSP_TRGT_MASK = (0x1U << 19), 259 PORT_SSP_INIT_MASK = (0x1U << 11), 260 PORT_DEV_TRGT_MASK = (0x7U << 17), 261 PORT_DEV_INIT_MASK = (0x7U << 9), 262 PORT_DEV_TYPE_MASK = (0x7U << 0), 263 264 /* Port n PHY Status */ 265 PHY_RDY = (1U << 2), 266 PHY_DW_SYNC = (1U << 1), 267 PHY_OOB_DTCTD = (1U << 0), 268 269 /* VSR */ 270 /* PHYMODE 6 (CDB) */ 271 PHY_MODE6_LATECLK = (1U << 29), /* Lock Clock */ 272 PHY_MODE6_DTL_SPEED = (1U << 27), /* Digital Loop Speed */ 273 PHY_MODE6_FC_ORDER = (1U << 26), /* Fibre Channel Mode Order*/ 274 PHY_MODE6_MUCNT_EN = (1U << 24), /* u Count Enable */ 275 PHY_MODE6_SEL_MUCNT_LEN = (1U << 22), /* Training Length Select */ 276 PHY_MODE6_SELMUPI = (1U << 20), /* Phase Multi Select (init) */ 277 PHY_MODE6_SELMUPF = (1U << 18), /* Phase Multi Select (final) */ 278 PHY_MODE6_SELMUFF = (1U << 16), /* Freq Loop Multi Sel(final) */ 279 PHY_MODE6_SELMUFI = (1U << 14), /* Freq Loop Multi Sel(init) */ 280 PHY_MODE6_FREEZE_LOOP = (1U << 12), /* Freeze Rx CDR Loop */ 281 PHY_MODE6_INT_RXFOFFS = (1U << 3), /* Rx CDR Freq Loop Enable */ 282 PHY_MODE6_FRC_RXFOFFS = (1U << 2), /* Initial Rx CDR Offset */ 283 PHY_MODE6_STAU_0D8 = (1U << 1), /* Rx CDR Freq Loop Saturate */ 284 PHY_MODE6_RXSAT_DIS = (1U << 0), /* Saturate Ctl */ 285 }; 286 287 /* SAS/SATA configuration port registers, aka phy registers */ 288 enum sas_sata_config_port_regs { 289 PHYR_IDENTIFY = 0x00, /* info for IDENTIFY frame */ 290 PHYR_ADDR_LO = 0x04, /* my SAS address (low) */ 291 PHYR_ADDR_HI = 0x08, /* my SAS address (high) */ 292 PHYR_ATT_DEV_INFO = 0x0C, /* attached device info */ 293 PHYR_ATT_ADDR_LO = 0x10, /* attached dev SAS addr (low) */ 294 PHYR_ATT_ADDR_HI = 0x14, /* attached dev SAS addr (high) */ 295 PHYR_SATA_CTL = 0x18, /* SATA control */ 296 PHYR_PHY_STAT = 0x1C, /* PHY status */ 297 PHYR_SATA_SIG0 = 0x20, /*port SATA signature FIS(Byte 0-3) */ 298 PHYR_SATA_SIG1 = 0x24, /*port SATA signature FIS(Byte 4-7) */ 299 PHYR_SATA_SIG2 = 0x28, /*port SATA signature FIS(Byte 8-11) */ 300 PHYR_SATA_SIG3 = 0x2c, /*port SATA signature FIS(Byte 12-15) */ 301 PHYR_R_ERR_COUNT = 0x30, /* port R_ERR count register */ 302 PHYR_CRC_ERR_COUNT = 0x34, /* port CRC error count register */ 303 PHYR_WIDE_PORT = 0x38, /* wide port participating */ 304 PHYR_CURRENT0 = 0x80, /* current connection info 0 */ 305 PHYR_CURRENT1 = 0x84, /* current connection info 1 */ 306 PHYR_CURRENT2 = 0x88, /* current connection info 2 */ 307 CONFIG_ID_FRAME0 = 0x100, /* Port device ID frame register 0 */ 308 CONFIG_ID_FRAME1 = 0x104, /* Port device ID frame register 1 */ 309 CONFIG_ID_FRAME2 = 0x108, /* Port device ID frame register 2 */ 310 CONFIG_ID_FRAME3 = 0x10c, /* Port device ID frame register 3 */ 311 CONFIG_ID_FRAME4 = 0x110, /* Port device ID frame register 4 */ 312 CONFIG_ID_FRAME5 = 0x114, /* Port device ID frame register 5 */ 313 CONFIG_ID_FRAME6 = 0x118, /* Port device ID frame register 6 */ 314 CONFIG_ATT_ID_FRAME0 = 0x11c, /* attached ID frame register 0 */ 315 CONFIG_ATT_ID_FRAME1 = 0x120, /* attached ID frame register 1 */ 316 CONFIG_ATT_ID_FRAME2 = 0x124, /* attached ID frame register 2 */ 317 CONFIG_ATT_ID_FRAME3 = 0x128, /* attached ID frame register 3 */ 318 CONFIG_ATT_ID_FRAME4 = 0x12c, /* attached ID frame register 4 */ 319 CONFIG_ATT_ID_FRAME5 = 0x130, /* attached ID frame register 5 */ 320 CONFIG_ATT_ID_FRAME6 = 0x134, /* attached ID frame register 6 */ 321 }; 322 323 enum sas_cmd_port_registers { 324 CMD_CMRST_OOB_DET = 0x100, /* COMRESET OOB detect register */ 325 CMD_CMWK_OOB_DET = 0x104, /* COMWAKE OOB detect register */ 326 CMD_CMSAS_OOB_DET = 0x108, /* COMSAS OOB detect register */ 327 CMD_BRST_OOB_DET = 0x10c, /* burst OOB detect register */ 328 CMD_OOB_SPACE = 0x110, /* OOB space control register */ 329 CMD_OOB_BURST = 0x114, /* OOB burst control register */ 330 CMD_PHY_TIMER = 0x118, /* PHY timer control register */ 331 CMD_PHY_CONFIG0 = 0x11c, /* PHY config register 0 */ 332 CMD_PHY_CONFIG1 = 0x120, /* PHY config register 1 */ 333 CMD_SAS_CTL0 = 0x124, /* SAS control register 0 */ 334 CMD_SAS_CTL1 = 0x128, /* SAS control register 1 */ 335 CMD_SAS_CTL2 = 0x12c, /* SAS control register 2 */ 336 CMD_SAS_CTL3 = 0x130, /* SAS control register 3 */ 337 CMD_ID_TEST = 0x134, /* ID test register */ 338 CMD_PL_TIMER = 0x138, /* PL timer register */ 339 CMD_WD_TIMER = 0x13c, /* WD timer register */ 340 CMD_PORT_SEL_COUNT = 0x140, /* port selector count register */ 341 CMD_APP_MEM_CTL = 0x144, /* Application Memory Control */ 342 CMD_XOR_MEM_CTL = 0x148, /* XOR Block Memory Control */ 343 CMD_DMA_MEM_CTL = 0x14c, /* DMA Block Memory Control */ 344 CMD_PORT_MEM_CTL0 = 0x150, /* Port Memory Control 0 */ 345 CMD_PORT_MEM_CTL1 = 0x154, /* Port Memory Control 1 */ 346 CMD_SATA_PORT_MEM_CTL0 = 0x158, /* SATA Port Memory Control 0 */ 347 CMD_SATA_PORT_MEM_CTL1 = 0x15c, /* SATA Port Memory Control 1 */ 348 CMD_XOR_MEM_BIST_CTL = 0x160, /* XOR Memory BIST Control */ 349 CMD_XOR_MEM_BIST_STAT = 0x164, /* XOR Memroy BIST Status */ 350 CMD_DMA_MEM_BIST_CTL = 0x168, /* DMA Memory BIST Control */ 351 CMD_DMA_MEM_BIST_STAT = 0x16c, /* DMA Memory BIST Status */ 352 CMD_PORT_MEM_BIST_CTL = 0x170, /* Port Memory BIST Control */ 353 CMD_PORT_MEM_BIST_STAT0 = 0x174, /* Port Memory BIST Status 0 */ 354 CMD_PORT_MEM_BIST_STAT1 = 0x178, /* Port Memory BIST Status 1 */ 355 CMD_STP_MEM_BIST_CTL = 0x17c, /* STP Memory BIST Control */ 356 CMD_STP_MEM_BIST_STAT0 = 0x180, /* STP Memory BIST Status 0 */ 357 CMD_STP_MEM_BIST_STAT1 = 0x184, /* STP Memory BIST Status 1 */ 358 CMD_RESET_COUNT = 0x188, /* Reset Count */ 359 CMD_MONTR_DATA_SEL = 0x18C, /* Monitor Data/Select */ 360 CMD_PLL_PHY_CONFIG = 0x190, /* PLL/PHY Configuration */ 361 CMD_PHY_CTL = 0x194, /* PHY Control and Status */ 362 CMD_PHY_TEST_COUNT0 = 0x198, /* Phy Test Count 0 */ 363 CMD_PHY_TEST_COUNT1 = 0x19C, /* Phy Test Count 1 */ 364 CMD_PHY_TEST_COUNT2 = 0x1A0, /* Phy Test Count 2 */ 365 CMD_APP_ERR_CONFIG = 0x1A4, /* Application Error Configuration */ 366 CMD_PND_FIFO_CTL0 = 0x1A8, /* Pending FIFO Control 0 */ 367 CMD_HOST_CTL = 0x1AC, /* Host Control Status */ 368 CMD_HOST_WR_DATA = 0x1B0, /* Host Write Data */ 369 CMD_HOST_RD_DATA = 0x1B4, /* Host Read Data */ 370 CMD_PHY_MODE_21 = 0x1B8, /* Phy Mode 21 */ 371 CMD_SL_MODE0 = 0x1BC, /* SL Mode 0 */ 372 CMD_SL_MODE1 = 0x1C0, /* SL Mode 1 */ 373 CMD_PND_FIFO_CTL1 = 0x1C4, /* Pending FIFO Control 1 */ 374 CMD_PORT_LAYER_TIMER1 = 0x1E0, /* Port Layer Timer 1 */ 375 CMD_LINK_TIMER = 0x1E4, /* Link Timer */ 376 }; 377 378 enum mvs_info_flags { 379 MVF_PHY_PWR_FIX = (1U << 1), /* bug workaround */ 380 MVF_FLAG_SOC = (1U << 2), /* SoC integrated controllers */ 381 }; 382 383 enum mvs_event_flags { 384 PHY_PLUG_EVENT = (3U), 385 PHY_PLUG_IN = (1U << 0), /* phy plug in */ 386 PHY_PLUG_OUT = (1U << 1), /* phy plug out */ 387 EXP_BRCT_CHG = (1U << 2), /* broadcast change */ 388 }; 389 390 enum mvs_port_type { 391 PORT_TGT_MASK = (1U << 5), 392 PORT_INIT_PORT = (1U << 4), 393 PORT_TGT_PORT = (1U << 3), 394 PORT_INIT_TGT_PORT = (PORT_INIT_PORT | PORT_TGT_PORT), 395 PORT_TYPE_SAS = (1U << 1), 396 PORT_TYPE_SATA = (1U << 0), 397 }; 398 399 /* Command Table Format */ 400 enum ct_format { 401 /* SSP */ 402 SSP_F_H = 0x00, 403 SSP_F_IU = 0x18, 404 SSP_F_MAX = 0x4D, 405 /* STP */ 406 STP_CMD_FIS = 0x00, 407 STP_ATAPI_CMD = 0x40, 408 STP_F_MAX = 0x10, 409 /* SMP */ 410 SMP_F_T = 0x00, 411 SMP_F_DEP = 0x01, 412 SMP_F_MAX = 0x101, 413 }; 414 415 enum status_buffer { 416 SB_EIR_OFF = 0x00, /* Error Information Record */ 417 SB_RFB_OFF = 0x08, /* Response Frame Buffer */ 418 SB_RFB_MAX = 0x400, /* RFB size*/ 419 }; 420 421 enum error_info_rec { 422 CMD_ISS_STPD = (1U << 31), /* Cmd Issue Stopped */ 423 CMD_PI_ERR = (1U << 30), /* Protection info error. see flags2 */ 424 RSP_OVER = (1U << 29), /* rsp buffer overflow */ 425 RETRY_LIM = (1U << 28), /* FIS/frame retry limit exceeded */ 426 UNK_FIS = (1U << 27), /* unknown FIS */ 427 DMA_TERM = (1U << 26), /* DMA terminate primitive rx'd */ 428 SYNC_ERR = (1U << 25), /* SYNC rx'd during frame xmit */ 429 TFILE_ERR = (1U << 24), /* SATA taskfile Error bit set */ 430 R_ERR = (1U << 23), /* SATA returned R_ERR prim */ 431 RD_OFS = (1U << 20), /* Read DATA frame invalid offset */ 432 XFER_RDY_OFS = (1U << 19), /* XFER_RDY offset error */ 433 UNEXP_XFER_RDY = (1U << 18), /* unexpected XFER_RDY error */ 434 DATA_OVER_UNDER = (1U << 16), /* data overflow/underflow */ 435 INTERLOCK = (1U << 15), /* interlock error */ 436 NAK = (1U << 14), /* NAK rx'd */ 437 ACK_NAK_TO = (1U << 13), /* ACK/NAK timeout */ 438 CXN_CLOSED = (1U << 12), /* cxn closed w/out ack/nak */ 439 OPEN_TO = (1U << 11), /* I_T nexus lost, open cxn timeout */ 440 PATH_BLOCKED = (1U << 10), /* I_T nexus lost, pathway blocked */ 441 NO_DEST = (1U << 9), /* I_T nexus lost, no destination */ 442 STP_RES_BSY = (1U << 8), /* STP resources busy */ 443 BREAK = (1U << 7), /* break received */ 444 BAD_DEST = (1U << 6), /* bad destination */ 445 BAD_PROTO = (1U << 5), /* protocol not supported */ 446 BAD_RATE = (1U << 4), /* cxn rate not supported */ 447 WRONG_DEST = (1U << 3), /* wrong destination error */ 448 CREDIT_TO = (1U << 2), /* credit timeout */ 449 WDOG_TO = (1U << 1), /* watchdog timeout */ 450 BUF_PAR = (1U << 0), /* buffer parity error */ 451 }; 452 453 enum error_info_rec_2 { 454 SLOT_BSY_ERR = (1U << 31), /* Slot Busy Error */ 455 GRD_CHK_ERR = (1U << 14), /* Guard Check Error */ 456 APP_CHK_ERR = (1U << 13), /* Application Check error */ 457 REF_CHK_ERR = (1U << 12), /* Reference Check Error */ 458 USR_BLK_NM = (1U << 0), /* User Block Number */ 459 }; 460 461 enum pci_cfg_register_bits { 462 PCTL_PWR_OFF = (0xFU << 24), 463 PCTL_COM_ON = (0xFU << 20), 464 PCTL_LINK_RST = (0xFU << 16), 465 PCTL_LINK_OFFS = (16), 466 PCTL_PHY_DSBL = (0xFU << 12), 467 PCTL_PHY_DSBL_OFFS = (12), 468 PRD_REQ_SIZE = (0x4000), 469 PRD_REQ_MASK = (0x00007000), 470 PLS_NEG_LINK_WD = (0x3FU << 4), 471 PLS_NEG_LINK_WD_OFFS = 4, 472 PLS_LINK_SPD = (0x0FU << 0), 473 PLS_LINK_SPD_OFFS = 0, 474 }; 475 476 enum open_frame_protocol { 477 PROTOCOL_SMP = 0x0, 478 PROTOCOL_SSP = 0x1, 479 PROTOCOL_STP = 0x2, 480 }; 481 482 /* define for response frame datapres field */ 483 enum datapres_field { 484 NO_DATA = 0, 485 RESPONSE_DATA = 1, 486 SENSE_DATA = 2, 487 }; 488 489 #endif 490