1 /* 2 * Marvell 88SE94xx hardware specific 3 * 4 * Copyright 2007 Red Hat, Inc. 5 * Copyright 2008 Marvell. <kewei@marvell.com> 6 * 7 * This file is licensed under GPLv2. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; version 2 of the 12 * License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 22 * USA 23 */ 24 25 #include "mv_sas.h" 26 #include "mv_94xx.h" 27 #include "mv_chips.h" 28 29 static void mvs_94xx_detect_porttype(struct mvs_info *mvi, int i) 30 { 31 u32 reg; 32 struct mvs_phy *phy = &mvi->phy[i]; 33 u32 phy_status; 34 35 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE3); 36 reg = mvs_read_port_vsr_data(mvi, i); 37 phy_status = ((reg & 0x3f0000) >> 16) & 0xff; 38 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 39 switch (phy_status) { 40 case 0x10: 41 phy->phy_type |= PORT_TYPE_SAS; 42 break; 43 case 0x1d: 44 default: 45 phy->phy_type |= PORT_TYPE_SATA; 46 break; 47 } 48 } 49 50 static void __devinit mvs_94xx_enable_xmt(struct mvs_info *mvi, int phy_id) 51 { 52 void __iomem *regs = mvi->regs; 53 u32 tmp; 54 55 tmp = mr32(MVS_PCS); 56 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2); 57 mw32(MVS_PCS, tmp); 58 } 59 60 static void mvs_94xx_phy_reset(struct mvs_info *mvi, u32 phy_id, int hard) 61 { 62 u32 tmp; 63 64 tmp = mvs_read_port_irq_stat(mvi, phy_id); 65 tmp &= ~PHYEV_RDY_CH; 66 mvs_write_port_irq_stat(mvi, phy_id, tmp); 67 if (hard) { 68 tmp = mvs_read_phy_ctl(mvi, phy_id); 69 tmp |= PHY_RST_HARD; 70 mvs_write_phy_ctl(mvi, phy_id, tmp); 71 do { 72 tmp = mvs_read_phy_ctl(mvi, phy_id); 73 } while (tmp & PHY_RST_HARD); 74 } else { 75 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_STAT); 76 tmp = mvs_read_port_vsr_data(mvi, phy_id); 77 tmp |= PHY_RST; 78 mvs_write_port_vsr_data(mvi, phy_id, tmp); 79 } 80 } 81 82 static void mvs_94xx_phy_disable(struct mvs_info *mvi, u32 phy_id) 83 { 84 u32 tmp; 85 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2); 86 tmp = mvs_read_port_vsr_data(mvi, phy_id); 87 mvs_write_port_vsr_data(mvi, phy_id, tmp | 0x00800000); 88 } 89 90 static void mvs_94xx_phy_enable(struct mvs_info *mvi, u32 phy_id) 91 { 92 mvs_write_port_vsr_addr(mvi, phy_id, 0x1B4); 93 mvs_write_port_vsr_data(mvi, phy_id, 0x8300ffc1); 94 mvs_write_port_vsr_addr(mvi, phy_id, 0x104); 95 mvs_write_port_vsr_data(mvi, phy_id, 0x00018080); 96 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2); 97 mvs_write_port_vsr_data(mvi, phy_id, 0x00207fff); 98 } 99 100 static int __devinit mvs_94xx_init(struct mvs_info *mvi) 101 { 102 void __iomem *regs = mvi->regs; 103 int i; 104 u32 tmp, cctl; 105 106 mvs_show_pcie_usage(mvi); 107 if (mvi->flags & MVF_FLAG_SOC) { 108 tmp = mr32(MVS_PHY_CTL); 109 tmp &= ~PCTL_PWR_OFF; 110 tmp |= PCTL_PHY_DSBL; 111 mw32(MVS_PHY_CTL, tmp); 112 } 113 114 /* Init Chip */ 115 /* make sure RST is set; HBA_RST /should/ have done that for us */ 116 cctl = mr32(MVS_CTL) & 0xFFFF; 117 if (cctl & CCTL_RST) 118 cctl &= ~CCTL_RST; 119 else 120 mw32_f(MVS_CTL, cctl | CCTL_RST); 121 122 if (mvi->flags & MVF_FLAG_SOC) { 123 tmp = mr32(MVS_PHY_CTL); 124 tmp &= ~PCTL_PWR_OFF; 125 tmp |= PCTL_COM_ON; 126 tmp &= ~PCTL_PHY_DSBL; 127 tmp |= PCTL_LINK_RST; 128 mw32(MVS_PHY_CTL, tmp); 129 msleep(100); 130 tmp &= ~PCTL_LINK_RST; 131 mw32(MVS_PHY_CTL, tmp); 132 msleep(100); 133 } 134 135 /* reset control */ 136 mw32(MVS_PCS, 0); /* MVS_PCS */ 137 mw32(MVS_STP_REG_SET_0, 0); 138 mw32(MVS_STP_REG_SET_1, 0); 139 140 /* init phys */ 141 mvs_phy_hacks(mvi); 142 143 /* disable Multiplexing, enable phy implemented */ 144 mw32(MVS_PORTS_IMP, 0xFF); 145 146 147 mw32(MVS_PA_VSR_ADDR, 0x00000104); 148 mw32(MVS_PA_VSR_PORT, 0x00018080); 149 mw32(MVS_PA_VSR_ADDR, VSR_PHY_MODE8); 150 mw32(MVS_PA_VSR_PORT, 0x0084ffff); 151 152 /* set LED blink when IO*/ 153 mw32(MVS_PA_VSR_ADDR, 0x00000030); 154 tmp = mr32(MVS_PA_VSR_PORT); 155 tmp &= 0xFFFF00FF; 156 tmp |= 0x00003300; 157 mw32(MVS_PA_VSR_PORT, tmp); 158 159 mw32(MVS_CMD_LIST_LO, mvi->slot_dma); 160 mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16); 161 162 mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma); 163 mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16); 164 165 mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ); 166 mw32(MVS_TX_LO, mvi->tx_dma); 167 mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16); 168 169 mw32(MVS_RX_CFG, MVS_RX_RING_SZ); 170 mw32(MVS_RX_LO, mvi->rx_dma); 171 mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16); 172 173 for (i = 0; i < mvi->chip->n_phy; i++) { 174 mvs_94xx_phy_disable(mvi, i); 175 /* set phy local SAS address */ 176 mvs_set_sas_addr(mvi, i, CONFIG_ID_FRAME3, CONFIG_ID_FRAME4, 177 (mvi->phy[i].dev_sas_addr)); 178 179 mvs_94xx_enable_xmt(mvi, i); 180 mvs_94xx_phy_enable(mvi, i); 181 182 mvs_94xx_phy_reset(mvi, i, 1); 183 msleep(500); 184 mvs_94xx_detect_porttype(mvi, i); 185 } 186 187 if (mvi->flags & MVF_FLAG_SOC) { 188 /* set select registers */ 189 writel(0x0E008000, regs + 0x000); 190 writel(0x59000008, regs + 0x004); 191 writel(0x20, regs + 0x008); 192 writel(0x20, regs + 0x00c); 193 writel(0x20, regs + 0x010); 194 writel(0x20, regs + 0x014); 195 writel(0x20, regs + 0x018); 196 writel(0x20, regs + 0x01c); 197 } 198 for (i = 0; i < mvi->chip->n_phy; i++) { 199 /* clear phy int status */ 200 tmp = mvs_read_port_irq_stat(mvi, i); 201 tmp &= ~PHYEV_SIG_FIS; 202 mvs_write_port_irq_stat(mvi, i, tmp); 203 204 /* set phy int mask */ 205 tmp = PHYEV_RDY_CH | PHYEV_BROAD_CH | 206 PHYEV_ID_DONE | PHYEV_DCDR_ERR | PHYEV_CRC_ERR ; 207 mvs_write_port_irq_mask(mvi, i, tmp); 208 209 msleep(100); 210 mvs_update_phyinfo(mvi, i, 1); 211 } 212 213 /* FIXME: update wide port bitmaps */ 214 215 /* little endian for open address and command table, etc. */ 216 /* 217 * it seems that ( from the spec ) turning on big-endian won't 218 * do us any good on big-endian machines, need further confirmation 219 */ 220 cctl = mr32(MVS_CTL); 221 cctl |= CCTL_ENDIAN_CMD; 222 cctl |= CCTL_ENDIAN_DATA; 223 cctl &= ~CCTL_ENDIAN_OPEN; 224 cctl |= CCTL_ENDIAN_RSP; 225 mw32_f(MVS_CTL, cctl); 226 227 /* reset CMD queue */ 228 tmp = mr32(MVS_PCS); 229 tmp |= PCS_CMD_RST; 230 mw32(MVS_PCS, tmp); 231 /* interrupt coalescing may cause missing HW interrput in some case, 232 * and the max count is 0x1ff, while our max slot is 0x200, 233 * it will make count 0. 234 */ 235 tmp = 0; 236 mw32(MVS_INT_COAL, tmp); 237 238 tmp = 0x100; 239 mw32(MVS_INT_COAL_TMOUT, tmp); 240 241 /* ladies and gentlemen, start your engines */ 242 mw32(MVS_TX_CFG, 0); 243 mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ | TX_EN); 244 mw32(MVS_RX_CFG, MVS_RX_RING_SZ | RX_EN); 245 /* enable CMD/CMPL_Q/RESP mode */ 246 mw32(MVS_PCS, PCS_SATA_RETRY_2 | PCS_FIS_RX_EN | 247 PCS_CMD_EN | PCS_CMD_STOP_ERR); 248 249 /* enable completion queue interrupt */ 250 tmp = (CINT_PORT_MASK | CINT_DONE | CINT_MEM | CINT_SRS | CINT_CI_STOP | 251 CINT_DMA_PCIE); 252 tmp |= CINT_PHY_MASK; 253 mw32(MVS_INT_MASK, tmp); 254 255 /* Enable SRS interrupt */ 256 mw32(MVS_INT_MASK_SRS_0, 0xFFFF); 257 258 return 0; 259 } 260 261 static int mvs_94xx_ioremap(struct mvs_info *mvi) 262 { 263 if (!mvs_ioremap(mvi, 2, -1)) { 264 mvi->regs_ex = mvi->regs + 0x10200; 265 mvi->regs += 0x20000; 266 if (mvi->id == 1) 267 mvi->regs += 0x4000; 268 return 0; 269 } 270 return -1; 271 } 272 273 static void mvs_94xx_iounmap(struct mvs_info *mvi) 274 { 275 if (mvi->regs) { 276 mvi->regs -= 0x20000; 277 if (mvi->id == 1) 278 mvi->regs -= 0x4000; 279 mvs_iounmap(mvi->regs); 280 } 281 } 282 283 static void mvs_94xx_interrupt_enable(struct mvs_info *mvi) 284 { 285 void __iomem *regs = mvi->regs_ex; 286 u32 tmp; 287 288 tmp = mr32(MVS_GBL_CTL); 289 tmp |= (IRQ_SAS_A | IRQ_SAS_B); 290 mw32(MVS_GBL_INT_STAT, tmp); 291 writel(tmp, regs + 0x0C); 292 writel(tmp, regs + 0x10); 293 writel(tmp, regs + 0x14); 294 writel(tmp, regs + 0x18); 295 mw32(MVS_GBL_CTL, tmp); 296 } 297 298 static void mvs_94xx_interrupt_disable(struct mvs_info *mvi) 299 { 300 void __iomem *regs = mvi->regs_ex; 301 u32 tmp; 302 303 tmp = mr32(MVS_GBL_CTL); 304 305 tmp &= ~(IRQ_SAS_A | IRQ_SAS_B); 306 mw32(MVS_GBL_INT_STAT, tmp); 307 writel(tmp, regs + 0x0C); 308 writel(tmp, regs + 0x10); 309 writel(tmp, regs + 0x14); 310 writel(tmp, regs + 0x18); 311 mw32(MVS_GBL_CTL, tmp); 312 } 313 314 static u32 mvs_94xx_isr_status(struct mvs_info *mvi, int irq) 315 { 316 void __iomem *regs = mvi->regs_ex; 317 u32 stat = 0; 318 if (!(mvi->flags & MVF_FLAG_SOC)) { 319 stat = mr32(MVS_GBL_INT_STAT); 320 321 if (!(stat & (IRQ_SAS_A | IRQ_SAS_B))) 322 return 0; 323 } 324 return stat; 325 } 326 327 static irqreturn_t mvs_94xx_isr(struct mvs_info *mvi, int irq, u32 stat) 328 { 329 void __iomem *regs = mvi->regs; 330 331 if (((stat & IRQ_SAS_A) && mvi->id == 0) || 332 ((stat & IRQ_SAS_B) && mvi->id == 1)) { 333 mw32_f(MVS_INT_STAT, CINT_DONE); 334 #ifndef MVS_USE_TASKLET 335 spin_lock(&mvi->lock); 336 #endif 337 mvs_int_full(mvi); 338 #ifndef MVS_USE_TASKLET 339 spin_unlock(&mvi->lock); 340 #endif 341 } 342 return IRQ_HANDLED; 343 } 344 345 static void mvs_94xx_command_active(struct mvs_info *mvi, u32 slot_idx) 346 { 347 u32 tmp; 348 mvs_cw32(mvi, 0x300 + (slot_idx >> 3), 1 << (slot_idx % 32)); 349 do { 350 tmp = mvs_cr32(mvi, 0x300 + (slot_idx >> 3)); 351 } while (tmp & 1 << (slot_idx % 32)); 352 } 353 354 static void mvs_94xx_issue_stop(struct mvs_info *mvi, enum mvs_port_type type, 355 u32 tfs) 356 { 357 void __iomem *regs = mvi->regs; 358 u32 tmp; 359 360 if (type == PORT_TYPE_SATA) { 361 tmp = mr32(MVS_INT_STAT_SRS_0) | (1U << tfs); 362 mw32(MVS_INT_STAT_SRS_0, tmp); 363 } 364 mw32(MVS_INT_STAT, CINT_CI_STOP); 365 tmp = mr32(MVS_PCS) | 0xFF00; 366 mw32(MVS_PCS, tmp); 367 } 368 369 static void mvs_94xx_free_reg_set(struct mvs_info *mvi, u8 *tfs) 370 { 371 void __iomem *regs = mvi->regs; 372 u32 tmp; 373 u8 reg_set = *tfs; 374 375 if (*tfs == MVS_ID_NOT_MAPPED) 376 return; 377 378 mvi->sata_reg_set &= ~bit(reg_set); 379 if (reg_set < 32) { 380 w_reg_set_enable(reg_set, (u32)mvi->sata_reg_set); 381 tmp = mr32(MVS_INT_STAT_SRS_0) & (u32)mvi->sata_reg_set; 382 if (tmp) 383 mw32(MVS_INT_STAT_SRS_0, tmp); 384 } else { 385 w_reg_set_enable(reg_set, mvi->sata_reg_set); 386 tmp = mr32(MVS_INT_STAT_SRS_1) & mvi->sata_reg_set; 387 if (tmp) 388 mw32(MVS_INT_STAT_SRS_1, tmp); 389 } 390 391 *tfs = MVS_ID_NOT_MAPPED; 392 393 return; 394 } 395 396 static u8 mvs_94xx_assign_reg_set(struct mvs_info *mvi, u8 *tfs) 397 { 398 int i; 399 void __iomem *regs = mvi->regs; 400 401 if (*tfs != MVS_ID_NOT_MAPPED) 402 return 0; 403 404 i = mv_ffc64(mvi->sata_reg_set); 405 if (i > 32) { 406 mvi->sata_reg_set |= bit(i); 407 w_reg_set_enable(i, (u32)(mvi->sata_reg_set >> 32)); 408 *tfs = i; 409 return 0; 410 } else if (i >= 0) { 411 mvi->sata_reg_set |= bit(i); 412 w_reg_set_enable(i, (u32)mvi->sata_reg_set); 413 *tfs = i; 414 return 0; 415 } 416 return MVS_ID_NOT_MAPPED; 417 } 418 419 static void mvs_94xx_make_prd(struct scatterlist *scatter, int nr, void *prd) 420 { 421 int i; 422 struct scatterlist *sg; 423 struct mvs_prd *buf_prd = prd; 424 for_each_sg(scatter, sg, nr, i) { 425 buf_prd->addr = cpu_to_le64(sg_dma_address(sg)); 426 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg)); 427 buf_prd++; 428 } 429 } 430 431 static int mvs_94xx_oob_done(struct mvs_info *mvi, int i) 432 { 433 u32 phy_st; 434 phy_st = mvs_read_phy_ctl(mvi, i); 435 if (phy_st & PHY_READY_MASK) /* phy ready */ 436 return 1; 437 return 0; 438 } 439 440 static void mvs_94xx_get_dev_identify_frame(struct mvs_info *mvi, int port_id, 441 struct sas_identify_frame *id) 442 { 443 int i; 444 u32 id_frame[7]; 445 446 for (i = 0; i < 7; i++) { 447 mvs_write_port_cfg_addr(mvi, port_id, 448 CONFIG_ID_FRAME0 + i * 4); 449 id_frame[i] = mvs_read_port_cfg_data(mvi, port_id); 450 } 451 memcpy(id, id_frame, 28); 452 } 453 454 static void mvs_94xx_get_att_identify_frame(struct mvs_info *mvi, int port_id, 455 struct sas_identify_frame *id) 456 { 457 int i; 458 u32 id_frame[7]; 459 460 /* mvs_hexdump(28, (u8 *)id_frame, 0); */ 461 for (i = 0; i < 7; i++) { 462 mvs_write_port_cfg_addr(mvi, port_id, 463 CONFIG_ATT_ID_FRAME0 + i * 4); 464 id_frame[i] = mvs_read_port_cfg_data(mvi, port_id); 465 mv_dprintk("94xx phy %d atta frame %d %x.\n", 466 port_id + mvi->id * mvi->chip->n_phy, i, id_frame[i]); 467 } 468 /* mvs_hexdump(28, (u8 *)id_frame, 0); */ 469 memcpy(id, id_frame, 28); 470 } 471 472 static u32 mvs_94xx_make_dev_info(struct sas_identify_frame *id) 473 { 474 u32 att_dev_info = 0; 475 476 att_dev_info |= id->dev_type; 477 if (id->stp_iport) 478 att_dev_info |= PORT_DEV_STP_INIT; 479 if (id->smp_iport) 480 att_dev_info |= PORT_DEV_SMP_INIT; 481 if (id->ssp_iport) 482 att_dev_info |= PORT_DEV_SSP_INIT; 483 if (id->stp_tport) 484 att_dev_info |= PORT_DEV_STP_TRGT; 485 if (id->smp_tport) 486 att_dev_info |= PORT_DEV_SMP_TRGT; 487 if (id->ssp_tport) 488 att_dev_info |= PORT_DEV_SSP_TRGT; 489 490 att_dev_info |= (u32)id->phy_id<<24; 491 return att_dev_info; 492 } 493 494 static u32 mvs_94xx_make_att_info(struct sas_identify_frame *id) 495 { 496 return mvs_94xx_make_dev_info(id); 497 } 498 499 static void mvs_94xx_fix_phy_info(struct mvs_info *mvi, int i, 500 struct sas_identify_frame *id) 501 { 502 struct mvs_phy *phy = &mvi->phy[i]; 503 struct asd_sas_phy *sas_phy = &phy->sas_phy; 504 mv_dprintk("get all reg link rate is 0x%x\n", phy->phy_status); 505 sas_phy->linkrate = 506 (phy->phy_status & PHY_NEG_SPP_PHYS_LINK_RATE_MASK) >> 507 PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET; 508 sas_phy->linkrate += 0x8; 509 mv_dprintk("get link rate is %d\n", sas_phy->linkrate); 510 phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS; 511 phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS; 512 mvs_94xx_get_dev_identify_frame(mvi, i, id); 513 phy->dev_info = mvs_94xx_make_dev_info(id); 514 515 if (phy->phy_type & PORT_TYPE_SAS) { 516 mvs_94xx_get_att_identify_frame(mvi, i, id); 517 phy->att_dev_info = mvs_94xx_make_att_info(id); 518 phy->att_dev_sas_addr = *(u64 *)id->sas_addr; 519 } else { 520 phy->att_dev_info = PORT_DEV_STP_TRGT | 1; 521 } 522 523 } 524 525 void mvs_94xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id, 526 struct sas_phy_linkrates *rates) 527 { 528 /* TODO */ 529 } 530 531 static void mvs_94xx_clear_active_cmds(struct mvs_info *mvi) 532 { 533 u32 tmp; 534 void __iomem *regs = mvi->regs; 535 tmp = mr32(MVS_STP_REG_SET_0); 536 mw32(MVS_STP_REG_SET_0, 0); 537 mw32(MVS_STP_REG_SET_0, tmp); 538 tmp = mr32(MVS_STP_REG_SET_1); 539 mw32(MVS_STP_REG_SET_1, 0); 540 mw32(MVS_STP_REG_SET_1, tmp); 541 } 542 543 544 u32 mvs_94xx_spi_read_data(struct mvs_info *mvi) 545 { 546 void __iomem *regs = mvi->regs_ex - 0x10200; 547 return mr32(SPI_RD_DATA_REG_94XX); 548 } 549 550 void mvs_94xx_spi_write_data(struct mvs_info *mvi, u32 data) 551 { 552 void __iomem *regs = mvi->regs_ex - 0x10200; 553 mw32(SPI_RD_DATA_REG_94XX, data); 554 } 555 556 557 int mvs_94xx_spi_buildcmd(struct mvs_info *mvi, 558 u32 *dwCmd, 559 u8 cmd, 560 u8 read, 561 u8 length, 562 u32 addr 563 ) 564 { 565 void __iomem *regs = mvi->regs_ex - 0x10200; 566 u32 dwTmp; 567 568 dwTmp = ((u32)cmd << 8) | ((u32)length << 4); 569 if (read) 570 dwTmp |= SPI_CTRL_READ_94XX; 571 572 if (addr != MV_MAX_U32) { 573 mw32(SPI_ADDR_REG_94XX, (addr & 0x0003FFFFL)); 574 dwTmp |= SPI_ADDR_VLD_94XX; 575 } 576 577 *dwCmd = dwTmp; 578 return 0; 579 } 580 581 582 int mvs_94xx_spi_issuecmd(struct mvs_info *mvi, u32 cmd) 583 { 584 void __iomem *regs = mvi->regs_ex - 0x10200; 585 mw32(SPI_CTRL_REG_94XX, cmd | SPI_CTRL_SpiStart_94XX); 586 587 return 0; 588 } 589 590 int mvs_94xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout) 591 { 592 void __iomem *regs = mvi->regs_ex - 0x10200; 593 u32 i, dwTmp; 594 595 for (i = 0; i < timeout; i++) { 596 dwTmp = mr32(SPI_CTRL_REG_94XX); 597 if (!(dwTmp & SPI_CTRL_SpiStart_94XX)) 598 return 0; 599 msleep(10); 600 } 601 602 return -1; 603 } 604 605 #ifndef DISABLE_HOTPLUG_DMA_FIX 606 void mvs_94xx_fix_dma(dma_addr_t buf_dma, int buf_len, int from, void *prd) 607 { 608 int i; 609 struct mvs_prd *buf_prd = prd; 610 buf_prd += from; 611 for (i = 0; i < MAX_SG_ENTRY - from; i++) { 612 buf_prd->addr = cpu_to_le64(buf_dma); 613 buf_prd->im_len.len = cpu_to_le32(buf_len); 614 ++buf_prd; 615 } 616 } 617 #endif 618 619 /* 620 * FIXME JEJB: temporary nop clear_srs_irq to make 94xx still work 621 * with 64xx fixes 622 */ 623 static void mvs_94xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, 624 u8 clear_all) 625 { 626 } 627 628 const struct mvs_dispatch mvs_94xx_dispatch = { 629 "mv94xx", 630 mvs_94xx_init, 631 NULL, 632 mvs_94xx_ioremap, 633 mvs_94xx_iounmap, 634 mvs_94xx_isr, 635 mvs_94xx_isr_status, 636 mvs_94xx_interrupt_enable, 637 mvs_94xx_interrupt_disable, 638 mvs_read_phy_ctl, 639 mvs_write_phy_ctl, 640 mvs_read_port_cfg_data, 641 mvs_write_port_cfg_data, 642 mvs_write_port_cfg_addr, 643 mvs_read_port_vsr_data, 644 mvs_write_port_vsr_data, 645 mvs_write_port_vsr_addr, 646 mvs_read_port_irq_stat, 647 mvs_write_port_irq_stat, 648 mvs_read_port_irq_mask, 649 mvs_write_port_irq_mask, 650 mvs_get_sas_addr, 651 mvs_94xx_command_active, 652 mvs_94xx_clear_srs_irq, 653 mvs_94xx_issue_stop, 654 mvs_start_delivery, 655 mvs_rx_update, 656 mvs_int_full, 657 mvs_94xx_assign_reg_set, 658 mvs_94xx_free_reg_set, 659 mvs_get_prd_size, 660 mvs_get_prd_count, 661 mvs_94xx_make_prd, 662 mvs_94xx_detect_porttype, 663 mvs_94xx_oob_done, 664 mvs_94xx_fix_phy_info, 665 NULL, 666 mvs_94xx_phy_set_link_rate, 667 mvs_hw_max_link_rate, 668 mvs_94xx_phy_disable, 669 mvs_94xx_phy_enable, 670 mvs_94xx_phy_reset, 671 NULL, 672 mvs_94xx_clear_active_cmds, 673 mvs_94xx_spi_read_data, 674 mvs_94xx_spi_write_data, 675 mvs_94xx_spi_buildcmd, 676 mvs_94xx_spi_issuecmd, 677 mvs_94xx_spi_waitdataready, 678 #ifndef DISABLE_HOTPLUG_DMA_FIX 679 mvs_94xx_fix_dma, 680 #endif 681 }; 682 683