1 /* 2 * Marvell 88SE94xx hardware specific 3 * 4 * Copyright 2007 Red Hat, Inc. 5 * Copyright 2008 Marvell. <kewei@marvell.com> 6 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com> 7 * 8 * This file is licensed under GPLv2. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; version 2 of the 13 * License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 23 * USA 24 */ 25 26 #include "mv_sas.h" 27 #include "mv_94xx.h" 28 #include "mv_chips.h" 29 30 static void mvs_94xx_detect_porttype(struct mvs_info *mvi, int i) 31 { 32 u32 reg; 33 struct mvs_phy *phy = &mvi->phy[i]; 34 u32 phy_status; 35 36 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE3); 37 reg = mvs_read_port_vsr_data(mvi, i); 38 phy_status = ((reg & 0x3f0000) >> 16) & 0xff; 39 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 40 switch (phy_status) { 41 case 0x10: 42 phy->phy_type |= PORT_TYPE_SAS; 43 break; 44 case 0x1d: 45 default: 46 phy->phy_type |= PORT_TYPE_SATA; 47 break; 48 } 49 } 50 51 void set_phy_tuning(struct mvs_info *mvi, int phy_id, 52 struct phy_tuning phy_tuning) 53 { 54 u32 tmp, setting_0 = 0, setting_1 = 0; 55 u8 i; 56 57 /* Remap information for B0 chip: 58 * 59 * R0Ch -> R118h[15:0] (Adapted DFE F3 - F5 coefficient) 60 * R0Dh -> R118h[31:16] (Generation 1 Setting 0) 61 * R0Eh -> R11Ch[15:0] (Generation 1 Setting 1) 62 * R0Fh -> R11Ch[31:16] (Generation 2 Setting 0) 63 * R10h -> R120h[15:0] (Generation 2 Setting 1) 64 * R11h -> R120h[31:16] (Generation 3 Setting 0) 65 * R12h -> R124h[15:0] (Generation 3 Setting 1) 66 * R13h -> R124h[31:16] (Generation 4 Setting 0 (Reserved)) 67 */ 68 69 /* A0 has a different set of registers */ 70 if (mvi->pdev->revision == VANIR_A0_REV) 71 return; 72 73 for (i = 0; i < 3; i++) { 74 /* loop 3 times, set Gen 1, Gen 2, Gen 3 */ 75 switch (i) { 76 case 0: 77 setting_0 = GENERATION_1_SETTING; 78 setting_1 = GENERATION_1_2_SETTING; 79 break; 80 case 1: 81 setting_0 = GENERATION_1_2_SETTING; 82 setting_1 = GENERATION_2_3_SETTING; 83 break; 84 case 2: 85 setting_0 = GENERATION_2_3_SETTING; 86 setting_1 = GENERATION_3_4_SETTING; 87 break; 88 } 89 90 /* Set: 91 * 92 * Transmitter Emphasis Enable 93 * Transmitter Emphasis Amplitude 94 * Transmitter Amplitude 95 */ 96 mvs_write_port_vsr_addr(mvi, phy_id, setting_0); 97 tmp = mvs_read_port_vsr_data(mvi, phy_id); 98 tmp &= ~(0xFBE << 16); 99 tmp |= (((phy_tuning.trans_emp_en << 11) | 100 (phy_tuning.trans_emp_amp << 7) | 101 (phy_tuning.trans_amp << 1)) << 16); 102 mvs_write_port_vsr_data(mvi, phy_id, tmp); 103 104 /* Set Transmitter Amplitude Adjust */ 105 mvs_write_port_vsr_addr(mvi, phy_id, setting_1); 106 tmp = mvs_read_port_vsr_data(mvi, phy_id); 107 tmp &= ~(0xC000); 108 tmp |= (phy_tuning.trans_amp_adj << 14); 109 mvs_write_port_vsr_data(mvi, phy_id, tmp); 110 } 111 } 112 113 void set_phy_ffe_tuning(struct mvs_info *mvi, int phy_id, 114 struct ffe_control ffe) 115 { 116 u32 tmp; 117 118 /* Don't run this if A0/B0 */ 119 if ((mvi->pdev->revision == VANIR_A0_REV) 120 || (mvi->pdev->revision == VANIR_B0_REV)) 121 return; 122 123 /* FFE Resistor and Capacitor */ 124 /* R10Ch DFE Resolution Control/Squelch and FFE Setting 125 * 126 * FFE_FORCE [7] 127 * FFE_RES_SEL [6:4] 128 * FFE_CAP_SEL [3:0] 129 */ 130 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_FFE_CONTROL); 131 tmp = mvs_read_port_vsr_data(mvi, phy_id); 132 tmp &= ~0xFF; 133 134 /* Read from HBA_Info_Page */ 135 tmp |= ((0x1 << 7) | 136 (ffe.ffe_rss_sel << 4) | 137 (ffe.ffe_cap_sel << 0)); 138 139 mvs_write_port_vsr_data(mvi, phy_id, tmp); 140 141 /* R064h PHY Mode Register 1 142 * 143 * DFE_DIS 18 144 */ 145 mvs_write_port_vsr_addr(mvi, phy_id, VSR_REF_CLOCK_CRTL); 146 tmp = mvs_read_port_vsr_data(mvi, phy_id); 147 tmp &= ~0x40001; 148 /* Hard coding */ 149 /* No defines in HBA_Info_Page */ 150 tmp |= (0 << 18); 151 mvs_write_port_vsr_data(mvi, phy_id, tmp); 152 153 /* R110h DFE F0-F1 Coefficient Control/DFE Update Control 154 * 155 * DFE_UPDATE_EN [11:6] 156 * DFE_FX_FORCE [5:0] 157 */ 158 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_DFE_UPDATE_CRTL); 159 tmp = mvs_read_port_vsr_data(mvi, phy_id); 160 tmp &= ~0xFFF; 161 /* Hard coding */ 162 /* No defines in HBA_Info_Page */ 163 tmp |= ((0x3F << 6) | (0x0 << 0)); 164 mvs_write_port_vsr_data(mvi, phy_id, tmp); 165 166 /* R1A0h Interface and Digital Reference Clock Control/Reserved_50h 167 * 168 * FFE_TRAIN_EN 3 169 */ 170 mvs_write_port_vsr_addr(mvi, phy_id, VSR_REF_CLOCK_CRTL); 171 tmp = mvs_read_port_vsr_data(mvi, phy_id); 172 tmp &= ~0x8; 173 /* Hard coding */ 174 /* No defines in HBA_Info_Page */ 175 tmp |= (0 << 3); 176 mvs_write_port_vsr_data(mvi, phy_id, tmp); 177 } 178 179 /*Notice: this function must be called when phy is disabled*/ 180 void set_phy_rate(struct mvs_info *mvi, int phy_id, u8 rate) 181 { 182 union reg_phy_cfg phy_cfg, phy_cfg_tmp; 183 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2); 184 phy_cfg_tmp.v = mvs_read_port_vsr_data(mvi, phy_id); 185 phy_cfg.v = 0; 186 phy_cfg.u.disable_phy = phy_cfg_tmp.u.disable_phy; 187 phy_cfg.u.sas_support = 1; 188 phy_cfg.u.sata_support = 1; 189 phy_cfg.u.sata_host_mode = 1; 190 191 switch (rate) { 192 case 0x0: 193 /* support 1.5 Gbps */ 194 phy_cfg.u.speed_support = 1; 195 phy_cfg.u.snw_3_support = 0; 196 phy_cfg.u.tx_lnk_parity = 1; 197 phy_cfg.u.tx_spt_phs_lnk_rate = 0x30; 198 break; 199 case 0x1: 200 201 /* support 1.5, 3.0 Gbps */ 202 phy_cfg.u.speed_support = 3; 203 phy_cfg.u.tx_spt_phs_lnk_rate = 0x3c; 204 phy_cfg.u.tx_lgcl_lnk_rate = 0x08; 205 break; 206 case 0x2: 207 default: 208 /* support 1.5, 3.0, 6.0 Gbps */ 209 phy_cfg.u.speed_support = 7; 210 phy_cfg.u.snw_3_support = 1; 211 phy_cfg.u.tx_lnk_parity = 1; 212 phy_cfg.u.tx_spt_phs_lnk_rate = 0x3f; 213 phy_cfg.u.tx_lgcl_lnk_rate = 0x09; 214 break; 215 } 216 mvs_write_port_vsr_data(mvi, phy_id, phy_cfg.v); 217 } 218 219 static void __devinit 220 mvs_94xx_config_reg_from_hba(struct mvs_info *mvi, int phy_id) 221 { 222 u32 temp; 223 temp = (u32)(*(u32 *)&mvi->hba_info_param.phy_tuning[phy_id]); 224 if (temp == 0xFFFFFFFFL) { 225 mvi->hba_info_param.phy_tuning[phy_id].trans_emp_amp = 0x6; 226 mvi->hba_info_param.phy_tuning[phy_id].trans_amp = 0x1A; 227 mvi->hba_info_param.phy_tuning[phy_id].trans_amp_adj = 0x3; 228 } 229 230 temp = (u8)(*(u8 *)&mvi->hba_info_param.ffe_ctl[phy_id]); 231 if (temp == 0xFFL) { 232 switch (mvi->pdev->revision) { 233 case VANIR_A0_REV: 234 case VANIR_B0_REV: 235 mvi->hba_info_param.ffe_ctl[phy_id].ffe_rss_sel = 0x7; 236 mvi->hba_info_param.ffe_ctl[phy_id].ffe_cap_sel = 0x7; 237 break; 238 case VANIR_C0_REV: 239 case VANIR_C1_REV: 240 case VANIR_C2_REV: 241 default: 242 mvi->hba_info_param.ffe_ctl[phy_id].ffe_rss_sel = 0x7; 243 mvi->hba_info_param.ffe_ctl[phy_id].ffe_cap_sel = 0xC; 244 break; 245 } 246 } 247 248 temp = (u8)(*(u8 *)&mvi->hba_info_param.phy_rate[phy_id]); 249 if (temp == 0xFFL) 250 /*set default phy_rate = 6Gbps*/ 251 mvi->hba_info_param.phy_rate[phy_id] = 0x2; 252 253 set_phy_tuning(mvi, phy_id, 254 mvi->hba_info_param.phy_tuning[phy_id]); 255 set_phy_ffe_tuning(mvi, phy_id, 256 mvi->hba_info_param.ffe_ctl[phy_id]); 257 set_phy_rate(mvi, phy_id, 258 mvi->hba_info_param.phy_rate[phy_id]); 259 } 260 261 static void __devinit mvs_94xx_enable_xmt(struct mvs_info *mvi, int phy_id) 262 { 263 void __iomem *regs = mvi->regs; 264 u32 tmp; 265 266 tmp = mr32(MVS_PCS); 267 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2); 268 mw32(MVS_PCS, tmp); 269 } 270 271 static void mvs_94xx_phy_reset(struct mvs_info *mvi, u32 phy_id, int hard) 272 { 273 u32 tmp; 274 u32 delay = 5000; 275 if (hard == MVS_PHY_TUNE) { 276 mvs_write_port_cfg_addr(mvi, phy_id, PHYR_SATA_CTL); 277 tmp = mvs_read_port_cfg_data(mvi, phy_id); 278 mvs_write_port_cfg_data(mvi, phy_id, tmp|0x20000000); 279 mvs_write_port_cfg_data(mvi, phy_id, tmp|0x100000); 280 return; 281 } 282 tmp = mvs_read_port_irq_stat(mvi, phy_id); 283 tmp &= ~PHYEV_RDY_CH; 284 mvs_write_port_irq_stat(mvi, phy_id, tmp); 285 if (hard) { 286 tmp = mvs_read_phy_ctl(mvi, phy_id); 287 tmp |= PHY_RST_HARD; 288 mvs_write_phy_ctl(mvi, phy_id, tmp); 289 do { 290 tmp = mvs_read_phy_ctl(mvi, phy_id); 291 udelay(10); 292 delay--; 293 } while ((tmp & PHY_RST_HARD) && delay); 294 if (!delay) 295 mv_dprintk("phy hard reset failed.\n"); 296 } else { 297 tmp = mvs_read_phy_ctl(mvi, phy_id); 298 tmp |= PHY_RST; 299 mvs_write_phy_ctl(mvi, phy_id, tmp); 300 } 301 } 302 303 static void mvs_94xx_phy_disable(struct mvs_info *mvi, u32 phy_id) 304 { 305 u32 tmp; 306 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2); 307 tmp = mvs_read_port_vsr_data(mvi, phy_id); 308 mvs_write_port_vsr_data(mvi, phy_id, tmp | 0x00800000); 309 } 310 311 static void mvs_94xx_phy_enable(struct mvs_info *mvi, u32 phy_id) 312 { 313 u32 tmp; 314 u8 revision = 0; 315 316 revision = mvi->pdev->revision; 317 if (revision == VANIR_A0_REV) { 318 mvs_write_port_vsr_addr(mvi, phy_id, CMD_HOST_RD_DATA); 319 mvs_write_port_vsr_data(mvi, phy_id, 0x8300ffc1); 320 } 321 if (revision == VANIR_B0_REV) { 322 mvs_write_port_vsr_addr(mvi, phy_id, CMD_APP_MEM_CTL); 323 mvs_write_port_vsr_data(mvi, phy_id, 0x08001006); 324 mvs_write_port_vsr_addr(mvi, phy_id, CMD_HOST_RD_DATA); 325 mvs_write_port_vsr_data(mvi, phy_id, 0x0000705f); 326 } 327 328 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2); 329 tmp = mvs_read_port_vsr_data(mvi, phy_id); 330 tmp |= bit(0); 331 mvs_write_port_vsr_data(mvi, phy_id, tmp & 0xfd7fffff); 332 } 333 334 static int __devinit mvs_94xx_init(struct mvs_info *mvi) 335 { 336 void __iomem *regs = mvi->regs; 337 int i; 338 u32 tmp, cctl; 339 u8 revision; 340 341 revision = mvi->pdev->revision; 342 mvs_show_pcie_usage(mvi); 343 if (mvi->flags & MVF_FLAG_SOC) { 344 tmp = mr32(MVS_PHY_CTL); 345 tmp &= ~PCTL_PWR_OFF; 346 tmp |= PCTL_PHY_DSBL; 347 mw32(MVS_PHY_CTL, tmp); 348 } 349 350 /* Init Chip */ 351 /* make sure RST is set; HBA_RST /should/ have done that for us */ 352 cctl = mr32(MVS_CTL) & 0xFFFF; 353 if (cctl & CCTL_RST) 354 cctl &= ~CCTL_RST; 355 else 356 mw32_f(MVS_CTL, cctl | CCTL_RST); 357 358 if (mvi->flags & MVF_FLAG_SOC) { 359 tmp = mr32(MVS_PHY_CTL); 360 tmp &= ~PCTL_PWR_OFF; 361 tmp |= PCTL_COM_ON; 362 tmp &= ~PCTL_PHY_DSBL; 363 tmp |= PCTL_LINK_RST; 364 mw32(MVS_PHY_CTL, tmp); 365 msleep(100); 366 tmp &= ~PCTL_LINK_RST; 367 mw32(MVS_PHY_CTL, tmp); 368 msleep(100); 369 } 370 371 /* disable Multiplexing, enable phy implemented */ 372 mw32(MVS_PORTS_IMP, 0xFF); 373 374 if (revision == VANIR_A0_REV) { 375 mw32(MVS_PA_VSR_ADDR, CMD_CMWK_OOB_DET); 376 mw32(MVS_PA_VSR_PORT, 0x00018080); 377 } 378 mw32(MVS_PA_VSR_ADDR, VSR_PHY_MODE2); 379 if (revision == VANIR_A0_REV || revision == VANIR_B0_REV) 380 /* set 6G/3G/1.5G, multiplexing, without SSC */ 381 mw32(MVS_PA_VSR_PORT, 0x0084d4fe); 382 else 383 /* set 6G/3G/1.5G, multiplexing, with and without SSC */ 384 mw32(MVS_PA_VSR_PORT, 0x0084fffe); 385 386 if (revision == VANIR_B0_REV) { 387 mw32(MVS_PA_VSR_ADDR, CMD_APP_MEM_CTL); 388 mw32(MVS_PA_VSR_PORT, 0x08001006); 389 mw32(MVS_PA_VSR_ADDR, CMD_HOST_RD_DATA); 390 mw32(MVS_PA_VSR_PORT, 0x0000705f); 391 } 392 393 /* reset control */ 394 mw32(MVS_PCS, 0); /* MVS_PCS */ 395 mw32(MVS_STP_REG_SET_0, 0); 396 mw32(MVS_STP_REG_SET_1, 0); 397 398 /* init phys */ 399 mvs_phy_hacks(mvi); 400 401 /* set LED blink when IO*/ 402 mw32(MVS_PA_VSR_ADDR, VSR_PHY_ACT_LED); 403 tmp = mr32(MVS_PA_VSR_PORT); 404 tmp &= 0xFFFF00FF; 405 tmp |= 0x00003300; 406 mw32(MVS_PA_VSR_PORT, tmp); 407 408 mw32(MVS_CMD_LIST_LO, mvi->slot_dma); 409 mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16); 410 411 mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma); 412 mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16); 413 414 mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ); 415 mw32(MVS_TX_LO, mvi->tx_dma); 416 mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16); 417 418 mw32(MVS_RX_CFG, MVS_RX_RING_SZ); 419 mw32(MVS_RX_LO, mvi->rx_dma); 420 mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16); 421 422 for (i = 0; i < mvi->chip->n_phy; i++) { 423 mvs_94xx_phy_disable(mvi, i); 424 /* set phy local SAS address */ 425 mvs_set_sas_addr(mvi, i, CONFIG_ID_FRAME3, CONFIG_ID_FRAME4, 426 cpu_to_le64(mvi->phy[i].dev_sas_addr)); 427 428 mvs_94xx_enable_xmt(mvi, i); 429 mvs_94xx_config_reg_from_hba(mvi, i); 430 mvs_94xx_phy_enable(mvi, i); 431 432 mvs_94xx_phy_reset(mvi, i, PHY_RST_HARD); 433 msleep(500); 434 mvs_94xx_detect_porttype(mvi, i); 435 } 436 437 if (mvi->flags & MVF_FLAG_SOC) { 438 /* set select registers */ 439 writel(0x0E008000, regs + 0x000); 440 writel(0x59000008, regs + 0x004); 441 writel(0x20, regs + 0x008); 442 writel(0x20, regs + 0x00c); 443 writel(0x20, regs + 0x010); 444 writel(0x20, regs + 0x014); 445 writel(0x20, regs + 0x018); 446 writel(0x20, regs + 0x01c); 447 } 448 for (i = 0; i < mvi->chip->n_phy; i++) { 449 /* clear phy int status */ 450 tmp = mvs_read_port_irq_stat(mvi, i); 451 tmp &= ~PHYEV_SIG_FIS; 452 mvs_write_port_irq_stat(mvi, i, tmp); 453 454 /* set phy int mask */ 455 tmp = PHYEV_RDY_CH | PHYEV_BROAD_CH | 456 PHYEV_ID_DONE | PHYEV_DCDR_ERR | PHYEV_CRC_ERR ; 457 mvs_write_port_irq_mask(mvi, i, tmp); 458 459 msleep(100); 460 mvs_update_phyinfo(mvi, i, 1); 461 } 462 463 /* little endian for open address and command table, etc. */ 464 cctl = mr32(MVS_CTL); 465 cctl |= CCTL_ENDIAN_CMD; 466 cctl &= ~CCTL_ENDIAN_OPEN; 467 cctl |= CCTL_ENDIAN_RSP; 468 mw32_f(MVS_CTL, cctl); 469 470 /* reset CMD queue */ 471 tmp = mr32(MVS_PCS); 472 tmp |= PCS_CMD_RST; 473 tmp &= ~PCS_SELF_CLEAR; 474 mw32(MVS_PCS, tmp); 475 /* 476 * the max count is 0x1ff, while our max slot is 0x200, 477 * it will make count 0. 478 */ 479 tmp = 0; 480 if (MVS_CHIP_SLOT_SZ > 0x1ff) 481 mw32(MVS_INT_COAL, 0x1ff | COAL_EN); 482 else 483 mw32(MVS_INT_COAL, MVS_CHIP_SLOT_SZ | COAL_EN); 484 485 /* default interrupt coalescing time is 128us */ 486 tmp = 0x10000 | interrupt_coalescing; 487 mw32(MVS_INT_COAL_TMOUT, tmp); 488 489 /* ladies and gentlemen, start your engines */ 490 mw32(MVS_TX_CFG, 0); 491 mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ | TX_EN); 492 mw32(MVS_RX_CFG, MVS_RX_RING_SZ | RX_EN); 493 /* enable CMD/CMPL_Q/RESP mode */ 494 mw32(MVS_PCS, PCS_SATA_RETRY_2 | PCS_FIS_RX_EN | 495 PCS_CMD_EN | PCS_CMD_STOP_ERR); 496 497 /* enable completion queue interrupt */ 498 tmp = (CINT_PORT_MASK | CINT_DONE | CINT_MEM | CINT_SRS | CINT_CI_STOP | 499 CINT_DMA_PCIE | CINT_NON_SPEC_NCQ_ERROR); 500 tmp |= CINT_PHY_MASK; 501 mw32(MVS_INT_MASK, tmp); 502 503 /* Enable SRS interrupt */ 504 mw32(MVS_INT_MASK_SRS_0, 0xFFFF); 505 506 return 0; 507 } 508 509 static int mvs_94xx_ioremap(struct mvs_info *mvi) 510 { 511 if (!mvs_ioremap(mvi, 2, -1)) { 512 mvi->regs_ex = mvi->regs + 0x10200; 513 mvi->regs += 0x20000; 514 if (mvi->id == 1) 515 mvi->regs += 0x4000; 516 return 0; 517 } 518 return -1; 519 } 520 521 static void mvs_94xx_iounmap(struct mvs_info *mvi) 522 { 523 if (mvi->regs) { 524 mvi->regs -= 0x20000; 525 if (mvi->id == 1) 526 mvi->regs -= 0x4000; 527 mvs_iounmap(mvi->regs); 528 } 529 } 530 531 static void mvs_94xx_interrupt_enable(struct mvs_info *mvi) 532 { 533 void __iomem *regs = mvi->regs_ex; 534 u32 tmp; 535 536 tmp = mr32(MVS_GBL_CTL); 537 tmp |= (IRQ_SAS_A | IRQ_SAS_B); 538 mw32(MVS_GBL_INT_STAT, tmp); 539 writel(tmp, regs + 0x0C); 540 writel(tmp, regs + 0x10); 541 writel(tmp, regs + 0x14); 542 writel(tmp, regs + 0x18); 543 mw32(MVS_GBL_CTL, tmp); 544 } 545 546 static void mvs_94xx_interrupt_disable(struct mvs_info *mvi) 547 { 548 void __iomem *regs = mvi->regs_ex; 549 u32 tmp; 550 551 tmp = mr32(MVS_GBL_CTL); 552 553 tmp &= ~(IRQ_SAS_A | IRQ_SAS_B); 554 mw32(MVS_GBL_INT_STAT, tmp); 555 writel(tmp, regs + 0x0C); 556 writel(tmp, regs + 0x10); 557 writel(tmp, regs + 0x14); 558 writel(tmp, regs + 0x18); 559 mw32(MVS_GBL_CTL, tmp); 560 } 561 562 static u32 mvs_94xx_isr_status(struct mvs_info *mvi, int irq) 563 { 564 void __iomem *regs = mvi->regs_ex; 565 u32 stat = 0; 566 if (!(mvi->flags & MVF_FLAG_SOC)) { 567 stat = mr32(MVS_GBL_INT_STAT); 568 569 if (!(stat & (IRQ_SAS_A | IRQ_SAS_B))) 570 return 0; 571 } 572 return stat; 573 } 574 575 static irqreturn_t mvs_94xx_isr(struct mvs_info *mvi, int irq, u32 stat) 576 { 577 void __iomem *regs = mvi->regs; 578 579 if (((stat & IRQ_SAS_A) && mvi->id == 0) || 580 ((stat & IRQ_SAS_B) && mvi->id == 1)) { 581 mw32_f(MVS_INT_STAT, CINT_DONE); 582 583 spin_lock(&mvi->lock); 584 mvs_int_full(mvi); 585 spin_unlock(&mvi->lock); 586 } 587 return IRQ_HANDLED; 588 } 589 590 static void mvs_94xx_command_active(struct mvs_info *mvi, u32 slot_idx) 591 { 592 u32 tmp; 593 tmp = mvs_cr32(mvi, MVS_COMMAND_ACTIVE+(slot_idx >> 3)); 594 if (tmp && 1 << (slot_idx % 32)) { 595 mv_printk("command active %08X, slot [%x].\n", tmp, slot_idx); 596 mvs_cw32(mvi, MVS_COMMAND_ACTIVE + (slot_idx >> 3), 597 1 << (slot_idx % 32)); 598 do { 599 tmp = mvs_cr32(mvi, 600 MVS_COMMAND_ACTIVE + (slot_idx >> 3)); 601 } while (tmp & 1 << (slot_idx % 32)); 602 } 603 } 604 605 void mvs_94xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, u8 clear_all) 606 { 607 void __iomem *regs = mvi->regs; 608 u32 tmp; 609 610 if (clear_all) { 611 tmp = mr32(MVS_INT_STAT_SRS_0); 612 if (tmp) { 613 mv_dprintk("check SRS 0 %08X.\n", tmp); 614 mw32(MVS_INT_STAT_SRS_0, tmp); 615 } 616 tmp = mr32(MVS_INT_STAT_SRS_1); 617 if (tmp) { 618 mv_dprintk("check SRS 1 %08X.\n", tmp); 619 mw32(MVS_INT_STAT_SRS_1, tmp); 620 } 621 } else { 622 if (reg_set > 31) 623 tmp = mr32(MVS_INT_STAT_SRS_1); 624 else 625 tmp = mr32(MVS_INT_STAT_SRS_0); 626 627 if (tmp & (1 << (reg_set % 32))) { 628 mv_dprintk("register set 0x%x was stopped.\n", reg_set); 629 if (reg_set > 31) 630 mw32(MVS_INT_STAT_SRS_1, 1 << (reg_set % 32)); 631 else 632 mw32(MVS_INT_STAT_SRS_0, 1 << (reg_set % 32)); 633 } 634 } 635 } 636 637 static void mvs_94xx_issue_stop(struct mvs_info *mvi, enum mvs_port_type type, 638 u32 tfs) 639 { 640 void __iomem *regs = mvi->regs; 641 u32 tmp; 642 mvs_94xx_clear_srs_irq(mvi, 0, 1); 643 644 tmp = mr32(MVS_INT_STAT); 645 mw32(MVS_INT_STAT, tmp | CINT_CI_STOP); 646 tmp = mr32(MVS_PCS) | 0xFF00; 647 mw32(MVS_PCS, tmp); 648 } 649 650 static void mvs_94xx_non_spec_ncq_error(struct mvs_info *mvi) 651 { 652 void __iomem *regs = mvi->regs; 653 u32 err_0, err_1; 654 u8 i; 655 struct mvs_device *device; 656 657 err_0 = mr32(MVS_NON_NCQ_ERR_0); 658 err_1 = mr32(MVS_NON_NCQ_ERR_1); 659 660 mv_dprintk("non specific ncq error err_0:%x,err_1:%x.\n", 661 err_0, err_1); 662 for (i = 0; i < 32; i++) { 663 if (err_0 & bit(i)) { 664 device = mvs_find_dev_by_reg_set(mvi, i); 665 if (device) 666 mvs_release_task(mvi, device->sas_device); 667 } 668 if (err_1 & bit(i)) { 669 device = mvs_find_dev_by_reg_set(mvi, i+32); 670 if (device) 671 mvs_release_task(mvi, device->sas_device); 672 } 673 } 674 675 mw32(MVS_NON_NCQ_ERR_0, err_0); 676 mw32(MVS_NON_NCQ_ERR_1, err_1); 677 } 678 679 static void mvs_94xx_free_reg_set(struct mvs_info *mvi, u8 *tfs) 680 { 681 void __iomem *regs = mvi->regs; 682 u8 reg_set = *tfs; 683 684 if (*tfs == MVS_ID_NOT_MAPPED) 685 return; 686 687 mvi->sata_reg_set &= ~bit(reg_set); 688 if (reg_set < 32) 689 w_reg_set_enable(reg_set, (u32)mvi->sata_reg_set); 690 else 691 w_reg_set_enable(reg_set, (u32)(mvi->sata_reg_set >> 32)); 692 693 *tfs = MVS_ID_NOT_MAPPED; 694 695 return; 696 } 697 698 static u8 mvs_94xx_assign_reg_set(struct mvs_info *mvi, u8 *tfs) 699 { 700 int i; 701 void __iomem *regs = mvi->regs; 702 703 if (*tfs != MVS_ID_NOT_MAPPED) 704 return 0; 705 706 i = mv_ffc64(mvi->sata_reg_set); 707 if (i >= 32) { 708 mvi->sata_reg_set |= bit(i); 709 w_reg_set_enable(i, (u32)(mvi->sata_reg_set >> 32)); 710 *tfs = i; 711 return 0; 712 } else if (i >= 0) { 713 mvi->sata_reg_set |= bit(i); 714 w_reg_set_enable(i, (u32)mvi->sata_reg_set); 715 *tfs = i; 716 return 0; 717 } 718 return MVS_ID_NOT_MAPPED; 719 } 720 721 static void mvs_94xx_make_prd(struct scatterlist *scatter, int nr, void *prd) 722 { 723 int i; 724 struct scatterlist *sg; 725 struct mvs_prd *buf_prd = prd; 726 struct mvs_prd_imt im_len; 727 *(u32 *)&im_len = 0; 728 for_each_sg(scatter, sg, nr, i) { 729 buf_prd->addr = cpu_to_le64(sg_dma_address(sg)); 730 im_len.len = sg_dma_len(sg); 731 buf_prd->im_len = cpu_to_le32(*(u32 *)&im_len); 732 buf_prd++; 733 } 734 } 735 736 static int mvs_94xx_oob_done(struct mvs_info *mvi, int i) 737 { 738 u32 phy_st; 739 phy_st = mvs_read_phy_ctl(mvi, i); 740 if (phy_st & PHY_READY_MASK) 741 return 1; 742 return 0; 743 } 744 745 static void mvs_94xx_get_dev_identify_frame(struct mvs_info *mvi, int port_id, 746 struct sas_identify_frame *id) 747 { 748 int i; 749 u32 id_frame[7]; 750 751 for (i = 0; i < 7; i++) { 752 mvs_write_port_cfg_addr(mvi, port_id, 753 CONFIG_ID_FRAME0 + i * 4); 754 id_frame[i] = cpu_to_le32(mvs_read_port_cfg_data(mvi, port_id)); 755 } 756 memcpy(id, id_frame, 28); 757 } 758 759 static void mvs_94xx_get_att_identify_frame(struct mvs_info *mvi, int port_id, 760 struct sas_identify_frame *id) 761 { 762 int i; 763 u32 id_frame[7]; 764 765 for (i = 0; i < 7; i++) { 766 mvs_write_port_cfg_addr(mvi, port_id, 767 CONFIG_ATT_ID_FRAME0 + i * 4); 768 id_frame[i] = cpu_to_le32(mvs_read_port_cfg_data(mvi, port_id)); 769 mv_dprintk("94xx phy %d atta frame %d %x.\n", 770 port_id + mvi->id * mvi->chip->n_phy, i, id_frame[i]); 771 } 772 memcpy(id, id_frame, 28); 773 } 774 775 static u32 mvs_94xx_make_dev_info(struct sas_identify_frame *id) 776 { 777 u32 att_dev_info = 0; 778 779 att_dev_info |= id->dev_type; 780 if (id->stp_iport) 781 att_dev_info |= PORT_DEV_STP_INIT; 782 if (id->smp_iport) 783 att_dev_info |= PORT_DEV_SMP_INIT; 784 if (id->ssp_iport) 785 att_dev_info |= PORT_DEV_SSP_INIT; 786 if (id->stp_tport) 787 att_dev_info |= PORT_DEV_STP_TRGT; 788 if (id->smp_tport) 789 att_dev_info |= PORT_DEV_SMP_TRGT; 790 if (id->ssp_tport) 791 att_dev_info |= PORT_DEV_SSP_TRGT; 792 793 att_dev_info |= (u32)id->phy_id<<24; 794 return att_dev_info; 795 } 796 797 static u32 mvs_94xx_make_att_info(struct sas_identify_frame *id) 798 { 799 return mvs_94xx_make_dev_info(id); 800 } 801 802 static void mvs_94xx_fix_phy_info(struct mvs_info *mvi, int i, 803 struct sas_identify_frame *id) 804 { 805 struct mvs_phy *phy = &mvi->phy[i]; 806 struct asd_sas_phy *sas_phy = &phy->sas_phy; 807 mv_dprintk("get all reg link rate is 0x%x\n", phy->phy_status); 808 sas_phy->linkrate = 809 (phy->phy_status & PHY_NEG_SPP_PHYS_LINK_RATE_MASK) >> 810 PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET; 811 sas_phy->linkrate += 0x8; 812 mv_dprintk("get link rate is %d\n", sas_phy->linkrate); 813 phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS; 814 phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS; 815 mvs_94xx_get_dev_identify_frame(mvi, i, id); 816 phy->dev_info = mvs_94xx_make_dev_info(id); 817 818 if (phy->phy_type & PORT_TYPE_SAS) { 819 mvs_94xx_get_att_identify_frame(mvi, i, id); 820 phy->att_dev_info = mvs_94xx_make_att_info(id); 821 phy->att_dev_sas_addr = *(u64 *)id->sas_addr; 822 } else { 823 phy->att_dev_info = PORT_DEV_STP_TRGT | 1; 824 } 825 826 } 827 828 void mvs_94xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id, 829 struct sas_phy_linkrates *rates) 830 { 831 u32 lrmax = 0; 832 u32 tmp; 833 834 tmp = mvs_read_phy_ctl(mvi, phy_id); 835 lrmax = (rates->maximum_linkrate - SAS_LINK_RATE_1_5_GBPS) << 12; 836 837 if (lrmax) { 838 tmp &= ~(0x3 << 12); 839 tmp |= lrmax; 840 } 841 mvs_write_phy_ctl(mvi, phy_id, tmp); 842 mvs_94xx_phy_reset(mvi, phy_id, PHY_RST_HARD); 843 } 844 845 static void mvs_94xx_clear_active_cmds(struct mvs_info *mvi) 846 { 847 u32 tmp; 848 void __iomem *regs = mvi->regs; 849 tmp = mr32(MVS_STP_REG_SET_0); 850 mw32(MVS_STP_REG_SET_0, 0); 851 mw32(MVS_STP_REG_SET_0, tmp); 852 tmp = mr32(MVS_STP_REG_SET_1); 853 mw32(MVS_STP_REG_SET_1, 0); 854 mw32(MVS_STP_REG_SET_1, tmp); 855 } 856 857 858 u32 mvs_94xx_spi_read_data(struct mvs_info *mvi) 859 { 860 void __iomem *regs = mvi->regs_ex - 0x10200; 861 return mr32(SPI_RD_DATA_REG_94XX); 862 } 863 864 void mvs_94xx_spi_write_data(struct mvs_info *mvi, u32 data) 865 { 866 void __iomem *regs = mvi->regs_ex - 0x10200; 867 mw32(SPI_RD_DATA_REG_94XX, data); 868 } 869 870 871 int mvs_94xx_spi_buildcmd(struct mvs_info *mvi, 872 u32 *dwCmd, 873 u8 cmd, 874 u8 read, 875 u8 length, 876 u32 addr 877 ) 878 { 879 void __iomem *regs = mvi->regs_ex - 0x10200; 880 u32 dwTmp; 881 882 dwTmp = ((u32)cmd << 8) | ((u32)length << 4); 883 if (read) 884 dwTmp |= SPI_CTRL_READ_94XX; 885 886 if (addr != MV_MAX_U32) { 887 mw32(SPI_ADDR_REG_94XX, (addr & 0x0003FFFFL)); 888 dwTmp |= SPI_ADDR_VLD_94XX; 889 } 890 891 *dwCmd = dwTmp; 892 return 0; 893 } 894 895 896 int mvs_94xx_spi_issuecmd(struct mvs_info *mvi, u32 cmd) 897 { 898 void __iomem *regs = mvi->regs_ex - 0x10200; 899 mw32(SPI_CTRL_REG_94XX, cmd | SPI_CTRL_SpiStart_94XX); 900 901 return 0; 902 } 903 904 int mvs_94xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout) 905 { 906 void __iomem *regs = mvi->regs_ex - 0x10200; 907 u32 i, dwTmp; 908 909 for (i = 0; i < timeout; i++) { 910 dwTmp = mr32(SPI_CTRL_REG_94XX); 911 if (!(dwTmp & SPI_CTRL_SpiStart_94XX)) 912 return 0; 913 msleep(10); 914 } 915 916 return -1; 917 } 918 919 void mvs_94xx_fix_dma(struct mvs_info *mvi, u32 phy_mask, 920 int buf_len, int from, void *prd) 921 { 922 int i; 923 struct mvs_prd *buf_prd = prd; 924 dma_addr_t buf_dma; 925 struct mvs_prd_imt im_len; 926 927 *(u32 *)&im_len = 0; 928 buf_prd += from; 929 930 #define PRD_CHAINED_ENTRY 0x01 931 if ((mvi->pdev->revision == VANIR_A0_REV) || 932 (mvi->pdev->revision == VANIR_B0_REV)) 933 buf_dma = (phy_mask <= 0x08) ? 934 mvi->bulk_buffer_dma : mvi->bulk_buffer_dma1; 935 else 936 return; 937 938 for (i = from; i < MAX_SG_ENTRY; i++, ++buf_prd) { 939 if (i == MAX_SG_ENTRY - 1) { 940 buf_prd->addr = cpu_to_le64(virt_to_phys(buf_prd - 1)); 941 im_len.len = 2; 942 im_len.misc_ctl = PRD_CHAINED_ENTRY; 943 } else { 944 buf_prd->addr = cpu_to_le64(buf_dma); 945 im_len.len = buf_len; 946 } 947 buf_prd->im_len = cpu_to_le32(*(u32 *)&im_len); 948 } 949 } 950 951 static void mvs_94xx_tune_interrupt(struct mvs_info *mvi, u32 time) 952 { 953 void __iomem *regs = mvi->regs; 954 u32 tmp = 0; 955 /* 956 * the max count is 0x1ff, while our max slot is 0x200, 957 * it will make count 0. 958 */ 959 if (time == 0) { 960 mw32(MVS_INT_COAL, 0); 961 mw32(MVS_INT_COAL_TMOUT, 0x10000); 962 } else { 963 if (MVS_CHIP_SLOT_SZ > 0x1ff) 964 mw32(MVS_INT_COAL, 0x1ff|COAL_EN); 965 else 966 mw32(MVS_INT_COAL, MVS_CHIP_SLOT_SZ|COAL_EN); 967 968 tmp = 0x10000 | time; 969 mw32(MVS_INT_COAL_TMOUT, tmp); 970 } 971 972 } 973 974 const struct mvs_dispatch mvs_94xx_dispatch = { 975 "mv94xx", 976 mvs_94xx_init, 977 NULL, 978 mvs_94xx_ioremap, 979 mvs_94xx_iounmap, 980 mvs_94xx_isr, 981 mvs_94xx_isr_status, 982 mvs_94xx_interrupt_enable, 983 mvs_94xx_interrupt_disable, 984 mvs_read_phy_ctl, 985 mvs_write_phy_ctl, 986 mvs_read_port_cfg_data, 987 mvs_write_port_cfg_data, 988 mvs_write_port_cfg_addr, 989 mvs_read_port_vsr_data, 990 mvs_write_port_vsr_data, 991 mvs_write_port_vsr_addr, 992 mvs_read_port_irq_stat, 993 mvs_write_port_irq_stat, 994 mvs_read_port_irq_mask, 995 mvs_write_port_irq_mask, 996 mvs_94xx_command_active, 997 mvs_94xx_clear_srs_irq, 998 mvs_94xx_issue_stop, 999 mvs_start_delivery, 1000 mvs_rx_update, 1001 mvs_int_full, 1002 mvs_94xx_assign_reg_set, 1003 mvs_94xx_free_reg_set, 1004 mvs_get_prd_size, 1005 mvs_get_prd_count, 1006 mvs_94xx_make_prd, 1007 mvs_94xx_detect_porttype, 1008 mvs_94xx_oob_done, 1009 mvs_94xx_fix_phy_info, 1010 NULL, 1011 mvs_94xx_phy_set_link_rate, 1012 mvs_hw_max_link_rate, 1013 mvs_94xx_phy_disable, 1014 mvs_94xx_phy_enable, 1015 mvs_94xx_phy_reset, 1016 NULL, 1017 mvs_94xx_clear_active_cmds, 1018 mvs_94xx_spi_read_data, 1019 mvs_94xx_spi_write_data, 1020 mvs_94xx_spi_buildcmd, 1021 mvs_94xx_spi_issuecmd, 1022 mvs_94xx_spi_waitdataready, 1023 mvs_94xx_fix_dma, 1024 mvs_94xx_tune_interrupt, 1025 mvs_94xx_non_spec_ncq_error, 1026 }; 1027 1028