1 /* 2 * This is the Fusion MPT base driver providing common API layer interface 3 * for access to MPT (Message Passing Technology) firmware. 4 * 5 * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.h 6 * Copyright (C) 2012-2014 LSI Corporation 7 * Copyright (C) 2013-2014 Avago Technologies 8 * (mailto: MPT-FusionLinux.pdl@avagotech.com) 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 2 13 * of the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * NO WARRANTY 21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR 22 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT 23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, 24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is 25 * solely responsible for determining the appropriateness of using and 26 * distributing the Program and assumes all risks associated with its 27 * exercise of rights under this Agreement, including but not limited to 28 * the risks and costs of program errors, damage to or loss of data, 29 * programs or equipment, and unavailability or interruption of operations. 30 31 * DISCLAIMER OF LIABILITY 32 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY 33 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND 35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 36 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 37 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED 38 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES 39 40 * You should have received a copy of the GNU General Public License 41 * along with this program; if not, write to the Free Software 42 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, 43 * USA. 44 */ 45 46 #ifndef MPT3SAS_BASE_H_INCLUDED 47 #define MPT3SAS_BASE_H_INCLUDED 48 49 #include "mpi/mpi2_type.h" 50 #include "mpi/mpi2.h" 51 #include "mpi/mpi2_ioc.h" 52 #include "mpi/mpi2_cnfg.h" 53 #include "mpi/mpi2_init.h" 54 #include "mpi/mpi2_raid.h" 55 #include "mpi/mpi2_tool.h" 56 #include "mpi/mpi2_sas.h" 57 #include "mpi/mpi2_pci.h" 58 #include "mpi/mpi2_image.h" 59 60 #include <scsi/scsi.h> 61 #include <scsi/scsi_cmnd.h> 62 #include <scsi/scsi_device.h> 63 #include <scsi/scsi_host.h> 64 #include <scsi/scsi_tcq.h> 65 #include <scsi/scsi_transport_sas.h> 66 #include <scsi/scsi_dbg.h> 67 #include <scsi/scsi_eh.h> 68 #include <linux/pci.h> 69 #include <linux/poll.h> 70 #include <linux/irq_poll.h> 71 72 #include "mpt3sas_debug.h" 73 #include "mpt3sas_trigger_diag.h" 74 #include "mpt3sas_trigger_pages.h" 75 76 /* driver versioning info */ 77 #define MPT3SAS_DRIVER_NAME "mpt3sas" 78 #define MPT3SAS_AUTHOR "Avago Technologies <MPT-FusionLinux.pdl@avagotech.com>" 79 #define MPT3SAS_DESCRIPTION "LSI MPT Fusion SAS 3.0 Device Driver" 80 #define MPT3SAS_DRIVER_VERSION "36.100.00.00" 81 #define MPT3SAS_MAJOR_VERSION 36 82 #define MPT3SAS_MINOR_VERSION 100 83 #define MPT3SAS_BUILD_VERSION 0 84 #define MPT3SAS_RELEASE_VERSION 00 85 86 #define MPT2SAS_DRIVER_NAME "mpt2sas" 87 #define MPT2SAS_DESCRIPTION "LSI MPT Fusion SAS 2.0 Device Driver" 88 #define MPT2SAS_DRIVER_VERSION "20.102.00.00" 89 #define MPT2SAS_MAJOR_VERSION 20 90 #define MPT2SAS_MINOR_VERSION 102 91 #define MPT2SAS_BUILD_VERSION 0 92 #define MPT2SAS_RELEASE_VERSION 00 93 94 /* CoreDump: Default timeout */ 95 #define MPT3SAS_DEFAULT_COREDUMP_TIMEOUT_SECONDS (15) /*15 seconds*/ 96 #define MPT3SAS_COREDUMP_LOOP_DONE (0xFF) 97 #define MPT3SAS_TIMESYNC_TIMEOUT_SECONDS (10) /* 10 seconds */ 98 #define MPT3SAS_TIMESYNC_UPDATE_INTERVAL (900) /* 15 minutes */ 99 #define MPT3SAS_TIMESYNC_UNIT_MASK (0x80) /* bit 7 */ 100 #define MPT3SAS_TIMESYNC_MASK (0x7F) /* 0 - 6 bits */ 101 #define SECONDS_PER_MIN (60) 102 #define SECONDS_PER_HOUR (3600) 103 #define MPT3SAS_COREDUMP_LOOP_DONE (0xFF) 104 #define MPI26_SET_IOC_PARAMETER_SYNC_TIMESTAMP (0x81) 105 106 /* 107 * Set MPT3SAS_SG_DEPTH value based on user input. 108 */ 109 #define MPT_MAX_PHYS_SEGMENTS SG_CHUNK_SIZE 110 #define MPT_MIN_PHYS_SEGMENTS 16 111 #define MPT_KDUMP_MIN_PHYS_SEGMENTS 32 112 113 #define MCPU_MAX_CHAINS_PER_IO 3 114 115 #ifdef CONFIG_SCSI_MPT3SAS_MAX_SGE 116 #define MPT3SAS_SG_DEPTH CONFIG_SCSI_MPT3SAS_MAX_SGE 117 #else 118 #define MPT3SAS_SG_DEPTH MPT_MAX_PHYS_SEGMENTS 119 #endif 120 121 #ifdef CONFIG_SCSI_MPT2SAS_MAX_SGE 122 #define MPT2SAS_SG_DEPTH CONFIG_SCSI_MPT2SAS_MAX_SGE 123 #else 124 #define MPT2SAS_SG_DEPTH MPT_MAX_PHYS_SEGMENTS 125 #endif 126 127 /* 128 * Generic Defines 129 */ 130 #define MPT3SAS_SATA_QUEUE_DEPTH 32 131 #define MPT3SAS_SAS_QUEUE_DEPTH 254 132 #define MPT3SAS_RAID_QUEUE_DEPTH 128 133 #define MPT3SAS_KDUMP_SCSI_IO_DEPTH 200 134 135 #define MPT3SAS_RAID_MAX_SECTORS 8192 136 #define MPT3SAS_HOST_PAGE_SIZE_4K 12 137 #define MPT3SAS_NVME_QUEUE_DEPTH 128 138 #define MPT_NAME_LENGTH 32 /* generic length of strings */ 139 #define MPT_STRING_LENGTH 64 140 #define MPI_FRAME_START_OFFSET 256 141 #define REPLY_FREE_POOL_SIZE 512 /*(32 maxcredix *4)*(4 times)*/ 142 143 #define MPT_MAX_CALLBACKS 32 144 145 #define INTERNAL_CMDS_COUNT 10 /* reserved cmds */ 146 /* reserved for issuing internally framed scsi io cmds */ 147 #define INTERNAL_SCSIIO_CMDS_COUNT 3 148 149 #define MPI3_HIM_MASK 0xFFFFFFFF /* mask every bit*/ 150 151 #define MPT3SAS_INVALID_DEVICE_HANDLE 0xFFFF 152 153 #define MAX_CHAIN_ELEMT_SZ 16 154 #define DEFAULT_NUM_FWCHAIN_ELEMTS 8 155 156 #define IO_UNIT_CONTROL_SHUTDOWN_TIMEOUT 6 157 #define FW_IMG_HDR_READ_TIMEOUT 15 158 159 #define IOC_OPERATIONAL_WAIT_COUNT 10 160 161 /* 162 * NVMe defines 163 */ 164 #define NVME_PRP_SIZE 8 /* PRP size */ 165 #define NVME_ERROR_RESPONSE_SIZE 16 /* Max NVME Error Response */ 166 #define NVME_TASK_ABORT_MIN_TIMEOUT 6 167 #define NVME_TASK_ABORT_MAX_TIMEOUT 60 168 #define NVME_TASK_MNGT_CUSTOM_MASK (0x0010) 169 #define NVME_PRP_PAGE_SIZE 4096 /* Page size */ 170 171 struct mpt3sas_nvme_cmd { 172 u8 rsvd[24]; 173 __le64 prp1; 174 __le64 prp2; 175 }; 176 177 /* 178 * logging format 179 */ 180 #define ioc_err(ioc, fmt, ...) \ 181 pr_err("%s: " fmt, (ioc)->name, ##__VA_ARGS__) 182 #define ioc_notice(ioc, fmt, ...) \ 183 pr_notice("%s: " fmt, (ioc)->name, ##__VA_ARGS__) 184 #define ioc_warn(ioc, fmt, ...) \ 185 pr_warn("%s: " fmt, (ioc)->name, ##__VA_ARGS__) 186 #define ioc_info(ioc, fmt, ...) \ 187 pr_info("%s: " fmt, (ioc)->name, ##__VA_ARGS__) 188 189 /* 190 * WarpDrive Specific Log codes 191 */ 192 193 #define MPT2_WARPDRIVE_LOGENTRY (0x8002) 194 #define MPT2_WARPDRIVE_LC_SSDT (0x41) 195 #define MPT2_WARPDRIVE_LC_SSDLW (0x43) 196 #define MPT2_WARPDRIVE_LC_SSDLF (0x44) 197 #define MPT2_WARPDRIVE_LC_BRMF (0x4D) 198 199 /* 200 * per target private data 201 */ 202 #define MPT_TARGET_FLAGS_RAID_COMPONENT 0x01 203 #define MPT_TARGET_FLAGS_VOLUME 0x02 204 #define MPT_TARGET_FLAGS_DELETED 0x04 205 #define MPT_TARGET_FASTPATH_IO 0x08 206 #define MPT_TARGET_FLAGS_PCIE_DEVICE 0x10 207 208 #define SAS2_PCI_DEVICE_B0_REVISION (0x01) 209 #define SAS3_PCI_DEVICE_C0_REVISION (0x02) 210 211 /* Atlas PCIe Switch Management Port */ 212 #define MPI26_ATLAS_PCIe_SWITCH_DEVID (0x00B2) 213 214 /* 215 * Intel HBA branding 216 */ 217 #define MPT2SAS_INTEL_RMS25JB080_BRANDING \ 218 "Intel(R) Integrated RAID Module RMS25JB080" 219 #define MPT2SAS_INTEL_RMS25JB040_BRANDING \ 220 "Intel(R) Integrated RAID Module RMS25JB040" 221 #define MPT2SAS_INTEL_RMS25KB080_BRANDING \ 222 "Intel(R) Integrated RAID Module RMS25KB080" 223 #define MPT2SAS_INTEL_RMS25KB040_BRANDING \ 224 "Intel(R) Integrated RAID Module RMS25KB040" 225 #define MPT2SAS_INTEL_RMS25LB040_BRANDING \ 226 "Intel(R) Integrated RAID Module RMS25LB040" 227 #define MPT2SAS_INTEL_RMS25LB080_BRANDING \ 228 "Intel(R) Integrated RAID Module RMS25LB080" 229 #define MPT2SAS_INTEL_RMS2LL080_BRANDING \ 230 "Intel Integrated RAID Module RMS2LL080" 231 #define MPT2SAS_INTEL_RMS2LL040_BRANDING \ 232 "Intel Integrated RAID Module RMS2LL040" 233 #define MPT2SAS_INTEL_RS25GB008_BRANDING \ 234 "Intel(R) RAID Controller RS25GB008" 235 #define MPT2SAS_INTEL_SSD910_BRANDING \ 236 "Intel(R) SSD 910 Series" 237 238 #define MPT3SAS_INTEL_RMS3JC080_BRANDING \ 239 "Intel(R) Integrated RAID Module RMS3JC080" 240 #define MPT3SAS_INTEL_RS3GC008_BRANDING \ 241 "Intel(R) RAID Controller RS3GC008" 242 #define MPT3SAS_INTEL_RS3FC044_BRANDING \ 243 "Intel(R) RAID Controller RS3FC044" 244 #define MPT3SAS_INTEL_RS3UC080_BRANDING \ 245 "Intel(R) RAID Controller RS3UC080" 246 247 /* 248 * Intel HBA SSDIDs 249 */ 250 #define MPT2SAS_INTEL_RMS25JB080_SSDID 0x3516 251 #define MPT2SAS_INTEL_RMS25JB040_SSDID 0x3517 252 #define MPT2SAS_INTEL_RMS25KB080_SSDID 0x3518 253 #define MPT2SAS_INTEL_RMS25KB040_SSDID 0x3519 254 #define MPT2SAS_INTEL_RMS25LB040_SSDID 0x351A 255 #define MPT2SAS_INTEL_RMS25LB080_SSDID 0x351B 256 #define MPT2SAS_INTEL_RMS2LL080_SSDID 0x350E 257 #define MPT2SAS_INTEL_RMS2LL040_SSDID 0x350F 258 #define MPT2SAS_INTEL_RS25GB008_SSDID 0x3000 259 #define MPT2SAS_INTEL_SSD910_SSDID 0x3700 260 261 #define MPT3SAS_INTEL_RMS3JC080_SSDID 0x3521 262 #define MPT3SAS_INTEL_RS3GC008_SSDID 0x3522 263 #define MPT3SAS_INTEL_RS3FC044_SSDID 0x3523 264 #define MPT3SAS_INTEL_RS3UC080_SSDID 0x3524 265 266 /* 267 * Dell HBA branding 268 */ 269 #define MPT2SAS_DELL_BRANDING_SIZE 32 270 271 #define MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING "Dell 6Gbps SAS HBA" 272 #define MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING "Dell PERC H200 Adapter" 273 #define MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING "Dell PERC H200 Integrated" 274 #define MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING "Dell PERC H200 Modular" 275 #define MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING "Dell PERC H200 Embedded" 276 #define MPT2SAS_DELL_PERC_H200_BRANDING "Dell PERC H200" 277 #define MPT2SAS_DELL_6GBPS_SAS_BRANDING "Dell 6Gbps SAS" 278 279 #define MPT3SAS_DELL_12G_HBA_BRANDING \ 280 "Dell 12Gbps HBA" 281 282 /* 283 * Dell HBA SSDIDs 284 */ 285 #define MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID 0x1F1C 286 #define MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID 0x1F1D 287 #define MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID 0x1F1E 288 #define MPT2SAS_DELL_PERC_H200_MODULAR_SSDID 0x1F1F 289 #define MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID 0x1F20 290 #define MPT2SAS_DELL_PERC_H200_SSDID 0x1F21 291 #define MPT2SAS_DELL_6GBPS_SAS_SSDID 0x1F22 292 293 #define MPT3SAS_DELL_12G_HBA_SSDID 0x1F46 294 295 /* 296 * Cisco HBA branding 297 */ 298 #define MPT3SAS_CISCO_12G_8E_HBA_BRANDING \ 299 "Cisco 9300-8E 12G SAS HBA" 300 #define MPT3SAS_CISCO_12G_8I_HBA_BRANDING \ 301 "Cisco 9300-8i 12G SAS HBA" 302 #define MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING \ 303 "Cisco 12G Modular SAS Pass through Controller" 304 #define MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING \ 305 "UCS C3X60 12G SAS Pass through Controller" 306 /* 307 * Cisco HBA SSSDIDs 308 */ 309 #define MPT3SAS_CISCO_12G_8E_HBA_SSDID 0x14C 310 #define MPT3SAS_CISCO_12G_8I_HBA_SSDID 0x154 311 #define MPT3SAS_CISCO_12G_AVILA_HBA_SSDID 0x155 312 #define MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID 0x156 313 314 /* 315 * status bits for ioc->diag_buffer_status 316 */ 317 #define MPT3_DIAG_BUFFER_IS_REGISTERED (0x01) 318 #define MPT3_DIAG_BUFFER_IS_RELEASED (0x02) 319 #define MPT3_DIAG_BUFFER_IS_DIAG_RESET (0x04) 320 #define MPT3_DIAG_BUFFER_IS_DRIVER_ALLOCATED (0x08) 321 #define MPT3_DIAG_BUFFER_IS_APP_OWNED (0x10) 322 323 /* 324 * HP HBA branding 325 */ 326 #define MPT2SAS_HP_3PAR_SSVID 0x1590 327 328 #define MPT2SAS_HP_2_4_INTERNAL_BRANDING \ 329 "HP H220 Host Bus Adapter" 330 #define MPT2SAS_HP_2_4_EXTERNAL_BRANDING \ 331 "HP H221 Host Bus Adapter" 332 #define MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING \ 333 "HP H222 Host Bus Adapter" 334 #define MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING \ 335 "HP H220i Host Bus Adapter" 336 #define MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING \ 337 "HP H210i Host Bus Adapter" 338 339 /* 340 * HO HBA SSDIDs 341 */ 342 #define MPT2SAS_HP_2_4_INTERNAL_SSDID 0x0041 343 #define MPT2SAS_HP_2_4_EXTERNAL_SSDID 0x0042 344 #define MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID 0x0043 345 #define MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID 0x0044 346 #define MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID 0x0046 347 348 /* 349 * Combined Reply Queue constants, 350 * There are twelve Supplemental Reply Post Host Index Registers 351 * and each register is at offset 0x10 bytes from the previous one. 352 */ 353 #define MAX_COMBINED_MSIX_VECTORS(gen35) ((gen35 == 1) ? 16 : 8) 354 #define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT_G3 12 355 #define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT_G35 16 356 #define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET (0x10) 357 358 /* OEM Identifiers */ 359 #define MFG10_OEM_ID_INVALID (0x00000000) 360 #define MFG10_OEM_ID_DELL (0x00000001) 361 #define MFG10_OEM_ID_FSC (0x00000002) 362 #define MFG10_OEM_ID_SUN (0x00000003) 363 #define MFG10_OEM_ID_IBM (0x00000004) 364 365 /* GENERIC Flags 0*/ 366 #define MFG10_GF0_OCE_DISABLED (0x00000001) 367 #define MFG10_GF0_R1E_DRIVE_COUNT (0x00000002) 368 #define MFG10_GF0_R10_DISPLAY (0x00000004) 369 #define MFG10_GF0_SSD_DATA_SCRUB_DISABLE (0x00000008) 370 #define MFG10_GF0_SINGLE_DRIVE_R0 (0x00000010) 371 372 #define VIRTUAL_IO_FAILED_RETRY (0x32010081) 373 374 /* High IOPs definitions */ 375 #define MPT3SAS_DEVICE_HIGH_IOPS_DEPTH 8 376 #define MPT3SAS_HIGH_IOPS_REPLY_QUEUES 8 377 #define MPT3SAS_HIGH_IOPS_BATCH_COUNT 16 378 #define MPT3SAS_GEN35_MAX_MSIX_QUEUES 128 379 #define RDPQ_MAX_INDEX_IN_ONE_CHUNK 16 380 381 /* OEM Specific Flags will come from OEM specific header files */ 382 struct Mpi2ManufacturingPage10_t { 383 MPI2_CONFIG_PAGE_HEADER Header; /* 00h */ 384 U8 OEMIdentifier; /* 04h */ 385 U8 Reserved1; /* 05h */ 386 U16 Reserved2; /* 08h */ 387 U32 Reserved3; /* 0Ch */ 388 U32 GenericFlags0; /* 10h */ 389 U32 GenericFlags1; /* 14h */ 390 U32 Reserved4; /* 18h */ 391 U32 OEMSpecificFlags0; /* 1Ch */ 392 U32 OEMSpecificFlags1; /* 20h */ 393 U32 Reserved5[18]; /* 24h - 60h*/ 394 }; 395 396 397 /* Miscellaneous options */ 398 struct Mpi2ManufacturingPage11_t { 399 MPI2_CONFIG_PAGE_HEADER Header; /* 00h */ 400 __le32 Reserved1; /* 04h */ 401 u8 Reserved2; /* 08h */ 402 u8 EEDPTagMode; /* 09h */ 403 u8 Reserved3; /* 0Ah */ 404 u8 Reserved4; /* 0Bh */ 405 __le32 Reserved5[8]; /* 0Ch-2Ch */ 406 u16 AddlFlags2; /* 2Ch */ 407 u8 AddlFlags3; /* 2Eh */ 408 u8 Reserved6; /* 2Fh */ 409 __le32 Reserved7[7]; /* 30h - 4Bh */ 410 u8 NVMeAbortTO; /* 4Ch */ 411 u8 NumPerDevEvents; /* 4Dh */ 412 u8 HostTraceBufferDecrementSizeKB; /* 4Eh */ 413 u8 HostTraceBufferFlags; /* 4Fh */ 414 u16 HostTraceBufferMaxSizeKB; /* 50h */ 415 u16 HostTraceBufferMinSizeKB; /* 52h */ 416 u8 CoreDumpTOSec; /* 54h */ 417 u8 TimeSyncInterval; /* 55h */ 418 u16 Reserved9; /* 56h */ 419 __le32 Reserved10; /* 58h */ 420 }; 421 422 /** 423 * struct MPT3SAS_TARGET - starget private hostdata 424 * @starget: starget object 425 * @sas_address: target sas address 426 * @raid_device: raid_device pointer to access volume data 427 * @handle: device handle 428 * @num_luns: number luns 429 * @flags: MPT_TARGET_FLAGS_XXX flags 430 * @deleted: target flaged for deletion 431 * @tm_busy: target is busy with TM request. 432 * @port: hba port entry containing target's port number info 433 * @sas_dev: The sas_device associated with this target 434 * @pcie_dev: The pcie device associated with this target 435 */ 436 struct MPT3SAS_TARGET { 437 struct scsi_target *starget; 438 u64 sas_address; 439 struct _raid_device *raid_device; 440 u16 handle; 441 int num_luns; 442 u32 flags; 443 u8 deleted; 444 u8 tm_busy; 445 struct hba_port *port; 446 struct _sas_device *sas_dev; 447 struct _pcie_device *pcie_dev; 448 }; 449 450 451 /* 452 * per device private data 453 */ 454 #define MPT_DEVICE_FLAGS_INIT 0x01 455 456 #define MFG_PAGE10_HIDE_SSDS_MASK (0x00000003) 457 #define MFG_PAGE10_HIDE_ALL_DISKS (0x00) 458 #define MFG_PAGE10_EXPOSE_ALL_DISKS (0x01) 459 #define MFG_PAGE10_HIDE_IF_VOL_PRESENT (0x02) 460 461 /** 462 * struct MPT3SAS_DEVICE - sdev private hostdata 463 * @sas_target: starget private hostdata 464 * @lun: lun number 465 * @flags: MPT_DEVICE_XXX flags 466 * @configured_lun: lun is configured 467 * @block: device is in SDEV_BLOCK state 468 * @tlr_snoop_check: flag used in determining whether to disable TLR 469 * @eedp_enable: eedp support enable bit 470 * @eedp_type: 0(type_1), 1(type_2), 2(type_3) 471 * @eedp_block_length: block size 472 * @ata_command_pending: SATL passthrough outstanding for device 473 */ 474 struct MPT3SAS_DEVICE { 475 struct MPT3SAS_TARGET *sas_target; 476 unsigned int lun; 477 u32 flags; 478 u8 configured_lun; 479 u8 block; 480 u8 tlr_snoop_check; 481 u8 ignore_delay_remove; 482 /* Iopriority Command Handling */ 483 u8 ncq_prio_enable; 484 /* 485 * Bug workaround for SATL handling: the mpt2/3sas firmware 486 * doesn't return BUSY or TASK_SET_FULL for subsequent 487 * commands while a SATL pass through is in operation as the 488 * spec requires, it simply does nothing with them until the 489 * pass through completes, causing them possibly to timeout if 490 * the passthrough is a long executing command (like format or 491 * secure erase). This variable allows us to do the right 492 * thing while a SATL command is pending. 493 */ 494 unsigned long ata_command_pending; 495 496 }; 497 498 #define MPT3_CMD_NOT_USED 0x8000 /* free */ 499 #define MPT3_CMD_COMPLETE 0x0001 /* completed */ 500 #define MPT3_CMD_PENDING 0x0002 /* pending */ 501 #define MPT3_CMD_REPLY_VALID 0x0004 /* reply is valid */ 502 #define MPT3_CMD_RESET 0x0008 /* host reset dropped the command */ 503 504 /** 505 * struct _internal_cmd - internal commands struct 506 * @mutex: mutex 507 * @done: completion 508 * @reply: reply message pointer 509 * @sense: sense data 510 * @status: MPT3_CMD_XXX status 511 * @smid: system message id 512 */ 513 struct _internal_cmd { 514 struct mutex mutex; 515 struct completion done; 516 void *reply; 517 void *sense; 518 u16 status; 519 u16 smid; 520 }; 521 522 523 524 /** 525 * struct _sas_device - attached device information 526 * @list: sas device list 527 * @starget: starget object 528 * @sas_address: device sas address 529 * @device_name: retrieved from the SAS IDENTIFY frame. 530 * @handle: device handle 531 * @sas_address_parent: sas address of parent expander or sas host 532 * @enclosure_handle: enclosure handle 533 * @enclosure_logical_id: enclosure logical identifier 534 * @volume_handle: volume handle (valid when hidden raid member) 535 * @volume_wwid: volume unique identifier 536 * @device_info: bitfield provides detailed info about the device 537 * @id: target id 538 * @channel: target channel 539 * @slot: number number 540 * @phy: phy identifier provided in sas device page 0 541 * @responding: used in _scsih_sas_device_mark_responding 542 * @fast_path: fast path feature enable bit 543 * @pfa_led_on: flag for PFA LED status 544 * @pend_sas_rphy_add: flag to check if device is in sas_rphy_add() 545 * addition routine. 546 * @chassis_slot: chassis slot 547 * @is_chassis_slot_valid: chassis slot valid or not 548 * @port: hba port entry containing device's port number info 549 * @rphy: device's sas_rphy address used to identify this device structure in 550 * target_alloc callback function 551 */ 552 struct _sas_device { 553 struct list_head list; 554 struct scsi_target *starget; 555 u64 sas_address; 556 u64 device_name; 557 u16 handle; 558 u64 sas_address_parent; 559 u16 enclosure_handle; 560 u64 enclosure_logical_id; 561 u16 volume_handle; 562 u64 volume_wwid; 563 u32 device_info; 564 int id; 565 int channel; 566 u16 slot; 567 u8 phy; 568 u8 responding; 569 u8 fast_path; 570 u8 pfa_led_on; 571 u8 pend_sas_rphy_add; 572 u8 enclosure_level; 573 u8 chassis_slot; 574 u8 is_chassis_slot_valid; 575 u8 connector_name[5]; 576 struct kref refcount; 577 struct hba_port *port; 578 struct sas_rphy *rphy; 579 }; 580 581 static inline void sas_device_get(struct _sas_device *s) 582 { 583 kref_get(&s->refcount); 584 } 585 586 static inline void sas_device_free(struct kref *r) 587 { 588 kfree(container_of(r, struct _sas_device, refcount)); 589 } 590 591 static inline void sas_device_put(struct _sas_device *s) 592 { 593 kref_put(&s->refcount, sas_device_free); 594 } 595 596 /* 597 * struct _pcie_device - attached PCIe device information 598 * @list: pcie device list 599 * @starget: starget object 600 * @wwid: device WWID 601 * @handle: device handle 602 * @device_info: bitfield provides detailed info about the device 603 * @id: target id 604 * @channel: target channel 605 * @slot: slot number 606 * @port_num: port number 607 * @responding: used in _scsih_pcie_device_mark_responding 608 * @fast_path: fast path feature enable bit 609 * @nvme_mdts: MaximumDataTransferSize from PCIe Device Page 2 for 610 * NVMe device only 611 * @enclosure_handle: enclosure handle 612 * @enclosure_logical_id: enclosure logical identifier 613 * @enclosure_level: The level of device's enclosure from the controller 614 * @connector_name: ASCII value of the Connector's name 615 * @serial_number: pointer of serial number string allocated runtime 616 * @access_status: Device's Access Status 617 * @shutdown_latency: NVMe device's RTD3 Entry Latency 618 * @refcount: reference count for deletion 619 */ 620 struct _pcie_device { 621 struct list_head list; 622 struct scsi_target *starget; 623 u64 wwid; 624 u16 handle; 625 u32 device_info; 626 int id; 627 int channel; 628 u16 slot; 629 u8 port_num; 630 u8 responding; 631 u8 fast_path; 632 u32 nvme_mdts; 633 u16 enclosure_handle; 634 u64 enclosure_logical_id; 635 u8 enclosure_level; 636 u8 connector_name[4]; 637 u8 *serial_number; 638 u8 reset_timeout; 639 u8 access_status; 640 u16 shutdown_latency; 641 struct kref refcount; 642 }; 643 /** 644 * pcie_device_get - Increment the pcie device reference count 645 * 646 * @p: pcie_device object 647 * 648 * When ever this function called it will increment the 649 * reference count of the pcie device for which this function called. 650 * 651 */ 652 static inline void pcie_device_get(struct _pcie_device *p) 653 { 654 kref_get(&p->refcount); 655 } 656 657 /** 658 * pcie_device_free - Release the pcie device object 659 * @r - kref object 660 * 661 * Free's the pcie device object. It will be called when reference count 662 * reaches to zero. 663 */ 664 static inline void pcie_device_free(struct kref *r) 665 { 666 kfree(container_of(r, struct _pcie_device, refcount)); 667 } 668 669 /** 670 * pcie_device_put - Decrement the pcie device reference count 671 * 672 * @p: pcie_device object 673 * 674 * When ever this function called it will decrement the 675 * reference count of the pcie device for which this function called. 676 * 677 * When refernce count reaches to Zero, this will call pcie_device_free to the 678 * pcie_device object. 679 */ 680 static inline void pcie_device_put(struct _pcie_device *p) 681 { 682 kref_put(&p->refcount, pcie_device_free); 683 } 684 /** 685 * struct _raid_device - raid volume link list 686 * @list: sas device list 687 * @starget: starget object 688 * @sdev: scsi device struct (volumes are single lun) 689 * @wwid: unique identifier for the volume 690 * @handle: device handle 691 * @block_size: Block size of the volume 692 * @id: target id 693 * @channel: target channel 694 * @volume_type: the raid level 695 * @device_info: bitfield provides detailed info about the hidden components 696 * @num_pds: number of hidden raid components 697 * @responding: used in _scsih_raid_device_mark_responding 698 * @percent_complete: resync percent complete 699 * @direct_io_enabled: Whether direct io to PDs are allowed or not 700 * @stripe_exponent: X where 2powX is the stripe sz in blocks 701 * @block_exponent: X where 2powX is the block sz in bytes 702 * @max_lba: Maximum number of LBA in the volume 703 * @stripe_sz: Stripe Size of the volume 704 * @device_info: Device info of the volume member disk 705 * @pd_handle: Array of handles of the physical drives for direct I/O in le16 706 */ 707 #define MPT_MAX_WARPDRIVE_PDS 8 708 struct _raid_device { 709 struct list_head list; 710 struct scsi_target *starget; 711 struct scsi_device *sdev; 712 u64 wwid; 713 u16 handle; 714 u16 block_sz; 715 int id; 716 int channel; 717 u8 volume_type; 718 u8 num_pds; 719 u8 responding; 720 u8 percent_complete; 721 u8 direct_io_enabled; 722 u8 stripe_exponent; 723 u8 block_exponent; 724 u64 max_lba; 725 u32 stripe_sz; 726 u32 device_info; 727 u16 pd_handle[MPT_MAX_WARPDRIVE_PDS]; 728 }; 729 730 /** 731 * struct _boot_device - boot device info 732 * 733 * @channel: sas, raid, or pcie channel 734 * @device: holds pointer for struct _sas_device, struct _raid_device or 735 * struct _pcie_device 736 */ 737 struct _boot_device { 738 int channel; 739 void *device; 740 }; 741 742 /** 743 * struct _sas_port - wide/narrow sas port information 744 * @port_list: list of ports belonging to expander 745 * @num_phys: number of phys belonging to this port 746 * @remote_identify: attached device identification 747 * @rphy: sas transport rphy object 748 * @port: sas transport wide/narrow port object 749 * @hba_port: hba port entry containing port's port number info 750 * @phy_list: _sas_phy list objects belonging to this port 751 */ 752 struct _sas_port { 753 struct list_head port_list; 754 u8 num_phys; 755 struct sas_identify remote_identify; 756 struct sas_rphy *rphy; 757 struct sas_port *port; 758 struct hba_port *hba_port; 759 struct list_head phy_list; 760 }; 761 762 /** 763 * struct _sas_phy - phy information 764 * @port_siblings: list of phys belonging to a port 765 * @identify: phy identification 766 * @remote_identify: attached device identification 767 * @phy: sas transport phy object 768 * @phy_id: unique phy id 769 * @handle: device handle for this phy 770 * @attached_handle: device handle for attached device 771 * @phy_belongs_to_port: port has been created for this phy 772 * @port: hba port entry containing port number info 773 */ 774 struct _sas_phy { 775 struct list_head port_siblings; 776 struct sas_identify identify; 777 struct sas_identify remote_identify; 778 struct sas_phy *phy; 779 u8 phy_id; 780 u16 handle; 781 u16 attached_handle; 782 u8 phy_belongs_to_port; 783 u8 hba_vphy; 784 struct hba_port *port; 785 }; 786 787 /** 788 * struct _sas_node - sas_host/expander information 789 * @list: list of expanders 790 * @parent_dev: parent device class 791 * @num_phys: number phys belonging to this sas_host/expander 792 * @sas_address: sas address of this sas_host/expander 793 * @handle: handle for this sas_host/expander 794 * @sas_address_parent: sas address of parent expander or sas host 795 * @enclosure_handle: handle for this a member of an enclosure 796 * @device_info: bitwise defining capabilities of this sas_host/expander 797 * @responding: used in _scsih_expander_device_mark_responding 798 * @phy: a list of phys that make up this sas_host/expander 799 * @sas_port_list: list of ports attached to this sas_host/expander 800 * @port: hba port entry containing node's port number info 801 * @rphy: sas_rphy object of this expander 802 */ 803 struct _sas_node { 804 struct list_head list; 805 struct device *parent_dev; 806 u8 num_phys; 807 u64 sas_address; 808 u16 handle; 809 u64 sas_address_parent; 810 u16 enclosure_handle; 811 u64 enclosure_logical_id; 812 u8 responding; 813 struct hba_port *port; 814 struct _sas_phy *phy; 815 struct list_head sas_port_list; 816 struct sas_rphy *rphy; 817 }; 818 819 /** 820 * struct _enclosure_node - enclosure information 821 * @list: list of enclosures 822 * @pg0: enclosure pg0; 823 */ 824 struct _enclosure_node { 825 struct list_head list; 826 Mpi2SasEnclosurePage0_t pg0; 827 }; 828 829 /** 830 * enum reset_type - reset state 831 * @FORCE_BIG_HAMMER: issue diagnostic reset 832 * @SOFT_RESET: issue message_unit_reset, if fails to to big hammer 833 */ 834 enum reset_type { 835 FORCE_BIG_HAMMER, 836 SOFT_RESET, 837 }; 838 839 /** 840 * struct pcie_sg_list - PCIe SGL buffer (contiguous per I/O) 841 * @pcie_sgl: PCIe native SGL for NVMe devices 842 * @pcie_sgl_dma: physical address 843 */ 844 struct pcie_sg_list { 845 void *pcie_sgl; 846 dma_addr_t pcie_sgl_dma; 847 }; 848 849 /** 850 * struct chain_tracker - firmware chain tracker 851 * @chain_buffer: chain buffer 852 * @chain_buffer_dma: physical address 853 * @tracker_list: list of free request (ioc->free_chain_list) 854 */ 855 struct chain_tracker { 856 void *chain_buffer; 857 dma_addr_t chain_buffer_dma; 858 }; 859 860 struct chain_lookup { 861 struct chain_tracker *chains_per_smid; 862 atomic_t chain_offset; 863 }; 864 865 /** 866 * struct scsiio_tracker - scsi mf request tracker 867 * @smid: system message id 868 * @cb_idx: callback index 869 * @direct_io: To indicate whether I/O is direct (WARPDRIVE) 870 * @chain_list: list of associated firmware chain tracker 871 * @msix_io: IO's msix 872 */ 873 struct scsiio_tracker { 874 u16 smid; 875 struct scsi_cmnd *scmd; 876 u8 cb_idx; 877 u8 direct_io; 878 struct pcie_sg_list pcie_sg_list; 879 struct list_head chain_list; 880 u16 msix_io; 881 }; 882 883 /** 884 * struct request_tracker - firmware request tracker 885 * @smid: system message id 886 * @cb_idx: callback index 887 * @tracker_list: list of free request (ioc->free_list) 888 */ 889 struct request_tracker { 890 u16 smid; 891 u8 cb_idx; 892 struct list_head tracker_list; 893 }; 894 895 /** 896 * struct _tr_list - target reset list 897 * @handle: device handle 898 * @state: state machine 899 */ 900 struct _tr_list { 901 struct list_head list; 902 u16 handle; 903 u16 state; 904 }; 905 906 /** 907 * struct _sc_list - delayed SAS_IO_UNIT_CONTROL message list 908 * @handle: device handle 909 */ 910 struct _sc_list { 911 struct list_head list; 912 u16 handle; 913 }; 914 915 /** 916 * struct _event_ack_list - delayed event acknowledgment list 917 * @Event: Event ID 918 * @EventContext: used to track the event uniquely 919 */ 920 struct _event_ack_list { 921 struct list_head list; 922 U16 Event; 923 U32 EventContext; 924 }; 925 926 /** 927 * struct adapter_reply_queue - the reply queue struct 928 * @ioc: per adapter object 929 * @msix_index: msix index into vector table 930 * @vector: irq vector 931 * @reply_post_host_index: head index in the pool where FW completes IO 932 * @reply_post_free: reply post base virt address 933 * @name: the name registered to request_irq() 934 * @busy: isr is actively processing replies on another cpu 935 * @os_irq: irq number 936 * @irqpoll: irq_poll object 937 * @irq_poll_scheduled: Tells whether irq poll is scheduled or not 938 * @list: this list 939 */ 940 struct adapter_reply_queue { 941 struct MPT3SAS_ADAPTER *ioc; 942 u8 msix_index; 943 u32 reply_post_host_index; 944 Mpi2ReplyDescriptorsUnion_t *reply_post_free; 945 char name[MPT_NAME_LENGTH]; 946 atomic_t busy; 947 u32 os_irq; 948 struct irq_poll irqpoll; 949 bool irq_poll_scheduled; 950 bool irq_line_enable; 951 struct list_head list; 952 }; 953 954 typedef void (*MPT_ADD_SGE)(void *paddr, u32 flags_length, dma_addr_t dma_addr); 955 956 /* SAS3.0 support */ 957 typedef int (*MPT_BUILD_SG_SCMD)(struct MPT3SAS_ADAPTER *ioc, 958 struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *pcie_device); 959 typedef void (*MPT_BUILD_SG)(struct MPT3SAS_ADAPTER *ioc, void *psge, 960 dma_addr_t data_out_dma, size_t data_out_sz, 961 dma_addr_t data_in_dma, size_t data_in_sz); 962 typedef void (*MPT_BUILD_ZERO_LEN_SGE)(struct MPT3SAS_ADAPTER *ioc, 963 void *paddr); 964 965 /* SAS3.5 support */ 966 typedef void (*NVME_BUILD_PRP)(struct MPT3SAS_ADAPTER *ioc, u16 smid, 967 Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request, 968 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma, 969 size_t data_in_sz); 970 971 /* To support atomic and non atomic descriptors*/ 972 typedef void (*PUT_SMID_IO_FP_HIP) (struct MPT3SAS_ADAPTER *ioc, u16 smid, 973 u16 funcdep); 974 typedef void (*PUT_SMID_DEFAULT) (struct MPT3SAS_ADAPTER *ioc, u16 smid); 975 typedef u32 (*BASE_READ_REG) (const volatile void __iomem *addr); 976 /* 977 * To get high iops reply queue's msix index when high iops mode is enabled 978 * else get the msix index of general reply queues. 979 */ 980 typedef u8 (*GET_MSIX_INDEX) (struct MPT3SAS_ADAPTER *ioc, 981 struct scsi_cmnd *scmd); 982 983 /* IOC Facts and Port Facts converted from little endian to cpu */ 984 union mpi3_version_union { 985 MPI2_VERSION_STRUCT Struct; 986 u32 Word; 987 }; 988 989 struct mpt3sas_facts { 990 u16 MsgVersion; 991 u16 HeaderVersion; 992 u8 IOCNumber; 993 u8 VP_ID; 994 u8 VF_ID; 995 u16 IOCExceptions; 996 u16 IOCStatus; 997 u32 IOCLogInfo; 998 u8 MaxChainDepth; 999 u8 WhoInit; 1000 u8 NumberOfPorts; 1001 u8 MaxMSIxVectors; 1002 u16 RequestCredit; 1003 u16 ProductID; 1004 u32 IOCCapabilities; 1005 union mpi3_version_union FWVersion; 1006 u16 IOCRequestFrameSize; 1007 u16 IOCMaxChainSegmentSize; 1008 u16 MaxInitiators; 1009 u16 MaxTargets; 1010 u16 MaxSasExpanders; 1011 u16 MaxEnclosures; 1012 u16 ProtocolFlags; 1013 u16 HighPriorityCredit; 1014 u16 MaxReplyDescriptorPostQueueDepth; 1015 u8 ReplyFrameSize; 1016 u8 MaxVolumes; 1017 u16 MaxDevHandle; 1018 u16 MaxPersistentEntries; 1019 u16 MinDevHandle; 1020 u8 CurrentHostPageSize; 1021 }; 1022 1023 struct mpt3sas_port_facts { 1024 u8 PortNumber; 1025 u8 VP_ID; 1026 u8 VF_ID; 1027 u8 PortType; 1028 u16 MaxPostedCmdBuffers; 1029 }; 1030 1031 struct reply_post_struct { 1032 Mpi2ReplyDescriptorsUnion_t *reply_post_free; 1033 dma_addr_t reply_post_free_dma; 1034 }; 1035 1036 /** 1037 * struct virtual_phy - vSES phy structure 1038 * sas_address: SAS Address of vSES device 1039 * phy_mask: vSES device's phy number 1040 * flags: flags used to manage this structure 1041 */ 1042 struct virtual_phy { 1043 struct list_head list; 1044 u64 sas_address; 1045 u32 phy_mask; 1046 u8 flags; 1047 }; 1048 1049 #define MPT_VPHY_FLAG_DIRTY_PHY 0x01 1050 1051 /** 1052 * struct hba_port - Saves each HBA's Wide/Narrow port info 1053 * @sas_address: sas address of this wide/narrow port's attached device 1054 * @phy_mask: HBA PHY's belonging to this port 1055 * @port_id: port number 1056 * @flags: hba port flags 1057 * @vphys_mask : mask of vSES devices Phy number 1058 * @vphys_list : list containing vSES device structures 1059 */ 1060 struct hba_port { 1061 struct list_head list; 1062 u64 sas_address; 1063 u32 phy_mask; 1064 u8 port_id; 1065 u8 flags; 1066 u32 vphys_mask; 1067 struct list_head vphys_list; 1068 }; 1069 1070 /* hba port flags */ 1071 #define HBA_PORT_FLAG_DIRTY_PORT 0x01 1072 #define HBA_PORT_FLAG_NEW_PORT 0x02 1073 1074 #define MULTIPATH_DISABLED_PORT_ID 0xFF 1075 1076 typedef void (*MPT3SAS_FLUSH_RUNNING_CMDS)(struct MPT3SAS_ADAPTER *ioc); 1077 /** 1078 * struct MPT3SAS_ADAPTER - per adapter struct 1079 * @list: ioc_list 1080 * @shost: shost object 1081 * @id: unique adapter id 1082 * @cpu_count: number online cpus 1083 * @name: generic ioc string 1084 * @tmp_string: tmp string used for logging 1085 * @pdev: pci pdev object 1086 * @pio_chip: physical io register space 1087 * @chip: memory mapped register space 1088 * @chip_phys: physical addrss prior to mapping 1089 * @logging_level: see mpt3sas_debug.h 1090 * @fwfault_debug: debuging FW timeouts 1091 * @ir_firmware: IR firmware present 1092 * @bars: bitmask of BAR's that must be configured 1093 * @mask_interrupts: ignore interrupt 1094 * @pci_access_mutex: Mutex to synchronize ioctl, sysfs show path and 1095 * pci resource handling 1096 * @fault_reset_work_q_name: fw fault work queue 1097 * @fault_reset_work_q: "" 1098 * @fault_reset_work: "" 1099 * @firmware_event_name: fw event work queue 1100 * @firmware_event_thread: "" 1101 * @fw_event_lock: 1102 * @fw_event_list: list of fw events 1103 * @current_evet: current processing firmware event 1104 * @fw_event_cleanup: set to one while cleaning up the fw events 1105 * @aen_event_read_flag: event log was read 1106 * @broadcast_aen_busy: broadcast aen waiting to be serviced 1107 * @shost_recovery: host reset in progress 1108 * @ioc_reset_in_progress_lock: 1109 * @ioc_link_reset_in_progress: phy/hard reset in progress 1110 * @ignore_loginfos: ignore loginfos during task management 1111 * @remove_host: flag for when driver unloads, to avoid sending dev resets 1112 * @pci_error_recovery: flag to prevent ioc access until slot reset completes 1113 * @wait_for_discovery_to_complete: flag set at driver load time when 1114 * waiting on reporting devices 1115 * @is_driver_loading: flag set at driver load time 1116 * @port_enable_failed: flag set when port enable has failed 1117 * @start_scan: flag set from scan_start callback, cleared from _mpt3sas_fw_work 1118 * @start_scan_failed: means port enable failed, return's the ioc_status 1119 * @msix_enable: flag indicating msix is enabled 1120 * @msix_vector_count: number msix vectors 1121 * @cpu_msix_table: table for mapping cpus to msix index 1122 * @cpu_msix_table_sz: table size 1123 * @total_io_cnt: Gives total IO count, used to load balance the interrupts 1124 * @ioc_coredump_loop: will have non-zero value when FW is in CoreDump state 1125 * @timestamp_update_count: Counter to fire timeSync command 1126 * time_sync_interval: Time sync interval read from man page 11 1127 * @high_iops_outstanding: used to load balance the interrupts 1128 * within high iops reply queues 1129 * @msix_load_balance: Enables load balancing of interrupts across 1130 * the multiple MSIXs 1131 * @schedule_dead_ioc_flush_running_cmds: callback to flush pending commands 1132 * @thresh_hold: Max number of reply descriptors processed 1133 * before updating Host Index 1134 * @drv_support_bitmap: driver's supported feature bit map 1135 * @use_32bit_dma: Flag to use 32 bit consistent dma mask 1136 * @scsi_io_cb_idx: shost generated commands 1137 * @tm_cb_idx: task management commands 1138 * @scsih_cb_idx: scsih internal commands 1139 * @transport_cb_idx: transport internal commands 1140 * @ctl_cb_idx: clt internal commands 1141 * @base_cb_idx: base internal commands 1142 * @config_cb_idx: base internal commands 1143 * @tm_tr_cb_idx : device removal target reset handshake 1144 * @tm_tr_volume_cb_idx : volume removal target reset 1145 * @base_cmds: 1146 * @transport_cmds: 1147 * @scsih_cmds: 1148 * @tm_cmds: 1149 * @ctl_cmds: 1150 * @config_cmds: 1151 * @base_add_sg_single: handler for either 32/64 bit sgl's 1152 * @event_type: bits indicating which events to log 1153 * @event_context: unique id for each logged event 1154 * @event_log: event log pointer 1155 * @event_masks: events that are masked 1156 * @max_shutdown_latency: timeout value for NVMe shutdown operation, 1157 * which is equal that NVMe drive's RTD3 Entry Latency 1158 * which has reported maximum RTD3 Entry Latency value 1159 * among attached NVMe drives. 1160 * @facts: static facts data 1161 * @prev_fw_facts: previous fw facts data 1162 * @pfacts: static port facts data 1163 * @manu_pg0: static manufacturing page 0 1164 * @manu_pg10: static manufacturing page 10 1165 * @manu_pg11: static manufacturing page 11 1166 * @bios_pg2: static bios page 2 1167 * @bios_pg3: static bios page 3 1168 * @ioc_pg8: static ioc page 8 1169 * @iounit_pg0: static iounit page 0 1170 * @iounit_pg1: static iounit page 1 1171 * @iounit_pg8: static iounit page 8 1172 * @sas_hba: sas host object 1173 * @sas_expander_list: expander object list 1174 * @enclosure_list: enclosure object list 1175 * @sas_node_lock: 1176 * @sas_device_list: sas device object list 1177 * @sas_device_init_list: sas device object list (used only at init time) 1178 * @sas_device_lock: 1179 * @pcie_device_list: pcie device object list 1180 * @pcie_device_init_list: pcie device object list (used only at init time) 1181 * @pcie_device_lock: 1182 * @io_missing_delay: time for IO completed by fw when PDR enabled 1183 * @device_missing_delay: time for device missing by fw when PDR enabled 1184 * @sas_id : used for setting volume target IDs 1185 * @pcie_target_id: used for setting pcie target IDs 1186 * @blocking_handles: bitmask used to identify which devices need blocking 1187 * @pd_handles : bitmask for PD handles 1188 * @pd_handles_sz : size of pd_handle bitmask 1189 * @config_page_sz: config page size 1190 * @config_page: reserve memory for config page payload 1191 * @config_page_dma: 1192 * @hba_queue_depth: hba request queue depth 1193 * @sge_size: sg element size for either 32/64 bit 1194 * @scsiio_depth: SCSI_IO queue depth 1195 * @request_sz: per request frame size 1196 * @request: pool of request frames 1197 * @request_dma: 1198 * @request_dma_sz: 1199 * @scsi_lookup: firmware request tracker list 1200 * @scsi_lookup_lock: 1201 * @free_list: free list of request 1202 * @pending_io_count: 1203 * @reset_wq: 1204 * @chain: pool of chains 1205 * @chain_dma: 1206 * @max_sges_in_main_message: number sg elements in main message 1207 * @max_sges_in_chain_message: number sg elements per chain 1208 * @chains_needed_per_io: max chains per io 1209 * @chain_depth: total chains allocated 1210 * @chain_segment_sz: gives the max number of 1211 * SGEs accommodate on single chain buffer 1212 * @hi_priority_smid: 1213 * @hi_priority: 1214 * @hi_priority_dma: 1215 * @hi_priority_depth: 1216 * @hpr_lookup: 1217 * @hpr_free_list: 1218 * @internal_smid: 1219 * @internal: 1220 * @internal_dma: 1221 * @internal_depth: 1222 * @internal_lookup: 1223 * @internal_free_list: 1224 * @sense: pool of sense 1225 * @sense_dma: 1226 * @sense_dma_pool: 1227 * @reply_depth: hba reply queue depth: 1228 * @reply_sz: per reply frame size: 1229 * @reply: pool of replys: 1230 * @reply_dma: 1231 * @reply_dma_pool: 1232 * @reply_free_queue_depth: reply free depth 1233 * @reply_free: pool for reply free queue (32 bit addr) 1234 * @reply_free_dma: 1235 * @reply_free_dma_pool: 1236 * @reply_free_host_index: tail index in pool to insert free replys 1237 * @reply_post_queue_depth: reply post queue depth 1238 * @reply_post_struct: struct for reply_post_free physical & virt address 1239 * @rdpq_array_capable: FW supports multiple reply queue addresses in ioc_init 1240 * @rdpq_array_enable: rdpq_array support is enabled in the driver 1241 * @rdpq_array_enable_assigned: this ensures that rdpq_array_enable flag 1242 * is assigned only ones 1243 * @reply_queue_count: number of reply queue's 1244 * @reply_queue_list: link list contaning the reply queue info 1245 * @msix96_vector: 96 MSI-X vector support 1246 * @replyPostRegisterIndex: index of next position in Reply Desc Post Queue 1247 * @delayed_tr_list: target reset link list 1248 * @delayed_tr_volume_list: volume target reset link list 1249 * @delayed_sc_list: 1250 * @delayed_event_ack_list: 1251 * @temp_sensors_count: flag to carry the number of temperature sensors 1252 * @pci_access_mutex: Mutex to synchronize ioctl,sysfs show path and 1253 * pci resource handling. PCI resource freeing will lead to free 1254 * vital hardware/memory resource, which might be in use by cli/sysfs 1255 * path functions resulting in Null pointer reference followed by kernel 1256 * crash. To avoid the above race condition we use mutex syncrhonization 1257 * which ensures the syncrhonization between cli/sysfs_show path. 1258 * @atomic_desc_capable: Atomic Request Descriptor support. 1259 * @GET_MSIX_INDEX: Get the msix index of high iops queues. 1260 * @multipath_on_hba: flag to determine multipath on hba is enabled or not 1261 * @port_table_list: list containing HBA's wide/narrow port's info 1262 */ 1263 struct MPT3SAS_ADAPTER { 1264 struct list_head list; 1265 struct Scsi_Host *shost; 1266 u8 id; 1267 int cpu_count; 1268 char name[MPT_NAME_LENGTH]; 1269 char driver_name[MPT_NAME_LENGTH - 8]; 1270 char tmp_string[MPT_STRING_LENGTH]; 1271 struct pci_dev *pdev; 1272 Mpi2SystemInterfaceRegs_t __iomem *chip; 1273 phys_addr_t chip_phys; 1274 int logging_level; 1275 int fwfault_debug; 1276 u8 ir_firmware; 1277 int bars; 1278 u8 mask_interrupts; 1279 1280 /* fw fault handler */ 1281 char fault_reset_work_q_name[20]; 1282 struct workqueue_struct *fault_reset_work_q; 1283 struct delayed_work fault_reset_work; 1284 1285 /* fw event handler */ 1286 char firmware_event_name[20]; 1287 struct workqueue_struct *firmware_event_thread; 1288 spinlock_t fw_event_lock; 1289 struct list_head fw_event_list; 1290 struct fw_event_work *current_event; 1291 u8 fw_events_cleanup; 1292 1293 /* misc flags */ 1294 int aen_event_read_flag; 1295 u8 broadcast_aen_busy; 1296 u16 broadcast_aen_pending; 1297 u8 shost_recovery; 1298 u8 got_task_abort_from_ioctl; 1299 1300 struct mutex reset_in_progress_mutex; 1301 spinlock_t ioc_reset_in_progress_lock; 1302 u8 ioc_link_reset_in_progress; 1303 1304 u8 ignore_loginfos; 1305 u8 remove_host; 1306 u8 pci_error_recovery; 1307 u8 wait_for_discovery_to_complete; 1308 u8 is_driver_loading; 1309 u8 port_enable_failed; 1310 u8 start_scan; 1311 u16 start_scan_failed; 1312 1313 u8 msix_enable; 1314 u16 msix_vector_count; 1315 u8 *cpu_msix_table; 1316 u16 cpu_msix_table_sz; 1317 resource_size_t __iomem **reply_post_host_index; 1318 u32 ioc_reset_count; 1319 MPT3SAS_FLUSH_RUNNING_CMDS schedule_dead_ioc_flush_running_cmds; 1320 u32 non_operational_loop; 1321 u8 ioc_coredump_loop; 1322 u32 timestamp_update_count; 1323 u32 time_sync_interval; 1324 atomic64_t total_io_cnt; 1325 atomic64_t high_iops_outstanding; 1326 bool msix_load_balance; 1327 u16 thresh_hold; 1328 u8 high_iops_queues; 1329 u32 drv_support_bitmap; 1330 bool enable_sdev_max_qd; 1331 bool use_32bit_dma; 1332 1333 /* internal commands, callback index */ 1334 u8 scsi_io_cb_idx; 1335 u8 tm_cb_idx; 1336 u8 transport_cb_idx; 1337 u8 scsih_cb_idx; 1338 u8 ctl_cb_idx; 1339 u8 base_cb_idx; 1340 u8 port_enable_cb_idx; 1341 u8 config_cb_idx; 1342 u8 tm_tr_cb_idx; 1343 u8 tm_tr_volume_cb_idx; 1344 u8 tm_sas_control_cb_idx; 1345 struct _internal_cmd base_cmds; 1346 struct _internal_cmd port_enable_cmds; 1347 struct _internal_cmd transport_cmds; 1348 struct _internal_cmd scsih_cmds; 1349 struct _internal_cmd tm_cmds; 1350 struct _internal_cmd ctl_cmds; 1351 struct _internal_cmd config_cmds; 1352 1353 MPT_ADD_SGE base_add_sg_single; 1354 1355 /* function ptr for either IEEE or MPI sg elements */ 1356 MPT_BUILD_SG_SCMD build_sg_scmd; 1357 MPT_BUILD_SG build_sg; 1358 MPT_BUILD_ZERO_LEN_SGE build_zero_len_sge; 1359 u16 sge_size_ieee; 1360 u16 hba_mpi_version_belonged; 1361 1362 /* function ptr for MPI sg elements only */ 1363 MPT_BUILD_SG build_sg_mpi; 1364 MPT_BUILD_ZERO_LEN_SGE build_zero_len_sge_mpi; 1365 1366 /* function ptr for NVMe PRP elements only */ 1367 NVME_BUILD_PRP build_nvme_prp; 1368 1369 /* event log */ 1370 u32 event_type[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS]; 1371 u32 event_context; 1372 void *event_log; 1373 u32 event_masks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS]; 1374 1375 u8 tm_custom_handling; 1376 u8 nvme_abort_timeout; 1377 u16 max_shutdown_latency; 1378 1379 /* static config pages */ 1380 struct mpt3sas_facts facts; 1381 struct mpt3sas_facts prev_fw_facts; 1382 struct mpt3sas_port_facts *pfacts; 1383 Mpi2ManufacturingPage0_t manu_pg0; 1384 struct Mpi2ManufacturingPage10_t manu_pg10; 1385 struct Mpi2ManufacturingPage11_t manu_pg11; 1386 Mpi2BiosPage2_t bios_pg2; 1387 Mpi2BiosPage3_t bios_pg3; 1388 Mpi2IOCPage8_t ioc_pg8; 1389 Mpi2IOUnitPage0_t iounit_pg0; 1390 Mpi2IOUnitPage1_t iounit_pg1; 1391 Mpi2IOUnitPage8_t iounit_pg8; 1392 Mpi2IOCPage1_t ioc_pg1_copy; 1393 1394 struct _boot_device req_boot_device; 1395 struct _boot_device req_alt_boot_device; 1396 struct _boot_device current_boot_device; 1397 1398 /* sas hba, expander, and device list */ 1399 struct _sas_node sas_hba; 1400 struct list_head sas_expander_list; 1401 struct list_head enclosure_list; 1402 spinlock_t sas_node_lock; 1403 struct list_head sas_device_list; 1404 struct list_head sas_device_init_list; 1405 spinlock_t sas_device_lock; 1406 struct list_head pcie_device_list; 1407 struct list_head pcie_device_init_list; 1408 spinlock_t pcie_device_lock; 1409 1410 struct list_head raid_device_list; 1411 spinlock_t raid_device_lock; 1412 u8 io_missing_delay; 1413 u16 device_missing_delay; 1414 int sas_id; 1415 int pcie_target_id; 1416 1417 void *blocking_handles; 1418 void *pd_handles; 1419 u16 pd_handles_sz; 1420 1421 void *pend_os_device_add; 1422 u16 pend_os_device_add_sz; 1423 1424 /* config page */ 1425 u16 config_page_sz; 1426 void *config_page; 1427 dma_addr_t config_page_dma; 1428 void *config_vaddr; 1429 1430 /* scsiio request */ 1431 u16 hba_queue_depth; 1432 u16 sge_size; 1433 u16 scsiio_depth; 1434 u16 request_sz; 1435 u8 *request; 1436 dma_addr_t request_dma; 1437 u32 request_dma_sz; 1438 struct pcie_sg_list *pcie_sg_lookup; 1439 spinlock_t scsi_lookup_lock; 1440 int pending_io_count; 1441 wait_queue_head_t reset_wq; 1442 1443 /* PCIe SGL */ 1444 struct dma_pool *pcie_sgl_dma_pool; 1445 /* Host Page Size */ 1446 u32 page_size; 1447 1448 /* chain */ 1449 struct chain_lookup *chain_lookup; 1450 struct list_head free_chain_list; 1451 struct dma_pool *chain_dma_pool; 1452 ulong chain_pages; 1453 u16 max_sges_in_main_message; 1454 u16 max_sges_in_chain_message; 1455 u16 chains_needed_per_io; 1456 u32 chain_depth; 1457 u16 chain_segment_sz; 1458 u16 chains_per_prp_buffer; 1459 1460 /* hi-priority queue */ 1461 u16 hi_priority_smid; 1462 u8 *hi_priority; 1463 dma_addr_t hi_priority_dma; 1464 u16 hi_priority_depth; 1465 struct request_tracker *hpr_lookup; 1466 struct list_head hpr_free_list; 1467 1468 /* internal queue */ 1469 u16 internal_smid; 1470 u8 *internal; 1471 dma_addr_t internal_dma; 1472 u16 internal_depth; 1473 struct request_tracker *internal_lookup; 1474 struct list_head internal_free_list; 1475 1476 /* sense */ 1477 u8 *sense; 1478 dma_addr_t sense_dma; 1479 struct dma_pool *sense_dma_pool; 1480 1481 /* reply */ 1482 u16 reply_sz; 1483 u8 *reply; 1484 dma_addr_t reply_dma; 1485 u32 reply_dma_max_address; 1486 u32 reply_dma_min_address; 1487 struct dma_pool *reply_dma_pool; 1488 1489 /* reply free queue */ 1490 u16 reply_free_queue_depth; 1491 __le32 *reply_free; 1492 dma_addr_t reply_free_dma; 1493 struct dma_pool *reply_free_dma_pool; 1494 u32 reply_free_host_index; 1495 1496 /* reply post queue */ 1497 u16 reply_post_queue_depth; 1498 struct reply_post_struct *reply_post; 1499 u8 rdpq_array_capable; 1500 u8 rdpq_array_enable; 1501 u8 rdpq_array_enable_assigned; 1502 struct dma_pool *reply_post_free_dma_pool; 1503 struct dma_pool *reply_post_free_array_dma_pool; 1504 Mpi2IOCInitRDPQArrayEntry *reply_post_free_array; 1505 dma_addr_t reply_post_free_array_dma; 1506 u8 reply_queue_count; 1507 struct list_head reply_queue_list; 1508 1509 u8 combined_reply_queue; 1510 u8 combined_reply_index_count; 1511 u8 smp_affinity_enable; 1512 /* reply post register index */ 1513 resource_size_t **replyPostRegisterIndex; 1514 1515 struct list_head delayed_tr_list; 1516 struct list_head delayed_tr_volume_list; 1517 struct list_head delayed_sc_list; 1518 struct list_head delayed_event_ack_list; 1519 u8 temp_sensors_count; 1520 struct mutex pci_access_mutex; 1521 1522 /* diag buffer support */ 1523 u8 *diag_buffer[MPI2_DIAG_BUF_TYPE_COUNT]; 1524 u32 diag_buffer_sz[MPI2_DIAG_BUF_TYPE_COUNT]; 1525 dma_addr_t diag_buffer_dma[MPI2_DIAG_BUF_TYPE_COUNT]; 1526 u8 diag_buffer_status[MPI2_DIAG_BUF_TYPE_COUNT]; 1527 u32 unique_id[MPI2_DIAG_BUF_TYPE_COUNT]; 1528 u32 product_specific[MPI2_DIAG_BUF_TYPE_COUNT][23]; 1529 u32 diagnostic_flags[MPI2_DIAG_BUF_TYPE_COUNT]; 1530 u32 ring_buffer_offset; 1531 u32 ring_buffer_sz; 1532 u8 is_warpdrive; 1533 u8 is_mcpu_endpoint; 1534 u8 hide_ir_msg; 1535 u8 mfg_pg10_hide_flag; 1536 u8 hide_drives; 1537 spinlock_t diag_trigger_lock; 1538 u8 diag_trigger_active; 1539 u8 atomic_desc_capable; 1540 BASE_READ_REG base_readl; 1541 struct SL_WH_MASTER_TRIGGER_T diag_trigger_master; 1542 struct SL_WH_EVENT_TRIGGERS_T diag_trigger_event; 1543 struct SL_WH_SCSI_TRIGGERS_T diag_trigger_scsi; 1544 struct SL_WH_MPI_TRIGGERS_T diag_trigger_mpi; 1545 u8 supports_trigger_pages; 1546 void *device_remove_in_progress; 1547 u16 device_remove_in_progress_sz; 1548 u8 is_gen35_ioc; 1549 u8 is_aero_ioc; 1550 struct dentry *debugfs_root; 1551 struct dentry *ioc_dump; 1552 PUT_SMID_IO_FP_HIP put_smid_scsi_io; 1553 PUT_SMID_IO_FP_HIP put_smid_fast_path; 1554 PUT_SMID_IO_FP_HIP put_smid_hi_priority; 1555 PUT_SMID_DEFAULT put_smid_default; 1556 GET_MSIX_INDEX get_msix_index_for_smlio; 1557 1558 u8 multipath_on_hba; 1559 struct list_head port_table_list; 1560 }; 1561 1562 struct mpt3sas_debugfs_buffer { 1563 void *buf; 1564 u32 len; 1565 }; 1566 1567 #define MPT_DRV_SUPPORT_BITMAP_MEMMOVE 0x00000001 1568 1569 typedef u8 (*MPT_CALLBACK)(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, 1570 u32 reply); 1571 1572 1573 /* base shared API */ 1574 extern struct list_head mpt3sas_ioc_list; 1575 extern char driver_name[MPT_NAME_LENGTH]; 1576 /* spinlock on list operations over IOCs 1577 * Case: when multiple warpdrive cards(IOCs) are in use 1578 * Each IOC will added to the ioc list structure on initialization. 1579 * Watchdog threads run at regular intervals to check IOC for any 1580 * fault conditions which will trigger the dead_ioc thread to 1581 * deallocate pci resource, resulting deleting the IOC netry from list, 1582 * this deletion need to protected by spinlock to enusre that 1583 * ioc removal is syncrhonized, if not synchronized it might lead to 1584 * list_del corruption as the ioc list is traversed in cli path. 1585 */ 1586 extern spinlock_t gioc_lock; 1587 1588 void mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc); 1589 void mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc); 1590 1591 int mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc); 1592 void mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc); 1593 int mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc); 1594 void mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc); 1595 void mpt3sas_free_enclosure_list(struct MPT3SAS_ADAPTER *ioc); 1596 int mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc, 1597 enum reset_type type); 1598 1599 void *mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid); 1600 void *mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid); 1601 __le32 mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, 1602 u16 smid); 1603 void *mpt3sas_base_get_pcie_sgl(struct MPT3SAS_ADAPTER *ioc, u16 smid); 1604 dma_addr_t mpt3sas_base_get_pcie_sgl_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid); 1605 void mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc, u8 poll); 1606 void mpt3sas_base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc); 1607 void mpt3sas_base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc); 1608 1609 void mpt3sas_base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid, 1610 u16 handle); 1611 void mpt3sas_base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid, 1612 u16 msix_task); 1613 void mpt3sas_base_put_smid_nvme_encap(struct MPT3SAS_ADAPTER *ioc, u16 smid); 1614 void mpt3sas_base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid); 1615 /* hi-priority queue */ 1616 u16 mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx); 1617 u16 mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx, 1618 struct scsi_cmnd *scmd); 1619 void mpt3sas_base_clear_st(struct MPT3SAS_ADAPTER *ioc, 1620 struct scsiio_tracker *st); 1621 1622 u16 mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx); 1623 void mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid); 1624 void mpt3sas_base_initialize_callback_handler(void); 1625 u8 mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func); 1626 void mpt3sas_base_release_callback_handler(u8 cb_idx); 1627 1628 u8 mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, 1629 u32 reply); 1630 u8 mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, 1631 u8 msix_index, u32 reply); 1632 void *mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, 1633 u32 phys_addr); 1634 1635 u32 mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked); 1636 1637 void mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code); 1638 #define mpt3sas_print_fault_code(ioc, fault_code) \ 1639 do { pr_err("%s fault info from func: %s\n", ioc->name, __func__); \ 1640 mpt3sas_base_fault_info(ioc, fault_code); } while (0) 1641 1642 void mpt3sas_base_coredump_info(struct MPT3SAS_ADAPTER *ioc, u16 fault_code); 1643 #define mpt3sas_print_coredump_info(ioc, fault_code) \ 1644 do { pr_err("%s fault info from func: %s\n", ioc->name, __func__); \ 1645 mpt3sas_base_coredump_info(ioc, fault_code); } while (0) 1646 1647 int mpt3sas_base_wait_for_coredump_completion(struct MPT3SAS_ADAPTER *ioc, 1648 const char *caller); 1649 int mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc, 1650 Mpi2SasIoUnitControlReply_t *mpi_reply, 1651 Mpi2SasIoUnitControlRequest_t *mpi_request); 1652 int mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc, 1653 Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request); 1654 1655 void mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, 1656 u32 *event_type); 1657 1658 void mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc); 1659 1660 void mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc, 1661 u16 device_missing_delay, u8 io_missing_delay); 1662 1663 int mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc); 1664 1665 void 1666 mpt3sas_wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc); 1667 1668 u8 mpt3sas_base_check_cmd_timeout(struct MPT3SAS_ADAPTER *ioc, 1669 u8 status, void *mpi_request, int sz); 1670 #define mpt3sas_check_cmd_timeout(ioc, status, mpi_request, sz, issue_reset) \ 1671 do { ioc_err(ioc, "In func: %s\n", __func__); \ 1672 issue_reset = mpt3sas_base_check_cmd_timeout(ioc, \ 1673 status, mpi_request, sz); } while (0) 1674 1675 int mpt3sas_wait_for_ioc(struct MPT3SAS_ADAPTER *ioc, int wait_count); 1676 1677 /* scsih shared API */ 1678 struct scsi_cmnd *mpt3sas_scsih_scsi_lookup_get(struct MPT3SAS_ADAPTER *ioc, 1679 u16 smid); 1680 u8 mpt3sas_scsih_event_callback(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, 1681 u32 reply); 1682 void mpt3sas_scsih_pre_reset_handler(struct MPT3SAS_ADAPTER *ioc); 1683 void mpt3sas_scsih_clear_outstanding_scsi_tm_commands( 1684 struct MPT3SAS_ADAPTER *ioc); 1685 void mpt3sas_scsih_reset_done_handler(struct MPT3SAS_ADAPTER *ioc); 1686 1687 int mpt3sas_scsih_issue_tm(struct MPT3SAS_ADAPTER *ioc, u16 handle, 1688 uint channel, uint id, u64 lun, u8 type, u16 smid_task, 1689 u16 msix_task, u8 timeout, u8 tr_method); 1690 int mpt3sas_scsih_issue_locked_tm(struct MPT3SAS_ADAPTER *ioc, u16 handle, 1691 uint channel, uint id, u64 lun, u8 type, u16 smid_task, 1692 u16 msix_task, u8 timeout, u8 tr_method); 1693 1694 void mpt3sas_scsih_set_tm_flag(struct MPT3SAS_ADAPTER *ioc, u16 handle); 1695 void mpt3sas_scsih_clear_tm_flag(struct MPT3SAS_ADAPTER *ioc, u16 handle); 1696 void mpt3sas_expander_remove(struct MPT3SAS_ADAPTER *ioc, u64 sas_address, 1697 struct hba_port *port); 1698 void mpt3sas_device_remove_by_sas_address(struct MPT3SAS_ADAPTER *ioc, 1699 u64 sas_address, struct hba_port *port); 1700 u8 mpt3sas_check_for_pending_internal_cmds(struct MPT3SAS_ADAPTER *ioc, 1701 u16 smid); 1702 struct hba_port * 1703 mpt3sas_get_port_by_id(struct MPT3SAS_ADAPTER *ioc, u8 port, 1704 u8 bypass_dirty_port_flag); 1705 1706 struct _sas_node *mpt3sas_scsih_expander_find_by_handle( 1707 struct MPT3SAS_ADAPTER *ioc, u16 handle); 1708 struct _sas_node *mpt3sas_scsih_expander_find_by_sas_address( 1709 struct MPT3SAS_ADAPTER *ioc, u64 sas_address, 1710 struct hba_port *port); 1711 struct _sas_device *mpt3sas_get_sdev_by_addr( 1712 struct MPT3SAS_ADAPTER *ioc, u64 sas_address, 1713 struct hba_port *port); 1714 struct _sas_device *__mpt3sas_get_sdev_by_addr( 1715 struct MPT3SAS_ADAPTER *ioc, u64 sas_address, 1716 struct hba_port *port); 1717 struct _sas_device *mpt3sas_get_sdev_by_handle(struct MPT3SAS_ADAPTER *ioc, 1718 u16 handle); 1719 struct _pcie_device *mpt3sas_get_pdev_by_handle(struct MPT3SAS_ADAPTER *ioc, 1720 u16 handle); 1721 1722 void mpt3sas_port_enable_complete(struct MPT3SAS_ADAPTER *ioc); 1723 struct _raid_device * 1724 mpt3sas_raid_device_find_by_handle(struct MPT3SAS_ADAPTER *ioc, u16 handle); 1725 void mpt3sas_scsih_change_queue_depth(struct scsi_device *sdev, int qdepth); 1726 struct _sas_device * 1727 __mpt3sas_get_sdev_by_rphy(struct MPT3SAS_ADAPTER *ioc, struct sas_rphy *rphy); 1728 struct virtual_phy * 1729 mpt3sas_get_vphy_by_phy(struct MPT3SAS_ADAPTER *ioc, 1730 struct hba_port *port, u32 phy); 1731 1732 /* config shared API */ 1733 u8 mpt3sas_config_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, 1734 u32 reply); 1735 int mpt3sas_config_get_number_hba_phys(struct MPT3SAS_ADAPTER *ioc, 1736 u8 *num_phys); 1737 int mpt3sas_config_get_manufacturing_pg0(struct MPT3SAS_ADAPTER *ioc, 1738 Mpi2ConfigReply_t *mpi_reply, Mpi2ManufacturingPage0_t *config_page); 1739 int mpt3sas_config_get_manufacturing_pg7(struct MPT3SAS_ADAPTER *ioc, 1740 Mpi2ConfigReply_t *mpi_reply, Mpi2ManufacturingPage7_t *config_page, 1741 u16 sz); 1742 int mpt3sas_config_get_manufacturing_pg10(struct MPT3SAS_ADAPTER *ioc, 1743 Mpi2ConfigReply_t *mpi_reply, 1744 struct Mpi2ManufacturingPage10_t *config_page); 1745 1746 int mpt3sas_config_get_manufacturing_pg11(struct MPT3SAS_ADAPTER *ioc, 1747 Mpi2ConfigReply_t *mpi_reply, 1748 struct Mpi2ManufacturingPage11_t *config_page); 1749 int mpt3sas_config_set_manufacturing_pg11(struct MPT3SAS_ADAPTER *ioc, 1750 Mpi2ConfigReply_t *mpi_reply, 1751 struct Mpi2ManufacturingPage11_t *config_page); 1752 1753 int mpt3sas_config_get_bios_pg2(struct MPT3SAS_ADAPTER *ioc, Mpi2ConfigReply_t 1754 *mpi_reply, Mpi2BiosPage2_t *config_page); 1755 int mpt3sas_config_get_bios_pg3(struct MPT3SAS_ADAPTER *ioc, Mpi2ConfigReply_t 1756 *mpi_reply, Mpi2BiosPage3_t *config_page); 1757 int mpt3sas_config_get_iounit_pg0(struct MPT3SAS_ADAPTER *ioc, Mpi2ConfigReply_t 1758 *mpi_reply, Mpi2IOUnitPage0_t *config_page); 1759 int mpt3sas_config_get_sas_device_pg0(struct MPT3SAS_ADAPTER *ioc, 1760 Mpi2ConfigReply_t *mpi_reply, Mpi2SasDevicePage0_t *config_page, 1761 u32 form, u32 handle); 1762 int mpt3sas_config_get_sas_device_pg1(struct MPT3SAS_ADAPTER *ioc, 1763 Mpi2ConfigReply_t *mpi_reply, Mpi2SasDevicePage1_t *config_page, 1764 u32 form, u32 handle); 1765 int mpt3sas_config_get_pcie_device_pg0(struct MPT3SAS_ADAPTER *ioc, 1766 Mpi2ConfigReply_t *mpi_reply, Mpi26PCIeDevicePage0_t *config_page, 1767 u32 form, u32 handle); 1768 int mpt3sas_config_get_pcie_device_pg2(struct MPT3SAS_ADAPTER *ioc, 1769 Mpi2ConfigReply_t *mpi_reply, Mpi26PCIeDevicePage2_t *config_page, 1770 u32 form, u32 handle); 1771 int mpt3sas_config_get_sas_iounit_pg0(struct MPT3SAS_ADAPTER *ioc, 1772 Mpi2ConfigReply_t *mpi_reply, Mpi2SasIOUnitPage0_t *config_page, 1773 u16 sz); 1774 int mpt3sas_config_get_iounit_pg1(struct MPT3SAS_ADAPTER *ioc, Mpi2ConfigReply_t 1775 *mpi_reply, Mpi2IOUnitPage1_t *config_page); 1776 int mpt3sas_config_get_iounit_pg3(struct MPT3SAS_ADAPTER *ioc, 1777 Mpi2ConfigReply_t *mpi_reply, Mpi2IOUnitPage3_t *config_page, u16 sz); 1778 int mpt3sas_config_set_iounit_pg1(struct MPT3SAS_ADAPTER *ioc, Mpi2ConfigReply_t 1779 *mpi_reply, Mpi2IOUnitPage1_t *config_page); 1780 int mpt3sas_config_get_iounit_pg8(struct MPT3SAS_ADAPTER *ioc, Mpi2ConfigReply_t 1781 *mpi_reply, Mpi2IOUnitPage8_t *config_page); 1782 int mpt3sas_config_get_sas_iounit_pg1(struct MPT3SAS_ADAPTER *ioc, 1783 Mpi2ConfigReply_t *mpi_reply, Mpi2SasIOUnitPage1_t *config_page, 1784 u16 sz); 1785 int mpt3sas_config_set_sas_iounit_pg1(struct MPT3SAS_ADAPTER *ioc, 1786 Mpi2ConfigReply_t *mpi_reply, Mpi2SasIOUnitPage1_t *config_page, 1787 u16 sz); 1788 int mpt3sas_config_get_ioc_pg1(struct MPT3SAS_ADAPTER *ioc, Mpi2ConfigReply_t 1789 *mpi_reply, Mpi2IOCPage1_t *config_page); 1790 int mpt3sas_config_set_ioc_pg1(struct MPT3SAS_ADAPTER *ioc, Mpi2ConfigReply_t 1791 *mpi_reply, Mpi2IOCPage1_t *config_page); 1792 int mpt3sas_config_get_ioc_pg8(struct MPT3SAS_ADAPTER *ioc, Mpi2ConfigReply_t 1793 *mpi_reply, Mpi2IOCPage8_t *config_page); 1794 int mpt3sas_config_get_expander_pg0(struct MPT3SAS_ADAPTER *ioc, 1795 Mpi2ConfigReply_t *mpi_reply, Mpi2ExpanderPage0_t *config_page, 1796 u32 form, u32 handle); 1797 int mpt3sas_config_get_expander_pg1(struct MPT3SAS_ADAPTER *ioc, 1798 Mpi2ConfigReply_t *mpi_reply, Mpi2ExpanderPage1_t *config_page, 1799 u32 phy_number, u16 handle); 1800 int mpt3sas_config_get_enclosure_pg0(struct MPT3SAS_ADAPTER *ioc, 1801 Mpi2ConfigReply_t *mpi_reply, Mpi2SasEnclosurePage0_t *config_page, 1802 u32 form, u32 handle); 1803 int mpt3sas_config_get_phy_pg0(struct MPT3SAS_ADAPTER *ioc, Mpi2ConfigReply_t 1804 *mpi_reply, Mpi2SasPhyPage0_t *config_page, u32 phy_number); 1805 int mpt3sas_config_get_phy_pg1(struct MPT3SAS_ADAPTER *ioc, Mpi2ConfigReply_t 1806 *mpi_reply, Mpi2SasPhyPage1_t *config_page, u32 phy_number); 1807 int mpt3sas_config_get_raid_volume_pg1(struct MPT3SAS_ADAPTER *ioc, 1808 Mpi2ConfigReply_t *mpi_reply, Mpi2RaidVolPage1_t *config_page, u32 form, 1809 u32 handle); 1810 int mpt3sas_config_get_number_pds(struct MPT3SAS_ADAPTER *ioc, u16 handle, 1811 u8 *num_pds); 1812 int mpt3sas_config_get_raid_volume_pg0(struct MPT3SAS_ADAPTER *ioc, 1813 Mpi2ConfigReply_t *mpi_reply, Mpi2RaidVolPage0_t *config_page, u32 form, 1814 u32 handle, u16 sz); 1815 int mpt3sas_config_get_phys_disk_pg0(struct MPT3SAS_ADAPTER *ioc, 1816 Mpi2ConfigReply_t *mpi_reply, Mpi2RaidPhysDiskPage0_t *config_page, 1817 u32 form, u32 form_specific); 1818 int mpt3sas_config_get_volume_handle(struct MPT3SAS_ADAPTER *ioc, u16 pd_handle, 1819 u16 *volume_handle); 1820 int mpt3sas_config_get_volume_wwid(struct MPT3SAS_ADAPTER *ioc, 1821 u16 volume_handle, u64 *wwid); 1822 int 1823 mpt3sas_config_get_driver_trigger_pg0(struct MPT3SAS_ADAPTER *ioc, 1824 Mpi2ConfigReply_t *mpi_reply, Mpi26DriverTriggerPage0_t *config_page); 1825 int 1826 mpt3sas_config_get_driver_trigger_pg1(struct MPT3SAS_ADAPTER *ioc, 1827 Mpi2ConfigReply_t *mpi_reply, Mpi26DriverTriggerPage1_t *config_page); 1828 int 1829 mpt3sas_config_get_driver_trigger_pg2(struct MPT3SAS_ADAPTER *ioc, 1830 Mpi2ConfigReply_t *mpi_reply, Mpi26DriverTriggerPage2_t *config_page); 1831 int 1832 mpt3sas_config_get_driver_trigger_pg3(struct MPT3SAS_ADAPTER *ioc, 1833 Mpi2ConfigReply_t *mpi_reply, Mpi26DriverTriggerPage3_t *config_page); 1834 int 1835 mpt3sas_config_get_driver_trigger_pg4(struct MPT3SAS_ADAPTER *ioc, 1836 Mpi2ConfigReply_t *mpi_reply, Mpi26DriverTriggerPage4_t *config_page); 1837 int 1838 mpt3sas_config_update_driver_trigger_pg1(struct MPT3SAS_ADAPTER *ioc, 1839 struct SL_WH_MASTER_TRIGGER_T *master_tg, bool set); 1840 int 1841 mpt3sas_config_update_driver_trigger_pg2(struct MPT3SAS_ADAPTER *ioc, 1842 struct SL_WH_EVENT_TRIGGERS_T *event_tg, bool set); 1843 int 1844 mpt3sas_config_update_driver_trigger_pg3(struct MPT3SAS_ADAPTER *ioc, 1845 struct SL_WH_SCSI_TRIGGERS_T *scsi_tg, bool set); 1846 int 1847 mpt3sas_config_update_driver_trigger_pg4(struct MPT3SAS_ADAPTER *ioc, 1848 struct SL_WH_MPI_TRIGGERS_T *mpi_tg, bool set); 1849 1850 /* ctl shared API */ 1851 extern struct device_attribute *mpt3sas_host_attrs[]; 1852 extern struct device_attribute *mpt3sas_dev_attrs[]; 1853 void mpt3sas_ctl_init(ushort hbas_to_enumerate); 1854 void mpt3sas_ctl_exit(ushort hbas_to_enumerate); 1855 u8 mpt3sas_ctl_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, 1856 u32 reply); 1857 void mpt3sas_ctl_pre_reset_handler(struct MPT3SAS_ADAPTER *ioc); 1858 void mpt3sas_ctl_clear_outstanding_ioctls(struct MPT3SAS_ADAPTER *ioc); 1859 void mpt3sas_ctl_reset_done_handler(struct MPT3SAS_ADAPTER *ioc); 1860 u8 mpt3sas_ctl_event_callback(struct MPT3SAS_ADAPTER *ioc, 1861 u8 msix_index, u32 reply); 1862 void mpt3sas_ctl_add_to_event_log(struct MPT3SAS_ADAPTER *ioc, 1863 Mpi2EventNotificationReply_t *mpi_reply); 1864 1865 void mpt3sas_enable_diag_buffer(struct MPT3SAS_ADAPTER *ioc, 1866 u8 bits_to_register); 1867 int mpt3sas_send_diag_release(struct MPT3SAS_ADAPTER *ioc, u8 buffer_type, 1868 u8 *issue_reset); 1869 1870 /* transport shared API */ 1871 extern struct scsi_transport_template *mpt3sas_transport_template; 1872 u8 mpt3sas_transport_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, 1873 u32 reply); 1874 struct _sas_port *mpt3sas_transport_port_add(struct MPT3SAS_ADAPTER *ioc, 1875 u16 handle, u64 sas_address, struct hba_port *port); 1876 void mpt3sas_transport_port_remove(struct MPT3SAS_ADAPTER *ioc, u64 sas_address, 1877 u64 sas_address_parent, struct hba_port *port); 1878 int mpt3sas_transport_add_host_phy(struct MPT3SAS_ADAPTER *ioc, struct _sas_phy 1879 *mpt3sas_phy, Mpi2SasPhyPage0_t phy_pg0, struct device *parent_dev); 1880 int mpt3sas_transport_add_expander_phy(struct MPT3SAS_ADAPTER *ioc, 1881 struct _sas_phy *mpt3sas_phy, Mpi2ExpanderPage1_t expander_pg1, 1882 struct device *parent_dev); 1883 void mpt3sas_transport_update_links(struct MPT3SAS_ADAPTER *ioc, 1884 u64 sas_address, u16 handle, u8 phy_number, u8 link_rate, 1885 struct hba_port *port); 1886 extern struct sas_function_template mpt3sas_transport_functions; 1887 extern struct scsi_transport_template *mpt3sas_transport_template; 1888 void 1889 mpt3sas_transport_del_phy_from_an_existing_port(struct MPT3SAS_ADAPTER *ioc, 1890 struct _sas_node *sas_node, struct _sas_phy *mpt3sas_phy); 1891 void 1892 mpt3sas_transport_add_phy_to_an_existing_port(struct MPT3SAS_ADAPTER *ioc, 1893 struct _sas_node *sas_node, struct _sas_phy *mpt3sas_phy, 1894 u64 sas_address, struct hba_port *port); 1895 /* trigger data externs */ 1896 void mpt3sas_send_trigger_data_event(struct MPT3SAS_ADAPTER *ioc, 1897 struct SL_WH_TRIGGERS_EVENT_DATA_T *event_data); 1898 void mpt3sas_process_trigger_data(struct MPT3SAS_ADAPTER *ioc, 1899 struct SL_WH_TRIGGERS_EVENT_DATA_T *event_data); 1900 void mpt3sas_trigger_master(struct MPT3SAS_ADAPTER *ioc, 1901 u32 trigger_bitmask); 1902 void mpt3sas_trigger_event(struct MPT3SAS_ADAPTER *ioc, u16 event, 1903 u16 log_entry_qualifier); 1904 void mpt3sas_trigger_scsi(struct MPT3SAS_ADAPTER *ioc, u8 sense_key, 1905 u8 asc, u8 ascq); 1906 void mpt3sas_trigger_mpi(struct MPT3SAS_ADAPTER *ioc, u16 ioc_status, 1907 u32 loginfo); 1908 1909 /* warpdrive APIs */ 1910 u8 mpt3sas_get_num_volumes(struct MPT3SAS_ADAPTER *ioc); 1911 void mpt3sas_init_warpdrive_properties(struct MPT3SAS_ADAPTER *ioc, 1912 struct _raid_device *raid_device); 1913 void 1914 mpt3sas_setup_direct_io(struct MPT3SAS_ADAPTER *ioc, struct scsi_cmnd *scmd, 1915 struct _raid_device *raid_device, Mpi25SCSIIORequest_t *mpi_request); 1916 1917 /* NCQ Prio Handling Check */ 1918 bool scsih_ncq_prio_supp(struct scsi_device *sdev); 1919 1920 void mpt3sas_setup_debugfs(struct MPT3SAS_ADAPTER *ioc); 1921 void mpt3sas_destroy_debugfs(struct MPT3SAS_ADAPTER *ioc); 1922 void mpt3sas_init_debugfs(void); 1923 void mpt3sas_exit_debugfs(void); 1924 1925 /** 1926 * _scsih_is_pcie_scsi_device - determines if device is an pcie scsi device 1927 * @device_info: bitfield providing information about the device. 1928 * Context: none 1929 * 1930 * Returns 1 if scsi device. 1931 */ 1932 static inline int 1933 mpt3sas_scsih_is_pcie_scsi_device(u32 device_info) 1934 { 1935 if ((device_info & 1936 MPI26_PCIE_DEVINFO_MASK_DEVICE_TYPE) == MPI26_PCIE_DEVINFO_SCSI) 1937 return 1; 1938 else 1939 return 0; 1940 } 1941 #endif /* MPT3SAS_BASE_H_INCLUDED */ 1942