1 /* 2 * This is the Fusion MPT base driver providing common API layer interface 3 * for access to MPT (Message Passing Technology) firmware. 4 * 5 * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c 6 * Copyright (C) 2012-2014 LSI Corporation 7 * Copyright (C) 2013-2014 Avago Technologies 8 * (mailto: MPT-FusionLinux.pdl@avagotech.com) 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 2 13 * of the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * NO WARRANTY 21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR 22 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT 23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, 24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is 25 * solely responsible for determining the appropriateness of using and 26 * distributing the Program and assumes all risks associated with its 27 * exercise of rights under this Agreement, including but not limited to 28 * the risks and costs of program errors, damage to or loss of data, 29 * programs or equipment, and unavailability or interruption of operations. 30 31 * DISCLAIMER OF LIABILITY 32 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY 33 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND 35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 36 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 37 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED 38 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES 39 40 * You should have received a copy of the GNU General Public License 41 * along with this program; if not, write to the Free Software 42 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, 43 * USA. 44 */ 45 46 #include <linux/kernel.h> 47 #include <linux/module.h> 48 #include <linux/errno.h> 49 #include <linux/init.h> 50 #include <linux/slab.h> 51 #include <linux/types.h> 52 #include <linux/pci.h> 53 #include <linux/kdev_t.h> 54 #include <linux/blkdev.h> 55 #include <linux/delay.h> 56 #include <linux/interrupt.h> 57 #include <linux/dma-mapping.h> 58 #include <linux/io.h> 59 #include <linux/time.h> 60 #include <linux/ktime.h> 61 #include <linux/kthread.h> 62 #include <linux/aer.h> 63 64 65 #include "mpt3sas_base.h" 66 67 static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS]; 68 69 70 #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */ 71 72 /* maximum controller queue depth */ 73 #define MAX_HBA_QUEUE_DEPTH 30000 74 #define MAX_CHAIN_DEPTH 100000 75 static int max_queue_depth = -1; 76 module_param(max_queue_depth, int, 0); 77 MODULE_PARM_DESC(max_queue_depth, " max controller queue depth "); 78 79 static int max_sgl_entries = -1; 80 module_param(max_sgl_entries, int, 0); 81 MODULE_PARM_DESC(max_sgl_entries, " max sg entries "); 82 83 static int msix_disable = -1; 84 module_param(msix_disable, int, 0); 85 MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)"); 86 87 static int smp_affinity_enable = 1; 88 module_param(smp_affinity_enable, int, S_IRUGO); 89 MODULE_PARM_DESC(smp_affinity_enable, "SMP affinity feature enable/disbale Default: enable(1)"); 90 91 static int max_msix_vectors = -1; 92 module_param(max_msix_vectors, int, 0); 93 MODULE_PARM_DESC(max_msix_vectors, 94 " max msix vectors"); 95 96 static int mpt3sas_fwfault_debug; 97 MODULE_PARM_DESC(mpt3sas_fwfault_debug, 98 " enable detection of firmware fault and halt firmware - (default=0)"); 99 100 static int 101 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc); 102 103 /** 104 * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug. 105 * 106 */ 107 static int 108 _scsih_set_fwfault_debug(const char *val, struct kernel_param *kp) 109 { 110 int ret = param_set_int(val, kp); 111 struct MPT3SAS_ADAPTER *ioc; 112 113 if (ret) 114 return ret; 115 116 /* global ioc spinlock to protect controller list on list operations */ 117 pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug); 118 spin_lock(&gioc_lock); 119 list_for_each_entry(ioc, &mpt3sas_ioc_list, list) 120 ioc->fwfault_debug = mpt3sas_fwfault_debug; 121 spin_unlock(&gioc_lock); 122 return 0; 123 } 124 module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug, 125 param_get_int, &mpt3sas_fwfault_debug, 0644); 126 127 /** 128 * mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc 129 * @arg: input argument, used to derive ioc 130 * 131 * Return 0 if controller is removed from pci subsystem. 132 * Return -1 for other case. 133 */ 134 static int mpt3sas_remove_dead_ioc_func(void *arg) 135 { 136 struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg; 137 struct pci_dev *pdev; 138 139 if ((ioc == NULL)) 140 return -1; 141 142 pdev = ioc->pdev; 143 if ((pdev == NULL)) 144 return -1; 145 pci_stop_and_remove_bus_device_locked(pdev); 146 return 0; 147 } 148 149 /** 150 * _base_fault_reset_work - workq handling ioc fault conditions 151 * @work: input argument, used to derive ioc 152 * Context: sleep. 153 * 154 * Return nothing. 155 */ 156 static void 157 _base_fault_reset_work(struct work_struct *work) 158 { 159 struct MPT3SAS_ADAPTER *ioc = 160 container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work); 161 unsigned long flags; 162 u32 doorbell; 163 int rc; 164 struct task_struct *p; 165 166 167 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 168 if (ioc->shost_recovery || ioc->pci_error_recovery) 169 goto rearm_timer; 170 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 171 172 doorbell = mpt3sas_base_get_iocstate(ioc, 0); 173 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) { 174 pr_err(MPT3SAS_FMT "SAS host is non-operational !!!!\n", 175 ioc->name); 176 177 /* It may be possible that EEH recovery can resolve some of 178 * pci bus failure issues rather removing the dead ioc function 179 * by considering controller is in a non-operational state. So 180 * here priority is given to the EEH recovery. If it doesn't 181 * not resolve this issue, mpt3sas driver will consider this 182 * controller to non-operational state and remove the dead ioc 183 * function. 184 */ 185 if (ioc->non_operational_loop++ < 5) { 186 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, 187 flags); 188 goto rearm_timer; 189 } 190 191 /* 192 * Call _scsih_flush_pending_cmds callback so that we flush all 193 * pending commands back to OS. This call is required to aovid 194 * deadlock at block layer. Dead IOC will fail to do diag reset, 195 * and this call is safe since dead ioc will never return any 196 * command back from HW. 197 */ 198 ioc->schedule_dead_ioc_flush_running_cmds(ioc); 199 /* 200 * Set remove_host flag early since kernel thread will 201 * take some time to execute. 202 */ 203 ioc->remove_host = 1; 204 /*Remove the Dead Host */ 205 p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc, 206 "%s_dead_ioc_%d", ioc->driver_name, ioc->id); 207 if (IS_ERR(p)) 208 pr_err(MPT3SAS_FMT 209 "%s: Running mpt3sas_dead_ioc thread failed !!!!\n", 210 ioc->name, __func__); 211 else 212 pr_err(MPT3SAS_FMT 213 "%s: Running mpt3sas_dead_ioc thread success !!!!\n", 214 ioc->name, __func__); 215 return; /* don't rearm timer */ 216 } 217 218 ioc->non_operational_loop = 0; 219 220 if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) { 221 rc = mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER); 222 pr_warn(MPT3SAS_FMT "%s: hard reset: %s\n", ioc->name, 223 __func__, (rc == 0) ? "success" : "failed"); 224 doorbell = mpt3sas_base_get_iocstate(ioc, 0); 225 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) 226 mpt3sas_base_fault_info(ioc, doorbell & 227 MPI2_DOORBELL_DATA_MASK); 228 if (rc && (doorbell & MPI2_IOC_STATE_MASK) != 229 MPI2_IOC_STATE_OPERATIONAL) 230 return; /* don't rearm timer */ 231 } 232 233 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 234 rearm_timer: 235 if (ioc->fault_reset_work_q) 236 queue_delayed_work(ioc->fault_reset_work_q, 237 &ioc->fault_reset_work, 238 msecs_to_jiffies(FAULT_POLLING_INTERVAL)); 239 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 240 } 241 242 /** 243 * mpt3sas_base_start_watchdog - start the fault_reset_work_q 244 * @ioc: per adapter object 245 * Context: sleep. 246 * 247 * Return nothing. 248 */ 249 void 250 mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc) 251 { 252 unsigned long flags; 253 254 if (ioc->fault_reset_work_q) 255 return; 256 257 /* initialize fault polling */ 258 259 INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work); 260 snprintf(ioc->fault_reset_work_q_name, 261 sizeof(ioc->fault_reset_work_q_name), "poll_%s%d_status", 262 ioc->driver_name, ioc->id); 263 ioc->fault_reset_work_q = 264 create_singlethread_workqueue(ioc->fault_reset_work_q_name); 265 if (!ioc->fault_reset_work_q) { 266 pr_err(MPT3SAS_FMT "%s: failed (line=%d)\n", 267 ioc->name, __func__, __LINE__); 268 return; 269 } 270 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 271 if (ioc->fault_reset_work_q) 272 queue_delayed_work(ioc->fault_reset_work_q, 273 &ioc->fault_reset_work, 274 msecs_to_jiffies(FAULT_POLLING_INTERVAL)); 275 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 276 } 277 278 /** 279 * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q 280 * @ioc: per adapter object 281 * Context: sleep. 282 * 283 * Return nothing. 284 */ 285 void 286 mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc) 287 { 288 unsigned long flags; 289 struct workqueue_struct *wq; 290 291 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 292 wq = ioc->fault_reset_work_q; 293 ioc->fault_reset_work_q = NULL; 294 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 295 if (wq) { 296 if (!cancel_delayed_work_sync(&ioc->fault_reset_work)) 297 flush_workqueue(wq); 298 destroy_workqueue(wq); 299 } 300 } 301 302 /** 303 * mpt3sas_base_fault_info - verbose translation of firmware FAULT code 304 * @ioc: per adapter object 305 * @fault_code: fault code 306 * 307 * Return nothing. 308 */ 309 void 310 mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code) 311 { 312 pr_err(MPT3SAS_FMT "fault_state(0x%04x)!\n", 313 ioc->name, fault_code); 314 } 315 316 /** 317 * mpt3sas_halt_firmware - halt's mpt controller firmware 318 * @ioc: per adapter object 319 * 320 * For debugging timeout related issues. Writing 0xCOFFEE00 321 * to the doorbell register will halt controller firmware. With 322 * the purpose to stop both driver and firmware, the enduser can 323 * obtain a ring buffer from controller UART. 324 */ 325 void 326 mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc) 327 { 328 u32 doorbell; 329 330 if (!ioc->fwfault_debug) 331 return; 332 333 dump_stack(); 334 335 doorbell = readl(&ioc->chip->Doorbell); 336 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) 337 mpt3sas_base_fault_info(ioc , doorbell); 338 else { 339 writel(0xC0FFEE00, &ioc->chip->Doorbell); 340 pr_err(MPT3SAS_FMT "Firmware is halted due to command timeout\n", 341 ioc->name); 342 } 343 344 if (ioc->fwfault_debug == 2) 345 for (;;) 346 ; 347 else 348 panic("panic in %s\n", __func__); 349 } 350 351 /** 352 * _base_sas_ioc_info - verbose translation of the ioc status 353 * @ioc: per adapter object 354 * @mpi_reply: reply mf payload returned from firmware 355 * @request_hdr: request mf 356 * 357 * Return nothing. 358 */ 359 static void 360 _base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply, 361 MPI2RequestHeader_t *request_hdr) 362 { 363 u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & 364 MPI2_IOCSTATUS_MASK; 365 char *desc = NULL; 366 u16 frame_sz; 367 char *func_str = NULL; 368 369 /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */ 370 if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST || 371 request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH || 372 request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION) 373 return; 374 375 if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE) 376 return; 377 378 switch (ioc_status) { 379 380 /**************************************************************************** 381 * Common IOCStatus values for all replies 382 ****************************************************************************/ 383 384 case MPI2_IOCSTATUS_INVALID_FUNCTION: 385 desc = "invalid function"; 386 break; 387 case MPI2_IOCSTATUS_BUSY: 388 desc = "busy"; 389 break; 390 case MPI2_IOCSTATUS_INVALID_SGL: 391 desc = "invalid sgl"; 392 break; 393 case MPI2_IOCSTATUS_INTERNAL_ERROR: 394 desc = "internal error"; 395 break; 396 case MPI2_IOCSTATUS_INVALID_VPID: 397 desc = "invalid vpid"; 398 break; 399 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES: 400 desc = "insufficient resources"; 401 break; 402 case MPI2_IOCSTATUS_INSUFFICIENT_POWER: 403 desc = "insufficient power"; 404 break; 405 case MPI2_IOCSTATUS_INVALID_FIELD: 406 desc = "invalid field"; 407 break; 408 case MPI2_IOCSTATUS_INVALID_STATE: 409 desc = "invalid state"; 410 break; 411 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED: 412 desc = "op state not supported"; 413 break; 414 415 /**************************************************************************** 416 * Config IOCStatus values 417 ****************************************************************************/ 418 419 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION: 420 desc = "config invalid action"; 421 break; 422 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE: 423 desc = "config invalid type"; 424 break; 425 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE: 426 desc = "config invalid page"; 427 break; 428 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA: 429 desc = "config invalid data"; 430 break; 431 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS: 432 desc = "config no defaults"; 433 break; 434 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT: 435 desc = "config cant commit"; 436 break; 437 438 /**************************************************************************** 439 * SCSI IO Reply 440 ****************************************************************************/ 441 442 case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR: 443 case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE: 444 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE: 445 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN: 446 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN: 447 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR: 448 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR: 449 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED: 450 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: 451 case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED: 452 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED: 453 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED: 454 break; 455 456 /**************************************************************************** 457 * For use by SCSI Initiator and SCSI Target end-to-end data protection 458 ****************************************************************************/ 459 460 case MPI2_IOCSTATUS_EEDP_GUARD_ERROR: 461 desc = "eedp guard error"; 462 break; 463 case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR: 464 desc = "eedp ref tag error"; 465 break; 466 case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR: 467 desc = "eedp app tag error"; 468 break; 469 470 /**************************************************************************** 471 * SCSI Target values 472 ****************************************************************************/ 473 474 case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX: 475 desc = "target invalid io index"; 476 break; 477 case MPI2_IOCSTATUS_TARGET_ABORTED: 478 desc = "target aborted"; 479 break; 480 case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE: 481 desc = "target no conn retryable"; 482 break; 483 case MPI2_IOCSTATUS_TARGET_NO_CONNECTION: 484 desc = "target no connection"; 485 break; 486 case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH: 487 desc = "target xfer count mismatch"; 488 break; 489 case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR: 490 desc = "target data offset error"; 491 break; 492 case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA: 493 desc = "target too much write data"; 494 break; 495 case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT: 496 desc = "target iu too short"; 497 break; 498 case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT: 499 desc = "target ack nak timeout"; 500 break; 501 case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED: 502 desc = "target nak received"; 503 break; 504 505 /**************************************************************************** 506 * Serial Attached SCSI values 507 ****************************************************************************/ 508 509 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED: 510 desc = "smp request failed"; 511 break; 512 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN: 513 desc = "smp data overrun"; 514 break; 515 516 /**************************************************************************** 517 * Diagnostic Buffer Post / Diagnostic Release values 518 ****************************************************************************/ 519 520 case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED: 521 desc = "diagnostic released"; 522 break; 523 default: 524 break; 525 } 526 527 if (!desc) 528 return; 529 530 switch (request_hdr->Function) { 531 case MPI2_FUNCTION_CONFIG: 532 frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size; 533 func_str = "config_page"; 534 break; 535 case MPI2_FUNCTION_SCSI_TASK_MGMT: 536 frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t); 537 func_str = "task_mgmt"; 538 break; 539 case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL: 540 frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t); 541 func_str = "sas_iounit_ctl"; 542 break; 543 case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR: 544 frame_sz = sizeof(Mpi2SepRequest_t); 545 func_str = "enclosure"; 546 break; 547 case MPI2_FUNCTION_IOC_INIT: 548 frame_sz = sizeof(Mpi2IOCInitRequest_t); 549 func_str = "ioc_init"; 550 break; 551 case MPI2_FUNCTION_PORT_ENABLE: 552 frame_sz = sizeof(Mpi2PortEnableRequest_t); 553 func_str = "port_enable"; 554 break; 555 case MPI2_FUNCTION_SMP_PASSTHROUGH: 556 frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size; 557 func_str = "smp_passthru"; 558 break; 559 default: 560 frame_sz = 32; 561 func_str = "unknown"; 562 break; 563 } 564 565 pr_warn(MPT3SAS_FMT "ioc_status: %s(0x%04x), request(0x%p),(%s)\n", 566 ioc->name, desc, ioc_status, request_hdr, func_str); 567 568 _debug_dump_mf(request_hdr, frame_sz/4); 569 } 570 571 /** 572 * _base_display_event_data - verbose translation of firmware asyn events 573 * @ioc: per adapter object 574 * @mpi_reply: reply mf payload returned from firmware 575 * 576 * Return nothing. 577 */ 578 static void 579 _base_display_event_data(struct MPT3SAS_ADAPTER *ioc, 580 Mpi2EventNotificationReply_t *mpi_reply) 581 { 582 char *desc = NULL; 583 u16 event; 584 585 if (!(ioc->logging_level & MPT_DEBUG_EVENTS)) 586 return; 587 588 event = le16_to_cpu(mpi_reply->Event); 589 590 switch (event) { 591 case MPI2_EVENT_LOG_DATA: 592 desc = "Log Data"; 593 break; 594 case MPI2_EVENT_STATE_CHANGE: 595 desc = "Status Change"; 596 break; 597 case MPI2_EVENT_HARD_RESET_RECEIVED: 598 desc = "Hard Reset Received"; 599 break; 600 case MPI2_EVENT_EVENT_CHANGE: 601 desc = "Event Change"; 602 break; 603 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE: 604 desc = "Device Status Change"; 605 break; 606 case MPI2_EVENT_IR_OPERATION_STATUS: 607 if (!ioc->hide_ir_msg) 608 desc = "IR Operation Status"; 609 break; 610 case MPI2_EVENT_SAS_DISCOVERY: 611 { 612 Mpi2EventDataSasDiscovery_t *event_data = 613 (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData; 614 pr_info(MPT3SAS_FMT "Discovery: (%s)", ioc->name, 615 (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ? 616 "start" : "stop"); 617 if (event_data->DiscoveryStatus) 618 pr_cont(" discovery_status(0x%08x)", 619 le32_to_cpu(event_data->DiscoveryStatus)); 620 pr_cont("\n"); 621 return; 622 } 623 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE: 624 desc = "SAS Broadcast Primitive"; 625 break; 626 case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE: 627 desc = "SAS Init Device Status Change"; 628 break; 629 case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW: 630 desc = "SAS Init Table Overflow"; 631 break; 632 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 633 desc = "SAS Topology Change List"; 634 break; 635 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE: 636 desc = "SAS Enclosure Device Status Change"; 637 break; 638 case MPI2_EVENT_IR_VOLUME: 639 if (!ioc->hide_ir_msg) 640 desc = "IR Volume"; 641 break; 642 case MPI2_EVENT_IR_PHYSICAL_DISK: 643 if (!ioc->hide_ir_msg) 644 desc = "IR Physical Disk"; 645 break; 646 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST: 647 if (!ioc->hide_ir_msg) 648 desc = "IR Configuration Change List"; 649 break; 650 case MPI2_EVENT_LOG_ENTRY_ADDED: 651 if (!ioc->hide_ir_msg) 652 desc = "Log Entry Added"; 653 break; 654 case MPI2_EVENT_TEMP_THRESHOLD: 655 desc = "Temperature Threshold"; 656 break; 657 case MPI2_EVENT_ACTIVE_CABLE_EXCEPTION: 658 desc = "Active cable exception"; 659 break; 660 } 661 662 if (!desc) 663 return; 664 665 pr_info(MPT3SAS_FMT "%s\n", ioc->name, desc); 666 } 667 668 /** 669 * _base_sas_log_info - verbose translation of firmware log info 670 * @ioc: per adapter object 671 * @log_info: log info 672 * 673 * Return nothing. 674 */ 675 static void 676 _base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info) 677 { 678 union loginfo_type { 679 u32 loginfo; 680 struct { 681 u32 subcode:16; 682 u32 code:8; 683 u32 originator:4; 684 u32 bus_type:4; 685 } dw; 686 }; 687 union loginfo_type sas_loginfo; 688 char *originator_str = NULL; 689 690 sas_loginfo.loginfo = log_info; 691 if (sas_loginfo.dw.bus_type != 3 /*SAS*/) 692 return; 693 694 /* each nexus loss loginfo */ 695 if (log_info == 0x31170000) 696 return; 697 698 /* eat the loginfos associated with task aborts */ 699 if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info == 700 0x31140000 || log_info == 0x31130000)) 701 return; 702 703 switch (sas_loginfo.dw.originator) { 704 case 0: 705 originator_str = "IOP"; 706 break; 707 case 1: 708 originator_str = "PL"; 709 break; 710 case 2: 711 if (!ioc->hide_ir_msg) 712 originator_str = "IR"; 713 else 714 originator_str = "WarpDrive"; 715 break; 716 } 717 718 pr_warn(MPT3SAS_FMT 719 "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n", 720 ioc->name, log_info, 721 originator_str, sas_loginfo.dw.code, 722 sas_loginfo.dw.subcode); 723 } 724 725 /** 726 * _base_display_reply_info - 727 * @ioc: per adapter object 728 * @smid: system request message index 729 * @msix_index: MSIX table index supplied by the OS 730 * @reply: reply message frame(lower 32bit addr) 731 * 732 * Return nothing. 733 */ 734 static void 735 _base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, 736 u32 reply) 737 { 738 MPI2DefaultReply_t *mpi_reply; 739 u16 ioc_status; 740 u32 loginfo = 0; 741 742 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); 743 if (unlikely(!mpi_reply)) { 744 pr_err(MPT3SAS_FMT "mpi_reply not valid at %s:%d/%s()!\n", 745 ioc->name, __FILE__, __LINE__, __func__); 746 return; 747 } 748 ioc_status = le16_to_cpu(mpi_reply->IOCStatus); 749 750 if ((ioc_status & MPI2_IOCSTATUS_MASK) && 751 (ioc->logging_level & MPT_DEBUG_REPLY)) { 752 _base_sas_ioc_info(ioc , mpi_reply, 753 mpt3sas_base_get_msg_frame(ioc, smid)); 754 } 755 756 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 757 loginfo = le32_to_cpu(mpi_reply->IOCLogInfo); 758 _base_sas_log_info(ioc, loginfo); 759 } 760 761 if (ioc_status || loginfo) { 762 ioc_status &= MPI2_IOCSTATUS_MASK; 763 mpt3sas_trigger_mpi(ioc, ioc_status, loginfo); 764 } 765 } 766 767 /** 768 * mpt3sas_base_done - base internal command completion routine 769 * @ioc: per adapter object 770 * @smid: system request message index 771 * @msix_index: MSIX table index supplied by the OS 772 * @reply: reply message frame(lower 32bit addr) 773 * 774 * Return 1 meaning mf should be freed from _base_interrupt 775 * 0 means the mf is freed from this function. 776 */ 777 u8 778 mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, 779 u32 reply) 780 { 781 MPI2DefaultReply_t *mpi_reply; 782 783 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); 784 if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK) 785 return mpt3sas_check_for_pending_internal_cmds(ioc, smid); 786 787 if (ioc->base_cmds.status == MPT3_CMD_NOT_USED) 788 return 1; 789 790 ioc->base_cmds.status |= MPT3_CMD_COMPLETE; 791 if (mpi_reply) { 792 ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID; 793 memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4); 794 } 795 ioc->base_cmds.status &= ~MPT3_CMD_PENDING; 796 797 complete(&ioc->base_cmds.done); 798 return 1; 799 } 800 801 /** 802 * _base_async_event - main callback handler for firmware asyn events 803 * @ioc: per adapter object 804 * @msix_index: MSIX table index supplied by the OS 805 * @reply: reply message frame(lower 32bit addr) 806 * 807 * Return 1 meaning mf should be freed from _base_interrupt 808 * 0 means the mf is freed from this function. 809 */ 810 static u8 811 _base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply) 812 { 813 Mpi2EventNotificationReply_t *mpi_reply; 814 Mpi2EventAckRequest_t *ack_request; 815 u16 smid; 816 struct _event_ack_list *delayed_event_ack; 817 818 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); 819 if (!mpi_reply) 820 return 1; 821 if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION) 822 return 1; 823 824 _base_display_event_data(ioc, mpi_reply); 825 826 if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED)) 827 goto out; 828 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 829 if (!smid) { 830 delayed_event_ack = kzalloc(sizeof(*delayed_event_ack), 831 GFP_ATOMIC); 832 if (!delayed_event_ack) 833 goto out; 834 INIT_LIST_HEAD(&delayed_event_ack->list); 835 delayed_event_ack->Event = mpi_reply->Event; 836 delayed_event_ack->EventContext = mpi_reply->EventContext; 837 list_add_tail(&delayed_event_ack->list, 838 &ioc->delayed_event_ack_list); 839 dewtprintk(ioc, pr_info(MPT3SAS_FMT 840 "DELAYED: EVENT ACK: event (0x%04x)\n", 841 ioc->name, le16_to_cpu(mpi_reply->Event))); 842 goto out; 843 } 844 845 ack_request = mpt3sas_base_get_msg_frame(ioc, smid); 846 memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t)); 847 ack_request->Function = MPI2_FUNCTION_EVENT_ACK; 848 ack_request->Event = mpi_reply->Event; 849 ack_request->EventContext = mpi_reply->EventContext; 850 ack_request->VF_ID = 0; /* TODO */ 851 ack_request->VP_ID = 0; 852 ioc->put_smid_default(ioc, smid); 853 854 out: 855 856 /* scsih callback handler */ 857 mpt3sas_scsih_event_callback(ioc, msix_index, reply); 858 859 /* ctl callback handler */ 860 mpt3sas_ctl_event_callback(ioc, msix_index, reply); 861 862 return 1; 863 } 864 865 /** 866 * _base_get_cb_idx - obtain the callback index 867 * @ioc: per adapter object 868 * @smid: system request message index 869 * 870 * Return callback index. 871 */ 872 static u8 873 _base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid) 874 { 875 int i; 876 u8 cb_idx; 877 878 if (smid < ioc->hi_priority_smid) { 879 i = smid - 1; 880 cb_idx = ioc->scsi_lookup[i].cb_idx; 881 } else if (smid < ioc->internal_smid) { 882 i = smid - ioc->hi_priority_smid; 883 cb_idx = ioc->hpr_lookup[i].cb_idx; 884 } else if (smid <= ioc->hba_queue_depth) { 885 i = smid - ioc->internal_smid; 886 cb_idx = ioc->internal_lookup[i].cb_idx; 887 } else 888 cb_idx = 0xFF; 889 return cb_idx; 890 } 891 892 /** 893 * _base_mask_interrupts - disable interrupts 894 * @ioc: per adapter object 895 * 896 * Disabling ResetIRQ, Reply and Doorbell Interrupts 897 * 898 * Return nothing. 899 */ 900 static void 901 _base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc) 902 { 903 u32 him_register; 904 905 ioc->mask_interrupts = 1; 906 him_register = readl(&ioc->chip->HostInterruptMask); 907 him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK; 908 writel(him_register, &ioc->chip->HostInterruptMask); 909 readl(&ioc->chip->HostInterruptMask); 910 } 911 912 /** 913 * _base_unmask_interrupts - enable interrupts 914 * @ioc: per adapter object 915 * 916 * Enabling only Reply Interrupts 917 * 918 * Return nothing. 919 */ 920 static void 921 _base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc) 922 { 923 u32 him_register; 924 925 him_register = readl(&ioc->chip->HostInterruptMask); 926 him_register &= ~MPI2_HIM_RIM; 927 writel(him_register, &ioc->chip->HostInterruptMask); 928 ioc->mask_interrupts = 0; 929 } 930 931 union reply_descriptor { 932 u64 word; 933 struct { 934 u32 low; 935 u32 high; 936 } u; 937 }; 938 939 /** 940 * _base_interrupt - MPT adapter (IOC) specific interrupt handler. 941 * @irq: irq number (not used) 942 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure 943 * @r: pt_regs pointer (not used) 944 * 945 * Return IRQ_HANDLE if processed, else IRQ_NONE. 946 */ 947 static irqreturn_t 948 _base_interrupt(int irq, void *bus_id) 949 { 950 struct adapter_reply_queue *reply_q = bus_id; 951 union reply_descriptor rd; 952 u32 completed_cmds; 953 u8 request_desript_type; 954 u16 smid; 955 u8 cb_idx; 956 u32 reply; 957 u8 msix_index = reply_q->msix_index; 958 struct MPT3SAS_ADAPTER *ioc = reply_q->ioc; 959 Mpi2ReplyDescriptorsUnion_t *rpf; 960 u8 rc; 961 962 if (ioc->mask_interrupts) 963 return IRQ_NONE; 964 965 if (!atomic_add_unless(&reply_q->busy, 1, 1)) 966 return IRQ_NONE; 967 968 rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index]; 969 request_desript_type = rpf->Default.ReplyFlags 970 & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 971 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) { 972 atomic_dec(&reply_q->busy); 973 return IRQ_NONE; 974 } 975 976 completed_cmds = 0; 977 cb_idx = 0xFF; 978 do { 979 rd.word = le64_to_cpu(rpf->Words); 980 if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX) 981 goto out; 982 reply = 0; 983 smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1); 984 if (request_desript_type == 985 MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS || 986 request_desript_type == 987 MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) { 988 cb_idx = _base_get_cb_idx(ioc, smid); 989 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) && 990 (likely(mpt_callbacks[cb_idx] != NULL))) { 991 rc = mpt_callbacks[cb_idx](ioc, smid, 992 msix_index, 0); 993 if (rc) 994 mpt3sas_base_free_smid(ioc, smid); 995 } 996 } else if (request_desript_type == 997 MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) { 998 reply = le32_to_cpu( 999 rpf->AddressReply.ReplyFrameAddress); 1000 if (reply > ioc->reply_dma_max_address || 1001 reply < ioc->reply_dma_min_address) 1002 reply = 0; 1003 if (smid) { 1004 cb_idx = _base_get_cb_idx(ioc, smid); 1005 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) && 1006 (likely(mpt_callbacks[cb_idx] != NULL))) { 1007 rc = mpt_callbacks[cb_idx](ioc, smid, 1008 msix_index, reply); 1009 if (reply) 1010 _base_display_reply_info(ioc, 1011 smid, msix_index, reply); 1012 if (rc) 1013 mpt3sas_base_free_smid(ioc, 1014 smid); 1015 } 1016 } else { 1017 _base_async_event(ioc, msix_index, reply); 1018 } 1019 1020 /* reply free queue handling */ 1021 if (reply) { 1022 ioc->reply_free_host_index = 1023 (ioc->reply_free_host_index == 1024 (ioc->reply_free_queue_depth - 1)) ? 1025 0 : ioc->reply_free_host_index + 1; 1026 ioc->reply_free[ioc->reply_free_host_index] = 1027 cpu_to_le32(reply); 1028 writel(ioc->reply_free_host_index, 1029 &ioc->chip->ReplyFreeHostIndex); 1030 } 1031 } 1032 1033 rpf->Words = cpu_to_le64(ULLONG_MAX); 1034 reply_q->reply_post_host_index = 1035 (reply_q->reply_post_host_index == 1036 (ioc->reply_post_queue_depth - 1)) ? 0 : 1037 reply_q->reply_post_host_index + 1; 1038 request_desript_type = 1039 reply_q->reply_post_free[reply_q->reply_post_host_index]. 1040 Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 1041 completed_cmds++; 1042 /* Update the reply post host index after continuously 1043 * processing the threshold number of Reply Descriptors. 1044 * So that FW can find enough entries to post the Reply 1045 * Descriptors in the reply descriptor post queue. 1046 */ 1047 if (completed_cmds > ioc->hba_queue_depth/3) { 1048 if (ioc->combined_reply_queue) { 1049 writel(reply_q->reply_post_host_index | 1050 ((msix_index & 7) << 1051 MPI2_RPHI_MSIX_INDEX_SHIFT), 1052 ioc->replyPostRegisterIndex[msix_index/8]); 1053 } else { 1054 writel(reply_q->reply_post_host_index | 1055 (msix_index << 1056 MPI2_RPHI_MSIX_INDEX_SHIFT), 1057 &ioc->chip->ReplyPostHostIndex); 1058 } 1059 completed_cmds = 1; 1060 } 1061 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) 1062 goto out; 1063 if (!reply_q->reply_post_host_index) 1064 rpf = reply_q->reply_post_free; 1065 else 1066 rpf++; 1067 } while (1); 1068 1069 out: 1070 1071 if (!completed_cmds) { 1072 atomic_dec(&reply_q->busy); 1073 return IRQ_NONE; 1074 } 1075 1076 if (ioc->is_warpdrive) { 1077 writel(reply_q->reply_post_host_index, 1078 ioc->reply_post_host_index[msix_index]); 1079 atomic_dec(&reply_q->busy); 1080 return IRQ_HANDLED; 1081 } 1082 1083 /* Update Reply Post Host Index. 1084 * For those HBA's which support combined reply queue feature 1085 * 1. Get the correct Supplemental Reply Post Host Index Register. 1086 * i.e. (msix_index / 8)th entry from Supplemental Reply Post Host 1087 * Index Register address bank i.e replyPostRegisterIndex[], 1088 * 2. Then update this register with new reply host index value 1089 * in ReplyPostIndex field and the MSIxIndex field with 1090 * msix_index value reduced to a value between 0 and 7, 1091 * using a modulo 8 operation. Since each Supplemental Reply Post 1092 * Host Index Register supports 8 MSI-X vectors. 1093 * 1094 * For other HBA's just update the Reply Post Host Index register with 1095 * new reply host index value in ReplyPostIndex Field and msix_index 1096 * value in MSIxIndex field. 1097 */ 1098 if (ioc->combined_reply_queue) 1099 writel(reply_q->reply_post_host_index | ((msix_index & 7) << 1100 MPI2_RPHI_MSIX_INDEX_SHIFT), 1101 ioc->replyPostRegisterIndex[msix_index/8]); 1102 else 1103 writel(reply_q->reply_post_host_index | (msix_index << 1104 MPI2_RPHI_MSIX_INDEX_SHIFT), 1105 &ioc->chip->ReplyPostHostIndex); 1106 atomic_dec(&reply_q->busy); 1107 return IRQ_HANDLED; 1108 } 1109 1110 /** 1111 * _base_is_controller_msix_enabled - is controller support muli-reply queues 1112 * @ioc: per adapter object 1113 * 1114 */ 1115 static inline int 1116 _base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc) 1117 { 1118 return (ioc->facts.IOCCapabilities & 1119 MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable; 1120 } 1121 1122 /** 1123 * mpt3sas_base_sync_reply_irqs - flush pending MSIX interrupts 1124 * @ioc: per adapter object 1125 * Context: non ISR conext 1126 * 1127 * Called when a Task Management request has completed. 1128 * 1129 * Return nothing. 1130 */ 1131 void 1132 mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc) 1133 { 1134 struct adapter_reply_queue *reply_q; 1135 1136 /* If MSIX capability is turned off 1137 * then multi-queues are not enabled 1138 */ 1139 if (!_base_is_controller_msix_enabled(ioc)) 1140 return; 1141 1142 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 1143 if (ioc->shost_recovery || ioc->remove_host || 1144 ioc->pci_error_recovery) 1145 return; 1146 /* TMs are on msix_index == 0 */ 1147 if (reply_q->msix_index == 0) 1148 continue; 1149 synchronize_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index)); 1150 } 1151 } 1152 1153 /** 1154 * mpt3sas_base_release_callback_handler - clear interrupt callback handler 1155 * @cb_idx: callback index 1156 * 1157 * Return nothing. 1158 */ 1159 void 1160 mpt3sas_base_release_callback_handler(u8 cb_idx) 1161 { 1162 mpt_callbacks[cb_idx] = NULL; 1163 } 1164 1165 /** 1166 * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler 1167 * @cb_func: callback function 1168 * 1169 * Returns cb_func. 1170 */ 1171 u8 1172 mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func) 1173 { 1174 u8 cb_idx; 1175 1176 for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--) 1177 if (mpt_callbacks[cb_idx] == NULL) 1178 break; 1179 1180 mpt_callbacks[cb_idx] = cb_func; 1181 return cb_idx; 1182 } 1183 1184 /** 1185 * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler 1186 * 1187 * Return nothing. 1188 */ 1189 void 1190 mpt3sas_base_initialize_callback_handler(void) 1191 { 1192 u8 cb_idx; 1193 1194 for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++) 1195 mpt3sas_base_release_callback_handler(cb_idx); 1196 } 1197 1198 1199 /** 1200 * _base_build_zero_len_sge - build zero length sg entry 1201 * @ioc: per adapter object 1202 * @paddr: virtual address for SGE 1203 * 1204 * Create a zero length scatter gather entry to insure the IOCs hardware has 1205 * something to use if the target device goes brain dead and tries 1206 * to send data even when none is asked for. 1207 * 1208 * Return nothing. 1209 */ 1210 static void 1211 _base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr) 1212 { 1213 u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT | 1214 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST | 1215 MPI2_SGE_FLAGS_SIMPLE_ELEMENT) << 1216 MPI2_SGE_FLAGS_SHIFT); 1217 ioc->base_add_sg_single(paddr, flags_length, -1); 1218 } 1219 1220 /** 1221 * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr. 1222 * @paddr: virtual address for SGE 1223 * @flags_length: SGE flags and data transfer length 1224 * @dma_addr: Physical address 1225 * 1226 * Return nothing. 1227 */ 1228 static void 1229 _base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr) 1230 { 1231 Mpi2SGESimple32_t *sgel = paddr; 1232 1233 flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING | 1234 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT; 1235 sgel->FlagsLength = cpu_to_le32(flags_length); 1236 sgel->Address = cpu_to_le32(dma_addr); 1237 } 1238 1239 1240 /** 1241 * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr. 1242 * @paddr: virtual address for SGE 1243 * @flags_length: SGE flags and data transfer length 1244 * @dma_addr: Physical address 1245 * 1246 * Return nothing. 1247 */ 1248 static void 1249 _base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr) 1250 { 1251 Mpi2SGESimple64_t *sgel = paddr; 1252 1253 flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING | 1254 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT; 1255 sgel->FlagsLength = cpu_to_le32(flags_length); 1256 sgel->Address = cpu_to_le64(dma_addr); 1257 } 1258 1259 /** 1260 * _base_get_chain_buffer_tracker - obtain chain tracker 1261 * @ioc: per adapter object 1262 * @smid: smid associated to an IO request 1263 * 1264 * Returns chain tracker(from ioc->free_chain_list) 1265 */ 1266 static struct chain_tracker * 1267 _base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc, u16 smid) 1268 { 1269 struct chain_tracker *chain_req; 1270 unsigned long flags; 1271 1272 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 1273 if (list_empty(&ioc->free_chain_list)) { 1274 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 1275 dfailprintk(ioc, pr_warn(MPT3SAS_FMT 1276 "chain buffers not available\n", ioc->name)); 1277 return NULL; 1278 } 1279 chain_req = list_entry(ioc->free_chain_list.next, 1280 struct chain_tracker, tracker_list); 1281 list_del_init(&chain_req->tracker_list); 1282 list_add_tail(&chain_req->tracker_list, 1283 &ioc->scsi_lookup[smid - 1].chain_list); 1284 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 1285 return chain_req; 1286 } 1287 1288 1289 /** 1290 * _base_build_sg - build generic sg 1291 * @ioc: per adapter object 1292 * @psge: virtual address for SGE 1293 * @data_out_dma: physical address for WRITES 1294 * @data_out_sz: data xfer size for WRITES 1295 * @data_in_dma: physical address for READS 1296 * @data_in_sz: data xfer size for READS 1297 * 1298 * Return nothing. 1299 */ 1300 static void 1301 _base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge, 1302 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma, 1303 size_t data_in_sz) 1304 { 1305 u32 sgl_flags; 1306 1307 if (!data_out_sz && !data_in_sz) { 1308 _base_build_zero_len_sge(ioc, psge); 1309 return; 1310 } 1311 1312 if (data_out_sz && data_in_sz) { 1313 /* WRITE sgel first */ 1314 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 1315 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC); 1316 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 1317 ioc->base_add_sg_single(psge, sgl_flags | 1318 data_out_sz, data_out_dma); 1319 1320 /* incr sgel */ 1321 psge += ioc->sge_size; 1322 1323 /* READ sgel last */ 1324 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 1325 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | 1326 MPI2_SGE_FLAGS_END_OF_LIST); 1327 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 1328 ioc->base_add_sg_single(psge, sgl_flags | 1329 data_in_sz, data_in_dma); 1330 } else if (data_out_sz) /* WRITE */ { 1331 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 1332 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | 1333 MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC); 1334 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 1335 ioc->base_add_sg_single(psge, sgl_flags | 1336 data_out_sz, data_out_dma); 1337 } else if (data_in_sz) /* READ */ { 1338 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 1339 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | 1340 MPI2_SGE_FLAGS_END_OF_LIST); 1341 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 1342 ioc->base_add_sg_single(psge, sgl_flags | 1343 data_in_sz, data_in_dma); 1344 } 1345 } 1346 1347 /* IEEE format sgls */ 1348 1349 /** 1350 * _base_add_sg_single_ieee - add sg element for IEEE format 1351 * @paddr: virtual address for SGE 1352 * @flags: SGE flags 1353 * @chain_offset: number of 128 byte elements from start of segment 1354 * @length: data transfer length 1355 * @dma_addr: Physical address 1356 * 1357 * Return nothing. 1358 */ 1359 static void 1360 _base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length, 1361 dma_addr_t dma_addr) 1362 { 1363 Mpi25IeeeSgeChain64_t *sgel = paddr; 1364 1365 sgel->Flags = flags; 1366 sgel->NextChainOffset = chain_offset; 1367 sgel->Length = cpu_to_le32(length); 1368 sgel->Address = cpu_to_le64(dma_addr); 1369 } 1370 1371 /** 1372 * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format 1373 * @ioc: per adapter object 1374 * @paddr: virtual address for SGE 1375 * 1376 * Create a zero length scatter gather entry to insure the IOCs hardware has 1377 * something to use if the target device goes brain dead and tries 1378 * to send data even when none is asked for. 1379 * 1380 * Return nothing. 1381 */ 1382 static void 1383 _base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr) 1384 { 1385 u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 1386 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR | 1387 MPI25_IEEE_SGE_FLAGS_END_OF_LIST); 1388 1389 _base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1); 1390 } 1391 1392 /** 1393 * _base_build_sg_scmd - main sg creation routine 1394 * @ioc: per adapter object 1395 * @scmd: scsi command 1396 * @smid: system request message index 1397 * Context: none. 1398 * 1399 * The main routine that builds scatter gather table from a given 1400 * scsi request sent via the .queuecommand main handler. 1401 * 1402 * Returns 0 success, anything else error 1403 */ 1404 static int 1405 _base_build_sg_scmd(struct MPT3SAS_ADAPTER *ioc, 1406 struct scsi_cmnd *scmd, u16 smid) 1407 { 1408 Mpi2SCSIIORequest_t *mpi_request; 1409 dma_addr_t chain_dma; 1410 struct scatterlist *sg_scmd; 1411 void *sg_local, *chain; 1412 u32 chain_offset; 1413 u32 chain_length; 1414 u32 chain_flags; 1415 int sges_left; 1416 u32 sges_in_segment; 1417 u32 sgl_flags; 1418 u32 sgl_flags_last_element; 1419 u32 sgl_flags_end_buffer; 1420 struct chain_tracker *chain_req; 1421 1422 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 1423 1424 /* init scatter gather flags */ 1425 sgl_flags = MPI2_SGE_FLAGS_SIMPLE_ELEMENT; 1426 if (scmd->sc_data_direction == DMA_TO_DEVICE) 1427 sgl_flags |= MPI2_SGE_FLAGS_HOST_TO_IOC; 1428 sgl_flags_last_element = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT) 1429 << MPI2_SGE_FLAGS_SHIFT; 1430 sgl_flags_end_buffer = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT | 1431 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST) 1432 << MPI2_SGE_FLAGS_SHIFT; 1433 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 1434 1435 sg_scmd = scsi_sglist(scmd); 1436 sges_left = scsi_dma_map(scmd); 1437 if (sges_left < 0) { 1438 sdev_printk(KERN_ERR, scmd->device, 1439 "pci_map_sg failed: request for %d bytes!\n", 1440 scsi_bufflen(scmd)); 1441 return -ENOMEM; 1442 } 1443 1444 sg_local = &mpi_request->SGL; 1445 sges_in_segment = ioc->max_sges_in_main_message; 1446 if (sges_left <= sges_in_segment) 1447 goto fill_in_last_segment; 1448 1449 mpi_request->ChainOffset = (offsetof(Mpi2SCSIIORequest_t, SGL) + 1450 (sges_in_segment * ioc->sge_size))/4; 1451 1452 /* fill in main message segment when there is a chain following */ 1453 while (sges_in_segment) { 1454 if (sges_in_segment == 1) 1455 ioc->base_add_sg_single(sg_local, 1456 sgl_flags_last_element | sg_dma_len(sg_scmd), 1457 sg_dma_address(sg_scmd)); 1458 else 1459 ioc->base_add_sg_single(sg_local, sgl_flags | 1460 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 1461 sg_scmd = sg_next(sg_scmd); 1462 sg_local += ioc->sge_size; 1463 sges_left--; 1464 sges_in_segment--; 1465 } 1466 1467 /* initializing the chain flags and pointers */ 1468 chain_flags = MPI2_SGE_FLAGS_CHAIN_ELEMENT << MPI2_SGE_FLAGS_SHIFT; 1469 chain_req = _base_get_chain_buffer_tracker(ioc, smid); 1470 if (!chain_req) 1471 return -1; 1472 chain = chain_req->chain_buffer; 1473 chain_dma = chain_req->chain_buffer_dma; 1474 do { 1475 sges_in_segment = (sges_left <= 1476 ioc->max_sges_in_chain_message) ? sges_left : 1477 ioc->max_sges_in_chain_message; 1478 chain_offset = (sges_left == sges_in_segment) ? 1479 0 : (sges_in_segment * ioc->sge_size)/4; 1480 chain_length = sges_in_segment * ioc->sge_size; 1481 if (chain_offset) { 1482 chain_offset = chain_offset << 1483 MPI2_SGE_CHAIN_OFFSET_SHIFT; 1484 chain_length += ioc->sge_size; 1485 } 1486 ioc->base_add_sg_single(sg_local, chain_flags | chain_offset | 1487 chain_length, chain_dma); 1488 sg_local = chain; 1489 if (!chain_offset) 1490 goto fill_in_last_segment; 1491 1492 /* fill in chain segments */ 1493 while (sges_in_segment) { 1494 if (sges_in_segment == 1) 1495 ioc->base_add_sg_single(sg_local, 1496 sgl_flags_last_element | 1497 sg_dma_len(sg_scmd), 1498 sg_dma_address(sg_scmd)); 1499 else 1500 ioc->base_add_sg_single(sg_local, sgl_flags | 1501 sg_dma_len(sg_scmd), 1502 sg_dma_address(sg_scmd)); 1503 sg_scmd = sg_next(sg_scmd); 1504 sg_local += ioc->sge_size; 1505 sges_left--; 1506 sges_in_segment--; 1507 } 1508 1509 chain_req = _base_get_chain_buffer_tracker(ioc, smid); 1510 if (!chain_req) 1511 return -1; 1512 chain = chain_req->chain_buffer; 1513 chain_dma = chain_req->chain_buffer_dma; 1514 } while (1); 1515 1516 1517 fill_in_last_segment: 1518 1519 /* fill the last segment */ 1520 while (sges_left) { 1521 if (sges_left == 1) 1522 ioc->base_add_sg_single(sg_local, sgl_flags_end_buffer | 1523 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 1524 else 1525 ioc->base_add_sg_single(sg_local, sgl_flags | 1526 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 1527 sg_scmd = sg_next(sg_scmd); 1528 sg_local += ioc->sge_size; 1529 sges_left--; 1530 } 1531 1532 return 0; 1533 } 1534 1535 /** 1536 * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format 1537 * @ioc: per adapter object 1538 * @scmd: scsi command 1539 * @smid: system request message index 1540 * Context: none. 1541 * 1542 * The main routine that builds scatter gather table from a given 1543 * scsi request sent via the .queuecommand main handler. 1544 * 1545 * Returns 0 success, anything else error 1546 */ 1547 static int 1548 _base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc, 1549 struct scsi_cmnd *scmd, u16 smid) 1550 { 1551 Mpi2SCSIIORequest_t *mpi_request; 1552 dma_addr_t chain_dma; 1553 struct scatterlist *sg_scmd; 1554 void *sg_local, *chain; 1555 u32 chain_offset; 1556 u32 chain_length; 1557 int sges_left; 1558 u32 sges_in_segment; 1559 u8 simple_sgl_flags; 1560 u8 simple_sgl_flags_last; 1561 u8 chain_sgl_flags; 1562 struct chain_tracker *chain_req; 1563 1564 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 1565 1566 /* init scatter gather flags */ 1567 simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 1568 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 1569 simple_sgl_flags_last = simple_sgl_flags | 1570 MPI25_IEEE_SGE_FLAGS_END_OF_LIST; 1571 chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | 1572 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 1573 1574 sg_scmd = scsi_sglist(scmd); 1575 sges_left = scsi_dma_map(scmd); 1576 if (sges_left < 0) { 1577 sdev_printk(KERN_ERR, scmd->device, 1578 "pci_map_sg failed: request for %d bytes!\n", 1579 scsi_bufflen(scmd)); 1580 return -ENOMEM; 1581 } 1582 1583 sg_local = &mpi_request->SGL; 1584 sges_in_segment = (ioc->request_sz - 1585 offsetof(Mpi2SCSIIORequest_t, SGL))/ioc->sge_size_ieee; 1586 if (sges_left <= sges_in_segment) 1587 goto fill_in_last_segment; 1588 1589 mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) + 1590 (offsetof(Mpi2SCSIIORequest_t, SGL)/ioc->sge_size_ieee); 1591 1592 /* fill in main message segment when there is a chain following */ 1593 while (sges_in_segment > 1) { 1594 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, 1595 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 1596 sg_scmd = sg_next(sg_scmd); 1597 sg_local += ioc->sge_size_ieee; 1598 sges_left--; 1599 sges_in_segment--; 1600 } 1601 1602 /* initializing the pointers */ 1603 chain_req = _base_get_chain_buffer_tracker(ioc, smid); 1604 if (!chain_req) 1605 return -1; 1606 chain = chain_req->chain_buffer; 1607 chain_dma = chain_req->chain_buffer_dma; 1608 do { 1609 sges_in_segment = (sges_left <= 1610 ioc->max_sges_in_chain_message) ? sges_left : 1611 ioc->max_sges_in_chain_message; 1612 chain_offset = (sges_left == sges_in_segment) ? 1613 0 : sges_in_segment; 1614 chain_length = sges_in_segment * ioc->sge_size_ieee; 1615 if (chain_offset) 1616 chain_length += ioc->sge_size_ieee; 1617 _base_add_sg_single_ieee(sg_local, chain_sgl_flags, 1618 chain_offset, chain_length, chain_dma); 1619 1620 sg_local = chain; 1621 if (!chain_offset) 1622 goto fill_in_last_segment; 1623 1624 /* fill in chain segments */ 1625 while (sges_in_segment) { 1626 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, 1627 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 1628 sg_scmd = sg_next(sg_scmd); 1629 sg_local += ioc->sge_size_ieee; 1630 sges_left--; 1631 sges_in_segment--; 1632 } 1633 1634 chain_req = _base_get_chain_buffer_tracker(ioc, smid); 1635 if (!chain_req) 1636 return -1; 1637 chain = chain_req->chain_buffer; 1638 chain_dma = chain_req->chain_buffer_dma; 1639 } while (1); 1640 1641 1642 fill_in_last_segment: 1643 1644 /* fill the last segment */ 1645 while (sges_left > 0) { 1646 if (sges_left == 1) 1647 _base_add_sg_single_ieee(sg_local, 1648 simple_sgl_flags_last, 0, sg_dma_len(sg_scmd), 1649 sg_dma_address(sg_scmd)); 1650 else 1651 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, 1652 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 1653 sg_scmd = sg_next(sg_scmd); 1654 sg_local += ioc->sge_size_ieee; 1655 sges_left--; 1656 } 1657 1658 return 0; 1659 } 1660 1661 /** 1662 * _base_build_sg_ieee - build generic sg for IEEE format 1663 * @ioc: per adapter object 1664 * @psge: virtual address for SGE 1665 * @data_out_dma: physical address for WRITES 1666 * @data_out_sz: data xfer size for WRITES 1667 * @data_in_dma: physical address for READS 1668 * @data_in_sz: data xfer size for READS 1669 * 1670 * Return nothing. 1671 */ 1672 static void 1673 _base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge, 1674 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma, 1675 size_t data_in_sz) 1676 { 1677 u8 sgl_flags; 1678 1679 if (!data_out_sz && !data_in_sz) { 1680 _base_build_zero_len_sge_ieee(ioc, psge); 1681 return; 1682 } 1683 1684 if (data_out_sz && data_in_sz) { 1685 /* WRITE sgel first */ 1686 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 1687 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 1688 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz, 1689 data_out_dma); 1690 1691 /* incr sgel */ 1692 psge += ioc->sge_size_ieee; 1693 1694 /* READ sgel last */ 1695 sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST; 1696 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz, 1697 data_in_dma); 1698 } else if (data_out_sz) /* WRITE */ { 1699 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 1700 MPI25_IEEE_SGE_FLAGS_END_OF_LIST | 1701 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 1702 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz, 1703 data_out_dma); 1704 } else if (data_in_sz) /* READ */ { 1705 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 1706 MPI25_IEEE_SGE_FLAGS_END_OF_LIST | 1707 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 1708 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz, 1709 data_in_dma); 1710 } 1711 } 1712 1713 #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10)) 1714 1715 /** 1716 * _base_config_dma_addressing - set dma addressing 1717 * @ioc: per adapter object 1718 * @pdev: PCI device struct 1719 * 1720 * Returns 0 for success, non-zero for failure. 1721 */ 1722 static int 1723 _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev) 1724 { 1725 struct sysinfo s; 1726 u64 consistent_dma_mask; 1727 1728 if (ioc->dma_mask) 1729 consistent_dma_mask = DMA_BIT_MASK(64); 1730 else 1731 consistent_dma_mask = DMA_BIT_MASK(32); 1732 1733 if (sizeof(dma_addr_t) > 4) { 1734 const uint64_t required_mask = 1735 dma_get_required_mask(&pdev->dev); 1736 if ((required_mask > DMA_BIT_MASK(32)) && 1737 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && 1738 !pci_set_consistent_dma_mask(pdev, consistent_dma_mask)) { 1739 ioc->base_add_sg_single = &_base_add_sg_single_64; 1740 ioc->sge_size = sizeof(Mpi2SGESimple64_t); 1741 ioc->dma_mask = 64; 1742 goto out; 1743 } 1744 } 1745 1746 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) 1747 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { 1748 ioc->base_add_sg_single = &_base_add_sg_single_32; 1749 ioc->sge_size = sizeof(Mpi2SGESimple32_t); 1750 ioc->dma_mask = 32; 1751 } else 1752 return -ENODEV; 1753 1754 out: 1755 si_meminfo(&s); 1756 pr_info(MPT3SAS_FMT 1757 "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n", 1758 ioc->name, ioc->dma_mask, convert_to_kb(s.totalram)); 1759 1760 return 0; 1761 } 1762 1763 static int 1764 _base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc, 1765 struct pci_dev *pdev) 1766 { 1767 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { 1768 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) 1769 return -ENODEV; 1770 } 1771 return 0; 1772 } 1773 1774 /** 1775 * _base_check_enable_msix - checks MSIX capabable. 1776 * @ioc: per adapter object 1777 * 1778 * Check to see if card is capable of MSIX, and set number 1779 * of available msix vectors 1780 */ 1781 static int 1782 _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc) 1783 { 1784 int base; 1785 u16 message_control; 1786 1787 /* Check whether controller SAS2008 B0 controller, 1788 * if it is SAS2008 B0 controller use IO-APIC instead of MSIX 1789 */ 1790 if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 && 1791 ioc->pdev->revision == SAS2_PCI_DEVICE_B0_REVISION) { 1792 return -EINVAL; 1793 } 1794 1795 base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX); 1796 if (!base) { 1797 dfailprintk(ioc, pr_info(MPT3SAS_FMT "msix not supported\n", 1798 ioc->name)); 1799 return -EINVAL; 1800 } 1801 1802 /* get msix vector count */ 1803 /* NUMA_IO not supported for older controllers */ 1804 if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 || 1805 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 || 1806 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 || 1807 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 || 1808 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 || 1809 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 || 1810 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2) 1811 ioc->msix_vector_count = 1; 1812 else { 1813 pci_read_config_word(ioc->pdev, base + 2, &message_control); 1814 ioc->msix_vector_count = (message_control & 0x3FF) + 1; 1815 } 1816 dinitprintk(ioc, pr_info(MPT3SAS_FMT 1817 "msix is supported, vector_count(%d)\n", 1818 ioc->name, ioc->msix_vector_count)); 1819 return 0; 1820 } 1821 1822 /** 1823 * _base_free_irq - free irq 1824 * @ioc: per adapter object 1825 * 1826 * Freeing respective reply_queue from the list. 1827 */ 1828 static void 1829 _base_free_irq(struct MPT3SAS_ADAPTER *ioc) 1830 { 1831 struct adapter_reply_queue *reply_q, *next; 1832 1833 if (list_empty(&ioc->reply_queue_list)) 1834 return; 1835 1836 list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) { 1837 list_del(&reply_q->list); 1838 free_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index), 1839 reply_q); 1840 kfree(reply_q); 1841 } 1842 } 1843 1844 /** 1845 * _base_request_irq - request irq 1846 * @ioc: per adapter object 1847 * @index: msix index into vector table 1848 * 1849 * Inserting respective reply_queue into the list. 1850 */ 1851 static int 1852 _base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index) 1853 { 1854 struct pci_dev *pdev = ioc->pdev; 1855 struct adapter_reply_queue *reply_q; 1856 int r; 1857 1858 reply_q = kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL); 1859 if (!reply_q) { 1860 pr_err(MPT3SAS_FMT "unable to allocate memory %d!\n", 1861 ioc->name, (int)sizeof(struct adapter_reply_queue)); 1862 return -ENOMEM; 1863 } 1864 reply_q->ioc = ioc; 1865 reply_q->msix_index = index; 1866 1867 atomic_set(&reply_q->busy, 0); 1868 if (ioc->msix_enable) 1869 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d", 1870 ioc->driver_name, ioc->id, index); 1871 else 1872 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d", 1873 ioc->driver_name, ioc->id); 1874 r = request_irq(pci_irq_vector(pdev, index), _base_interrupt, 1875 IRQF_SHARED, reply_q->name, reply_q); 1876 if (r) { 1877 pr_err(MPT3SAS_FMT "unable to allocate interrupt %d!\n", 1878 reply_q->name, pci_irq_vector(pdev, index)); 1879 kfree(reply_q); 1880 return -EBUSY; 1881 } 1882 1883 INIT_LIST_HEAD(&reply_q->list); 1884 list_add_tail(&reply_q->list, &ioc->reply_queue_list); 1885 return 0; 1886 } 1887 1888 /** 1889 * _base_assign_reply_queues - assigning msix index for each cpu 1890 * @ioc: per adapter object 1891 * 1892 * The enduser would need to set the affinity via /proc/irq/#/smp_affinity 1893 * 1894 * It would nice if we could call irq_set_affinity, however it is not 1895 * an exported symbol 1896 */ 1897 static void 1898 _base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc) 1899 { 1900 unsigned int cpu, nr_cpus, nr_msix, index = 0; 1901 struct adapter_reply_queue *reply_q; 1902 1903 if (!_base_is_controller_msix_enabled(ioc)) 1904 return; 1905 1906 memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz); 1907 1908 nr_cpus = num_online_cpus(); 1909 nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count, 1910 ioc->facts.MaxMSIxVectors); 1911 if (!nr_msix) 1912 return; 1913 1914 if (smp_affinity_enable) { 1915 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 1916 const cpumask_t *mask = pci_irq_get_affinity(ioc->pdev, 1917 reply_q->msix_index); 1918 if (!mask) { 1919 pr_warn(MPT3SAS_FMT "no affinity for msi %x\n", 1920 ioc->name, reply_q->msix_index); 1921 continue; 1922 } 1923 1924 for_each_cpu(cpu, mask) 1925 ioc->cpu_msix_table[cpu] = reply_q->msix_index; 1926 } 1927 return; 1928 } 1929 cpu = cpumask_first(cpu_online_mask); 1930 1931 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 1932 1933 unsigned int i, group = nr_cpus / nr_msix; 1934 1935 if (cpu >= nr_cpus) 1936 break; 1937 1938 if (index < nr_cpus % nr_msix) 1939 group++; 1940 1941 for (i = 0 ; i < group ; i++) { 1942 ioc->cpu_msix_table[cpu] = reply_q->msix_index; 1943 cpu = cpumask_next(cpu, cpu_online_mask); 1944 } 1945 index++; 1946 } 1947 } 1948 1949 /** 1950 * _base_disable_msix - disables msix 1951 * @ioc: per adapter object 1952 * 1953 */ 1954 static void 1955 _base_disable_msix(struct MPT3SAS_ADAPTER *ioc) 1956 { 1957 if (!ioc->msix_enable) 1958 return; 1959 pci_disable_msix(ioc->pdev); 1960 ioc->msix_enable = 0; 1961 } 1962 1963 /** 1964 * _base_enable_msix - enables msix, failback to io_apic 1965 * @ioc: per adapter object 1966 * 1967 */ 1968 static int 1969 _base_enable_msix(struct MPT3SAS_ADAPTER *ioc) 1970 { 1971 int r; 1972 int i, local_max_msix_vectors; 1973 u8 try_msix = 0; 1974 unsigned int irq_flags = PCI_IRQ_MSIX; 1975 1976 if (msix_disable == -1 || msix_disable == 0) 1977 try_msix = 1; 1978 1979 if (!try_msix) 1980 goto try_ioapic; 1981 1982 if (_base_check_enable_msix(ioc) != 0) 1983 goto try_ioapic; 1984 1985 ioc->reply_queue_count = min_t(int, ioc->cpu_count, 1986 ioc->msix_vector_count); 1987 1988 printk(MPT3SAS_FMT "MSI-X vectors supported: %d, no of cores" 1989 ": %d, max_msix_vectors: %d\n", ioc->name, ioc->msix_vector_count, 1990 ioc->cpu_count, max_msix_vectors); 1991 1992 if (!ioc->rdpq_array_enable && max_msix_vectors == -1) 1993 local_max_msix_vectors = 8; 1994 else 1995 local_max_msix_vectors = max_msix_vectors; 1996 1997 if (local_max_msix_vectors > 0) 1998 ioc->reply_queue_count = min_t(int, local_max_msix_vectors, 1999 ioc->reply_queue_count); 2000 else if (local_max_msix_vectors == 0) 2001 goto try_ioapic; 2002 2003 if (ioc->msix_vector_count < ioc->cpu_count) 2004 smp_affinity_enable = 0; 2005 2006 if (smp_affinity_enable) 2007 irq_flags |= PCI_IRQ_AFFINITY; 2008 2009 r = pci_alloc_irq_vectors(ioc->pdev, 1, ioc->reply_queue_count, 2010 irq_flags); 2011 if (r < 0) { 2012 dfailprintk(ioc, pr_info(MPT3SAS_FMT 2013 "pci_alloc_irq_vectors failed (r=%d) !!!\n", 2014 ioc->name, r)); 2015 goto try_ioapic; 2016 } 2017 2018 ioc->msix_enable = 1; 2019 ioc->reply_queue_count = r; 2020 for (i = 0; i < ioc->reply_queue_count; i++) { 2021 r = _base_request_irq(ioc, i); 2022 if (r) { 2023 _base_free_irq(ioc); 2024 _base_disable_msix(ioc); 2025 goto try_ioapic; 2026 } 2027 } 2028 2029 return 0; 2030 2031 /* failback to io_apic interrupt routing */ 2032 try_ioapic: 2033 2034 ioc->reply_queue_count = 1; 2035 r = pci_alloc_irq_vectors(ioc->pdev, 1, 1, PCI_IRQ_LEGACY); 2036 if (r < 0) { 2037 dfailprintk(ioc, pr_info(MPT3SAS_FMT 2038 "pci_alloc_irq_vector(legacy) failed (r=%d) !!!\n", 2039 ioc->name, r)); 2040 } else 2041 r = _base_request_irq(ioc, 0); 2042 2043 return r; 2044 } 2045 2046 /** 2047 * mpt3sas_base_unmap_resources - free controller resources 2048 * @ioc: per adapter object 2049 */ 2050 static void 2051 mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc) 2052 { 2053 struct pci_dev *pdev = ioc->pdev; 2054 2055 dexitprintk(ioc, printk(MPT3SAS_FMT "%s\n", 2056 ioc->name, __func__)); 2057 2058 _base_free_irq(ioc); 2059 _base_disable_msix(ioc); 2060 2061 if (ioc->combined_reply_queue) { 2062 kfree(ioc->replyPostRegisterIndex); 2063 ioc->replyPostRegisterIndex = NULL; 2064 } 2065 2066 if (ioc->chip_phys) { 2067 iounmap(ioc->chip); 2068 ioc->chip_phys = 0; 2069 } 2070 2071 if (pci_is_enabled(pdev)) { 2072 pci_release_selected_regions(ioc->pdev, ioc->bars); 2073 pci_disable_pcie_error_reporting(pdev); 2074 pci_disable_device(pdev); 2075 } 2076 } 2077 2078 /** 2079 * mpt3sas_base_map_resources - map in controller resources (io/irq/memap) 2080 * @ioc: per adapter object 2081 * 2082 * Returns 0 for success, non-zero for failure. 2083 */ 2084 int 2085 mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc) 2086 { 2087 struct pci_dev *pdev = ioc->pdev; 2088 u32 memap_sz; 2089 u32 pio_sz; 2090 int i, r = 0; 2091 u64 pio_chip = 0; 2092 u64 chip_phys = 0; 2093 struct adapter_reply_queue *reply_q; 2094 2095 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", 2096 ioc->name, __func__)); 2097 2098 ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM); 2099 if (pci_enable_device_mem(pdev)) { 2100 pr_warn(MPT3SAS_FMT "pci_enable_device_mem: failed\n", 2101 ioc->name); 2102 ioc->bars = 0; 2103 return -ENODEV; 2104 } 2105 2106 2107 if (pci_request_selected_regions(pdev, ioc->bars, 2108 ioc->driver_name)) { 2109 pr_warn(MPT3SAS_FMT "pci_request_selected_regions: failed\n", 2110 ioc->name); 2111 ioc->bars = 0; 2112 r = -ENODEV; 2113 goto out_fail; 2114 } 2115 2116 /* AER (Advanced Error Reporting) hooks */ 2117 pci_enable_pcie_error_reporting(pdev); 2118 2119 pci_set_master(pdev); 2120 2121 2122 if (_base_config_dma_addressing(ioc, pdev) != 0) { 2123 pr_warn(MPT3SAS_FMT "no suitable DMA mask for %s\n", 2124 ioc->name, pci_name(pdev)); 2125 r = -ENODEV; 2126 goto out_fail; 2127 } 2128 2129 for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) && 2130 (!memap_sz || !pio_sz); i++) { 2131 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) { 2132 if (pio_sz) 2133 continue; 2134 pio_chip = (u64)pci_resource_start(pdev, i); 2135 pio_sz = pci_resource_len(pdev, i); 2136 } else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) { 2137 if (memap_sz) 2138 continue; 2139 ioc->chip_phys = pci_resource_start(pdev, i); 2140 chip_phys = (u64)ioc->chip_phys; 2141 memap_sz = pci_resource_len(pdev, i); 2142 ioc->chip = ioremap(ioc->chip_phys, memap_sz); 2143 } 2144 } 2145 2146 if (ioc->chip == NULL) { 2147 pr_err(MPT3SAS_FMT "unable to map adapter memory! " 2148 " or resource not found\n", ioc->name); 2149 r = -EINVAL; 2150 goto out_fail; 2151 } 2152 2153 _base_mask_interrupts(ioc); 2154 2155 r = _base_get_ioc_facts(ioc); 2156 if (r) 2157 goto out_fail; 2158 2159 if (!ioc->rdpq_array_enable_assigned) { 2160 ioc->rdpq_array_enable = ioc->rdpq_array_capable; 2161 ioc->rdpq_array_enable_assigned = 1; 2162 } 2163 2164 r = _base_enable_msix(ioc); 2165 if (r) 2166 goto out_fail; 2167 2168 /* Use the Combined reply queue feature only for SAS3 C0 & higher 2169 * revision HBAs and also only when reply queue count is greater than 8 2170 */ 2171 if (ioc->combined_reply_queue && ioc->reply_queue_count > 8) { 2172 /* Determine the Supplemental Reply Post Host Index Registers 2173 * Addresse. Supplemental Reply Post Host Index Registers 2174 * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and 2175 * each register is at offset bytes of 2176 * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one. 2177 */ 2178 ioc->replyPostRegisterIndex = kcalloc( 2179 ioc->combined_reply_index_count, 2180 sizeof(resource_size_t *), GFP_KERNEL); 2181 if (!ioc->replyPostRegisterIndex) { 2182 dfailprintk(ioc, printk(MPT3SAS_FMT 2183 "allocation for reply Post Register Index failed!!!\n", 2184 ioc->name)); 2185 r = -ENOMEM; 2186 goto out_fail; 2187 } 2188 2189 for (i = 0; i < ioc->combined_reply_index_count; i++) { 2190 ioc->replyPostRegisterIndex[i] = (resource_size_t *) 2191 ((u8 *)&ioc->chip->Doorbell + 2192 MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET + 2193 (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET)); 2194 } 2195 } else 2196 ioc->combined_reply_queue = 0; 2197 2198 if (ioc->is_warpdrive) { 2199 ioc->reply_post_host_index[0] = (resource_size_t __iomem *) 2200 &ioc->chip->ReplyPostHostIndex; 2201 2202 for (i = 1; i < ioc->cpu_msix_table_sz; i++) 2203 ioc->reply_post_host_index[i] = 2204 (resource_size_t __iomem *) 2205 ((u8 __iomem *)&ioc->chip->Doorbell + (0x4000 + ((i - 1) 2206 * 4))); 2207 } 2208 2209 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) 2210 pr_info(MPT3SAS_FMT "%s: IRQ %d\n", 2211 reply_q->name, ((ioc->msix_enable) ? "PCI-MSI-X enabled" : 2212 "IO-APIC enabled"), 2213 pci_irq_vector(ioc->pdev, reply_q->msix_index)); 2214 2215 pr_info(MPT3SAS_FMT "iomem(0x%016llx), mapped(0x%p), size(%d)\n", 2216 ioc->name, (unsigned long long)chip_phys, ioc->chip, memap_sz); 2217 pr_info(MPT3SAS_FMT "ioport(0x%016llx), size(%d)\n", 2218 ioc->name, (unsigned long long)pio_chip, pio_sz); 2219 2220 /* Save PCI configuration state for recovery from PCI AER/EEH errors */ 2221 pci_save_state(pdev); 2222 return 0; 2223 2224 out_fail: 2225 mpt3sas_base_unmap_resources(ioc); 2226 return r; 2227 } 2228 2229 /** 2230 * mpt3sas_base_get_msg_frame - obtain request mf pointer 2231 * @ioc: per adapter object 2232 * @smid: system request message index(smid zero is invalid) 2233 * 2234 * Returns virt pointer to message frame. 2235 */ 2236 void * 2237 mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid) 2238 { 2239 return (void *)(ioc->request + (smid * ioc->request_sz)); 2240 } 2241 2242 /** 2243 * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr 2244 * @ioc: per adapter object 2245 * @smid: system request message index 2246 * 2247 * Returns virt pointer to sense buffer. 2248 */ 2249 void * 2250 mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid) 2251 { 2252 return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE)); 2253 } 2254 2255 /** 2256 * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr 2257 * @ioc: per adapter object 2258 * @smid: system request message index 2259 * 2260 * Returns phys pointer to the low 32bit address of the sense buffer. 2261 */ 2262 __le32 2263 mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid) 2264 { 2265 return cpu_to_le32(ioc->sense_dma + ((smid - 1) * 2266 SCSI_SENSE_BUFFERSIZE)); 2267 } 2268 2269 /** 2270 * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address 2271 * @ioc: per adapter object 2272 * @phys_addr: lower 32 physical addr of the reply 2273 * 2274 * Converts 32bit lower physical addr into a virt address. 2275 */ 2276 void * 2277 mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr) 2278 { 2279 if (!phys_addr) 2280 return NULL; 2281 return ioc->reply + (phys_addr - (u32)ioc->reply_dma); 2282 } 2283 2284 static inline u8 2285 _base_get_msix_index(struct MPT3SAS_ADAPTER *ioc) 2286 { 2287 return ioc->cpu_msix_table[raw_smp_processor_id()]; 2288 } 2289 2290 /** 2291 * mpt3sas_base_get_smid - obtain a free smid from internal queue 2292 * @ioc: per adapter object 2293 * @cb_idx: callback index 2294 * 2295 * Returns smid (zero is invalid) 2296 */ 2297 u16 2298 mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx) 2299 { 2300 unsigned long flags; 2301 struct request_tracker *request; 2302 u16 smid; 2303 2304 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 2305 if (list_empty(&ioc->internal_free_list)) { 2306 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2307 pr_err(MPT3SAS_FMT "%s: smid not available\n", 2308 ioc->name, __func__); 2309 return 0; 2310 } 2311 2312 request = list_entry(ioc->internal_free_list.next, 2313 struct request_tracker, tracker_list); 2314 request->cb_idx = cb_idx; 2315 smid = request->smid; 2316 list_del(&request->tracker_list); 2317 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2318 return smid; 2319 } 2320 2321 /** 2322 * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue 2323 * @ioc: per adapter object 2324 * @cb_idx: callback index 2325 * @scmd: pointer to scsi command object 2326 * 2327 * Returns smid (zero is invalid) 2328 */ 2329 u16 2330 mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx, 2331 struct scsi_cmnd *scmd) 2332 { 2333 unsigned long flags; 2334 struct scsiio_tracker *request; 2335 u16 smid; 2336 2337 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 2338 if (list_empty(&ioc->free_list)) { 2339 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2340 pr_err(MPT3SAS_FMT "%s: smid not available\n", 2341 ioc->name, __func__); 2342 return 0; 2343 } 2344 2345 request = list_entry(ioc->free_list.next, 2346 struct scsiio_tracker, tracker_list); 2347 request->scmd = scmd; 2348 request->cb_idx = cb_idx; 2349 smid = request->smid; 2350 request->msix_io = _base_get_msix_index(ioc); 2351 list_del(&request->tracker_list); 2352 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2353 return smid; 2354 } 2355 2356 /** 2357 * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue 2358 * @ioc: per adapter object 2359 * @cb_idx: callback index 2360 * 2361 * Returns smid (zero is invalid) 2362 */ 2363 u16 2364 mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx) 2365 { 2366 unsigned long flags; 2367 struct request_tracker *request; 2368 u16 smid; 2369 2370 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 2371 if (list_empty(&ioc->hpr_free_list)) { 2372 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2373 return 0; 2374 } 2375 2376 request = list_entry(ioc->hpr_free_list.next, 2377 struct request_tracker, tracker_list); 2378 request->cb_idx = cb_idx; 2379 smid = request->smid; 2380 list_del(&request->tracker_list); 2381 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2382 return smid; 2383 } 2384 2385 /** 2386 * mpt3sas_base_free_smid - put smid back on free_list 2387 * @ioc: per adapter object 2388 * @smid: system request message index 2389 * 2390 * Return nothing. 2391 */ 2392 void 2393 mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid) 2394 { 2395 unsigned long flags; 2396 int i; 2397 struct chain_tracker *chain_req, *next; 2398 2399 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 2400 if (smid < ioc->hi_priority_smid) { 2401 /* scsiio queue */ 2402 i = smid - 1; 2403 if (!list_empty(&ioc->scsi_lookup[i].chain_list)) { 2404 list_for_each_entry_safe(chain_req, next, 2405 &ioc->scsi_lookup[i].chain_list, tracker_list) { 2406 list_del_init(&chain_req->tracker_list); 2407 list_add(&chain_req->tracker_list, 2408 &ioc->free_chain_list); 2409 } 2410 } 2411 ioc->scsi_lookup[i].cb_idx = 0xFF; 2412 ioc->scsi_lookup[i].scmd = NULL; 2413 ioc->scsi_lookup[i].direct_io = 0; 2414 list_add(&ioc->scsi_lookup[i].tracker_list, &ioc->free_list); 2415 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2416 2417 /* 2418 * See _wait_for_commands_to_complete() call with regards 2419 * to this code. 2420 */ 2421 if (ioc->shost_recovery && ioc->pending_io_count) { 2422 if (ioc->pending_io_count == 1) 2423 wake_up(&ioc->reset_wq); 2424 ioc->pending_io_count--; 2425 } 2426 return; 2427 } else if (smid < ioc->internal_smid) { 2428 /* hi-priority */ 2429 i = smid - ioc->hi_priority_smid; 2430 ioc->hpr_lookup[i].cb_idx = 0xFF; 2431 list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list); 2432 } else if (smid <= ioc->hba_queue_depth) { 2433 /* internal queue */ 2434 i = smid - ioc->internal_smid; 2435 ioc->internal_lookup[i].cb_idx = 0xFF; 2436 list_add(&ioc->internal_lookup[i].tracker_list, 2437 &ioc->internal_free_list); 2438 } 2439 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2440 } 2441 2442 /** 2443 * _base_writeq - 64 bit write to MMIO 2444 * @ioc: per adapter object 2445 * @b: data payload 2446 * @addr: address in MMIO space 2447 * @writeq_lock: spin lock 2448 * 2449 * Glue for handling an atomic 64 bit word to MMIO. This special handling takes 2450 * care of 32 bit environment where its not quarenteed to send the entire word 2451 * in one transfer. 2452 */ 2453 #if defined(writeq) && defined(CONFIG_64BIT) 2454 static inline void 2455 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock) 2456 { 2457 writeq(cpu_to_le64(b), addr); 2458 } 2459 #else 2460 static inline void 2461 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock) 2462 { 2463 unsigned long flags; 2464 __u64 data_out = cpu_to_le64(b); 2465 2466 spin_lock_irqsave(writeq_lock, flags); 2467 writel((u32)(data_out), addr); 2468 writel((u32)(data_out >> 32), (addr + 4)); 2469 spin_unlock_irqrestore(writeq_lock, flags); 2470 } 2471 #endif 2472 2473 /** 2474 * _base_put_smid_scsi_io - send SCSI_IO request to firmware 2475 * @ioc: per adapter object 2476 * @smid: system request message index 2477 * @handle: device handle 2478 * 2479 * Return nothing. 2480 */ 2481 static void 2482 _base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle) 2483 { 2484 Mpi2RequestDescriptorUnion_t descriptor; 2485 u64 *request = (u64 *)&descriptor; 2486 2487 2488 descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; 2489 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc); 2490 descriptor.SCSIIO.SMID = cpu_to_le16(smid); 2491 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle); 2492 descriptor.SCSIIO.LMID = 0; 2493 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 2494 &ioc->scsi_lookup_lock); 2495 } 2496 2497 /** 2498 * _base_put_smid_fast_path - send fast path request to firmware 2499 * @ioc: per adapter object 2500 * @smid: system request message index 2501 * @handle: device handle 2502 * 2503 * Return nothing. 2504 */ 2505 static void 2506 _base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid, 2507 u16 handle) 2508 { 2509 Mpi2RequestDescriptorUnion_t descriptor; 2510 u64 *request = (u64 *)&descriptor; 2511 2512 descriptor.SCSIIO.RequestFlags = 2513 MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO; 2514 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc); 2515 descriptor.SCSIIO.SMID = cpu_to_le16(smid); 2516 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle); 2517 descriptor.SCSIIO.LMID = 0; 2518 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 2519 &ioc->scsi_lookup_lock); 2520 } 2521 2522 /** 2523 * _base_put_smid_hi_priority - send Task Management request to firmware 2524 * @ioc: per adapter object 2525 * @smid: system request message index 2526 * @msix_task: msix_task will be same as msix of IO incase of task abort else 0. 2527 * Return nothing. 2528 */ 2529 static void 2530 _base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid, 2531 u16 msix_task) 2532 { 2533 Mpi2RequestDescriptorUnion_t descriptor; 2534 u64 *request = (u64 *)&descriptor; 2535 2536 descriptor.HighPriority.RequestFlags = 2537 MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY; 2538 descriptor.HighPriority.MSIxIndex = msix_task; 2539 descriptor.HighPriority.SMID = cpu_to_le16(smid); 2540 descriptor.HighPriority.LMID = 0; 2541 descriptor.HighPriority.Reserved1 = 0; 2542 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 2543 &ioc->scsi_lookup_lock); 2544 } 2545 2546 /** 2547 * _base_put_smid_default - Default, primarily used for config pages 2548 * @ioc: per adapter object 2549 * @smid: system request message index 2550 * 2551 * Return nothing. 2552 */ 2553 static void 2554 _base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid) 2555 { 2556 Mpi2RequestDescriptorUnion_t descriptor; 2557 u64 *request = (u64 *)&descriptor; 2558 2559 descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 2560 descriptor.Default.MSIxIndex = _base_get_msix_index(ioc); 2561 descriptor.Default.SMID = cpu_to_le16(smid); 2562 descriptor.Default.LMID = 0; 2563 descriptor.Default.DescriptorTypeDependent = 0; 2564 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 2565 &ioc->scsi_lookup_lock); 2566 } 2567 2568 /** 2569 * _base_put_smid_scsi_io_atomic - send SCSI_IO request to firmware using 2570 * Atomic Request Descriptor 2571 * @ioc: per adapter object 2572 * @smid: system request message index 2573 * @handle: device handle, unused in this function, for function type match 2574 * 2575 * Return nothing. 2576 */ 2577 static void 2578 _base_put_smid_scsi_io_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid, 2579 u16 handle) 2580 { 2581 Mpi26AtomicRequestDescriptor_t descriptor; 2582 u32 *request = (u32 *)&descriptor; 2583 2584 descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; 2585 descriptor.MSIxIndex = _base_get_msix_index(ioc); 2586 descriptor.SMID = cpu_to_le16(smid); 2587 2588 writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost); 2589 } 2590 2591 /** 2592 * _base_put_smid_fast_path_atomic - send fast path request to firmware 2593 * using Atomic Request Descriptor 2594 * @ioc: per adapter object 2595 * @smid: system request message index 2596 * @handle: device handle, unused in this function, for function type match 2597 * Return nothing 2598 */ 2599 static void 2600 _base_put_smid_fast_path_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid, 2601 u16 handle) 2602 { 2603 Mpi26AtomicRequestDescriptor_t descriptor; 2604 u32 *request = (u32 *)&descriptor; 2605 2606 descriptor.RequestFlags = MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO; 2607 descriptor.MSIxIndex = _base_get_msix_index(ioc); 2608 descriptor.SMID = cpu_to_le16(smid); 2609 2610 writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost); 2611 } 2612 2613 /** 2614 * _base_put_smid_hi_priority_atomic - send Task Management request to 2615 * firmware using Atomic Request Descriptor 2616 * @ioc: per adapter object 2617 * @smid: system request message index 2618 * @msix_task: msix_task will be same as msix of IO incase of task abort else 0 2619 * 2620 * Return nothing. 2621 */ 2622 static void 2623 _base_put_smid_hi_priority_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid, 2624 u16 msix_task) 2625 { 2626 Mpi26AtomicRequestDescriptor_t descriptor; 2627 u32 *request = (u32 *)&descriptor; 2628 2629 descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY; 2630 descriptor.MSIxIndex = msix_task; 2631 descriptor.SMID = cpu_to_le16(smid); 2632 2633 writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost); 2634 } 2635 2636 /** 2637 * _base_put_smid_default - Default, primarily used for config pages 2638 * use Atomic Request Descriptor 2639 * @ioc: per adapter object 2640 * @smid: system request message index 2641 * 2642 * Return nothing. 2643 */ 2644 static void 2645 _base_put_smid_default_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid) 2646 { 2647 Mpi26AtomicRequestDescriptor_t descriptor; 2648 u32 *request = (u32 *)&descriptor; 2649 2650 descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 2651 descriptor.MSIxIndex = _base_get_msix_index(ioc); 2652 descriptor.SMID = cpu_to_le16(smid); 2653 2654 writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost); 2655 } 2656 2657 /** 2658 * _base_display_OEMs_branding - Display branding string 2659 * @ioc: per adapter object 2660 * 2661 * Return nothing. 2662 */ 2663 static void 2664 _base_display_OEMs_branding(struct MPT3SAS_ADAPTER *ioc) 2665 { 2666 if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL) 2667 return; 2668 2669 switch (ioc->pdev->subsystem_vendor) { 2670 case PCI_VENDOR_ID_INTEL: 2671 switch (ioc->pdev->device) { 2672 case MPI2_MFGPAGE_DEVID_SAS2008: 2673 switch (ioc->pdev->subsystem_device) { 2674 case MPT2SAS_INTEL_RMS2LL080_SSDID: 2675 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2676 MPT2SAS_INTEL_RMS2LL080_BRANDING); 2677 break; 2678 case MPT2SAS_INTEL_RMS2LL040_SSDID: 2679 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2680 MPT2SAS_INTEL_RMS2LL040_BRANDING); 2681 break; 2682 case MPT2SAS_INTEL_SSD910_SSDID: 2683 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2684 MPT2SAS_INTEL_SSD910_BRANDING); 2685 break; 2686 default: 2687 pr_info(MPT3SAS_FMT 2688 "Intel(R) Controller: Subsystem ID: 0x%X\n", 2689 ioc->name, ioc->pdev->subsystem_device); 2690 break; 2691 } 2692 case MPI2_MFGPAGE_DEVID_SAS2308_2: 2693 switch (ioc->pdev->subsystem_device) { 2694 case MPT2SAS_INTEL_RS25GB008_SSDID: 2695 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2696 MPT2SAS_INTEL_RS25GB008_BRANDING); 2697 break; 2698 case MPT2SAS_INTEL_RMS25JB080_SSDID: 2699 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2700 MPT2SAS_INTEL_RMS25JB080_BRANDING); 2701 break; 2702 case MPT2SAS_INTEL_RMS25JB040_SSDID: 2703 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2704 MPT2SAS_INTEL_RMS25JB040_BRANDING); 2705 break; 2706 case MPT2SAS_INTEL_RMS25KB080_SSDID: 2707 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2708 MPT2SAS_INTEL_RMS25KB080_BRANDING); 2709 break; 2710 case MPT2SAS_INTEL_RMS25KB040_SSDID: 2711 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2712 MPT2SAS_INTEL_RMS25KB040_BRANDING); 2713 break; 2714 case MPT2SAS_INTEL_RMS25LB040_SSDID: 2715 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2716 MPT2SAS_INTEL_RMS25LB040_BRANDING); 2717 break; 2718 case MPT2SAS_INTEL_RMS25LB080_SSDID: 2719 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2720 MPT2SAS_INTEL_RMS25LB080_BRANDING); 2721 break; 2722 default: 2723 pr_info(MPT3SAS_FMT 2724 "Intel(R) Controller: Subsystem ID: 0x%X\n", 2725 ioc->name, ioc->pdev->subsystem_device); 2726 break; 2727 } 2728 case MPI25_MFGPAGE_DEVID_SAS3008: 2729 switch (ioc->pdev->subsystem_device) { 2730 case MPT3SAS_INTEL_RMS3JC080_SSDID: 2731 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2732 MPT3SAS_INTEL_RMS3JC080_BRANDING); 2733 break; 2734 2735 case MPT3SAS_INTEL_RS3GC008_SSDID: 2736 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2737 MPT3SAS_INTEL_RS3GC008_BRANDING); 2738 break; 2739 case MPT3SAS_INTEL_RS3FC044_SSDID: 2740 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2741 MPT3SAS_INTEL_RS3FC044_BRANDING); 2742 break; 2743 case MPT3SAS_INTEL_RS3UC080_SSDID: 2744 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2745 MPT3SAS_INTEL_RS3UC080_BRANDING); 2746 break; 2747 default: 2748 pr_info(MPT3SAS_FMT 2749 "Intel(R) Controller: Subsystem ID: 0x%X\n", 2750 ioc->name, ioc->pdev->subsystem_device); 2751 break; 2752 } 2753 break; 2754 default: 2755 pr_info(MPT3SAS_FMT 2756 "Intel(R) Controller: Subsystem ID: 0x%X\n", 2757 ioc->name, ioc->pdev->subsystem_device); 2758 break; 2759 } 2760 break; 2761 case PCI_VENDOR_ID_DELL: 2762 switch (ioc->pdev->device) { 2763 case MPI2_MFGPAGE_DEVID_SAS2008: 2764 switch (ioc->pdev->subsystem_device) { 2765 case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID: 2766 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2767 MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING); 2768 break; 2769 case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID: 2770 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2771 MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING); 2772 break; 2773 case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID: 2774 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2775 MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING); 2776 break; 2777 case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID: 2778 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2779 MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING); 2780 break; 2781 case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID: 2782 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2783 MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING); 2784 break; 2785 case MPT2SAS_DELL_PERC_H200_SSDID: 2786 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2787 MPT2SAS_DELL_PERC_H200_BRANDING); 2788 break; 2789 case MPT2SAS_DELL_6GBPS_SAS_SSDID: 2790 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2791 MPT2SAS_DELL_6GBPS_SAS_BRANDING); 2792 break; 2793 default: 2794 pr_info(MPT3SAS_FMT 2795 "Dell 6Gbps HBA: Subsystem ID: 0x%X\n", 2796 ioc->name, ioc->pdev->subsystem_device); 2797 break; 2798 } 2799 break; 2800 case MPI25_MFGPAGE_DEVID_SAS3008: 2801 switch (ioc->pdev->subsystem_device) { 2802 case MPT3SAS_DELL_12G_HBA_SSDID: 2803 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2804 MPT3SAS_DELL_12G_HBA_BRANDING); 2805 break; 2806 default: 2807 pr_info(MPT3SAS_FMT 2808 "Dell 12Gbps HBA: Subsystem ID: 0x%X\n", 2809 ioc->name, ioc->pdev->subsystem_device); 2810 break; 2811 } 2812 break; 2813 default: 2814 pr_info(MPT3SAS_FMT 2815 "Dell HBA: Subsystem ID: 0x%X\n", ioc->name, 2816 ioc->pdev->subsystem_device); 2817 break; 2818 } 2819 break; 2820 case PCI_VENDOR_ID_CISCO: 2821 switch (ioc->pdev->device) { 2822 case MPI25_MFGPAGE_DEVID_SAS3008: 2823 switch (ioc->pdev->subsystem_device) { 2824 case MPT3SAS_CISCO_12G_8E_HBA_SSDID: 2825 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2826 MPT3SAS_CISCO_12G_8E_HBA_BRANDING); 2827 break; 2828 case MPT3SAS_CISCO_12G_8I_HBA_SSDID: 2829 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2830 MPT3SAS_CISCO_12G_8I_HBA_BRANDING); 2831 break; 2832 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID: 2833 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2834 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING); 2835 break; 2836 default: 2837 pr_info(MPT3SAS_FMT 2838 "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n", 2839 ioc->name, ioc->pdev->subsystem_device); 2840 break; 2841 } 2842 break; 2843 case MPI25_MFGPAGE_DEVID_SAS3108_1: 2844 switch (ioc->pdev->subsystem_device) { 2845 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID: 2846 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2847 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING); 2848 break; 2849 case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID: 2850 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2851 MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING 2852 ); 2853 break; 2854 default: 2855 pr_info(MPT3SAS_FMT 2856 "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n", 2857 ioc->name, ioc->pdev->subsystem_device); 2858 break; 2859 } 2860 break; 2861 default: 2862 pr_info(MPT3SAS_FMT 2863 "Cisco SAS HBA: Subsystem ID: 0x%X\n", 2864 ioc->name, ioc->pdev->subsystem_device); 2865 break; 2866 } 2867 break; 2868 case MPT2SAS_HP_3PAR_SSVID: 2869 switch (ioc->pdev->device) { 2870 case MPI2_MFGPAGE_DEVID_SAS2004: 2871 switch (ioc->pdev->subsystem_device) { 2872 case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID: 2873 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2874 MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING); 2875 break; 2876 default: 2877 pr_info(MPT3SAS_FMT 2878 "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n", 2879 ioc->name, ioc->pdev->subsystem_device); 2880 break; 2881 } 2882 case MPI2_MFGPAGE_DEVID_SAS2308_2: 2883 switch (ioc->pdev->subsystem_device) { 2884 case MPT2SAS_HP_2_4_INTERNAL_SSDID: 2885 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2886 MPT2SAS_HP_2_4_INTERNAL_BRANDING); 2887 break; 2888 case MPT2SAS_HP_2_4_EXTERNAL_SSDID: 2889 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2890 MPT2SAS_HP_2_4_EXTERNAL_BRANDING); 2891 break; 2892 case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID: 2893 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2894 MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING); 2895 break; 2896 case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID: 2897 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2898 MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING); 2899 break; 2900 default: 2901 pr_info(MPT3SAS_FMT 2902 "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n", 2903 ioc->name, ioc->pdev->subsystem_device); 2904 break; 2905 } 2906 default: 2907 pr_info(MPT3SAS_FMT 2908 "HP SAS HBA: Subsystem ID: 0x%X\n", 2909 ioc->name, ioc->pdev->subsystem_device); 2910 break; 2911 } 2912 default: 2913 break; 2914 } 2915 } 2916 2917 /** 2918 * _base_display_ioc_capabilities - Disply IOC's capabilities. 2919 * @ioc: per adapter object 2920 * 2921 * Return nothing. 2922 */ 2923 static void 2924 _base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc) 2925 { 2926 int i = 0; 2927 char desc[16]; 2928 u32 iounit_pg1_flags; 2929 u32 bios_version; 2930 2931 bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion); 2932 strncpy(desc, ioc->manu_pg0.ChipName, 16); 2933 pr_info(MPT3SAS_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "\ 2934 "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n", 2935 ioc->name, desc, 2936 (ioc->facts.FWVersion.Word & 0xFF000000) >> 24, 2937 (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16, 2938 (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8, 2939 ioc->facts.FWVersion.Word & 0x000000FF, 2940 ioc->pdev->revision, 2941 (bios_version & 0xFF000000) >> 24, 2942 (bios_version & 0x00FF0000) >> 16, 2943 (bios_version & 0x0000FF00) >> 8, 2944 bios_version & 0x000000FF); 2945 2946 _base_display_OEMs_branding(ioc); 2947 2948 pr_info(MPT3SAS_FMT "Protocol=(", ioc->name); 2949 2950 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) { 2951 pr_info("Initiator"); 2952 i++; 2953 } 2954 2955 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) { 2956 pr_info("%sTarget", i ? "," : ""); 2957 i++; 2958 } 2959 2960 i = 0; 2961 pr_info("), "); 2962 pr_info("Capabilities=("); 2963 2964 if (!ioc->hide_ir_msg) { 2965 if (ioc->facts.IOCCapabilities & 2966 MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) { 2967 pr_info("Raid"); 2968 i++; 2969 } 2970 } 2971 2972 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) { 2973 pr_info("%sTLR", i ? "," : ""); 2974 i++; 2975 } 2976 2977 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) { 2978 pr_info("%sMulticast", i ? "," : ""); 2979 i++; 2980 } 2981 2982 if (ioc->facts.IOCCapabilities & 2983 MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) { 2984 pr_info("%sBIDI Target", i ? "," : ""); 2985 i++; 2986 } 2987 2988 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) { 2989 pr_info("%sEEDP", i ? "," : ""); 2990 i++; 2991 } 2992 2993 if (ioc->facts.IOCCapabilities & 2994 MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) { 2995 pr_info("%sSnapshot Buffer", i ? "," : ""); 2996 i++; 2997 } 2998 2999 if (ioc->facts.IOCCapabilities & 3000 MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) { 3001 pr_info("%sDiag Trace Buffer", i ? "," : ""); 3002 i++; 3003 } 3004 3005 if (ioc->facts.IOCCapabilities & 3006 MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) { 3007 pr_info("%sDiag Extended Buffer", i ? "," : ""); 3008 i++; 3009 } 3010 3011 if (ioc->facts.IOCCapabilities & 3012 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) { 3013 pr_info("%sTask Set Full", i ? "," : ""); 3014 i++; 3015 } 3016 3017 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags); 3018 if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) { 3019 pr_info("%sNCQ", i ? "," : ""); 3020 i++; 3021 } 3022 3023 pr_info(")\n"); 3024 } 3025 3026 /** 3027 * mpt3sas_base_update_missing_delay - change the missing delay timers 3028 * @ioc: per adapter object 3029 * @device_missing_delay: amount of time till device is reported missing 3030 * @io_missing_delay: interval IO is returned when there is a missing device 3031 * 3032 * Return nothing. 3033 * 3034 * Passed on the command line, this function will modify the device missing 3035 * delay, as well as the io missing delay. This should be called at driver 3036 * load time. 3037 */ 3038 void 3039 mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc, 3040 u16 device_missing_delay, u8 io_missing_delay) 3041 { 3042 u16 dmd, dmd_new, dmd_orignal; 3043 u8 io_missing_delay_original; 3044 u16 sz; 3045 Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL; 3046 Mpi2ConfigReply_t mpi_reply; 3047 u8 num_phys = 0; 3048 u16 ioc_status; 3049 3050 mpt3sas_config_get_number_hba_phys(ioc, &num_phys); 3051 if (!num_phys) 3052 return; 3053 3054 sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys * 3055 sizeof(Mpi2SasIOUnit1PhyData_t)); 3056 sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL); 3057 if (!sas_iounit_pg1) { 3058 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n", 3059 ioc->name, __FILE__, __LINE__, __func__); 3060 goto out; 3061 } 3062 if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply, 3063 sas_iounit_pg1, sz))) { 3064 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n", 3065 ioc->name, __FILE__, __LINE__, __func__); 3066 goto out; 3067 } 3068 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & 3069 MPI2_IOCSTATUS_MASK; 3070 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 3071 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n", 3072 ioc->name, __FILE__, __LINE__, __func__); 3073 goto out; 3074 } 3075 3076 /* device missing delay */ 3077 dmd = sas_iounit_pg1->ReportDeviceMissingDelay; 3078 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16) 3079 dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16; 3080 else 3081 dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK; 3082 dmd_orignal = dmd; 3083 if (device_missing_delay > 0x7F) { 3084 dmd = (device_missing_delay > 0x7F0) ? 0x7F0 : 3085 device_missing_delay; 3086 dmd = dmd / 16; 3087 dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16; 3088 } else 3089 dmd = device_missing_delay; 3090 sas_iounit_pg1->ReportDeviceMissingDelay = dmd; 3091 3092 /* io missing delay */ 3093 io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay; 3094 sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay; 3095 3096 if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1, 3097 sz)) { 3098 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16) 3099 dmd_new = (dmd & 3100 MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16; 3101 else 3102 dmd_new = 3103 dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK; 3104 pr_info(MPT3SAS_FMT "device_missing_delay: old(%d), new(%d)\n", 3105 ioc->name, dmd_orignal, dmd_new); 3106 pr_info(MPT3SAS_FMT "ioc_missing_delay: old(%d), new(%d)\n", 3107 ioc->name, io_missing_delay_original, 3108 io_missing_delay); 3109 ioc->device_missing_delay = dmd_new; 3110 ioc->io_missing_delay = io_missing_delay; 3111 } 3112 3113 out: 3114 kfree(sas_iounit_pg1); 3115 } 3116 /** 3117 * _base_static_config_pages - static start of day config pages 3118 * @ioc: per adapter object 3119 * 3120 * Return nothing. 3121 */ 3122 static void 3123 _base_static_config_pages(struct MPT3SAS_ADAPTER *ioc) 3124 { 3125 Mpi2ConfigReply_t mpi_reply; 3126 u32 iounit_pg1_flags; 3127 3128 mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0); 3129 if (ioc->ir_firmware) 3130 mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply, 3131 &ioc->manu_pg10); 3132 3133 /* 3134 * Ensure correct T10 PI operation if vendor left EEDPTagMode 3135 * flag unset in NVDATA. 3136 */ 3137 mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply, &ioc->manu_pg11); 3138 if (ioc->manu_pg11.EEDPTagMode == 0) { 3139 pr_err("%s: overriding NVDATA EEDPTagMode setting\n", 3140 ioc->name); 3141 ioc->manu_pg11.EEDPTagMode &= ~0x3; 3142 ioc->manu_pg11.EEDPTagMode |= 0x1; 3143 mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply, 3144 &ioc->manu_pg11); 3145 } 3146 3147 mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2); 3148 mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3); 3149 mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8); 3150 mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0); 3151 mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1); 3152 mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8); 3153 _base_display_ioc_capabilities(ioc); 3154 3155 /* 3156 * Enable task_set_full handling in iounit_pg1 when the 3157 * facts capabilities indicate that its supported. 3158 */ 3159 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags); 3160 if ((ioc->facts.IOCCapabilities & 3161 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING)) 3162 iounit_pg1_flags &= 3163 ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING; 3164 else 3165 iounit_pg1_flags |= 3166 MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING; 3167 ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags); 3168 mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1); 3169 3170 if (ioc->iounit_pg8.NumSensors) 3171 ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors; 3172 } 3173 3174 /** 3175 * _base_release_memory_pools - release memory 3176 * @ioc: per adapter object 3177 * 3178 * Free memory allocated from _base_allocate_memory_pools. 3179 * 3180 * Return nothing. 3181 */ 3182 static void 3183 _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc) 3184 { 3185 int i = 0; 3186 struct reply_post_struct *rps; 3187 3188 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3189 __func__)); 3190 3191 if (ioc->request) { 3192 pci_free_consistent(ioc->pdev, ioc->request_dma_sz, 3193 ioc->request, ioc->request_dma); 3194 dexitprintk(ioc, pr_info(MPT3SAS_FMT 3195 "request_pool(0x%p): free\n", 3196 ioc->name, ioc->request)); 3197 ioc->request = NULL; 3198 } 3199 3200 if (ioc->sense) { 3201 dma_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma); 3202 dma_pool_destroy(ioc->sense_dma_pool); 3203 dexitprintk(ioc, pr_info(MPT3SAS_FMT 3204 "sense_pool(0x%p): free\n", 3205 ioc->name, ioc->sense)); 3206 ioc->sense = NULL; 3207 } 3208 3209 if (ioc->reply) { 3210 dma_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma); 3211 dma_pool_destroy(ioc->reply_dma_pool); 3212 dexitprintk(ioc, pr_info(MPT3SAS_FMT 3213 "reply_pool(0x%p): free\n", 3214 ioc->name, ioc->reply)); 3215 ioc->reply = NULL; 3216 } 3217 3218 if (ioc->reply_free) { 3219 dma_pool_free(ioc->reply_free_dma_pool, ioc->reply_free, 3220 ioc->reply_free_dma); 3221 dma_pool_destroy(ioc->reply_free_dma_pool); 3222 dexitprintk(ioc, pr_info(MPT3SAS_FMT 3223 "reply_free_pool(0x%p): free\n", 3224 ioc->name, ioc->reply_free)); 3225 ioc->reply_free = NULL; 3226 } 3227 3228 if (ioc->reply_post) { 3229 do { 3230 rps = &ioc->reply_post[i]; 3231 if (rps->reply_post_free) { 3232 dma_pool_free( 3233 ioc->reply_post_free_dma_pool, 3234 rps->reply_post_free, 3235 rps->reply_post_free_dma); 3236 dexitprintk(ioc, pr_info(MPT3SAS_FMT 3237 "reply_post_free_pool(0x%p): free\n", 3238 ioc->name, rps->reply_post_free)); 3239 rps->reply_post_free = NULL; 3240 } 3241 } while (ioc->rdpq_array_enable && 3242 (++i < ioc->reply_queue_count)); 3243 3244 dma_pool_destroy(ioc->reply_post_free_dma_pool); 3245 kfree(ioc->reply_post); 3246 } 3247 3248 if (ioc->config_page) { 3249 dexitprintk(ioc, pr_info(MPT3SAS_FMT 3250 "config_page(0x%p): free\n", ioc->name, 3251 ioc->config_page)); 3252 pci_free_consistent(ioc->pdev, ioc->config_page_sz, 3253 ioc->config_page, ioc->config_page_dma); 3254 } 3255 3256 if (ioc->scsi_lookup) { 3257 free_pages((ulong)ioc->scsi_lookup, ioc->scsi_lookup_pages); 3258 ioc->scsi_lookup = NULL; 3259 } 3260 kfree(ioc->hpr_lookup); 3261 kfree(ioc->internal_lookup); 3262 if (ioc->chain_lookup) { 3263 for (i = 0; i < ioc->chain_depth; i++) { 3264 if (ioc->chain_lookup[i].chain_buffer) 3265 dma_pool_free(ioc->chain_dma_pool, 3266 ioc->chain_lookup[i].chain_buffer, 3267 ioc->chain_lookup[i].chain_buffer_dma); 3268 } 3269 dma_pool_destroy(ioc->chain_dma_pool); 3270 free_pages((ulong)ioc->chain_lookup, ioc->chain_pages); 3271 ioc->chain_lookup = NULL; 3272 } 3273 } 3274 3275 /** 3276 * _base_allocate_memory_pools - allocate start of day memory pools 3277 * @ioc: per adapter object 3278 * 3279 * Returns 0 success, anything else error 3280 */ 3281 static int 3282 _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) 3283 { 3284 struct mpt3sas_facts *facts; 3285 u16 max_sge_elements; 3286 u16 chains_needed_per_io; 3287 u32 sz, total_sz, reply_post_free_sz; 3288 u32 retry_sz; 3289 u16 max_request_credit; 3290 unsigned short sg_tablesize; 3291 u16 sge_size; 3292 int i; 3293 3294 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3295 __func__)); 3296 3297 3298 retry_sz = 0; 3299 facts = &ioc->facts; 3300 3301 /* command line tunables for max sgl entries */ 3302 if (max_sgl_entries != -1) 3303 sg_tablesize = max_sgl_entries; 3304 else { 3305 if (ioc->hba_mpi_version_belonged == MPI2_VERSION) 3306 sg_tablesize = MPT2SAS_SG_DEPTH; 3307 else 3308 sg_tablesize = MPT3SAS_SG_DEPTH; 3309 } 3310 3311 if (sg_tablesize < MPT_MIN_PHYS_SEGMENTS) 3312 sg_tablesize = MPT_MIN_PHYS_SEGMENTS; 3313 else if (sg_tablesize > MPT_MAX_PHYS_SEGMENTS) { 3314 sg_tablesize = min_t(unsigned short, sg_tablesize, 3315 SG_MAX_SEGMENTS); 3316 pr_warn(MPT3SAS_FMT 3317 "sg_tablesize(%u) is bigger than kernel" 3318 " defined SG_CHUNK_SIZE(%u)\n", ioc->name, 3319 sg_tablesize, MPT_MAX_PHYS_SEGMENTS); 3320 } 3321 ioc->shost->sg_tablesize = sg_tablesize; 3322 3323 ioc->internal_depth = min_t(int, (facts->HighPriorityCredit + (5)), 3324 (facts->RequestCredit / 4)); 3325 if (ioc->internal_depth < INTERNAL_CMDS_COUNT) { 3326 if (facts->RequestCredit <= (INTERNAL_CMDS_COUNT + 3327 INTERNAL_SCSIIO_CMDS_COUNT)) { 3328 pr_err(MPT3SAS_FMT "IOC doesn't have enough Request \ 3329 Credits, it has just %d number of credits\n", 3330 ioc->name, facts->RequestCredit); 3331 return -ENOMEM; 3332 } 3333 ioc->internal_depth = 10; 3334 } 3335 3336 ioc->hi_priority_depth = ioc->internal_depth - (5); 3337 /* command line tunables for max controller queue depth */ 3338 if (max_queue_depth != -1 && max_queue_depth != 0) { 3339 max_request_credit = min_t(u16, max_queue_depth + 3340 ioc->internal_depth, facts->RequestCredit); 3341 if (max_request_credit > MAX_HBA_QUEUE_DEPTH) 3342 max_request_credit = MAX_HBA_QUEUE_DEPTH; 3343 } else 3344 max_request_credit = min_t(u16, facts->RequestCredit, 3345 MAX_HBA_QUEUE_DEPTH); 3346 3347 /* Firmware maintains additional facts->HighPriorityCredit number of 3348 * credits for HiPriprity Request messages, so hba queue depth will be 3349 * sum of max_request_credit and high priority queue depth. 3350 */ 3351 ioc->hba_queue_depth = max_request_credit + ioc->hi_priority_depth; 3352 3353 /* request frame size */ 3354 ioc->request_sz = facts->IOCRequestFrameSize * 4; 3355 3356 /* reply frame size */ 3357 ioc->reply_sz = facts->ReplyFrameSize * 4; 3358 3359 /* chain segment size */ 3360 if (ioc->hba_mpi_version_belonged != MPI2_VERSION) { 3361 if (facts->IOCMaxChainSegmentSize) 3362 ioc->chain_segment_sz = 3363 facts->IOCMaxChainSegmentSize * 3364 MAX_CHAIN_ELEMT_SZ; 3365 else 3366 /* set to 128 bytes size if IOCMaxChainSegmentSize is zero */ 3367 ioc->chain_segment_sz = DEFAULT_NUM_FWCHAIN_ELEMTS * 3368 MAX_CHAIN_ELEMT_SZ; 3369 } else 3370 ioc->chain_segment_sz = ioc->request_sz; 3371 3372 /* calculate the max scatter element size */ 3373 sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee); 3374 3375 retry_allocation: 3376 total_sz = 0; 3377 /* calculate number of sg elements left over in the 1st frame */ 3378 max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) - 3379 sizeof(Mpi2SGEIOUnion_t)) + sge_size); 3380 ioc->max_sges_in_main_message = max_sge_elements/sge_size; 3381 3382 /* now do the same for a chain buffer */ 3383 max_sge_elements = ioc->chain_segment_sz - sge_size; 3384 ioc->max_sges_in_chain_message = max_sge_elements/sge_size; 3385 3386 /* 3387 * MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE 3388 */ 3389 chains_needed_per_io = ((ioc->shost->sg_tablesize - 3390 ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message) 3391 + 1; 3392 if (chains_needed_per_io > facts->MaxChainDepth) { 3393 chains_needed_per_io = facts->MaxChainDepth; 3394 ioc->shost->sg_tablesize = min_t(u16, 3395 ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message 3396 * chains_needed_per_io), ioc->shost->sg_tablesize); 3397 } 3398 ioc->chains_needed_per_io = chains_needed_per_io; 3399 3400 /* reply free queue sizing - taking into account for 64 FW events */ 3401 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64; 3402 3403 /* calculate reply descriptor post queue depth */ 3404 ioc->reply_post_queue_depth = ioc->hba_queue_depth + 3405 ioc->reply_free_queue_depth + 1 ; 3406 /* align the reply post queue on the next 16 count boundary */ 3407 if (ioc->reply_post_queue_depth % 16) 3408 ioc->reply_post_queue_depth += 16 - 3409 (ioc->reply_post_queue_depth % 16); 3410 3411 if (ioc->reply_post_queue_depth > 3412 facts->MaxReplyDescriptorPostQueueDepth) { 3413 ioc->reply_post_queue_depth = 3414 facts->MaxReplyDescriptorPostQueueDepth - 3415 (facts->MaxReplyDescriptorPostQueueDepth % 16); 3416 ioc->hba_queue_depth = 3417 ((ioc->reply_post_queue_depth - 64) / 2) - 1; 3418 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64; 3419 } 3420 3421 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scatter gather: " \ 3422 "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), " 3423 "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message, 3424 ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize, 3425 ioc->chains_needed_per_io)); 3426 3427 /* reply post queue, 16 byte align */ 3428 reply_post_free_sz = ioc->reply_post_queue_depth * 3429 sizeof(Mpi2DefaultReplyDescriptor_t); 3430 3431 sz = reply_post_free_sz; 3432 if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable) 3433 sz *= ioc->reply_queue_count; 3434 3435 ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ? 3436 (ioc->reply_queue_count):1, 3437 sizeof(struct reply_post_struct), GFP_KERNEL); 3438 3439 if (!ioc->reply_post) { 3440 pr_err(MPT3SAS_FMT "reply_post_free pool: kcalloc failed\n", 3441 ioc->name); 3442 goto out; 3443 } 3444 ioc->reply_post_free_dma_pool = dma_pool_create("reply_post_free pool", 3445 &ioc->pdev->dev, sz, 16, 0); 3446 if (!ioc->reply_post_free_dma_pool) { 3447 pr_err(MPT3SAS_FMT 3448 "reply_post_free pool: dma_pool_create failed\n", 3449 ioc->name); 3450 goto out; 3451 } 3452 i = 0; 3453 do { 3454 ioc->reply_post[i].reply_post_free = 3455 dma_pool_alloc(ioc->reply_post_free_dma_pool, 3456 GFP_KERNEL, 3457 &ioc->reply_post[i].reply_post_free_dma); 3458 if (!ioc->reply_post[i].reply_post_free) { 3459 pr_err(MPT3SAS_FMT 3460 "reply_post_free pool: dma_pool_alloc failed\n", 3461 ioc->name); 3462 goto out; 3463 } 3464 memset(ioc->reply_post[i].reply_post_free, 0, sz); 3465 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3466 "reply post free pool (0x%p): depth(%d)," 3467 "element_size(%d), pool_size(%d kB)\n", ioc->name, 3468 ioc->reply_post[i].reply_post_free, 3469 ioc->reply_post_queue_depth, 8, sz/1024)); 3470 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3471 "reply_post_free_dma = (0x%llx)\n", ioc->name, 3472 (unsigned long long) 3473 ioc->reply_post[i].reply_post_free_dma)); 3474 total_sz += sz; 3475 } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count)); 3476 3477 if (ioc->dma_mask == 64) { 3478 if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) { 3479 pr_warn(MPT3SAS_FMT 3480 "no suitable consistent DMA mask for %s\n", 3481 ioc->name, pci_name(ioc->pdev)); 3482 goto out; 3483 } 3484 } 3485 3486 ioc->scsiio_depth = ioc->hba_queue_depth - 3487 ioc->hi_priority_depth - ioc->internal_depth; 3488 3489 /* set the scsi host can_queue depth 3490 * with some internal commands that could be outstanding 3491 */ 3492 ioc->shost->can_queue = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT; 3493 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3494 "scsi host: can_queue depth (%d)\n", 3495 ioc->name, ioc->shost->can_queue)); 3496 3497 3498 /* contiguous pool for request and chains, 16 byte align, one extra " 3499 * "frame for smid=0 3500 */ 3501 ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth; 3502 sz = ((ioc->scsiio_depth + 1) * ioc->request_sz); 3503 3504 /* hi-priority queue */ 3505 sz += (ioc->hi_priority_depth * ioc->request_sz); 3506 3507 /* internal queue */ 3508 sz += (ioc->internal_depth * ioc->request_sz); 3509 3510 ioc->request_dma_sz = sz; 3511 ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma); 3512 if (!ioc->request) { 3513 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \ 3514 "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), " 3515 "total(%d kB)\n", ioc->name, ioc->hba_queue_depth, 3516 ioc->chains_needed_per_io, ioc->request_sz, sz/1024); 3517 if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH) 3518 goto out; 3519 retry_sz = 64; 3520 ioc->hba_queue_depth -= retry_sz; 3521 _base_release_memory_pools(ioc); 3522 goto retry_allocation; 3523 } 3524 3525 if (retry_sz) 3526 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \ 3527 "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), " 3528 "total(%d kb)\n", ioc->name, ioc->hba_queue_depth, 3529 ioc->chains_needed_per_io, ioc->request_sz, sz/1024); 3530 3531 /* hi-priority queue */ 3532 ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) * 3533 ioc->request_sz); 3534 ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) * 3535 ioc->request_sz); 3536 3537 /* internal queue */ 3538 ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth * 3539 ioc->request_sz); 3540 ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth * 3541 ioc->request_sz); 3542 3543 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3544 "request pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n", 3545 ioc->name, ioc->request, ioc->hba_queue_depth, ioc->request_sz, 3546 (ioc->hba_queue_depth * ioc->request_sz)/1024)); 3547 3548 dinitprintk(ioc, pr_info(MPT3SAS_FMT "request pool: dma(0x%llx)\n", 3549 ioc->name, (unsigned long long) ioc->request_dma)); 3550 total_sz += sz; 3551 3552 sz = ioc->scsiio_depth * sizeof(struct scsiio_tracker); 3553 ioc->scsi_lookup_pages = get_order(sz); 3554 ioc->scsi_lookup = (struct scsiio_tracker *)__get_free_pages( 3555 GFP_KERNEL, ioc->scsi_lookup_pages); 3556 if (!ioc->scsi_lookup) { 3557 pr_err(MPT3SAS_FMT "scsi_lookup: get_free_pages failed, sz(%d)\n", 3558 ioc->name, (int)sz); 3559 goto out; 3560 } 3561 3562 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scsiio(0x%p): depth(%d)\n", 3563 ioc->name, ioc->request, ioc->scsiio_depth)); 3564 3565 ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH); 3566 sz = ioc->chain_depth * sizeof(struct chain_tracker); 3567 ioc->chain_pages = get_order(sz); 3568 ioc->chain_lookup = (struct chain_tracker *)__get_free_pages( 3569 GFP_KERNEL, ioc->chain_pages); 3570 if (!ioc->chain_lookup) { 3571 pr_err(MPT3SAS_FMT "chain_lookup: __get_free_pages failed\n", 3572 ioc->name); 3573 goto out; 3574 } 3575 ioc->chain_dma_pool = dma_pool_create("chain pool", &ioc->pdev->dev, 3576 ioc->chain_segment_sz, 16, 0); 3577 if (!ioc->chain_dma_pool) { 3578 pr_err(MPT3SAS_FMT "chain_dma_pool: dma_pool_create failed\n", 3579 ioc->name); 3580 goto out; 3581 } 3582 for (i = 0; i < ioc->chain_depth; i++) { 3583 ioc->chain_lookup[i].chain_buffer = dma_pool_alloc( 3584 ioc->chain_dma_pool , GFP_KERNEL, 3585 &ioc->chain_lookup[i].chain_buffer_dma); 3586 if (!ioc->chain_lookup[i].chain_buffer) { 3587 ioc->chain_depth = i; 3588 goto chain_done; 3589 } 3590 total_sz += ioc->chain_segment_sz; 3591 } 3592 chain_done: 3593 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3594 "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n", 3595 ioc->name, ioc->chain_depth, ioc->chain_segment_sz, 3596 ((ioc->chain_depth * ioc->chain_segment_sz))/1024)); 3597 3598 /* initialize hi-priority queue smid's */ 3599 ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth, 3600 sizeof(struct request_tracker), GFP_KERNEL); 3601 if (!ioc->hpr_lookup) { 3602 pr_err(MPT3SAS_FMT "hpr_lookup: kcalloc failed\n", 3603 ioc->name); 3604 goto out; 3605 } 3606 ioc->hi_priority_smid = ioc->scsiio_depth + 1; 3607 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3608 "hi_priority(0x%p): depth(%d), start smid(%d)\n", 3609 ioc->name, ioc->hi_priority, 3610 ioc->hi_priority_depth, ioc->hi_priority_smid)); 3611 3612 /* initialize internal queue smid's */ 3613 ioc->internal_lookup = kcalloc(ioc->internal_depth, 3614 sizeof(struct request_tracker), GFP_KERNEL); 3615 if (!ioc->internal_lookup) { 3616 pr_err(MPT3SAS_FMT "internal_lookup: kcalloc failed\n", 3617 ioc->name); 3618 goto out; 3619 } 3620 ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth; 3621 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3622 "internal(0x%p): depth(%d), start smid(%d)\n", 3623 ioc->name, ioc->internal, 3624 ioc->internal_depth, ioc->internal_smid)); 3625 3626 /* sense buffers, 4 byte align */ 3627 sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE; 3628 ioc->sense_dma_pool = dma_pool_create("sense pool", &ioc->pdev->dev, sz, 3629 4, 0); 3630 if (!ioc->sense_dma_pool) { 3631 pr_err(MPT3SAS_FMT "sense pool: dma_pool_create failed\n", 3632 ioc->name); 3633 goto out; 3634 } 3635 ioc->sense = dma_pool_alloc(ioc->sense_dma_pool, GFP_KERNEL, 3636 &ioc->sense_dma); 3637 if (!ioc->sense) { 3638 pr_err(MPT3SAS_FMT "sense pool: dma_pool_alloc failed\n", 3639 ioc->name); 3640 goto out; 3641 } 3642 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3643 "sense pool(0x%p): depth(%d), element_size(%d), pool_size" 3644 "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth, 3645 SCSI_SENSE_BUFFERSIZE, sz/1024)); 3646 dinitprintk(ioc, pr_info(MPT3SAS_FMT "sense_dma(0x%llx)\n", 3647 ioc->name, (unsigned long long)ioc->sense_dma)); 3648 total_sz += sz; 3649 3650 /* reply pool, 4 byte align */ 3651 sz = ioc->reply_free_queue_depth * ioc->reply_sz; 3652 ioc->reply_dma_pool = dma_pool_create("reply pool", &ioc->pdev->dev, sz, 3653 4, 0); 3654 if (!ioc->reply_dma_pool) { 3655 pr_err(MPT3SAS_FMT "reply pool: dma_pool_create failed\n", 3656 ioc->name); 3657 goto out; 3658 } 3659 ioc->reply = dma_pool_alloc(ioc->reply_dma_pool, GFP_KERNEL, 3660 &ioc->reply_dma); 3661 if (!ioc->reply) { 3662 pr_err(MPT3SAS_FMT "reply pool: dma_pool_alloc failed\n", 3663 ioc->name); 3664 goto out; 3665 } 3666 ioc->reply_dma_min_address = (u32)(ioc->reply_dma); 3667 ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz; 3668 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3669 "reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n", 3670 ioc->name, ioc->reply, 3671 ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024)); 3672 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_dma(0x%llx)\n", 3673 ioc->name, (unsigned long long)ioc->reply_dma)); 3674 total_sz += sz; 3675 3676 /* reply free queue, 16 byte align */ 3677 sz = ioc->reply_free_queue_depth * 4; 3678 ioc->reply_free_dma_pool = dma_pool_create("reply_free pool", 3679 &ioc->pdev->dev, sz, 16, 0); 3680 if (!ioc->reply_free_dma_pool) { 3681 pr_err(MPT3SAS_FMT "reply_free pool: dma_pool_create failed\n", 3682 ioc->name); 3683 goto out; 3684 } 3685 ioc->reply_free = dma_pool_alloc(ioc->reply_free_dma_pool, GFP_KERNEL, 3686 &ioc->reply_free_dma); 3687 if (!ioc->reply_free) { 3688 pr_err(MPT3SAS_FMT "reply_free pool: dma_pool_alloc failed\n", 3689 ioc->name); 3690 goto out; 3691 } 3692 memset(ioc->reply_free, 0, sz); 3693 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_free pool(0x%p): " \ 3694 "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name, 3695 ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024)); 3696 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3697 "reply_free_dma (0x%llx)\n", 3698 ioc->name, (unsigned long long)ioc->reply_free_dma)); 3699 total_sz += sz; 3700 3701 ioc->config_page_sz = 512; 3702 ioc->config_page = pci_alloc_consistent(ioc->pdev, 3703 ioc->config_page_sz, &ioc->config_page_dma); 3704 if (!ioc->config_page) { 3705 pr_err(MPT3SAS_FMT 3706 "config page: dma_pool_alloc failed\n", 3707 ioc->name); 3708 goto out; 3709 } 3710 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3711 "config page(0x%p): size(%d)\n", 3712 ioc->name, ioc->config_page, ioc->config_page_sz)); 3713 dinitprintk(ioc, pr_info(MPT3SAS_FMT "config_page_dma(0x%llx)\n", 3714 ioc->name, (unsigned long long)ioc->config_page_dma)); 3715 total_sz += ioc->config_page_sz; 3716 3717 pr_info(MPT3SAS_FMT "Allocated physical memory: size(%d kB)\n", 3718 ioc->name, total_sz/1024); 3719 pr_info(MPT3SAS_FMT 3720 "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n", 3721 ioc->name, ioc->shost->can_queue, facts->RequestCredit); 3722 pr_info(MPT3SAS_FMT "Scatter Gather Elements per IO(%d)\n", 3723 ioc->name, ioc->shost->sg_tablesize); 3724 return 0; 3725 3726 out: 3727 return -ENOMEM; 3728 } 3729 3730 /** 3731 * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter. 3732 * @ioc: Pointer to MPT_ADAPTER structure 3733 * @cooked: Request raw or cooked IOC state 3734 * 3735 * Returns all IOC Doorbell register bits if cooked==0, else just the 3736 * Doorbell bits in MPI_IOC_STATE_MASK. 3737 */ 3738 u32 3739 mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked) 3740 { 3741 u32 s, sc; 3742 3743 s = readl(&ioc->chip->Doorbell); 3744 sc = s & MPI2_IOC_STATE_MASK; 3745 return cooked ? sc : s; 3746 } 3747 3748 /** 3749 * _base_wait_on_iocstate - waiting on a particular ioc state 3750 * @ioc_state: controller state { READY, OPERATIONAL, or RESET } 3751 * @timeout: timeout in second 3752 * 3753 * Returns 0 for success, non-zero for failure. 3754 */ 3755 static int 3756 _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout) 3757 { 3758 u32 count, cntdn; 3759 u32 current_state; 3760 3761 count = 0; 3762 cntdn = 1000 * timeout; 3763 do { 3764 current_state = mpt3sas_base_get_iocstate(ioc, 1); 3765 if (current_state == ioc_state) 3766 return 0; 3767 if (count && current_state == MPI2_IOC_STATE_FAULT) 3768 break; 3769 3770 usleep_range(1000, 1500); 3771 count++; 3772 } while (--cntdn); 3773 3774 return current_state; 3775 } 3776 3777 /** 3778 * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by 3779 * a write to the doorbell) 3780 * @ioc: per adapter object 3781 * @timeout: timeout in second 3782 * 3783 * Returns 0 for success, non-zero for failure. 3784 * 3785 * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell. 3786 */ 3787 static int 3788 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc); 3789 3790 static int 3791 _base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout) 3792 { 3793 u32 cntdn, count; 3794 u32 int_status; 3795 3796 count = 0; 3797 cntdn = 1000 * timeout; 3798 do { 3799 int_status = readl(&ioc->chip->HostInterruptStatus); 3800 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { 3801 dhsprintk(ioc, pr_info(MPT3SAS_FMT 3802 "%s: successful count(%d), timeout(%d)\n", 3803 ioc->name, __func__, count, timeout)); 3804 return 0; 3805 } 3806 3807 usleep_range(1000, 1500); 3808 count++; 3809 } while (--cntdn); 3810 3811 pr_err(MPT3SAS_FMT 3812 "%s: failed due to timeout count(%d), int_status(%x)!\n", 3813 ioc->name, __func__, count, int_status); 3814 return -EFAULT; 3815 } 3816 3817 static int 3818 _base_spin_on_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout) 3819 { 3820 u32 cntdn, count; 3821 u32 int_status; 3822 3823 count = 0; 3824 cntdn = 2000 * timeout; 3825 do { 3826 int_status = readl(&ioc->chip->HostInterruptStatus); 3827 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { 3828 dhsprintk(ioc, pr_info(MPT3SAS_FMT 3829 "%s: successful count(%d), timeout(%d)\n", 3830 ioc->name, __func__, count, timeout)); 3831 return 0; 3832 } 3833 3834 udelay(500); 3835 count++; 3836 } while (--cntdn); 3837 3838 pr_err(MPT3SAS_FMT 3839 "%s: failed due to timeout count(%d), int_status(%x)!\n", 3840 ioc->name, __func__, count, int_status); 3841 return -EFAULT; 3842 3843 } 3844 3845 /** 3846 * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell. 3847 * @ioc: per adapter object 3848 * @timeout: timeout in second 3849 * 3850 * Returns 0 for success, non-zero for failure. 3851 * 3852 * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to 3853 * doorbell. 3854 */ 3855 static int 3856 _base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout) 3857 { 3858 u32 cntdn, count; 3859 u32 int_status; 3860 u32 doorbell; 3861 3862 count = 0; 3863 cntdn = 1000 * timeout; 3864 do { 3865 int_status = readl(&ioc->chip->HostInterruptStatus); 3866 if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) { 3867 dhsprintk(ioc, pr_info(MPT3SAS_FMT 3868 "%s: successful count(%d), timeout(%d)\n", 3869 ioc->name, __func__, count, timeout)); 3870 return 0; 3871 } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { 3872 doorbell = readl(&ioc->chip->Doorbell); 3873 if ((doorbell & MPI2_IOC_STATE_MASK) == 3874 MPI2_IOC_STATE_FAULT) { 3875 mpt3sas_base_fault_info(ioc , doorbell); 3876 return -EFAULT; 3877 } 3878 } else if (int_status == 0xFFFFFFFF) 3879 goto out; 3880 3881 usleep_range(1000, 1500); 3882 count++; 3883 } while (--cntdn); 3884 3885 out: 3886 pr_err(MPT3SAS_FMT 3887 "%s: failed due to timeout count(%d), int_status(%x)!\n", 3888 ioc->name, __func__, count, int_status); 3889 return -EFAULT; 3890 } 3891 3892 /** 3893 * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use 3894 * @ioc: per adapter object 3895 * @timeout: timeout in second 3896 * 3897 * Returns 0 for success, non-zero for failure. 3898 * 3899 */ 3900 static int 3901 _base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout) 3902 { 3903 u32 cntdn, count; 3904 u32 doorbell_reg; 3905 3906 count = 0; 3907 cntdn = 1000 * timeout; 3908 do { 3909 doorbell_reg = readl(&ioc->chip->Doorbell); 3910 if (!(doorbell_reg & MPI2_DOORBELL_USED)) { 3911 dhsprintk(ioc, pr_info(MPT3SAS_FMT 3912 "%s: successful count(%d), timeout(%d)\n", 3913 ioc->name, __func__, count, timeout)); 3914 return 0; 3915 } 3916 3917 usleep_range(1000, 1500); 3918 count++; 3919 } while (--cntdn); 3920 3921 pr_err(MPT3SAS_FMT 3922 "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n", 3923 ioc->name, __func__, count, doorbell_reg); 3924 return -EFAULT; 3925 } 3926 3927 /** 3928 * _base_send_ioc_reset - send doorbell reset 3929 * @ioc: per adapter object 3930 * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET 3931 * @timeout: timeout in second 3932 * 3933 * Returns 0 for success, non-zero for failure. 3934 */ 3935 static int 3936 _base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout) 3937 { 3938 u32 ioc_state; 3939 int r = 0; 3940 3941 if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) { 3942 pr_err(MPT3SAS_FMT "%s: unknown reset_type\n", 3943 ioc->name, __func__); 3944 return -EFAULT; 3945 } 3946 3947 if (!(ioc->facts.IOCCapabilities & 3948 MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY)) 3949 return -EFAULT; 3950 3951 pr_info(MPT3SAS_FMT "sending message unit reset !!\n", ioc->name); 3952 3953 writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT, 3954 &ioc->chip->Doorbell); 3955 if ((_base_wait_for_doorbell_ack(ioc, 15))) { 3956 r = -EFAULT; 3957 goto out; 3958 } 3959 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout); 3960 if (ioc_state) { 3961 pr_err(MPT3SAS_FMT 3962 "%s: failed going to ready state (ioc_state=0x%x)\n", 3963 ioc->name, __func__, ioc_state); 3964 r = -EFAULT; 3965 goto out; 3966 } 3967 out: 3968 pr_info(MPT3SAS_FMT "message unit reset: %s\n", 3969 ioc->name, ((r == 0) ? "SUCCESS" : "FAILED")); 3970 return r; 3971 } 3972 3973 /** 3974 * _base_handshake_req_reply_wait - send request thru doorbell interface 3975 * @ioc: per adapter object 3976 * @request_bytes: request length 3977 * @request: pointer having request payload 3978 * @reply_bytes: reply length 3979 * @reply: pointer to reply payload 3980 * @timeout: timeout in second 3981 * 3982 * Returns 0 for success, non-zero for failure. 3983 */ 3984 static int 3985 _base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes, 3986 u32 *request, int reply_bytes, u16 *reply, int timeout) 3987 { 3988 MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply; 3989 int i; 3990 u8 failed; 3991 __le32 *mfp; 3992 3993 /* make sure doorbell is not in use */ 3994 if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) { 3995 pr_err(MPT3SAS_FMT 3996 "doorbell is in use (line=%d)\n", 3997 ioc->name, __LINE__); 3998 return -EFAULT; 3999 } 4000 4001 /* clear pending doorbell interrupts from previous state changes */ 4002 if (readl(&ioc->chip->HostInterruptStatus) & 4003 MPI2_HIS_IOC2SYS_DB_STATUS) 4004 writel(0, &ioc->chip->HostInterruptStatus); 4005 4006 /* send message to ioc */ 4007 writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) | 4008 ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)), 4009 &ioc->chip->Doorbell); 4010 4011 if ((_base_spin_on_doorbell_int(ioc, 5))) { 4012 pr_err(MPT3SAS_FMT 4013 "doorbell handshake int failed (line=%d)\n", 4014 ioc->name, __LINE__); 4015 return -EFAULT; 4016 } 4017 writel(0, &ioc->chip->HostInterruptStatus); 4018 4019 if ((_base_wait_for_doorbell_ack(ioc, 5))) { 4020 pr_err(MPT3SAS_FMT 4021 "doorbell handshake ack failed (line=%d)\n", 4022 ioc->name, __LINE__); 4023 return -EFAULT; 4024 } 4025 4026 /* send message 32-bits at a time */ 4027 for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) { 4028 writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell); 4029 if ((_base_wait_for_doorbell_ack(ioc, 5))) 4030 failed = 1; 4031 } 4032 4033 if (failed) { 4034 pr_err(MPT3SAS_FMT 4035 "doorbell handshake sending request failed (line=%d)\n", 4036 ioc->name, __LINE__); 4037 return -EFAULT; 4038 } 4039 4040 /* now wait for the reply */ 4041 if ((_base_wait_for_doorbell_int(ioc, timeout))) { 4042 pr_err(MPT3SAS_FMT 4043 "doorbell handshake int failed (line=%d)\n", 4044 ioc->name, __LINE__); 4045 return -EFAULT; 4046 } 4047 4048 /* read the first two 16-bits, it gives the total length of the reply */ 4049 reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell) 4050 & MPI2_DOORBELL_DATA_MASK); 4051 writel(0, &ioc->chip->HostInterruptStatus); 4052 if ((_base_wait_for_doorbell_int(ioc, 5))) { 4053 pr_err(MPT3SAS_FMT 4054 "doorbell handshake int failed (line=%d)\n", 4055 ioc->name, __LINE__); 4056 return -EFAULT; 4057 } 4058 reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell) 4059 & MPI2_DOORBELL_DATA_MASK); 4060 writel(0, &ioc->chip->HostInterruptStatus); 4061 4062 for (i = 2; i < default_reply->MsgLength * 2; i++) { 4063 if ((_base_wait_for_doorbell_int(ioc, 5))) { 4064 pr_err(MPT3SAS_FMT 4065 "doorbell handshake int failed (line=%d)\n", 4066 ioc->name, __LINE__); 4067 return -EFAULT; 4068 } 4069 if (i >= reply_bytes/2) /* overflow case */ 4070 readl(&ioc->chip->Doorbell); 4071 else 4072 reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell) 4073 & MPI2_DOORBELL_DATA_MASK); 4074 writel(0, &ioc->chip->HostInterruptStatus); 4075 } 4076 4077 _base_wait_for_doorbell_int(ioc, 5); 4078 if (_base_wait_for_doorbell_not_used(ioc, 5) != 0) { 4079 dhsprintk(ioc, pr_info(MPT3SAS_FMT 4080 "doorbell is in use (line=%d)\n", ioc->name, __LINE__)); 4081 } 4082 writel(0, &ioc->chip->HostInterruptStatus); 4083 4084 if (ioc->logging_level & MPT_DEBUG_INIT) { 4085 mfp = (__le32 *)reply; 4086 pr_info("\toffset:data\n"); 4087 for (i = 0; i < reply_bytes/4; i++) 4088 pr_info("\t[0x%02x]:%08x\n", i*4, 4089 le32_to_cpu(mfp[i])); 4090 } 4091 return 0; 4092 } 4093 4094 /** 4095 * mpt3sas_base_sas_iounit_control - send sas iounit control to FW 4096 * @ioc: per adapter object 4097 * @mpi_reply: the reply payload from FW 4098 * @mpi_request: the request payload sent to FW 4099 * 4100 * The SAS IO Unit Control Request message allows the host to perform low-level 4101 * operations, such as resets on the PHYs of the IO Unit, also allows the host 4102 * to obtain the IOC assigned device handles for a device if it has other 4103 * identifying information about the device, in addition allows the host to 4104 * remove IOC resources associated with the device. 4105 * 4106 * Returns 0 for success, non-zero for failure. 4107 */ 4108 int 4109 mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc, 4110 Mpi2SasIoUnitControlReply_t *mpi_reply, 4111 Mpi2SasIoUnitControlRequest_t *mpi_request) 4112 { 4113 u16 smid; 4114 u32 ioc_state; 4115 bool issue_reset = false; 4116 int rc; 4117 void *request; 4118 u16 wait_state_count; 4119 4120 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 4121 __func__)); 4122 4123 mutex_lock(&ioc->base_cmds.mutex); 4124 4125 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) { 4126 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n", 4127 ioc->name, __func__); 4128 rc = -EAGAIN; 4129 goto out; 4130 } 4131 4132 wait_state_count = 0; 4133 ioc_state = mpt3sas_base_get_iocstate(ioc, 1); 4134 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) { 4135 if (wait_state_count++ == 10) { 4136 pr_err(MPT3SAS_FMT 4137 "%s: failed due to ioc not operational\n", 4138 ioc->name, __func__); 4139 rc = -EFAULT; 4140 goto out; 4141 } 4142 ssleep(1); 4143 ioc_state = mpt3sas_base_get_iocstate(ioc, 1); 4144 pr_info(MPT3SAS_FMT 4145 "%s: waiting for operational state(count=%d)\n", 4146 ioc->name, __func__, wait_state_count); 4147 } 4148 4149 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 4150 if (!smid) { 4151 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", 4152 ioc->name, __func__); 4153 rc = -EAGAIN; 4154 goto out; 4155 } 4156 4157 rc = 0; 4158 ioc->base_cmds.status = MPT3_CMD_PENDING; 4159 request = mpt3sas_base_get_msg_frame(ioc, smid); 4160 ioc->base_cmds.smid = smid; 4161 memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t)); 4162 if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET || 4163 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) 4164 ioc->ioc_link_reset_in_progress = 1; 4165 init_completion(&ioc->base_cmds.done); 4166 ioc->put_smid_default(ioc, smid); 4167 wait_for_completion_timeout(&ioc->base_cmds.done, 4168 msecs_to_jiffies(10000)); 4169 if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET || 4170 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) && 4171 ioc->ioc_link_reset_in_progress) 4172 ioc->ioc_link_reset_in_progress = 0; 4173 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { 4174 pr_err(MPT3SAS_FMT "%s: timeout\n", 4175 ioc->name, __func__); 4176 _debug_dump_mf(mpi_request, 4177 sizeof(Mpi2SasIoUnitControlRequest_t)/4); 4178 if (!(ioc->base_cmds.status & MPT3_CMD_RESET)) 4179 issue_reset = true; 4180 goto issue_host_reset; 4181 } 4182 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) 4183 memcpy(mpi_reply, ioc->base_cmds.reply, 4184 sizeof(Mpi2SasIoUnitControlReply_t)); 4185 else 4186 memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t)); 4187 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 4188 goto out; 4189 4190 issue_host_reset: 4191 if (issue_reset) 4192 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER); 4193 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 4194 rc = -EFAULT; 4195 out: 4196 mutex_unlock(&ioc->base_cmds.mutex); 4197 return rc; 4198 } 4199 4200 /** 4201 * mpt3sas_base_scsi_enclosure_processor - sending request to sep device 4202 * @ioc: per adapter object 4203 * @mpi_reply: the reply payload from FW 4204 * @mpi_request: the request payload sent to FW 4205 * 4206 * The SCSI Enclosure Processor request message causes the IOC to 4207 * communicate with SES devices to control LED status signals. 4208 * 4209 * Returns 0 for success, non-zero for failure. 4210 */ 4211 int 4212 mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc, 4213 Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request) 4214 { 4215 u16 smid; 4216 u32 ioc_state; 4217 bool issue_reset = false; 4218 int rc; 4219 void *request; 4220 u16 wait_state_count; 4221 4222 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 4223 __func__)); 4224 4225 mutex_lock(&ioc->base_cmds.mutex); 4226 4227 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) { 4228 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n", 4229 ioc->name, __func__); 4230 rc = -EAGAIN; 4231 goto out; 4232 } 4233 4234 wait_state_count = 0; 4235 ioc_state = mpt3sas_base_get_iocstate(ioc, 1); 4236 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) { 4237 if (wait_state_count++ == 10) { 4238 pr_err(MPT3SAS_FMT 4239 "%s: failed due to ioc not operational\n", 4240 ioc->name, __func__); 4241 rc = -EFAULT; 4242 goto out; 4243 } 4244 ssleep(1); 4245 ioc_state = mpt3sas_base_get_iocstate(ioc, 1); 4246 pr_info(MPT3SAS_FMT 4247 "%s: waiting for operational state(count=%d)\n", 4248 ioc->name, 4249 __func__, wait_state_count); 4250 } 4251 4252 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 4253 if (!smid) { 4254 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", 4255 ioc->name, __func__); 4256 rc = -EAGAIN; 4257 goto out; 4258 } 4259 4260 rc = 0; 4261 ioc->base_cmds.status = MPT3_CMD_PENDING; 4262 request = mpt3sas_base_get_msg_frame(ioc, smid); 4263 ioc->base_cmds.smid = smid; 4264 memcpy(request, mpi_request, sizeof(Mpi2SepReply_t)); 4265 init_completion(&ioc->base_cmds.done); 4266 ioc->put_smid_default(ioc, smid); 4267 wait_for_completion_timeout(&ioc->base_cmds.done, 4268 msecs_to_jiffies(10000)); 4269 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { 4270 pr_err(MPT3SAS_FMT "%s: timeout\n", 4271 ioc->name, __func__); 4272 _debug_dump_mf(mpi_request, 4273 sizeof(Mpi2SepRequest_t)/4); 4274 if (!(ioc->base_cmds.status & MPT3_CMD_RESET)) 4275 issue_reset = false; 4276 goto issue_host_reset; 4277 } 4278 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) 4279 memcpy(mpi_reply, ioc->base_cmds.reply, 4280 sizeof(Mpi2SepReply_t)); 4281 else 4282 memset(mpi_reply, 0, sizeof(Mpi2SepReply_t)); 4283 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 4284 goto out; 4285 4286 issue_host_reset: 4287 if (issue_reset) 4288 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER); 4289 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 4290 rc = -EFAULT; 4291 out: 4292 mutex_unlock(&ioc->base_cmds.mutex); 4293 return rc; 4294 } 4295 4296 /** 4297 * _base_get_port_facts - obtain port facts reply and save in ioc 4298 * @ioc: per adapter object 4299 * 4300 * Returns 0 for success, non-zero for failure. 4301 */ 4302 static int 4303 _base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port) 4304 { 4305 Mpi2PortFactsRequest_t mpi_request; 4306 Mpi2PortFactsReply_t mpi_reply; 4307 struct mpt3sas_port_facts *pfacts; 4308 int mpi_reply_sz, mpi_request_sz, r; 4309 4310 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 4311 __func__)); 4312 4313 mpi_reply_sz = sizeof(Mpi2PortFactsReply_t); 4314 mpi_request_sz = sizeof(Mpi2PortFactsRequest_t); 4315 memset(&mpi_request, 0, mpi_request_sz); 4316 mpi_request.Function = MPI2_FUNCTION_PORT_FACTS; 4317 mpi_request.PortNumber = port; 4318 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz, 4319 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5); 4320 4321 if (r != 0) { 4322 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n", 4323 ioc->name, __func__, r); 4324 return r; 4325 } 4326 4327 pfacts = &ioc->pfacts[port]; 4328 memset(pfacts, 0, sizeof(struct mpt3sas_port_facts)); 4329 pfacts->PortNumber = mpi_reply.PortNumber; 4330 pfacts->VP_ID = mpi_reply.VP_ID; 4331 pfacts->VF_ID = mpi_reply.VF_ID; 4332 pfacts->MaxPostedCmdBuffers = 4333 le16_to_cpu(mpi_reply.MaxPostedCmdBuffers); 4334 4335 return 0; 4336 } 4337 4338 /** 4339 * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL 4340 * @ioc: per adapter object 4341 * @timeout: 4342 * 4343 * Returns 0 for success, non-zero for failure. 4344 */ 4345 static int 4346 _base_wait_for_iocstate(struct MPT3SAS_ADAPTER *ioc, int timeout) 4347 { 4348 u32 ioc_state; 4349 int rc; 4350 4351 dinitprintk(ioc, printk(MPT3SAS_FMT "%s\n", ioc->name, 4352 __func__)); 4353 4354 if (ioc->pci_error_recovery) { 4355 dfailprintk(ioc, printk(MPT3SAS_FMT 4356 "%s: host in pci error recovery\n", ioc->name, __func__)); 4357 return -EFAULT; 4358 } 4359 4360 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 4361 dhsprintk(ioc, printk(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n", 4362 ioc->name, __func__, ioc_state)); 4363 4364 if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) || 4365 (ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL) 4366 return 0; 4367 4368 if (ioc_state & MPI2_DOORBELL_USED) { 4369 dhsprintk(ioc, printk(MPT3SAS_FMT 4370 "unexpected doorbell active!\n", ioc->name)); 4371 goto issue_diag_reset; 4372 } 4373 4374 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { 4375 mpt3sas_base_fault_info(ioc, ioc_state & 4376 MPI2_DOORBELL_DATA_MASK); 4377 goto issue_diag_reset; 4378 } 4379 4380 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout); 4381 if (ioc_state) { 4382 dfailprintk(ioc, printk(MPT3SAS_FMT 4383 "%s: failed going to ready state (ioc_state=0x%x)\n", 4384 ioc->name, __func__, ioc_state)); 4385 return -EFAULT; 4386 } 4387 4388 issue_diag_reset: 4389 rc = _base_diag_reset(ioc); 4390 return rc; 4391 } 4392 4393 /** 4394 * _base_get_ioc_facts - obtain ioc facts reply and save in ioc 4395 * @ioc: per adapter object 4396 * 4397 * Returns 0 for success, non-zero for failure. 4398 */ 4399 static int 4400 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc) 4401 { 4402 Mpi2IOCFactsRequest_t mpi_request; 4403 Mpi2IOCFactsReply_t mpi_reply; 4404 struct mpt3sas_facts *facts; 4405 int mpi_reply_sz, mpi_request_sz, r; 4406 4407 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 4408 __func__)); 4409 4410 r = _base_wait_for_iocstate(ioc, 10); 4411 if (r) { 4412 dfailprintk(ioc, printk(MPT3SAS_FMT 4413 "%s: failed getting to correct state\n", 4414 ioc->name, __func__)); 4415 return r; 4416 } 4417 mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t); 4418 mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t); 4419 memset(&mpi_request, 0, mpi_request_sz); 4420 mpi_request.Function = MPI2_FUNCTION_IOC_FACTS; 4421 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz, 4422 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5); 4423 4424 if (r != 0) { 4425 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n", 4426 ioc->name, __func__, r); 4427 return r; 4428 } 4429 4430 facts = &ioc->facts; 4431 memset(facts, 0, sizeof(struct mpt3sas_facts)); 4432 facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion); 4433 facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion); 4434 facts->VP_ID = mpi_reply.VP_ID; 4435 facts->VF_ID = mpi_reply.VF_ID; 4436 facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions); 4437 facts->MaxChainDepth = mpi_reply.MaxChainDepth; 4438 facts->WhoInit = mpi_reply.WhoInit; 4439 facts->NumberOfPorts = mpi_reply.NumberOfPorts; 4440 facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors; 4441 facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit); 4442 facts->MaxReplyDescriptorPostQueueDepth = 4443 le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth); 4444 facts->ProductID = le16_to_cpu(mpi_reply.ProductID); 4445 facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities); 4446 if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID)) 4447 ioc->ir_firmware = 1; 4448 if ((facts->IOCCapabilities & 4449 MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE)) 4450 ioc->rdpq_array_capable = 1; 4451 if (facts->IOCCapabilities & MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ) 4452 ioc->atomic_desc_capable = 1; 4453 facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word); 4454 facts->IOCRequestFrameSize = 4455 le16_to_cpu(mpi_reply.IOCRequestFrameSize); 4456 if (ioc->hba_mpi_version_belonged != MPI2_VERSION) { 4457 facts->IOCMaxChainSegmentSize = 4458 le16_to_cpu(mpi_reply.IOCMaxChainSegmentSize); 4459 } 4460 facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators); 4461 facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets); 4462 ioc->shost->max_id = -1; 4463 facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders); 4464 facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures); 4465 facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags); 4466 facts->HighPriorityCredit = 4467 le16_to_cpu(mpi_reply.HighPriorityCredit); 4468 facts->ReplyFrameSize = mpi_reply.ReplyFrameSize; 4469 facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle); 4470 4471 dinitprintk(ioc, pr_info(MPT3SAS_FMT 4472 "hba queue depth(%d), max chains per io(%d)\n", 4473 ioc->name, facts->RequestCredit, 4474 facts->MaxChainDepth)); 4475 dinitprintk(ioc, pr_info(MPT3SAS_FMT 4476 "request frame size(%d), reply frame size(%d)\n", ioc->name, 4477 facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4)); 4478 return 0; 4479 } 4480 4481 /** 4482 * _base_send_ioc_init - send ioc_init to firmware 4483 * @ioc: per adapter object 4484 * 4485 * Returns 0 for success, non-zero for failure. 4486 */ 4487 static int 4488 _base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc) 4489 { 4490 Mpi2IOCInitRequest_t mpi_request; 4491 Mpi2IOCInitReply_t mpi_reply; 4492 int i, r = 0; 4493 ktime_t current_time; 4494 u16 ioc_status; 4495 u32 reply_post_free_array_sz = 0; 4496 Mpi2IOCInitRDPQArrayEntry *reply_post_free_array = NULL; 4497 dma_addr_t reply_post_free_array_dma; 4498 4499 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 4500 __func__)); 4501 4502 memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t)); 4503 mpi_request.Function = MPI2_FUNCTION_IOC_INIT; 4504 mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER; 4505 mpi_request.VF_ID = 0; /* TODO */ 4506 mpi_request.VP_ID = 0; 4507 mpi_request.MsgVersion = cpu_to_le16(ioc->hba_mpi_version_belonged); 4508 mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION); 4509 4510 if (_base_is_controller_msix_enabled(ioc)) 4511 mpi_request.HostMSIxVectors = ioc->reply_queue_count; 4512 mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4); 4513 mpi_request.ReplyDescriptorPostQueueDepth = 4514 cpu_to_le16(ioc->reply_post_queue_depth); 4515 mpi_request.ReplyFreeQueueDepth = 4516 cpu_to_le16(ioc->reply_free_queue_depth); 4517 4518 mpi_request.SenseBufferAddressHigh = 4519 cpu_to_le32((u64)ioc->sense_dma >> 32); 4520 mpi_request.SystemReplyAddressHigh = 4521 cpu_to_le32((u64)ioc->reply_dma >> 32); 4522 mpi_request.SystemRequestFrameBaseAddress = 4523 cpu_to_le64((u64)ioc->request_dma); 4524 mpi_request.ReplyFreeQueueAddress = 4525 cpu_to_le64((u64)ioc->reply_free_dma); 4526 4527 if (ioc->rdpq_array_enable) { 4528 reply_post_free_array_sz = ioc->reply_queue_count * 4529 sizeof(Mpi2IOCInitRDPQArrayEntry); 4530 reply_post_free_array = pci_alloc_consistent(ioc->pdev, 4531 reply_post_free_array_sz, &reply_post_free_array_dma); 4532 if (!reply_post_free_array) { 4533 pr_err(MPT3SAS_FMT 4534 "reply_post_free_array: pci_alloc_consistent failed\n", 4535 ioc->name); 4536 r = -ENOMEM; 4537 goto out; 4538 } 4539 memset(reply_post_free_array, 0, reply_post_free_array_sz); 4540 for (i = 0; i < ioc->reply_queue_count; i++) 4541 reply_post_free_array[i].RDPQBaseAddress = 4542 cpu_to_le64( 4543 (u64)ioc->reply_post[i].reply_post_free_dma); 4544 mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE; 4545 mpi_request.ReplyDescriptorPostQueueAddress = 4546 cpu_to_le64((u64)reply_post_free_array_dma); 4547 } else { 4548 mpi_request.ReplyDescriptorPostQueueAddress = 4549 cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma); 4550 } 4551 4552 /* This time stamp specifies number of milliseconds 4553 * since epoch ~ midnight January 1, 1970. 4554 */ 4555 current_time = ktime_get_real(); 4556 mpi_request.TimeStamp = cpu_to_le64(ktime_to_ms(current_time)); 4557 4558 if (ioc->logging_level & MPT_DEBUG_INIT) { 4559 __le32 *mfp; 4560 int i; 4561 4562 mfp = (__le32 *)&mpi_request; 4563 pr_info("\toffset:data\n"); 4564 for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++) 4565 pr_info("\t[0x%02x]:%08x\n", i*4, 4566 le32_to_cpu(mfp[i])); 4567 } 4568 4569 r = _base_handshake_req_reply_wait(ioc, 4570 sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request, 4571 sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10); 4572 4573 if (r != 0) { 4574 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n", 4575 ioc->name, __func__, r); 4576 goto out; 4577 } 4578 4579 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK; 4580 if (ioc_status != MPI2_IOCSTATUS_SUCCESS || 4581 mpi_reply.IOCLogInfo) { 4582 pr_err(MPT3SAS_FMT "%s: failed\n", ioc->name, __func__); 4583 r = -EIO; 4584 } 4585 4586 out: 4587 if (reply_post_free_array) 4588 pci_free_consistent(ioc->pdev, reply_post_free_array_sz, 4589 reply_post_free_array, 4590 reply_post_free_array_dma); 4591 return r; 4592 } 4593 4594 /** 4595 * mpt3sas_port_enable_done - command completion routine for port enable 4596 * @ioc: per adapter object 4597 * @smid: system request message index 4598 * @msix_index: MSIX table index supplied by the OS 4599 * @reply: reply message frame(lower 32bit addr) 4600 * 4601 * Return 1 meaning mf should be freed from _base_interrupt 4602 * 0 means the mf is freed from this function. 4603 */ 4604 u8 4605 mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, 4606 u32 reply) 4607 { 4608 MPI2DefaultReply_t *mpi_reply; 4609 u16 ioc_status; 4610 4611 if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED) 4612 return 1; 4613 4614 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); 4615 if (!mpi_reply) 4616 return 1; 4617 4618 if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE) 4619 return 1; 4620 4621 ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING; 4622 ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE; 4623 ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID; 4624 memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4); 4625 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK; 4626 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) 4627 ioc->port_enable_failed = 1; 4628 4629 if (ioc->is_driver_loading) { 4630 if (ioc_status == MPI2_IOCSTATUS_SUCCESS) { 4631 mpt3sas_port_enable_complete(ioc); 4632 return 1; 4633 } else { 4634 ioc->start_scan_failed = ioc_status; 4635 ioc->start_scan = 0; 4636 return 1; 4637 } 4638 } 4639 complete(&ioc->port_enable_cmds.done); 4640 return 1; 4641 } 4642 4643 /** 4644 * _base_send_port_enable - send port_enable(discovery stuff) to firmware 4645 * @ioc: per adapter object 4646 * 4647 * Returns 0 for success, non-zero for failure. 4648 */ 4649 static int 4650 _base_send_port_enable(struct MPT3SAS_ADAPTER *ioc) 4651 { 4652 Mpi2PortEnableRequest_t *mpi_request; 4653 Mpi2PortEnableReply_t *mpi_reply; 4654 int r = 0; 4655 u16 smid; 4656 u16 ioc_status; 4657 4658 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name); 4659 4660 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { 4661 pr_err(MPT3SAS_FMT "%s: internal command already in use\n", 4662 ioc->name, __func__); 4663 return -EAGAIN; 4664 } 4665 4666 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx); 4667 if (!smid) { 4668 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", 4669 ioc->name, __func__); 4670 return -EAGAIN; 4671 } 4672 4673 ioc->port_enable_cmds.status = MPT3_CMD_PENDING; 4674 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 4675 ioc->port_enable_cmds.smid = smid; 4676 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t)); 4677 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE; 4678 4679 init_completion(&ioc->port_enable_cmds.done); 4680 ioc->put_smid_default(ioc, smid); 4681 wait_for_completion_timeout(&ioc->port_enable_cmds.done, 300*HZ); 4682 if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) { 4683 pr_err(MPT3SAS_FMT "%s: timeout\n", 4684 ioc->name, __func__); 4685 _debug_dump_mf(mpi_request, 4686 sizeof(Mpi2PortEnableRequest_t)/4); 4687 if (ioc->port_enable_cmds.status & MPT3_CMD_RESET) 4688 r = -EFAULT; 4689 else 4690 r = -ETIME; 4691 goto out; 4692 } 4693 4694 mpi_reply = ioc->port_enable_cmds.reply; 4695 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK; 4696 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 4697 pr_err(MPT3SAS_FMT "%s: failed with (ioc_status=0x%08x)\n", 4698 ioc->name, __func__, ioc_status); 4699 r = -EFAULT; 4700 goto out; 4701 } 4702 4703 out: 4704 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED; 4705 pr_info(MPT3SAS_FMT "port enable: %s\n", ioc->name, ((r == 0) ? 4706 "SUCCESS" : "FAILED")); 4707 return r; 4708 } 4709 4710 /** 4711 * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply) 4712 * @ioc: per adapter object 4713 * 4714 * Returns 0 for success, non-zero for failure. 4715 */ 4716 int 4717 mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc) 4718 { 4719 Mpi2PortEnableRequest_t *mpi_request; 4720 u16 smid; 4721 4722 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name); 4723 4724 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { 4725 pr_err(MPT3SAS_FMT "%s: internal command already in use\n", 4726 ioc->name, __func__); 4727 return -EAGAIN; 4728 } 4729 4730 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx); 4731 if (!smid) { 4732 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", 4733 ioc->name, __func__); 4734 return -EAGAIN; 4735 } 4736 4737 ioc->port_enable_cmds.status = MPT3_CMD_PENDING; 4738 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 4739 ioc->port_enable_cmds.smid = smid; 4740 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t)); 4741 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE; 4742 4743 ioc->put_smid_default(ioc, smid); 4744 return 0; 4745 } 4746 4747 /** 4748 * _base_determine_wait_on_discovery - desposition 4749 * @ioc: per adapter object 4750 * 4751 * Decide whether to wait on discovery to complete. Used to either 4752 * locate boot device, or report volumes ahead of physical devices. 4753 * 4754 * Returns 1 for wait, 0 for don't wait 4755 */ 4756 static int 4757 _base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc) 4758 { 4759 /* We wait for discovery to complete if IR firmware is loaded. 4760 * The sas topology events arrive before PD events, so we need time to 4761 * turn on the bit in ioc->pd_handles to indicate PD 4762 * Also, it maybe required to report Volumes ahead of physical 4763 * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set. 4764 */ 4765 if (ioc->ir_firmware) 4766 return 1; 4767 4768 /* if no Bios, then we don't need to wait */ 4769 if (!ioc->bios_pg3.BiosVersion) 4770 return 0; 4771 4772 /* Bios is present, then we drop down here. 4773 * 4774 * If there any entries in the Bios Page 2, then we wait 4775 * for discovery to complete. 4776 */ 4777 4778 /* Current Boot Device */ 4779 if ((ioc->bios_pg2.CurrentBootDeviceForm & 4780 MPI2_BIOSPAGE2_FORM_MASK) == 4781 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED && 4782 /* Request Boot Device */ 4783 (ioc->bios_pg2.ReqBootDeviceForm & 4784 MPI2_BIOSPAGE2_FORM_MASK) == 4785 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED && 4786 /* Alternate Request Boot Device */ 4787 (ioc->bios_pg2.ReqAltBootDeviceForm & 4788 MPI2_BIOSPAGE2_FORM_MASK) == 4789 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED) 4790 return 0; 4791 4792 return 1; 4793 } 4794 4795 /** 4796 * _base_unmask_events - turn on notification for this event 4797 * @ioc: per adapter object 4798 * @event: firmware event 4799 * 4800 * The mask is stored in ioc->event_masks. 4801 */ 4802 static void 4803 _base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event) 4804 { 4805 u32 desired_event; 4806 4807 if (event >= 128) 4808 return; 4809 4810 desired_event = (1 << (event % 32)); 4811 4812 if (event < 32) 4813 ioc->event_masks[0] &= ~desired_event; 4814 else if (event < 64) 4815 ioc->event_masks[1] &= ~desired_event; 4816 else if (event < 96) 4817 ioc->event_masks[2] &= ~desired_event; 4818 else if (event < 128) 4819 ioc->event_masks[3] &= ~desired_event; 4820 } 4821 4822 /** 4823 * _base_event_notification - send event notification 4824 * @ioc: per adapter object 4825 * 4826 * Returns 0 for success, non-zero for failure. 4827 */ 4828 static int 4829 _base_event_notification(struct MPT3SAS_ADAPTER *ioc) 4830 { 4831 Mpi2EventNotificationRequest_t *mpi_request; 4832 u16 smid; 4833 int r = 0; 4834 int i; 4835 4836 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 4837 __func__)); 4838 4839 if (ioc->base_cmds.status & MPT3_CMD_PENDING) { 4840 pr_err(MPT3SAS_FMT "%s: internal command already in use\n", 4841 ioc->name, __func__); 4842 return -EAGAIN; 4843 } 4844 4845 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 4846 if (!smid) { 4847 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", 4848 ioc->name, __func__); 4849 return -EAGAIN; 4850 } 4851 ioc->base_cmds.status = MPT3_CMD_PENDING; 4852 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 4853 ioc->base_cmds.smid = smid; 4854 memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t)); 4855 mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION; 4856 mpi_request->VF_ID = 0; /* TODO */ 4857 mpi_request->VP_ID = 0; 4858 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 4859 mpi_request->EventMasks[i] = 4860 cpu_to_le32(ioc->event_masks[i]); 4861 init_completion(&ioc->base_cmds.done); 4862 ioc->put_smid_default(ioc, smid); 4863 wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ); 4864 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { 4865 pr_err(MPT3SAS_FMT "%s: timeout\n", 4866 ioc->name, __func__); 4867 _debug_dump_mf(mpi_request, 4868 sizeof(Mpi2EventNotificationRequest_t)/4); 4869 if (ioc->base_cmds.status & MPT3_CMD_RESET) 4870 r = -EFAULT; 4871 else 4872 r = -ETIME; 4873 } else 4874 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s: complete\n", 4875 ioc->name, __func__)); 4876 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 4877 return r; 4878 } 4879 4880 /** 4881 * mpt3sas_base_validate_event_type - validating event types 4882 * @ioc: per adapter object 4883 * @event: firmware event 4884 * 4885 * This will turn on firmware event notification when application 4886 * ask for that event. We don't mask events that are already enabled. 4887 */ 4888 void 4889 mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type) 4890 { 4891 int i, j; 4892 u32 event_mask, desired_event; 4893 u8 send_update_to_fw; 4894 4895 for (i = 0, send_update_to_fw = 0; i < 4896 MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) { 4897 event_mask = ~event_type[i]; 4898 desired_event = 1; 4899 for (j = 0; j < 32; j++) { 4900 if (!(event_mask & desired_event) && 4901 (ioc->event_masks[i] & desired_event)) { 4902 ioc->event_masks[i] &= ~desired_event; 4903 send_update_to_fw = 1; 4904 } 4905 desired_event = (desired_event << 1); 4906 } 4907 } 4908 4909 if (!send_update_to_fw) 4910 return; 4911 4912 mutex_lock(&ioc->base_cmds.mutex); 4913 _base_event_notification(ioc); 4914 mutex_unlock(&ioc->base_cmds.mutex); 4915 } 4916 4917 /** 4918 * _base_diag_reset - the "big hammer" start of day reset 4919 * @ioc: per adapter object 4920 * 4921 * Returns 0 for success, non-zero for failure. 4922 */ 4923 static int 4924 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc) 4925 { 4926 u32 host_diagnostic; 4927 u32 ioc_state; 4928 u32 count; 4929 u32 hcb_size; 4930 4931 pr_info(MPT3SAS_FMT "sending diag reset !!\n", ioc->name); 4932 4933 drsprintk(ioc, pr_info(MPT3SAS_FMT "clear interrupts\n", 4934 ioc->name)); 4935 4936 count = 0; 4937 do { 4938 /* Write magic sequence to WriteSequence register 4939 * Loop until in diagnostic mode 4940 */ 4941 drsprintk(ioc, pr_info(MPT3SAS_FMT 4942 "write magic sequence\n", ioc->name)); 4943 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence); 4944 writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence); 4945 writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence); 4946 writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence); 4947 writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence); 4948 writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence); 4949 writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence); 4950 4951 /* wait 100 msec */ 4952 msleep(100); 4953 4954 if (count++ > 20) 4955 goto out; 4956 4957 host_diagnostic = readl(&ioc->chip->HostDiagnostic); 4958 drsprintk(ioc, pr_info(MPT3SAS_FMT 4959 "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n", 4960 ioc->name, count, host_diagnostic)); 4961 4962 } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0); 4963 4964 hcb_size = readl(&ioc->chip->HCBSize); 4965 4966 drsprintk(ioc, pr_info(MPT3SAS_FMT "diag reset: issued\n", 4967 ioc->name)); 4968 writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER, 4969 &ioc->chip->HostDiagnostic); 4970 4971 /*This delay allows the chip PCIe hardware time to finish reset tasks*/ 4972 msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000); 4973 4974 /* Approximately 300 second max wait */ 4975 for (count = 0; count < (300000000 / 4976 MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) { 4977 4978 host_diagnostic = readl(&ioc->chip->HostDiagnostic); 4979 4980 if (host_diagnostic == 0xFFFFFFFF) 4981 goto out; 4982 if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER)) 4983 break; 4984 4985 msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC / 1000); 4986 } 4987 4988 if (host_diagnostic & MPI2_DIAG_HCB_MODE) { 4989 4990 drsprintk(ioc, pr_info(MPT3SAS_FMT 4991 "restart the adapter assuming the HCB Address points to good F/W\n", 4992 ioc->name)); 4993 host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK; 4994 host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW; 4995 writel(host_diagnostic, &ioc->chip->HostDiagnostic); 4996 4997 drsprintk(ioc, pr_info(MPT3SAS_FMT 4998 "re-enable the HCDW\n", ioc->name)); 4999 writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE, 5000 &ioc->chip->HCBSize); 5001 } 5002 5003 drsprintk(ioc, pr_info(MPT3SAS_FMT "restart the adapter\n", 5004 ioc->name)); 5005 writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET, 5006 &ioc->chip->HostDiagnostic); 5007 5008 drsprintk(ioc, pr_info(MPT3SAS_FMT 5009 "disable writes to the diagnostic register\n", ioc->name)); 5010 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence); 5011 5012 drsprintk(ioc, pr_info(MPT3SAS_FMT 5013 "Wait for FW to go to the READY state\n", ioc->name)); 5014 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20); 5015 if (ioc_state) { 5016 pr_err(MPT3SAS_FMT 5017 "%s: failed going to ready state (ioc_state=0x%x)\n", 5018 ioc->name, __func__, ioc_state); 5019 goto out; 5020 } 5021 5022 pr_info(MPT3SAS_FMT "diag reset: SUCCESS\n", ioc->name); 5023 return 0; 5024 5025 out: 5026 pr_err(MPT3SAS_FMT "diag reset: FAILED\n", ioc->name); 5027 return -EFAULT; 5028 } 5029 5030 /** 5031 * _base_make_ioc_ready - put controller in READY state 5032 * @ioc: per adapter object 5033 * @type: FORCE_BIG_HAMMER or SOFT_RESET 5034 * 5035 * Returns 0 for success, non-zero for failure. 5036 */ 5037 static int 5038 _base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, enum reset_type type) 5039 { 5040 u32 ioc_state; 5041 int rc; 5042 int count; 5043 5044 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 5045 __func__)); 5046 5047 if (ioc->pci_error_recovery) 5048 return 0; 5049 5050 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 5051 dhsprintk(ioc, pr_info(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n", 5052 ioc->name, __func__, ioc_state)); 5053 5054 /* if in RESET state, it should move to READY state shortly */ 5055 count = 0; 5056 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) { 5057 while ((ioc_state & MPI2_IOC_STATE_MASK) != 5058 MPI2_IOC_STATE_READY) { 5059 if (count++ == 10) { 5060 pr_err(MPT3SAS_FMT 5061 "%s: failed going to ready state (ioc_state=0x%x)\n", 5062 ioc->name, __func__, ioc_state); 5063 return -EFAULT; 5064 } 5065 ssleep(1); 5066 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 5067 } 5068 } 5069 5070 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) 5071 return 0; 5072 5073 if (ioc_state & MPI2_DOORBELL_USED) { 5074 dhsprintk(ioc, pr_info(MPT3SAS_FMT 5075 "unexpected doorbell active!\n", 5076 ioc->name)); 5077 goto issue_diag_reset; 5078 } 5079 5080 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { 5081 mpt3sas_base_fault_info(ioc, ioc_state & 5082 MPI2_DOORBELL_DATA_MASK); 5083 goto issue_diag_reset; 5084 } 5085 5086 if (type == FORCE_BIG_HAMMER) 5087 goto issue_diag_reset; 5088 5089 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL) 5090 if (!(_base_send_ioc_reset(ioc, 5091 MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15))) { 5092 return 0; 5093 } 5094 5095 issue_diag_reset: 5096 rc = _base_diag_reset(ioc); 5097 return rc; 5098 } 5099 5100 /** 5101 * _base_make_ioc_operational - put controller in OPERATIONAL state 5102 * @ioc: per adapter object 5103 * 5104 * Returns 0 for success, non-zero for failure. 5105 */ 5106 static int 5107 _base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc) 5108 { 5109 int r, i, index; 5110 unsigned long flags; 5111 u32 reply_address; 5112 u16 smid; 5113 struct _tr_list *delayed_tr, *delayed_tr_next; 5114 struct _sc_list *delayed_sc, *delayed_sc_next; 5115 struct _event_ack_list *delayed_event_ack, *delayed_event_ack_next; 5116 u8 hide_flag; 5117 struct adapter_reply_queue *reply_q; 5118 Mpi2ReplyDescriptorsUnion_t *reply_post_free_contig; 5119 5120 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 5121 __func__)); 5122 5123 /* clean the delayed target reset list */ 5124 list_for_each_entry_safe(delayed_tr, delayed_tr_next, 5125 &ioc->delayed_tr_list, list) { 5126 list_del(&delayed_tr->list); 5127 kfree(delayed_tr); 5128 } 5129 5130 5131 list_for_each_entry_safe(delayed_tr, delayed_tr_next, 5132 &ioc->delayed_tr_volume_list, list) { 5133 list_del(&delayed_tr->list); 5134 kfree(delayed_tr); 5135 } 5136 5137 list_for_each_entry_safe(delayed_sc, delayed_sc_next, 5138 &ioc->delayed_sc_list, list) { 5139 list_del(&delayed_sc->list); 5140 kfree(delayed_sc); 5141 } 5142 5143 list_for_each_entry_safe(delayed_event_ack, delayed_event_ack_next, 5144 &ioc->delayed_event_ack_list, list) { 5145 list_del(&delayed_event_ack->list); 5146 kfree(delayed_event_ack); 5147 } 5148 5149 /* initialize the scsi lookup free list */ 5150 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 5151 INIT_LIST_HEAD(&ioc->free_list); 5152 smid = 1; 5153 for (i = 0; i < ioc->scsiio_depth; i++, smid++) { 5154 INIT_LIST_HEAD(&ioc->scsi_lookup[i].chain_list); 5155 ioc->scsi_lookup[i].cb_idx = 0xFF; 5156 ioc->scsi_lookup[i].smid = smid; 5157 ioc->scsi_lookup[i].scmd = NULL; 5158 ioc->scsi_lookup[i].direct_io = 0; 5159 list_add_tail(&ioc->scsi_lookup[i].tracker_list, 5160 &ioc->free_list); 5161 } 5162 5163 /* hi-priority queue */ 5164 INIT_LIST_HEAD(&ioc->hpr_free_list); 5165 smid = ioc->hi_priority_smid; 5166 for (i = 0; i < ioc->hi_priority_depth; i++, smid++) { 5167 ioc->hpr_lookup[i].cb_idx = 0xFF; 5168 ioc->hpr_lookup[i].smid = smid; 5169 list_add_tail(&ioc->hpr_lookup[i].tracker_list, 5170 &ioc->hpr_free_list); 5171 } 5172 5173 /* internal queue */ 5174 INIT_LIST_HEAD(&ioc->internal_free_list); 5175 smid = ioc->internal_smid; 5176 for (i = 0; i < ioc->internal_depth; i++, smid++) { 5177 ioc->internal_lookup[i].cb_idx = 0xFF; 5178 ioc->internal_lookup[i].smid = smid; 5179 list_add_tail(&ioc->internal_lookup[i].tracker_list, 5180 &ioc->internal_free_list); 5181 } 5182 5183 /* chain pool */ 5184 INIT_LIST_HEAD(&ioc->free_chain_list); 5185 for (i = 0; i < ioc->chain_depth; i++) 5186 list_add_tail(&ioc->chain_lookup[i].tracker_list, 5187 &ioc->free_chain_list); 5188 5189 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 5190 5191 /* initialize Reply Free Queue */ 5192 for (i = 0, reply_address = (u32)ioc->reply_dma ; 5193 i < ioc->reply_free_queue_depth ; i++, reply_address += 5194 ioc->reply_sz) 5195 ioc->reply_free[i] = cpu_to_le32(reply_address); 5196 5197 /* initialize reply queues */ 5198 if (ioc->is_driver_loading) 5199 _base_assign_reply_queues(ioc); 5200 5201 /* initialize Reply Post Free Queue */ 5202 index = 0; 5203 reply_post_free_contig = ioc->reply_post[0].reply_post_free; 5204 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 5205 /* 5206 * If RDPQ is enabled, switch to the next allocation. 5207 * Otherwise advance within the contiguous region. 5208 */ 5209 if (ioc->rdpq_array_enable) { 5210 reply_q->reply_post_free = 5211 ioc->reply_post[index++].reply_post_free; 5212 } else { 5213 reply_q->reply_post_free = reply_post_free_contig; 5214 reply_post_free_contig += ioc->reply_post_queue_depth; 5215 } 5216 5217 reply_q->reply_post_host_index = 0; 5218 for (i = 0; i < ioc->reply_post_queue_depth; i++) 5219 reply_q->reply_post_free[i].Words = 5220 cpu_to_le64(ULLONG_MAX); 5221 if (!_base_is_controller_msix_enabled(ioc)) 5222 goto skip_init_reply_post_free_queue; 5223 } 5224 skip_init_reply_post_free_queue: 5225 5226 r = _base_send_ioc_init(ioc); 5227 if (r) 5228 return r; 5229 5230 /* initialize reply free host index */ 5231 ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1; 5232 writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex); 5233 5234 /* initialize reply post host index */ 5235 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 5236 if (ioc->combined_reply_queue) 5237 writel((reply_q->msix_index & 7)<< 5238 MPI2_RPHI_MSIX_INDEX_SHIFT, 5239 ioc->replyPostRegisterIndex[reply_q->msix_index/8]); 5240 else 5241 writel(reply_q->msix_index << 5242 MPI2_RPHI_MSIX_INDEX_SHIFT, 5243 &ioc->chip->ReplyPostHostIndex); 5244 5245 if (!_base_is_controller_msix_enabled(ioc)) 5246 goto skip_init_reply_post_host_index; 5247 } 5248 5249 skip_init_reply_post_host_index: 5250 5251 _base_unmask_interrupts(ioc); 5252 r = _base_event_notification(ioc); 5253 if (r) 5254 return r; 5255 5256 _base_static_config_pages(ioc); 5257 5258 if (ioc->is_driver_loading) { 5259 5260 if (ioc->is_warpdrive && ioc->manu_pg10.OEMIdentifier 5261 == 0x80) { 5262 hide_flag = (u8) ( 5263 le32_to_cpu(ioc->manu_pg10.OEMSpecificFlags0) & 5264 MFG_PAGE10_HIDE_SSDS_MASK); 5265 if (hide_flag != MFG_PAGE10_HIDE_SSDS_MASK) 5266 ioc->mfg_pg10_hide_flag = hide_flag; 5267 } 5268 5269 ioc->wait_for_discovery_to_complete = 5270 _base_determine_wait_on_discovery(ioc); 5271 5272 return r; /* scan_start and scan_finished support */ 5273 } 5274 5275 r = _base_send_port_enable(ioc); 5276 if (r) 5277 return r; 5278 5279 return r; 5280 } 5281 5282 /** 5283 * mpt3sas_base_free_resources - free resources controller resources 5284 * @ioc: per adapter object 5285 * 5286 * Return nothing. 5287 */ 5288 void 5289 mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc) 5290 { 5291 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 5292 __func__)); 5293 5294 /* synchronizing freeing resource with pci_access_mutex lock */ 5295 mutex_lock(&ioc->pci_access_mutex); 5296 if (ioc->chip_phys && ioc->chip) { 5297 _base_mask_interrupts(ioc); 5298 ioc->shost_recovery = 1; 5299 _base_make_ioc_ready(ioc, SOFT_RESET); 5300 ioc->shost_recovery = 0; 5301 } 5302 5303 mpt3sas_base_unmap_resources(ioc); 5304 mutex_unlock(&ioc->pci_access_mutex); 5305 return; 5306 } 5307 5308 /** 5309 * mpt3sas_base_attach - attach controller instance 5310 * @ioc: per adapter object 5311 * 5312 * Returns 0 for success, non-zero for failure. 5313 */ 5314 int 5315 mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc) 5316 { 5317 int r, i; 5318 int cpu_id, last_cpu_id = 0; 5319 5320 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 5321 __func__)); 5322 5323 /* setup cpu_msix_table */ 5324 ioc->cpu_count = num_online_cpus(); 5325 for_each_online_cpu(cpu_id) 5326 last_cpu_id = cpu_id; 5327 ioc->cpu_msix_table_sz = last_cpu_id + 1; 5328 ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL); 5329 ioc->reply_queue_count = 1; 5330 if (!ioc->cpu_msix_table) { 5331 dfailprintk(ioc, pr_info(MPT3SAS_FMT 5332 "allocation for cpu_msix_table failed!!!\n", 5333 ioc->name)); 5334 r = -ENOMEM; 5335 goto out_free_resources; 5336 } 5337 5338 if (ioc->is_warpdrive) { 5339 ioc->reply_post_host_index = kcalloc(ioc->cpu_msix_table_sz, 5340 sizeof(resource_size_t *), GFP_KERNEL); 5341 if (!ioc->reply_post_host_index) { 5342 dfailprintk(ioc, pr_info(MPT3SAS_FMT "allocation " 5343 "for reply_post_host_index failed!!!\n", 5344 ioc->name)); 5345 r = -ENOMEM; 5346 goto out_free_resources; 5347 } 5348 } 5349 5350 ioc->rdpq_array_enable_assigned = 0; 5351 ioc->dma_mask = 0; 5352 r = mpt3sas_base_map_resources(ioc); 5353 if (r) 5354 goto out_free_resources; 5355 5356 pci_set_drvdata(ioc->pdev, ioc->shost); 5357 r = _base_get_ioc_facts(ioc); 5358 if (r) 5359 goto out_free_resources; 5360 5361 switch (ioc->hba_mpi_version_belonged) { 5362 case MPI2_VERSION: 5363 ioc->build_sg_scmd = &_base_build_sg_scmd; 5364 ioc->build_sg = &_base_build_sg; 5365 ioc->build_zero_len_sge = &_base_build_zero_len_sge; 5366 break; 5367 case MPI25_VERSION: 5368 case MPI26_VERSION: 5369 /* 5370 * In SAS3.0, 5371 * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and 5372 * Target Status - all require the IEEE formated scatter gather 5373 * elements. 5374 */ 5375 ioc->build_sg_scmd = &_base_build_sg_scmd_ieee; 5376 ioc->build_sg = &_base_build_sg_ieee; 5377 ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee; 5378 ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t); 5379 5380 break; 5381 } 5382 5383 if (ioc->atomic_desc_capable) { 5384 ioc->put_smid_default = &_base_put_smid_default_atomic; 5385 ioc->put_smid_scsi_io = &_base_put_smid_scsi_io_atomic; 5386 ioc->put_smid_fast_path = &_base_put_smid_fast_path_atomic; 5387 ioc->put_smid_hi_priority = &_base_put_smid_hi_priority_atomic; 5388 } else { 5389 ioc->put_smid_default = &_base_put_smid_default; 5390 ioc->put_smid_scsi_io = &_base_put_smid_scsi_io; 5391 ioc->put_smid_fast_path = &_base_put_smid_fast_path; 5392 ioc->put_smid_hi_priority = &_base_put_smid_hi_priority; 5393 } 5394 5395 5396 /* 5397 * These function pointers for other requests that don't 5398 * the require IEEE scatter gather elements. 5399 * 5400 * For example Configuration Pages and SAS IOUNIT Control don't. 5401 */ 5402 ioc->build_sg_mpi = &_base_build_sg; 5403 ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge; 5404 5405 r = _base_make_ioc_ready(ioc, SOFT_RESET); 5406 if (r) 5407 goto out_free_resources; 5408 5409 ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts, 5410 sizeof(struct mpt3sas_port_facts), GFP_KERNEL); 5411 if (!ioc->pfacts) { 5412 r = -ENOMEM; 5413 goto out_free_resources; 5414 } 5415 5416 for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) { 5417 r = _base_get_port_facts(ioc, i); 5418 if (r) 5419 goto out_free_resources; 5420 } 5421 5422 r = _base_allocate_memory_pools(ioc); 5423 if (r) 5424 goto out_free_resources; 5425 5426 init_waitqueue_head(&ioc->reset_wq); 5427 5428 /* allocate memory pd handle bitmask list */ 5429 ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8); 5430 if (ioc->facts.MaxDevHandle % 8) 5431 ioc->pd_handles_sz++; 5432 ioc->pd_handles = kzalloc(ioc->pd_handles_sz, 5433 GFP_KERNEL); 5434 if (!ioc->pd_handles) { 5435 r = -ENOMEM; 5436 goto out_free_resources; 5437 } 5438 ioc->blocking_handles = kzalloc(ioc->pd_handles_sz, 5439 GFP_KERNEL); 5440 if (!ioc->blocking_handles) { 5441 r = -ENOMEM; 5442 goto out_free_resources; 5443 } 5444 5445 /* allocate memory for pending OS device add list */ 5446 ioc->pend_os_device_add_sz = (ioc->facts.MaxDevHandle / 8); 5447 if (ioc->facts.MaxDevHandle % 8) 5448 ioc->pend_os_device_add_sz++; 5449 ioc->pend_os_device_add = kzalloc(ioc->pend_os_device_add_sz, 5450 GFP_KERNEL); 5451 if (!ioc->pend_os_device_add) 5452 goto out_free_resources; 5453 5454 ioc->device_remove_in_progress_sz = ioc->pend_os_device_add_sz; 5455 ioc->device_remove_in_progress = 5456 kzalloc(ioc->device_remove_in_progress_sz, GFP_KERNEL); 5457 if (!ioc->device_remove_in_progress) 5458 goto out_free_resources; 5459 5460 ioc->fwfault_debug = mpt3sas_fwfault_debug; 5461 5462 /* base internal command bits */ 5463 mutex_init(&ioc->base_cmds.mutex); 5464 ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 5465 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 5466 5467 /* port_enable command bits */ 5468 ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 5469 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED; 5470 5471 /* transport internal command bits */ 5472 ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 5473 ioc->transport_cmds.status = MPT3_CMD_NOT_USED; 5474 mutex_init(&ioc->transport_cmds.mutex); 5475 5476 /* scsih internal command bits */ 5477 ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 5478 ioc->scsih_cmds.status = MPT3_CMD_NOT_USED; 5479 mutex_init(&ioc->scsih_cmds.mutex); 5480 5481 /* task management internal command bits */ 5482 ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 5483 ioc->tm_cmds.status = MPT3_CMD_NOT_USED; 5484 mutex_init(&ioc->tm_cmds.mutex); 5485 5486 /* config page internal command bits */ 5487 ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 5488 ioc->config_cmds.status = MPT3_CMD_NOT_USED; 5489 mutex_init(&ioc->config_cmds.mutex); 5490 5491 /* ctl module internal command bits */ 5492 ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 5493 ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL); 5494 ioc->ctl_cmds.status = MPT3_CMD_NOT_USED; 5495 mutex_init(&ioc->ctl_cmds.mutex); 5496 5497 if (!ioc->base_cmds.reply || !ioc->port_enable_cmds.reply || 5498 !ioc->transport_cmds.reply || !ioc->scsih_cmds.reply || 5499 !ioc->tm_cmds.reply || !ioc->config_cmds.reply || 5500 !ioc->ctl_cmds.reply || !ioc->ctl_cmds.sense) { 5501 r = -ENOMEM; 5502 goto out_free_resources; 5503 } 5504 5505 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 5506 ioc->event_masks[i] = -1; 5507 5508 /* here we enable the events we care about */ 5509 _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY); 5510 _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE); 5511 _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST); 5512 _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE); 5513 _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE); 5514 _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST); 5515 _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME); 5516 _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK); 5517 _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS); 5518 _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED); 5519 _base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD); 5520 if (ioc->hba_mpi_version_belonged == MPI26_VERSION) 5521 _base_unmask_events(ioc, MPI2_EVENT_ACTIVE_CABLE_EXCEPTION); 5522 5523 r = _base_make_ioc_operational(ioc); 5524 if (r) 5525 goto out_free_resources; 5526 5527 ioc->non_operational_loop = 0; 5528 ioc->got_task_abort_from_ioctl = 0; 5529 return 0; 5530 5531 out_free_resources: 5532 5533 ioc->remove_host = 1; 5534 5535 mpt3sas_base_free_resources(ioc); 5536 _base_release_memory_pools(ioc); 5537 pci_set_drvdata(ioc->pdev, NULL); 5538 kfree(ioc->cpu_msix_table); 5539 if (ioc->is_warpdrive) 5540 kfree(ioc->reply_post_host_index); 5541 kfree(ioc->pd_handles); 5542 kfree(ioc->blocking_handles); 5543 kfree(ioc->device_remove_in_progress); 5544 kfree(ioc->pend_os_device_add); 5545 kfree(ioc->tm_cmds.reply); 5546 kfree(ioc->transport_cmds.reply); 5547 kfree(ioc->scsih_cmds.reply); 5548 kfree(ioc->config_cmds.reply); 5549 kfree(ioc->base_cmds.reply); 5550 kfree(ioc->port_enable_cmds.reply); 5551 kfree(ioc->ctl_cmds.reply); 5552 kfree(ioc->ctl_cmds.sense); 5553 kfree(ioc->pfacts); 5554 ioc->ctl_cmds.reply = NULL; 5555 ioc->base_cmds.reply = NULL; 5556 ioc->tm_cmds.reply = NULL; 5557 ioc->scsih_cmds.reply = NULL; 5558 ioc->transport_cmds.reply = NULL; 5559 ioc->config_cmds.reply = NULL; 5560 ioc->pfacts = NULL; 5561 return r; 5562 } 5563 5564 5565 /** 5566 * mpt3sas_base_detach - remove controller instance 5567 * @ioc: per adapter object 5568 * 5569 * Return nothing. 5570 */ 5571 void 5572 mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc) 5573 { 5574 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 5575 __func__)); 5576 5577 mpt3sas_base_stop_watchdog(ioc); 5578 mpt3sas_base_free_resources(ioc); 5579 _base_release_memory_pools(ioc); 5580 pci_set_drvdata(ioc->pdev, NULL); 5581 kfree(ioc->cpu_msix_table); 5582 if (ioc->is_warpdrive) 5583 kfree(ioc->reply_post_host_index); 5584 kfree(ioc->pd_handles); 5585 kfree(ioc->blocking_handles); 5586 kfree(ioc->device_remove_in_progress); 5587 kfree(ioc->pend_os_device_add); 5588 kfree(ioc->pfacts); 5589 kfree(ioc->ctl_cmds.reply); 5590 kfree(ioc->ctl_cmds.sense); 5591 kfree(ioc->base_cmds.reply); 5592 kfree(ioc->port_enable_cmds.reply); 5593 kfree(ioc->tm_cmds.reply); 5594 kfree(ioc->transport_cmds.reply); 5595 kfree(ioc->scsih_cmds.reply); 5596 kfree(ioc->config_cmds.reply); 5597 } 5598 5599 /** 5600 * _base_reset_handler - reset callback handler (for base) 5601 * @ioc: per adapter object 5602 * @reset_phase: phase 5603 * 5604 * The handler for doing any required cleanup or initialization. 5605 * 5606 * The reset phase can be MPT3_IOC_PRE_RESET, MPT3_IOC_AFTER_RESET, 5607 * MPT3_IOC_DONE_RESET 5608 * 5609 * Return nothing. 5610 */ 5611 static void 5612 _base_reset_handler(struct MPT3SAS_ADAPTER *ioc, int reset_phase) 5613 { 5614 mpt3sas_scsih_reset_handler(ioc, reset_phase); 5615 mpt3sas_ctl_reset_handler(ioc, reset_phase); 5616 switch (reset_phase) { 5617 case MPT3_IOC_PRE_RESET: 5618 dtmprintk(ioc, pr_info(MPT3SAS_FMT 5619 "%s: MPT3_IOC_PRE_RESET\n", ioc->name, __func__)); 5620 break; 5621 case MPT3_IOC_AFTER_RESET: 5622 dtmprintk(ioc, pr_info(MPT3SAS_FMT 5623 "%s: MPT3_IOC_AFTER_RESET\n", ioc->name, __func__)); 5624 if (ioc->transport_cmds.status & MPT3_CMD_PENDING) { 5625 ioc->transport_cmds.status |= MPT3_CMD_RESET; 5626 mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid); 5627 complete(&ioc->transport_cmds.done); 5628 } 5629 if (ioc->base_cmds.status & MPT3_CMD_PENDING) { 5630 ioc->base_cmds.status |= MPT3_CMD_RESET; 5631 mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid); 5632 complete(&ioc->base_cmds.done); 5633 } 5634 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { 5635 ioc->port_enable_failed = 1; 5636 ioc->port_enable_cmds.status |= MPT3_CMD_RESET; 5637 mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid); 5638 if (ioc->is_driver_loading) { 5639 ioc->start_scan_failed = 5640 MPI2_IOCSTATUS_INTERNAL_ERROR; 5641 ioc->start_scan = 0; 5642 ioc->port_enable_cmds.status = 5643 MPT3_CMD_NOT_USED; 5644 } else 5645 complete(&ioc->port_enable_cmds.done); 5646 } 5647 if (ioc->config_cmds.status & MPT3_CMD_PENDING) { 5648 ioc->config_cmds.status |= MPT3_CMD_RESET; 5649 mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid); 5650 ioc->config_cmds.smid = USHRT_MAX; 5651 complete(&ioc->config_cmds.done); 5652 } 5653 break; 5654 case MPT3_IOC_DONE_RESET: 5655 dtmprintk(ioc, pr_info(MPT3SAS_FMT 5656 "%s: MPT3_IOC_DONE_RESET\n", ioc->name, __func__)); 5657 break; 5658 } 5659 } 5660 5661 /** 5662 * _wait_for_commands_to_complete - reset controller 5663 * @ioc: Pointer to MPT_ADAPTER structure 5664 * 5665 * This function waiting(3s) for all pending commands to complete 5666 * prior to putting controller in reset. 5667 */ 5668 static void 5669 _wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc) 5670 { 5671 u32 ioc_state; 5672 unsigned long flags; 5673 u16 i; 5674 5675 ioc->pending_io_count = 0; 5676 5677 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 5678 if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) 5679 return; 5680 5681 /* pending command count */ 5682 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 5683 for (i = 0; i < ioc->scsiio_depth; i++) 5684 if (ioc->scsi_lookup[i].cb_idx != 0xFF) 5685 ioc->pending_io_count++; 5686 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 5687 5688 if (!ioc->pending_io_count) 5689 return; 5690 5691 /* wait for pending commands to complete */ 5692 wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ); 5693 } 5694 5695 /** 5696 * mpt3sas_base_hard_reset_handler - reset controller 5697 * @ioc: Pointer to MPT_ADAPTER structure 5698 * @type: FORCE_BIG_HAMMER or SOFT_RESET 5699 * 5700 * Returns 0 for success, non-zero for failure. 5701 */ 5702 int 5703 mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc, 5704 enum reset_type type) 5705 { 5706 int r; 5707 unsigned long flags; 5708 u32 ioc_state; 5709 u8 is_fault = 0, is_trigger = 0; 5710 5711 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: enter\n", ioc->name, 5712 __func__)); 5713 5714 if (ioc->pci_error_recovery) { 5715 pr_err(MPT3SAS_FMT "%s: pci error recovery reset\n", 5716 ioc->name, __func__); 5717 r = 0; 5718 goto out_unlocked; 5719 } 5720 5721 if (mpt3sas_fwfault_debug) 5722 mpt3sas_halt_firmware(ioc); 5723 5724 /* wait for an active reset in progress to complete */ 5725 if (!mutex_trylock(&ioc->reset_in_progress_mutex)) { 5726 do { 5727 ssleep(1); 5728 } while (ioc->shost_recovery == 1); 5729 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name, 5730 __func__)); 5731 return ioc->ioc_reset_in_progress_status; 5732 } 5733 5734 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 5735 ioc->shost_recovery = 1; 5736 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 5737 5738 if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] & 5739 MPT3_DIAG_BUFFER_IS_REGISTERED) && 5740 (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] & 5741 MPT3_DIAG_BUFFER_IS_RELEASED))) { 5742 is_trigger = 1; 5743 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 5744 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) 5745 is_fault = 1; 5746 } 5747 _base_reset_handler(ioc, MPT3_IOC_PRE_RESET); 5748 _wait_for_commands_to_complete(ioc); 5749 _base_mask_interrupts(ioc); 5750 r = _base_make_ioc_ready(ioc, type); 5751 if (r) 5752 goto out; 5753 _base_reset_handler(ioc, MPT3_IOC_AFTER_RESET); 5754 5755 /* If this hard reset is called while port enable is active, then 5756 * there is no reason to call make_ioc_operational 5757 */ 5758 if (ioc->is_driver_loading && ioc->port_enable_failed) { 5759 ioc->remove_host = 1; 5760 r = -EFAULT; 5761 goto out; 5762 } 5763 r = _base_get_ioc_facts(ioc); 5764 if (r) 5765 goto out; 5766 5767 if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable) 5768 panic("%s: Issue occurred with flashing controller firmware." 5769 "Please reboot the system and ensure that the correct" 5770 " firmware version is running\n", ioc->name); 5771 5772 r = _base_make_ioc_operational(ioc); 5773 if (!r) 5774 _base_reset_handler(ioc, MPT3_IOC_DONE_RESET); 5775 5776 out: 5777 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: %s\n", 5778 ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED"))); 5779 5780 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 5781 ioc->ioc_reset_in_progress_status = r; 5782 ioc->shost_recovery = 0; 5783 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 5784 ioc->ioc_reset_count++; 5785 mutex_unlock(&ioc->reset_in_progress_mutex); 5786 5787 out_unlocked: 5788 if ((r == 0) && is_trigger) { 5789 if (is_fault) 5790 mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT); 5791 else 5792 mpt3sas_trigger_master(ioc, 5793 MASTER_TRIGGER_ADAPTER_RESET); 5794 } 5795 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name, 5796 __func__)); 5797 return r; 5798 } 5799