1 /*
2  * This is the Fusion MPT base driver providing common API layer interface
3  * for access to MPT (Message Passing Technology) firmware.
4  *
5  * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c
6  * Copyright (C) 2012-2014  LSI Corporation
7  * Copyright (C) 2013-2014 Avago Technologies
8  *  (mailto: MPT-FusionLinux.pdl@avagotech.com)
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License
12  * as published by the Free Software Foundation; either version 2
13  * of the License, or (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * NO WARRANTY
21  * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
22  * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
23  * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
24  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
25  * solely responsible for determining the appropriateness of using and
26  * distributing the Program and assumes all risks associated with its
27  * exercise of rights under this Agreement, including but not limited to
28  * the risks and costs of program errors, damage to or loss of data,
29  * programs or equipment, and unavailability or interruption of operations.
30 
31  * DISCLAIMER OF LIABILITY
32  * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
33  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34  * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
35  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
36  * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
37  * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
38  * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
39 
40  * You should have received a copy of the GNU General Public License
41  * along with this program; if not, write to the Free Software
42  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301,
43  * USA.
44  */
45 
46 #include <linux/kernel.h>
47 #include <linux/module.h>
48 #include <linux/errno.h>
49 #include <linux/init.h>
50 #include <linux/slab.h>
51 #include <linux/types.h>
52 #include <linux/pci.h>
53 #include <linux/kdev_t.h>
54 #include <linux/blkdev.h>
55 #include <linux/delay.h>
56 #include <linux/interrupt.h>
57 #include <linux/dma-mapping.h>
58 #include <linux/io.h>
59 #include <linux/time.h>
60 #include <linux/kthread.h>
61 #include <linux/aer.h>
62 
63 
64 #include "mpt3sas_base.h"
65 
66 static MPT_CALLBACK	mpt_callbacks[MPT_MAX_CALLBACKS];
67 
68 
69 #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */
70 
71  /* maximum controller queue depth */
72 #define MAX_HBA_QUEUE_DEPTH	30000
73 #define MAX_CHAIN_DEPTH		100000
74 static int max_queue_depth = -1;
75 module_param(max_queue_depth, int, 0);
76 MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
77 
78 static int max_sgl_entries = -1;
79 module_param(max_sgl_entries, int, 0);
80 MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
81 
82 static int msix_disable = -1;
83 module_param(msix_disable, int, 0);
84 MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
85 
86 static int max_msix_vectors = -1;
87 module_param(max_msix_vectors, int, 0);
88 MODULE_PARM_DESC(max_msix_vectors,
89 	" max msix vectors");
90 
91 static int mpt3sas_fwfault_debug;
92 MODULE_PARM_DESC(mpt3sas_fwfault_debug,
93 	" enable detection of firmware fault and halt firmware - (default=0)");
94 
95 static int
96 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc, int sleep_flag);
97 
98 /**
99  * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug.
100  *
101  */
102 static int
103 _scsih_set_fwfault_debug(const char *val, struct kernel_param *kp)
104 {
105 	int ret = param_set_int(val, kp);
106 	struct MPT3SAS_ADAPTER *ioc;
107 
108 	if (ret)
109 		return ret;
110 
111 	pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug);
112 	list_for_each_entry(ioc, &mpt3sas_ioc_list, list)
113 		ioc->fwfault_debug = mpt3sas_fwfault_debug;
114 	return 0;
115 }
116 module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug,
117 	param_get_int, &mpt3sas_fwfault_debug, 0644);
118 
119 /**
120  *  mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc
121  * @arg: input argument, used to derive ioc
122  *
123  * Return 0 if controller is removed from pci subsystem.
124  * Return -1 for other case.
125  */
126 static int mpt3sas_remove_dead_ioc_func(void *arg)
127 {
128 	struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg;
129 	struct pci_dev *pdev;
130 
131 	if ((ioc == NULL))
132 		return -1;
133 
134 	pdev = ioc->pdev;
135 	if ((pdev == NULL))
136 		return -1;
137 	pci_stop_and_remove_bus_device_locked(pdev);
138 	return 0;
139 }
140 
141 /**
142  * _base_fault_reset_work - workq handling ioc fault conditions
143  * @work: input argument, used to derive ioc
144  * Context: sleep.
145  *
146  * Return nothing.
147  */
148 static void
149 _base_fault_reset_work(struct work_struct *work)
150 {
151 	struct MPT3SAS_ADAPTER *ioc =
152 	    container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work);
153 	unsigned long	 flags;
154 	u32 doorbell;
155 	int rc;
156 	struct task_struct *p;
157 
158 
159 	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
160 	if (ioc->shost_recovery)
161 		goto rearm_timer;
162 	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
163 
164 	doorbell = mpt3sas_base_get_iocstate(ioc, 0);
165 	if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) {
166 		pr_err(MPT3SAS_FMT "SAS host is non-operational !!!!\n",
167 		    ioc->name);
168 
169 		/*
170 		 * Call _scsih_flush_pending_cmds callback so that we flush all
171 		 * pending commands back to OS. This call is required to aovid
172 		 * deadlock at block layer. Dead IOC will fail to do diag reset,
173 		 * and this call is safe since dead ioc will never return any
174 		 * command back from HW.
175 		 */
176 		ioc->schedule_dead_ioc_flush_running_cmds(ioc);
177 		/*
178 		 * Set remove_host flag early since kernel thread will
179 		 * take some time to execute.
180 		 */
181 		ioc->remove_host = 1;
182 		/*Remove the Dead Host */
183 		p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc,
184 		    "mpt3sas_dead_ioc_%d", ioc->id);
185 		if (IS_ERR(p))
186 			pr_err(MPT3SAS_FMT
187 			"%s: Running mpt3sas_dead_ioc thread failed !!!!\n",
188 			ioc->name, __func__);
189 		else
190 			pr_err(MPT3SAS_FMT
191 			"%s: Running mpt3sas_dead_ioc thread success !!!!\n",
192 			ioc->name, __func__);
193 		return; /* don't rearm timer */
194 	}
195 
196 	if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) {
197 		rc = mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
198 		    FORCE_BIG_HAMMER);
199 		pr_warn(MPT3SAS_FMT "%s: hard reset: %s\n", ioc->name,
200 		    __func__, (rc == 0) ? "success" : "failed");
201 		doorbell = mpt3sas_base_get_iocstate(ioc, 0);
202 		if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
203 			mpt3sas_base_fault_info(ioc, doorbell &
204 			    MPI2_DOORBELL_DATA_MASK);
205 		if (rc && (doorbell & MPI2_IOC_STATE_MASK) !=
206 		    MPI2_IOC_STATE_OPERATIONAL)
207 			return; /* don't rearm timer */
208 	}
209 
210 	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
211  rearm_timer:
212 	if (ioc->fault_reset_work_q)
213 		queue_delayed_work(ioc->fault_reset_work_q,
214 		    &ioc->fault_reset_work,
215 		    msecs_to_jiffies(FAULT_POLLING_INTERVAL));
216 	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
217 }
218 
219 /**
220  * mpt3sas_base_start_watchdog - start the fault_reset_work_q
221  * @ioc: per adapter object
222  * Context: sleep.
223  *
224  * Return nothing.
225  */
226 void
227 mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc)
228 {
229 	unsigned long	 flags;
230 
231 	if (ioc->fault_reset_work_q)
232 		return;
233 
234 	/* initialize fault polling */
235 
236 	INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
237 	snprintf(ioc->fault_reset_work_q_name,
238 	    sizeof(ioc->fault_reset_work_q_name), "poll_%d_status", ioc->id);
239 	ioc->fault_reset_work_q =
240 		create_singlethread_workqueue(ioc->fault_reset_work_q_name);
241 	if (!ioc->fault_reset_work_q) {
242 		pr_err(MPT3SAS_FMT "%s: failed (line=%d)\n",
243 		    ioc->name, __func__, __LINE__);
244 			return;
245 	}
246 	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
247 	if (ioc->fault_reset_work_q)
248 		queue_delayed_work(ioc->fault_reset_work_q,
249 		    &ioc->fault_reset_work,
250 		    msecs_to_jiffies(FAULT_POLLING_INTERVAL));
251 	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
252 }
253 
254 /**
255  * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q
256  * @ioc: per adapter object
257  * Context: sleep.
258  *
259  * Return nothing.
260  */
261 void
262 mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc)
263 {
264 	unsigned long flags;
265 	struct workqueue_struct *wq;
266 
267 	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
268 	wq = ioc->fault_reset_work_q;
269 	ioc->fault_reset_work_q = NULL;
270 	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
271 	if (wq) {
272 		if (!cancel_delayed_work_sync(&ioc->fault_reset_work))
273 			flush_workqueue(wq);
274 		destroy_workqueue(wq);
275 	}
276 }
277 
278 /**
279  * mpt3sas_base_fault_info - verbose translation of firmware FAULT code
280  * @ioc: per adapter object
281  * @fault_code: fault code
282  *
283  * Return nothing.
284  */
285 void
286 mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code)
287 {
288 	pr_err(MPT3SAS_FMT "fault_state(0x%04x)!\n",
289 	    ioc->name, fault_code);
290 }
291 
292 /**
293  * mpt3sas_halt_firmware - halt's mpt controller firmware
294  * @ioc: per adapter object
295  *
296  * For debugging timeout related issues.  Writing 0xCOFFEE00
297  * to the doorbell register will halt controller firmware. With
298  * the purpose to stop both driver and firmware, the enduser can
299  * obtain a ring buffer from controller UART.
300  */
301 void
302 mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc)
303 {
304 	u32 doorbell;
305 
306 	if (!ioc->fwfault_debug)
307 		return;
308 
309 	dump_stack();
310 
311 	doorbell = readl(&ioc->chip->Doorbell);
312 	if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
313 		mpt3sas_base_fault_info(ioc , doorbell);
314 	else {
315 		writel(0xC0FFEE00, &ioc->chip->Doorbell);
316 		pr_err(MPT3SAS_FMT "Firmware is halted due to command timeout\n",
317 			ioc->name);
318 	}
319 
320 	if (ioc->fwfault_debug == 2)
321 		for (;;)
322 			;
323 	else
324 		panic("panic in %s\n", __func__);
325 }
326 
327 #ifdef CONFIG_SCSI_MPT3SAS_LOGGING
328 /**
329  * _base_sas_ioc_info - verbose translation of the ioc status
330  * @ioc: per adapter object
331  * @mpi_reply: reply mf payload returned from firmware
332  * @request_hdr: request mf
333  *
334  * Return nothing.
335  */
336 static void
337 _base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
338 	MPI2RequestHeader_t *request_hdr)
339 {
340 	u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
341 	    MPI2_IOCSTATUS_MASK;
342 	char *desc = NULL;
343 	u16 frame_sz;
344 	char *func_str = NULL;
345 
346 	/* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */
347 	if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
348 	    request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
349 	    request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
350 		return;
351 
352 	if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE)
353 		return;
354 
355 	switch (ioc_status) {
356 
357 /****************************************************************************
358 *  Common IOCStatus values for all replies
359 ****************************************************************************/
360 
361 	case MPI2_IOCSTATUS_INVALID_FUNCTION:
362 		desc = "invalid function";
363 		break;
364 	case MPI2_IOCSTATUS_BUSY:
365 		desc = "busy";
366 		break;
367 	case MPI2_IOCSTATUS_INVALID_SGL:
368 		desc = "invalid sgl";
369 		break;
370 	case MPI2_IOCSTATUS_INTERNAL_ERROR:
371 		desc = "internal error";
372 		break;
373 	case MPI2_IOCSTATUS_INVALID_VPID:
374 		desc = "invalid vpid";
375 		break;
376 	case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
377 		desc = "insufficient resources";
378 		break;
379 	case MPI2_IOCSTATUS_INVALID_FIELD:
380 		desc = "invalid field";
381 		break;
382 	case MPI2_IOCSTATUS_INVALID_STATE:
383 		desc = "invalid state";
384 		break;
385 	case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
386 		desc = "op state not supported";
387 		break;
388 
389 /****************************************************************************
390 *  Config IOCStatus values
391 ****************************************************************************/
392 
393 	case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
394 		desc = "config invalid action";
395 		break;
396 	case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
397 		desc = "config invalid type";
398 		break;
399 	case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
400 		desc = "config invalid page";
401 		break;
402 	case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
403 		desc = "config invalid data";
404 		break;
405 	case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
406 		desc = "config no defaults";
407 		break;
408 	case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
409 		desc = "config cant commit";
410 		break;
411 
412 /****************************************************************************
413 *  SCSI IO Reply
414 ****************************************************************************/
415 
416 	case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
417 	case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
418 	case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
419 	case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
420 	case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
421 	case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
422 	case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
423 	case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
424 	case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
425 	case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
426 	case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
427 	case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
428 		break;
429 
430 /****************************************************************************
431 *  For use by SCSI Initiator and SCSI Target end-to-end data protection
432 ****************************************************************************/
433 
434 	case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
435 		desc = "eedp guard error";
436 		break;
437 	case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
438 		desc = "eedp ref tag error";
439 		break;
440 	case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
441 		desc = "eedp app tag error";
442 		break;
443 
444 /****************************************************************************
445 *  SCSI Target values
446 ****************************************************************************/
447 
448 	case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
449 		desc = "target invalid io index";
450 		break;
451 	case MPI2_IOCSTATUS_TARGET_ABORTED:
452 		desc = "target aborted";
453 		break;
454 	case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
455 		desc = "target no conn retryable";
456 		break;
457 	case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
458 		desc = "target no connection";
459 		break;
460 	case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
461 		desc = "target xfer count mismatch";
462 		break;
463 	case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
464 		desc = "target data offset error";
465 		break;
466 	case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
467 		desc = "target too much write data";
468 		break;
469 	case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
470 		desc = "target iu too short";
471 		break;
472 	case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
473 		desc = "target ack nak timeout";
474 		break;
475 	case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
476 		desc = "target nak received";
477 		break;
478 
479 /****************************************************************************
480 *  Serial Attached SCSI values
481 ****************************************************************************/
482 
483 	case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
484 		desc = "smp request failed";
485 		break;
486 	case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
487 		desc = "smp data overrun";
488 		break;
489 
490 /****************************************************************************
491 *  Diagnostic Buffer Post / Diagnostic Release values
492 ****************************************************************************/
493 
494 	case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
495 		desc = "diagnostic released";
496 		break;
497 	default:
498 		break;
499 	}
500 
501 	if (!desc)
502 		return;
503 
504 	switch (request_hdr->Function) {
505 	case MPI2_FUNCTION_CONFIG:
506 		frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
507 		func_str = "config_page";
508 		break;
509 	case MPI2_FUNCTION_SCSI_TASK_MGMT:
510 		frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
511 		func_str = "task_mgmt";
512 		break;
513 	case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
514 		frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
515 		func_str = "sas_iounit_ctl";
516 		break;
517 	case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
518 		frame_sz = sizeof(Mpi2SepRequest_t);
519 		func_str = "enclosure";
520 		break;
521 	case MPI2_FUNCTION_IOC_INIT:
522 		frame_sz = sizeof(Mpi2IOCInitRequest_t);
523 		func_str = "ioc_init";
524 		break;
525 	case MPI2_FUNCTION_PORT_ENABLE:
526 		frame_sz = sizeof(Mpi2PortEnableRequest_t);
527 		func_str = "port_enable";
528 		break;
529 	case MPI2_FUNCTION_SMP_PASSTHROUGH:
530 		frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
531 		func_str = "smp_passthru";
532 		break;
533 	default:
534 		frame_sz = 32;
535 		func_str = "unknown";
536 		break;
537 	}
538 
539 	pr_warn(MPT3SAS_FMT "ioc_status: %s(0x%04x), request(0x%p),(%s)\n",
540 		ioc->name, desc, ioc_status, request_hdr, func_str);
541 
542 	_debug_dump_mf(request_hdr, frame_sz/4);
543 }
544 
545 /**
546  * _base_display_event_data - verbose translation of firmware asyn events
547  * @ioc: per adapter object
548  * @mpi_reply: reply mf payload returned from firmware
549  *
550  * Return nothing.
551  */
552 static void
553 _base_display_event_data(struct MPT3SAS_ADAPTER *ioc,
554 	Mpi2EventNotificationReply_t *mpi_reply)
555 {
556 	char *desc = NULL;
557 	u16 event;
558 
559 	if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
560 		return;
561 
562 	event = le16_to_cpu(mpi_reply->Event);
563 
564 	switch (event) {
565 	case MPI2_EVENT_LOG_DATA:
566 		desc = "Log Data";
567 		break;
568 	case MPI2_EVENT_STATE_CHANGE:
569 		desc = "Status Change";
570 		break;
571 	case MPI2_EVENT_HARD_RESET_RECEIVED:
572 		desc = "Hard Reset Received";
573 		break;
574 	case MPI2_EVENT_EVENT_CHANGE:
575 		desc = "Event Change";
576 		break;
577 	case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
578 		desc = "Device Status Change";
579 		break;
580 	case MPI2_EVENT_IR_OPERATION_STATUS:
581 		desc = "IR Operation Status";
582 		break;
583 	case MPI2_EVENT_SAS_DISCOVERY:
584 	{
585 		Mpi2EventDataSasDiscovery_t *event_data =
586 		    (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
587 		pr_info(MPT3SAS_FMT "Discovery: (%s)", ioc->name,
588 		    (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ?
589 		    "start" : "stop");
590 		if (event_data->DiscoveryStatus)
591 			pr_info("discovery_status(0x%08x)",
592 			    le32_to_cpu(event_data->DiscoveryStatus));
593 			pr_info("\n");
594 		return;
595 	}
596 	case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
597 		desc = "SAS Broadcast Primitive";
598 		break;
599 	case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
600 		desc = "SAS Init Device Status Change";
601 		break;
602 	case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
603 		desc = "SAS Init Table Overflow";
604 		break;
605 	case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
606 		desc = "SAS Topology Change List";
607 		break;
608 	case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
609 		desc = "SAS Enclosure Device Status Change";
610 		break;
611 	case MPI2_EVENT_IR_VOLUME:
612 		desc = "IR Volume";
613 		break;
614 	case MPI2_EVENT_IR_PHYSICAL_DISK:
615 		desc = "IR Physical Disk";
616 		break;
617 	case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
618 		desc = "IR Configuration Change List";
619 		break;
620 	case MPI2_EVENT_LOG_ENTRY_ADDED:
621 		desc = "Log Entry Added";
622 		break;
623 	case MPI2_EVENT_TEMP_THRESHOLD:
624 		desc = "Temperature Threshold";
625 		break;
626 	}
627 
628 	if (!desc)
629 		return;
630 
631 	pr_info(MPT3SAS_FMT "%s\n", ioc->name, desc);
632 }
633 #endif
634 
635 /**
636  * _base_sas_log_info - verbose translation of firmware log info
637  * @ioc: per adapter object
638  * @log_info: log info
639  *
640  * Return nothing.
641  */
642 static void
643 _base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info)
644 {
645 	union loginfo_type {
646 		u32	loginfo;
647 		struct {
648 			u32	subcode:16;
649 			u32	code:8;
650 			u32	originator:4;
651 			u32	bus_type:4;
652 		} dw;
653 	};
654 	union loginfo_type sas_loginfo;
655 	char *originator_str = NULL;
656 
657 	sas_loginfo.loginfo = log_info;
658 	if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
659 		return;
660 
661 	/* each nexus loss loginfo */
662 	if (log_info == 0x31170000)
663 		return;
664 
665 	/* eat the loginfos associated with task aborts */
666 	if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info ==
667 	    0x31140000 || log_info == 0x31130000))
668 		return;
669 
670 	switch (sas_loginfo.dw.originator) {
671 	case 0:
672 		originator_str = "IOP";
673 		break;
674 	case 1:
675 		originator_str = "PL";
676 		break;
677 	case 2:
678 		originator_str = "IR";
679 		break;
680 	}
681 
682 	pr_warn(MPT3SAS_FMT
683 		"log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n",
684 		ioc->name, log_info,
685 	     originator_str, sas_loginfo.dw.code,
686 	     sas_loginfo.dw.subcode);
687 }
688 
689 /**
690  * _base_display_reply_info -
691  * @ioc: per adapter object
692  * @smid: system request message index
693  * @msix_index: MSIX table index supplied by the OS
694  * @reply: reply message frame(lower 32bit addr)
695  *
696  * Return nothing.
697  */
698 static void
699 _base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
700 	u32 reply)
701 {
702 	MPI2DefaultReply_t *mpi_reply;
703 	u16 ioc_status;
704 	u32 loginfo = 0;
705 
706 	mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
707 	if (unlikely(!mpi_reply)) {
708 		pr_err(MPT3SAS_FMT "mpi_reply not valid at %s:%d/%s()!\n",
709 		    ioc->name, __FILE__, __LINE__, __func__);
710 		return;
711 	}
712 	ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
713 #ifdef CONFIG_SCSI_MPT3SAS_LOGGING
714 	if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
715 	    (ioc->logging_level & MPT_DEBUG_REPLY)) {
716 		_base_sas_ioc_info(ioc , mpi_reply,
717 		   mpt3sas_base_get_msg_frame(ioc, smid));
718 	}
719 #endif
720 	if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
721 		loginfo = le32_to_cpu(mpi_reply->IOCLogInfo);
722 		_base_sas_log_info(ioc, loginfo);
723 	}
724 
725 	if (ioc_status || loginfo) {
726 		ioc_status &= MPI2_IOCSTATUS_MASK;
727 		mpt3sas_trigger_mpi(ioc, ioc_status, loginfo);
728 	}
729 }
730 
731 /**
732  * mpt3sas_base_done - base internal command completion routine
733  * @ioc: per adapter object
734  * @smid: system request message index
735  * @msix_index: MSIX table index supplied by the OS
736  * @reply: reply message frame(lower 32bit addr)
737  *
738  * Return 1 meaning mf should be freed from _base_interrupt
739  *        0 means the mf is freed from this function.
740  */
741 u8
742 mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
743 	u32 reply)
744 {
745 	MPI2DefaultReply_t *mpi_reply;
746 
747 	mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
748 	if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
749 		return 1;
750 
751 	if (ioc->base_cmds.status == MPT3_CMD_NOT_USED)
752 		return 1;
753 
754 	ioc->base_cmds.status |= MPT3_CMD_COMPLETE;
755 	if (mpi_reply) {
756 		ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID;
757 		memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
758 	}
759 	ioc->base_cmds.status &= ~MPT3_CMD_PENDING;
760 
761 	complete(&ioc->base_cmds.done);
762 	return 1;
763 }
764 
765 /**
766  * _base_async_event - main callback handler for firmware asyn events
767  * @ioc: per adapter object
768  * @msix_index: MSIX table index supplied by the OS
769  * @reply: reply message frame(lower 32bit addr)
770  *
771  * Return 1 meaning mf should be freed from _base_interrupt
772  *        0 means the mf is freed from this function.
773  */
774 static u8
775 _base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
776 {
777 	Mpi2EventNotificationReply_t *mpi_reply;
778 	Mpi2EventAckRequest_t *ack_request;
779 	u16 smid;
780 
781 	mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
782 	if (!mpi_reply)
783 		return 1;
784 	if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
785 		return 1;
786 #ifdef CONFIG_SCSI_MPT3SAS_LOGGING
787 	_base_display_event_data(ioc, mpi_reply);
788 #endif
789 	if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
790 		goto out;
791 	smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
792 	if (!smid) {
793 		pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
794 		    ioc->name, __func__);
795 		goto out;
796 	}
797 
798 	ack_request = mpt3sas_base_get_msg_frame(ioc, smid);
799 	memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
800 	ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
801 	ack_request->Event = mpi_reply->Event;
802 	ack_request->EventContext = mpi_reply->EventContext;
803 	ack_request->VF_ID = 0;  /* TODO */
804 	ack_request->VP_ID = 0;
805 	mpt3sas_base_put_smid_default(ioc, smid);
806 
807  out:
808 
809 	/* scsih callback handler */
810 	mpt3sas_scsih_event_callback(ioc, msix_index, reply);
811 
812 	/* ctl callback handler */
813 	mpt3sas_ctl_event_callback(ioc, msix_index, reply);
814 
815 	return 1;
816 }
817 
818 /**
819  * _base_get_cb_idx - obtain the callback index
820  * @ioc: per adapter object
821  * @smid: system request message index
822  *
823  * Return callback index.
824  */
825 static u8
826 _base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid)
827 {
828 	int i;
829 	u8 cb_idx;
830 
831 	if (smid < ioc->hi_priority_smid) {
832 		i = smid - 1;
833 		cb_idx = ioc->scsi_lookup[i].cb_idx;
834 	} else if (smid < ioc->internal_smid) {
835 		i = smid - ioc->hi_priority_smid;
836 		cb_idx = ioc->hpr_lookup[i].cb_idx;
837 	} else if (smid <= ioc->hba_queue_depth) {
838 		i = smid - ioc->internal_smid;
839 		cb_idx = ioc->internal_lookup[i].cb_idx;
840 	} else
841 		cb_idx = 0xFF;
842 	return cb_idx;
843 }
844 
845 /**
846  * _base_mask_interrupts - disable interrupts
847  * @ioc: per adapter object
848  *
849  * Disabling ResetIRQ, Reply and Doorbell Interrupts
850  *
851  * Return nothing.
852  */
853 static void
854 _base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc)
855 {
856 	u32 him_register;
857 
858 	ioc->mask_interrupts = 1;
859 	him_register = readl(&ioc->chip->HostInterruptMask);
860 	him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
861 	writel(him_register, &ioc->chip->HostInterruptMask);
862 	readl(&ioc->chip->HostInterruptMask);
863 }
864 
865 /**
866  * _base_unmask_interrupts - enable interrupts
867  * @ioc: per adapter object
868  *
869  * Enabling only Reply Interrupts
870  *
871  * Return nothing.
872  */
873 static void
874 _base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc)
875 {
876 	u32 him_register;
877 
878 	him_register = readl(&ioc->chip->HostInterruptMask);
879 	him_register &= ~MPI2_HIM_RIM;
880 	writel(him_register, &ioc->chip->HostInterruptMask);
881 	ioc->mask_interrupts = 0;
882 }
883 
884 union reply_descriptor {
885 	u64 word;
886 	struct {
887 		u32 low;
888 		u32 high;
889 	} u;
890 };
891 
892 /**
893  * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
894  * @irq: irq number (not used)
895  * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
896  * @r: pt_regs pointer (not used)
897  *
898  * Return IRQ_HANDLE if processed, else IRQ_NONE.
899  */
900 static irqreturn_t
901 _base_interrupt(int irq, void *bus_id)
902 {
903 	struct adapter_reply_queue *reply_q = bus_id;
904 	union reply_descriptor rd;
905 	u32 completed_cmds;
906 	u8 request_desript_type;
907 	u16 smid;
908 	u8 cb_idx;
909 	u32 reply;
910 	u8 msix_index = reply_q->msix_index;
911 	struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
912 	Mpi2ReplyDescriptorsUnion_t *rpf;
913 	u8 rc;
914 
915 	if (ioc->mask_interrupts)
916 		return IRQ_NONE;
917 
918 	if (!atomic_add_unless(&reply_q->busy, 1, 1))
919 		return IRQ_NONE;
920 
921 	rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index];
922 	request_desript_type = rpf->Default.ReplyFlags
923 	     & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
924 	if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) {
925 		atomic_dec(&reply_q->busy);
926 		return IRQ_NONE;
927 	}
928 
929 	completed_cmds = 0;
930 	cb_idx = 0xFF;
931 	do {
932 		rd.word = le64_to_cpu(rpf->Words);
933 		if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
934 			goto out;
935 		reply = 0;
936 		smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
937 		if (request_desript_type ==
938 		    MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS ||
939 		    request_desript_type ==
940 		    MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) {
941 			cb_idx = _base_get_cb_idx(ioc, smid);
942 			if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
943 			    (likely(mpt_callbacks[cb_idx] != NULL))) {
944 				rc = mpt_callbacks[cb_idx](ioc, smid,
945 				    msix_index, 0);
946 				if (rc)
947 					mpt3sas_base_free_smid(ioc, smid);
948 			}
949 		} else if (request_desript_type ==
950 		    MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
951 			reply = le32_to_cpu(
952 			    rpf->AddressReply.ReplyFrameAddress);
953 			if (reply > ioc->reply_dma_max_address ||
954 			    reply < ioc->reply_dma_min_address)
955 				reply = 0;
956 			if (smid) {
957 				cb_idx = _base_get_cb_idx(ioc, smid);
958 				if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
959 				    (likely(mpt_callbacks[cb_idx] != NULL))) {
960 					rc = mpt_callbacks[cb_idx](ioc, smid,
961 					    msix_index, reply);
962 					if (reply)
963 						_base_display_reply_info(ioc,
964 						    smid, msix_index, reply);
965 					if (rc)
966 						mpt3sas_base_free_smid(ioc,
967 						    smid);
968 				}
969 			} else {
970 				_base_async_event(ioc, msix_index, reply);
971 			}
972 
973 			/* reply free queue handling */
974 			if (reply) {
975 				ioc->reply_free_host_index =
976 				    (ioc->reply_free_host_index ==
977 				    (ioc->reply_free_queue_depth - 1)) ?
978 				    0 : ioc->reply_free_host_index + 1;
979 				ioc->reply_free[ioc->reply_free_host_index] =
980 				    cpu_to_le32(reply);
981 				wmb();
982 				writel(ioc->reply_free_host_index,
983 				    &ioc->chip->ReplyFreeHostIndex);
984 			}
985 		}
986 
987 		rpf->Words = cpu_to_le64(ULLONG_MAX);
988 		reply_q->reply_post_host_index =
989 		    (reply_q->reply_post_host_index ==
990 		    (ioc->reply_post_queue_depth - 1)) ? 0 :
991 		    reply_q->reply_post_host_index + 1;
992 		request_desript_type =
993 		    reply_q->reply_post_free[reply_q->reply_post_host_index].
994 		    Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
995 		completed_cmds++;
996 		if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
997 			goto out;
998 		if (!reply_q->reply_post_host_index)
999 			rpf = reply_q->reply_post_free;
1000 		else
1001 			rpf++;
1002 	} while (1);
1003 
1004  out:
1005 
1006 	if (!completed_cmds) {
1007 		atomic_dec(&reply_q->busy);
1008 		return IRQ_NONE;
1009 	}
1010 
1011 	wmb();
1012 
1013 	/* Update Reply Post Host Index.
1014 	 * For those HBA's which support combined reply queue feature
1015 	 * 1. Get the correct Supplemental Reply Post Host Index Register.
1016 	 *    i.e. (msix_index / 8)th entry from Supplemental Reply Post Host
1017 	 *    Index Register address bank i.e replyPostRegisterIndex[],
1018 	 * 2. Then update this register with new reply host index value
1019 	 *    in ReplyPostIndex field and the MSIxIndex field with
1020 	 *    msix_index value reduced to a value between 0 and 7,
1021 	 *    using a modulo 8 operation. Since each Supplemental Reply Post
1022 	 *    Host Index Register supports 8 MSI-X vectors.
1023 	 *
1024 	 * For other HBA's just update the Reply Post Host Index register with
1025 	 * new reply host index value in ReplyPostIndex Field and msix_index
1026 	 * value in MSIxIndex field.
1027 	 */
1028 	if (ioc->msix96_vector)
1029 		writel(reply_q->reply_post_host_index | ((msix_index  & 7) <<
1030 			MPI2_RPHI_MSIX_INDEX_SHIFT),
1031 			ioc->replyPostRegisterIndex[msix_index/8]);
1032 	else
1033 		writel(reply_q->reply_post_host_index | (msix_index <<
1034 			MPI2_RPHI_MSIX_INDEX_SHIFT),
1035 			&ioc->chip->ReplyPostHostIndex);
1036 	atomic_dec(&reply_q->busy);
1037 	return IRQ_HANDLED;
1038 }
1039 
1040 /**
1041  * _base_is_controller_msix_enabled - is controller support muli-reply queues
1042  * @ioc: per adapter object
1043  *
1044  */
1045 static inline int
1046 _base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc)
1047 {
1048 	return (ioc->facts.IOCCapabilities &
1049 	    MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable;
1050 }
1051 
1052 /**
1053  * mpt3sas_base_flush_reply_queues - flushing the MSIX reply queues
1054  * @ioc: per adapter object
1055  * Context: ISR conext
1056  *
1057  * Called when a Task Management request has completed. We want
1058  * to flush the other reply queues so all the outstanding IO has been
1059  * completed back to OS before we process the TM completetion.
1060  *
1061  * Return nothing.
1062  */
1063 void
1064 mpt3sas_base_flush_reply_queues(struct MPT3SAS_ADAPTER *ioc)
1065 {
1066 	struct adapter_reply_queue *reply_q;
1067 
1068 	/* If MSIX capability is turned off
1069 	 * then multi-queues are not enabled
1070 	 */
1071 	if (!_base_is_controller_msix_enabled(ioc))
1072 		return;
1073 
1074 	list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1075 		if (ioc->shost_recovery)
1076 			return;
1077 		/* TMs are on msix_index == 0 */
1078 		if (reply_q->msix_index == 0)
1079 			continue;
1080 		_base_interrupt(reply_q->vector, (void *)reply_q);
1081 	}
1082 }
1083 
1084 /**
1085  * mpt3sas_base_release_callback_handler - clear interrupt callback handler
1086  * @cb_idx: callback index
1087  *
1088  * Return nothing.
1089  */
1090 void
1091 mpt3sas_base_release_callback_handler(u8 cb_idx)
1092 {
1093 	mpt_callbacks[cb_idx] = NULL;
1094 }
1095 
1096 /**
1097  * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler
1098  * @cb_func: callback function
1099  *
1100  * Returns cb_func.
1101  */
1102 u8
1103 mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func)
1104 {
1105 	u8 cb_idx;
1106 
1107 	for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
1108 		if (mpt_callbacks[cb_idx] == NULL)
1109 			break;
1110 
1111 	mpt_callbacks[cb_idx] = cb_func;
1112 	return cb_idx;
1113 }
1114 
1115 /**
1116  * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler
1117  *
1118  * Return nothing.
1119  */
1120 void
1121 mpt3sas_base_initialize_callback_handler(void)
1122 {
1123 	u8 cb_idx;
1124 
1125 	for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
1126 		mpt3sas_base_release_callback_handler(cb_idx);
1127 }
1128 
1129 
1130 /**
1131  * _base_build_zero_len_sge - build zero length sg entry
1132  * @ioc: per adapter object
1133  * @paddr: virtual address for SGE
1134  *
1135  * Create a zero length scatter gather entry to insure the IOCs hardware has
1136  * something to use if the target device goes brain dead and tries
1137  * to send data even when none is asked for.
1138  *
1139  * Return nothing.
1140  */
1141 static void
1142 _base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1143 {
1144 	u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
1145 	    MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
1146 	    MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
1147 	    MPI2_SGE_FLAGS_SHIFT);
1148 	ioc->base_add_sg_single(paddr, flags_length, -1);
1149 }
1150 
1151 /**
1152  * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr.
1153  * @paddr: virtual address for SGE
1154  * @flags_length: SGE flags and data transfer length
1155  * @dma_addr: Physical address
1156  *
1157  * Return nothing.
1158  */
1159 static void
1160 _base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1161 {
1162 	Mpi2SGESimple32_t *sgel = paddr;
1163 
1164 	flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
1165 	    MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1166 	sgel->FlagsLength = cpu_to_le32(flags_length);
1167 	sgel->Address = cpu_to_le32(dma_addr);
1168 }
1169 
1170 
1171 /**
1172  * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr.
1173  * @paddr: virtual address for SGE
1174  * @flags_length: SGE flags and data transfer length
1175  * @dma_addr: Physical address
1176  *
1177  * Return nothing.
1178  */
1179 static void
1180 _base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1181 {
1182 	Mpi2SGESimple64_t *sgel = paddr;
1183 
1184 	flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
1185 	    MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1186 	sgel->FlagsLength = cpu_to_le32(flags_length);
1187 	sgel->Address = cpu_to_le64(dma_addr);
1188 }
1189 
1190 /**
1191  * _base_get_chain_buffer_tracker - obtain chain tracker
1192  * @ioc: per adapter object
1193  * @smid: smid associated to an IO request
1194  *
1195  * Returns chain tracker(from ioc->free_chain_list)
1196  */
1197 static struct chain_tracker *
1198 _base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1199 {
1200 	struct chain_tracker *chain_req;
1201 	unsigned long flags;
1202 
1203 	spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
1204 	if (list_empty(&ioc->free_chain_list)) {
1205 		spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1206 		dfailprintk(ioc, pr_warn(MPT3SAS_FMT
1207 			"chain buffers not available\n", ioc->name));
1208 		return NULL;
1209 	}
1210 	chain_req = list_entry(ioc->free_chain_list.next,
1211 	    struct chain_tracker, tracker_list);
1212 	list_del_init(&chain_req->tracker_list);
1213 	list_add_tail(&chain_req->tracker_list,
1214 	    &ioc->scsi_lookup[smid - 1].chain_list);
1215 	spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1216 	return chain_req;
1217 }
1218 
1219 
1220 /**
1221  * _base_build_sg - build generic sg
1222  * @ioc: per adapter object
1223  * @psge: virtual address for SGE
1224  * @data_out_dma: physical address for WRITES
1225  * @data_out_sz: data xfer size for WRITES
1226  * @data_in_dma: physical address for READS
1227  * @data_in_sz: data xfer size for READS
1228  *
1229  * Return nothing.
1230  */
1231 static void
1232 _base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge,
1233 	dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1234 	size_t data_in_sz)
1235 {
1236 	u32 sgl_flags;
1237 
1238 	if (!data_out_sz && !data_in_sz) {
1239 		_base_build_zero_len_sge(ioc, psge);
1240 		return;
1241 	}
1242 
1243 	if (data_out_sz && data_in_sz) {
1244 		/* WRITE sgel first */
1245 		sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1246 		    MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC);
1247 		sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1248 		ioc->base_add_sg_single(psge, sgl_flags |
1249 		    data_out_sz, data_out_dma);
1250 
1251 		/* incr sgel */
1252 		psge += ioc->sge_size;
1253 
1254 		/* READ sgel last */
1255 		sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1256 		    MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1257 		    MPI2_SGE_FLAGS_END_OF_LIST);
1258 		sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1259 		ioc->base_add_sg_single(psge, sgl_flags |
1260 		    data_in_sz, data_in_dma);
1261 	} else if (data_out_sz) /* WRITE */ {
1262 		sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1263 		    MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1264 		    MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC);
1265 		sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1266 		ioc->base_add_sg_single(psge, sgl_flags |
1267 		    data_out_sz, data_out_dma);
1268 	} else if (data_in_sz) /* READ */ {
1269 		sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1270 		    MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1271 		    MPI2_SGE_FLAGS_END_OF_LIST);
1272 		sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1273 		ioc->base_add_sg_single(psge, sgl_flags |
1274 		    data_in_sz, data_in_dma);
1275 	}
1276 }
1277 
1278 /* IEEE format sgls */
1279 
1280 /**
1281  * _base_add_sg_single_ieee - add sg element for IEEE format
1282  * @paddr: virtual address for SGE
1283  * @flags: SGE flags
1284  * @chain_offset: number of 128 byte elements from start of segment
1285  * @length: data transfer length
1286  * @dma_addr: Physical address
1287  *
1288  * Return nothing.
1289  */
1290 static void
1291 _base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length,
1292 	dma_addr_t dma_addr)
1293 {
1294 	Mpi25IeeeSgeChain64_t *sgel = paddr;
1295 
1296 	sgel->Flags = flags;
1297 	sgel->NextChainOffset = chain_offset;
1298 	sgel->Length = cpu_to_le32(length);
1299 	sgel->Address = cpu_to_le64(dma_addr);
1300 }
1301 
1302 /**
1303  * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format
1304  * @ioc: per adapter object
1305  * @paddr: virtual address for SGE
1306  *
1307  * Create a zero length scatter gather entry to insure the IOCs hardware has
1308  * something to use if the target device goes brain dead and tries
1309  * to send data even when none is asked for.
1310  *
1311  * Return nothing.
1312  */
1313 static void
1314 _base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1315 {
1316 	u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1317 		MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
1318 		MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
1319 	_base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1);
1320 }
1321 
1322 /**
1323  * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format
1324  * @ioc: per adapter object
1325  * @scmd: scsi command
1326  * @smid: system request message index
1327  * Context: none.
1328  *
1329  * The main routine that builds scatter gather table from a given
1330  * scsi request sent via the .queuecommand main handler.
1331  *
1332  * Returns 0 success, anything else error
1333  */
1334 static int
1335 _base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc,
1336 	struct scsi_cmnd *scmd, u16 smid)
1337 {
1338 	Mpi2SCSIIORequest_t *mpi_request;
1339 	dma_addr_t chain_dma;
1340 	struct scatterlist *sg_scmd;
1341 	void *sg_local, *chain;
1342 	u32 chain_offset;
1343 	u32 chain_length;
1344 	int sges_left;
1345 	u32 sges_in_segment;
1346 	u8 simple_sgl_flags;
1347 	u8 simple_sgl_flags_last;
1348 	u8 chain_sgl_flags;
1349 	struct chain_tracker *chain_req;
1350 
1351 	mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
1352 
1353 	/* init scatter gather flags */
1354 	simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1355 	    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1356 	simple_sgl_flags_last = simple_sgl_flags |
1357 	    MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
1358 	chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
1359 	    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1360 
1361 	sg_scmd = scsi_sglist(scmd);
1362 	sges_left = scsi_dma_map(scmd);
1363 	if (sges_left < 0) {
1364 		sdev_printk(KERN_ERR, scmd->device,
1365 			"pci_map_sg failed: request for %d bytes!\n",
1366 			scsi_bufflen(scmd));
1367 		return -ENOMEM;
1368 	}
1369 
1370 	sg_local = &mpi_request->SGL;
1371 	sges_in_segment = (ioc->request_sz -
1372 	    offsetof(Mpi2SCSIIORequest_t, SGL))/ioc->sge_size_ieee;
1373 	if (sges_left <= sges_in_segment)
1374 		goto fill_in_last_segment;
1375 
1376 	mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) +
1377 	    (offsetof(Mpi2SCSIIORequest_t, SGL)/ioc->sge_size_ieee);
1378 
1379 	/* fill in main message segment when there is a chain following */
1380 	while (sges_in_segment > 1) {
1381 		_base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1382 		    sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1383 		sg_scmd = sg_next(sg_scmd);
1384 		sg_local += ioc->sge_size_ieee;
1385 		sges_left--;
1386 		sges_in_segment--;
1387 	}
1388 
1389 	/* initializing the pointers */
1390 	chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1391 	if (!chain_req)
1392 		return -1;
1393 	chain = chain_req->chain_buffer;
1394 	chain_dma = chain_req->chain_buffer_dma;
1395 	do {
1396 		sges_in_segment = (sges_left <=
1397 		    ioc->max_sges_in_chain_message) ? sges_left :
1398 		    ioc->max_sges_in_chain_message;
1399 		chain_offset = (sges_left == sges_in_segment) ?
1400 		    0 : sges_in_segment;
1401 		chain_length = sges_in_segment * ioc->sge_size_ieee;
1402 		if (chain_offset)
1403 			chain_length += ioc->sge_size_ieee;
1404 		_base_add_sg_single_ieee(sg_local, chain_sgl_flags,
1405 		    chain_offset, chain_length, chain_dma);
1406 
1407 		sg_local = chain;
1408 		if (!chain_offset)
1409 			goto fill_in_last_segment;
1410 
1411 		/* fill in chain segments */
1412 		while (sges_in_segment) {
1413 			_base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1414 			    sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1415 			sg_scmd = sg_next(sg_scmd);
1416 			sg_local += ioc->sge_size_ieee;
1417 			sges_left--;
1418 			sges_in_segment--;
1419 		}
1420 
1421 		chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1422 		if (!chain_req)
1423 			return -1;
1424 		chain = chain_req->chain_buffer;
1425 		chain_dma = chain_req->chain_buffer_dma;
1426 	} while (1);
1427 
1428 
1429  fill_in_last_segment:
1430 
1431 	/* fill the last segment */
1432 	while (sges_left > 0) {
1433 		if (sges_left == 1)
1434 			_base_add_sg_single_ieee(sg_local,
1435 			    simple_sgl_flags_last, 0, sg_dma_len(sg_scmd),
1436 			    sg_dma_address(sg_scmd));
1437 		else
1438 			_base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1439 			    sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1440 		sg_scmd = sg_next(sg_scmd);
1441 		sg_local += ioc->sge_size_ieee;
1442 		sges_left--;
1443 	}
1444 
1445 	return 0;
1446 }
1447 
1448 /**
1449  * _base_build_sg_ieee - build generic sg for IEEE format
1450  * @ioc: per adapter object
1451  * @psge: virtual address for SGE
1452  * @data_out_dma: physical address for WRITES
1453  * @data_out_sz: data xfer size for WRITES
1454  * @data_in_dma: physical address for READS
1455  * @data_in_sz: data xfer size for READS
1456  *
1457  * Return nothing.
1458  */
1459 static void
1460 _base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge,
1461 	dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1462 	size_t data_in_sz)
1463 {
1464 	u8 sgl_flags;
1465 
1466 	if (!data_out_sz && !data_in_sz) {
1467 		_base_build_zero_len_sge_ieee(ioc, psge);
1468 		return;
1469 	}
1470 
1471 	if (data_out_sz && data_in_sz) {
1472 		/* WRITE sgel first */
1473 		sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1474 		    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1475 		_base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
1476 		    data_out_dma);
1477 
1478 		/* incr sgel */
1479 		psge += ioc->sge_size_ieee;
1480 
1481 		/* READ sgel last */
1482 		sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
1483 		_base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
1484 		    data_in_dma);
1485 	} else if (data_out_sz) /* WRITE */ {
1486 		sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1487 		    MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
1488 		    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1489 		_base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
1490 		    data_out_dma);
1491 	} else if (data_in_sz) /* READ */ {
1492 		sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1493 		    MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
1494 		    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1495 		_base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
1496 		    data_in_dma);
1497 	}
1498 }
1499 
1500 #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
1501 
1502 /**
1503  * _base_config_dma_addressing - set dma addressing
1504  * @ioc: per adapter object
1505  * @pdev: PCI device struct
1506  *
1507  * Returns 0 for success, non-zero for failure.
1508  */
1509 static int
1510 _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
1511 {
1512 	struct sysinfo s;
1513 	u64 consistent_dma_mask;
1514 
1515 	if (ioc->dma_mask)
1516 		consistent_dma_mask = DMA_BIT_MASK(64);
1517 	else
1518 		consistent_dma_mask = DMA_BIT_MASK(32);
1519 
1520 	if (sizeof(dma_addr_t) > 4) {
1521 		const uint64_t required_mask =
1522 		    dma_get_required_mask(&pdev->dev);
1523 		if ((required_mask > DMA_BIT_MASK(32)) &&
1524 		    !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
1525 		    !pci_set_consistent_dma_mask(pdev, consistent_dma_mask)) {
1526 			ioc->base_add_sg_single = &_base_add_sg_single_64;
1527 			ioc->sge_size = sizeof(Mpi2SGESimple64_t);
1528 			ioc->dma_mask = 64;
1529 			goto out;
1530 		}
1531 	}
1532 
1533 	if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
1534 	    && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1535 		ioc->base_add_sg_single = &_base_add_sg_single_32;
1536 		ioc->sge_size = sizeof(Mpi2SGESimple32_t);
1537 		ioc->dma_mask = 32;
1538 	} else
1539 		return -ENODEV;
1540 
1541  out:
1542 	si_meminfo(&s);
1543 	pr_info(MPT3SAS_FMT
1544 		"%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
1545 		ioc->name, ioc->dma_mask, convert_to_kb(s.totalram));
1546 
1547 	return 0;
1548 }
1549 
1550 static int
1551 _base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc,
1552 				      struct pci_dev *pdev)
1553 {
1554 	if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
1555 		if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
1556 			return -ENODEV;
1557 	}
1558 	return 0;
1559 }
1560 
1561 /**
1562  * _base_check_enable_msix - checks MSIX capabable.
1563  * @ioc: per adapter object
1564  *
1565  * Check to see if card is capable of MSIX, and set number
1566  * of available msix vectors
1567  */
1568 static int
1569 _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)
1570 {
1571 	int base;
1572 	u16 message_control;
1573 
1574 	base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
1575 	if (!base) {
1576 		dfailprintk(ioc, pr_info(MPT3SAS_FMT "msix not supported\n",
1577 			ioc->name));
1578 		return -EINVAL;
1579 	}
1580 
1581 	/* get msix vector count */
1582 
1583 	pci_read_config_word(ioc->pdev, base + 2, &message_control);
1584 	ioc->msix_vector_count = (message_control & 0x3FF) + 1;
1585 	dinitprintk(ioc, pr_info(MPT3SAS_FMT
1586 		"msix is supported, vector_count(%d)\n",
1587 		ioc->name, ioc->msix_vector_count));
1588 	return 0;
1589 }
1590 
1591 /**
1592  * _base_free_irq - free irq
1593  * @ioc: per adapter object
1594  *
1595  * Freeing respective reply_queue from the list.
1596  */
1597 static void
1598 _base_free_irq(struct MPT3SAS_ADAPTER *ioc)
1599 {
1600 	struct adapter_reply_queue *reply_q, *next;
1601 
1602 	if (list_empty(&ioc->reply_queue_list))
1603 		return;
1604 
1605 	list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
1606 		list_del(&reply_q->list);
1607 		irq_set_affinity_hint(reply_q->vector, NULL);
1608 		free_cpumask_var(reply_q->affinity_hint);
1609 		synchronize_irq(reply_q->vector);
1610 		free_irq(reply_q->vector, reply_q);
1611 		kfree(reply_q);
1612 	}
1613 }
1614 
1615 /**
1616  * _base_request_irq - request irq
1617  * @ioc: per adapter object
1618  * @index: msix index into vector table
1619  * @vector: irq vector
1620  *
1621  * Inserting respective reply_queue into the list.
1622  */
1623 static int
1624 _base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index, u32 vector)
1625 {
1626 	struct adapter_reply_queue *reply_q;
1627 	int r;
1628 
1629 	reply_q =  kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL);
1630 	if (!reply_q) {
1631 		pr_err(MPT3SAS_FMT "unable to allocate memory %d!\n",
1632 		    ioc->name, (int)sizeof(struct adapter_reply_queue));
1633 		return -ENOMEM;
1634 	}
1635 	reply_q->ioc = ioc;
1636 	reply_q->msix_index = index;
1637 	reply_q->vector = vector;
1638 
1639 	if (!alloc_cpumask_var(&reply_q->affinity_hint, GFP_KERNEL))
1640 		return -ENOMEM;
1641 	cpumask_clear(reply_q->affinity_hint);
1642 
1643 	atomic_set(&reply_q->busy, 0);
1644 	if (ioc->msix_enable)
1645 		snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d",
1646 		    MPT3SAS_DRIVER_NAME, ioc->id, index);
1647 	else
1648 		snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d",
1649 		    MPT3SAS_DRIVER_NAME, ioc->id);
1650 	r = request_irq(vector, _base_interrupt, IRQF_SHARED, reply_q->name,
1651 	    reply_q);
1652 	if (r) {
1653 		pr_err(MPT3SAS_FMT "unable to allocate interrupt %d!\n",
1654 		    reply_q->name, vector);
1655 		kfree(reply_q);
1656 		return -EBUSY;
1657 	}
1658 
1659 	INIT_LIST_HEAD(&reply_q->list);
1660 	list_add_tail(&reply_q->list, &ioc->reply_queue_list);
1661 	return 0;
1662 }
1663 
1664 /**
1665  * _base_assign_reply_queues - assigning msix index for each cpu
1666  * @ioc: per adapter object
1667  *
1668  * The enduser would need to set the affinity via /proc/irq/#/smp_affinity
1669  *
1670  * It would nice if we could call irq_set_affinity, however it is not
1671  * an exported symbol
1672  */
1673 static void
1674 _base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc)
1675 {
1676 	unsigned int cpu, nr_cpus, nr_msix, index = 0;
1677 	struct adapter_reply_queue *reply_q;
1678 
1679 	if (!_base_is_controller_msix_enabled(ioc))
1680 		return;
1681 
1682 	memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz);
1683 
1684 	nr_cpus = num_online_cpus();
1685 	nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count,
1686 					       ioc->facts.MaxMSIxVectors);
1687 	if (!nr_msix)
1688 		return;
1689 
1690 	cpu = cpumask_first(cpu_online_mask);
1691 
1692 	list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1693 
1694 		unsigned int i, group = nr_cpus / nr_msix;
1695 
1696 		if (cpu >= nr_cpus)
1697 			break;
1698 
1699 		if (index < nr_cpus % nr_msix)
1700 			group++;
1701 
1702 		for (i = 0 ; i < group ; i++) {
1703 			ioc->cpu_msix_table[cpu] = index;
1704 			cpumask_or(reply_q->affinity_hint,
1705 				   reply_q->affinity_hint, get_cpu_mask(cpu));
1706 			cpu = cpumask_next(cpu, cpu_online_mask);
1707 		}
1708 
1709 		if (irq_set_affinity_hint(reply_q->vector,
1710 					   reply_q->affinity_hint))
1711 			dinitprintk(ioc, pr_info(MPT3SAS_FMT
1712 			    "error setting affinity hint for irq vector %d\n",
1713 			    ioc->name, reply_q->vector));
1714 		index++;
1715 	}
1716 }
1717 
1718 /**
1719  * _base_disable_msix - disables msix
1720  * @ioc: per adapter object
1721  *
1722  */
1723 static void
1724 _base_disable_msix(struct MPT3SAS_ADAPTER *ioc)
1725 {
1726 	if (!ioc->msix_enable)
1727 		return;
1728 	pci_disable_msix(ioc->pdev);
1729 	ioc->msix_enable = 0;
1730 }
1731 
1732 /**
1733  * _base_enable_msix - enables msix, failback to io_apic
1734  * @ioc: per adapter object
1735  *
1736  */
1737 static int
1738 _base_enable_msix(struct MPT3SAS_ADAPTER *ioc)
1739 {
1740 	struct msix_entry *entries, *a;
1741 	int r;
1742 	int i;
1743 	u8 try_msix = 0;
1744 
1745 	if (msix_disable == -1 || msix_disable == 0)
1746 		try_msix = 1;
1747 
1748 	if (!try_msix)
1749 		goto try_ioapic;
1750 
1751 	if (_base_check_enable_msix(ioc) != 0)
1752 		goto try_ioapic;
1753 
1754 	ioc->reply_queue_count = min_t(int, ioc->cpu_count,
1755 	    ioc->msix_vector_count);
1756 
1757 	printk(MPT3SAS_FMT "MSI-X vectors supported: %d, no of cores"
1758 	  ": %d, max_msix_vectors: %d\n", ioc->name, ioc->msix_vector_count,
1759 	  ioc->cpu_count, max_msix_vectors);
1760 
1761 	if (!ioc->rdpq_array_enable && max_msix_vectors == -1)
1762 		max_msix_vectors = 8;
1763 
1764 	if (max_msix_vectors > 0) {
1765 		ioc->reply_queue_count = min_t(int, max_msix_vectors,
1766 			ioc->reply_queue_count);
1767 		ioc->msix_vector_count = ioc->reply_queue_count;
1768 	} else if (max_msix_vectors == 0)
1769 		goto try_ioapic;
1770 
1771 	entries = kcalloc(ioc->reply_queue_count, sizeof(struct msix_entry),
1772 	    GFP_KERNEL);
1773 	if (!entries) {
1774 		dfailprintk(ioc, pr_info(MPT3SAS_FMT
1775 			"kcalloc failed @ at %s:%d/%s() !!!\n",
1776 			ioc->name, __FILE__, __LINE__, __func__));
1777 		goto try_ioapic;
1778 	}
1779 
1780 	for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++)
1781 		a->entry = i;
1782 
1783 	r = pci_enable_msix_exact(ioc->pdev, entries, ioc->reply_queue_count);
1784 	if (r) {
1785 		dfailprintk(ioc, pr_info(MPT3SAS_FMT
1786 			"pci_enable_msix_exact failed (r=%d) !!!\n",
1787 			ioc->name, r));
1788 		kfree(entries);
1789 		goto try_ioapic;
1790 	}
1791 
1792 	ioc->msix_enable = 1;
1793 	for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++) {
1794 		r = _base_request_irq(ioc, i, a->vector);
1795 		if (r) {
1796 			_base_free_irq(ioc);
1797 			_base_disable_msix(ioc);
1798 			kfree(entries);
1799 			goto try_ioapic;
1800 		}
1801 	}
1802 
1803 	kfree(entries);
1804 	return 0;
1805 
1806 /* failback to io_apic interrupt routing */
1807  try_ioapic:
1808 
1809 	ioc->reply_queue_count = 1;
1810 	r = _base_request_irq(ioc, 0, ioc->pdev->irq);
1811 
1812 	return r;
1813 }
1814 
1815 /**
1816  * mpt3sas_base_unmap_resources - free controller resources
1817  * @ioc: per adapter object
1818  */
1819 void
1820 mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc)
1821 {
1822 	struct pci_dev *pdev = ioc->pdev;
1823 
1824 	dexitprintk(ioc, printk(MPT3SAS_FMT "%s\n",
1825 		ioc->name, __func__));
1826 
1827 	_base_free_irq(ioc);
1828 	_base_disable_msix(ioc);
1829 
1830 	if (ioc->msix96_vector)
1831 		kfree(ioc->replyPostRegisterIndex);
1832 
1833 	if (ioc->chip_phys) {
1834 		iounmap(ioc->chip);
1835 		ioc->chip_phys = 0;
1836 	}
1837 
1838 	if (pci_is_enabled(pdev)) {
1839 		pci_release_selected_regions(ioc->pdev, ioc->bars);
1840 		pci_disable_pcie_error_reporting(pdev);
1841 		pci_disable_device(pdev);
1842 	}
1843 }
1844 
1845 /**
1846  * mpt3sas_base_map_resources - map in controller resources (io/irq/memap)
1847  * @ioc: per adapter object
1848  *
1849  * Returns 0 for success, non-zero for failure.
1850  */
1851 int
1852 mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
1853 {
1854 	struct pci_dev *pdev = ioc->pdev;
1855 	u32 memap_sz;
1856 	u32 pio_sz;
1857 	int i, r = 0;
1858 	u64 pio_chip = 0;
1859 	u64 chip_phys = 0;
1860 	struct adapter_reply_queue *reply_q;
1861 
1862 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n",
1863 	    ioc->name, __func__));
1864 
1865 	ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
1866 	if (pci_enable_device_mem(pdev)) {
1867 		pr_warn(MPT3SAS_FMT "pci_enable_device_mem: failed\n",
1868 			ioc->name);
1869 		ioc->bars = 0;
1870 		return -ENODEV;
1871 	}
1872 
1873 
1874 	if (pci_request_selected_regions(pdev, ioc->bars,
1875 	    MPT3SAS_DRIVER_NAME)) {
1876 		pr_warn(MPT3SAS_FMT "pci_request_selected_regions: failed\n",
1877 			ioc->name);
1878 		ioc->bars = 0;
1879 		r = -ENODEV;
1880 		goto out_fail;
1881 	}
1882 
1883 /* AER (Advanced Error Reporting) hooks */
1884 	pci_enable_pcie_error_reporting(pdev);
1885 
1886 	pci_set_master(pdev);
1887 
1888 
1889 	if (_base_config_dma_addressing(ioc, pdev) != 0) {
1890 		pr_warn(MPT3SAS_FMT "no suitable DMA mask for %s\n",
1891 		    ioc->name, pci_name(pdev));
1892 		r = -ENODEV;
1893 		goto out_fail;
1894 	}
1895 
1896 	for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) &&
1897 	     (!memap_sz || !pio_sz); i++) {
1898 		if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
1899 			if (pio_sz)
1900 				continue;
1901 			pio_chip = (u64)pci_resource_start(pdev, i);
1902 			pio_sz = pci_resource_len(pdev, i);
1903 		} else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
1904 			if (memap_sz)
1905 				continue;
1906 			ioc->chip_phys = pci_resource_start(pdev, i);
1907 			chip_phys = (u64)ioc->chip_phys;
1908 			memap_sz = pci_resource_len(pdev, i);
1909 			ioc->chip = ioremap(ioc->chip_phys, memap_sz);
1910 		}
1911 	}
1912 
1913 	if (ioc->chip == NULL) {
1914 		pr_err(MPT3SAS_FMT "unable to map adapter memory! "
1915 			" or resource not found\n", ioc->name);
1916 		r = -EINVAL;
1917 		goto out_fail;
1918 	}
1919 
1920 	_base_mask_interrupts(ioc);
1921 
1922 	r = _base_get_ioc_facts(ioc, CAN_SLEEP);
1923 	if (r)
1924 		goto out_fail;
1925 
1926 	if (!ioc->rdpq_array_enable_assigned) {
1927 		ioc->rdpq_array_enable = ioc->rdpq_array_capable;
1928 		ioc->rdpq_array_enable_assigned = 1;
1929 	}
1930 
1931 	r = _base_enable_msix(ioc);
1932 	if (r)
1933 		goto out_fail;
1934 
1935 	/* Use the Combined reply queue feature only for SAS3 C0 & higher
1936 	 * revision HBAs and also only when reply queue count is greater than 8
1937 	 */
1938 	if (ioc->msix96_vector && ioc->reply_queue_count > 8) {
1939 		/* Determine the Supplemental Reply Post Host Index Registers
1940 		 * Addresse. Supplemental Reply Post Host Index Registers
1941 		 * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and
1942 		 * each register is at offset bytes of
1943 		 * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one.
1944 		 */
1945 		ioc->replyPostRegisterIndex = kcalloc(
1946 		     MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT,
1947 		     sizeof(resource_size_t *), GFP_KERNEL);
1948 		if (!ioc->replyPostRegisterIndex) {
1949 			dfailprintk(ioc, printk(MPT3SAS_FMT
1950 			"allocation for reply Post Register Index failed!!!\n",
1951 								   ioc->name));
1952 			r = -ENOMEM;
1953 			goto out_fail;
1954 		}
1955 
1956 		for (i = 0; i < MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT; i++) {
1957 			ioc->replyPostRegisterIndex[i] = (resource_size_t *)
1958 			     ((u8 *)&ioc->chip->Doorbell +
1959 			     MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET +
1960 			     (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET));
1961 		}
1962 	} else
1963 		ioc->msix96_vector = 0;
1964 
1965 	list_for_each_entry(reply_q, &ioc->reply_queue_list, list)
1966 		pr_info(MPT3SAS_FMT "%s: IRQ %d\n",
1967 		    reply_q->name,  ((ioc->msix_enable) ? "PCI-MSI-X enabled" :
1968 		    "IO-APIC enabled"), reply_q->vector);
1969 
1970 	pr_info(MPT3SAS_FMT "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
1971 	    ioc->name, (unsigned long long)chip_phys, ioc->chip, memap_sz);
1972 	pr_info(MPT3SAS_FMT "ioport(0x%016llx), size(%d)\n",
1973 	    ioc->name, (unsigned long long)pio_chip, pio_sz);
1974 
1975 	/* Save PCI configuration state for recovery from PCI AER/EEH errors */
1976 	pci_save_state(pdev);
1977 	return 0;
1978 
1979  out_fail:
1980 	mpt3sas_base_unmap_resources(ioc);
1981 	return r;
1982 }
1983 
1984 /**
1985  * mpt3sas_base_get_msg_frame - obtain request mf pointer
1986  * @ioc: per adapter object
1987  * @smid: system request message index(smid zero is invalid)
1988  *
1989  * Returns virt pointer to message frame.
1990  */
1991 void *
1992 mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1993 {
1994 	return (void *)(ioc->request + (smid * ioc->request_sz));
1995 }
1996 
1997 /**
1998  * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr
1999  * @ioc: per adapter object
2000  * @smid: system request message index
2001  *
2002  * Returns virt pointer to sense buffer.
2003  */
2004 void *
2005 mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2006 {
2007 	return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
2008 }
2009 
2010 /**
2011  * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr
2012  * @ioc: per adapter object
2013  * @smid: system request message index
2014  *
2015  * Returns phys pointer to the low 32bit address of the sense buffer.
2016  */
2017 __le32
2018 mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2019 {
2020 	return cpu_to_le32(ioc->sense_dma + ((smid - 1) *
2021 	    SCSI_SENSE_BUFFERSIZE));
2022 }
2023 
2024 /**
2025  * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address
2026  * @ioc: per adapter object
2027  * @phys_addr: lower 32 physical addr of the reply
2028  *
2029  * Converts 32bit lower physical addr into a virt address.
2030  */
2031 void *
2032 mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr)
2033 {
2034 	if (!phys_addr)
2035 		return NULL;
2036 	return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
2037 }
2038 
2039 /**
2040  * mpt3sas_base_get_smid - obtain a free smid from internal queue
2041  * @ioc: per adapter object
2042  * @cb_idx: callback index
2043  *
2044  * Returns smid (zero is invalid)
2045  */
2046 u16
2047 mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
2048 {
2049 	unsigned long flags;
2050 	struct request_tracker *request;
2051 	u16 smid;
2052 
2053 	spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2054 	if (list_empty(&ioc->internal_free_list)) {
2055 		spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2056 		pr_err(MPT3SAS_FMT "%s: smid not available\n",
2057 		    ioc->name, __func__);
2058 		return 0;
2059 	}
2060 
2061 	request = list_entry(ioc->internal_free_list.next,
2062 	    struct request_tracker, tracker_list);
2063 	request->cb_idx = cb_idx;
2064 	smid = request->smid;
2065 	list_del(&request->tracker_list);
2066 	spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2067 	return smid;
2068 }
2069 
2070 /**
2071  * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue
2072  * @ioc: per adapter object
2073  * @cb_idx: callback index
2074  * @scmd: pointer to scsi command object
2075  *
2076  * Returns smid (zero is invalid)
2077  */
2078 u16
2079 mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx,
2080 	struct scsi_cmnd *scmd)
2081 {
2082 	unsigned long flags;
2083 	struct scsiio_tracker *request;
2084 	u16 smid;
2085 
2086 	spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2087 	if (list_empty(&ioc->free_list)) {
2088 		spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2089 		pr_err(MPT3SAS_FMT "%s: smid not available\n",
2090 		    ioc->name, __func__);
2091 		return 0;
2092 	}
2093 
2094 	request = list_entry(ioc->free_list.next,
2095 	    struct scsiio_tracker, tracker_list);
2096 	request->scmd = scmd;
2097 	request->cb_idx = cb_idx;
2098 	smid = request->smid;
2099 	list_del(&request->tracker_list);
2100 	spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2101 	return smid;
2102 }
2103 
2104 /**
2105  * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue
2106  * @ioc: per adapter object
2107  * @cb_idx: callback index
2108  *
2109  * Returns smid (zero is invalid)
2110  */
2111 u16
2112 mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
2113 {
2114 	unsigned long flags;
2115 	struct request_tracker *request;
2116 	u16 smid;
2117 
2118 	spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2119 	if (list_empty(&ioc->hpr_free_list)) {
2120 		spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2121 		return 0;
2122 	}
2123 
2124 	request = list_entry(ioc->hpr_free_list.next,
2125 	    struct request_tracker, tracker_list);
2126 	request->cb_idx = cb_idx;
2127 	smid = request->smid;
2128 	list_del(&request->tracker_list);
2129 	spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2130 	return smid;
2131 }
2132 
2133 /**
2134  * mpt3sas_base_free_smid - put smid back on free_list
2135  * @ioc: per adapter object
2136  * @smid: system request message index
2137  *
2138  * Return nothing.
2139  */
2140 void
2141 mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2142 {
2143 	unsigned long flags;
2144 	int i;
2145 	struct chain_tracker *chain_req, *next;
2146 
2147 	spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2148 	if (smid < ioc->hi_priority_smid) {
2149 		/* scsiio queue */
2150 		i = smid - 1;
2151 		if (!list_empty(&ioc->scsi_lookup[i].chain_list)) {
2152 			list_for_each_entry_safe(chain_req, next,
2153 			    &ioc->scsi_lookup[i].chain_list, tracker_list) {
2154 				list_del_init(&chain_req->tracker_list);
2155 				list_add(&chain_req->tracker_list,
2156 				    &ioc->free_chain_list);
2157 			}
2158 		}
2159 		ioc->scsi_lookup[i].cb_idx = 0xFF;
2160 		ioc->scsi_lookup[i].scmd = NULL;
2161 		list_add(&ioc->scsi_lookup[i].tracker_list, &ioc->free_list);
2162 		spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2163 
2164 		/*
2165 		 * See _wait_for_commands_to_complete() call with regards
2166 		 * to this code.
2167 		 */
2168 		if (ioc->shost_recovery && ioc->pending_io_count) {
2169 			if (ioc->pending_io_count == 1)
2170 				wake_up(&ioc->reset_wq);
2171 			ioc->pending_io_count--;
2172 		}
2173 		return;
2174 	} else if (smid < ioc->internal_smid) {
2175 		/* hi-priority */
2176 		i = smid - ioc->hi_priority_smid;
2177 		ioc->hpr_lookup[i].cb_idx = 0xFF;
2178 		list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list);
2179 	} else if (smid <= ioc->hba_queue_depth) {
2180 		/* internal queue */
2181 		i = smid - ioc->internal_smid;
2182 		ioc->internal_lookup[i].cb_idx = 0xFF;
2183 		list_add(&ioc->internal_lookup[i].tracker_list,
2184 		    &ioc->internal_free_list);
2185 	}
2186 	spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2187 }
2188 
2189 /**
2190  * _base_writeq - 64 bit write to MMIO
2191  * @ioc: per adapter object
2192  * @b: data payload
2193  * @addr: address in MMIO space
2194  * @writeq_lock: spin lock
2195  *
2196  * Glue for handling an atomic 64 bit word to MMIO. This special handling takes
2197  * care of 32 bit environment where its not quarenteed to send the entire word
2198  * in one transfer.
2199  */
2200 #if defined(writeq) && defined(CONFIG_64BIT)
2201 static inline void
2202 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
2203 {
2204 	writeq(cpu_to_le64(b), addr);
2205 }
2206 #else
2207 static inline void
2208 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
2209 {
2210 	unsigned long flags;
2211 	__u64 data_out = cpu_to_le64(b);
2212 
2213 	spin_lock_irqsave(writeq_lock, flags);
2214 	writel((u32)(data_out), addr);
2215 	writel((u32)(data_out >> 32), (addr + 4));
2216 	spin_unlock_irqrestore(writeq_lock, flags);
2217 }
2218 #endif
2219 
2220 static inline u8
2221 _base_get_msix_index(struct MPT3SAS_ADAPTER *ioc)
2222 {
2223 	return ioc->cpu_msix_table[raw_smp_processor_id()];
2224 }
2225 
2226 /**
2227  * mpt3sas_base_put_smid_scsi_io - send SCSI_IO request to firmware
2228  * @ioc: per adapter object
2229  * @smid: system request message index
2230  * @handle: device handle
2231  *
2232  * Return nothing.
2233  */
2234 void
2235 mpt3sas_base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle)
2236 {
2237 	Mpi2RequestDescriptorUnion_t descriptor;
2238 	u64 *request = (u64 *)&descriptor;
2239 
2240 
2241 	descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
2242 	descriptor.SCSIIO.MSIxIndex =  _base_get_msix_index(ioc);
2243 	descriptor.SCSIIO.SMID = cpu_to_le16(smid);
2244 	descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
2245 	descriptor.SCSIIO.LMID = 0;
2246 	_base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2247 	    &ioc->scsi_lookup_lock);
2248 }
2249 
2250 /**
2251  * mpt3sas_base_put_smid_fast_path - send fast path request to firmware
2252  * @ioc: per adapter object
2253  * @smid: system request message index
2254  * @handle: device handle
2255  *
2256  * Return nothing.
2257  */
2258 void
2259 mpt3sas_base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid,
2260 	u16 handle)
2261 {
2262 	Mpi2RequestDescriptorUnion_t descriptor;
2263 	u64 *request = (u64 *)&descriptor;
2264 
2265 	descriptor.SCSIIO.RequestFlags =
2266 	    MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
2267 	descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
2268 	descriptor.SCSIIO.SMID = cpu_to_le16(smid);
2269 	descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
2270 	descriptor.SCSIIO.LMID = 0;
2271 	_base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2272 	    &ioc->scsi_lookup_lock);
2273 }
2274 
2275 /**
2276  * mpt3sas_base_put_smid_hi_priority - send Task Managment request to firmware
2277  * @ioc: per adapter object
2278  * @smid: system request message index
2279  *
2280  * Return nothing.
2281  */
2282 void
2283 mpt3sas_base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2284 {
2285 	Mpi2RequestDescriptorUnion_t descriptor;
2286 	u64 *request = (u64 *)&descriptor;
2287 
2288 	descriptor.HighPriority.RequestFlags =
2289 	    MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
2290 	descriptor.HighPriority.MSIxIndex =  0;
2291 	descriptor.HighPriority.SMID = cpu_to_le16(smid);
2292 	descriptor.HighPriority.LMID = 0;
2293 	descriptor.HighPriority.Reserved1 = 0;
2294 	_base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2295 	    &ioc->scsi_lookup_lock);
2296 }
2297 
2298 /**
2299  * mpt3sas_base_put_smid_default - Default, primarily used for config pages
2300  * @ioc: per adapter object
2301  * @smid: system request message index
2302  *
2303  * Return nothing.
2304  */
2305 void
2306 mpt3sas_base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2307 {
2308 	Mpi2RequestDescriptorUnion_t descriptor;
2309 	u64 *request = (u64 *)&descriptor;
2310 
2311 	descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
2312 	descriptor.Default.MSIxIndex =  _base_get_msix_index(ioc);
2313 	descriptor.Default.SMID = cpu_to_le16(smid);
2314 	descriptor.Default.LMID = 0;
2315 	descriptor.Default.DescriptorTypeDependent = 0;
2316 	_base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2317 	    &ioc->scsi_lookup_lock);
2318 }
2319 
2320 /**
2321  * _base_display_intel_branding - Display branding string
2322  * @ioc: per adapter object
2323  *
2324  * Return nothing.
2325  */
2326 static void
2327 _base_display_intel_branding(struct MPT3SAS_ADAPTER *ioc)
2328 {
2329 	if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL)
2330 		return;
2331 
2332 	switch (ioc->pdev->device) {
2333 	case MPI25_MFGPAGE_DEVID_SAS3008:
2334 		switch (ioc->pdev->subsystem_device) {
2335 		case MPT3SAS_INTEL_RMS3JC080_SSDID:
2336 			pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2337 				MPT3SAS_INTEL_RMS3JC080_BRANDING);
2338 			break;
2339 
2340 		case MPT3SAS_INTEL_RS3GC008_SSDID:
2341 			pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2342 				MPT3SAS_INTEL_RS3GC008_BRANDING);
2343 			break;
2344 		case MPT3SAS_INTEL_RS3FC044_SSDID:
2345 			pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2346 				MPT3SAS_INTEL_RS3FC044_BRANDING);
2347 			break;
2348 		case MPT3SAS_INTEL_RS3UC080_SSDID:
2349 			pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2350 				MPT3SAS_INTEL_RS3UC080_BRANDING);
2351 			break;
2352 		default:
2353 			pr_info(MPT3SAS_FMT
2354 				"Intel(R) Controller: Subsystem ID: 0x%X\n",
2355 				ioc->name, ioc->pdev->subsystem_device);
2356 			break;
2357 		}
2358 		break;
2359 	default:
2360 		pr_info(MPT3SAS_FMT
2361 			"Intel(R) Controller: Subsystem ID: 0x%X\n",
2362 			ioc->name, ioc->pdev->subsystem_device);
2363 		break;
2364 	}
2365 }
2366 
2367 
2368 
2369 /**
2370  * _base_display_dell_branding - Display branding string
2371  * @ioc: per adapter object
2372  *
2373  * Return nothing.
2374  */
2375 static void
2376 _base_display_dell_branding(struct MPT3SAS_ADAPTER *ioc)
2377 {
2378 	if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_DELL)
2379 		return;
2380 
2381 	switch (ioc->pdev->device) {
2382 	case MPI25_MFGPAGE_DEVID_SAS3008:
2383 		switch (ioc->pdev->subsystem_device) {
2384 		case MPT3SAS_DELL_12G_HBA_SSDID:
2385 			pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2386 				MPT3SAS_DELL_12G_HBA_BRANDING);
2387 			break;
2388 		default:
2389 			pr_info(MPT3SAS_FMT
2390 			   "Dell 12Gbps HBA: Subsystem ID: 0x%X\n", ioc->name,
2391 			   ioc->pdev->subsystem_device);
2392 			break;
2393 		}
2394 		break;
2395 	default:
2396 		pr_info(MPT3SAS_FMT
2397 			"Dell 12Gbps HBA: Subsystem ID: 0x%X\n", ioc->name,
2398 			ioc->pdev->subsystem_device);
2399 		break;
2400 	}
2401 }
2402 
2403 /**
2404  * _base_display_cisco_branding - Display branding string
2405  * @ioc: per adapter object
2406  *
2407  * Return nothing.
2408  */
2409 static void
2410 _base_display_cisco_branding(struct MPT3SAS_ADAPTER *ioc)
2411 {
2412 	if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_CISCO)
2413 		return;
2414 
2415 	switch (ioc->pdev->device) {
2416 	case MPI25_MFGPAGE_DEVID_SAS3008:
2417 		switch (ioc->pdev->subsystem_device) {
2418 		case MPT3SAS_CISCO_12G_8E_HBA_SSDID:
2419 			pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2420 				MPT3SAS_CISCO_12G_8E_HBA_BRANDING);
2421 			break;
2422 		case MPT3SAS_CISCO_12G_8I_HBA_SSDID:
2423 			pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2424 				MPT3SAS_CISCO_12G_8I_HBA_BRANDING);
2425 			break;
2426 		case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
2427 			pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2428 				MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
2429 			break;
2430 		default:
2431 			pr_info(MPT3SAS_FMT
2432 			  "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
2433 			  ioc->name, ioc->pdev->subsystem_device);
2434 			break;
2435 		}
2436 		break;
2437 	case MPI25_MFGPAGE_DEVID_SAS3108_1:
2438 		switch (ioc->pdev->subsystem_device) {
2439 		case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
2440 			pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2441 			MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
2442 			break;
2443 		case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID:
2444 			pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2445 			MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING);
2446 			break;
2447 		default:
2448 			pr_info(MPT3SAS_FMT
2449 			 "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
2450 			 ioc->name, ioc->pdev->subsystem_device);
2451 			break;
2452 		}
2453 		break;
2454 	default:
2455 		 pr_info(MPT3SAS_FMT
2456 			"Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
2457 			ioc->name, ioc->pdev->subsystem_device);
2458 		break;
2459 	}
2460 }
2461 
2462 /**
2463  * _base_display_ioc_capabilities - Disply IOC's capabilities.
2464  * @ioc: per adapter object
2465  *
2466  * Return nothing.
2467  */
2468 static void
2469 _base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc)
2470 {
2471 	int i = 0;
2472 	char desc[16];
2473 	u32 iounit_pg1_flags;
2474 	u32 bios_version;
2475 
2476 	bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion);
2477 	strncpy(desc, ioc->manu_pg0.ChipName, 16);
2478 	pr_info(MPT3SAS_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "\
2479 	   "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
2480 	    ioc->name, desc,
2481 	   (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
2482 	   (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
2483 	   (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
2484 	   ioc->facts.FWVersion.Word & 0x000000FF,
2485 	   ioc->pdev->revision,
2486 	   (bios_version & 0xFF000000) >> 24,
2487 	   (bios_version & 0x00FF0000) >> 16,
2488 	   (bios_version & 0x0000FF00) >> 8,
2489 	    bios_version & 0x000000FF);
2490 
2491 	_base_display_intel_branding(ioc);
2492 	_base_display_dell_branding(ioc);
2493 	_base_display_cisco_branding(ioc);
2494 
2495 	pr_info(MPT3SAS_FMT "Protocol=(", ioc->name);
2496 
2497 	if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
2498 		pr_info("Initiator");
2499 		i++;
2500 	}
2501 
2502 	if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
2503 		pr_info("%sTarget", i ? "," : "");
2504 		i++;
2505 	}
2506 
2507 	i = 0;
2508 	pr_info("), ");
2509 	pr_info("Capabilities=(");
2510 
2511 	if (ioc->facts.IOCCapabilities &
2512 		    MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
2513 			pr_info("Raid");
2514 			i++;
2515 	}
2516 
2517 	if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
2518 		pr_info("%sTLR", i ? "," : "");
2519 		i++;
2520 	}
2521 
2522 	if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
2523 		pr_info("%sMulticast", i ? "," : "");
2524 		i++;
2525 	}
2526 
2527 	if (ioc->facts.IOCCapabilities &
2528 	    MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
2529 		pr_info("%sBIDI Target", i ? "," : "");
2530 		i++;
2531 	}
2532 
2533 	if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
2534 		pr_info("%sEEDP", i ? "," : "");
2535 		i++;
2536 	}
2537 
2538 	if (ioc->facts.IOCCapabilities &
2539 	    MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
2540 		pr_info("%sSnapshot Buffer", i ? "," : "");
2541 		i++;
2542 	}
2543 
2544 	if (ioc->facts.IOCCapabilities &
2545 	    MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
2546 		pr_info("%sDiag Trace Buffer", i ? "," : "");
2547 		i++;
2548 	}
2549 
2550 	if (ioc->facts.IOCCapabilities &
2551 	    MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
2552 		pr_info("%sDiag Extended Buffer", i ? "," : "");
2553 		i++;
2554 	}
2555 
2556 	if (ioc->facts.IOCCapabilities &
2557 	    MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
2558 		pr_info("%sTask Set Full", i ? "," : "");
2559 		i++;
2560 	}
2561 
2562 	iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
2563 	if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
2564 		pr_info("%sNCQ", i ? "," : "");
2565 		i++;
2566 	}
2567 
2568 	pr_info(")\n");
2569 }
2570 
2571 /**
2572  * mpt3sas_base_update_missing_delay - change the missing delay timers
2573  * @ioc: per adapter object
2574  * @device_missing_delay: amount of time till device is reported missing
2575  * @io_missing_delay: interval IO is returned when there is a missing device
2576  *
2577  * Return nothing.
2578  *
2579  * Passed on the command line, this function will modify the device missing
2580  * delay, as well as the io missing delay. This should be called at driver
2581  * load time.
2582  */
2583 void
2584 mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc,
2585 	u16 device_missing_delay, u8 io_missing_delay)
2586 {
2587 	u16 dmd, dmd_new, dmd_orignal;
2588 	u8 io_missing_delay_original;
2589 	u16 sz;
2590 	Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL;
2591 	Mpi2ConfigReply_t mpi_reply;
2592 	u8 num_phys = 0;
2593 	u16 ioc_status;
2594 
2595 	mpt3sas_config_get_number_hba_phys(ioc, &num_phys);
2596 	if (!num_phys)
2597 		return;
2598 
2599 	sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys *
2600 	    sizeof(Mpi2SasIOUnit1PhyData_t));
2601 	sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL);
2602 	if (!sas_iounit_pg1) {
2603 		pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2604 		    ioc->name, __FILE__, __LINE__, __func__);
2605 		goto out;
2606 	}
2607 	if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
2608 	    sas_iounit_pg1, sz))) {
2609 		pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2610 		    ioc->name, __FILE__, __LINE__, __func__);
2611 		goto out;
2612 	}
2613 	ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
2614 	    MPI2_IOCSTATUS_MASK;
2615 	if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
2616 		pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2617 		    ioc->name, __FILE__, __LINE__, __func__);
2618 		goto out;
2619 	}
2620 
2621 	/* device missing delay */
2622 	dmd = sas_iounit_pg1->ReportDeviceMissingDelay;
2623 	if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
2624 		dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
2625 	else
2626 		dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
2627 	dmd_orignal = dmd;
2628 	if (device_missing_delay > 0x7F) {
2629 		dmd = (device_missing_delay > 0x7F0) ? 0x7F0 :
2630 		    device_missing_delay;
2631 		dmd = dmd / 16;
2632 		dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16;
2633 	} else
2634 		dmd = device_missing_delay;
2635 	sas_iounit_pg1->ReportDeviceMissingDelay = dmd;
2636 
2637 	/* io missing delay */
2638 	io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay;
2639 	sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay;
2640 
2641 	if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1,
2642 	    sz)) {
2643 		if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
2644 			dmd_new = (dmd &
2645 			    MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
2646 		else
2647 			dmd_new =
2648 		    dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
2649 		pr_info(MPT3SAS_FMT "device_missing_delay: old(%d), new(%d)\n",
2650 			ioc->name, dmd_orignal, dmd_new);
2651 		pr_info(MPT3SAS_FMT "ioc_missing_delay: old(%d), new(%d)\n",
2652 			ioc->name, io_missing_delay_original,
2653 		    io_missing_delay);
2654 		ioc->device_missing_delay = dmd_new;
2655 		ioc->io_missing_delay = io_missing_delay;
2656 	}
2657 
2658 out:
2659 	kfree(sas_iounit_pg1);
2660 }
2661 /**
2662  * _base_static_config_pages - static start of day config pages
2663  * @ioc: per adapter object
2664  *
2665  * Return nothing.
2666  */
2667 static void
2668 _base_static_config_pages(struct MPT3SAS_ADAPTER *ioc)
2669 {
2670 	Mpi2ConfigReply_t mpi_reply;
2671 	u32 iounit_pg1_flags;
2672 
2673 	mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0);
2674 	if (ioc->ir_firmware)
2675 		mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
2676 		    &ioc->manu_pg10);
2677 
2678 	/*
2679 	 * Ensure correct T10 PI operation if vendor left EEDPTagMode
2680 	 * flag unset in NVDATA.
2681 	 */
2682 	mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply, &ioc->manu_pg11);
2683 	if (ioc->manu_pg11.EEDPTagMode == 0) {
2684 		pr_err("%s: overriding NVDATA EEDPTagMode setting\n",
2685 		    ioc->name);
2686 		ioc->manu_pg11.EEDPTagMode &= ~0x3;
2687 		ioc->manu_pg11.EEDPTagMode |= 0x1;
2688 		mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply,
2689 		    &ioc->manu_pg11);
2690 	}
2691 
2692 	mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
2693 	mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
2694 	mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
2695 	mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0);
2696 	mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
2697 	mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8);
2698 	_base_display_ioc_capabilities(ioc);
2699 
2700 	/*
2701 	 * Enable task_set_full handling in iounit_pg1 when the
2702 	 * facts capabilities indicate that its supported.
2703 	 */
2704 	iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
2705 	if ((ioc->facts.IOCCapabilities &
2706 	    MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING))
2707 		iounit_pg1_flags &=
2708 		    ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
2709 	else
2710 		iounit_pg1_flags |=
2711 		    MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
2712 	ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags);
2713 	mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
2714 
2715 	if (ioc->iounit_pg8.NumSensors)
2716 		ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors;
2717 }
2718 
2719 /**
2720  * _base_release_memory_pools - release memory
2721  * @ioc: per adapter object
2722  *
2723  * Free memory allocated from _base_allocate_memory_pools.
2724  *
2725  * Return nothing.
2726  */
2727 static void
2728 _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
2729 {
2730 	int i = 0;
2731 	struct reply_post_struct *rps;
2732 
2733 	dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2734 	    __func__));
2735 
2736 	if (ioc->request) {
2737 		pci_free_consistent(ioc->pdev, ioc->request_dma_sz,
2738 		    ioc->request,  ioc->request_dma);
2739 		dexitprintk(ioc, pr_info(MPT3SAS_FMT
2740 			"request_pool(0x%p): free\n",
2741 			ioc->name, ioc->request));
2742 		ioc->request = NULL;
2743 	}
2744 
2745 	if (ioc->sense) {
2746 		pci_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
2747 		if (ioc->sense_dma_pool)
2748 			pci_pool_destroy(ioc->sense_dma_pool);
2749 		dexitprintk(ioc, pr_info(MPT3SAS_FMT
2750 			"sense_pool(0x%p): free\n",
2751 			ioc->name, ioc->sense));
2752 		ioc->sense = NULL;
2753 	}
2754 
2755 	if (ioc->reply) {
2756 		pci_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
2757 		if (ioc->reply_dma_pool)
2758 			pci_pool_destroy(ioc->reply_dma_pool);
2759 		dexitprintk(ioc, pr_info(MPT3SAS_FMT
2760 			"reply_pool(0x%p): free\n",
2761 			ioc->name, ioc->reply));
2762 		ioc->reply = NULL;
2763 	}
2764 
2765 	if (ioc->reply_free) {
2766 		pci_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
2767 		    ioc->reply_free_dma);
2768 		if (ioc->reply_free_dma_pool)
2769 			pci_pool_destroy(ioc->reply_free_dma_pool);
2770 		dexitprintk(ioc, pr_info(MPT3SAS_FMT
2771 			"reply_free_pool(0x%p): free\n",
2772 			ioc->name, ioc->reply_free));
2773 		ioc->reply_free = NULL;
2774 	}
2775 
2776 	if (ioc->reply_post) {
2777 		do {
2778 			rps = &ioc->reply_post[i];
2779 			if (rps->reply_post_free) {
2780 				pci_pool_free(
2781 				    ioc->reply_post_free_dma_pool,
2782 				    rps->reply_post_free,
2783 				    rps->reply_post_free_dma);
2784 				dexitprintk(ioc, pr_info(MPT3SAS_FMT
2785 				    "reply_post_free_pool(0x%p): free\n",
2786 				    ioc->name, rps->reply_post_free));
2787 				rps->reply_post_free = NULL;
2788 			}
2789 		} while (ioc->rdpq_array_enable &&
2790 			   (++i < ioc->reply_queue_count));
2791 
2792 		if (ioc->reply_post_free_dma_pool)
2793 			pci_pool_destroy(ioc->reply_post_free_dma_pool);
2794 		kfree(ioc->reply_post);
2795 	}
2796 
2797 	if (ioc->config_page) {
2798 		dexitprintk(ioc, pr_info(MPT3SAS_FMT
2799 		    "config_page(0x%p): free\n", ioc->name,
2800 		    ioc->config_page));
2801 		pci_free_consistent(ioc->pdev, ioc->config_page_sz,
2802 		    ioc->config_page, ioc->config_page_dma);
2803 	}
2804 
2805 	if (ioc->scsi_lookup) {
2806 		free_pages((ulong)ioc->scsi_lookup, ioc->scsi_lookup_pages);
2807 		ioc->scsi_lookup = NULL;
2808 	}
2809 	kfree(ioc->hpr_lookup);
2810 	kfree(ioc->internal_lookup);
2811 	if (ioc->chain_lookup) {
2812 		for (i = 0; i < ioc->chain_depth; i++) {
2813 			if (ioc->chain_lookup[i].chain_buffer)
2814 				pci_pool_free(ioc->chain_dma_pool,
2815 				    ioc->chain_lookup[i].chain_buffer,
2816 				    ioc->chain_lookup[i].chain_buffer_dma);
2817 		}
2818 		if (ioc->chain_dma_pool)
2819 			pci_pool_destroy(ioc->chain_dma_pool);
2820 		free_pages((ulong)ioc->chain_lookup, ioc->chain_pages);
2821 		ioc->chain_lookup = NULL;
2822 	}
2823 }
2824 
2825 /**
2826  * _base_allocate_memory_pools - allocate start of day memory pools
2827  * @ioc: per adapter object
2828  * @sleep_flag: CAN_SLEEP or NO_SLEEP
2829  *
2830  * Returns 0 success, anything else error
2831  */
2832 static int
2833 _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc,  int sleep_flag)
2834 {
2835 	struct mpt3sas_facts *facts;
2836 	u16 max_sge_elements;
2837 	u16 chains_needed_per_io;
2838 	u32 sz, total_sz, reply_post_free_sz;
2839 	u32 retry_sz;
2840 	u16 max_request_credit;
2841 	unsigned short sg_tablesize;
2842 	u16 sge_size;
2843 	int i;
2844 
2845 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2846 	    __func__));
2847 
2848 
2849 	retry_sz = 0;
2850 	facts = &ioc->facts;
2851 
2852 	/* command line tunables for max sgl entries */
2853 	if (max_sgl_entries != -1)
2854 		sg_tablesize = max_sgl_entries;
2855 	else
2856 		sg_tablesize = MPT3SAS_SG_DEPTH;
2857 
2858 	if (sg_tablesize < MPT3SAS_MIN_PHYS_SEGMENTS)
2859 		sg_tablesize = MPT3SAS_MIN_PHYS_SEGMENTS;
2860 	else if (sg_tablesize > MPT3SAS_MAX_PHYS_SEGMENTS) {
2861 		sg_tablesize = min_t(unsigned short, sg_tablesize,
2862 				      SCSI_MAX_SG_CHAIN_SEGMENTS);
2863 		pr_warn(MPT3SAS_FMT
2864 		 "sg_tablesize(%u) is bigger than kernel"
2865 		 " defined SCSI_MAX_SG_SEGMENTS(%u)\n", ioc->name,
2866 		 sg_tablesize, MPT3SAS_MAX_PHYS_SEGMENTS);
2867 	}
2868 	ioc->shost->sg_tablesize = sg_tablesize;
2869 
2870 	ioc->hi_priority_depth = facts->HighPriorityCredit;
2871 	ioc->internal_depth = ioc->hi_priority_depth + (5);
2872 	/* command line tunables  for max controller queue depth */
2873 	if (max_queue_depth != -1 && max_queue_depth != 0) {
2874 		max_request_credit = min_t(u16, max_queue_depth +
2875 		    ioc->hi_priority_depth + ioc->internal_depth,
2876 		    facts->RequestCredit);
2877 		if (max_request_credit > MAX_HBA_QUEUE_DEPTH)
2878 			max_request_credit =  MAX_HBA_QUEUE_DEPTH;
2879 	} else
2880 		max_request_credit = min_t(u16, facts->RequestCredit,
2881 		    MAX_HBA_QUEUE_DEPTH);
2882 
2883 	ioc->hba_queue_depth = max_request_credit;
2884 
2885 	/* request frame size */
2886 	ioc->request_sz = facts->IOCRequestFrameSize * 4;
2887 
2888 	/* reply frame size */
2889 	ioc->reply_sz = facts->ReplyFrameSize * 4;
2890 
2891 	/* calculate the max scatter element size */
2892 	sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee);
2893 
2894  retry_allocation:
2895 	total_sz = 0;
2896 	/* calculate number of sg elements left over in the 1st frame */
2897 	max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) -
2898 	    sizeof(Mpi2SGEIOUnion_t)) + sge_size);
2899 	ioc->max_sges_in_main_message = max_sge_elements/sge_size;
2900 
2901 	/* now do the same for a chain buffer */
2902 	max_sge_elements = ioc->request_sz - sge_size;
2903 	ioc->max_sges_in_chain_message = max_sge_elements/sge_size;
2904 
2905 	/*
2906 	 *  MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE
2907 	 */
2908 	chains_needed_per_io = ((ioc->shost->sg_tablesize -
2909 	   ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message)
2910 	    + 1;
2911 	if (chains_needed_per_io > facts->MaxChainDepth) {
2912 		chains_needed_per_io = facts->MaxChainDepth;
2913 		ioc->shost->sg_tablesize = min_t(u16,
2914 		ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message
2915 		* chains_needed_per_io), ioc->shost->sg_tablesize);
2916 	}
2917 	ioc->chains_needed_per_io = chains_needed_per_io;
2918 
2919 	/* reply free queue sizing - taking into account for 64 FW events */
2920 	ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
2921 
2922 	/* calculate reply descriptor post queue depth */
2923 	ioc->reply_post_queue_depth = ioc->hba_queue_depth +
2924 				ioc->reply_free_queue_depth +  1 ;
2925 	/* align the reply post queue on the next 16 count boundary */
2926 	if (ioc->reply_post_queue_depth % 16)
2927 		ioc->reply_post_queue_depth += 16 -
2928 		(ioc->reply_post_queue_depth % 16);
2929 
2930 
2931 	if (ioc->reply_post_queue_depth >
2932 	    facts->MaxReplyDescriptorPostQueueDepth) {
2933 		ioc->reply_post_queue_depth =
2934 				facts->MaxReplyDescriptorPostQueueDepth -
2935 		    (facts->MaxReplyDescriptorPostQueueDepth % 16);
2936 		ioc->hba_queue_depth =
2937 				((ioc->reply_post_queue_depth - 64) / 2) - 1;
2938 		ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
2939 	}
2940 
2941 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "scatter gather: " \
2942 	    "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), "
2943 	    "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message,
2944 	    ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize,
2945 	    ioc->chains_needed_per_io));
2946 
2947 	/* reply post queue, 16 byte align */
2948 	reply_post_free_sz = ioc->reply_post_queue_depth *
2949 	    sizeof(Mpi2DefaultReplyDescriptor_t);
2950 
2951 	sz = reply_post_free_sz;
2952 	if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable)
2953 		sz *= ioc->reply_queue_count;
2954 
2955 	ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ?
2956 	    (ioc->reply_queue_count):1,
2957 	    sizeof(struct reply_post_struct), GFP_KERNEL);
2958 
2959 	if (!ioc->reply_post) {
2960 		pr_err(MPT3SAS_FMT "reply_post_free pool: kcalloc failed\n",
2961 			ioc->name);
2962 		goto out;
2963 	}
2964 	ioc->reply_post_free_dma_pool = pci_pool_create("reply_post_free pool",
2965 	    ioc->pdev, sz, 16, 0);
2966 	if (!ioc->reply_post_free_dma_pool) {
2967 		pr_err(MPT3SAS_FMT
2968 		 "reply_post_free pool: pci_pool_create failed\n",
2969 		 ioc->name);
2970 		goto out;
2971 	}
2972 	i = 0;
2973 	do {
2974 		ioc->reply_post[i].reply_post_free =
2975 		    pci_pool_alloc(ioc->reply_post_free_dma_pool,
2976 		    GFP_KERNEL,
2977 		    &ioc->reply_post[i].reply_post_free_dma);
2978 		if (!ioc->reply_post[i].reply_post_free) {
2979 			pr_err(MPT3SAS_FMT
2980 			"reply_post_free pool: pci_pool_alloc failed\n",
2981 			ioc->name);
2982 			goto out;
2983 		}
2984 		memset(ioc->reply_post[i].reply_post_free, 0, sz);
2985 		dinitprintk(ioc, pr_info(MPT3SAS_FMT
2986 		    "reply post free pool (0x%p): depth(%d),"
2987 		    "element_size(%d), pool_size(%d kB)\n", ioc->name,
2988 		    ioc->reply_post[i].reply_post_free,
2989 		    ioc->reply_post_queue_depth, 8, sz/1024));
2990 		dinitprintk(ioc, pr_info(MPT3SAS_FMT
2991 		    "reply_post_free_dma = (0x%llx)\n", ioc->name,
2992 		    (unsigned long long)
2993 		    ioc->reply_post[i].reply_post_free_dma));
2994 		total_sz += sz;
2995 	} while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count));
2996 
2997 	if (ioc->dma_mask == 64) {
2998 		if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) {
2999 			pr_warn(MPT3SAS_FMT
3000 			    "no suitable consistent DMA mask for %s\n",
3001 			    ioc->name, pci_name(ioc->pdev));
3002 			goto out;
3003 		}
3004 	}
3005 
3006 	ioc->scsiio_depth = ioc->hba_queue_depth -
3007 	    ioc->hi_priority_depth - ioc->internal_depth;
3008 
3009 	/* set the scsi host can_queue depth
3010 	 * with some internal commands that could be outstanding
3011 	 */
3012 	ioc->shost->can_queue = ioc->scsiio_depth;
3013 	dinitprintk(ioc, pr_info(MPT3SAS_FMT
3014 		"scsi host: can_queue depth (%d)\n",
3015 		ioc->name, ioc->shost->can_queue));
3016 
3017 
3018 	/* contiguous pool for request and chains, 16 byte align, one extra "
3019 	 * "frame for smid=0
3020 	 */
3021 	ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth;
3022 	sz = ((ioc->scsiio_depth + 1) * ioc->request_sz);
3023 
3024 	/* hi-priority queue */
3025 	sz += (ioc->hi_priority_depth * ioc->request_sz);
3026 
3027 	/* internal queue */
3028 	sz += (ioc->internal_depth * ioc->request_sz);
3029 
3030 	ioc->request_dma_sz = sz;
3031 	ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma);
3032 	if (!ioc->request) {
3033 		pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
3034 		    "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
3035 		    "total(%d kB)\n", ioc->name, ioc->hba_queue_depth,
3036 		    ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
3037 		if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH)
3038 			goto out;
3039 		retry_sz += 64;
3040 		ioc->hba_queue_depth = max_request_credit - retry_sz;
3041 		goto retry_allocation;
3042 	}
3043 
3044 	if (retry_sz)
3045 		pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
3046 		    "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
3047 		    "total(%d kb)\n", ioc->name, ioc->hba_queue_depth,
3048 		    ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
3049 
3050 	/* hi-priority queue */
3051 	ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
3052 	    ioc->request_sz);
3053 	ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) *
3054 	    ioc->request_sz);
3055 
3056 	/* internal queue */
3057 	ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth *
3058 	    ioc->request_sz);
3059 	ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
3060 	    ioc->request_sz);
3061 
3062 	dinitprintk(ioc, pr_info(MPT3SAS_FMT
3063 		"request pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
3064 		ioc->name, ioc->request, ioc->hba_queue_depth, ioc->request_sz,
3065 	    (ioc->hba_queue_depth * ioc->request_sz)/1024));
3066 
3067 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "request pool: dma(0x%llx)\n",
3068 	    ioc->name, (unsigned long long) ioc->request_dma));
3069 	total_sz += sz;
3070 
3071 	sz = ioc->scsiio_depth * sizeof(struct scsiio_tracker);
3072 	ioc->scsi_lookup_pages = get_order(sz);
3073 	ioc->scsi_lookup = (struct scsiio_tracker *)__get_free_pages(
3074 	    GFP_KERNEL, ioc->scsi_lookup_pages);
3075 	if (!ioc->scsi_lookup) {
3076 		pr_err(MPT3SAS_FMT "scsi_lookup: get_free_pages failed, sz(%d)\n",
3077 			ioc->name, (int)sz);
3078 		goto out;
3079 	}
3080 
3081 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "scsiio(0x%p): depth(%d)\n",
3082 		ioc->name, ioc->request, ioc->scsiio_depth));
3083 
3084 	ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH);
3085 	sz = ioc->chain_depth * sizeof(struct chain_tracker);
3086 	ioc->chain_pages = get_order(sz);
3087 	ioc->chain_lookup = (struct chain_tracker *)__get_free_pages(
3088 	    GFP_KERNEL, ioc->chain_pages);
3089 	if (!ioc->chain_lookup) {
3090 		pr_err(MPT3SAS_FMT "chain_lookup: __get_free_pages failed\n",
3091 			ioc->name);
3092 		goto out;
3093 	}
3094 	ioc->chain_dma_pool = pci_pool_create("chain pool", ioc->pdev,
3095 	    ioc->request_sz, 16, 0);
3096 	if (!ioc->chain_dma_pool) {
3097 		pr_err(MPT3SAS_FMT "chain_dma_pool: pci_pool_create failed\n",
3098 			ioc->name);
3099 		goto out;
3100 	}
3101 	for (i = 0; i < ioc->chain_depth; i++) {
3102 		ioc->chain_lookup[i].chain_buffer = pci_pool_alloc(
3103 		    ioc->chain_dma_pool , GFP_KERNEL,
3104 		    &ioc->chain_lookup[i].chain_buffer_dma);
3105 		if (!ioc->chain_lookup[i].chain_buffer) {
3106 			ioc->chain_depth = i;
3107 			goto chain_done;
3108 		}
3109 		total_sz += ioc->request_sz;
3110 	}
3111  chain_done:
3112 	dinitprintk(ioc, pr_info(MPT3SAS_FMT
3113 		"chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n",
3114 		ioc->name, ioc->chain_depth, ioc->request_sz,
3115 		((ioc->chain_depth *  ioc->request_sz))/1024));
3116 
3117 	/* initialize hi-priority queue smid's */
3118 	ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
3119 	    sizeof(struct request_tracker), GFP_KERNEL);
3120 	if (!ioc->hpr_lookup) {
3121 		pr_err(MPT3SAS_FMT "hpr_lookup: kcalloc failed\n",
3122 		    ioc->name);
3123 		goto out;
3124 	}
3125 	ioc->hi_priority_smid = ioc->scsiio_depth + 1;
3126 	dinitprintk(ioc, pr_info(MPT3SAS_FMT
3127 		"hi_priority(0x%p): depth(%d), start smid(%d)\n",
3128 		ioc->name, ioc->hi_priority,
3129 	    ioc->hi_priority_depth, ioc->hi_priority_smid));
3130 
3131 	/* initialize internal queue smid's */
3132 	ioc->internal_lookup = kcalloc(ioc->internal_depth,
3133 	    sizeof(struct request_tracker), GFP_KERNEL);
3134 	if (!ioc->internal_lookup) {
3135 		pr_err(MPT3SAS_FMT "internal_lookup: kcalloc failed\n",
3136 		    ioc->name);
3137 		goto out;
3138 	}
3139 	ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
3140 	dinitprintk(ioc, pr_info(MPT3SAS_FMT
3141 		"internal(0x%p): depth(%d), start smid(%d)\n",
3142 		ioc->name, ioc->internal,
3143 	    ioc->internal_depth, ioc->internal_smid));
3144 
3145 	/* sense buffers, 4 byte align */
3146 	sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
3147 	ioc->sense_dma_pool = pci_pool_create("sense pool", ioc->pdev, sz, 4,
3148 	    0);
3149 	if (!ioc->sense_dma_pool) {
3150 		pr_err(MPT3SAS_FMT "sense pool: pci_pool_create failed\n",
3151 		    ioc->name);
3152 		goto out;
3153 	}
3154 	ioc->sense = pci_pool_alloc(ioc->sense_dma_pool , GFP_KERNEL,
3155 	    &ioc->sense_dma);
3156 	if (!ioc->sense) {
3157 		pr_err(MPT3SAS_FMT "sense pool: pci_pool_alloc failed\n",
3158 		    ioc->name);
3159 		goto out;
3160 	}
3161 	dinitprintk(ioc, pr_info(MPT3SAS_FMT
3162 	    "sense pool(0x%p): depth(%d), element_size(%d), pool_size"
3163 	    "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth,
3164 	    SCSI_SENSE_BUFFERSIZE, sz/1024));
3165 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "sense_dma(0x%llx)\n",
3166 	    ioc->name, (unsigned long long)ioc->sense_dma));
3167 	total_sz += sz;
3168 
3169 	/* reply pool, 4 byte align */
3170 	sz = ioc->reply_free_queue_depth * ioc->reply_sz;
3171 	ioc->reply_dma_pool = pci_pool_create("reply pool", ioc->pdev, sz, 4,
3172 	    0);
3173 	if (!ioc->reply_dma_pool) {
3174 		pr_err(MPT3SAS_FMT "reply pool: pci_pool_create failed\n",
3175 		    ioc->name);
3176 		goto out;
3177 	}
3178 	ioc->reply = pci_pool_alloc(ioc->reply_dma_pool , GFP_KERNEL,
3179 	    &ioc->reply_dma);
3180 	if (!ioc->reply) {
3181 		pr_err(MPT3SAS_FMT "reply pool: pci_pool_alloc failed\n",
3182 		    ioc->name);
3183 		goto out;
3184 	}
3185 	ioc->reply_dma_min_address = (u32)(ioc->reply_dma);
3186 	ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz;
3187 	dinitprintk(ioc, pr_info(MPT3SAS_FMT
3188 		"reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
3189 		ioc->name, ioc->reply,
3190 	    ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024));
3191 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_dma(0x%llx)\n",
3192 	    ioc->name, (unsigned long long)ioc->reply_dma));
3193 	total_sz += sz;
3194 
3195 	/* reply free queue, 16 byte align */
3196 	sz = ioc->reply_free_queue_depth * 4;
3197 	ioc->reply_free_dma_pool = pci_pool_create("reply_free pool",
3198 	    ioc->pdev, sz, 16, 0);
3199 	if (!ioc->reply_free_dma_pool) {
3200 		pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_create failed\n",
3201 			ioc->name);
3202 		goto out;
3203 	}
3204 	ioc->reply_free = pci_pool_alloc(ioc->reply_free_dma_pool , GFP_KERNEL,
3205 	    &ioc->reply_free_dma);
3206 	if (!ioc->reply_free) {
3207 		pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_alloc failed\n",
3208 			ioc->name);
3209 		goto out;
3210 	}
3211 	memset(ioc->reply_free, 0, sz);
3212 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_free pool(0x%p): " \
3213 	    "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name,
3214 	    ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024));
3215 	dinitprintk(ioc, pr_info(MPT3SAS_FMT
3216 		"reply_free_dma (0x%llx)\n",
3217 		ioc->name, (unsigned long long)ioc->reply_free_dma));
3218 	total_sz += sz;
3219 
3220 	ioc->config_page_sz = 512;
3221 	ioc->config_page = pci_alloc_consistent(ioc->pdev,
3222 	    ioc->config_page_sz, &ioc->config_page_dma);
3223 	if (!ioc->config_page) {
3224 		pr_err(MPT3SAS_FMT
3225 			"config page: pci_pool_alloc failed\n",
3226 			ioc->name);
3227 		goto out;
3228 	}
3229 	dinitprintk(ioc, pr_info(MPT3SAS_FMT
3230 		"config page(0x%p): size(%d)\n",
3231 		ioc->name, ioc->config_page, ioc->config_page_sz));
3232 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "config_page_dma(0x%llx)\n",
3233 		ioc->name, (unsigned long long)ioc->config_page_dma));
3234 	total_sz += ioc->config_page_sz;
3235 
3236 	pr_info(MPT3SAS_FMT "Allocated physical memory: size(%d kB)\n",
3237 	    ioc->name, total_sz/1024);
3238 	pr_info(MPT3SAS_FMT
3239 		"Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n",
3240 	    ioc->name, ioc->shost->can_queue, facts->RequestCredit);
3241 	pr_info(MPT3SAS_FMT "Scatter Gather Elements per IO(%d)\n",
3242 	    ioc->name, ioc->shost->sg_tablesize);
3243 	return 0;
3244 
3245  out:
3246 	return -ENOMEM;
3247 }
3248 
3249 /**
3250  * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter.
3251  * @ioc: Pointer to MPT_ADAPTER structure
3252  * @cooked: Request raw or cooked IOC state
3253  *
3254  * Returns all IOC Doorbell register bits if cooked==0, else just the
3255  * Doorbell bits in MPI_IOC_STATE_MASK.
3256  */
3257 u32
3258 mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked)
3259 {
3260 	u32 s, sc;
3261 
3262 	s = readl(&ioc->chip->Doorbell);
3263 	sc = s & MPI2_IOC_STATE_MASK;
3264 	return cooked ? sc : s;
3265 }
3266 
3267 /**
3268  * _base_wait_on_iocstate - waiting on a particular ioc state
3269  * @ioc_state: controller state { READY, OPERATIONAL, or RESET }
3270  * @timeout: timeout in second
3271  * @sleep_flag: CAN_SLEEP or NO_SLEEP
3272  *
3273  * Returns 0 for success, non-zero for failure.
3274  */
3275 static int
3276 _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout,
3277 	int sleep_flag)
3278 {
3279 	u32 count, cntdn;
3280 	u32 current_state;
3281 
3282 	count = 0;
3283 	cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3284 	do {
3285 		current_state = mpt3sas_base_get_iocstate(ioc, 1);
3286 		if (current_state == ioc_state)
3287 			return 0;
3288 		if (count && current_state == MPI2_IOC_STATE_FAULT)
3289 			break;
3290 		if (sleep_flag == CAN_SLEEP)
3291 			usleep_range(1000, 1500);
3292 		else
3293 			udelay(500);
3294 		count++;
3295 	} while (--cntdn);
3296 
3297 	return current_state;
3298 }
3299 
3300 /**
3301  * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
3302  * a write to the doorbell)
3303  * @ioc: per adapter object
3304  * @timeout: timeout in second
3305  * @sleep_flag: CAN_SLEEP or NO_SLEEP
3306  *
3307  * Returns 0 for success, non-zero for failure.
3308  *
3309  * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
3310  */
3311 static int
3312 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc, int sleep_flag);
3313 
3314 static int
3315 _base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout,
3316 	int sleep_flag)
3317 {
3318 	u32 cntdn, count;
3319 	u32 int_status;
3320 
3321 	count = 0;
3322 	cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3323 	do {
3324 		int_status = readl(&ioc->chip->HostInterruptStatus);
3325 		if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3326 			dhsprintk(ioc, pr_info(MPT3SAS_FMT
3327 				"%s: successful count(%d), timeout(%d)\n",
3328 				ioc->name, __func__, count, timeout));
3329 			return 0;
3330 		}
3331 		if (sleep_flag == CAN_SLEEP)
3332 			usleep_range(1000, 1500);
3333 		else
3334 			udelay(500);
3335 		count++;
3336 	} while (--cntdn);
3337 
3338 	pr_err(MPT3SAS_FMT
3339 		"%s: failed due to timeout count(%d), int_status(%x)!\n",
3340 		ioc->name, __func__, count, int_status);
3341 	return -EFAULT;
3342 }
3343 
3344 /**
3345  * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell.
3346  * @ioc: per adapter object
3347  * @timeout: timeout in second
3348  * @sleep_flag: CAN_SLEEP or NO_SLEEP
3349  *
3350  * Returns 0 for success, non-zero for failure.
3351  *
3352  * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to
3353  * doorbell.
3354  */
3355 static int
3356 _base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout,
3357 	int sleep_flag)
3358 {
3359 	u32 cntdn, count;
3360 	u32 int_status;
3361 	u32 doorbell;
3362 
3363 	count = 0;
3364 	cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3365 	do {
3366 		int_status = readl(&ioc->chip->HostInterruptStatus);
3367 		if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
3368 			dhsprintk(ioc, pr_info(MPT3SAS_FMT
3369 				"%s: successful count(%d), timeout(%d)\n",
3370 				ioc->name, __func__, count, timeout));
3371 			return 0;
3372 		} else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3373 			doorbell = readl(&ioc->chip->Doorbell);
3374 			if ((doorbell & MPI2_IOC_STATE_MASK) ==
3375 			    MPI2_IOC_STATE_FAULT) {
3376 				mpt3sas_base_fault_info(ioc , doorbell);
3377 				return -EFAULT;
3378 			}
3379 		} else if (int_status == 0xFFFFFFFF)
3380 			goto out;
3381 
3382 		if (sleep_flag == CAN_SLEEP)
3383 			usleep_range(1000, 1500);
3384 		else
3385 			udelay(500);
3386 		count++;
3387 	} while (--cntdn);
3388 
3389  out:
3390 	pr_err(MPT3SAS_FMT
3391 	 "%s: failed due to timeout count(%d), int_status(%x)!\n",
3392 	 ioc->name, __func__, count, int_status);
3393 	return -EFAULT;
3394 }
3395 
3396 /**
3397  * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use
3398  * @ioc: per adapter object
3399  * @timeout: timeout in second
3400  * @sleep_flag: CAN_SLEEP or NO_SLEEP
3401  *
3402  * Returns 0 for success, non-zero for failure.
3403  *
3404  */
3405 static int
3406 _base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout,
3407 	int sleep_flag)
3408 {
3409 	u32 cntdn, count;
3410 	u32 doorbell_reg;
3411 
3412 	count = 0;
3413 	cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3414 	do {
3415 		doorbell_reg = readl(&ioc->chip->Doorbell);
3416 		if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
3417 			dhsprintk(ioc, pr_info(MPT3SAS_FMT
3418 				"%s: successful count(%d), timeout(%d)\n",
3419 				ioc->name, __func__, count, timeout));
3420 			return 0;
3421 		}
3422 		if (sleep_flag == CAN_SLEEP)
3423 			usleep_range(1000, 1500);
3424 		else
3425 			udelay(500);
3426 		count++;
3427 	} while (--cntdn);
3428 
3429 	pr_err(MPT3SAS_FMT
3430 		"%s: failed due to timeout count(%d), doorbell_reg(%x)!\n",
3431 		ioc->name, __func__, count, doorbell_reg);
3432 	return -EFAULT;
3433 }
3434 
3435 /**
3436  * _base_send_ioc_reset - send doorbell reset
3437  * @ioc: per adapter object
3438  * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
3439  * @timeout: timeout in second
3440  * @sleep_flag: CAN_SLEEP or NO_SLEEP
3441  *
3442  * Returns 0 for success, non-zero for failure.
3443  */
3444 static int
3445 _base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout,
3446 	int sleep_flag)
3447 {
3448 	u32 ioc_state;
3449 	int r = 0;
3450 
3451 	if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
3452 		pr_err(MPT3SAS_FMT "%s: unknown reset_type\n",
3453 		    ioc->name, __func__);
3454 		return -EFAULT;
3455 	}
3456 
3457 	if (!(ioc->facts.IOCCapabilities &
3458 	   MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
3459 		return -EFAULT;
3460 
3461 	pr_info(MPT3SAS_FMT "sending message unit reset !!\n", ioc->name);
3462 
3463 	writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
3464 	    &ioc->chip->Doorbell);
3465 	if ((_base_wait_for_doorbell_ack(ioc, 15, sleep_flag))) {
3466 		r = -EFAULT;
3467 		goto out;
3468 	}
3469 	ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY,
3470 	    timeout, sleep_flag);
3471 	if (ioc_state) {
3472 		pr_err(MPT3SAS_FMT
3473 			"%s: failed going to ready state (ioc_state=0x%x)\n",
3474 			ioc->name, __func__, ioc_state);
3475 		r = -EFAULT;
3476 		goto out;
3477 	}
3478  out:
3479 	pr_info(MPT3SAS_FMT "message unit reset: %s\n",
3480 	    ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
3481 	return r;
3482 }
3483 
3484 /**
3485  * _base_handshake_req_reply_wait - send request thru doorbell interface
3486  * @ioc: per adapter object
3487  * @request_bytes: request length
3488  * @request: pointer having request payload
3489  * @reply_bytes: reply length
3490  * @reply: pointer to reply payload
3491  * @timeout: timeout in second
3492  * @sleep_flag: CAN_SLEEP or NO_SLEEP
3493  *
3494  * Returns 0 for success, non-zero for failure.
3495  */
3496 static int
3497 _base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes,
3498 	u32 *request, int reply_bytes, u16 *reply, int timeout, int sleep_flag)
3499 {
3500 	MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
3501 	int i;
3502 	u8 failed;
3503 	u16 dummy;
3504 	__le32 *mfp;
3505 
3506 	/* make sure doorbell is not in use */
3507 	if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
3508 		pr_err(MPT3SAS_FMT
3509 			"doorbell is in use (line=%d)\n",
3510 			ioc->name, __LINE__);
3511 		return -EFAULT;
3512 	}
3513 
3514 	/* clear pending doorbell interrupts from previous state changes */
3515 	if (readl(&ioc->chip->HostInterruptStatus) &
3516 	    MPI2_HIS_IOC2SYS_DB_STATUS)
3517 		writel(0, &ioc->chip->HostInterruptStatus);
3518 
3519 	/* send message to ioc */
3520 	writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
3521 	    ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)),
3522 	    &ioc->chip->Doorbell);
3523 
3524 	if ((_base_wait_for_doorbell_int(ioc, 5, NO_SLEEP))) {
3525 		pr_err(MPT3SAS_FMT
3526 			"doorbell handshake int failed (line=%d)\n",
3527 			ioc->name, __LINE__);
3528 		return -EFAULT;
3529 	}
3530 	writel(0, &ioc->chip->HostInterruptStatus);
3531 
3532 	if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag))) {
3533 		pr_err(MPT3SAS_FMT
3534 			"doorbell handshake ack failed (line=%d)\n",
3535 			ioc->name, __LINE__);
3536 		return -EFAULT;
3537 	}
3538 
3539 	/* send message 32-bits at a time */
3540 	for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) {
3541 		writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
3542 		if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag)))
3543 			failed = 1;
3544 	}
3545 
3546 	if (failed) {
3547 		pr_err(MPT3SAS_FMT
3548 			"doorbell handshake sending request failed (line=%d)\n",
3549 			ioc->name, __LINE__);
3550 		return -EFAULT;
3551 	}
3552 
3553 	/* now wait for the reply */
3554 	if ((_base_wait_for_doorbell_int(ioc, timeout, sleep_flag))) {
3555 		pr_err(MPT3SAS_FMT
3556 			"doorbell handshake int failed (line=%d)\n",
3557 			ioc->name, __LINE__);
3558 		return -EFAULT;
3559 	}
3560 
3561 	/* read the first two 16-bits, it gives the total length of the reply */
3562 	reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3563 	    & MPI2_DOORBELL_DATA_MASK);
3564 	writel(0, &ioc->chip->HostInterruptStatus);
3565 	if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
3566 		pr_err(MPT3SAS_FMT
3567 			"doorbell handshake int failed (line=%d)\n",
3568 			ioc->name, __LINE__);
3569 		return -EFAULT;
3570 	}
3571 	reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3572 	    & MPI2_DOORBELL_DATA_MASK);
3573 	writel(0, &ioc->chip->HostInterruptStatus);
3574 
3575 	for (i = 2; i < default_reply->MsgLength * 2; i++)  {
3576 		if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
3577 			pr_err(MPT3SAS_FMT
3578 				"doorbell handshake int failed (line=%d)\n",
3579 				ioc->name, __LINE__);
3580 			return -EFAULT;
3581 		}
3582 		if (i >=  reply_bytes/2) /* overflow case */
3583 			dummy = readl(&ioc->chip->Doorbell);
3584 		else
3585 			reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3586 			    & MPI2_DOORBELL_DATA_MASK);
3587 		writel(0, &ioc->chip->HostInterruptStatus);
3588 	}
3589 
3590 	_base_wait_for_doorbell_int(ioc, 5, sleep_flag);
3591 	if (_base_wait_for_doorbell_not_used(ioc, 5, sleep_flag) != 0) {
3592 		dhsprintk(ioc, pr_info(MPT3SAS_FMT
3593 			"doorbell is in use (line=%d)\n", ioc->name, __LINE__));
3594 	}
3595 	writel(0, &ioc->chip->HostInterruptStatus);
3596 
3597 	if (ioc->logging_level & MPT_DEBUG_INIT) {
3598 		mfp = (__le32 *)reply;
3599 		pr_info("\toffset:data\n");
3600 		for (i = 0; i < reply_bytes/4; i++)
3601 			pr_info("\t[0x%02x]:%08x\n", i*4,
3602 			    le32_to_cpu(mfp[i]));
3603 	}
3604 	return 0;
3605 }
3606 
3607 /**
3608  * mpt3sas_base_sas_iounit_control - send sas iounit control to FW
3609  * @ioc: per adapter object
3610  * @mpi_reply: the reply payload from FW
3611  * @mpi_request: the request payload sent to FW
3612  *
3613  * The SAS IO Unit Control Request message allows the host to perform low-level
3614  * operations, such as resets on the PHYs of the IO Unit, also allows the host
3615  * to obtain the IOC assigned device handles for a device if it has other
3616  * identifying information about the device, in addition allows the host to
3617  * remove IOC resources associated with the device.
3618  *
3619  * Returns 0 for success, non-zero for failure.
3620  */
3621 int
3622 mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc,
3623 	Mpi2SasIoUnitControlReply_t *mpi_reply,
3624 	Mpi2SasIoUnitControlRequest_t *mpi_request)
3625 {
3626 	u16 smid;
3627 	u32 ioc_state;
3628 	unsigned long timeleft;
3629 	bool issue_reset = false;
3630 	int rc;
3631 	void *request;
3632 	u16 wait_state_count;
3633 
3634 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3635 	    __func__));
3636 
3637 	mutex_lock(&ioc->base_cmds.mutex);
3638 
3639 	if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
3640 		pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
3641 		    ioc->name, __func__);
3642 		rc = -EAGAIN;
3643 		goto out;
3644 	}
3645 
3646 	wait_state_count = 0;
3647 	ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
3648 	while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
3649 		if (wait_state_count++ == 10) {
3650 			pr_err(MPT3SAS_FMT
3651 			    "%s: failed due to ioc not operational\n",
3652 			    ioc->name, __func__);
3653 			rc = -EFAULT;
3654 			goto out;
3655 		}
3656 		ssleep(1);
3657 		ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
3658 		pr_info(MPT3SAS_FMT
3659 			"%s: waiting for operational state(count=%d)\n",
3660 			ioc->name, __func__, wait_state_count);
3661 	}
3662 
3663 	smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
3664 	if (!smid) {
3665 		pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
3666 		    ioc->name, __func__);
3667 		rc = -EAGAIN;
3668 		goto out;
3669 	}
3670 
3671 	rc = 0;
3672 	ioc->base_cmds.status = MPT3_CMD_PENDING;
3673 	request = mpt3sas_base_get_msg_frame(ioc, smid);
3674 	ioc->base_cmds.smid = smid;
3675 	memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t));
3676 	if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
3677 	    mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
3678 		ioc->ioc_link_reset_in_progress = 1;
3679 	init_completion(&ioc->base_cmds.done);
3680 	mpt3sas_base_put_smid_default(ioc, smid);
3681 	timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
3682 	    msecs_to_jiffies(10000));
3683 	if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
3684 	    mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) &&
3685 	    ioc->ioc_link_reset_in_progress)
3686 		ioc->ioc_link_reset_in_progress = 0;
3687 	if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
3688 		pr_err(MPT3SAS_FMT "%s: timeout\n",
3689 		    ioc->name, __func__);
3690 		_debug_dump_mf(mpi_request,
3691 		    sizeof(Mpi2SasIoUnitControlRequest_t)/4);
3692 		if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
3693 			issue_reset = true;
3694 		goto issue_host_reset;
3695 	}
3696 	if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
3697 		memcpy(mpi_reply, ioc->base_cmds.reply,
3698 		    sizeof(Mpi2SasIoUnitControlReply_t));
3699 	else
3700 		memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t));
3701 	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
3702 	goto out;
3703 
3704  issue_host_reset:
3705 	if (issue_reset)
3706 		mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
3707 		    FORCE_BIG_HAMMER);
3708 	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
3709 	rc = -EFAULT;
3710  out:
3711 	mutex_unlock(&ioc->base_cmds.mutex);
3712 	return rc;
3713 }
3714 
3715 /**
3716  * mpt3sas_base_scsi_enclosure_processor - sending request to sep device
3717  * @ioc: per adapter object
3718  * @mpi_reply: the reply payload from FW
3719  * @mpi_request: the request payload sent to FW
3720  *
3721  * The SCSI Enclosure Processor request message causes the IOC to
3722  * communicate with SES devices to control LED status signals.
3723  *
3724  * Returns 0 for success, non-zero for failure.
3725  */
3726 int
3727 mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc,
3728 	Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request)
3729 {
3730 	u16 smid;
3731 	u32 ioc_state;
3732 	unsigned long timeleft;
3733 	bool issue_reset = false;
3734 	int rc;
3735 	void *request;
3736 	u16 wait_state_count;
3737 
3738 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3739 	    __func__));
3740 
3741 	mutex_lock(&ioc->base_cmds.mutex);
3742 
3743 	if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
3744 		pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
3745 		    ioc->name, __func__);
3746 		rc = -EAGAIN;
3747 		goto out;
3748 	}
3749 
3750 	wait_state_count = 0;
3751 	ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
3752 	while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
3753 		if (wait_state_count++ == 10) {
3754 			pr_err(MPT3SAS_FMT
3755 			    "%s: failed due to ioc not operational\n",
3756 			    ioc->name, __func__);
3757 			rc = -EFAULT;
3758 			goto out;
3759 		}
3760 		ssleep(1);
3761 		ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
3762 		pr_info(MPT3SAS_FMT
3763 			"%s: waiting for operational state(count=%d)\n",
3764 			ioc->name,
3765 		    __func__, wait_state_count);
3766 	}
3767 
3768 	smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
3769 	if (!smid) {
3770 		pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
3771 		    ioc->name, __func__);
3772 		rc = -EAGAIN;
3773 		goto out;
3774 	}
3775 
3776 	rc = 0;
3777 	ioc->base_cmds.status = MPT3_CMD_PENDING;
3778 	request = mpt3sas_base_get_msg_frame(ioc, smid);
3779 	ioc->base_cmds.smid = smid;
3780 	memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
3781 	init_completion(&ioc->base_cmds.done);
3782 	mpt3sas_base_put_smid_default(ioc, smid);
3783 	timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
3784 	    msecs_to_jiffies(10000));
3785 	if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
3786 		pr_err(MPT3SAS_FMT "%s: timeout\n",
3787 		    ioc->name, __func__);
3788 		_debug_dump_mf(mpi_request,
3789 		    sizeof(Mpi2SepRequest_t)/4);
3790 		if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
3791 			issue_reset = false;
3792 		goto issue_host_reset;
3793 	}
3794 	if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
3795 		memcpy(mpi_reply, ioc->base_cmds.reply,
3796 		    sizeof(Mpi2SepReply_t));
3797 	else
3798 		memset(mpi_reply, 0, sizeof(Mpi2SepReply_t));
3799 	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
3800 	goto out;
3801 
3802  issue_host_reset:
3803 	if (issue_reset)
3804 		mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
3805 		    FORCE_BIG_HAMMER);
3806 	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
3807 	rc = -EFAULT;
3808  out:
3809 	mutex_unlock(&ioc->base_cmds.mutex);
3810 	return rc;
3811 }
3812 
3813 /**
3814  * _base_get_port_facts - obtain port facts reply and save in ioc
3815  * @ioc: per adapter object
3816  * @sleep_flag: CAN_SLEEP or NO_SLEEP
3817  *
3818  * Returns 0 for success, non-zero for failure.
3819  */
3820 static int
3821 _base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port, int sleep_flag)
3822 {
3823 	Mpi2PortFactsRequest_t mpi_request;
3824 	Mpi2PortFactsReply_t mpi_reply;
3825 	struct mpt3sas_port_facts *pfacts;
3826 	int mpi_reply_sz, mpi_request_sz, r;
3827 
3828 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3829 	    __func__));
3830 
3831 	mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
3832 	mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
3833 	memset(&mpi_request, 0, mpi_request_sz);
3834 	mpi_request.Function = MPI2_FUNCTION_PORT_FACTS;
3835 	mpi_request.PortNumber = port;
3836 	r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
3837 	    (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
3838 
3839 	if (r != 0) {
3840 		pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
3841 		    ioc->name, __func__, r);
3842 		return r;
3843 	}
3844 
3845 	pfacts = &ioc->pfacts[port];
3846 	memset(pfacts, 0, sizeof(struct mpt3sas_port_facts));
3847 	pfacts->PortNumber = mpi_reply.PortNumber;
3848 	pfacts->VP_ID = mpi_reply.VP_ID;
3849 	pfacts->VF_ID = mpi_reply.VF_ID;
3850 	pfacts->MaxPostedCmdBuffers =
3851 	    le16_to_cpu(mpi_reply.MaxPostedCmdBuffers);
3852 
3853 	return 0;
3854 }
3855 
3856 /**
3857  * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL
3858  * @ioc: per adapter object
3859  * @timeout:
3860  * @sleep_flag: CAN_SLEEP or NO_SLEEP
3861  *
3862  * Returns 0 for success, non-zero for failure.
3863  */
3864 static int
3865 _base_wait_for_iocstate(struct MPT3SAS_ADAPTER *ioc, int timeout,
3866 	int sleep_flag)
3867 {
3868 	u32 ioc_state;
3869 	int rc;
3870 
3871 	dinitprintk(ioc, printk(MPT3SAS_FMT "%s\n", ioc->name,
3872 	    __func__));
3873 
3874 	if (ioc->pci_error_recovery) {
3875 		dfailprintk(ioc, printk(MPT3SAS_FMT
3876 		    "%s: host in pci error recovery\n", ioc->name, __func__));
3877 		return -EFAULT;
3878 	}
3879 
3880 	ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
3881 	dhsprintk(ioc, printk(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
3882 	    ioc->name, __func__, ioc_state));
3883 
3884 	if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) ||
3885 	    (ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
3886 		return 0;
3887 
3888 	if (ioc_state & MPI2_DOORBELL_USED) {
3889 		dhsprintk(ioc, printk(MPT3SAS_FMT
3890 		    "unexpected doorbell active!\n", ioc->name));
3891 		goto issue_diag_reset;
3892 	}
3893 
3894 	if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
3895 		mpt3sas_base_fault_info(ioc, ioc_state &
3896 		    MPI2_DOORBELL_DATA_MASK);
3897 		goto issue_diag_reset;
3898 	}
3899 
3900 	ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY,
3901 	    timeout, sleep_flag);
3902 	if (ioc_state) {
3903 		dfailprintk(ioc, printk(MPT3SAS_FMT
3904 		    "%s: failed going to ready state (ioc_state=0x%x)\n",
3905 		    ioc->name, __func__, ioc_state));
3906 		return -EFAULT;
3907 	}
3908 
3909  issue_diag_reset:
3910 	rc = _base_diag_reset(ioc, sleep_flag);
3911 	return rc;
3912 }
3913 
3914 /**
3915  * _base_get_ioc_facts - obtain ioc facts reply and save in ioc
3916  * @ioc: per adapter object
3917  * @sleep_flag: CAN_SLEEP or NO_SLEEP
3918  *
3919  * Returns 0 for success, non-zero for failure.
3920  */
3921 static int
3922 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
3923 {
3924 	Mpi2IOCFactsRequest_t mpi_request;
3925 	Mpi2IOCFactsReply_t mpi_reply;
3926 	struct mpt3sas_facts *facts;
3927 	int mpi_reply_sz, mpi_request_sz, r;
3928 
3929 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3930 	    __func__));
3931 
3932 	r = _base_wait_for_iocstate(ioc, 10, sleep_flag);
3933 	if (r) {
3934 		dfailprintk(ioc, printk(MPT3SAS_FMT
3935 		    "%s: failed getting to correct state\n",
3936 		    ioc->name, __func__));
3937 		return r;
3938 	}
3939 	mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
3940 	mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t);
3941 	memset(&mpi_request, 0, mpi_request_sz);
3942 	mpi_request.Function = MPI2_FUNCTION_IOC_FACTS;
3943 	r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
3944 	    (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
3945 
3946 	if (r != 0) {
3947 		pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
3948 		    ioc->name, __func__, r);
3949 		return r;
3950 	}
3951 
3952 	facts = &ioc->facts;
3953 	memset(facts, 0, sizeof(struct mpt3sas_facts));
3954 	facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion);
3955 	facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion);
3956 	facts->VP_ID = mpi_reply.VP_ID;
3957 	facts->VF_ID = mpi_reply.VF_ID;
3958 	facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions);
3959 	facts->MaxChainDepth = mpi_reply.MaxChainDepth;
3960 	facts->WhoInit = mpi_reply.WhoInit;
3961 	facts->NumberOfPorts = mpi_reply.NumberOfPorts;
3962 	facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors;
3963 	facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);
3964 	facts->MaxReplyDescriptorPostQueueDepth =
3965 	    le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);
3966 	facts->ProductID = le16_to_cpu(mpi_reply.ProductID);
3967 	facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities);
3968 	if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID))
3969 		ioc->ir_firmware = 1;
3970 	if ((facts->IOCCapabilities &
3971 	      MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE))
3972 		ioc->rdpq_array_capable = 1;
3973 	facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
3974 	facts->IOCRequestFrameSize =
3975 	    le16_to_cpu(mpi_reply.IOCRequestFrameSize);
3976 	facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators);
3977 	facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets);
3978 	ioc->shost->max_id = -1;
3979 	facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders);
3980 	facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures);
3981 	facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags);
3982 	facts->HighPriorityCredit =
3983 	    le16_to_cpu(mpi_reply.HighPriorityCredit);
3984 	facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
3985 	facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
3986 
3987 	dinitprintk(ioc, pr_info(MPT3SAS_FMT
3988 		"hba queue depth(%d), max chains per io(%d)\n",
3989 		ioc->name, facts->RequestCredit,
3990 	    facts->MaxChainDepth));
3991 	dinitprintk(ioc, pr_info(MPT3SAS_FMT
3992 		"request frame size(%d), reply frame size(%d)\n", ioc->name,
3993 	    facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4));
3994 	return 0;
3995 }
3996 
3997 /**
3998  * _base_send_ioc_init - send ioc_init to firmware
3999  * @ioc: per adapter object
4000  * @sleep_flag: CAN_SLEEP or NO_SLEEP
4001  *
4002  * Returns 0 for success, non-zero for failure.
4003  */
4004 static int
4005 _base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4006 {
4007 	Mpi2IOCInitRequest_t mpi_request;
4008 	Mpi2IOCInitReply_t mpi_reply;
4009 	int i, r = 0;
4010 	struct timeval current_time;
4011 	u16 ioc_status;
4012 	u32 reply_post_free_array_sz = 0;
4013 	Mpi2IOCInitRDPQArrayEntry *reply_post_free_array = NULL;
4014 	dma_addr_t reply_post_free_array_dma;
4015 
4016 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4017 	    __func__));
4018 
4019 	memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
4020 	mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
4021 	mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
4022 	mpi_request.VF_ID = 0; /* TODO */
4023 	mpi_request.VP_ID = 0;
4024 	mpi_request.MsgVersion = cpu_to_le16(MPI25_VERSION);
4025 	mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
4026 
4027 	if (_base_is_controller_msix_enabled(ioc))
4028 		mpi_request.HostMSIxVectors = ioc->reply_queue_count;
4029 	mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4);
4030 	mpi_request.ReplyDescriptorPostQueueDepth =
4031 	    cpu_to_le16(ioc->reply_post_queue_depth);
4032 	mpi_request.ReplyFreeQueueDepth =
4033 	    cpu_to_le16(ioc->reply_free_queue_depth);
4034 
4035 	mpi_request.SenseBufferAddressHigh =
4036 	    cpu_to_le32((u64)ioc->sense_dma >> 32);
4037 	mpi_request.SystemReplyAddressHigh =
4038 	    cpu_to_le32((u64)ioc->reply_dma >> 32);
4039 	mpi_request.SystemRequestFrameBaseAddress =
4040 	    cpu_to_le64((u64)ioc->request_dma);
4041 	mpi_request.ReplyFreeQueueAddress =
4042 	    cpu_to_le64((u64)ioc->reply_free_dma);
4043 
4044 	if (ioc->rdpq_array_enable) {
4045 		reply_post_free_array_sz = ioc->reply_queue_count *
4046 		    sizeof(Mpi2IOCInitRDPQArrayEntry);
4047 		reply_post_free_array = pci_alloc_consistent(ioc->pdev,
4048 			reply_post_free_array_sz, &reply_post_free_array_dma);
4049 		if (!reply_post_free_array) {
4050 			pr_err(MPT3SAS_FMT
4051 			"reply_post_free_array: pci_alloc_consistent failed\n",
4052 			ioc->name);
4053 			r = -ENOMEM;
4054 			goto out;
4055 		}
4056 		memset(reply_post_free_array, 0, reply_post_free_array_sz);
4057 		for (i = 0; i < ioc->reply_queue_count; i++)
4058 			reply_post_free_array[i].RDPQBaseAddress =
4059 			    cpu_to_le64(
4060 				(u64)ioc->reply_post[i].reply_post_free_dma);
4061 		mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE;
4062 		mpi_request.ReplyDescriptorPostQueueAddress =
4063 		    cpu_to_le64((u64)reply_post_free_array_dma);
4064 	} else {
4065 		mpi_request.ReplyDescriptorPostQueueAddress =
4066 		    cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma);
4067 	}
4068 
4069 	/* This time stamp specifies number of milliseconds
4070 	 * since epoch ~ midnight January 1, 1970.
4071 	 */
4072 	do_gettimeofday(&current_time);
4073 	mpi_request.TimeStamp = cpu_to_le64((u64)current_time.tv_sec * 1000 +
4074 	    (current_time.tv_usec / 1000));
4075 
4076 	if (ioc->logging_level & MPT_DEBUG_INIT) {
4077 		__le32 *mfp;
4078 		int i;
4079 
4080 		mfp = (__le32 *)&mpi_request;
4081 		pr_info("\toffset:data\n");
4082 		for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
4083 			pr_info("\t[0x%02x]:%08x\n", i*4,
4084 			    le32_to_cpu(mfp[i]));
4085 	}
4086 
4087 	r = _base_handshake_req_reply_wait(ioc,
4088 	    sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request,
4089 	    sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10,
4090 	    sleep_flag);
4091 
4092 	if (r != 0) {
4093 		pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
4094 		    ioc->name, __func__, r);
4095 		goto out;
4096 	}
4097 
4098 	ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
4099 	if (ioc_status != MPI2_IOCSTATUS_SUCCESS ||
4100 	    mpi_reply.IOCLogInfo) {
4101 		pr_err(MPT3SAS_FMT "%s: failed\n", ioc->name, __func__);
4102 		r = -EIO;
4103 	}
4104 
4105 out:
4106 	if (reply_post_free_array)
4107 		pci_free_consistent(ioc->pdev, reply_post_free_array_sz,
4108 				    reply_post_free_array,
4109 				    reply_post_free_array_dma);
4110 	return r;
4111 }
4112 
4113 /**
4114  * mpt3sas_port_enable_done - command completion routine for port enable
4115  * @ioc: per adapter object
4116  * @smid: system request message index
4117  * @msix_index: MSIX table index supplied by the OS
4118  * @reply: reply message frame(lower 32bit addr)
4119  *
4120  * Return 1 meaning mf should be freed from _base_interrupt
4121  *        0 means the mf is freed from this function.
4122  */
4123 u8
4124 mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
4125 	u32 reply)
4126 {
4127 	MPI2DefaultReply_t *mpi_reply;
4128 	u16 ioc_status;
4129 
4130 	if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED)
4131 		return 1;
4132 
4133 	mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
4134 	if (!mpi_reply)
4135 		return 1;
4136 
4137 	if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE)
4138 		return 1;
4139 
4140 	ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING;
4141 	ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE;
4142 	ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID;
4143 	memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
4144 	ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
4145 	if (ioc_status != MPI2_IOCSTATUS_SUCCESS)
4146 		ioc->port_enable_failed = 1;
4147 
4148 	if (ioc->is_driver_loading) {
4149 		if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
4150 			mpt3sas_port_enable_complete(ioc);
4151 			return 1;
4152 		} else {
4153 			ioc->start_scan_failed = ioc_status;
4154 			ioc->start_scan = 0;
4155 			return 1;
4156 		}
4157 	}
4158 	complete(&ioc->port_enable_cmds.done);
4159 	return 1;
4160 }
4161 
4162 /**
4163  * _base_send_port_enable - send port_enable(discovery stuff) to firmware
4164  * @ioc: per adapter object
4165  * @sleep_flag: CAN_SLEEP or NO_SLEEP
4166  *
4167  * Returns 0 for success, non-zero for failure.
4168  */
4169 static int
4170 _base_send_port_enable(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4171 {
4172 	Mpi2PortEnableRequest_t *mpi_request;
4173 	Mpi2PortEnableReply_t *mpi_reply;
4174 	unsigned long timeleft;
4175 	int r = 0;
4176 	u16 smid;
4177 	u16 ioc_status;
4178 
4179 	pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
4180 
4181 	if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
4182 		pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4183 		    ioc->name, __func__);
4184 		return -EAGAIN;
4185 	}
4186 
4187 	smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
4188 	if (!smid) {
4189 		pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4190 		    ioc->name, __func__);
4191 		return -EAGAIN;
4192 	}
4193 
4194 	ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
4195 	mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4196 	ioc->port_enable_cmds.smid = smid;
4197 	memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
4198 	mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
4199 
4200 	init_completion(&ioc->port_enable_cmds.done);
4201 	mpt3sas_base_put_smid_default(ioc, smid);
4202 	timeleft = wait_for_completion_timeout(&ioc->port_enable_cmds.done,
4203 	    300*HZ);
4204 	if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) {
4205 		pr_err(MPT3SAS_FMT "%s: timeout\n",
4206 		    ioc->name, __func__);
4207 		_debug_dump_mf(mpi_request,
4208 		    sizeof(Mpi2PortEnableRequest_t)/4);
4209 		if (ioc->port_enable_cmds.status & MPT3_CMD_RESET)
4210 			r = -EFAULT;
4211 		else
4212 			r = -ETIME;
4213 		goto out;
4214 	}
4215 
4216 	mpi_reply = ioc->port_enable_cmds.reply;
4217 	ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
4218 	if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
4219 		pr_err(MPT3SAS_FMT "%s: failed with (ioc_status=0x%08x)\n",
4220 		    ioc->name, __func__, ioc_status);
4221 		r = -EFAULT;
4222 		goto out;
4223 	}
4224 
4225  out:
4226 	ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
4227 	pr_info(MPT3SAS_FMT "port enable: %s\n", ioc->name, ((r == 0) ?
4228 	    "SUCCESS" : "FAILED"));
4229 	return r;
4230 }
4231 
4232 /**
4233  * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply)
4234  * @ioc: per adapter object
4235  *
4236  * Returns 0 for success, non-zero for failure.
4237  */
4238 int
4239 mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc)
4240 {
4241 	Mpi2PortEnableRequest_t *mpi_request;
4242 	u16 smid;
4243 
4244 	pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
4245 
4246 	if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
4247 		pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4248 		    ioc->name, __func__);
4249 		return -EAGAIN;
4250 	}
4251 
4252 	smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
4253 	if (!smid) {
4254 		pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4255 		    ioc->name, __func__);
4256 		return -EAGAIN;
4257 	}
4258 
4259 	ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
4260 	mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4261 	ioc->port_enable_cmds.smid = smid;
4262 	memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
4263 	mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
4264 
4265 	mpt3sas_base_put_smid_default(ioc, smid);
4266 	return 0;
4267 }
4268 
4269 /**
4270  * _base_determine_wait_on_discovery - desposition
4271  * @ioc: per adapter object
4272  *
4273  * Decide whether to wait on discovery to complete. Used to either
4274  * locate boot device, or report volumes ahead of physical devices.
4275  *
4276  * Returns 1 for wait, 0 for don't wait
4277  */
4278 static int
4279 _base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc)
4280 {
4281 	/* We wait for discovery to complete if IR firmware is loaded.
4282 	 * The sas topology events arrive before PD events, so we need time to
4283 	 * turn on the bit in ioc->pd_handles to indicate PD
4284 	 * Also, it maybe required to report Volumes ahead of physical
4285 	 * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set.
4286 	 */
4287 	if (ioc->ir_firmware)
4288 		return 1;
4289 
4290 	/* if no Bios, then we don't need to wait */
4291 	if (!ioc->bios_pg3.BiosVersion)
4292 		return 0;
4293 
4294 	/* Bios is present, then we drop down here.
4295 	 *
4296 	 * If there any entries in the Bios Page 2, then we wait
4297 	 * for discovery to complete.
4298 	 */
4299 
4300 	/* Current Boot Device */
4301 	if ((ioc->bios_pg2.CurrentBootDeviceForm &
4302 	    MPI2_BIOSPAGE2_FORM_MASK) ==
4303 	    MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
4304 	/* Request Boot Device */
4305 	   (ioc->bios_pg2.ReqBootDeviceForm &
4306 	    MPI2_BIOSPAGE2_FORM_MASK) ==
4307 	    MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
4308 	/* Alternate Request Boot Device */
4309 	   (ioc->bios_pg2.ReqAltBootDeviceForm &
4310 	    MPI2_BIOSPAGE2_FORM_MASK) ==
4311 	    MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED)
4312 		return 0;
4313 
4314 	return 1;
4315 }
4316 
4317 /**
4318  * _base_unmask_events - turn on notification for this event
4319  * @ioc: per adapter object
4320  * @event: firmware event
4321  *
4322  * The mask is stored in ioc->event_masks.
4323  */
4324 static void
4325 _base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event)
4326 {
4327 	u32 desired_event;
4328 
4329 	if (event >= 128)
4330 		return;
4331 
4332 	desired_event = (1 << (event % 32));
4333 
4334 	if (event < 32)
4335 		ioc->event_masks[0] &= ~desired_event;
4336 	else if (event < 64)
4337 		ioc->event_masks[1] &= ~desired_event;
4338 	else if (event < 96)
4339 		ioc->event_masks[2] &= ~desired_event;
4340 	else if (event < 128)
4341 		ioc->event_masks[3] &= ~desired_event;
4342 }
4343 
4344 /**
4345  * _base_event_notification - send event notification
4346  * @ioc: per adapter object
4347  * @sleep_flag: CAN_SLEEP or NO_SLEEP
4348  *
4349  * Returns 0 for success, non-zero for failure.
4350  */
4351 static int
4352 _base_event_notification(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4353 {
4354 	Mpi2EventNotificationRequest_t *mpi_request;
4355 	unsigned long timeleft;
4356 	u16 smid;
4357 	int r = 0;
4358 	int i;
4359 
4360 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4361 	    __func__));
4362 
4363 	if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
4364 		pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4365 		    ioc->name, __func__);
4366 		return -EAGAIN;
4367 	}
4368 
4369 	smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4370 	if (!smid) {
4371 		pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4372 		    ioc->name, __func__);
4373 		return -EAGAIN;
4374 	}
4375 	ioc->base_cmds.status = MPT3_CMD_PENDING;
4376 	mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4377 	ioc->base_cmds.smid = smid;
4378 	memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t));
4379 	mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
4380 	mpi_request->VF_ID = 0; /* TODO */
4381 	mpi_request->VP_ID = 0;
4382 	for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4383 		mpi_request->EventMasks[i] =
4384 		    cpu_to_le32(ioc->event_masks[i]);
4385 	init_completion(&ioc->base_cmds.done);
4386 	mpt3sas_base_put_smid_default(ioc, smid);
4387 	timeleft = wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
4388 	if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4389 		pr_err(MPT3SAS_FMT "%s: timeout\n",
4390 		    ioc->name, __func__);
4391 		_debug_dump_mf(mpi_request,
4392 		    sizeof(Mpi2EventNotificationRequest_t)/4);
4393 		if (ioc->base_cmds.status & MPT3_CMD_RESET)
4394 			r = -EFAULT;
4395 		else
4396 			r = -ETIME;
4397 	} else
4398 		dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s: complete\n",
4399 		    ioc->name, __func__));
4400 	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4401 	return r;
4402 }
4403 
4404 /**
4405  * mpt3sas_base_validate_event_type - validating event types
4406  * @ioc: per adapter object
4407  * @event: firmware event
4408  *
4409  * This will turn on firmware event notification when application
4410  * ask for that event. We don't mask events that are already enabled.
4411  */
4412 void
4413 mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type)
4414 {
4415 	int i, j;
4416 	u32 event_mask, desired_event;
4417 	u8 send_update_to_fw;
4418 
4419 	for (i = 0, send_update_to_fw = 0; i <
4420 	    MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) {
4421 		event_mask = ~event_type[i];
4422 		desired_event = 1;
4423 		for (j = 0; j < 32; j++) {
4424 			if (!(event_mask & desired_event) &&
4425 			    (ioc->event_masks[i] & desired_event)) {
4426 				ioc->event_masks[i] &= ~desired_event;
4427 				send_update_to_fw = 1;
4428 			}
4429 			desired_event = (desired_event << 1);
4430 		}
4431 	}
4432 
4433 	if (!send_update_to_fw)
4434 		return;
4435 
4436 	mutex_lock(&ioc->base_cmds.mutex);
4437 	_base_event_notification(ioc, CAN_SLEEP);
4438 	mutex_unlock(&ioc->base_cmds.mutex);
4439 }
4440 
4441 /**
4442  * _base_diag_reset - the "big hammer" start of day reset
4443  * @ioc: per adapter object
4444  * @sleep_flag: CAN_SLEEP or NO_SLEEP
4445  *
4446  * Returns 0 for success, non-zero for failure.
4447  */
4448 static int
4449 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4450 {
4451 	u32 host_diagnostic;
4452 	u32 ioc_state;
4453 	u32 count;
4454 	u32 hcb_size;
4455 
4456 	pr_info(MPT3SAS_FMT "sending diag reset !!\n", ioc->name);
4457 
4458 	drsprintk(ioc, pr_info(MPT3SAS_FMT "clear interrupts\n",
4459 	    ioc->name));
4460 
4461 	count = 0;
4462 	do {
4463 		/* Write magic sequence to WriteSequence register
4464 		 * Loop until in diagnostic mode
4465 		 */
4466 		drsprintk(ioc, pr_info(MPT3SAS_FMT
4467 			"write magic sequence\n", ioc->name));
4468 		writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
4469 		writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
4470 		writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
4471 		writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
4472 		writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
4473 		writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
4474 		writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
4475 
4476 		/* wait 100 msec */
4477 		if (sleep_flag == CAN_SLEEP)
4478 			msleep(100);
4479 		else
4480 			mdelay(100);
4481 
4482 		if (count++ > 20)
4483 			goto out;
4484 
4485 		host_diagnostic = readl(&ioc->chip->HostDiagnostic);
4486 		drsprintk(ioc, pr_info(MPT3SAS_FMT
4487 			"wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
4488 		    ioc->name, count, host_diagnostic));
4489 
4490 	} while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
4491 
4492 	hcb_size = readl(&ioc->chip->HCBSize);
4493 
4494 	drsprintk(ioc, pr_info(MPT3SAS_FMT "diag reset: issued\n",
4495 	    ioc->name));
4496 	writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
4497 	     &ioc->chip->HostDiagnostic);
4498 
4499 	/*This delay allows the chip PCIe hardware time to finish reset tasks*/
4500 	if (sleep_flag == CAN_SLEEP)
4501 		msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
4502 	else
4503 		mdelay(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
4504 
4505 	/* Approximately 300 second max wait */
4506 	for (count = 0; count < (300000000 /
4507 		MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
4508 
4509 		host_diagnostic = readl(&ioc->chip->HostDiagnostic);
4510 
4511 		if (host_diagnostic == 0xFFFFFFFF)
4512 			goto out;
4513 		if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
4514 			break;
4515 
4516 		/* Wait to pass the second read delay window */
4517 		if (sleep_flag == CAN_SLEEP)
4518 			msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC
4519 								/ 1000);
4520 		else
4521 			mdelay(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC
4522 								/ 1000);
4523 	}
4524 
4525 	if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
4526 
4527 		drsprintk(ioc, pr_info(MPT3SAS_FMT
4528 		"restart the adapter assuming the HCB Address points to good F/W\n",
4529 		    ioc->name));
4530 		host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
4531 		host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
4532 		writel(host_diagnostic, &ioc->chip->HostDiagnostic);
4533 
4534 		drsprintk(ioc, pr_info(MPT3SAS_FMT
4535 		    "re-enable the HCDW\n", ioc->name));
4536 		writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
4537 		    &ioc->chip->HCBSize);
4538 	}
4539 
4540 	drsprintk(ioc, pr_info(MPT3SAS_FMT "restart the adapter\n",
4541 	    ioc->name));
4542 	writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
4543 	    &ioc->chip->HostDiagnostic);
4544 
4545 	drsprintk(ioc, pr_info(MPT3SAS_FMT
4546 		"disable writes to the diagnostic register\n", ioc->name));
4547 	writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
4548 
4549 	drsprintk(ioc, pr_info(MPT3SAS_FMT
4550 		"Wait for FW to go to the READY state\n", ioc->name));
4551 	ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20,
4552 	    sleep_flag);
4553 	if (ioc_state) {
4554 		pr_err(MPT3SAS_FMT
4555 			"%s: failed going to ready state (ioc_state=0x%x)\n",
4556 			ioc->name, __func__, ioc_state);
4557 		goto out;
4558 	}
4559 
4560 	pr_info(MPT3SAS_FMT "diag reset: SUCCESS\n", ioc->name);
4561 	return 0;
4562 
4563  out:
4564 	pr_err(MPT3SAS_FMT "diag reset: FAILED\n", ioc->name);
4565 	return -EFAULT;
4566 }
4567 
4568 /**
4569  * _base_make_ioc_ready - put controller in READY state
4570  * @ioc: per adapter object
4571  * @sleep_flag: CAN_SLEEP or NO_SLEEP
4572  * @type: FORCE_BIG_HAMMER or SOFT_RESET
4573  *
4574  * Returns 0 for success, non-zero for failure.
4575  */
4576 static int
4577 _base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, int sleep_flag,
4578 	enum reset_type type)
4579 {
4580 	u32 ioc_state;
4581 	int rc;
4582 	int count;
4583 
4584 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4585 	    __func__));
4586 
4587 	if (ioc->pci_error_recovery)
4588 		return 0;
4589 
4590 	ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4591 	dhsprintk(ioc, pr_info(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
4592 	    ioc->name, __func__, ioc_state));
4593 
4594 	/* if in RESET state, it should move to READY state shortly */
4595 	count = 0;
4596 	if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
4597 		while ((ioc_state & MPI2_IOC_STATE_MASK) !=
4598 		    MPI2_IOC_STATE_READY) {
4599 			if (count++ == 10) {
4600 				pr_err(MPT3SAS_FMT
4601 					"%s: failed going to ready state (ioc_state=0x%x)\n",
4602 				    ioc->name, __func__, ioc_state);
4603 				return -EFAULT;
4604 			}
4605 			if (sleep_flag == CAN_SLEEP)
4606 				ssleep(1);
4607 			else
4608 				mdelay(1000);
4609 			ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4610 		}
4611 	}
4612 
4613 	if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY)
4614 		return 0;
4615 
4616 	if (ioc_state & MPI2_DOORBELL_USED) {
4617 		dhsprintk(ioc, pr_info(MPT3SAS_FMT
4618 			"unexpected doorbell active!\n",
4619 			ioc->name));
4620 		goto issue_diag_reset;
4621 	}
4622 
4623 	if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
4624 		mpt3sas_base_fault_info(ioc, ioc_state &
4625 		    MPI2_DOORBELL_DATA_MASK);
4626 		goto issue_diag_reset;
4627 	}
4628 
4629 	if (type == FORCE_BIG_HAMMER)
4630 		goto issue_diag_reset;
4631 
4632 	if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
4633 		if (!(_base_send_ioc_reset(ioc,
4634 		    MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15, CAN_SLEEP))) {
4635 			return 0;
4636 	}
4637 
4638  issue_diag_reset:
4639 	rc = _base_diag_reset(ioc, CAN_SLEEP);
4640 	return rc;
4641 }
4642 
4643 /**
4644  * _base_make_ioc_operational - put controller in OPERATIONAL state
4645  * @ioc: per adapter object
4646  * @sleep_flag: CAN_SLEEP or NO_SLEEP
4647  *
4648  * Returns 0 for success, non-zero for failure.
4649  */
4650 static int
4651 _base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4652 {
4653 	int r, i;
4654 	unsigned long	flags;
4655 	u32 reply_address;
4656 	u16 smid;
4657 	struct _tr_list *delayed_tr, *delayed_tr_next;
4658 	struct adapter_reply_queue *reply_q;
4659 	long reply_post_free;
4660 	u32 reply_post_free_sz, index = 0;
4661 
4662 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4663 	    __func__));
4664 
4665 	/* clean the delayed target reset list */
4666 	list_for_each_entry_safe(delayed_tr, delayed_tr_next,
4667 	    &ioc->delayed_tr_list, list) {
4668 		list_del(&delayed_tr->list);
4669 		kfree(delayed_tr);
4670 	}
4671 
4672 
4673 	list_for_each_entry_safe(delayed_tr, delayed_tr_next,
4674 	    &ioc->delayed_tr_volume_list, list) {
4675 		list_del(&delayed_tr->list);
4676 		kfree(delayed_tr);
4677 	}
4678 
4679 	/* initialize the scsi lookup free list */
4680 	spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
4681 	INIT_LIST_HEAD(&ioc->free_list);
4682 	smid = 1;
4683 	for (i = 0; i < ioc->scsiio_depth; i++, smid++) {
4684 		INIT_LIST_HEAD(&ioc->scsi_lookup[i].chain_list);
4685 		ioc->scsi_lookup[i].cb_idx = 0xFF;
4686 		ioc->scsi_lookup[i].smid = smid;
4687 		ioc->scsi_lookup[i].scmd = NULL;
4688 		list_add_tail(&ioc->scsi_lookup[i].tracker_list,
4689 		    &ioc->free_list);
4690 	}
4691 
4692 	/* hi-priority queue */
4693 	INIT_LIST_HEAD(&ioc->hpr_free_list);
4694 	smid = ioc->hi_priority_smid;
4695 	for (i = 0; i < ioc->hi_priority_depth; i++, smid++) {
4696 		ioc->hpr_lookup[i].cb_idx = 0xFF;
4697 		ioc->hpr_lookup[i].smid = smid;
4698 		list_add_tail(&ioc->hpr_lookup[i].tracker_list,
4699 		    &ioc->hpr_free_list);
4700 	}
4701 
4702 	/* internal queue */
4703 	INIT_LIST_HEAD(&ioc->internal_free_list);
4704 	smid = ioc->internal_smid;
4705 	for (i = 0; i < ioc->internal_depth; i++, smid++) {
4706 		ioc->internal_lookup[i].cb_idx = 0xFF;
4707 		ioc->internal_lookup[i].smid = smid;
4708 		list_add_tail(&ioc->internal_lookup[i].tracker_list,
4709 		    &ioc->internal_free_list);
4710 	}
4711 
4712 	/* chain pool */
4713 	INIT_LIST_HEAD(&ioc->free_chain_list);
4714 	for (i = 0; i < ioc->chain_depth; i++)
4715 		list_add_tail(&ioc->chain_lookup[i].tracker_list,
4716 		    &ioc->free_chain_list);
4717 
4718 	spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
4719 
4720 	/* initialize Reply Free Queue */
4721 	for (i = 0, reply_address = (u32)ioc->reply_dma ;
4722 	    i < ioc->reply_free_queue_depth ; i++, reply_address +=
4723 	    ioc->reply_sz)
4724 		ioc->reply_free[i] = cpu_to_le32(reply_address);
4725 
4726 	/* initialize reply queues */
4727 	if (ioc->is_driver_loading)
4728 		_base_assign_reply_queues(ioc);
4729 
4730 	/* initialize Reply Post Free Queue */
4731 	reply_post_free_sz = ioc->reply_post_queue_depth *
4732 	    sizeof(Mpi2DefaultReplyDescriptor_t);
4733 	reply_post_free = (long)ioc->reply_post[index].reply_post_free;
4734 	list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
4735 		reply_q->reply_post_host_index = 0;
4736 		reply_q->reply_post_free = (Mpi2ReplyDescriptorsUnion_t *)
4737 		    reply_post_free;
4738 		for (i = 0; i < ioc->reply_post_queue_depth; i++)
4739 			reply_q->reply_post_free[i].Words =
4740 			    cpu_to_le64(ULLONG_MAX);
4741 		if (!_base_is_controller_msix_enabled(ioc))
4742 			goto skip_init_reply_post_free_queue;
4743 		/*
4744 		 * If RDPQ is enabled, switch to the next allocation.
4745 		 * Otherwise advance within the contiguous region.
4746 		 */
4747 		if (ioc->rdpq_array_enable)
4748 			reply_post_free = (long)
4749 			    ioc->reply_post[++index].reply_post_free;
4750 		else
4751 			reply_post_free += reply_post_free_sz;
4752 	}
4753  skip_init_reply_post_free_queue:
4754 
4755 	r = _base_send_ioc_init(ioc, sleep_flag);
4756 	if (r)
4757 		return r;
4758 
4759 	/* initialize reply free host index */
4760 	ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
4761 	writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
4762 
4763 	/* initialize reply post host index */
4764 	list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
4765 		if (ioc->msix96_vector)
4766 			writel((reply_q->msix_index & 7)<<
4767 			   MPI2_RPHI_MSIX_INDEX_SHIFT,
4768 			   ioc->replyPostRegisterIndex[reply_q->msix_index/8]);
4769 		else
4770 			writel(reply_q->msix_index <<
4771 				MPI2_RPHI_MSIX_INDEX_SHIFT,
4772 				&ioc->chip->ReplyPostHostIndex);
4773 
4774 		if (!_base_is_controller_msix_enabled(ioc))
4775 			goto skip_init_reply_post_host_index;
4776 	}
4777 
4778  skip_init_reply_post_host_index:
4779 
4780 	_base_unmask_interrupts(ioc);
4781 	r = _base_event_notification(ioc, sleep_flag);
4782 	if (r)
4783 		return r;
4784 
4785 	if (sleep_flag == CAN_SLEEP)
4786 		_base_static_config_pages(ioc);
4787 
4788 
4789 	if (ioc->is_driver_loading) {
4790 		ioc->wait_for_discovery_to_complete =
4791 		    _base_determine_wait_on_discovery(ioc);
4792 
4793 		return r; /* scan_start and scan_finished support */
4794 	}
4795 
4796 	r = _base_send_port_enable(ioc, sleep_flag);
4797 	if (r)
4798 		return r;
4799 
4800 	return r;
4801 }
4802 
4803 /**
4804  * mpt3sas_base_free_resources - free resources controller resources
4805  * @ioc: per adapter object
4806  *
4807  * Return nothing.
4808  */
4809 void
4810 mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc)
4811 {
4812 	dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4813 	    __func__));
4814 
4815 	if (ioc->chip_phys && ioc->chip) {
4816 		_base_mask_interrupts(ioc);
4817 		ioc->shost_recovery = 1;
4818 		_base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
4819 		ioc->shost_recovery = 0;
4820 	}
4821 
4822 	mpt3sas_base_unmap_resources(ioc);
4823 	return;
4824 }
4825 
4826 /**
4827  * mpt3sas_base_attach - attach controller instance
4828  * @ioc: per adapter object
4829  *
4830  * Returns 0 for success, non-zero for failure.
4831  */
4832 int
4833 mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
4834 {
4835 	int r, i;
4836 	int cpu_id, last_cpu_id = 0;
4837 	u8 revision;
4838 
4839 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4840 	    __func__));
4841 
4842 	/* setup cpu_msix_table */
4843 	ioc->cpu_count = num_online_cpus();
4844 	for_each_online_cpu(cpu_id)
4845 		last_cpu_id = cpu_id;
4846 	ioc->cpu_msix_table_sz = last_cpu_id + 1;
4847 	ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL);
4848 	ioc->reply_queue_count = 1;
4849 	if (!ioc->cpu_msix_table) {
4850 		dfailprintk(ioc, pr_info(MPT3SAS_FMT
4851 			"allocation for cpu_msix_table failed!!!\n",
4852 			ioc->name));
4853 		r = -ENOMEM;
4854 		goto out_free_resources;
4855 	}
4856 
4857 	/* Check whether the controller revision is C0 or above.
4858 	 * only C0 and above revision controllers support 96 MSI-X vectors.
4859 	 */
4860 	revision = ioc->pdev->revision;
4861 
4862 	if ((ioc->pdev->device == MPI25_MFGPAGE_DEVID_SAS3004 ||
4863 	     ioc->pdev->device == MPI25_MFGPAGE_DEVID_SAS3008 ||
4864 	     ioc->pdev->device == MPI25_MFGPAGE_DEVID_SAS3108_1 ||
4865 	     ioc->pdev->device == MPI25_MFGPAGE_DEVID_SAS3108_2 ||
4866 	     ioc->pdev->device == MPI25_MFGPAGE_DEVID_SAS3108_5 ||
4867 	     ioc->pdev->device == MPI25_MFGPAGE_DEVID_SAS3108_6) &&
4868 	     (revision >= 0x02))
4869 		ioc->msix96_vector = 1;
4870 
4871 	ioc->rdpq_array_enable_assigned = 0;
4872 	ioc->dma_mask = 0;
4873 	r = mpt3sas_base_map_resources(ioc);
4874 	if (r)
4875 		goto out_free_resources;
4876 
4877 
4878 	pci_set_drvdata(ioc->pdev, ioc->shost);
4879 	r = _base_get_ioc_facts(ioc, CAN_SLEEP);
4880 	if (r)
4881 		goto out_free_resources;
4882 
4883 	/*
4884 	 * In SAS3.0,
4885 	 * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and
4886 	 * Target Status - all require the IEEE formated scatter gather
4887 	 * elements.
4888 	 */
4889 
4890 	ioc->build_sg_scmd = &_base_build_sg_scmd_ieee;
4891 	ioc->build_sg = &_base_build_sg_ieee;
4892 	ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee;
4893 	ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t);
4894 
4895 	/*
4896 	 * These function pointers for other requests that don't
4897 	 * the require IEEE scatter gather elements.
4898 	 *
4899 	 * For example Configuration Pages and SAS IOUNIT Control don't.
4900 	 */
4901 	ioc->build_sg_mpi = &_base_build_sg;
4902 	ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge;
4903 
4904 	r = _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
4905 	if (r)
4906 		goto out_free_resources;
4907 
4908 	ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts,
4909 	    sizeof(struct mpt3sas_port_facts), GFP_KERNEL);
4910 	if (!ioc->pfacts) {
4911 		r = -ENOMEM;
4912 		goto out_free_resources;
4913 	}
4914 
4915 	for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
4916 		r = _base_get_port_facts(ioc, i, CAN_SLEEP);
4917 		if (r)
4918 			goto out_free_resources;
4919 	}
4920 
4921 	r = _base_allocate_memory_pools(ioc, CAN_SLEEP);
4922 	if (r)
4923 		goto out_free_resources;
4924 
4925 	init_waitqueue_head(&ioc->reset_wq);
4926 
4927 	/* allocate memory pd handle bitmask list */
4928 	ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
4929 	if (ioc->facts.MaxDevHandle % 8)
4930 		ioc->pd_handles_sz++;
4931 	ioc->pd_handles = kzalloc(ioc->pd_handles_sz,
4932 	    GFP_KERNEL);
4933 	if (!ioc->pd_handles) {
4934 		r = -ENOMEM;
4935 		goto out_free_resources;
4936 	}
4937 	ioc->blocking_handles = kzalloc(ioc->pd_handles_sz,
4938 	    GFP_KERNEL);
4939 	if (!ioc->blocking_handles) {
4940 		r = -ENOMEM;
4941 		goto out_free_resources;
4942 	}
4943 
4944 	ioc->fwfault_debug = mpt3sas_fwfault_debug;
4945 
4946 	/* base internal command bits */
4947 	mutex_init(&ioc->base_cmds.mutex);
4948 	ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4949 	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4950 
4951 	/* port_enable command bits */
4952 	ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4953 	ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
4954 
4955 	/* transport internal command bits */
4956 	ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4957 	ioc->transport_cmds.status = MPT3_CMD_NOT_USED;
4958 	mutex_init(&ioc->transport_cmds.mutex);
4959 
4960 	/* scsih internal command bits */
4961 	ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4962 	ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
4963 	mutex_init(&ioc->scsih_cmds.mutex);
4964 
4965 	/* task management internal command bits */
4966 	ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4967 	ioc->tm_cmds.status = MPT3_CMD_NOT_USED;
4968 	mutex_init(&ioc->tm_cmds.mutex);
4969 
4970 	/* config page internal command bits */
4971 	ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4972 	ioc->config_cmds.status = MPT3_CMD_NOT_USED;
4973 	mutex_init(&ioc->config_cmds.mutex);
4974 
4975 	/* ctl module internal command bits */
4976 	ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4977 	ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
4978 	ioc->ctl_cmds.status = MPT3_CMD_NOT_USED;
4979 	mutex_init(&ioc->ctl_cmds.mutex);
4980 
4981 	if (!ioc->base_cmds.reply || !ioc->transport_cmds.reply ||
4982 	    !ioc->scsih_cmds.reply || !ioc->tm_cmds.reply ||
4983 	    !ioc->config_cmds.reply || !ioc->ctl_cmds.reply ||
4984 	    !ioc->ctl_cmds.sense) {
4985 		r = -ENOMEM;
4986 		goto out_free_resources;
4987 	}
4988 
4989 	for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4990 		ioc->event_masks[i] = -1;
4991 
4992 	/* here we enable the events we care about */
4993 	_base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY);
4994 	_base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE);
4995 	_base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
4996 	_base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE);
4997 	_base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE);
4998 	_base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST);
4999 	_base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME);
5000 	_base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK);
5001 	_base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS);
5002 	_base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED);
5003 	_base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD);
5004 
5005 	r = _base_make_ioc_operational(ioc, CAN_SLEEP);
5006 	if (r)
5007 		goto out_free_resources;
5008 
5009 	return 0;
5010 
5011  out_free_resources:
5012 
5013 	ioc->remove_host = 1;
5014 
5015 	mpt3sas_base_free_resources(ioc);
5016 	_base_release_memory_pools(ioc);
5017 	pci_set_drvdata(ioc->pdev, NULL);
5018 	kfree(ioc->cpu_msix_table);
5019 	kfree(ioc->pd_handles);
5020 	kfree(ioc->blocking_handles);
5021 	kfree(ioc->tm_cmds.reply);
5022 	kfree(ioc->transport_cmds.reply);
5023 	kfree(ioc->scsih_cmds.reply);
5024 	kfree(ioc->config_cmds.reply);
5025 	kfree(ioc->base_cmds.reply);
5026 	kfree(ioc->port_enable_cmds.reply);
5027 	kfree(ioc->ctl_cmds.reply);
5028 	kfree(ioc->ctl_cmds.sense);
5029 	kfree(ioc->pfacts);
5030 	ioc->ctl_cmds.reply = NULL;
5031 	ioc->base_cmds.reply = NULL;
5032 	ioc->tm_cmds.reply = NULL;
5033 	ioc->scsih_cmds.reply = NULL;
5034 	ioc->transport_cmds.reply = NULL;
5035 	ioc->config_cmds.reply = NULL;
5036 	ioc->pfacts = NULL;
5037 	return r;
5038 }
5039 
5040 
5041 /**
5042  * mpt3sas_base_detach - remove controller instance
5043  * @ioc: per adapter object
5044  *
5045  * Return nothing.
5046  */
5047 void
5048 mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc)
5049 {
5050 	dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5051 	    __func__));
5052 
5053 	mpt3sas_base_stop_watchdog(ioc);
5054 	mpt3sas_base_free_resources(ioc);
5055 	_base_release_memory_pools(ioc);
5056 	pci_set_drvdata(ioc->pdev, NULL);
5057 	kfree(ioc->cpu_msix_table);
5058 	kfree(ioc->pd_handles);
5059 	kfree(ioc->blocking_handles);
5060 	kfree(ioc->pfacts);
5061 	kfree(ioc->ctl_cmds.reply);
5062 	kfree(ioc->ctl_cmds.sense);
5063 	kfree(ioc->base_cmds.reply);
5064 	kfree(ioc->port_enable_cmds.reply);
5065 	kfree(ioc->tm_cmds.reply);
5066 	kfree(ioc->transport_cmds.reply);
5067 	kfree(ioc->scsih_cmds.reply);
5068 	kfree(ioc->config_cmds.reply);
5069 }
5070 
5071 /**
5072  * _base_reset_handler - reset callback handler (for base)
5073  * @ioc: per adapter object
5074  * @reset_phase: phase
5075  *
5076  * The handler for doing any required cleanup or initialization.
5077  *
5078  * The reset phase can be MPT3_IOC_PRE_RESET, MPT3_IOC_AFTER_RESET,
5079  * MPT3_IOC_DONE_RESET
5080  *
5081  * Return nothing.
5082  */
5083 static void
5084 _base_reset_handler(struct MPT3SAS_ADAPTER *ioc, int reset_phase)
5085 {
5086 	mpt3sas_scsih_reset_handler(ioc, reset_phase);
5087 	mpt3sas_ctl_reset_handler(ioc, reset_phase);
5088 	switch (reset_phase) {
5089 	case MPT3_IOC_PRE_RESET:
5090 		dtmprintk(ioc, pr_info(MPT3SAS_FMT
5091 		"%s: MPT3_IOC_PRE_RESET\n", ioc->name, __func__));
5092 		break;
5093 	case MPT3_IOC_AFTER_RESET:
5094 		dtmprintk(ioc, pr_info(MPT3SAS_FMT
5095 		"%s: MPT3_IOC_AFTER_RESET\n", ioc->name, __func__));
5096 		if (ioc->transport_cmds.status & MPT3_CMD_PENDING) {
5097 			ioc->transport_cmds.status |= MPT3_CMD_RESET;
5098 			mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid);
5099 			complete(&ioc->transport_cmds.done);
5100 		}
5101 		if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
5102 			ioc->base_cmds.status |= MPT3_CMD_RESET;
5103 			mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid);
5104 			complete(&ioc->base_cmds.done);
5105 		}
5106 		if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
5107 			ioc->port_enable_failed = 1;
5108 			ioc->port_enable_cmds.status |= MPT3_CMD_RESET;
5109 			mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid);
5110 			if (ioc->is_driver_loading) {
5111 				ioc->start_scan_failed =
5112 				    MPI2_IOCSTATUS_INTERNAL_ERROR;
5113 				ioc->start_scan = 0;
5114 				ioc->port_enable_cmds.status =
5115 				    MPT3_CMD_NOT_USED;
5116 			} else
5117 				complete(&ioc->port_enable_cmds.done);
5118 		}
5119 		if (ioc->config_cmds.status & MPT3_CMD_PENDING) {
5120 			ioc->config_cmds.status |= MPT3_CMD_RESET;
5121 			mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid);
5122 			ioc->config_cmds.smid = USHRT_MAX;
5123 			complete(&ioc->config_cmds.done);
5124 		}
5125 		break;
5126 	case MPT3_IOC_DONE_RESET:
5127 		dtmprintk(ioc, pr_info(MPT3SAS_FMT
5128 			"%s: MPT3_IOC_DONE_RESET\n", ioc->name, __func__));
5129 		break;
5130 	}
5131 }
5132 
5133 /**
5134  * _wait_for_commands_to_complete - reset controller
5135  * @ioc: Pointer to MPT_ADAPTER structure
5136  * @sleep_flag: CAN_SLEEP or NO_SLEEP
5137  *
5138  * This function waiting(3s) for all pending commands to complete
5139  * prior to putting controller in reset.
5140  */
5141 static void
5142 _wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
5143 {
5144 	u32 ioc_state;
5145 	unsigned long flags;
5146 	u16 i;
5147 
5148 	ioc->pending_io_count = 0;
5149 	if (sleep_flag != CAN_SLEEP)
5150 		return;
5151 
5152 	ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
5153 	if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL)
5154 		return;
5155 
5156 	/* pending command count */
5157 	spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
5158 	for (i = 0; i < ioc->scsiio_depth; i++)
5159 		if (ioc->scsi_lookup[i].cb_idx != 0xFF)
5160 			ioc->pending_io_count++;
5161 	spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
5162 
5163 	if (!ioc->pending_io_count)
5164 		return;
5165 
5166 	/* wait for pending commands to complete */
5167 	wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ);
5168 }
5169 
5170 /**
5171  * mpt3sas_base_hard_reset_handler - reset controller
5172  * @ioc: Pointer to MPT_ADAPTER structure
5173  * @sleep_flag: CAN_SLEEP or NO_SLEEP
5174  * @type: FORCE_BIG_HAMMER or SOFT_RESET
5175  *
5176  * Returns 0 for success, non-zero for failure.
5177  */
5178 int
5179 mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc, int sleep_flag,
5180 	enum reset_type type)
5181 {
5182 	int r;
5183 	unsigned long flags;
5184 	u32 ioc_state;
5185 	u8 is_fault = 0, is_trigger = 0;
5186 
5187 	dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: enter\n", ioc->name,
5188 	    __func__));
5189 
5190 	if (ioc->pci_error_recovery) {
5191 		pr_err(MPT3SAS_FMT "%s: pci error recovery reset\n",
5192 		    ioc->name, __func__);
5193 		r = 0;
5194 		goto out_unlocked;
5195 	}
5196 
5197 	if (mpt3sas_fwfault_debug)
5198 		mpt3sas_halt_firmware(ioc);
5199 
5200 	/* TODO - What we really should be doing is pulling
5201 	 * out all the code associated with NO_SLEEP; its never used.
5202 	 * That is legacy code from mpt fusion driver, ported over.
5203 	 * I will leave this BUG_ON here for now till its been resolved.
5204 	 */
5205 	BUG_ON(sleep_flag == NO_SLEEP);
5206 
5207 	/* wait for an active reset in progress to complete */
5208 	if (!mutex_trylock(&ioc->reset_in_progress_mutex)) {
5209 		do {
5210 			ssleep(1);
5211 		} while (ioc->shost_recovery == 1);
5212 		dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
5213 		    __func__));
5214 		return ioc->ioc_reset_in_progress_status;
5215 	}
5216 
5217 	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
5218 	ioc->shost_recovery = 1;
5219 	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
5220 
5221 	if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
5222 	    MPT3_DIAG_BUFFER_IS_REGISTERED) &&
5223 	    (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
5224 	    MPT3_DIAG_BUFFER_IS_RELEASED))) {
5225 		is_trigger = 1;
5226 		ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
5227 		if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
5228 			is_fault = 1;
5229 	}
5230 	_base_reset_handler(ioc, MPT3_IOC_PRE_RESET);
5231 	_wait_for_commands_to_complete(ioc, sleep_flag);
5232 	_base_mask_interrupts(ioc);
5233 	r = _base_make_ioc_ready(ioc, sleep_flag, type);
5234 	if (r)
5235 		goto out;
5236 	_base_reset_handler(ioc, MPT3_IOC_AFTER_RESET);
5237 
5238 	/* If this hard reset is called while port enable is active, then
5239 	 * there is no reason to call make_ioc_operational
5240 	 */
5241 	if (ioc->is_driver_loading && ioc->port_enable_failed) {
5242 		ioc->remove_host = 1;
5243 		r = -EFAULT;
5244 		goto out;
5245 	}
5246 	r = _base_get_ioc_facts(ioc, CAN_SLEEP);
5247 	if (r)
5248 		goto out;
5249 
5250 	if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable)
5251 		panic("%s: Issue occurred with flashing controller firmware."
5252 		      "Please reboot the system and ensure that the correct"
5253 		      " firmware version is running\n", ioc->name);
5254 
5255 	r = _base_make_ioc_operational(ioc, sleep_flag);
5256 	if (!r)
5257 		_base_reset_handler(ioc, MPT3_IOC_DONE_RESET);
5258 
5259  out:
5260 	dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: %s\n",
5261 	    ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED")));
5262 
5263 	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
5264 	ioc->ioc_reset_in_progress_status = r;
5265 	ioc->shost_recovery = 0;
5266 	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
5267 	ioc->ioc_reset_count++;
5268 	mutex_unlock(&ioc->reset_in_progress_mutex);
5269 
5270  out_unlocked:
5271 	if ((r == 0) && is_trigger) {
5272 		if (is_fault)
5273 			mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT);
5274 		else
5275 			mpt3sas_trigger_master(ioc,
5276 			    MASTER_TRIGGER_ADAPTER_RESET);
5277 	}
5278 	dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
5279 	    __func__));
5280 	return r;
5281 }
5282