1 /*
2  * This is the Fusion MPT base driver providing common API layer interface
3  * for access to MPT (Message Passing Technology) firmware.
4  *
5  * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c
6  * Copyright (C) 2012-2014  LSI Corporation
7  * Copyright (C) 2013-2014 Avago Technologies
8  *  (mailto: MPT-FusionLinux.pdl@avagotech.com)
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License
12  * as published by the Free Software Foundation; either version 2
13  * of the License, or (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * NO WARRANTY
21  * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
22  * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
23  * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
24  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
25  * solely responsible for determining the appropriateness of using and
26  * distributing the Program and assumes all risks associated with its
27  * exercise of rights under this Agreement, including but not limited to
28  * the risks and costs of program errors, damage to or loss of data,
29  * programs or equipment, and unavailability or interruption of operations.
30 
31  * DISCLAIMER OF LIABILITY
32  * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
33  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34  * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
35  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
36  * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
37  * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
38  * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
39 
40  * You should have received a copy of the GNU General Public License
41  * along with this program; if not, write to the Free Software
42  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301,
43  * USA.
44  */
45 
46 #include <linux/kernel.h>
47 #include <linux/module.h>
48 #include <linux/errno.h>
49 #include <linux/init.h>
50 #include <linux/slab.h>
51 #include <linux/types.h>
52 #include <linux/pci.h>
53 #include <linux/kdev_t.h>
54 #include <linux/blkdev.h>
55 #include <linux/delay.h>
56 #include <linux/interrupt.h>
57 #include <linux/dma-mapping.h>
58 #include <linux/io.h>
59 #include <linux/time.h>
60 #include <linux/ktime.h>
61 #include <linux/kthread.h>
62 #include <asm/page.h>        /* To get host page size per arch */
63 #include <linux/aer.h>
64 
65 
66 #include "mpt3sas_base.h"
67 
68 static MPT_CALLBACK	mpt_callbacks[MPT_MAX_CALLBACKS];
69 
70 
71 #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */
72 
73  /* maximum controller queue depth */
74 #define MAX_HBA_QUEUE_DEPTH	30000
75 #define MAX_CHAIN_DEPTH		100000
76 static int max_queue_depth = -1;
77 module_param(max_queue_depth, int, 0444);
78 MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
79 
80 static int max_sgl_entries = -1;
81 module_param(max_sgl_entries, int, 0444);
82 MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
83 
84 static int msix_disable = -1;
85 module_param(msix_disable, int, 0444);
86 MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
87 
88 static int smp_affinity_enable = 1;
89 module_param(smp_affinity_enable, int, 0444);
90 MODULE_PARM_DESC(smp_affinity_enable, "SMP affinity feature enable/disable Default: enable(1)");
91 
92 static int max_msix_vectors = -1;
93 module_param(max_msix_vectors, int, 0444);
94 MODULE_PARM_DESC(max_msix_vectors,
95 	" max msix vectors");
96 
97 static int irqpoll_weight = -1;
98 module_param(irqpoll_weight, int, 0444);
99 MODULE_PARM_DESC(irqpoll_weight,
100 	"irq poll weight (default= one fourth of HBA queue depth)");
101 
102 static int mpt3sas_fwfault_debug;
103 MODULE_PARM_DESC(mpt3sas_fwfault_debug,
104 	" enable detection of firmware fault and halt firmware - (default=0)");
105 
106 static int perf_mode = -1;
107 module_param(perf_mode, int, 0444);
108 MODULE_PARM_DESC(perf_mode,
109 	"Performance mode (only for Aero/Sea Generation), options:\n\t\t"
110 	"0 - balanced: high iops mode is enabled &\n\t\t"
111 	"interrupt coalescing is enabled only on high iops queues,\n\t\t"
112 	"1 - iops: high iops mode is disabled &\n\t\t"
113 	"interrupt coalescing is enabled on all queues,\n\t\t"
114 	"2 - latency: high iops mode is disabled &\n\t\t"
115 	"interrupt coalescing is enabled on all queues with timeout value 0xA,\n"
116 	"\t\tdefault - default perf_mode is 'balanced'"
117 	);
118 
119 static int poll_queues;
120 module_param(poll_queues, int, 0444);
121 MODULE_PARM_DESC(poll_queues, "Number of queues to be use for io_uring poll mode.\n\t\t"
122 	"This parameter is effective only if host_tagset_enable=1. &\n\t\t"
123 	"when poll_queues are enabled then &\n\t\t"
124 	"perf_mode is set to latency mode. &\n\t\t"
125 	);
126 
127 enum mpt3sas_perf_mode {
128 	MPT_PERF_MODE_DEFAULT	= -1,
129 	MPT_PERF_MODE_BALANCED	= 0,
130 	MPT_PERF_MODE_IOPS	= 1,
131 	MPT_PERF_MODE_LATENCY	= 2,
132 };
133 
134 static int
135 _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc,
136 		u32 ioc_state, int timeout);
137 static int
138 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc);
139 static void
140 _base_clear_outstanding_commands(struct MPT3SAS_ADAPTER *ioc);
141 
142 /**
143  * mpt3sas_base_check_cmd_timeout - Function
144  *		to check timeout and command termination due
145  *		to Host reset.
146  *
147  * @ioc:	per adapter object.
148  * @status:	Status of issued command.
149  * @mpi_request:mf request pointer.
150  * @sz:		size of buffer.
151  *
152  * Return: 1/0 Reset to be done or Not
153  */
154 u8
155 mpt3sas_base_check_cmd_timeout(struct MPT3SAS_ADAPTER *ioc,
156 		u8 status, void *mpi_request, int sz)
157 {
158 	u8 issue_reset = 0;
159 
160 	if (!(status & MPT3_CMD_RESET))
161 		issue_reset = 1;
162 
163 	ioc_err(ioc, "Command %s\n",
164 		issue_reset == 0 ? "terminated due to Host Reset" : "Timeout");
165 	_debug_dump_mf(mpi_request, sz);
166 
167 	return issue_reset;
168 }
169 
170 /**
171  * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug.
172  * @val: ?
173  * @kp: ?
174  *
175  * Return: ?
176  */
177 static int
178 _scsih_set_fwfault_debug(const char *val, const struct kernel_param *kp)
179 {
180 	int ret = param_set_int(val, kp);
181 	struct MPT3SAS_ADAPTER *ioc;
182 
183 	if (ret)
184 		return ret;
185 
186 	/* global ioc spinlock to protect controller list on list operations */
187 	pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug);
188 	spin_lock(&gioc_lock);
189 	list_for_each_entry(ioc, &mpt3sas_ioc_list, list)
190 		ioc->fwfault_debug = mpt3sas_fwfault_debug;
191 	spin_unlock(&gioc_lock);
192 	return 0;
193 }
194 module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug,
195 	param_get_int, &mpt3sas_fwfault_debug, 0644);
196 
197 /**
198  * _base_readl_aero - retry readl for max three times.
199  * @addr: MPT Fusion system interface register address
200  *
201  * Retry the readl() for max three times if it gets zero value
202  * while reading the system interface register.
203  */
204 static inline u32
205 _base_readl_aero(const volatile void __iomem *addr)
206 {
207 	u32 i = 0, ret_val;
208 
209 	do {
210 		ret_val = readl(addr);
211 		i++;
212 	} while (ret_val == 0 && i < 3);
213 
214 	return ret_val;
215 }
216 
217 static inline u32
218 _base_readl(const volatile void __iomem *addr)
219 {
220 	return readl(addr);
221 }
222 
223 /**
224  * _base_clone_reply_to_sys_mem - copies reply to reply free iomem
225  *				  in BAR0 space.
226  *
227  * @ioc: per adapter object
228  * @reply: reply message frame(lower 32bit addr)
229  * @index: System request message index.
230  */
231 static void
232 _base_clone_reply_to_sys_mem(struct MPT3SAS_ADAPTER *ioc, u32 reply,
233 		u32 index)
234 {
235 	/*
236 	 * 256 is offset within sys register.
237 	 * 256 offset MPI frame starts. Max MPI frame supported is 32.
238 	 * 32 * 128 = 4K. From here, Clone of reply free for mcpu starts
239 	 */
240 	u16 cmd_credit = ioc->facts.RequestCredit + 1;
241 	void __iomem *reply_free_iomem = (void __iomem *)ioc->chip +
242 			MPI_FRAME_START_OFFSET +
243 			(cmd_credit * ioc->request_sz) + (index * sizeof(u32));
244 
245 	writel(reply, reply_free_iomem);
246 }
247 
248 /**
249  * _base_clone_mpi_to_sys_mem - Writes/copies MPI frames
250  *				to system/BAR0 region.
251  *
252  * @dst_iomem: Pointer to the destination location in BAR0 space.
253  * @src: Pointer to the Source data.
254  * @size: Size of data to be copied.
255  */
256 static void
257 _base_clone_mpi_to_sys_mem(void *dst_iomem, void *src, u32 size)
258 {
259 	int i;
260 	u32 *src_virt_mem = (u32 *)src;
261 
262 	for (i = 0; i < size/4; i++)
263 		writel((u32)src_virt_mem[i],
264 				(void __iomem *)dst_iomem + (i * 4));
265 }
266 
267 /**
268  * _base_clone_to_sys_mem - Writes/copies data to system/BAR0 region
269  *
270  * @dst_iomem: Pointer to the destination location in BAR0 space.
271  * @src: Pointer to the Source data.
272  * @size: Size of data to be copied.
273  */
274 static void
275 _base_clone_to_sys_mem(void __iomem *dst_iomem, void *src, u32 size)
276 {
277 	int i;
278 	u32 *src_virt_mem = (u32 *)(src);
279 
280 	for (i = 0; i < size/4; i++)
281 		writel((u32)src_virt_mem[i],
282 			(void __iomem *)dst_iomem + (i * 4));
283 }
284 
285 /**
286  * _base_get_chain - Calculates and Returns virtual chain address
287  *			 for the provided smid in BAR0 space.
288  *
289  * @ioc: per adapter object
290  * @smid: system request message index
291  * @sge_chain_count: Scatter gather chain count.
292  *
293  * Return: the chain address.
294  */
295 static inline void __iomem*
296 _base_get_chain(struct MPT3SAS_ADAPTER *ioc, u16 smid,
297 		u8 sge_chain_count)
298 {
299 	void __iomem *base_chain, *chain_virt;
300 	u16 cmd_credit = ioc->facts.RequestCredit + 1;
301 
302 	base_chain  = (void __iomem *)ioc->chip + MPI_FRAME_START_OFFSET +
303 		(cmd_credit * ioc->request_sz) +
304 		REPLY_FREE_POOL_SIZE;
305 	chain_virt = base_chain + (smid * ioc->facts.MaxChainDepth *
306 			ioc->request_sz) + (sge_chain_count * ioc->request_sz);
307 	return chain_virt;
308 }
309 
310 /**
311  * _base_get_chain_phys - Calculates and Returns physical address
312  *			in BAR0 for scatter gather chains, for
313  *			the provided smid.
314  *
315  * @ioc: per adapter object
316  * @smid: system request message index
317  * @sge_chain_count: Scatter gather chain count.
318  *
319  * Return: Physical chain address.
320  */
321 static inline phys_addr_t
322 _base_get_chain_phys(struct MPT3SAS_ADAPTER *ioc, u16 smid,
323 		u8 sge_chain_count)
324 {
325 	phys_addr_t base_chain_phys, chain_phys;
326 	u16 cmd_credit = ioc->facts.RequestCredit + 1;
327 
328 	base_chain_phys  = ioc->chip_phys + MPI_FRAME_START_OFFSET +
329 		(cmd_credit * ioc->request_sz) +
330 		REPLY_FREE_POOL_SIZE;
331 	chain_phys = base_chain_phys + (smid * ioc->facts.MaxChainDepth *
332 			ioc->request_sz) + (sge_chain_count * ioc->request_sz);
333 	return chain_phys;
334 }
335 
336 /**
337  * _base_get_buffer_bar0 - Calculates and Returns BAR0 mapped Host
338  *			buffer address for the provided smid.
339  *			(Each smid can have 64K starts from 17024)
340  *
341  * @ioc: per adapter object
342  * @smid: system request message index
343  *
344  * Return: Pointer to buffer location in BAR0.
345  */
346 
347 static void __iomem *
348 _base_get_buffer_bar0(struct MPT3SAS_ADAPTER *ioc, u16 smid)
349 {
350 	u16 cmd_credit = ioc->facts.RequestCredit + 1;
351 	// Added extra 1 to reach end of chain.
352 	void __iomem *chain_end = _base_get_chain(ioc,
353 			cmd_credit + 1,
354 			ioc->facts.MaxChainDepth);
355 	return chain_end + (smid * 64 * 1024);
356 }
357 
358 /**
359  * _base_get_buffer_phys_bar0 - Calculates and Returns BAR0 mapped
360  *		Host buffer Physical address for the provided smid.
361  *		(Each smid can have 64K starts from 17024)
362  *
363  * @ioc: per adapter object
364  * @smid: system request message index
365  *
366  * Return: Pointer to buffer location in BAR0.
367  */
368 static phys_addr_t
369 _base_get_buffer_phys_bar0(struct MPT3SAS_ADAPTER *ioc, u16 smid)
370 {
371 	u16 cmd_credit = ioc->facts.RequestCredit + 1;
372 	phys_addr_t chain_end_phys = _base_get_chain_phys(ioc,
373 			cmd_credit + 1,
374 			ioc->facts.MaxChainDepth);
375 	return chain_end_phys + (smid * 64 * 1024);
376 }
377 
378 /**
379  * _base_get_chain_buffer_dma_to_chain_buffer - Iterates chain
380  *			lookup list and Provides chain_buffer
381  *			address for the matching dma address.
382  *			(Each smid can have 64K starts from 17024)
383  *
384  * @ioc: per adapter object
385  * @chain_buffer_dma: Chain buffer dma address.
386  *
387  * Return: Pointer to chain buffer. Or Null on Failure.
388  */
389 static void *
390 _base_get_chain_buffer_dma_to_chain_buffer(struct MPT3SAS_ADAPTER *ioc,
391 		dma_addr_t chain_buffer_dma)
392 {
393 	u16 index, j;
394 	struct chain_tracker *ct;
395 
396 	for (index = 0; index < ioc->scsiio_depth; index++) {
397 		for (j = 0; j < ioc->chains_needed_per_io; j++) {
398 			ct = &ioc->chain_lookup[index].chains_per_smid[j];
399 			if (ct && ct->chain_buffer_dma == chain_buffer_dma)
400 				return ct->chain_buffer;
401 		}
402 	}
403 	ioc_info(ioc, "Provided chain_buffer_dma address is not in the lookup list\n");
404 	return NULL;
405 }
406 
407 /**
408  * _clone_sg_entries -	MPI EP's scsiio and config requests
409  *			are handled here. Base function for
410  *			double buffering, before submitting
411  *			the requests.
412  *
413  * @ioc: per adapter object.
414  * @mpi_request: mf request pointer.
415  * @smid: system request message index.
416  */
417 static void _clone_sg_entries(struct MPT3SAS_ADAPTER *ioc,
418 		void *mpi_request, u16 smid)
419 {
420 	Mpi2SGESimple32_t *sgel, *sgel_next;
421 	u32  sgl_flags, sge_chain_count = 0;
422 	bool is_write = false;
423 	u16 i = 0;
424 	void __iomem *buffer_iomem;
425 	phys_addr_t buffer_iomem_phys;
426 	void __iomem *buff_ptr;
427 	phys_addr_t buff_ptr_phys;
428 	void __iomem *dst_chain_addr[MCPU_MAX_CHAINS_PER_IO];
429 	void *src_chain_addr[MCPU_MAX_CHAINS_PER_IO];
430 	phys_addr_t dst_addr_phys;
431 	MPI2RequestHeader_t *request_hdr;
432 	struct scsi_cmnd *scmd;
433 	struct scatterlist *sg_scmd = NULL;
434 	int is_scsiio_req = 0;
435 
436 	request_hdr = (MPI2RequestHeader_t *) mpi_request;
437 
438 	if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST) {
439 		Mpi25SCSIIORequest_t *scsiio_request =
440 			(Mpi25SCSIIORequest_t *)mpi_request;
441 		sgel = (Mpi2SGESimple32_t *) &scsiio_request->SGL;
442 		is_scsiio_req = 1;
443 	} else if (request_hdr->Function == MPI2_FUNCTION_CONFIG) {
444 		Mpi2ConfigRequest_t  *config_req =
445 			(Mpi2ConfigRequest_t *)mpi_request;
446 		sgel = (Mpi2SGESimple32_t *) &config_req->PageBufferSGE;
447 	} else
448 		return;
449 
450 	/* From smid we can get scsi_cmd, once we have sg_scmd,
451 	 * we just need to get sg_virt and sg_next to get virtual
452 	 * address associated with sgel->Address.
453 	 */
454 
455 	if (is_scsiio_req) {
456 		/* Get scsi_cmd using smid */
457 		scmd = mpt3sas_scsih_scsi_lookup_get(ioc, smid);
458 		if (scmd == NULL) {
459 			ioc_err(ioc, "scmd is NULL\n");
460 			return;
461 		}
462 
463 		/* Get sg_scmd from scmd provided */
464 		sg_scmd = scsi_sglist(scmd);
465 	}
466 
467 	/*
468 	 * 0 - 255	System register
469 	 * 256 - 4352	MPI Frame. (This is based on maxCredit 32)
470 	 * 4352 - 4864	Reply_free pool (512 byte is reserved
471 	 *		considering maxCredit 32. Reply need extra
472 	 *		room, for mCPU case kept four times of
473 	 *		maxCredit).
474 	 * 4864 - 17152	SGE chain element. (32cmd * 3 chain of
475 	 *		128 byte size = 12288)
476 	 * 17152 - x	Host buffer mapped with smid.
477 	 *		(Each smid can have 64K Max IO.)
478 	 * BAR0+Last 1K MSIX Addr and Data
479 	 * Total size in use 2113664 bytes of 4MB BAR0
480 	 */
481 
482 	buffer_iomem = _base_get_buffer_bar0(ioc, smid);
483 	buffer_iomem_phys = _base_get_buffer_phys_bar0(ioc, smid);
484 
485 	buff_ptr = buffer_iomem;
486 	buff_ptr_phys = buffer_iomem_phys;
487 	WARN_ON(buff_ptr_phys > U32_MAX);
488 
489 	if (le32_to_cpu(sgel->FlagsLength) &
490 			(MPI2_SGE_FLAGS_HOST_TO_IOC << MPI2_SGE_FLAGS_SHIFT))
491 		is_write = true;
492 
493 	for (i = 0; i < MPT_MIN_PHYS_SEGMENTS + ioc->facts.MaxChainDepth; i++) {
494 
495 		sgl_flags =
496 		    (le32_to_cpu(sgel->FlagsLength) >> MPI2_SGE_FLAGS_SHIFT);
497 
498 		switch (sgl_flags & MPI2_SGE_FLAGS_ELEMENT_MASK) {
499 		case MPI2_SGE_FLAGS_CHAIN_ELEMENT:
500 			/*
501 			 * Helper function which on passing
502 			 * chain_buffer_dma returns chain_buffer. Get
503 			 * the virtual address for sgel->Address
504 			 */
505 			sgel_next =
506 				_base_get_chain_buffer_dma_to_chain_buffer(ioc,
507 						le32_to_cpu(sgel->Address));
508 			if (sgel_next == NULL)
509 				return;
510 			/*
511 			 * This is coping 128 byte chain
512 			 * frame (not a host buffer)
513 			 */
514 			dst_chain_addr[sge_chain_count] =
515 				_base_get_chain(ioc,
516 					smid, sge_chain_count);
517 			src_chain_addr[sge_chain_count] =
518 						(void *) sgel_next;
519 			dst_addr_phys = _base_get_chain_phys(ioc,
520 						smid, sge_chain_count);
521 			WARN_ON(dst_addr_phys > U32_MAX);
522 			sgel->Address =
523 				cpu_to_le32(lower_32_bits(dst_addr_phys));
524 			sgel = sgel_next;
525 			sge_chain_count++;
526 			break;
527 		case MPI2_SGE_FLAGS_SIMPLE_ELEMENT:
528 			if (is_write) {
529 				if (is_scsiio_req) {
530 					_base_clone_to_sys_mem(buff_ptr,
531 					    sg_virt(sg_scmd),
532 					    (le32_to_cpu(sgel->FlagsLength) &
533 					    0x00ffffff));
534 					/*
535 					 * FIXME: this relies on a a zero
536 					 * PCI mem_offset.
537 					 */
538 					sgel->Address =
539 					    cpu_to_le32((u32)buff_ptr_phys);
540 				} else {
541 					_base_clone_to_sys_mem(buff_ptr,
542 					    ioc->config_vaddr,
543 					    (le32_to_cpu(sgel->FlagsLength) &
544 					    0x00ffffff));
545 					sgel->Address =
546 					    cpu_to_le32((u32)buff_ptr_phys);
547 				}
548 			}
549 			buff_ptr += (le32_to_cpu(sgel->FlagsLength) &
550 			    0x00ffffff);
551 			buff_ptr_phys += (le32_to_cpu(sgel->FlagsLength) &
552 			    0x00ffffff);
553 			if ((le32_to_cpu(sgel->FlagsLength) &
554 			    (MPI2_SGE_FLAGS_END_OF_BUFFER
555 					<< MPI2_SGE_FLAGS_SHIFT)))
556 				goto eob_clone_chain;
557 			else {
558 				/*
559 				 * Every single element in MPT will have
560 				 * associated sg_next. Better to sanity that
561 				 * sg_next is not NULL, but it will be a bug
562 				 * if it is null.
563 				 */
564 				if (is_scsiio_req) {
565 					sg_scmd = sg_next(sg_scmd);
566 					if (sg_scmd)
567 						sgel++;
568 					else
569 						goto eob_clone_chain;
570 				}
571 			}
572 			break;
573 		}
574 	}
575 
576 eob_clone_chain:
577 	for (i = 0; i < sge_chain_count; i++) {
578 		if (is_scsiio_req)
579 			_base_clone_to_sys_mem(dst_chain_addr[i],
580 				src_chain_addr[i], ioc->request_sz);
581 	}
582 }
583 
584 /**
585  *  mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc
586  * @arg: input argument, used to derive ioc
587  *
588  * Return:
589  * 0 if controller is removed from pci subsystem.
590  * -1 for other case.
591  */
592 static int mpt3sas_remove_dead_ioc_func(void *arg)
593 {
594 	struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg;
595 	struct pci_dev *pdev;
596 
597 	if (!ioc)
598 		return -1;
599 
600 	pdev = ioc->pdev;
601 	if (!pdev)
602 		return -1;
603 	pci_stop_and_remove_bus_device_locked(pdev);
604 	return 0;
605 }
606 
607 /**
608  * _base_sync_drv_fw_timestamp - Sync Drive-Fw TimeStamp.
609  * @ioc: Per Adapter Object
610  *
611  * Return: nothing.
612  */
613 static void _base_sync_drv_fw_timestamp(struct MPT3SAS_ADAPTER *ioc)
614 {
615 	Mpi26IoUnitControlRequest_t *mpi_request;
616 	Mpi26IoUnitControlReply_t *mpi_reply;
617 	u16 smid;
618 	ktime_t current_time;
619 	u64 TimeStamp = 0;
620 	u8 issue_reset = 0;
621 
622 	mutex_lock(&ioc->scsih_cmds.mutex);
623 	if (ioc->scsih_cmds.status != MPT3_CMD_NOT_USED) {
624 		ioc_err(ioc, "scsih_cmd in use %s\n", __func__);
625 		goto out;
626 	}
627 	ioc->scsih_cmds.status = MPT3_CMD_PENDING;
628 	smid = mpt3sas_base_get_smid(ioc, ioc->scsih_cb_idx);
629 	if (!smid) {
630 		ioc_err(ioc, "Failed obtaining a smid %s\n", __func__);
631 		ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
632 		goto out;
633 	}
634 	mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
635 	ioc->scsih_cmds.smid = smid;
636 	memset(mpi_request, 0, sizeof(Mpi26IoUnitControlRequest_t));
637 	mpi_request->Function = MPI2_FUNCTION_IO_UNIT_CONTROL;
638 	mpi_request->Operation = MPI26_CTRL_OP_SET_IOC_PARAMETER;
639 	mpi_request->IOCParameter = MPI26_SET_IOC_PARAMETER_SYNC_TIMESTAMP;
640 	current_time = ktime_get_real();
641 	TimeStamp = ktime_to_ms(current_time);
642 	mpi_request->Reserved7 = cpu_to_le32(TimeStamp >> 32);
643 	mpi_request->IOCParameterValue = cpu_to_le32(TimeStamp & 0xFFFFFFFF);
644 	init_completion(&ioc->scsih_cmds.done);
645 	ioc->put_smid_default(ioc, smid);
646 	dinitprintk(ioc, ioc_info(ioc,
647 	    "Io Unit Control Sync TimeStamp (sending), @time %lld ms\n",
648 	    TimeStamp));
649 	wait_for_completion_timeout(&ioc->scsih_cmds.done,
650 		MPT3SAS_TIMESYNC_TIMEOUT_SECONDS*HZ);
651 	if (!(ioc->scsih_cmds.status & MPT3_CMD_COMPLETE)) {
652 		mpt3sas_check_cmd_timeout(ioc,
653 		    ioc->scsih_cmds.status, mpi_request,
654 		    sizeof(Mpi2SasIoUnitControlRequest_t)/4, issue_reset);
655 		goto issue_host_reset;
656 	}
657 	if (ioc->scsih_cmds.status & MPT3_CMD_REPLY_VALID) {
658 		mpi_reply = ioc->scsih_cmds.reply;
659 		dinitprintk(ioc, ioc_info(ioc,
660 		    "Io Unit Control sync timestamp (complete): ioc_status(0x%04x), loginfo(0x%08x)\n",
661 		    le16_to_cpu(mpi_reply->IOCStatus),
662 		    le32_to_cpu(mpi_reply->IOCLogInfo)));
663 	}
664 issue_host_reset:
665 	if (issue_reset)
666 		mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
667 	ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
668 out:
669 	mutex_unlock(&ioc->scsih_cmds.mutex);
670 }
671 
672 /**
673  * _base_fault_reset_work - workq handling ioc fault conditions
674  * @work: input argument, used to derive ioc
675  *
676  * Context: sleep.
677  */
678 static void
679 _base_fault_reset_work(struct work_struct *work)
680 {
681 	struct MPT3SAS_ADAPTER *ioc =
682 	    container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work);
683 	unsigned long	 flags;
684 	u32 doorbell;
685 	int rc;
686 	struct task_struct *p;
687 
688 
689 	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
690 	if ((ioc->shost_recovery && (ioc->ioc_coredump_loop == 0)) ||
691 			ioc->pci_error_recovery)
692 		goto rearm_timer;
693 	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
694 
695 	doorbell = mpt3sas_base_get_iocstate(ioc, 0);
696 	if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) {
697 		ioc_err(ioc, "SAS host is non-operational !!!!\n");
698 
699 		/* It may be possible that EEH recovery can resolve some of
700 		 * pci bus failure issues rather removing the dead ioc function
701 		 * by considering controller is in a non-operational state. So
702 		 * here priority is given to the EEH recovery. If it doesn't
703 		 * not resolve this issue, mpt3sas driver will consider this
704 		 * controller to non-operational state and remove the dead ioc
705 		 * function.
706 		 */
707 		if (ioc->non_operational_loop++ < 5) {
708 			spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock,
709 							 flags);
710 			goto rearm_timer;
711 		}
712 
713 		/*
714 		 * Call _scsih_flush_pending_cmds callback so that we flush all
715 		 * pending commands back to OS. This call is required to avoid
716 		 * deadlock at block layer. Dead IOC will fail to do diag reset,
717 		 * and this call is safe since dead ioc will never return any
718 		 * command back from HW.
719 		 */
720 		mpt3sas_base_pause_mq_polling(ioc);
721 		ioc->schedule_dead_ioc_flush_running_cmds(ioc);
722 		/*
723 		 * Set remove_host flag early since kernel thread will
724 		 * take some time to execute.
725 		 */
726 		ioc->remove_host = 1;
727 		/*Remove the Dead Host */
728 		p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc,
729 		    "%s_dead_ioc_%d", ioc->driver_name, ioc->id);
730 		if (IS_ERR(p))
731 			ioc_err(ioc, "%s: Running mpt3sas_dead_ioc thread failed !!!!\n",
732 				__func__);
733 		else
734 			ioc_err(ioc, "%s: Running mpt3sas_dead_ioc thread success !!!!\n",
735 				__func__);
736 		return; /* don't rearm timer */
737 	}
738 
739 	if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_COREDUMP) {
740 		u8 timeout = (ioc->manu_pg11.CoreDumpTOSec) ?
741 		    ioc->manu_pg11.CoreDumpTOSec :
742 		    MPT3SAS_DEFAULT_COREDUMP_TIMEOUT_SECONDS;
743 
744 		timeout /= (FAULT_POLLING_INTERVAL/1000);
745 
746 		if (ioc->ioc_coredump_loop == 0) {
747 			mpt3sas_print_coredump_info(ioc,
748 			    doorbell & MPI2_DOORBELL_DATA_MASK);
749 			/* do not accept any IOs and disable the interrupts */
750 			spin_lock_irqsave(
751 			    &ioc->ioc_reset_in_progress_lock, flags);
752 			ioc->shost_recovery = 1;
753 			spin_unlock_irqrestore(
754 			    &ioc->ioc_reset_in_progress_lock, flags);
755 			mpt3sas_base_mask_interrupts(ioc);
756 			mpt3sas_base_pause_mq_polling(ioc);
757 			_base_clear_outstanding_commands(ioc);
758 		}
759 
760 		ioc_info(ioc, "%s: CoreDump loop %d.",
761 		    __func__, ioc->ioc_coredump_loop);
762 
763 		/* Wait until CoreDump completes or times out */
764 		if (ioc->ioc_coredump_loop++ < timeout) {
765 			spin_lock_irqsave(
766 			    &ioc->ioc_reset_in_progress_lock, flags);
767 			goto rearm_timer;
768 		}
769 	}
770 
771 	if (ioc->ioc_coredump_loop) {
772 		if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_COREDUMP)
773 			ioc_err(ioc, "%s: CoreDump completed. LoopCount: %d",
774 			    __func__, ioc->ioc_coredump_loop);
775 		else
776 			ioc_err(ioc, "%s: CoreDump Timed out. LoopCount: %d",
777 			    __func__, ioc->ioc_coredump_loop);
778 		ioc->ioc_coredump_loop = MPT3SAS_COREDUMP_LOOP_DONE;
779 	}
780 	ioc->non_operational_loop = 0;
781 	if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) {
782 		rc = mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
783 		ioc_warn(ioc, "%s: hard reset: %s\n",
784 			 __func__, rc == 0 ? "success" : "failed");
785 		doorbell = mpt3sas_base_get_iocstate(ioc, 0);
786 		if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
787 			mpt3sas_print_fault_code(ioc, doorbell &
788 			    MPI2_DOORBELL_DATA_MASK);
789 		} else if ((doorbell & MPI2_IOC_STATE_MASK) ==
790 		    MPI2_IOC_STATE_COREDUMP)
791 			mpt3sas_print_coredump_info(ioc, doorbell &
792 			    MPI2_DOORBELL_DATA_MASK);
793 		if (rc && (doorbell & MPI2_IOC_STATE_MASK) !=
794 		    MPI2_IOC_STATE_OPERATIONAL)
795 			return; /* don't rearm timer */
796 	}
797 	ioc->ioc_coredump_loop = 0;
798 	if (ioc->time_sync_interval &&
799 	    ++ioc->timestamp_update_count >= ioc->time_sync_interval) {
800 		ioc->timestamp_update_count = 0;
801 		_base_sync_drv_fw_timestamp(ioc);
802 	}
803 	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
804  rearm_timer:
805 	if (ioc->fault_reset_work_q)
806 		queue_delayed_work(ioc->fault_reset_work_q,
807 		    &ioc->fault_reset_work,
808 		    msecs_to_jiffies(FAULT_POLLING_INTERVAL));
809 	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
810 }
811 
812 /**
813  * mpt3sas_base_start_watchdog - start the fault_reset_work_q
814  * @ioc: per adapter object
815  *
816  * Context: sleep.
817  */
818 void
819 mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc)
820 {
821 	unsigned long	 flags;
822 
823 	if (ioc->fault_reset_work_q)
824 		return;
825 
826 	ioc->timestamp_update_count = 0;
827 	/* initialize fault polling */
828 
829 	INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
830 	snprintf(ioc->fault_reset_work_q_name,
831 	    sizeof(ioc->fault_reset_work_q_name), "poll_%s%d_status",
832 	    ioc->driver_name, ioc->id);
833 	ioc->fault_reset_work_q =
834 		create_singlethread_workqueue(ioc->fault_reset_work_q_name);
835 	if (!ioc->fault_reset_work_q) {
836 		ioc_err(ioc, "%s: failed (line=%d)\n", __func__, __LINE__);
837 		return;
838 	}
839 	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
840 	if (ioc->fault_reset_work_q)
841 		queue_delayed_work(ioc->fault_reset_work_q,
842 		    &ioc->fault_reset_work,
843 		    msecs_to_jiffies(FAULT_POLLING_INTERVAL));
844 	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
845 }
846 
847 /**
848  * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q
849  * @ioc: per adapter object
850  *
851  * Context: sleep.
852  */
853 void
854 mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc)
855 {
856 	unsigned long flags;
857 	struct workqueue_struct *wq;
858 
859 	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
860 	wq = ioc->fault_reset_work_q;
861 	ioc->fault_reset_work_q = NULL;
862 	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
863 	if (wq) {
864 		if (!cancel_delayed_work_sync(&ioc->fault_reset_work))
865 			flush_workqueue(wq);
866 		destroy_workqueue(wq);
867 	}
868 }
869 
870 /**
871  * mpt3sas_base_fault_info - verbose translation of firmware FAULT code
872  * @ioc: per adapter object
873  * @fault_code: fault code
874  */
875 void
876 mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc, u16 fault_code)
877 {
878 	ioc_err(ioc, "fault_state(0x%04x)!\n", fault_code);
879 }
880 
881 /**
882  * mpt3sas_base_coredump_info - verbose translation of firmware CoreDump state
883  * @ioc: per adapter object
884  * @fault_code: fault code
885  *
886  * Return: nothing.
887  */
888 void
889 mpt3sas_base_coredump_info(struct MPT3SAS_ADAPTER *ioc, u16 fault_code)
890 {
891 	ioc_err(ioc, "coredump_state(0x%04x)!\n", fault_code);
892 }
893 
894 /**
895  * mpt3sas_base_wait_for_coredump_completion - Wait until coredump
896  * completes or times out
897  * @ioc: per adapter object
898  * @caller: caller function name
899  *
900  * Return: 0 for success, non-zero for failure.
901  */
902 int
903 mpt3sas_base_wait_for_coredump_completion(struct MPT3SAS_ADAPTER *ioc,
904 		const char *caller)
905 {
906 	u8 timeout = (ioc->manu_pg11.CoreDumpTOSec) ?
907 			ioc->manu_pg11.CoreDumpTOSec :
908 			MPT3SAS_DEFAULT_COREDUMP_TIMEOUT_SECONDS;
909 
910 	int ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_FAULT,
911 					timeout);
912 
913 	if (ioc_state)
914 		ioc_err(ioc,
915 		    "%s: CoreDump timed out. (ioc_state=0x%x)\n",
916 		    caller, ioc_state);
917 	else
918 		ioc_info(ioc,
919 		    "%s: CoreDump completed. (ioc_state=0x%x)\n",
920 		    caller, ioc_state);
921 
922 	return ioc_state;
923 }
924 
925 /**
926  * mpt3sas_halt_firmware - halt's mpt controller firmware
927  * @ioc: per adapter object
928  *
929  * For debugging timeout related issues.  Writing 0xCOFFEE00
930  * to the doorbell register will halt controller firmware. With
931  * the purpose to stop both driver and firmware, the enduser can
932  * obtain a ring buffer from controller UART.
933  */
934 void
935 mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc)
936 {
937 	u32 doorbell;
938 
939 	if (!ioc->fwfault_debug)
940 		return;
941 
942 	dump_stack();
943 
944 	doorbell = ioc->base_readl(&ioc->chip->Doorbell);
945 	if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
946 		mpt3sas_print_fault_code(ioc, doorbell &
947 		    MPI2_DOORBELL_DATA_MASK);
948 	} else if ((doorbell & MPI2_IOC_STATE_MASK) ==
949 	    MPI2_IOC_STATE_COREDUMP) {
950 		mpt3sas_print_coredump_info(ioc, doorbell &
951 		    MPI2_DOORBELL_DATA_MASK);
952 	} else {
953 		writel(0xC0FFEE00, &ioc->chip->Doorbell);
954 		ioc_err(ioc, "Firmware is halted due to command timeout\n");
955 	}
956 
957 	if (ioc->fwfault_debug == 2)
958 		for (;;)
959 			;
960 	else
961 		panic("panic in %s\n", __func__);
962 }
963 
964 /**
965  * _base_sas_ioc_info - verbose translation of the ioc status
966  * @ioc: per adapter object
967  * @mpi_reply: reply mf payload returned from firmware
968  * @request_hdr: request mf
969  */
970 static void
971 _base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
972 	MPI2RequestHeader_t *request_hdr)
973 {
974 	u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
975 	    MPI2_IOCSTATUS_MASK;
976 	char *desc = NULL;
977 	u16 frame_sz;
978 	char *func_str = NULL;
979 
980 	/* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */
981 	if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
982 	    request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
983 	    request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
984 		return;
985 
986 	if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE)
987 		return;
988 	/*
989 	 * Older Firmware version doesn't support driver trigger pages.
990 	 * So, skip displaying 'config invalid type' type
991 	 * of error message.
992 	 */
993 	if (request_hdr->Function == MPI2_FUNCTION_CONFIG) {
994 		Mpi2ConfigRequest_t *rqst = (Mpi2ConfigRequest_t *)request_hdr;
995 
996 		if ((rqst->ExtPageType ==
997 		    MPI2_CONFIG_EXTPAGETYPE_DRIVER_PERSISTENT_TRIGGER) &&
998 		    !(ioc->logging_level & MPT_DEBUG_CONFIG)) {
999 			return;
1000 		}
1001 	}
1002 
1003 	switch (ioc_status) {
1004 
1005 /****************************************************************************
1006 *  Common IOCStatus values for all replies
1007 ****************************************************************************/
1008 
1009 	case MPI2_IOCSTATUS_INVALID_FUNCTION:
1010 		desc = "invalid function";
1011 		break;
1012 	case MPI2_IOCSTATUS_BUSY:
1013 		desc = "busy";
1014 		break;
1015 	case MPI2_IOCSTATUS_INVALID_SGL:
1016 		desc = "invalid sgl";
1017 		break;
1018 	case MPI2_IOCSTATUS_INTERNAL_ERROR:
1019 		desc = "internal error";
1020 		break;
1021 	case MPI2_IOCSTATUS_INVALID_VPID:
1022 		desc = "invalid vpid";
1023 		break;
1024 	case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
1025 		desc = "insufficient resources";
1026 		break;
1027 	case MPI2_IOCSTATUS_INSUFFICIENT_POWER:
1028 		desc = "insufficient power";
1029 		break;
1030 	case MPI2_IOCSTATUS_INVALID_FIELD:
1031 		desc = "invalid field";
1032 		break;
1033 	case MPI2_IOCSTATUS_INVALID_STATE:
1034 		desc = "invalid state";
1035 		break;
1036 	case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
1037 		desc = "op state not supported";
1038 		break;
1039 
1040 /****************************************************************************
1041 *  Config IOCStatus values
1042 ****************************************************************************/
1043 
1044 	case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
1045 		desc = "config invalid action";
1046 		break;
1047 	case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
1048 		desc = "config invalid type";
1049 		break;
1050 	case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
1051 		desc = "config invalid page";
1052 		break;
1053 	case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
1054 		desc = "config invalid data";
1055 		break;
1056 	case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
1057 		desc = "config no defaults";
1058 		break;
1059 	case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
1060 		desc = "config can't commit";
1061 		break;
1062 
1063 /****************************************************************************
1064 *  SCSI IO Reply
1065 ****************************************************************************/
1066 
1067 	case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
1068 	case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
1069 	case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
1070 	case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
1071 	case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
1072 	case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
1073 	case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
1074 	case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
1075 	case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
1076 	case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
1077 	case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
1078 	case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
1079 		break;
1080 
1081 /****************************************************************************
1082 *  For use by SCSI Initiator and SCSI Target end-to-end data protection
1083 ****************************************************************************/
1084 
1085 	case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
1086 		desc = "eedp guard error";
1087 		break;
1088 	case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
1089 		desc = "eedp ref tag error";
1090 		break;
1091 	case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
1092 		desc = "eedp app tag error";
1093 		break;
1094 
1095 /****************************************************************************
1096 *  SCSI Target values
1097 ****************************************************************************/
1098 
1099 	case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
1100 		desc = "target invalid io index";
1101 		break;
1102 	case MPI2_IOCSTATUS_TARGET_ABORTED:
1103 		desc = "target aborted";
1104 		break;
1105 	case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
1106 		desc = "target no conn retryable";
1107 		break;
1108 	case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
1109 		desc = "target no connection";
1110 		break;
1111 	case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
1112 		desc = "target xfer count mismatch";
1113 		break;
1114 	case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
1115 		desc = "target data offset error";
1116 		break;
1117 	case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
1118 		desc = "target too much write data";
1119 		break;
1120 	case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
1121 		desc = "target iu too short";
1122 		break;
1123 	case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
1124 		desc = "target ack nak timeout";
1125 		break;
1126 	case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
1127 		desc = "target nak received";
1128 		break;
1129 
1130 /****************************************************************************
1131 *  Serial Attached SCSI values
1132 ****************************************************************************/
1133 
1134 	case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
1135 		desc = "smp request failed";
1136 		break;
1137 	case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
1138 		desc = "smp data overrun";
1139 		break;
1140 
1141 /****************************************************************************
1142 *  Diagnostic Buffer Post / Diagnostic Release values
1143 ****************************************************************************/
1144 
1145 	case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
1146 		desc = "diagnostic released";
1147 		break;
1148 	default:
1149 		break;
1150 	}
1151 
1152 	if (!desc)
1153 		return;
1154 
1155 	switch (request_hdr->Function) {
1156 	case MPI2_FUNCTION_CONFIG:
1157 		frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
1158 		func_str = "config_page";
1159 		break;
1160 	case MPI2_FUNCTION_SCSI_TASK_MGMT:
1161 		frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
1162 		func_str = "task_mgmt";
1163 		break;
1164 	case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
1165 		frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
1166 		func_str = "sas_iounit_ctl";
1167 		break;
1168 	case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
1169 		frame_sz = sizeof(Mpi2SepRequest_t);
1170 		func_str = "enclosure";
1171 		break;
1172 	case MPI2_FUNCTION_IOC_INIT:
1173 		frame_sz = sizeof(Mpi2IOCInitRequest_t);
1174 		func_str = "ioc_init";
1175 		break;
1176 	case MPI2_FUNCTION_PORT_ENABLE:
1177 		frame_sz = sizeof(Mpi2PortEnableRequest_t);
1178 		func_str = "port_enable";
1179 		break;
1180 	case MPI2_FUNCTION_SMP_PASSTHROUGH:
1181 		frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
1182 		func_str = "smp_passthru";
1183 		break;
1184 	case MPI2_FUNCTION_NVME_ENCAPSULATED:
1185 		frame_sz = sizeof(Mpi26NVMeEncapsulatedRequest_t) +
1186 		    ioc->sge_size;
1187 		func_str = "nvme_encapsulated";
1188 		break;
1189 	default:
1190 		frame_sz = 32;
1191 		func_str = "unknown";
1192 		break;
1193 	}
1194 
1195 	ioc_warn(ioc, "ioc_status: %s(0x%04x), request(0x%p),(%s)\n",
1196 		 desc, ioc_status, request_hdr, func_str);
1197 
1198 	_debug_dump_mf(request_hdr, frame_sz/4);
1199 }
1200 
1201 /**
1202  * _base_display_event_data - verbose translation of firmware asyn events
1203  * @ioc: per adapter object
1204  * @mpi_reply: reply mf payload returned from firmware
1205  */
1206 static void
1207 _base_display_event_data(struct MPT3SAS_ADAPTER *ioc,
1208 	Mpi2EventNotificationReply_t *mpi_reply)
1209 {
1210 	char *desc = NULL;
1211 	u16 event;
1212 
1213 	if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
1214 		return;
1215 
1216 	event = le16_to_cpu(mpi_reply->Event);
1217 
1218 	switch (event) {
1219 	case MPI2_EVENT_LOG_DATA:
1220 		desc = "Log Data";
1221 		break;
1222 	case MPI2_EVENT_STATE_CHANGE:
1223 		desc = "Status Change";
1224 		break;
1225 	case MPI2_EVENT_HARD_RESET_RECEIVED:
1226 		desc = "Hard Reset Received";
1227 		break;
1228 	case MPI2_EVENT_EVENT_CHANGE:
1229 		desc = "Event Change";
1230 		break;
1231 	case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
1232 		desc = "Device Status Change";
1233 		break;
1234 	case MPI2_EVENT_IR_OPERATION_STATUS:
1235 		if (!ioc->hide_ir_msg)
1236 			desc = "IR Operation Status";
1237 		break;
1238 	case MPI2_EVENT_SAS_DISCOVERY:
1239 	{
1240 		Mpi2EventDataSasDiscovery_t *event_data =
1241 		    (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
1242 		ioc_info(ioc, "Discovery: (%s)",
1243 			 event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED ?
1244 			 "start" : "stop");
1245 		if (event_data->DiscoveryStatus)
1246 			pr_cont(" discovery_status(0x%08x)",
1247 			    le32_to_cpu(event_data->DiscoveryStatus));
1248 		pr_cont("\n");
1249 		return;
1250 	}
1251 	case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
1252 		desc = "SAS Broadcast Primitive";
1253 		break;
1254 	case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
1255 		desc = "SAS Init Device Status Change";
1256 		break;
1257 	case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
1258 		desc = "SAS Init Table Overflow";
1259 		break;
1260 	case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
1261 		desc = "SAS Topology Change List";
1262 		break;
1263 	case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
1264 		desc = "SAS Enclosure Device Status Change";
1265 		break;
1266 	case MPI2_EVENT_IR_VOLUME:
1267 		if (!ioc->hide_ir_msg)
1268 			desc = "IR Volume";
1269 		break;
1270 	case MPI2_EVENT_IR_PHYSICAL_DISK:
1271 		if (!ioc->hide_ir_msg)
1272 			desc = "IR Physical Disk";
1273 		break;
1274 	case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
1275 		if (!ioc->hide_ir_msg)
1276 			desc = "IR Configuration Change List";
1277 		break;
1278 	case MPI2_EVENT_LOG_ENTRY_ADDED:
1279 		if (!ioc->hide_ir_msg)
1280 			desc = "Log Entry Added";
1281 		break;
1282 	case MPI2_EVENT_TEMP_THRESHOLD:
1283 		desc = "Temperature Threshold";
1284 		break;
1285 	case MPI2_EVENT_ACTIVE_CABLE_EXCEPTION:
1286 		desc = "Cable Event";
1287 		break;
1288 	case MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR:
1289 		desc = "SAS Device Discovery Error";
1290 		break;
1291 	case MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE:
1292 		desc = "PCIE Device Status Change";
1293 		break;
1294 	case MPI2_EVENT_PCIE_ENUMERATION:
1295 	{
1296 		Mpi26EventDataPCIeEnumeration_t *event_data =
1297 			(Mpi26EventDataPCIeEnumeration_t *)mpi_reply->EventData;
1298 		ioc_info(ioc, "PCIE Enumeration: (%s)",
1299 			 event_data->ReasonCode == MPI26_EVENT_PCIE_ENUM_RC_STARTED ?
1300 			 "start" : "stop");
1301 		if (event_data->EnumerationStatus)
1302 			pr_cont("enumeration_status(0x%08x)",
1303 				le32_to_cpu(event_data->EnumerationStatus));
1304 		pr_cont("\n");
1305 		return;
1306 	}
1307 	case MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST:
1308 		desc = "PCIE Topology Change List";
1309 		break;
1310 	}
1311 
1312 	if (!desc)
1313 		return;
1314 
1315 	ioc_info(ioc, "%s\n", desc);
1316 }
1317 
1318 /**
1319  * _base_sas_log_info - verbose translation of firmware log info
1320  * @ioc: per adapter object
1321  * @log_info: log info
1322  */
1323 static void
1324 _base_sas_log_info(struct MPT3SAS_ADAPTER *ioc, u32 log_info)
1325 {
1326 	union loginfo_type {
1327 		u32	loginfo;
1328 		struct {
1329 			u32	subcode:16;
1330 			u32	code:8;
1331 			u32	originator:4;
1332 			u32	bus_type:4;
1333 		} dw;
1334 	};
1335 	union loginfo_type sas_loginfo;
1336 	char *originator_str = NULL;
1337 
1338 	sas_loginfo.loginfo = log_info;
1339 	if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
1340 		return;
1341 
1342 	/* each nexus loss loginfo */
1343 	if (log_info == 0x31170000)
1344 		return;
1345 
1346 	/* eat the loginfos associated with task aborts */
1347 	if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info ==
1348 	    0x31140000 || log_info == 0x31130000))
1349 		return;
1350 
1351 	switch (sas_loginfo.dw.originator) {
1352 	case 0:
1353 		originator_str = "IOP";
1354 		break;
1355 	case 1:
1356 		originator_str = "PL";
1357 		break;
1358 	case 2:
1359 		if (!ioc->hide_ir_msg)
1360 			originator_str = "IR";
1361 		else
1362 			originator_str = "WarpDrive";
1363 		break;
1364 	}
1365 
1366 	ioc_warn(ioc, "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n",
1367 		 log_info,
1368 		 originator_str, sas_loginfo.dw.code, sas_loginfo.dw.subcode);
1369 }
1370 
1371 /**
1372  * _base_display_reply_info - handle reply descriptors depending on IOC Status
1373  * @ioc: per adapter object
1374  * @smid: system request message index
1375  * @msix_index: MSIX table index supplied by the OS
1376  * @reply: reply message frame (lower 32bit addr)
1377  */
1378 static void
1379 _base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
1380 	u32 reply)
1381 {
1382 	MPI2DefaultReply_t *mpi_reply;
1383 	u16 ioc_status;
1384 	u32 loginfo = 0;
1385 
1386 	mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
1387 	if (unlikely(!mpi_reply)) {
1388 		ioc_err(ioc, "mpi_reply not valid at %s:%d/%s()!\n",
1389 			__FILE__, __LINE__, __func__);
1390 		return;
1391 	}
1392 	ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
1393 
1394 	if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
1395 	    (ioc->logging_level & MPT_DEBUG_REPLY)) {
1396 		_base_sas_ioc_info(ioc, mpi_reply,
1397 		   mpt3sas_base_get_msg_frame(ioc, smid));
1398 	}
1399 
1400 	if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
1401 		loginfo = le32_to_cpu(mpi_reply->IOCLogInfo);
1402 		_base_sas_log_info(ioc, loginfo);
1403 	}
1404 
1405 	if (ioc_status || loginfo) {
1406 		ioc_status &= MPI2_IOCSTATUS_MASK;
1407 		mpt3sas_trigger_mpi(ioc, ioc_status, loginfo);
1408 	}
1409 }
1410 
1411 /**
1412  * mpt3sas_base_done - base internal command completion routine
1413  * @ioc: per adapter object
1414  * @smid: system request message index
1415  * @msix_index: MSIX table index supplied by the OS
1416  * @reply: reply message frame(lower 32bit addr)
1417  *
1418  * Return:
1419  * 1 meaning mf should be freed from _base_interrupt
1420  * 0 means the mf is freed from this function.
1421  */
1422 u8
1423 mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
1424 	u32 reply)
1425 {
1426 	MPI2DefaultReply_t *mpi_reply;
1427 
1428 	mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
1429 	if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
1430 		return mpt3sas_check_for_pending_internal_cmds(ioc, smid);
1431 
1432 	if (ioc->base_cmds.status == MPT3_CMD_NOT_USED)
1433 		return 1;
1434 
1435 	ioc->base_cmds.status |= MPT3_CMD_COMPLETE;
1436 	if (mpi_reply) {
1437 		ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID;
1438 		memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
1439 	}
1440 	ioc->base_cmds.status &= ~MPT3_CMD_PENDING;
1441 
1442 	complete(&ioc->base_cmds.done);
1443 	return 1;
1444 }
1445 
1446 /**
1447  * _base_async_event - main callback handler for firmware asyn events
1448  * @ioc: per adapter object
1449  * @msix_index: MSIX table index supplied by the OS
1450  * @reply: reply message frame(lower 32bit addr)
1451  *
1452  * Return:
1453  * 1 meaning mf should be freed from _base_interrupt
1454  * 0 means the mf is freed from this function.
1455  */
1456 static u8
1457 _base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
1458 {
1459 	Mpi2EventNotificationReply_t *mpi_reply;
1460 	Mpi2EventAckRequest_t *ack_request;
1461 	u16 smid;
1462 	struct _event_ack_list *delayed_event_ack;
1463 
1464 	mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
1465 	if (!mpi_reply)
1466 		return 1;
1467 	if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
1468 		return 1;
1469 
1470 	_base_display_event_data(ioc, mpi_reply);
1471 
1472 	if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
1473 		goto out;
1474 	smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
1475 	if (!smid) {
1476 		delayed_event_ack = kzalloc(sizeof(*delayed_event_ack),
1477 					GFP_ATOMIC);
1478 		if (!delayed_event_ack)
1479 			goto out;
1480 		INIT_LIST_HEAD(&delayed_event_ack->list);
1481 		delayed_event_ack->Event = mpi_reply->Event;
1482 		delayed_event_ack->EventContext = mpi_reply->EventContext;
1483 		list_add_tail(&delayed_event_ack->list,
1484 				&ioc->delayed_event_ack_list);
1485 		dewtprintk(ioc,
1486 			   ioc_info(ioc, "DELAYED: EVENT ACK: event (0x%04x)\n",
1487 				    le16_to_cpu(mpi_reply->Event)));
1488 		goto out;
1489 	}
1490 
1491 	ack_request = mpt3sas_base_get_msg_frame(ioc, smid);
1492 	memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
1493 	ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
1494 	ack_request->Event = mpi_reply->Event;
1495 	ack_request->EventContext = mpi_reply->EventContext;
1496 	ack_request->VF_ID = 0;  /* TODO */
1497 	ack_request->VP_ID = 0;
1498 	ioc->put_smid_default(ioc, smid);
1499 
1500  out:
1501 
1502 	/* scsih callback handler */
1503 	mpt3sas_scsih_event_callback(ioc, msix_index, reply);
1504 
1505 	/* ctl callback handler */
1506 	mpt3sas_ctl_event_callback(ioc, msix_index, reply);
1507 
1508 	return 1;
1509 }
1510 
1511 static struct scsiio_tracker *
1512 _get_st_from_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1513 {
1514 	struct scsi_cmnd *cmd;
1515 
1516 	if (WARN_ON(!smid) ||
1517 	    WARN_ON(smid >= ioc->hi_priority_smid))
1518 		return NULL;
1519 
1520 	cmd = mpt3sas_scsih_scsi_lookup_get(ioc, smid);
1521 	if (cmd)
1522 		return scsi_cmd_priv(cmd);
1523 
1524 	return NULL;
1525 }
1526 
1527 /**
1528  * _base_get_cb_idx - obtain the callback index
1529  * @ioc: per adapter object
1530  * @smid: system request message index
1531  *
1532  * Return: callback index.
1533  */
1534 static u8
1535 _base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1536 {
1537 	int i;
1538 	u16 ctl_smid = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT + 1;
1539 	u8 cb_idx = 0xFF;
1540 
1541 	if (smid < ioc->hi_priority_smid) {
1542 		struct scsiio_tracker *st;
1543 
1544 		if (smid < ctl_smid) {
1545 			st = _get_st_from_smid(ioc, smid);
1546 			if (st)
1547 				cb_idx = st->cb_idx;
1548 		} else if (smid == ctl_smid)
1549 			cb_idx = ioc->ctl_cb_idx;
1550 	} else if (smid < ioc->internal_smid) {
1551 		i = smid - ioc->hi_priority_smid;
1552 		cb_idx = ioc->hpr_lookup[i].cb_idx;
1553 	} else if (smid <= ioc->hba_queue_depth) {
1554 		i = smid - ioc->internal_smid;
1555 		cb_idx = ioc->internal_lookup[i].cb_idx;
1556 	}
1557 	return cb_idx;
1558 }
1559 
1560 /**
1561  * mpt3sas_base_pause_mq_polling - pause polling on the mq poll queues
1562  *				when driver is flushing out the IOs.
1563  * @ioc: per adapter object
1564  *
1565  * Pause polling on the mq poll (io uring) queues when driver is flushing
1566  * out the IOs. Otherwise we may see the race condition of completing the same
1567  * IO from two paths.
1568  *
1569  * Returns nothing.
1570  */
1571 void
1572 mpt3sas_base_pause_mq_polling(struct MPT3SAS_ADAPTER *ioc)
1573 {
1574 	int iopoll_q_count =
1575 	    ioc->reply_queue_count - ioc->iopoll_q_start_index;
1576 	int qid;
1577 
1578 	for (qid = 0; qid < iopoll_q_count; qid++)
1579 		atomic_set(&ioc->io_uring_poll_queues[qid].pause, 1);
1580 
1581 	/*
1582 	 * wait for current poll to complete.
1583 	 */
1584 	for (qid = 0; qid < iopoll_q_count; qid++) {
1585 		while (atomic_read(&ioc->io_uring_poll_queues[qid].busy)) {
1586 			cpu_relax();
1587 			udelay(500);
1588 		}
1589 	}
1590 }
1591 
1592 /**
1593  * mpt3sas_base_resume_mq_polling - Resume polling on mq poll queues.
1594  * @ioc: per adapter object
1595  *
1596  * Returns nothing.
1597  */
1598 void
1599 mpt3sas_base_resume_mq_polling(struct MPT3SAS_ADAPTER *ioc)
1600 {
1601 	int iopoll_q_count =
1602 	    ioc->reply_queue_count - ioc->iopoll_q_start_index;
1603 	int qid;
1604 
1605 	for (qid = 0; qid < iopoll_q_count; qid++)
1606 		atomic_set(&ioc->io_uring_poll_queues[qid].pause, 0);
1607 }
1608 
1609 /**
1610  * mpt3sas_base_mask_interrupts - disable interrupts
1611  * @ioc: per adapter object
1612  *
1613  * Disabling ResetIRQ, Reply and Doorbell Interrupts
1614  */
1615 void
1616 mpt3sas_base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc)
1617 {
1618 	u32 him_register;
1619 
1620 	ioc->mask_interrupts = 1;
1621 	him_register = ioc->base_readl(&ioc->chip->HostInterruptMask);
1622 	him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
1623 	writel(him_register, &ioc->chip->HostInterruptMask);
1624 	ioc->base_readl(&ioc->chip->HostInterruptMask);
1625 }
1626 
1627 /**
1628  * mpt3sas_base_unmask_interrupts - enable interrupts
1629  * @ioc: per adapter object
1630  *
1631  * Enabling only Reply Interrupts
1632  */
1633 void
1634 mpt3sas_base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc)
1635 {
1636 	u32 him_register;
1637 
1638 	him_register = ioc->base_readl(&ioc->chip->HostInterruptMask);
1639 	him_register &= ~MPI2_HIM_RIM;
1640 	writel(him_register, &ioc->chip->HostInterruptMask);
1641 	ioc->mask_interrupts = 0;
1642 }
1643 
1644 union reply_descriptor {
1645 	u64 word;
1646 	struct {
1647 		u32 low;
1648 		u32 high;
1649 	} u;
1650 };
1651 
1652 static u32 base_mod64(u64 dividend, u32 divisor)
1653 {
1654 	u32 remainder;
1655 
1656 	if (!divisor)
1657 		pr_err("mpt3sas: DIVISOR is zero, in div fn\n");
1658 	remainder = do_div(dividend, divisor);
1659 	return remainder;
1660 }
1661 
1662 /**
1663  * _base_process_reply_queue - Process reply descriptors from reply
1664  *		descriptor post queue.
1665  * @reply_q: per IRQ's reply queue object.
1666  *
1667  * Return: number of reply descriptors processed from reply
1668  *		descriptor queue.
1669  */
1670 static int
1671 _base_process_reply_queue(struct adapter_reply_queue *reply_q)
1672 {
1673 	union reply_descriptor rd;
1674 	u64 completed_cmds;
1675 	u8 request_descript_type;
1676 	u16 smid;
1677 	u8 cb_idx;
1678 	u32 reply;
1679 	u8 msix_index = reply_q->msix_index;
1680 	struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
1681 	Mpi2ReplyDescriptorsUnion_t *rpf;
1682 	u8 rc;
1683 
1684 	completed_cmds = 0;
1685 	if (!atomic_add_unless(&reply_q->busy, 1, 1))
1686 		return completed_cmds;
1687 
1688 	rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index];
1689 	request_descript_type = rpf->Default.ReplyFlags
1690 	     & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1691 	if (request_descript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) {
1692 		atomic_dec(&reply_q->busy);
1693 		return completed_cmds;
1694 	}
1695 
1696 	cb_idx = 0xFF;
1697 	do {
1698 		rd.word = le64_to_cpu(rpf->Words);
1699 		if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
1700 			goto out;
1701 		reply = 0;
1702 		smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
1703 		if (request_descript_type ==
1704 		    MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS ||
1705 		    request_descript_type ==
1706 		    MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS ||
1707 		    request_descript_type ==
1708 		    MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS) {
1709 			cb_idx = _base_get_cb_idx(ioc, smid);
1710 			if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
1711 			    (likely(mpt_callbacks[cb_idx] != NULL))) {
1712 				rc = mpt_callbacks[cb_idx](ioc, smid,
1713 				    msix_index, 0);
1714 				if (rc)
1715 					mpt3sas_base_free_smid(ioc, smid);
1716 			}
1717 		} else if (request_descript_type ==
1718 		    MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
1719 			reply = le32_to_cpu(
1720 			    rpf->AddressReply.ReplyFrameAddress);
1721 			if (reply > ioc->reply_dma_max_address ||
1722 			    reply < ioc->reply_dma_min_address)
1723 				reply = 0;
1724 			if (smid) {
1725 				cb_idx = _base_get_cb_idx(ioc, smid);
1726 				if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
1727 				    (likely(mpt_callbacks[cb_idx] != NULL))) {
1728 					rc = mpt_callbacks[cb_idx](ioc, smid,
1729 					    msix_index, reply);
1730 					if (reply)
1731 						_base_display_reply_info(ioc,
1732 						    smid, msix_index, reply);
1733 					if (rc)
1734 						mpt3sas_base_free_smid(ioc,
1735 						    smid);
1736 				}
1737 			} else {
1738 				_base_async_event(ioc, msix_index, reply);
1739 			}
1740 
1741 			/* reply free queue handling */
1742 			if (reply) {
1743 				ioc->reply_free_host_index =
1744 				    (ioc->reply_free_host_index ==
1745 				    (ioc->reply_free_queue_depth - 1)) ?
1746 				    0 : ioc->reply_free_host_index + 1;
1747 				ioc->reply_free[ioc->reply_free_host_index] =
1748 				    cpu_to_le32(reply);
1749 				if (ioc->is_mcpu_endpoint)
1750 					_base_clone_reply_to_sys_mem(ioc,
1751 						reply,
1752 						ioc->reply_free_host_index);
1753 				writel(ioc->reply_free_host_index,
1754 				    &ioc->chip->ReplyFreeHostIndex);
1755 			}
1756 		}
1757 
1758 		rpf->Words = cpu_to_le64(ULLONG_MAX);
1759 		reply_q->reply_post_host_index =
1760 		    (reply_q->reply_post_host_index ==
1761 		    (ioc->reply_post_queue_depth - 1)) ? 0 :
1762 		    reply_q->reply_post_host_index + 1;
1763 		request_descript_type =
1764 		    reply_q->reply_post_free[reply_q->reply_post_host_index].
1765 		    Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1766 		completed_cmds++;
1767 		/* Update the reply post host index after continuously
1768 		 * processing the threshold number of Reply Descriptors.
1769 		 * So that FW can find enough entries to post the Reply
1770 		 * Descriptors in the reply descriptor post queue.
1771 		 */
1772 		if (completed_cmds >= ioc->thresh_hold) {
1773 			if (ioc->combined_reply_queue) {
1774 				writel(reply_q->reply_post_host_index |
1775 						((msix_index  & 7) <<
1776 						 MPI2_RPHI_MSIX_INDEX_SHIFT),
1777 				    ioc->replyPostRegisterIndex[msix_index/8]);
1778 			} else {
1779 				writel(reply_q->reply_post_host_index |
1780 						(msix_index <<
1781 						 MPI2_RPHI_MSIX_INDEX_SHIFT),
1782 						&ioc->chip->ReplyPostHostIndex);
1783 			}
1784 			if (!reply_q->is_iouring_poll_q &&
1785 			    !reply_q->irq_poll_scheduled) {
1786 				reply_q->irq_poll_scheduled = true;
1787 				irq_poll_sched(&reply_q->irqpoll);
1788 			}
1789 			atomic_dec(&reply_q->busy);
1790 			return completed_cmds;
1791 		}
1792 		if (request_descript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
1793 			goto out;
1794 		if (!reply_q->reply_post_host_index)
1795 			rpf = reply_q->reply_post_free;
1796 		else
1797 			rpf++;
1798 	} while (1);
1799 
1800  out:
1801 
1802 	if (!completed_cmds) {
1803 		atomic_dec(&reply_q->busy);
1804 		return completed_cmds;
1805 	}
1806 
1807 	if (ioc->is_warpdrive) {
1808 		writel(reply_q->reply_post_host_index,
1809 		ioc->reply_post_host_index[msix_index]);
1810 		atomic_dec(&reply_q->busy);
1811 		return completed_cmds;
1812 	}
1813 
1814 	/* Update Reply Post Host Index.
1815 	 * For those HBA's which support combined reply queue feature
1816 	 * 1. Get the correct Supplemental Reply Post Host Index Register.
1817 	 *    i.e. (msix_index / 8)th entry from Supplemental Reply Post Host
1818 	 *    Index Register address bank i.e replyPostRegisterIndex[],
1819 	 * 2. Then update this register with new reply host index value
1820 	 *    in ReplyPostIndex field and the MSIxIndex field with
1821 	 *    msix_index value reduced to a value between 0 and 7,
1822 	 *    using a modulo 8 operation. Since each Supplemental Reply Post
1823 	 *    Host Index Register supports 8 MSI-X vectors.
1824 	 *
1825 	 * For other HBA's just update the Reply Post Host Index register with
1826 	 * new reply host index value in ReplyPostIndex Field and msix_index
1827 	 * value in MSIxIndex field.
1828 	 */
1829 	if (ioc->combined_reply_queue)
1830 		writel(reply_q->reply_post_host_index | ((msix_index  & 7) <<
1831 			MPI2_RPHI_MSIX_INDEX_SHIFT),
1832 			ioc->replyPostRegisterIndex[msix_index/8]);
1833 	else
1834 		writel(reply_q->reply_post_host_index | (msix_index <<
1835 			MPI2_RPHI_MSIX_INDEX_SHIFT),
1836 			&ioc->chip->ReplyPostHostIndex);
1837 	atomic_dec(&reply_q->busy);
1838 	return completed_cmds;
1839 }
1840 
1841 /**
1842  * mpt3sas_blk_mq_poll - poll the blk mq poll queue
1843  * @shost: Scsi_Host object
1844  * @queue_num: hw ctx queue number
1845  *
1846  * Return number of entries that has been processed from poll queue.
1847  */
1848 int mpt3sas_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num)
1849 {
1850 	struct MPT3SAS_ADAPTER *ioc =
1851 	    (struct MPT3SAS_ADAPTER *)shost->hostdata;
1852 	struct adapter_reply_queue *reply_q;
1853 	int num_entries = 0;
1854 	int qid = queue_num - ioc->iopoll_q_start_index;
1855 
1856 	if (atomic_read(&ioc->io_uring_poll_queues[qid].pause) ||
1857 	    !atomic_add_unless(&ioc->io_uring_poll_queues[qid].busy, 1, 1))
1858 		return 0;
1859 
1860 	reply_q = ioc->io_uring_poll_queues[qid].reply_q;
1861 
1862 	num_entries = _base_process_reply_queue(reply_q);
1863 	atomic_dec(&ioc->io_uring_poll_queues[qid].busy);
1864 
1865 	return num_entries;
1866 }
1867 
1868 /**
1869  * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
1870  * @irq: irq number (not used)
1871  * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
1872  *
1873  * Return: IRQ_HANDLED if processed, else IRQ_NONE.
1874  */
1875 static irqreturn_t
1876 _base_interrupt(int irq, void *bus_id)
1877 {
1878 	struct adapter_reply_queue *reply_q = bus_id;
1879 	struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
1880 
1881 	if (ioc->mask_interrupts)
1882 		return IRQ_NONE;
1883 	if (reply_q->irq_poll_scheduled)
1884 		return IRQ_HANDLED;
1885 	return ((_base_process_reply_queue(reply_q) > 0) ?
1886 			IRQ_HANDLED : IRQ_NONE);
1887 }
1888 
1889 /**
1890  * _base_irqpoll - IRQ poll callback handler
1891  * @irqpoll: irq_poll object
1892  * @budget: irq poll weight
1893  *
1894  * Return: number of reply descriptors processed
1895  */
1896 static int
1897 _base_irqpoll(struct irq_poll *irqpoll, int budget)
1898 {
1899 	struct adapter_reply_queue *reply_q;
1900 	int num_entries = 0;
1901 
1902 	reply_q = container_of(irqpoll, struct adapter_reply_queue,
1903 			irqpoll);
1904 	if (reply_q->irq_line_enable) {
1905 		disable_irq_nosync(reply_q->os_irq);
1906 		reply_q->irq_line_enable = false;
1907 	}
1908 	num_entries = _base_process_reply_queue(reply_q);
1909 	if (num_entries < budget) {
1910 		irq_poll_complete(irqpoll);
1911 		reply_q->irq_poll_scheduled = false;
1912 		reply_q->irq_line_enable = true;
1913 		enable_irq(reply_q->os_irq);
1914 		/*
1915 		 * Go for one more round of processing the
1916 		 * reply descriptor post queue in case the HBA
1917 		 * Firmware has posted some reply descriptors
1918 		 * while reenabling the IRQ.
1919 		 */
1920 		_base_process_reply_queue(reply_q);
1921 	}
1922 
1923 	return num_entries;
1924 }
1925 
1926 /**
1927  * _base_init_irqpolls - initliaze IRQ polls
1928  * @ioc: per adapter object
1929  *
1930  * Return: nothing
1931  */
1932 static void
1933 _base_init_irqpolls(struct MPT3SAS_ADAPTER *ioc)
1934 {
1935 	struct adapter_reply_queue *reply_q, *next;
1936 
1937 	if (list_empty(&ioc->reply_queue_list))
1938 		return;
1939 
1940 	list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
1941 		if (reply_q->is_iouring_poll_q)
1942 			continue;
1943 		irq_poll_init(&reply_q->irqpoll,
1944 			ioc->hba_queue_depth/4, _base_irqpoll);
1945 		reply_q->irq_poll_scheduled = false;
1946 		reply_q->irq_line_enable = true;
1947 		reply_q->os_irq = pci_irq_vector(ioc->pdev,
1948 		    reply_q->msix_index);
1949 	}
1950 }
1951 
1952 /**
1953  * _base_is_controller_msix_enabled - is controller support muli-reply queues
1954  * @ioc: per adapter object
1955  *
1956  * Return: Whether or not MSI/X is enabled.
1957  */
1958 static inline int
1959 _base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc)
1960 {
1961 	return (ioc->facts.IOCCapabilities &
1962 	    MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable;
1963 }
1964 
1965 /**
1966  * mpt3sas_base_sync_reply_irqs - flush pending MSIX interrupts
1967  * @ioc: per adapter object
1968  * @poll: poll over reply descriptor pools incase interrupt for
1969  *		timed-out SCSI command got delayed
1970  * Context: non-ISR context
1971  *
1972  * Called when a Task Management request has completed.
1973  */
1974 void
1975 mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc, u8 poll)
1976 {
1977 	struct adapter_reply_queue *reply_q;
1978 
1979 	/* If MSIX capability is turned off
1980 	 * then multi-queues are not enabled
1981 	 */
1982 	if (!_base_is_controller_msix_enabled(ioc))
1983 		return;
1984 
1985 	list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1986 		if (ioc->shost_recovery || ioc->remove_host ||
1987 				ioc->pci_error_recovery)
1988 			return;
1989 		/* TMs are on msix_index == 0 */
1990 		if (reply_q->msix_index == 0)
1991 			continue;
1992 
1993 		if (reply_q->is_iouring_poll_q) {
1994 			_base_process_reply_queue(reply_q);
1995 			continue;
1996 		}
1997 
1998 		synchronize_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index));
1999 		if (reply_q->irq_poll_scheduled) {
2000 			/* Calling irq_poll_disable will wait for any pending
2001 			 * callbacks to have completed.
2002 			 */
2003 			irq_poll_disable(&reply_q->irqpoll);
2004 			irq_poll_enable(&reply_q->irqpoll);
2005 			/* check how the scheduled poll has ended,
2006 			 * clean up only if necessary
2007 			 */
2008 			if (reply_q->irq_poll_scheduled) {
2009 				reply_q->irq_poll_scheduled = false;
2010 				reply_q->irq_line_enable = true;
2011 				enable_irq(reply_q->os_irq);
2012 			}
2013 		}
2014 
2015 		if (poll)
2016 			_base_process_reply_queue(reply_q);
2017 	}
2018 }
2019 
2020 /**
2021  * mpt3sas_base_release_callback_handler - clear interrupt callback handler
2022  * @cb_idx: callback index
2023  */
2024 void
2025 mpt3sas_base_release_callback_handler(u8 cb_idx)
2026 {
2027 	mpt_callbacks[cb_idx] = NULL;
2028 }
2029 
2030 /**
2031  * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler
2032  * @cb_func: callback function
2033  *
2034  * Return: Index of @cb_func.
2035  */
2036 u8
2037 mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func)
2038 {
2039 	u8 cb_idx;
2040 
2041 	for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
2042 		if (mpt_callbacks[cb_idx] == NULL)
2043 			break;
2044 
2045 	mpt_callbacks[cb_idx] = cb_func;
2046 	return cb_idx;
2047 }
2048 
2049 /**
2050  * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler
2051  */
2052 void
2053 mpt3sas_base_initialize_callback_handler(void)
2054 {
2055 	u8 cb_idx;
2056 
2057 	for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
2058 		mpt3sas_base_release_callback_handler(cb_idx);
2059 }
2060 
2061 
2062 /**
2063  * _base_build_zero_len_sge - build zero length sg entry
2064  * @ioc: per adapter object
2065  * @paddr: virtual address for SGE
2066  *
2067  * Create a zero length scatter gather entry to insure the IOCs hardware has
2068  * something to use if the target device goes brain dead and tries
2069  * to send data even when none is asked for.
2070  */
2071 static void
2072 _base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr)
2073 {
2074 	u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
2075 	    MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
2076 	    MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
2077 	    MPI2_SGE_FLAGS_SHIFT);
2078 	ioc->base_add_sg_single(paddr, flags_length, -1);
2079 }
2080 
2081 /**
2082  * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr.
2083  * @paddr: virtual address for SGE
2084  * @flags_length: SGE flags and data transfer length
2085  * @dma_addr: Physical address
2086  */
2087 static void
2088 _base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
2089 {
2090 	Mpi2SGESimple32_t *sgel = paddr;
2091 
2092 	flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
2093 	    MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
2094 	sgel->FlagsLength = cpu_to_le32(flags_length);
2095 	sgel->Address = cpu_to_le32(dma_addr);
2096 }
2097 
2098 
2099 /**
2100  * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr.
2101  * @paddr: virtual address for SGE
2102  * @flags_length: SGE flags and data transfer length
2103  * @dma_addr: Physical address
2104  */
2105 static void
2106 _base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
2107 {
2108 	Mpi2SGESimple64_t *sgel = paddr;
2109 
2110 	flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
2111 	    MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
2112 	sgel->FlagsLength = cpu_to_le32(flags_length);
2113 	sgel->Address = cpu_to_le64(dma_addr);
2114 }
2115 
2116 /**
2117  * _base_get_chain_buffer_tracker - obtain chain tracker
2118  * @ioc: per adapter object
2119  * @scmd: SCSI commands of the IO request
2120  *
2121  * Return: chain tracker from chain_lookup table using key as
2122  * smid and smid's chain_offset.
2123  */
2124 static struct chain_tracker *
2125 _base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc,
2126 			       struct scsi_cmnd *scmd)
2127 {
2128 	struct chain_tracker *chain_req;
2129 	struct scsiio_tracker *st = scsi_cmd_priv(scmd);
2130 	u16 smid = st->smid;
2131 	u8 chain_offset =
2132 	   atomic_read(&ioc->chain_lookup[smid - 1].chain_offset);
2133 
2134 	if (chain_offset == ioc->chains_needed_per_io)
2135 		return NULL;
2136 
2137 	chain_req = &ioc->chain_lookup[smid - 1].chains_per_smid[chain_offset];
2138 	atomic_inc(&ioc->chain_lookup[smid - 1].chain_offset);
2139 	return chain_req;
2140 }
2141 
2142 
2143 /**
2144  * _base_build_sg - build generic sg
2145  * @ioc: per adapter object
2146  * @psge: virtual address for SGE
2147  * @data_out_dma: physical address for WRITES
2148  * @data_out_sz: data xfer size for WRITES
2149  * @data_in_dma: physical address for READS
2150  * @data_in_sz: data xfer size for READS
2151  */
2152 static void
2153 _base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge,
2154 	dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
2155 	size_t data_in_sz)
2156 {
2157 	u32 sgl_flags;
2158 
2159 	if (!data_out_sz && !data_in_sz) {
2160 		_base_build_zero_len_sge(ioc, psge);
2161 		return;
2162 	}
2163 
2164 	if (data_out_sz && data_in_sz) {
2165 		/* WRITE sgel first */
2166 		sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
2167 		    MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC);
2168 		sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
2169 		ioc->base_add_sg_single(psge, sgl_flags |
2170 		    data_out_sz, data_out_dma);
2171 
2172 		/* incr sgel */
2173 		psge += ioc->sge_size;
2174 
2175 		/* READ sgel last */
2176 		sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
2177 		    MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
2178 		    MPI2_SGE_FLAGS_END_OF_LIST);
2179 		sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
2180 		ioc->base_add_sg_single(psge, sgl_flags |
2181 		    data_in_sz, data_in_dma);
2182 	} else if (data_out_sz) /* WRITE */ {
2183 		sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
2184 		    MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
2185 		    MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC);
2186 		sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
2187 		ioc->base_add_sg_single(psge, sgl_flags |
2188 		    data_out_sz, data_out_dma);
2189 	} else if (data_in_sz) /* READ */ {
2190 		sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
2191 		    MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
2192 		    MPI2_SGE_FLAGS_END_OF_LIST);
2193 		sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
2194 		ioc->base_add_sg_single(psge, sgl_flags |
2195 		    data_in_sz, data_in_dma);
2196 	}
2197 }
2198 
2199 /* IEEE format sgls */
2200 
2201 /**
2202  * _base_build_nvme_prp - This function is called for NVMe end devices to build
2203  *                        a native SGL (NVMe PRP).
2204  * @ioc: per adapter object
2205  * @smid: system request message index for getting asscociated SGL
2206  * @nvme_encap_request: the NVMe request msg frame pointer
2207  * @data_out_dma: physical address for WRITES
2208  * @data_out_sz: data xfer size for WRITES
2209  * @data_in_dma: physical address for READS
2210  * @data_in_sz: data xfer size for READS
2211  *
2212  * The native SGL is built starting in the first PRP
2213  * entry of the NVMe message (PRP1).  If the data buffer is small enough to be
2214  * described entirely using PRP1, then PRP2 is not used.  If needed, PRP2 is
2215  * used to describe a larger data buffer.  If the data buffer is too large to
2216  * describe using the two PRP entriess inside the NVMe message, then PRP1
2217  * describes the first data memory segment, and PRP2 contains a pointer to a PRP
2218  * list located elsewhere in memory to describe the remaining data memory
2219  * segments.  The PRP list will be contiguous.
2220  *
2221  * The native SGL for NVMe devices is a Physical Region Page (PRP).  A PRP
2222  * consists of a list of PRP entries to describe a number of noncontigous
2223  * physical memory segments as a single memory buffer, just as a SGL does.  Note
2224  * however, that this function is only used by the IOCTL call, so the memory
2225  * given will be guaranteed to be contiguous.  There is no need to translate
2226  * non-contiguous SGL into a PRP in this case.  All PRPs will describe
2227  * contiguous space that is one page size each.
2228  *
2229  * Each NVMe message contains two PRP entries.  The first (PRP1) either contains
2230  * a PRP list pointer or a PRP element, depending upon the command.  PRP2
2231  * contains the second PRP element if the memory being described fits within 2
2232  * PRP entries, or a PRP list pointer if the PRP spans more than two entries.
2233  *
2234  * A PRP list pointer contains the address of a PRP list, structured as a linear
2235  * array of PRP entries.  Each PRP entry in this list describes a segment of
2236  * physical memory.
2237  *
2238  * Each 64-bit PRP entry comprises an address and an offset field.  The address
2239  * always points at the beginning of a 4KB physical memory page, and the offset
2240  * describes where within that 4KB page the memory segment begins.  Only the
2241  * first element in a PRP list may contain a non-zero offset, implying that all
2242  * memory segments following the first begin at the start of a 4KB page.
2243  *
2244  * Each PRP element normally describes 4KB of physical memory, with exceptions
2245  * for the first and last elements in the list.  If the memory being described
2246  * by the list begins at a non-zero offset within the first 4KB page, then the
2247  * first PRP element will contain a non-zero offset indicating where the region
2248  * begins within the 4KB page.  The last memory segment may end before the end
2249  * of the 4KB segment, depending upon the overall size of the memory being
2250  * described by the PRP list.
2251  *
2252  * Since PRP entries lack any indication of size, the overall data buffer length
2253  * is used to determine where the end of the data memory buffer is located, and
2254  * how many PRP entries are required to describe it.
2255  */
2256 static void
2257 _base_build_nvme_prp(struct MPT3SAS_ADAPTER *ioc, u16 smid,
2258 	Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request,
2259 	dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
2260 	size_t data_in_sz)
2261 {
2262 	int		prp_size = NVME_PRP_SIZE;
2263 	__le64		*prp_entry, *prp1_entry, *prp2_entry;
2264 	__le64		*prp_page;
2265 	dma_addr_t	prp_entry_dma, prp_page_dma, dma_addr;
2266 	u32		offset, entry_len;
2267 	u32		page_mask_result, page_mask;
2268 	size_t		length;
2269 	struct mpt3sas_nvme_cmd *nvme_cmd =
2270 		(void *)nvme_encap_request->NVMe_Command;
2271 
2272 	/*
2273 	 * Not all commands require a data transfer. If no data, just return
2274 	 * without constructing any PRP.
2275 	 */
2276 	if (!data_in_sz && !data_out_sz)
2277 		return;
2278 	prp1_entry = &nvme_cmd->prp1;
2279 	prp2_entry = &nvme_cmd->prp2;
2280 	prp_entry = prp1_entry;
2281 	/*
2282 	 * For the PRP entries, use the specially allocated buffer of
2283 	 * contiguous memory.
2284 	 */
2285 	prp_page = (__le64 *)mpt3sas_base_get_pcie_sgl(ioc, smid);
2286 	prp_page_dma = mpt3sas_base_get_pcie_sgl_dma(ioc, smid);
2287 
2288 	/*
2289 	 * Check if we are within 1 entry of a page boundary we don't
2290 	 * want our first entry to be a PRP List entry.
2291 	 */
2292 	page_mask = ioc->page_size - 1;
2293 	page_mask_result = (uintptr_t)((u8 *)prp_page + prp_size) & page_mask;
2294 	if (!page_mask_result) {
2295 		/* Bump up to next page boundary. */
2296 		prp_page = (__le64 *)((u8 *)prp_page + prp_size);
2297 		prp_page_dma = prp_page_dma + prp_size;
2298 	}
2299 
2300 	/*
2301 	 * Set PRP physical pointer, which initially points to the current PRP
2302 	 * DMA memory page.
2303 	 */
2304 	prp_entry_dma = prp_page_dma;
2305 
2306 	/* Get physical address and length of the data buffer. */
2307 	if (data_in_sz) {
2308 		dma_addr = data_in_dma;
2309 		length = data_in_sz;
2310 	} else {
2311 		dma_addr = data_out_dma;
2312 		length = data_out_sz;
2313 	}
2314 
2315 	/* Loop while the length is not zero. */
2316 	while (length) {
2317 		/*
2318 		 * Check if we need to put a list pointer here if we are at
2319 		 * page boundary - prp_size (8 bytes).
2320 		 */
2321 		page_mask_result = (prp_entry_dma + prp_size) & page_mask;
2322 		if (!page_mask_result) {
2323 			/*
2324 			 * This is the last entry in a PRP List, so we need to
2325 			 * put a PRP list pointer here.  What this does is:
2326 			 *   - bump the current memory pointer to the next
2327 			 *     address, which will be the next full page.
2328 			 *   - set the PRP Entry to point to that page.  This
2329 			 *     is now the PRP List pointer.
2330 			 *   - bump the PRP Entry pointer the start of the
2331 			 *     next page.  Since all of this PRP memory is
2332 			 *     contiguous, no need to get a new page - it's
2333 			 *     just the next address.
2334 			 */
2335 			prp_entry_dma++;
2336 			*prp_entry = cpu_to_le64(prp_entry_dma);
2337 			prp_entry++;
2338 		}
2339 
2340 		/* Need to handle if entry will be part of a page. */
2341 		offset = dma_addr & page_mask;
2342 		entry_len = ioc->page_size - offset;
2343 
2344 		if (prp_entry == prp1_entry) {
2345 			/*
2346 			 * Must fill in the first PRP pointer (PRP1) before
2347 			 * moving on.
2348 			 */
2349 			*prp1_entry = cpu_to_le64(dma_addr);
2350 
2351 			/*
2352 			 * Now point to the second PRP entry within the
2353 			 * command (PRP2).
2354 			 */
2355 			prp_entry = prp2_entry;
2356 		} else if (prp_entry == prp2_entry) {
2357 			/*
2358 			 * Should the PRP2 entry be a PRP List pointer or just
2359 			 * a regular PRP pointer?  If there is more than one
2360 			 * more page of data, must use a PRP List pointer.
2361 			 */
2362 			if (length > ioc->page_size) {
2363 				/*
2364 				 * PRP2 will contain a PRP List pointer because
2365 				 * more PRP's are needed with this command. The
2366 				 * list will start at the beginning of the
2367 				 * contiguous buffer.
2368 				 */
2369 				*prp2_entry = cpu_to_le64(prp_entry_dma);
2370 
2371 				/*
2372 				 * The next PRP Entry will be the start of the
2373 				 * first PRP List.
2374 				 */
2375 				prp_entry = prp_page;
2376 			} else {
2377 				/*
2378 				 * After this, the PRP Entries are complete.
2379 				 * This command uses 2 PRP's and no PRP list.
2380 				 */
2381 				*prp2_entry = cpu_to_le64(dma_addr);
2382 			}
2383 		} else {
2384 			/*
2385 			 * Put entry in list and bump the addresses.
2386 			 *
2387 			 * After PRP1 and PRP2 are filled in, this will fill in
2388 			 * all remaining PRP entries in a PRP List, one per
2389 			 * each time through the loop.
2390 			 */
2391 			*prp_entry = cpu_to_le64(dma_addr);
2392 			prp_entry++;
2393 			prp_entry_dma++;
2394 		}
2395 
2396 		/*
2397 		 * Bump the phys address of the command's data buffer by the
2398 		 * entry_len.
2399 		 */
2400 		dma_addr += entry_len;
2401 
2402 		/* Decrement length accounting for last partial page. */
2403 		if (entry_len > length)
2404 			length = 0;
2405 		else
2406 			length -= entry_len;
2407 	}
2408 }
2409 
2410 /**
2411  * base_make_prp_nvme - Prepare PRPs (Physical Region Page) -
2412  *			SGLs specific to NVMe drives only
2413  *
2414  * @ioc:		per adapter object
2415  * @scmd:		SCSI command from the mid-layer
2416  * @mpi_request:	mpi request
2417  * @smid:		msg Index
2418  * @sge_count:		scatter gather element count.
2419  *
2420  * Return:		true: PRPs are built
2421  *			false: IEEE SGLs needs to be built
2422  */
2423 static void
2424 base_make_prp_nvme(struct MPT3SAS_ADAPTER *ioc,
2425 		struct scsi_cmnd *scmd,
2426 		Mpi25SCSIIORequest_t *mpi_request,
2427 		u16 smid, int sge_count)
2428 {
2429 	int sge_len, num_prp_in_chain = 0;
2430 	Mpi25IeeeSgeChain64_t *main_chain_element, *ptr_first_sgl;
2431 	__le64 *curr_buff;
2432 	dma_addr_t msg_dma, sge_addr, offset;
2433 	u32 page_mask, page_mask_result;
2434 	struct scatterlist *sg_scmd;
2435 	u32 first_prp_len;
2436 	int data_len = scsi_bufflen(scmd);
2437 	u32 nvme_pg_size;
2438 
2439 	nvme_pg_size = max_t(u32, ioc->page_size, NVME_PRP_PAGE_SIZE);
2440 	/*
2441 	 * Nvme has a very convoluted prp format.  One prp is required
2442 	 * for each page or partial page. Driver need to split up OS sg_list
2443 	 * entries if it is longer than one page or cross a page
2444 	 * boundary.  Driver also have to insert a PRP list pointer entry as
2445 	 * the last entry in each physical page of the PRP list.
2446 	 *
2447 	 * NOTE: The first PRP "entry" is actually placed in the first
2448 	 * SGL entry in the main message as IEEE 64 format.  The 2nd
2449 	 * entry in the main message is the chain element, and the rest
2450 	 * of the PRP entries are built in the contiguous pcie buffer.
2451 	 */
2452 	page_mask = nvme_pg_size - 1;
2453 
2454 	/*
2455 	 * Native SGL is needed.
2456 	 * Put a chain element in main message frame that points to the first
2457 	 * chain buffer.
2458 	 *
2459 	 * NOTE:  The ChainOffset field must be 0 when using a chain pointer to
2460 	 *        a native SGL.
2461 	 */
2462 
2463 	/* Set main message chain element pointer */
2464 	main_chain_element = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL;
2465 	/*
2466 	 * For NVMe the chain element needs to be the 2nd SG entry in the main
2467 	 * message.
2468 	 */
2469 	main_chain_element = (Mpi25IeeeSgeChain64_t *)
2470 		((u8 *)main_chain_element + sizeof(MPI25_IEEE_SGE_CHAIN64));
2471 
2472 	/*
2473 	 * For the PRP entries, use the specially allocated buffer of
2474 	 * contiguous memory.  Normal chain buffers can't be used
2475 	 * because each chain buffer would need to be the size of an OS
2476 	 * page (4k).
2477 	 */
2478 	curr_buff = mpt3sas_base_get_pcie_sgl(ioc, smid);
2479 	msg_dma = mpt3sas_base_get_pcie_sgl_dma(ioc, smid);
2480 
2481 	main_chain_element->Address = cpu_to_le64(msg_dma);
2482 	main_chain_element->NextChainOffset = 0;
2483 	main_chain_element->Flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
2484 			MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
2485 			MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP;
2486 
2487 	/* Build first prp, sge need not to be page aligned*/
2488 	ptr_first_sgl = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL;
2489 	sg_scmd = scsi_sglist(scmd);
2490 	sge_addr = sg_dma_address(sg_scmd);
2491 	sge_len = sg_dma_len(sg_scmd);
2492 
2493 	offset = sge_addr & page_mask;
2494 	first_prp_len = nvme_pg_size - offset;
2495 
2496 	ptr_first_sgl->Address = cpu_to_le64(sge_addr);
2497 	ptr_first_sgl->Length = cpu_to_le32(first_prp_len);
2498 
2499 	data_len -= first_prp_len;
2500 
2501 	if (sge_len > first_prp_len) {
2502 		sge_addr += first_prp_len;
2503 		sge_len -= first_prp_len;
2504 	} else if (data_len && (sge_len == first_prp_len)) {
2505 		sg_scmd = sg_next(sg_scmd);
2506 		sge_addr = sg_dma_address(sg_scmd);
2507 		sge_len = sg_dma_len(sg_scmd);
2508 	}
2509 
2510 	for (;;) {
2511 		offset = sge_addr & page_mask;
2512 
2513 		/* Put PRP pointer due to page boundary*/
2514 		page_mask_result = (uintptr_t)(curr_buff + 1) & page_mask;
2515 		if (unlikely(!page_mask_result)) {
2516 			scmd_printk(KERN_NOTICE,
2517 				scmd, "page boundary curr_buff: 0x%p\n",
2518 				curr_buff);
2519 			msg_dma += 8;
2520 			*curr_buff = cpu_to_le64(msg_dma);
2521 			curr_buff++;
2522 			num_prp_in_chain++;
2523 		}
2524 
2525 		*curr_buff = cpu_to_le64(sge_addr);
2526 		curr_buff++;
2527 		msg_dma += 8;
2528 		num_prp_in_chain++;
2529 
2530 		sge_addr += nvme_pg_size;
2531 		sge_len -= nvme_pg_size;
2532 		data_len -= nvme_pg_size;
2533 
2534 		if (data_len <= 0)
2535 			break;
2536 
2537 		if (sge_len > 0)
2538 			continue;
2539 
2540 		sg_scmd = sg_next(sg_scmd);
2541 		sge_addr = sg_dma_address(sg_scmd);
2542 		sge_len = sg_dma_len(sg_scmd);
2543 	}
2544 
2545 	main_chain_element->Length =
2546 		cpu_to_le32(num_prp_in_chain * sizeof(u64));
2547 	return;
2548 }
2549 
2550 static bool
2551 base_is_prp_possible(struct MPT3SAS_ADAPTER *ioc,
2552 	struct _pcie_device *pcie_device, struct scsi_cmnd *scmd, int sge_count)
2553 {
2554 	u32 data_length = 0;
2555 	bool build_prp = true;
2556 
2557 	data_length = scsi_bufflen(scmd);
2558 	if (pcie_device &&
2559 	    (mpt3sas_scsih_is_pcie_scsi_device(pcie_device->device_info))) {
2560 		build_prp = false;
2561 		return build_prp;
2562 	}
2563 
2564 	/* If Datalenth is <= 16K and number of SGE’s entries are <= 2
2565 	 * we built IEEE SGL
2566 	 */
2567 	if ((data_length <= NVME_PRP_PAGE_SIZE*4) && (sge_count <= 2))
2568 		build_prp = false;
2569 
2570 	return build_prp;
2571 }
2572 
2573 /**
2574  * _base_check_pcie_native_sgl - This function is called for PCIe end devices to
2575  * determine if the driver needs to build a native SGL.  If so, that native
2576  * SGL is built in the special contiguous buffers allocated especially for
2577  * PCIe SGL creation.  If the driver will not build a native SGL, return
2578  * TRUE and a normal IEEE SGL will be built.  Currently this routine
2579  * supports NVMe.
2580  * @ioc: per adapter object
2581  * @mpi_request: mf request pointer
2582  * @smid: system request message index
2583  * @scmd: scsi command
2584  * @pcie_device: points to the PCIe device's info
2585  *
2586  * Return: 0 if native SGL was built, 1 if no SGL was built
2587  */
2588 static int
2589 _base_check_pcie_native_sgl(struct MPT3SAS_ADAPTER *ioc,
2590 	Mpi25SCSIIORequest_t *mpi_request, u16 smid, struct scsi_cmnd *scmd,
2591 	struct _pcie_device *pcie_device)
2592 {
2593 	int sges_left;
2594 
2595 	/* Get the SG list pointer and info. */
2596 	sges_left = scsi_dma_map(scmd);
2597 	if (sges_left < 0)
2598 		return 1;
2599 
2600 	/* Check if we need to build a native SG list. */
2601 	if (!base_is_prp_possible(ioc, pcie_device,
2602 				scmd, sges_left)) {
2603 		/* We built a native SG list, just return. */
2604 		goto out;
2605 	}
2606 
2607 	/*
2608 	 * Build native NVMe PRP.
2609 	 */
2610 	base_make_prp_nvme(ioc, scmd, mpi_request,
2611 			smid, sges_left);
2612 
2613 	return 0;
2614 out:
2615 	scsi_dma_unmap(scmd);
2616 	return 1;
2617 }
2618 
2619 /**
2620  * _base_add_sg_single_ieee - add sg element for IEEE format
2621  * @paddr: virtual address for SGE
2622  * @flags: SGE flags
2623  * @chain_offset: number of 128 byte elements from start of segment
2624  * @length: data transfer length
2625  * @dma_addr: Physical address
2626  */
2627 static void
2628 _base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length,
2629 	dma_addr_t dma_addr)
2630 {
2631 	Mpi25IeeeSgeChain64_t *sgel = paddr;
2632 
2633 	sgel->Flags = flags;
2634 	sgel->NextChainOffset = chain_offset;
2635 	sgel->Length = cpu_to_le32(length);
2636 	sgel->Address = cpu_to_le64(dma_addr);
2637 }
2638 
2639 /**
2640  * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format
2641  * @ioc: per adapter object
2642  * @paddr: virtual address for SGE
2643  *
2644  * Create a zero length scatter gather entry to insure the IOCs hardware has
2645  * something to use if the target device goes brain dead and tries
2646  * to send data even when none is asked for.
2647  */
2648 static void
2649 _base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr)
2650 {
2651 	u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2652 		MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
2653 		MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
2654 
2655 	_base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1);
2656 }
2657 
2658 /**
2659  * _base_build_sg_scmd - main sg creation routine
2660  *		pcie_device is unused here!
2661  * @ioc: per adapter object
2662  * @scmd: scsi command
2663  * @smid: system request message index
2664  * @unused: unused pcie_device pointer
2665  * Context: none.
2666  *
2667  * The main routine that builds scatter gather table from a given
2668  * scsi request sent via the .queuecommand main handler.
2669  *
2670  * Return: 0 success, anything else error
2671  */
2672 static int
2673 _base_build_sg_scmd(struct MPT3SAS_ADAPTER *ioc,
2674 	struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *unused)
2675 {
2676 	Mpi2SCSIIORequest_t *mpi_request;
2677 	dma_addr_t chain_dma;
2678 	struct scatterlist *sg_scmd;
2679 	void *sg_local, *chain;
2680 	u32 chain_offset;
2681 	u32 chain_length;
2682 	u32 chain_flags;
2683 	int sges_left;
2684 	u32 sges_in_segment;
2685 	u32 sgl_flags;
2686 	u32 sgl_flags_last_element;
2687 	u32 sgl_flags_end_buffer;
2688 	struct chain_tracker *chain_req;
2689 
2690 	mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
2691 
2692 	/* init scatter gather flags */
2693 	sgl_flags = MPI2_SGE_FLAGS_SIMPLE_ELEMENT;
2694 	if (scmd->sc_data_direction == DMA_TO_DEVICE)
2695 		sgl_flags |= MPI2_SGE_FLAGS_HOST_TO_IOC;
2696 	sgl_flags_last_element = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT)
2697 	    << MPI2_SGE_FLAGS_SHIFT;
2698 	sgl_flags_end_buffer = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT |
2699 	    MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST)
2700 	    << MPI2_SGE_FLAGS_SHIFT;
2701 	sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
2702 
2703 	sg_scmd = scsi_sglist(scmd);
2704 	sges_left = scsi_dma_map(scmd);
2705 	if (sges_left < 0)
2706 		return -ENOMEM;
2707 
2708 	sg_local = &mpi_request->SGL;
2709 	sges_in_segment = ioc->max_sges_in_main_message;
2710 	if (sges_left <= sges_in_segment)
2711 		goto fill_in_last_segment;
2712 
2713 	mpi_request->ChainOffset = (offsetof(Mpi2SCSIIORequest_t, SGL) +
2714 	    (sges_in_segment * ioc->sge_size))/4;
2715 
2716 	/* fill in main message segment when there is a chain following */
2717 	while (sges_in_segment) {
2718 		if (sges_in_segment == 1)
2719 			ioc->base_add_sg_single(sg_local,
2720 			    sgl_flags_last_element | sg_dma_len(sg_scmd),
2721 			    sg_dma_address(sg_scmd));
2722 		else
2723 			ioc->base_add_sg_single(sg_local, sgl_flags |
2724 			    sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2725 		sg_scmd = sg_next(sg_scmd);
2726 		sg_local += ioc->sge_size;
2727 		sges_left--;
2728 		sges_in_segment--;
2729 	}
2730 
2731 	/* initializing the chain flags and pointers */
2732 	chain_flags = MPI2_SGE_FLAGS_CHAIN_ELEMENT << MPI2_SGE_FLAGS_SHIFT;
2733 	chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
2734 	if (!chain_req)
2735 		return -1;
2736 	chain = chain_req->chain_buffer;
2737 	chain_dma = chain_req->chain_buffer_dma;
2738 	do {
2739 		sges_in_segment = (sges_left <=
2740 		    ioc->max_sges_in_chain_message) ? sges_left :
2741 		    ioc->max_sges_in_chain_message;
2742 		chain_offset = (sges_left == sges_in_segment) ?
2743 		    0 : (sges_in_segment * ioc->sge_size)/4;
2744 		chain_length = sges_in_segment * ioc->sge_size;
2745 		if (chain_offset) {
2746 			chain_offset = chain_offset <<
2747 			    MPI2_SGE_CHAIN_OFFSET_SHIFT;
2748 			chain_length += ioc->sge_size;
2749 		}
2750 		ioc->base_add_sg_single(sg_local, chain_flags | chain_offset |
2751 		    chain_length, chain_dma);
2752 		sg_local = chain;
2753 		if (!chain_offset)
2754 			goto fill_in_last_segment;
2755 
2756 		/* fill in chain segments */
2757 		while (sges_in_segment) {
2758 			if (sges_in_segment == 1)
2759 				ioc->base_add_sg_single(sg_local,
2760 				    sgl_flags_last_element |
2761 				    sg_dma_len(sg_scmd),
2762 				    sg_dma_address(sg_scmd));
2763 			else
2764 				ioc->base_add_sg_single(sg_local, sgl_flags |
2765 				    sg_dma_len(sg_scmd),
2766 				    sg_dma_address(sg_scmd));
2767 			sg_scmd = sg_next(sg_scmd);
2768 			sg_local += ioc->sge_size;
2769 			sges_left--;
2770 			sges_in_segment--;
2771 		}
2772 
2773 		chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
2774 		if (!chain_req)
2775 			return -1;
2776 		chain = chain_req->chain_buffer;
2777 		chain_dma = chain_req->chain_buffer_dma;
2778 	} while (1);
2779 
2780 
2781  fill_in_last_segment:
2782 
2783 	/* fill the last segment */
2784 	while (sges_left) {
2785 		if (sges_left == 1)
2786 			ioc->base_add_sg_single(sg_local, sgl_flags_end_buffer |
2787 			    sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2788 		else
2789 			ioc->base_add_sg_single(sg_local, sgl_flags |
2790 			    sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2791 		sg_scmd = sg_next(sg_scmd);
2792 		sg_local += ioc->sge_size;
2793 		sges_left--;
2794 	}
2795 
2796 	return 0;
2797 }
2798 
2799 /**
2800  * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format
2801  * @ioc: per adapter object
2802  * @scmd: scsi command
2803  * @smid: system request message index
2804  * @pcie_device: Pointer to pcie_device. If set, the pcie native sgl will be
2805  * constructed on need.
2806  * Context: none.
2807  *
2808  * The main routine that builds scatter gather table from a given
2809  * scsi request sent via the .queuecommand main handler.
2810  *
2811  * Return: 0 success, anything else error
2812  */
2813 static int
2814 _base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc,
2815 	struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *pcie_device)
2816 {
2817 	Mpi25SCSIIORequest_t *mpi_request;
2818 	dma_addr_t chain_dma;
2819 	struct scatterlist *sg_scmd;
2820 	void *sg_local, *chain;
2821 	u32 chain_offset;
2822 	u32 chain_length;
2823 	int sges_left;
2824 	u32 sges_in_segment;
2825 	u8 simple_sgl_flags;
2826 	u8 simple_sgl_flags_last;
2827 	u8 chain_sgl_flags;
2828 	struct chain_tracker *chain_req;
2829 
2830 	mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
2831 
2832 	/* init scatter gather flags */
2833 	simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2834 	    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2835 	simple_sgl_flags_last = simple_sgl_flags |
2836 	    MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
2837 	chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
2838 	    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2839 
2840 	/* Check if we need to build a native SG list. */
2841 	if ((pcie_device) && (_base_check_pcie_native_sgl(ioc, mpi_request,
2842 			smid, scmd, pcie_device) == 0)) {
2843 		/* We built a native SG list, just return. */
2844 		return 0;
2845 	}
2846 
2847 	sg_scmd = scsi_sglist(scmd);
2848 	sges_left = scsi_dma_map(scmd);
2849 	if (sges_left < 0)
2850 		return -ENOMEM;
2851 
2852 	sg_local = &mpi_request->SGL;
2853 	sges_in_segment = (ioc->request_sz -
2854 		   offsetof(Mpi25SCSIIORequest_t, SGL))/ioc->sge_size_ieee;
2855 	if (sges_left <= sges_in_segment)
2856 		goto fill_in_last_segment;
2857 
2858 	mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) +
2859 	    (offsetof(Mpi25SCSIIORequest_t, SGL)/ioc->sge_size_ieee);
2860 
2861 	/* fill in main message segment when there is a chain following */
2862 	while (sges_in_segment > 1) {
2863 		_base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
2864 		    sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2865 		sg_scmd = sg_next(sg_scmd);
2866 		sg_local += ioc->sge_size_ieee;
2867 		sges_left--;
2868 		sges_in_segment--;
2869 	}
2870 
2871 	/* initializing the pointers */
2872 	chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
2873 	if (!chain_req)
2874 		return -1;
2875 	chain = chain_req->chain_buffer;
2876 	chain_dma = chain_req->chain_buffer_dma;
2877 	do {
2878 		sges_in_segment = (sges_left <=
2879 		    ioc->max_sges_in_chain_message) ? sges_left :
2880 		    ioc->max_sges_in_chain_message;
2881 		chain_offset = (sges_left == sges_in_segment) ?
2882 		    0 : sges_in_segment;
2883 		chain_length = sges_in_segment * ioc->sge_size_ieee;
2884 		if (chain_offset)
2885 			chain_length += ioc->sge_size_ieee;
2886 		_base_add_sg_single_ieee(sg_local, chain_sgl_flags,
2887 		    chain_offset, chain_length, chain_dma);
2888 
2889 		sg_local = chain;
2890 		if (!chain_offset)
2891 			goto fill_in_last_segment;
2892 
2893 		/* fill in chain segments */
2894 		while (sges_in_segment) {
2895 			_base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
2896 			    sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2897 			sg_scmd = sg_next(sg_scmd);
2898 			sg_local += ioc->sge_size_ieee;
2899 			sges_left--;
2900 			sges_in_segment--;
2901 		}
2902 
2903 		chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
2904 		if (!chain_req)
2905 			return -1;
2906 		chain = chain_req->chain_buffer;
2907 		chain_dma = chain_req->chain_buffer_dma;
2908 	} while (1);
2909 
2910 
2911  fill_in_last_segment:
2912 
2913 	/* fill the last segment */
2914 	while (sges_left > 0) {
2915 		if (sges_left == 1)
2916 			_base_add_sg_single_ieee(sg_local,
2917 			    simple_sgl_flags_last, 0, sg_dma_len(sg_scmd),
2918 			    sg_dma_address(sg_scmd));
2919 		else
2920 			_base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
2921 			    sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2922 		sg_scmd = sg_next(sg_scmd);
2923 		sg_local += ioc->sge_size_ieee;
2924 		sges_left--;
2925 	}
2926 
2927 	return 0;
2928 }
2929 
2930 /**
2931  * _base_build_sg_ieee - build generic sg for IEEE format
2932  * @ioc: per adapter object
2933  * @psge: virtual address for SGE
2934  * @data_out_dma: physical address for WRITES
2935  * @data_out_sz: data xfer size for WRITES
2936  * @data_in_dma: physical address for READS
2937  * @data_in_sz: data xfer size for READS
2938  */
2939 static void
2940 _base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge,
2941 	dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
2942 	size_t data_in_sz)
2943 {
2944 	u8 sgl_flags;
2945 
2946 	if (!data_out_sz && !data_in_sz) {
2947 		_base_build_zero_len_sge_ieee(ioc, psge);
2948 		return;
2949 	}
2950 
2951 	if (data_out_sz && data_in_sz) {
2952 		/* WRITE sgel first */
2953 		sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2954 		    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2955 		_base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
2956 		    data_out_dma);
2957 
2958 		/* incr sgel */
2959 		psge += ioc->sge_size_ieee;
2960 
2961 		/* READ sgel last */
2962 		sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
2963 		_base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
2964 		    data_in_dma);
2965 	} else if (data_out_sz) /* WRITE */ {
2966 		sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2967 		    MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
2968 		    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2969 		_base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
2970 		    data_out_dma);
2971 	} else if (data_in_sz) /* READ */ {
2972 		sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2973 		    MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
2974 		    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2975 		_base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
2976 		    data_in_dma);
2977 	}
2978 }
2979 
2980 #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
2981 
2982 /**
2983  * _base_config_dma_addressing - set dma addressing
2984  * @ioc: per adapter object
2985  * @pdev: PCI device struct
2986  *
2987  * Return: 0 for success, non-zero for failure.
2988  */
2989 static int
2990 _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
2991 {
2992 	struct sysinfo s;
2993 	u64 coherent_dma_mask, dma_mask;
2994 
2995 	if (ioc->is_mcpu_endpoint || sizeof(dma_addr_t) == 4) {
2996 		ioc->dma_mask = 32;
2997 		coherent_dma_mask = dma_mask = DMA_BIT_MASK(32);
2998 	/* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */
2999 	} else if (ioc->hba_mpi_version_belonged > MPI2_VERSION) {
3000 		ioc->dma_mask = 63;
3001 		coherent_dma_mask = dma_mask = DMA_BIT_MASK(63);
3002 	} else {
3003 		ioc->dma_mask = 64;
3004 		coherent_dma_mask = dma_mask = DMA_BIT_MASK(64);
3005 	}
3006 
3007 	if (ioc->use_32bit_dma)
3008 		coherent_dma_mask = DMA_BIT_MASK(32);
3009 
3010 	if (dma_set_mask(&pdev->dev, dma_mask) ||
3011 	    dma_set_coherent_mask(&pdev->dev, coherent_dma_mask))
3012 		return -ENODEV;
3013 
3014 	if (ioc->dma_mask > 32) {
3015 		ioc->base_add_sg_single = &_base_add_sg_single_64;
3016 		ioc->sge_size = sizeof(Mpi2SGESimple64_t);
3017 	} else {
3018 		ioc->base_add_sg_single = &_base_add_sg_single_32;
3019 		ioc->sge_size = sizeof(Mpi2SGESimple32_t);
3020 	}
3021 
3022 	si_meminfo(&s);
3023 	ioc_info(ioc, "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
3024 		ioc->dma_mask, convert_to_kb(s.totalram));
3025 
3026 	return 0;
3027 }
3028 
3029 /**
3030  * _base_check_enable_msix - checks MSIX capabable.
3031  * @ioc: per adapter object
3032  *
3033  * Check to see if card is capable of MSIX, and set number
3034  * of available msix vectors
3035  */
3036 static int
3037 _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)
3038 {
3039 	int base;
3040 	u16 message_control;
3041 
3042 	/* Check whether controller SAS2008 B0 controller,
3043 	 * if it is SAS2008 B0 controller use IO-APIC instead of MSIX
3044 	 */
3045 	if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 &&
3046 	    ioc->pdev->revision == SAS2_PCI_DEVICE_B0_REVISION) {
3047 		return -EINVAL;
3048 	}
3049 
3050 	base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
3051 	if (!base) {
3052 		dfailprintk(ioc, ioc_info(ioc, "msix not supported\n"));
3053 		return -EINVAL;
3054 	}
3055 
3056 	/* get msix vector count */
3057 	/* NUMA_IO not supported for older controllers */
3058 	if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 ||
3059 	    ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 ||
3060 	    ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 ||
3061 	    ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 ||
3062 	    ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 ||
3063 	    ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 ||
3064 	    ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2)
3065 		ioc->msix_vector_count = 1;
3066 	else {
3067 		pci_read_config_word(ioc->pdev, base + 2, &message_control);
3068 		ioc->msix_vector_count = (message_control & 0x3FF) + 1;
3069 	}
3070 	dinitprintk(ioc, ioc_info(ioc, "msix is supported, vector_count(%d)\n",
3071 				  ioc->msix_vector_count));
3072 	return 0;
3073 }
3074 
3075 /**
3076  * mpt3sas_base_free_irq - free irq
3077  * @ioc: per adapter object
3078  *
3079  * Freeing respective reply_queue from the list.
3080  */
3081 void
3082 mpt3sas_base_free_irq(struct MPT3SAS_ADAPTER *ioc)
3083 {
3084 	unsigned int irq;
3085 	struct adapter_reply_queue *reply_q, *next;
3086 
3087 	if (list_empty(&ioc->reply_queue_list))
3088 		return;
3089 
3090 	list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
3091 		list_del(&reply_q->list);
3092 		if (reply_q->is_iouring_poll_q) {
3093 			kfree(reply_q);
3094 			continue;
3095 		}
3096 
3097 		if (ioc->smp_affinity_enable) {
3098 			irq = pci_irq_vector(ioc->pdev, reply_q->msix_index);
3099 			irq_update_affinity_hint(irq, NULL);
3100 		}
3101 		free_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index),
3102 			 reply_q);
3103 		kfree(reply_q);
3104 	}
3105 }
3106 
3107 /**
3108  * _base_request_irq - request irq
3109  * @ioc: per adapter object
3110  * @index: msix index into vector table
3111  *
3112  * Inserting respective reply_queue into the list.
3113  */
3114 static int
3115 _base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index)
3116 {
3117 	struct pci_dev *pdev = ioc->pdev;
3118 	struct adapter_reply_queue *reply_q;
3119 	int r, qid;
3120 
3121 	reply_q =  kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL);
3122 	if (!reply_q) {
3123 		ioc_err(ioc, "unable to allocate memory %zu!\n",
3124 			sizeof(struct adapter_reply_queue));
3125 		return -ENOMEM;
3126 	}
3127 	reply_q->ioc = ioc;
3128 	reply_q->msix_index = index;
3129 
3130 	atomic_set(&reply_q->busy, 0);
3131 
3132 	if (index >= ioc->iopoll_q_start_index) {
3133 		qid = index - ioc->iopoll_q_start_index;
3134 		snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-mq-poll%d",
3135 		    ioc->driver_name, ioc->id, qid);
3136 		reply_q->is_iouring_poll_q = 1;
3137 		ioc->io_uring_poll_queues[qid].reply_q = reply_q;
3138 		goto out;
3139 	}
3140 
3141 
3142 	if (ioc->msix_enable)
3143 		snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d",
3144 		    ioc->driver_name, ioc->id, index);
3145 	else
3146 		snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d",
3147 		    ioc->driver_name, ioc->id);
3148 	r = request_irq(pci_irq_vector(pdev, index), _base_interrupt,
3149 			IRQF_SHARED, reply_q->name, reply_q);
3150 	if (r) {
3151 		pr_err("%s: unable to allocate interrupt %d!\n",
3152 		       reply_q->name, pci_irq_vector(pdev, index));
3153 		kfree(reply_q);
3154 		return -EBUSY;
3155 	}
3156 out:
3157 	INIT_LIST_HEAD(&reply_q->list);
3158 	list_add_tail(&reply_q->list, &ioc->reply_queue_list);
3159 	return 0;
3160 }
3161 
3162 /**
3163  * _base_assign_reply_queues - assigning msix index for each cpu
3164  * @ioc: per adapter object
3165  *
3166  * The enduser would need to set the affinity via /proc/irq/#/smp_affinity
3167  */
3168 static void
3169 _base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc)
3170 {
3171 	unsigned int cpu, nr_cpus, nr_msix, index = 0, irq;
3172 	struct adapter_reply_queue *reply_q;
3173 	int iopoll_q_count = ioc->reply_queue_count -
3174 	    ioc->iopoll_q_start_index;
3175 	const struct cpumask *mask;
3176 
3177 	if (!_base_is_controller_msix_enabled(ioc))
3178 		return;
3179 
3180 	if (ioc->msix_load_balance)
3181 		return;
3182 
3183 	memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz);
3184 
3185 	nr_cpus = num_online_cpus();
3186 	nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count,
3187 					       ioc->facts.MaxMSIxVectors);
3188 	if (!nr_msix)
3189 		return;
3190 
3191 	if (ioc->smp_affinity_enable) {
3192 
3193 		/*
3194 		 * set irq affinity to local numa node for those irqs
3195 		 * corresponding to high iops queues.
3196 		 */
3197 		if (ioc->high_iops_queues) {
3198 			mask = cpumask_of_node(dev_to_node(&ioc->pdev->dev));
3199 			for (index = 0; index < ioc->high_iops_queues;
3200 			    index++) {
3201 				irq = pci_irq_vector(ioc->pdev, index);
3202 				irq_set_affinity_and_hint(irq, mask);
3203 			}
3204 		}
3205 
3206 		list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
3207 			const cpumask_t *mask;
3208 
3209 			if (reply_q->msix_index < ioc->high_iops_queues ||
3210 			    reply_q->msix_index >= ioc->iopoll_q_start_index)
3211 				continue;
3212 
3213 			mask = pci_irq_get_affinity(ioc->pdev,
3214 			    reply_q->msix_index);
3215 			if (!mask) {
3216 				ioc_warn(ioc, "no affinity for msi %x\n",
3217 					 reply_q->msix_index);
3218 				goto fall_back;
3219 			}
3220 
3221 			for_each_cpu_and(cpu, mask, cpu_online_mask) {
3222 				if (cpu >= ioc->cpu_msix_table_sz)
3223 					break;
3224 				ioc->cpu_msix_table[cpu] = reply_q->msix_index;
3225 			}
3226 		}
3227 		return;
3228 	}
3229 
3230 fall_back:
3231 	cpu = cpumask_first(cpu_online_mask);
3232 	nr_msix -= (ioc->high_iops_queues - iopoll_q_count);
3233 	index = 0;
3234 
3235 	list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
3236 		unsigned int i, group = nr_cpus / nr_msix;
3237 
3238 		if (reply_q->msix_index < ioc->high_iops_queues ||
3239 		    reply_q->msix_index >= ioc->iopoll_q_start_index)
3240 			continue;
3241 
3242 		if (cpu >= nr_cpus)
3243 			break;
3244 
3245 		if (index < nr_cpus % nr_msix)
3246 			group++;
3247 
3248 		for (i = 0 ; i < group ; i++) {
3249 			ioc->cpu_msix_table[cpu] = reply_q->msix_index;
3250 			cpu = cpumask_next(cpu, cpu_online_mask);
3251 		}
3252 		index++;
3253 	}
3254 }
3255 
3256 /**
3257  * _base_check_and_enable_high_iops_queues - enable high iops mode
3258  * @ioc: per adapter object
3259  * @hba_msix_vector_count: msix vectors supported by HBA
3260  *
3261  * Enable high iops queues only if
3262  *  - HBA is a SEA/AERO controller and
3263  *  - MSI-Xs vector supported by the HBA is 128 and
3264  *  - total CPU count in the system >=16 and
3265  *  - loaded driver with default max_msix_vectors module parameter and
3266  *  - system booted in non kdump mode
3267  *
3268  * Return: nothing.
3269  */
3270 static void
3271 _base_check_and_enable_high_iops_queues(struct MPT3SAS_ADAPTER *ioc,
3272 		int hba_msix_vector_count)
3273 {
3274 	u16 lnksta, speed;
3275 
3276 	/*
3277 	 * Disable high iops queues if io uring poll queues are enabled.
3278 	 */
3279 	if (perf_mode == MPT_PERF_MODE_IOPS ||
3280 	    perf_mode == MPT_PERF_MODE_LATENCY ||
3281 	    ioc->io_uring_poll_queues) {
3282 		ioc->high_iops_queues = 0;
3283 		return;
3284 	}
3285 
3286 	if (perf_mode == MPT_PERF_MODE_DEFAULT) {
3287 
3288 		pcie_capability_read_word(ioc->pdev, PCI_EXP_LNKSTA, &lnksta);
3289 		speed = lnksta & PCI_EXP_LNKSTA_CLS;
3290 
3291 		if (speed < 0x4) {
3292 			ioc->high_iops_queues = 0;
3293 			return;
3294 		}
3295 	}
3296 
3297 	if (!reset_devices && ioc->is_aero_ioc &&
3298 	    hba_msix_vector_count == MPT3SAS_GEN35_MAX_MSIX_QUEUES &&
3299 	    num_online_cpus() >= MPT3SAS_HIGH_IOPS_REPLY_QUEUES &&
3300 	    max_msix_vectors == -1)
3301 		ioc->high_iops_queues = MPT3SAS_HIGH_IOPS_REPLY_QUEUES;
3302 	else
3303 		ioc->high_iops_queues = 0;
3304 }
3305 
3306 /**
3307  * mpt3sas_base_disable_msix - disables msix
3308  * @ioc: per adapter object
3309  *
3310  */
3311 void
3312 mpt3sas_base_disable_msix(struct MPT3SAS_ADAPTER *ioc)
3313 {
3314 	if (!ioc->msix_enable)
3315 		return;
3316 	pci_free_irq_vectors(ioc->pdev);
3317 	ioc->msix_enable = 0;
3318 	kfree(ioc->io_uring_poll_queues);
3319 }
3320 
3321 /**
3322  * _base_alloc_irq_vectors - allocate msix vectors
3323  * @ioc: per adapter object
3324  *
3325  */
3326 static int
3327 _base_alloc_irq_vectors(struct MPT3SAS_ADAPTER *ioc)
3328 {
3329 	int i, irq_flags = PCI_IRQ_MSIX;
3330 	struct irq_affinity desc = { .pre_vectors = ioc->high_iops_queues };
3331 	struct irq_affinity *descp = &desc;
3332 	/*
3333 	 * Don't allocate msix vectors for poll_queues.
3334 	 * msix_vectors is always within a range of FW supported reply queue.
3335 	 */
3336 	int nr_msix_vectors = ioc->iopoll_q_start_index;
3337 
3338 
3339 	if (ioc->smp_affinity_enable)
3340 		irq_flags |= PCI_IRQ_AFFINITY | PCI_IRQ_ALL_TYPES;
3341 	else
3342 		descp = NULL;
3343 
3344 	ioc_info(ioc, " %d %d %d\n", ioc->high_iops_queues,
3345 	    ioc->reply_queue_count, nr_msix_vectors);
3346 
3347 	i = pci_alloc_irq_vectors_affinity(ioc->pdev,
3348 	    ioc->high_iops_queues,
3349 	    nr_msix_vectors, irq_flags, descp);
3350 
3351 	return i;
3352 }
3353 
3354 /**
3355  * _base_enable_msix - enables msix, failback to io_apic
3356  * @ioc: per adapter object
3357  *
3358  */
3359 static int
3360 _base_enable_msix(struct MPT3SAS_ADAPTER *ioc)
3361 {
3362 	int r;
3363 	int i, local_max_msix_vectors;
3364 	u8 try_msix = 0;
3365 	int iopoll_q_count = 0;
3366 
3367 	ioc->msix_load_balance = false;
3368 
3369 	if (msix_disable == -1 || msix_disable == 0)
3370 		try_msix = 1;
3371 
3372 	if (!try_msix)
3373 		goto try_ioapic;
3374 
3375 	if (_base_check_enable_msix(ioc) != 0)
3376 		goto try_ioapic;
3377 
3378 	ioc_info(ioc, "MSI-X vectors supported: %d\n", ioc->msix_vector_count);
3379 	pr_info("\t no of cores: %d, max_msix_vectors: %d\n",
3380 		ioc->cpu_count, max_msix_vectors);
3381 
3382 	ioc->reply_queue_count =
3383 		min_t(int, ioc->cpu_count, ioc->msix_vector_count);
3384 
3385 	if (!ioc->rdpq_array_enable && max_msix_vectors == -1)
3386 		local_max_msix_vectors = (reset_devices) ? 1 : 8;
3387 	else
3388 		local_max_msix_vectors = max_msix_vectors;
3389 
3390 	if (local_max_msix_vectors == 0)
3391 		goto try_ioapic;
3392 
3393 	/*
3394 	 * Enable msix_load_balance only if combined reply queue mode is
3395 	 * disabled on SAS3 & above generation HBA devices.
3396 	 */
3397 	if (!ioc->combined_reply_queue &&
3398 	    ioc->hba_mpi_version_belonged != MPI2_VERSION) {
3399 		ioc_info(ioc,
3400 		    "combined ReplyQueue is off, Enabling msix load balance\n");
3401 		ioc->msix_load_balance = true;
3402 	}
3403 
3404 	/*
3405 	 * smp affinity setting is not need when msix load balance
3406 	 * is enabled.
3407 	 */
3408 	if (ioc->msix_load_balance)
3409 		ioc->smp_affinity_enable = 0;
3410 
3411 	if (!ioc->smp_affinity_enable || ioc->reply_queue_count <= 1)
3412 		ioc->shost->host_tagset = 0;
3413 
3414 	/*
3415 	 * Enable io uring poll queues only if host_tagset is enabled.
3416 	 */
3417 	if (ioc->shost->host_tagset)
3418 		iopoll_q_count = poll_queues;
3419 
3420 	if (iopoll_q_count) {
3421 		ioc->io_uring_poll_queues = kcalloc(iopoll_q_count,
3422 		    sizeof(struct io_uring_poll_queue), GFP_KERNEL);
3423 		if (!ioc->io_uring_poll_queues)
3424 			iopoll_q_count = 0;
3425 	}
3426 
3427 	if (ioc->is_aero_ioc)
3428 		_base_check_and_enable_high_iops_queues(ioc,
3429 		    ioc->msix_vector_count);
3430 
3431 	/*
3432 	 * Add high iops queues count to reply queue count if high iops queues
3433 	 * are enabled.
3434 	 */
3435 	ioc->reply_queue_count = min_t(int,
3436 	    ioc->reply_queue_count + ioc->high_iops_queues,
3437 	    ioc->msix_vector_count);
3438 
3439 	/*
3440 	 * Adjust the reply queue count incase reply queue count
3441 	 * exceeds the user provided MSIx vectors count.
3442 	 */
3443 	if (local_max_msix_vectors > 0)
3444 		ioc->reply_queue_count = min_t(int, local_max_msix_vectors,
3445 		    ioc->reply_queue_count);
3446 	/*
3447 	 * Add io uring poll queues count to reply queues count
3448 	 * if io uring is enabled in driver.
3449 	 */
3450 	if (iopoll_q_count) {
3451 		if (ioc->reply_queue_count < (iopoll_q_count + MPT3_MIN_IRQS))
3452 			iopoll_q_count = 0;
3453 		ioc->reply_queue_count = min_t(int,
3454 		    ioc->reply_queue_count + iopoll_q_count,
3455 		    ioc->msix_vector_count);
3456 	}
3457 
3458 	/*
3459 	 * Starting index of io uring poll queues in reply queue list.
3460 	 */
3461 	ioc->iopoll_q_start_index =
3462 	    ioc->reply_queue_count - iopoll_q_count;
3463 
3464 	r = _base_alloc_irq_vectors(ioc);
3465 	if (r < 0) {
3466 		ioc_info(ioc, "pci_alloc_irq_vectors failed (r=%d) !!!\n", r);
3467 		goto try_ioapic;
3468 	}
3469 
3470 	/*
3471 	 * Adjust the reply queue count if the allocated
3472 	 * MSIx vectors is less then the requested number
3473 	 * of MSIx vectors.
3474 	 */
3475 	if (r < ioc->iopoll_q_start_index) {
3476 		ioc->reply_queue_count = r + iopoll_q_count;
3477 		ioc->iopoll_q_start_index =
3478 		    ioc->reply_queue_count - iopoll_q_count;
3479 	}
3480 
3481 	ioc->msix_enable = 1;
3482 	for (i = 0; i < ioc->reply_queue_count; i++) {
3483 		r = _base_request_irq(ioc, i);
3484 		if (r) {
3485 			mpt3sas_base_free_irq(ioc);
3486 			mpt3sas_base_disable_msix(ioc);
3487 			goto try_ioapic;
3488 		}
3489 	}
3490 
3491 	ioc_info(ioc, "High IOPs queues : %s\n",
3492 			ioc->high_iops_queues ? "enabled" : "disabled");
3493 
3494 	return 0;
3495 
3496 /* failback to io_apic interrupt routing */
3497  try_ioapic:
3498 	ioc->high_iops_queues = 0;
3499 	ioc_info(ioc, "High IOPs queues : disabled\n");
3500 	ioc->reply_queue_count = 1;
3501 	ioc->iopoll_q_start_index = ioc->reply_queue_count - 0;
3502 	r = pci_alloc_irq_vectors(ioc->pdev, 1, 1, PCI_IRQ_LEGACY);
3503 	if (r < 0) {
3504 		dfailprintk(ioc,
3505 			    ioc_info(ioc, "pci_alloc_irq_vector(legacy) failed (r=%d) !!!\n",
3506 				     r));
3507 	} else
3508 		r = _base_request_irq(ioc, 0);
3509 
3510 	return r;
3511 }
3512 
3513 /**
3514  * mpt3sas_base_unmap_resources - free controller resources
3515  * @ioc: per adapter object
3516  */
3517 static void
3518 mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc)
3519 {
3520 	struct pci_dev *pdev = ioc->pdev;
3521 
3522 	dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
3523 
3524 	mpt3sas_base_free_irq(ioc);
3525 	mpt3sas_base_disable_msix(ioc);
3526 
3527 	kfree(ioc->replyPostRegisterIndex);
3528 	ioc->replyPostRegisterIndex = NULL;
3529 
3530 
3531 	if (ioc->chip_phys) {
3532 		iounmap(ioc->chip);
3533 		ioc->chip_phys = 0;
3534 	}
3535 
3536 	if (pci_is_enabled(pdev)) {
3537 		pci_release_selected_regions(ioc->pdev, ioc->bars);
3538 		pci_disable_pcie_error_reporting(pdev);
3539 		pci_disable_device(pdev);
3540 	}
3541 }
3542 
3543 static int
3544 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc);
3545 
3546 /**
3547  * mpt3sas_base_check_for_fault_and_issue_reset - check if IOC is in fault state
3548  *     and if it is in fault state then issue diag reset.
3549  * @ioc: per adapter object
3550  *
3551  * Return: 0 for success, non-zero for failure.
3552  */
3553 int
3554 mpt3sas_base_check_for_fault_and_issue_reset(struct MPT3SAS_ADAPTER *ioc)
3555 {
3556 	u32 ioc_state;
3557 	int rc = -EFAULT;
3558 
3559 	dinitprintk(ioc, pr_info("%s\n", __func__));
3560 	if (ioc->pci_error_recovery)
3561 		return 0;
3562 	ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
3563 	dhsprintk(ioc, pr_info("%s: ioc_state(0x%08x)\n", __func__, ioc_state));
3564 
3565 	if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
3566 		mpt3sas_print_fault_code(ioc, ioc_state &
3567 		    MPI2_DOORBELL_DATA_MASK);
3568 		mpt3sas_base_mask_interrupts(ioc);
3569 		rc = _base_diag_reset(ioc);
3570 	} else if ((ioc_state & MPI2_IOC_STATE_MASK) ==
3571 	    MPI2_IOC_STATE_COREDUMP) {
3572 		mpt3sas_print_coredump_info(ioc, ioc_state &
3573 		     MPI2_DOORBELL_DATA_MASK);
3574 		mpt3sas_base_wait_for_coredump_completion(ioc, __func__);
3575 		mpt3sas_base_mask_interrupts(ioc);
3576 		rc = _base_diag_reset(ioc);
3577 	}
3578 
3579 	return rc;
3580 }
3581 
3582 /**
3583  * mpt3sas_base_map_resources - map in controller resources (io/irq/memap)
3584  * @ioc: per adapter object
3585  *
3586  * Return: 0 for success, non-zero for failure.
3587  */
3588 int
3589 mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
3590 {
3591 	struct pci_dev *pdev = ioc->pdev;
3592 	u32 memap_sz;
3593 	u32 pio_sz;
3594 	int i, r = 0, rc;
3595 	u64 pio_chip = 0;
3596 	phys_addr_t chip_phys = 0;
3597 	struct adapter_reply_queue *reply_q;
3598 	int iopoll_q_count = 0;
3599 
3600 	dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
3601 
3602 	ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
3603 	if (pci_enable_device_mem(pdev)) {
3604 		ioc_warn(ioc, "pci_enable_device_mem: failed\n");
3605 		ioc->bars = 0;
3606 		return -ENODEV;
3607 	}
3608 
3609 
3610 	if (pci_request_selected_regions(pdev, ioc->bars,
3611 	    ioc->driver_name)) {
3612 		ioc_warn(ioc, "pci_request_selected_regions: failed\n");
3613 		ioc->bars = 0;
3614 		r = -ENODEV;
3615 		goto out_fail;
3616 	}
3617 
3618 /* AER (Advanced Error Reporting) hooks */
3619 	pci_enable_pcie_error_reporting(pdev);
3620 
3621 	pci_set_master(pdev);
3622 
3623 
3624 	if (_base_config_dma_addressing(ioc, pdev) != 0) {
3625 		ioc_warn(ioc, "no suitable DMA mask for %s\n", pci_name(pdev));
3626 		r = -ENODEV;
3627 		goto out_fail;
3628 	}
3629 
3630 	for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) &&
3631 	     (!memap_sz || !pio_sz); i++) {
3632 		if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
3633 			if (pio_sz)
3634 				continue;
3635 			pio_chip = (u64)pci_resource_start(pdev, i);
3636 			pio_sz = pci_resource_len(pdev, i);
3637 		} else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3638 			if (memap_sz)
3639 				continue;
3640 			ioc->chip_phys = pci_resource_start(pdev, i);
3641 			chip_phys = ioc->chip_phys;
3642 			memap_sz = pci_resource_len(pdev, i);
3643 			ioc->chip = ioremap(ioc->chip_phys, memap_sz);
3644 		}
3645 	}
3646 
3647 	if (ioc->chip == NULL) {
3648 		ioc_err(ioc,
3649 		    "unable to map adapter memory! or resource not found\n");
3650 		r = -EINVAL;
3651 		goto out_fail;
3652 	}
3653 
3654 	mpt3sas_base_mask_interrupts(ioc);
3655 
3656 	r = _base_get_ioc_facts(ioc);
3657 	if (r) {
3658 		rc = mpt3sas_base_check_for_fault_and_issue_reset(ioc);
3659 		if (rc || (_base_get_ioc_facts(ioc)))
3660 			goto out_fail;
3661 	}
3662 
3663 	if (!ioc->rdpq_array_enable_assigned) {
3664 		ioc->rdpq_array_enable = ioc->rdpq_array_capable;
3665 		ioc->rdpq_array_enable_assigned = 1;
3666 	}
3667 
3668 	r = _base_enable_msix(ioc);
3669 	if (r)
3670 		goto out_fail;
3671 
3672 	iopoll_q_count = ioc->reply_queue_count - ioc->iopoll_q_start_index;
3673 	for (i = 0; i < iopoll_q_count; i++) {
3674 		atomic_set(&ioc->io_uring_poll_queues[i].busy, 0);
3675 		atomic_set(&ioc->io_uring_poll_queues[i].pause, 0);
3676 	}
3677 
3678 	if (!ioc->is_driver_loading)
3679 		_base_init_irqpolls(ioc);
3680 	/* Use the Combined reply queue feature only for SAS3 C0 & higher
3681 	 * revision HBAs and also only when reply queue count is greater than 8
3682 	 */
3683 	if (ioc->combined_reply_queue) {
3684 		/* Determine the Supplemental Reply Post Host Index Registers
3685 		 * Addresse. Supplemental Reply Post Host Index Registers
3686 		 * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and
3687 		 * each register is at offset bytes of
3688 		 * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one.
3689 		 */
3690 		ioc->replyPostRegisterIndex = kcalloc(
3691 		     ioc->combined_reply_index_count,
3692 		     sizeof(resource_size_t *), GFP_KERNEL);
3693 		if (!ioc->replyPostRegisterIndex) {
3694 			ioc_err(ioc,
3695 			    "allocation for replyPostRegisterIndex failed!\n");
3696 			r = -ENOMEM;
3697 			goto out_fail;
3698 		}
3699 
3700 		for (i = 0; i < ioc->combined_reply_index_count; i++) {
3701 			ioc->replyPostRegisterIndex[i] =
3702 				(resource_size_t __iomem *)
3703 				((u8 __force *)&ioc->chip->Doorbell +
3704 				 MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET +
3705 				 (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET));
3706 		}
3707 	}
3708 
3709 	if (ioc->is_warpdrive) {
3710 		ioc->reply_post_host_index[0] = (resource_size_t __iomem *)
3711 		    &ioc->chip->ReplyPostHostIndex;
3712 
3713 		for (i = 1; i < ioc->cpu_msix_table_sz; i++)
3714 			ioc->reply_post_host_index[i] =
3715 			(resource_size_t __iomem *)
3716 			((u8 __iomem *)&ioc->chip->Doorbell + (0x4000 + ((i - 1)
3717 			* 4)));
3718 	}
3719 
3720 	list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
3721 		if (reply_q->msix_index >= ioc->iopoll_q_start_index) {
3722 			pr_info("%s: enabled: index: %d\n",
3723 			    reply_q->name, reply_q->msix_index);
3724 			continue;
3725 		}
3726 
3727 		pr_info("%s: %s enabled: IRQ %d\n",
3728 			reply_q->name,
3729 			ioc->msix_enable ? "PCI-MSI-X" : "IO-APIC",
3730 			pci_irq_vector(ioc->pdev, reply_q->msix_index));
3731 	}
3732 
3733 	ioc_info(ioc, "iomem(%pap), mapped(0x%p), size(%d)\n",
3734 		 &chip_phys, ioc->chip, memap_sz);
3735 	ioc_info(ioc, "ioport(0x%016llx), size(%d)\n",
3736 		 (unsigned long long)pio_chip, pio_sz);
3737 
3738 	/* Save PCI configuration state for recovery from PCI AER/EEH errors */
3739 	pci_save_state(pdev);
3740 	return 0;
3741 
3742  out_fail:
3743 	mpt3sas_base_unmap_resources(ioc);
3744 	return r;
3745 }
3746 
3747 /**
3748  * mpt3sas_base_get_msg_frame - obtain request mf pointer
3749  * @ioc: per adapter object
3750  * @smid: system request message index(smid zero is invalid)
3751  *
3752  * Return: virt pointer to message frame.
3753  */
3754 void *
3755 mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3756 {
3757 	return (void *)(ioc->request + (smid * ioc->request_sz));
3758 }
3759 
3760 /**
3761  * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr
3762  * @ioc: per adapter object
3763  * @smid: system request message index
3764  *
3765  * Return: virt pointer to sense buffer.
3766  */
3767 void *
3768 mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3769 {
3770 	return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
3771 }
3772 
3773 /**
3774  * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr
3775  * @ioc: per adapter object
3776  * @smid: system request message index
3777  *
3778  * Return: phys pointer to the low 32bit address of the sense buffer.
3779  */
3780 __le32
3781 mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3782 {
3783 	return cpu_to_le32(ioc->sense_dma + ((smid - 1) *
3784 	    SCSI_SENSE_BUFFERSIZE));
3785 }
3786 
3787 /**
3788  * mpt3sas_base_get_pcie_sgl - obtain a PCIe SGL virt addr
3789  * @ioc: per adapter object
3790  * @smid: system request message index
3791  *
3792  * Return: virt pointer to a PCIe SGL.
3793  */
3794 void *
3795 mpt3sas_base_get_pcie_sgl(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3796 {
3797 	return (void *)(ioc->pcie_sg_lookup[smid - 1].pcie_sgl);
3798 }
3799 
3800 /**
3801  * mpt3sas_base_get_pcie_sgl_dma - obtain a PCIe SGL dma addr
3802  * @ioc: per adapter object
3803  * @smid: system request message index
3804  *
3805  * Return: phys pointer to the address of the PCIe buffer.
3806  */
3807 dma_addr_t
3808 mpt3sas_base_get_pcie_sgl_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3809 {
3810 	return ioc->pcie_sg_lookup[smid - 1].pcie_sgl_dma;
3811 }
3812 
3813 /**
3814  * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address
3815  * @ioc: per adapter object
3816  * @phys_addr: lower 32 physical addr of the reply
3817  *
3818  * Converts 32bit lower physical addr into a virt address.
3819  */
3820 void *
3821 mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr)
3822 {
3823 	if (!phys_addr)
3824 		return NULL;
3825 	return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
3826 }
3827 
3828 /**
3829  * _base_get_msix_index - get the msix index
3830  * @ioc: per adapter object
3831  * @scmd: scsi_cmnd object
3832  *
3833  * Return: msix index of general reply queues,
3834  * i.e. reply queue on which IO request's reply
3835  * should be posted by the HBA firmware.
3836  */
3837 static inline u8
3838 _base_get_msix_index(struct MPT3SAS_ADAPTER *ioc,
3839 	struct scsi_cmnd *scmd)
3840 {
3841 	/* Enables reply_queue load balancing */
3842 	if (ioc->msix_load_balance)
3843 		return ioc->reply_queue_count ?
3844 		    base_mod64(atomic64_add_return(1,
3845 		    &ioc->total_io_cnt), ioc->reply_queue_count) : 0;
3846 
3847 	if (scmd && ioc->shost->nr_hw_queues > 1) {
3848 		u32 tag = blk_mq_unique_tag(scsi_cmd_to_rq(scmd));
3849 
3850 		return blk_mq_unique_tag_to_hwq(tag) +
3851 			ioc->high_iops_queues;
3852 	}
3853 
3854 	return ioc->cpu_msix_table[raw_smp_processor_id()];
3855 }
3856 
3857 /**
3858  * _base_get_high_iops_msix_index - get the msix index of
3859  *				high iops queues
3860  * @ioc: per adapter object
3861  * @scmd: scsi_cmnd object
3862  *
3863  * Return: msix index of high iops reply queues.
3864  * i.e. high iops reply queue on which IO request's
3865  * reply should be posted by the HBA firmware.
3866  */
3867 static inline u8
3868 _base_get_high_iops_msix_index(struct MPT3SAS_ADAPTER *ioc,
3869 	struct scsi_cmnd *scmd)
3870 {
3871 	/**
3872 	 * Round robin the IO interrupts among the high iops
3873 	 * reply queues in terms of batch count 16 when outstanding
3874 	 * IOs on the target device is >=8.
3875 	 */
3876 
3877 	if (scsi_device_busy(scmd->device) > MPT3SAS_DEVICE_HIGH_IOPS_DEPTH)
3878 		return base_mod64((
3879 		    atomic64_add_return(1, &ioc->high_iops_outstanding) /
3880 		    MPT3SAS_HIGH_IOPS_BATCH_COUNT),
3881 		    MPT3SAS_HIGH_IOPS_REPLY_QUEUES);
3882 
3883 	return _base_get_msix_index(ioc, scmd);
3884 }
3885 
3886 /**
3887  * mpt3sas_base_get_smid - obtain a free smid from internal queue
3888  * @ioc: per adapter object
3889  * @cb_idx: callback index
3890  *
3891  * Return: smid (zero is invalid)
3892  */
3893 u16
3894 mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
3895 {
3896 	unsigned long flags;
3897 	struct request_tracker *request;
3898 	u16 smid;
3899 
3900 	spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
3901 	if (list_empty(&ioc->internal_free_list)) {
3902 		spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3903 		ioc_err(ioc, "%s: smid not available\n", __func__);
3904 		return 0;
3905 	}
3906 
3907 	request = list_entry(ioc->internal_free_list.next,
3908 	    struct request_tracker, tracker_list);
3909 	request->cb_idx = cb_idx;
3910 	smid = request->smid;
3911 	list_del(&request->tracker_list);
3912 	spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3913 	return smid;
3914 }
3915 
3916 /**
3917  * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue
3918  * @ioc: per adapter object
3919  * @cb_idx: callback index
3920  * @scmd: pointer to scsi command object
3921  *
3922  * Return: smid (zero is invalid)
3923  */
3924 u16
3925 mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx,
3926 	struct scsi_cmnd *scmd)
3927 {
3928 	struct scsiio_tracker *request = scsi_cmd_priv(scmd);
3929 	u16 smid;
3930 	u32 tag, unique_tag;
3931 
3932 	unique_tag = blk_mq_unique_tag(scsi_cmd_to_rq(scmd));
3933 	tag = blk_mq_unique_tag_to_tag(unique_tag);
3934 
3935 	/*
3936 	 * Store hw queue number corresponding to the tag.
3937 	 * This hw queue number is used later to determine
3938 	 * the unique_tag using the logic below. This unique_tag
3939 	 * is used to retrieve the scmd pointer corresponding
3940 	 * to tag using scsi_host_find_tag() API.
3941 	 *
3942 	 * tag = smid - 1;
3943 	 * unique_tag = ioc->io_queue_num[tag] << BLK_MQ_UNIQUE_TAG_BITS | tag;
3944 	 */
3945 	ioc->io_queue_num[tag] = blk_mq_unique_tag_to_hwq(unique_tag);
3946 
3947 	smid = tag + 1;
3948 	request->cb_idx = cb_idx;
3949 	request->smid = smid;
3950 	request->scmd = scmd;
3951 	INIT_LIST_HEAD(&request->chain_list);
3952 	return smid;
3953 }
3954 
3955 /**
3956  * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue
3957  * @ioc: per adapter object
3958  * @cb_idx: callback index
3959  *
3960  * Return: smid (zero is invalid)
3961  */
3962 u16
3963 mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
3964 {
3965 	unsigned long flags;
3966 	struct request_tracker *request;
3967 	u16 smid;
3968 
3969 	spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
3970 	if (list_empty(&ioc->hpr_free_list)) {
3971 		spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3972 		return 0;
3973 	}
3974 
3975 	request = list_entry(ioc->hpr_free_list.next,
3976 	    struct request_tracker, tracker_list);
3977 	request->cb_idx = cb_idx;
3978 	smid = request->smid;
3979 	list_del(&request->tracker_list);
3980 	spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3981 	return smid;
3982 }
3983 
3984 static void
3985 _base_recovery_check(struct MPT3SAS_ADAPTER *ioc)
3986 {
3987 	/*
3988 	 * See _wait_for_commands_to_complete() call with regards to this code.
3989 	 */
3990 	if (ioc->shost_recovery && ioc->pending_io_count) {
3991 		ioc->pending_io_count = scsi_host_busy(ioc->shost);
3992 		if (ioc->pending_io_count == 0)
3993 			wake_up(&ioc->reset_wq);
3994 	}
3995 }
3996 
3997 void mpt3sas_base_clear_st(struct MPT3SAS_ADAPTER *ioc,
3998 			   struct scsiio_tracker *st)
3999 {
4000 	if (WARN_ON(st->smid == 0))
4001 		return;
4002 	st->cb_idx = 0xFF;
4003 	st->direct_io = 0;
4004 	st->scmd = NULL;
4005 	atomic_set(&ioc->chain_lookup[st->smid - 1].chain_offset, 0);
4006 	st->smid = 0;
4007 }
4008 
4009 /**
4010  * mpt3sas_base_free_smid - put smid back on free_list
4011  * @ioc: per adapter object
4012  * @smid: system request message index
4013  */
4014 void
4015 mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
4016 {
4017 	unsigned long flags;
4018 	int i;
4019 
4020 	if (smid < ioc->hi_priority_smid) {
4021 		struct scsiio_tracker *st;
4022 		void *request;
4023 
4024 		st = _get_st_from_smid(ioc, smid);
4025 		if (!st) {
4026 			_base_recovery_check(ioc);
4027 			return;
4028 		}
4029 
4030 		/* Clear MPI request frame */
4031 		request = mpt3sas_base_get_msg_frame(ioc, smid);
4032 		memset(request, 0, ioc->request_sz);
4033 
4034 		mpt3sas_base_clear_st(ioc, st);
4035 		_base_recovery_check(ioc);
4036 		ioc->io_queue_num[smid - 1] = 0;
4037 		return;
4038 	}
4039 
4040 	spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
4041 	if (smid < ioc->internal_smid) {
4042 		/* hi-priority */
4043 		i = smid - ioc->hi_priority_smid;
4044 		ioc->hpr_lookup[i].cb_idx = 0xFF;
4045 		list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list);
4046 	} else if (smid <= ioc->hba_queue_depth) {
4047 		/* internal queue */
4048 		i = smid - ioc->internal_smid;
4049 		ioc->internal_lookup[i].cb_idx = 0xFF;
4050 		list_add(&ioc->internal_lookup[i].tracker_list,
4051 		    &ioc->internal_free_list);
4052 	}
4053 	spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
4054 }
4055 
4056 /**
4057  * _base_mpi_ep_writeq - 32 bit write to MMIO
4058  * @b: data payload
4059  * @addr: address in MMIO space
4060  * @writeq_lock: spin lock
4061  *
4062  * This special handling for MPI EP to take care of 32 bit
4063  * environment where its not quarenteed to send the entire word
4064  * in one transfer.
4065  */
4066 static inline void
4067 _base_mpi_ep_writeq(__u64 b, volatile void __iomem *addr,
4068 					spinlock_t *writeq_lock)
4069 {
4070 	unsigned long flags;
4071 
4072 	spin_lock_irqsave(writeq_lock, flags);
4073 	__raw_writel((u32)(b), addr);
4074 	__raw_writel((u32)(b >> 32), (addr + 4));
4075 	spin_unlock_irqrestore(writeq_lock, flags);
4076 }
4077 
4078 /**
4079  * _base_writeq - 64 bit write to MMIO
4080  * @b: data payload
4081  * @addr: address in MMIO space
4082  * @writeq_lock: spin lock
4083  *
4084  * Glue for handling an atomic 64 bit word to MMIO. This special handling takes
4085  * care of 32 bit environment where its not quarenteed to send the entire word
4086  * in one transfer.
4087  */
4088 #if defined(writeq) && defined(CONFIG_64BIT)
4089 static inline void
4090 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
4091 {
4092 	wmb();
4093 	__raw_writeq(b, addr);
4094 	barrier();
4095 }
4096 #else
4097 static inline void
4098 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
4099 {
4100 	_base_mpi_ep_writeq(b, addr, writeq_lock);
4101 }
4102 #endif
4103 
4104 /**
4105  * _base_set_and_get_msix_index - get the msix index and assign to msix_io
4106  *                                variable of scsi tracker
4107  * @ioc: per adapter object
4108  * @smid: system request message index
4109  *
4110  * Return: msix index.
4111  */
4112 static u8
4113 _base_set_and_get_msix_index(struct MPT3SAS_ADAPTER *ioc, u16 smid)
4114 {
4115 	struct scsiio_tracker *st = NULL;
4116 
4117 	if (smid < ioc->hi_priority_smid)
4118 		st = _get_st_from_smid(ioc, smid);
4119 
4120 	if (st == NULL)
4121 		return  _base_get_msix_index(ioc, NULL);
4122 
4123 	st->msix_io = ioc->get_msix_index_for_smlio(ioc, st->scmd);
4124 	return st->msix_io;
4125 }
4126 
4127 /**
4128  * _base_put_smid_mpi_ep_scsi_io - send SCSI_IO request to firmware
4129  * @ioc: per adapter object
4130  * @smid: system request message index
4131  * @handle: device handle
4132  */
4133 static void
4134 _base_put_smid_mpi_ep_scsi_io(struct MPT3SAS_ADAPTER *ioc,
4135 	u16 smid, u16 handle)
4136 {
4137 	Mpi2RequestDescriptorUnion_t descriptor;
4138 	u64 *request = (u64 *)&descriptor;
4139 	void *mpi_req_iomem;
4140 	__le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid);
4141 
4142 	_clone_sg_entries(ioc, (void *) mfp, smid);
4143 	mpi_req_iomem = (void __force *)ioc->chip +
4144 			MPI_FRAME_START_OFFSET + (smid * ioc->request_sz);
4145 	_base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp,
4146 					ioc->request_sz);
4147 	descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
4148 	descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4149 	descriptor.SCSIIO.SMID = cpu_to_le16(smid);
4150 	descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
4151 	descriptor.SCSIIO.LMID = 0;
4152 	_base_mpi_ep_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
4153 	    &ioc->scsi_lookup_lock);
4154 }
4155 
4156 /**
4157  * _base_put_smid_scsi_io - send SCSI_IO request to firmware
4158  * @ioc: per adapter object
4159  * @smid: system request message index
4160  * @handle: device handle
4161  */
4162 static void
4163 _base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle)
4164 {
4165 	Mpi2RequestDescriptorUnion_t descriptor;
4166 	u64 *request = (u64 *)&descriptor;
4167 
4168 
4169 	descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
4170 	descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4171 	descriptor.SCSIIO.SMID = cpu_to_le16(smid);
4172 	descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
4173 	descriptor.SCSIIO.LMID = 0;
4174 	_base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
4175 	    &ioc->scsi_lookup_lock);
4176 }
4177 
4178 /**
4179  * _base_put_smid_fast_path - send fast path request to firmware
4180  * @ioc: per adapter object
4181  * @smid: system request message index
4182  * @handle: device handle
4183  */
4184 static void
4185 _base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid,
4186 	u16 handle)
4187 {
4188 	Mpi2RequestDescriptorUnion_t descriptor;
4189 	u64 *request = (u64 *)&descriptor;
4190 
4191 	descriptor.SCSIIO.RequestFlags =
4192 	    MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
4193 	descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4194 	descriptor.SCSIIO.SMID = cpu_to_le16(smid);
4195 	descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
4196 	descriptor.SCSIIO.LMID = 0;
4197 	_base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
4198 	    &ioc->scsi_lookup_lock);
4199 }
4200 
4201 /**
4202  * _base_put_smid_hi_priority - send Task Management request to firmware
4203  * @ioc: per adapter object
4204  * @smid: system request message index
4205  * @msix_task: msix_task will be same as msix of IO in case of task abort else 0
4206  */
4207 static void
4208 _base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid,
4209 	u16 msix_task)
4210 {
4211 	Mpi2RequestDescriptorUnion_t descriptor;
4212 	void *mpi_req_iomem;
4213 	u64 *request;
4214 
4215 	if (ioc->is_mcpu_endpoint) {
4216 		__le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid);
4217 
4218 		/* TBD 256 is offset within sys register. */
4219 		mpi_req_iomem = (void __force *)ioc->chip
4220 					+ MPI_FRAME_START_OFFSET
4221 					+ (smid * ioc->request_sz);
4222 		_base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp,
4223 							ioc->request_sz);
4224 	}
4225 
4226 	request = (u64 *)&descriptor;
4227 
4228 	descriptor.HighPriority.RequestFlags =
4229 	    MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
4230 	descriptor.HighPriority.MSIxIndex =  msix_task;
4231 	descriptor.HighPriority.SMID = cpu_to_le16(smid);
4232 	descriptor.HighPriority.LMID = 0;
4233 	descriptor.HighPriority.Reserved1 = 0;
4234 	if (ioc->is_mcpu_endpoint)
4235 		_base_mpi_ep_writeq(*request,
4236 				&ioc->chip->RequestDescriptorPostLow,
4237 				&ioc->scsi_lookup_lock);
4238 	else
4239 		_base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
4240 		    &ioc->scsi_lookup_lock);
4241 }
4242 
4243 /**
4244  * mpt3sas_base_put_smid_nvme_encap - send NVMe encapsulated request to
4245  *  firmware
4246  * @ioc: per adapter object
4247  * @smid: system request message index
4248  */
4249 void
4250 mpt3sas_base_put_smid_nvme_encap(struct MPT3SAS_ADAPTER *ioc, u16 smid)
4251 {
4252 	Mpi2RequestDescriptorUnion_t descriptor;
4253 	u64 *request = (u64 *)&descriptor;
4254 
4255 	descriptor.Default.RequestFlags =
4256 		MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED;
4257 	descriptor.Default.MSIxIndex =  _base_set_and_get_msix_index(ioc, smid);
4258 	descriptor.Default.SMID = cpu_to_le16(smid);
4259 	descriptor.Default.LMID = 0;
4260 	descriptor.Default.DescriptorTypeDependent = 0;
4261 	_base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
4262 	    &ioc->scsi_lookup_lock);
4263 }
4264 
4265 /**
4266  * _base_put_smid_default - Default, primarily used for config pages
4267  * @ioc: per adapter object
4268  * @smid: system request message index
4269  */
4270 static void
4271 _base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid)
4272 {
4273 	Mpi2RequestDescriptorUnion_t descriptor;
4274 	void *mpi_req_iomem;
4275 	u64 *request;
4276 
4277 	if (ioc->is_mcpu_endpoint) {
4278 		__le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid);
4279 
4280 		_clone_sg_entries(ioc, (void *) mfp, smid);
4281 		/* TBD 256 is offset within sys register */
4282 		mpi_req_iomem = (void __force *)ioc->chip +
4283 			MPI_FRAME_START_OFFSET + (smid * ioc->request_sz);
4284 		_base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp,
4285 							ioc->request_sz);
4286 	}
4287 	request = (u64 *)&descriptor;
4288 	descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
4289 	descriptor.Default.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4290 	descriptor.Default.SMID = cpu_to_le16(smid);
4291 	descriptor.Default.LMID = 0;
4292 	descriptor.Default.DescriptorTypeDependent = 0;
4293 	if (ioc->is_mcpu_endpoint)
4294 		_base_mpi_ep_writeq(*request,
4295 				&ioc->chip->RequestDescriptorPostLow,
4296 				&ioc->scsi_lookup_lock);
4297 	else
4298 		_base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
4299 				&ioc->scsi_lookup_lock);
4300 }
4301 
4302 /**
4303  * _base_put_smid_scsi_io_atomic - send SCSI_IO request to firmware using
4304  *   Atomic Request Descriptor
4305  * @ioc: per adapter object
4306  * @smid: system request message index
4307  * @handle: device handle, unused in this function, for function type match
4308  *
4309  * Return: nothing.
4310  */
4311 static void
4312 _base_put_smid_scsi_io_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
4313 	u16 handle)
4314 {
4315 	Mpi26AtomicRequestDescriptor_t descriptor;
4316 	u32 *request = (u32 *)&descriptor;
4317 
4318 	descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
4319 	descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4320 	descriptor.SMID = cpu_to_le16(smid);
4321 
4322 	writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
4323 }
4324 
4325 /**
4326  * _base_put_smid_fast_path_atomic - send fast path request to firmware
4327  * using Atomic Request Descriptor
4328  * @ioc: per adapter object
4329  * @smid: system request message index
4330  * @handle: device handle, unused in this function, for function type match
4331  * Return: nothing
4332  */
4333 static void
4334 _base_put_smid_fast_path_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
4335 	u16 handle)
4336 {
4337 	Mpi26AtomicRequestDescriptor_t descriptor;
4338 	u32 *request = (u32 *)&descriptor;
4339 
4340 	descriptor.RequestFlags = MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
4341 	descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4342 	descriptor.SMID = cpu_to_le16(smid);
4343 
4344 	writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
4345 }
4346 
4347 /**
4348  * _base_put_smid_hi_priority_atomic - send Task Management request to
4349  * firmware using Atomic Request Descriptor
4350  * @ioc: per adapter object
4351  * @smid: system request message index
4352  * @msix_task: msix_task will be same as msix of IO in case of task abort else 0
4353  *
4354  * Return: nothing.
4355  */
4356 static void
4357 _base_put_smid_hi_priority_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
4358 	u16 msix_task)
4359 {
4360 	Mpi26AtomicRequestDescriptor_t descriptor;
4361 	u32 *request = (u32 *)&descriptor;
4362 
4363 	descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
4364 	descriptor.MSIxIndex = msix_task;
4365 	descriptor.SMID = cpu_to_le16(smid);
4366 
4367 	writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
4368 }
4369 
4370 /**
4371  * _base_put_smid_default_atomic - Default, primarily used for config pages
4372  * use Atomic Request Descriptor
4373  * @ioc: per adapter object
4374  * @smid: system request message index
4375  *
4376  * Return: nothing.
4377  */
4378 static void
4379 _base_put_smid_default_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid)
4380 {
4381 	Mpi26AtomicRequestDescriptor_t descriptor;
4382 	u32 *request = (u32 *)&descriptor;
4383 
4384 	descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
4385 	descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4386 	descriptor.SMID = cpu_to_le16(smid);
4387 
4388 	writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
4389 }
4390 
4391 /**
4392  * _base_display_OEMs_branding - Display branding string
4393  * @ioc: per adapter object
4394  */
4395 static void
4396 _base_display_OEMs_branding(struct MPT3SAS_ADAPTER *ioc)
4397 {
4398 	if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL)
4399 		return;
4400 
4401 	switch (ioc->pdev->subsystem_vendor) {
4402 	case PCI_VENDOR_ID_INTEL:
4403 		switch (ioc->pdev->device) {
4404 		case MPI2_MFGPAGE_DEVID_SAS2008:
4405 			switch (ioc->pdev->subsystem_device) {
4406 			case MPT2SAS_INTEL_RMS2LL080_SSDID:
4407 				ioc_info(ioc, "%s\n",
4408 					 MPT2SAS_INTEL_RMS2LL080_BRANDING);
4409 				break;
4410 			case MPT2SAS_INTEL_RMS2LL040_SSDID:
4411 				ioc_info(ioc, "%s\n",
4412 					 MPT2SAS_INTEL_RMS2LL040_BRANDING);
4413 				break;
4414 			case MPT2SAS_INTEL_SSD910_SSDID:
4415 				ioc_info(ioc, "%s\n",
4416 					 MPT2SAS_INTEL_SSD910_BRANDING);
4417 				break;
4418 			default:
4419 				ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
4420 					 ioc->pdev->subsystem_device);
4421 				break;
4422 			}
4423 			break;
4424 		case MPI2_MFGPAGE_DEVID_SAS2308_2:
4425 			switch (ioc->pdev->subsystem_device) {
4426 			case MPT2SAS_INTEL_RS25GB008_SSDID:
4427 				ioc_info(ioc, "%s\n",
4428 					 MPT2SAS_INTEL_RS25GB008_BRANDING);
4429 				break;
4430 			case MPT2SAS_INTEL_RMS25JB080_SSDID:
4431 				ioc_info(ioc, "%s\n",
4432 					 MPT2SAS_INTEL_RMS25JB080_BRANDING);
4433 				break;
4434 			case MPT2SAS_INTEL_RMS25JB040_SSDID:
4435 				ioc_info(ioc, "%s\n",
4436 					 MPT2SAS_INTEL_RMS25JB040_BRANDING);
4437 				break;
4438 			case MPT2SAS_INTEL_RMS25KB080_SSDID:
4439 				ioc_info(ioc, "%s\n",
4440 					 MPT2SAS_INTEL_RMS25KB080_BRANDING);
4441 				break;
4442 			case MPT2SAS_INTEL_RMS25KB040_SSDID:
4443 				ioc_info(ioc, "%s\n",
4444 					 MPT2SAS_INTEL_RMS25KB040_BRANDING);
4445 				break;
4446 			case MPT2SAS_INTEL_RMS25LB040_SSDID:
4447 				ioc_info(ioc, "%s\n",
4448 					 MPT2SAS_INTEL_RMS25LB040_BRANDING);
4449 				break;
4450 			case MPT2SAS_INTEL_RMS25LB080_SSDID:
4451 				ioc_info(ioc, "%s\n",
4452 					 MPT2SAS_INTEL_RMS25LB080_BRANDING);
4453 				break;
4454 			default:
4455 				ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
4456 					 ioc->pdev->subsystem_device);
4457 				break;
4458 			}
4459 			break;
4460 		case MPI25_MFGPAGE_DEVID_SAS3008:
4461 			switch (ioc->pdev->subsystem_device) {
4462 			case MPT3SAS_INTEL_RMS3JC080_SSDID:
4463 				ioc_info(ioc, "%s\n",
4464 					 MPT3SAS_INTEL_RMS3JC080_BRANDING);
4465 				break;
4466 
4467 			case MPT3SAS_INTEL_RS3GC008_SSDID:
4468 				ioc_info(ioc, "%s\n",
4469 					 MPT3SAS_INTEL_RS3GC008_BRANDING);
4470 				break;
4471 			case MPT3SAS_INTEL_RS3FC044_SSDID:
4472 				ioc_info(ioc, "%s\n",
4473 					 MPT3SAS_INTEL_RS3FC044_BRANDING);
4474 				break;
4475 			case MPT3SAS_INTEL_RS3UC080_SSDID:
4476 				ioc_info(ioc, "%s\n",
4477 					 MPT3SAS_INTEL_RS3UC080_BRANDING);
4478 				break;
4479 			default:
4480 				ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
4481 					 ioc->pdev->subsystem_device);
4482 				break;
4483 			}
4484 			break;
4485 		default:
4486 			ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
4487 				 ioc->pdev->subsystem_device);
4488 			break;
4489 		}
4490 		break;
4491 	case PCI_VENDOR_ID_DELL:
4492 		switch (ioc->pdev->device) {
4493 		case MPI2_MFGPAGE_DEVID_SAS2008:
4494 			switch (ioc->pdev->subsystem_device) {
4495 			case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID:
4496 				ioc_info(ioc, "%s\n",
4497 					 MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING);
4498 				break;
4499 			case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID:
4500 				ioc_info(ioc, "%s\n",
4501 					 MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING);
4502 				break;
4503 			case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID:
4504 				ioc_info(ioc, "%s\n",
4505 					 MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING);
4506 				break;
4507 			case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID:
4508 				ioc_info(ioc, "%s\n",
4509 					 MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING);
4510 				break;
4511 			case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID:
4512 				ioc_info(ioc, "%s\n",
4513 					 MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING);
4514 				break;
4515 			case MPT2SAS_DELL_PERC_H200_SSDID:
4516 				ioc_info(ioc, "%s\n",
4517 					 MPT2SAS_DELL_PERC_H200_BRANDING);
4518 				break;
4519 			case MPT2SAS_DELL_6GBPS_SAS_SSDID:
4520 				ioc_info(ioc, "%s\n",
4521 					 MPT2SAS_DELL_6GBPS_SAS_BRANDING);
4522 				break;
4523 			default:
4524 				ioc_info(ioc, "Dell 6Gbps HBA: Subsystem ID: 0x%X\n",
4525 					 ioc->pdev->subsystem_device);
4526 				break;
4527 			}
4528 			break;
4529 		case MPI25_MFGPAGE_DEVID_SAS3008:
4530 			switch (ioc->pdev->subsystem_device) {
4531 			case MPT3SAS_DELL_12G_HBA_SSDID:
4532 				ioc_info(ioc, "%s\n",
4533 					 MPT3SAS_DELL_12G_HBA_BRANDING);
4534 				break;
4535 			default:
4536 				ioc_info(ioc, "Dell 12Gbps HBA: Subsystem ID: 0x%X\n",
4537 					 ioc->pdev->subsystem_device);
4538 				break;
4539 			}
4540 			break;
4541 		default:
4542 			ioc_info(ioc, "Dell HBA: Subsystem ID: 0x%X\n",
4543 				 ioc->pdev->subsystem_device);
4544 			break;
4545 		}
4546 		break;
4547 	case PCI_VENDOR_ID_CISCO:
4548 		switch (ioc->pdev->device) {
4549 		case MPI25_MFGPAGE_DEVID_SAS3008:
4550 			switch (ioc->pdev->subsystem_device) {
4551 			case MPT3SAS_CISCO_12G_8E_HBA_SSDID:
4552 				ioc_info(ioc, "%s\n",
4553 					 MPT3SAS_CISCO_12G_8E_HBA_BRANDING);
4554 				break;
4555 			case MPT3SAS_CISCO_12G_8I_HBA_SSDID:
4556 				ioc_info(ioc, "%s\n",
4557 					 MPT3SAS_CISCO_12G_8I_HBA_BRANDING);
4558 				break;
4559 			case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
4560 				ioc_info(ioc, "%s\n",
4561 					 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
4562 				break;
4563 			default:
4564 				ioc_info(ioc, "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
4565 					 ioc->pdev->subsystem_device);
4566 				break;
4567 			}
4568 			break;
4569 		case MPI25_MFGPAGE_DEVID_SAS3108_1:
4570 			switch (ioc->pdev->subsystem_device) {
4571 			case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
4572 				ioc_info(ioc, "%s\n",
4573 					 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
4574 				break;
4575 			case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID:
4576 				ioc_info(ioc, "%s\n",
4577 					 MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING);
4578 				break;
4579 			default:
4580 				ioc_info(ioc, "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
4581 					 ioc->pdev->subsystem_device);
4582 				break;
4583 			}
4584 			break;
4585 		default:
4586 			ioc_info(ioc, "Cisco SAS HBA: Subsystem ID: 0x%X\n",
4587 				 ioc->pdev->subsystem_device);
4588 			break;
4589 		}
4590 		break;
4591 	case MPT2SAS_HP_3PAR_SSVID:
4592 		switch (ioc->pdev->device) {
4593 		case MPI2_MFGPAGE_DEVID_SAS2004:
4594 			switch (ioc->pdev->subsystem_device) {
4595 			case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID:
4596 				ioc_info(ioc, "%s\n",
4597 					 MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING);
4598 				break;
4599 			default:
4600 				ioc_info(ioc, "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
4601 					 ioc->pdev->subsystem_device);
4602 				break;
4603 			}
4604 			break;
4605 		case MPI2_MFGPAGE_DEVID_SAS2308_2:
4606 			switch (ioc->pdev->subsystem_device) {
4607 			case MPT2SAS_HP_2_4_INTERNAL_SSDID:
4608 				ioc_info(ioc, "%s\n",
4609 					 MPT2SAS_HP_2_4_INTERNAL_BRANDING);
4610 				break;
4611 			case MPT2SAS_HP_2_4_EXTERNAL_SSDID:
4612 				ioc_info(ioc, "%s\n",
4613 					 MPT2SAS_HP_2_4_EXTERNAL_BRANDING);
4614 				break;
4615 			case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID:
4616 				ioc_info(ioc, "%s\n",
4617 					 MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING);
4618 				break;
4619 			case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID:
4620 				ioc_info(ioc, "%s\n",
4621 					 MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING);
4622 				break;
4623 			default:
4624 				ioc_info(ioc, "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
4625 					 ioc->pdev->subsystem_device);
4626 				break;
4627 			}
4628 			break;
4629 		default:
4630 			ioc_info(ioc, "HP SAS HBA: Subsystem ID: 0x%X\n",
4631 				 ioc->pdev->subsystem_device);
4632 			break;
4633 		}
4634 		break;
4635 	default:
4636 		break;
4637 	}
4638 }
4639 
4640 /**
4641  * _base_display_fwpkg_version - sends FWUpload request to pull FWPkg
4642  *				version from FW Image Header.
4643  * @ioc: per adapter object
4644  *
4645  * Return: 0 for success, non-zero for failure.
4646  */
4647 	static int
4648 _base_display_fwpkg_version(struct MPT3SAS_ADAPTER *ioc)
4649 {
4650 	Mpi2FWImageHeader_t *fw_img_hdr;
4651 	Mpi26ComponentImageHeader_t *cmp_img_hdr;
4652 	Mpi25FWUploadRequest_t *mpi_request;
4653 	Mpi2FWUploadReply_t mpi_reply;
4654 	int r = 0, issue_diag_reset = 0;
4655 	u32  package_version = 0;
4656 	void *fwpkg_data = NULL;
4657 	dma_addr_t fwpkg_data_dma;
4658 	u16 smid, ioc_status;
4659 	size_t data_length;
4660 
4661 	dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
4662 
4663 	if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
4664 		ioc_err(ioc, "%s: internal command already in use\n", __func__);
4665 		return -EAGAIN;
4666 	}
4667 
4668 	data_length = sizeof(Mpi2FWImageHeader_t);
4669 	fwpkg_data = dma_alloc_coherent(&ioc->pdev->dev, data_length,
4670 			&fwpkg_data_dma, GFP_KERNEL);
4671 	if (!fwpkg_data) {
4672 		ioc_err(ioc,
4673 		    "Memory allocation for fwpkg data failed at %s:%d/%s()!\n",
4674 			__FILE__, __LINE__, __func__);
4675 		return -ENOMEM;
4676 	}
4677 
4678 	smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4679 	if (!smid) {
4680 		ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
4681 		r = -EAGAIN;
4682 		goto out;
4683 	}
4684 
4685 	ioc->base_cmds.status = MPT3_CMD_PENDING;
4686 	mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4687 	ioc->base_cmds.smid = smid;
4688 	memset(mpi_request, 0, sizeof(Mpi25FWUploadRequest_t));
4689 	mpi_request->Function = MPI2_FUNCTION_FW_UPLOAD;
4690 	mpi_request->ImageType = MPI2_FW_UPLOAD_ITYPE_FW_FLASH;
4691 	mpi_request->ImageSize = cpu_to_le32(data_length);
4692 	ioc->build_sg(ioc, &mpi_request->SGL, 0, 0, fwpkg_data_dma,
4693 			data_length);
4694 	init_completion(&ioc->base_cmds.done);
4695 	ioc->put_smid_default(ioc, smid);
4696 	/* Wait for 15 seconds */
4697 	wait_for_completion_timeout(&ioc->base_cmds.done,
4698 			FW_IMG_HDR_READ_TIMEOUT*HZ);
4699 	ioc_info(ioc, "%s: complete\n", __func__);
4700 	if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4701 		ioc_err(ioc, "%s: timeout\n", __func__);
4702 		_debug_dump_mf(mpi_request,
4703 				sizeof(Mpi25FWUploadRequest_t)/4);
4704 		issue_diag_reset = 1;
4705 	} else {
4706 		memset(&mpi_reply, 0, sizeof(Mpi2FWUploadReply_t));
4707 		if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) {
4708 			memcpy(&mpi_reply, ioc->base_cmds.reply,
4709 					sizeof(Mpi2FWUploadReply_t));
4710 			ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
4711 						MPI2_IOCSTATUS_MASK;
4712 			if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
4713 				fw_img_hdr = (Mpi2FWImageHeader_t *)fwpkg_data;
4714 				if (le32_to_cpu(fw_img_hdr->Signature) ==
4715 				    MPI26_IMAGE_HEADER_SIGNATURE0_MPI26) {
4716 					cmp_img_hdr =
4717 					    (Mpi26ComponentImageHeader_t *)
4718 					    (fwpkg_data);
4719 					package_version =
4720 					    le32_to_cpu(
4721 					    cmp_img_hdr->ApplicationSpecific);
4722 				} else
4723 					package_version =
4724 					    le32_to_cpu(
4725 					    fw_img_hdr->PackageVersion.Word);
4726 				if (package_version)
4727 					ioc_info(ioc,
4728 					"FW Package Ver(%02d.%02d.%02d.%02d)\n",
4729 					((package_version) & 0xFF000000) >> 24,
4730 					((package_version) & 0x00FF0000) >> 16,
4731 					((package_version) & 0x0000FF00) >> 8,
4732 					(package_version) & 0x000000FF);
4733 			} else {
4734 				_debug_dump_mf(&mpi_reply,
4735 						sizeof(Mpi2FWUploadReply_t)/4);
4736 			}
4737 		}
4738 	}
4739 	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4740 out:
4741 	if (fwpkg_data)
4742 		dma_free_coherent(&ioc->pdev->dev, data_length, fwpkg_data,
4743 				fwpkg_data_dma);
4744 	if (issue_diag_reset) {
4745 		if (ioc->drv_internal_flags & MPT_DRV_INTERNAL_FIRST_PE_ISSUED)
4746 			return -EFAULT;
4747 		if (mpt3sas_base_check_for_fault_and_issue_reset(ioc))
4748 			return -EFAULT;
4749 		r = -EAGAIN;
4750 	}
4751 	return r;
4752 }
4753 
4754 /**
4755  * _base_display_ioc_capabilities - Display IOC's capabilities.
4756  * @ioc: per adapter object
4757  */
4758 static void
4759 _base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc)
4760 {
4761 	int i = 0;
4762 	char desc[17] = {0};
4763 	u32 iounit_pg1_flags;
4764 	u32 bios_version;
4765 
4766 	bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion);
4767 	strncpy(desc, ioc->manu_pg0.ChipName, 16);
4768 	ioc_info(ioc, "%s: FWVersion(%02d.%02d.%02d.%02d), ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
4769 		 desc,
4770 		 (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
4771 		 (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
4772 		 (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
4773 		 ioc->facts.FWVersion.Word & 0x000000FF,
4774 		 ioc->pdev->revision,
4775 		 (bios_version & 0xFF000000) >> 24,
4776 		 (bios_version & 0x00FF0000) >> 16,
4777 		 (bios_version & 0x0000FF00) >> 8,
4778 		 bios_version & 0x000000FF);
4779 
4780 	_base_display_OEMs_branding(ioc);
4781 
4782 	if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) {
4783 		pr_info("%sNVMe", i ? "," : "");
4784 		i++;
4785 	}
4786 
4787 	ioc_info(ioc, "Protocol=(");
4788 
4789 	if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
4790 		pr_cont("Initiator");
4791 		i++;
4792 	}
4793 
4794 	if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
4795 		pr_cont("%sTarget", i ? "," : "");
4796 		i++;
4797 	}
4798 
4799 	i = 0;
4800 	pr_cont("), Capabilities=(");
4801 
4802 	if (!ioc->hide_ir_msg) {
4803 		if (ioc->facts.IOCCapabilities &
4804 		    MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
4805 			pr_cont("Raid");
4806 			i++;
4807 		}
4808 	}
4809 
4810 	if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
4811 		pr_cont("%sTLR", i ? "," : "");
4812 		i++;
4813 	}
4814 
4815 	if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
4816 		pr_cont("%sMulticast", i ? "," : "");
4817 		i++;
4818 	}
4819 
4820 	if (ioc->facts.IOCCapabilities &
4821 	    MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
4822 		pr_cont("%sBIDI Target", i ? "," : "");
4823 		i++;
4824 	}
4825 
4826 	if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
4827 		pr_cont("%sEEDP", i ? "," : "");
4828 		i++;
4829 	}
4830 
4831 	if (ioc->facts.IOCCapabilities &
4832 	    MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
4833 		pr_cont("%sSnapshot Buffer", i ? "," : "");
4834 		i++;
4835 	}
4836 
4837 	if (ioc->facts.IOCCapabilities &
4838 	    MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
4839 		pr_cont("%sDiag Trace Buffer", i ? "," : "");
4840 		i++;
4841 	}
4842 
4843 	if (ioc->facts.IOCCapabilities &
4844 	    MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
4845 		pr_cont("%sDiag Extended Buffer", i ? "," : "");
4846 		i++;
4847 	}
4848 
4849 	if (ioc->facts.IOCCapabilities &
4850 	    MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
4851 		pr_cont("%sTask Set Full", i ? "," : "");
4852 		i++;
4853 	}
4854 
4855 	iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
4856 	if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
4857 		pr_cont("%sNCQ", i ? "," : "");
4858 		i++;
4859 	}
4860 
4861 	pr_cont(")\n");
4862 }
4863 
4864 /**
4865  * mpt3sas_base_update_missing_delay - change the missing delay timers
4866  * @ioc: per adapter object
4867  * @device_missing_delay: amount of time till device is reported missing
4868  * @io_missing_delay: interval IO is returned when there is a missing device
4869  *
4870  * Passed on the command line, this function will modify the device missing
4871  * delay, as well as the io missing delay. This should be called at driver
4872  * load time.
4873  */
4874 void
4875 mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc,
4876 	u16 device_missing_delay, u8 io_missing_delay)
4877 {
4878 	u16 dmd, dmd_new, dmd_orignal;
4879 	u8 io_missing_delay_original;
4880 	u16 sz;
4881 	Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL;
4882 	Mpi2ConfigReply_t mpi_reply;
4883 	u8 num_phys = 0;
4884 	u16 ioc_status;
4885 
4886 	mpt3sas_config_get_number_hba_phys(ioc, &num_phys);
4887 	if (!num_phys)
4888 		return;
4889 
4890 	sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys *
4891 	    sizeof(Mpi2SasIOUnit1PhyData_t));
4892 	sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL);
4893 	if (!sas_iounit_pg1) {
4894 		ioc_err(ioc, "failure at %s:%d/%s()!\n",
4895 			__FILE__, __LINE__, __func__);
4896 		goto out;
4897 	}
4898 	if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
4899 	    sas_iounit_pg1, sz))) {
4900 		ioc_err(ioc, "failure at %s:%d/%s()!\n",
4901 			__FILE__, __LINE__, __func__);
4902 		goto out;
4903 	}
4904 	ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
4905 	    MPI2_IOCSTATUS_MASK;
4906 	if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
4907 		ioc_err(ioc, "failure at %s:%d/%s()!\n",
4908 			__FILE__, __LINE__, __func__);
4909 		goto out;
4910 	}
4911 
4912 	/* device missing delay */
4913 	dmd = sas_iounit_pg1->ReportDeviceMissingDelay;
4914 	if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
4915 		dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
4916 	else
4917 		dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
4918 	dmd_orignal = dmd;
4919 	if (device_missing_delay > 0x7F) {
4920 		dmd = (device_missing_delay > 0x7F0) ? 0x7F0 :
4921 		    device_missing_delay;
4922 		dmd = dmd / 16;
4923 		dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16;
4924 	} else
4925 		dmd = device_missing_delay;
4926 	sas_iounit_pg1->ReportDeviceMissingDelay = dmd;
4927 
4928 	/* io missing delay */
4929 	io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay;
4930 	sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay;
4931 
4932 	if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1,
4933 	    sz)) {
4934 		if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
4935 			dmd_new = (dmd &
4936 			    MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
4937 		else
4938 			dmd_new =
4939 		    dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
4940 		ioc_info(ioc, "device_missing_delay: old(%d), new(%d)\n",
4941 			 dmd_orignal, dmd_new);
4942 		ioc_info(ioc, "ioc_missing_delay: old(%d), new(%d)\n",
4943 			 io_missing_delay_original,
4944 			 io_missing_delay);
4945 		ioc->device_missing_delay = dmd_new;
4946 		ioc->io_missing_delay = io_missing_delay;
4947 	}
4948 
4949 out:
4950 	kfree(sas_iounit_pg1);
4951 }
4952 
4953 /**
4954  * _base_update_ioc_page1_inlinewith_perf_mode - Update IOC Page1 fields
4955  *    according to performance mode.
4956  * @ioc : per adapter object
4957  *
4958  * Return: zero on success; otherwise return EAGAIN error code asking the
4959  * caller to retry.
4960  */
4961 static int
4962 _base_update_ioc_page1_inlinewith_perf_mode(struct MPT3SAS_ADAPTER *ioc)
4963 {
4964 	Mpi2IOCPage1_t ioc_pg1;
4965 	Mpi2ConfigReply_t mpi_reply;
4966 	int rc;
4967 
4968 	rc = mpt3sas_config_get_ioc_pg1(ioc, &mpi_reply, &ioc->ioc_pg1_copy);
4969 	if (rc)
4970 		return rc;
4971 	memcpy(&ioc_pg1, &ioc->ioc_pg1_copy, sizeof(Mpi2IOCPage1_t));
4972 
4973 	switch (perf_mode) {
4974 	case MPT_PERF_MODE_DEFAULT:
4975 	case MPT_PERF_MODE_BALANCED:
4976 		if (ioc->high_iops_queues) {
4977 			ioc_info(ioc,
4978 				"Enable interrupt coalescing only for first\t"
4979 				"%d reply queues\n",
4980 				MPT3SAS_HIGH_IOPS_REPLY_QUEUES);
4981 			/*
4982 			 * If 31st bit is zero then interrupt coalescing is
4983 			 * enabled for all reply descriptor post queues.
4984 			 * If 31st bit is set to one then user can
4985 			 * enable/disable interrupt coalescing on per reply
4986 			 * descriptor post queue group(8) basis. So to enable
4987 			 * interrupt coalescing only on first reply descriptor
4988 			 * post queue group 31st bit and zero th bit is enabled.
4989 			 */
4990 			ioc_pg1.ProductSpecific = cpu_to_le32(0x80000000 |
4991 			    ((1 << MPT3SAS_HIGH_IOPS_REPLY_QUEUES/8) - 1));
4992 			rc = mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1);
4993 			if (rc)
4994 				return rc;
4995 			ioc_info(ioc, "performance mode: balanced\n");
4996 			return 0;
4997 		}
4998 		fallthrough;
4999 	case MPT_PERF_MODE_LATENCY:
5000 		/*
5001 		 * Enable interrupt coalescing on all reply queues
5002 		 * with timeout value 0xA
5003 		 */
5004 		ioc_pg1.CoalescingTimeout = cpu_to_le32(0xa);
5005 		ioc_pg1.Flags |= cpu_to_le32(MPI2_IOCPAGE1_REPLY_COALESCING);
5006 		ioc_pg1.ProductSpecific = 0;
5007 		rc = mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1);
5008 		if (rc)
5009 			return rc;
5010 		ioc_info(ioc, "performance mode: latency\n");
5011 		break;
5012 	case MPT_PERF_MODE_IOPS:
5013 		/*
5014 		 * Enable interrupt coalescing on all reply queues.
5015 		 */
5016 		ioc_info(ioc,
5017 		    "performance mode: iops with coalescing timeout: 0x%x\n",
5018 		    le32_to_cpu(ioc_pg1.CoalescingTimeout));
5019 		ioc_pg1.Flags |= cpu_to_le32(MPI2_IOCPAGE1_REPLY_COALESCING);
5020 		ioc_pg1.ProductSpecific = 0;
5021 		rc = mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1);
5022 		if (rc)
5023 			return rc;
5024 		break;
5025 	}
5026 	return 0;
5027 }
5028 
5029 /**
5030  * _base_get_event_diag_triggers - get event diag trigger values from
5031  *				persistent pages
5032  * @ioc : per adapter object
5033  *
5034  * Return: nothing.
5035  */
5036 static int
5037 _base_get_event_diag_triggers(struct MPT3SAS_ADAPTER *ioc)
5038 {
5039 	Mpi26DriverTriggerPage2_t trigger_pg2;
5040 	struct SL_WH_EVENT_TRIGGER_T *event_tg;
5041 	MPI26_DRIVER_MPI_EVENT_TIGGER_ENTRY *mpi_event_tg;
5042 	Mpi2ConfigReply_t mpi_reply;
5043 	int r = 0, i = 0;
5044 	u16 count = 0;
5045 	u16 ioc_status;
5046 
5047 	r = mpt3sas_config_get_driver_trigger_pg2(ioc, &mpi_reply,
5048 	    &trigger_pg2);
5049 	if (r)
5050 		return r;
5051 
5052 	ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
5053 	    MPI2_IOCSTATUS_MASK;
5054 	if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
5055 		dinitprintk(ioc,
5056 		    ioc_err(ioc,
5057 		    "%s: Failed to get trigger pg2, ioc_status(0x%04x)\n",
5058 		   __func__, ioc_status));
5059 		return 0;
5060 	}
5061 
5062 	if (le16_to_cpu(trigger_pg2.NumMPIEventTrigger)) {
5063 		count = le16_to_cpu(trigger_pg2.NumMPIEventTrigger);
5064 		count = min_t(u16, NUM_VALID_ENTRIES, count);
5065 		ioc->diag_trigger_event.ValidEntries = count;
5066 
5067 		event_tg = &ioc->diag_trigger_event.EventTriggerEntry[0];
5068 		mpi_event_tg = &trigger_pg2.MPIEventTriggers[0];
5069 		for (i = 0; i < count; i++) {
5070 			event_tg->EventValue = le16_to_cpu(
5071 			    mpi_event_tg->MPIEventCode);
5072 			event_tg->LogEntryQualifier = le16_to_cpu(
5073 			    mpi_event_tg->MPIEventCodeSpecific);
5074 			event_tg++;
5075 			mpi_event_tg++;
5076 		}
5077 	}
5078 	return 0;
5079 }
5080 
5081 /**
5082  * _base_get_scsi_diag_triggers - get scsi diag trigger values from
5083  *				persistent pages
5084  * @ioc : per adapter object
5085  *
5086  * Return: 0 on success; otherwise return failure status.
5087  */
5088 static int
5089 _base_get_scsi_diag_triggers(struct MPT3SAS_ADAPTER *ioc)
5090 {
5091 	Mpi26DriverTriggerPage3_t trigger_pg3;
5092 	struct SL_WH_SCSI_TRIGGER_T *scsi_tg;
5093 	MPI26_DRIVER_SCSI_SENSE_TIGGER_ENTRY *mpi_scsi_tg;
5094 	Mpi2ConfigReply_t mpi_reply;
5095 	int r = 0, i = 0;
5096 	u16 count = 0;
5097 	u16 ioc_status;
5098 
5099 	r = mpt3sas_config_get_driver_trigger_pg3(ioc, &mpi_reply,
5100 	    &trigger_pg3);
5101 	if (r)
5102 		return r;
5103 
5104 	ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
5105 	    MPI2_IOCSTATUS_MASK;
5106 	if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
5107 		dinitprintk(ioc,
5108 		    ioc_err(ioc,
5109 		    "%s: Failed to get trigger pg3, ioc_status(0x%04x)\n",
5110 		    __func__, ioc_status));
5111 		return 0;
5112 	}
5113 
5114 	if (le16_to_cpu(trigger_pg3.NumSCSISenseTrigger)) {
5115 		count = le16_to_cpu(trigger_pg3.NumSCSISenseTrigger);
5116 		count = min_t(u16, NUM_VALID_ENTRIES, count);
5117 		ioc->diag_trigger_scsi.ValidEntries = count;
5118 
5119 		scsi_tg = &ioc->diag_trigger_scsi.SCSITriggerEntry[0];
5120 		mpi_scsi_tg = &trigger_pg3.SCSISenseTriggers[0];
5121 		for (i = 0; i < count; i++) {
5122 			scsi_tg->ASCQ = mpi_scsi_tg->ASCQ;
5123 			scsi_tg->ASC = mpi_scsi_tg->ASC;
5124 			scsi_tg->SenseKey = mpi_scsi_tg->SenseKey;
5125 
5126 			scsi_tg++;
5127 			mpi_scsi_tg++;
5128 		}
5129 	}
5130 	return 0;
5131 }
5132 
5133 /**
5134  * _base_get_mpi_diag_triggers - get mpi diag trigger values from
5135  *				persistent pages
5136  * @ioc : per adapter object
5137  *
5138  * Return: 0 on success; otherwise return failure status.
5139  */
5140 static int
5141 _base_get_mpi_diag_triggers(struct MPT3SAS_ADAPTER *ioc)
5142 {
5143 	Mpi26DriverTriggerPage4_t trigger_pg4;
5144 	struct SL_WH_MPI_TRIGGER_T *status_tg;
5145 	MPI26_DRIVER_IOCSTATUS_LOGINFO_TIGGER_ENTRY *mpi_status_tg;
5146 	Mpi2ConfigReply_t mpi_reply;
5147 	int r = 0, i = 0;
5148 	u16 count = 0;
5149 	u16 ioc_status;
5150 
5151 	r = mpt3sas_config_get_driver_trigger_pg4(ioc, &mpi_reply,
5152 	    &trigger_pg4);
5153 	if (r)
5154 		return r;
5155 
5156 	ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
5157 	    MPI2_IOCSTATUS_MASK;
5158 	if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
5159 		dinitprintk(ioc,
5160 		    ioc_err(ioc,
5161 		    "%s: Failed to get trigger pg4, ioc_status(0x%04x)\n",
5162 		    __func__, ioc_status));
5163 		return 0;
5164 	}
5165 
5166 	if (le16_to_cpu(trigger_pg4.NumIOCStatusLogInfoTrigger)) {
5167 		count = le16_to_cpu(trigger_pg4.NumIOCStatusLogInfoTrigger);
5168 		count = min_t(u16, NUM_VALID_ENTRIES, count);
5169 		ioc->diag_trigger_mpi.ValidEntries = count;
5170 
5171 		status_tg = &ioc->diag_trigger_mpi.MPITriggerEntry[0];
5172 		mpi_status_tg = &trigger_pg4.IOCStatusLoginfoTriggers[0];
5173 
5174 		for (i = 0; i < count; i++) {
5175 			status_tg->IOCStatus = le16_to_cpu(
5176 			    mpi_status_tg->IOCStatus);
5177 			status_tg->IocLogInfo = le32_to_cpu(
5178 			    mpi_status_tg->LogInfo);
5179 
5180 			status_tg++;
5181 			mpi_status_tg++;
5182 		}
5183 	}
5184 	return 0;
5185 }
5186 
5187 /**
5188  * _base_get_master_diag_triggers - get master diag trigger values from
5189  *				persistent pages
5190  * @ioc : per adapter object
5191  *
5192  * Return: nothing.
5193  */
5194 static int
5195 _base_get_master_diag_triggers(struct MPT3SAS_ADAPTER *ioc)
5196 {
5197 	Mpi26DriverTriggerPage1_t trigger_pg1;
5198 	Mpi2ConfigReply_t mpi_reply;
5199 	int r;
5200 	u16 ioc_status;
5201 
5202 	r = mpt3sas_config_get_driver_trigger_pg1(ioc, &mpi_reply,
5203 	    &trigger_pg1);
5204 	if (r)
5205 		return r;
5206 
5207 	ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
5208 	    MPI2_IOCSTATUS_MASK;
5209 	if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
5210 		dinitprintk(ioc,
5211 		    ioc_err(ioc,
5212 		    "%s: Failed to get trigger pg1, ioc_status(0x%04x)\n",
5213 		   __func__, ioc_status));
5214 		return 0;
5215 	}
5216 
5217 	if (le16_to_cpu(trigger_pg1.NumMasterTrigger))
5218 		ioc->diag_trigger_master.MasterData |=
5219 		    le32_to_cpu(
5220 		    trigger_pg1.MasterTriggers[0].MasterTriggerFlags);
5221 	return 0;
5222 }
5223 
5224 /**
5225  * _base_check_for_trigger_pages_support - checks whether HBA FW supports
5226  *					driver trigger pages or not
5227  * @ioc : per adapter object
5228  * @trigger_flags : address where trigger page0's TriggerFlags value is copied
5229  *
5230  * Return: trigger flags mask if HBA FW supports driver trigger pages;
5231  * otherwise returns %-EFAULT if driver trigger pages are not supported by FW or
5232  * return EAGAIN if diag reset occurred due to FW fault and asking the
5233  * caller to retry the command.
5234  *
5235  */
5236 static int
5237 _base_check_for_trigger_pages_support(struct MPT3SAS_ADAPTER *ioc, u32 *trigger_flags)
5238 {
5239 	Mpi26DriverTriggerPage0_t trigger_pg0;
5240 	int r = 0;
5241 	Mpi2ConfigReply_t mpi_reply;
5242 	u16 ioc_status;
5243 
5244 	r = mpt3sas_config_get_driver_trigger_pg0(ioc, &mpi_reply,
5245 	    &trigger_pg0);
5246 	if (r)
5247 		return r;
5248 
5249 	ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
5250 	    MPI2_IOCSTATUS_MASK;
5251 	if (ioc_status != MPI2_IOCSTATUS_SUCCESS)
5252 		return -EFAULT;
5253 
5254 	*trigger_flags = le16_to_cpu(trigger_pg0.TriggerFlags);
5255 	return 0;
5256 }
5257 
5258 /**
5259  * _base_get_diag_triggers - Retrieve diag trigger values from
5260  *				persistent pages.
5261  * @ioc : per adapter object
5262  *
5263  * Return: zero on success; otherwise return EAGAIN error codes
5264  * asking the caller to retry.
5265  */
5266 static int
5267 _base_get_diag_triggers(struct MPT3SAS_ADAPTER *ioc)
5268 {
5269 	int trigger_flags;
5270 	int r;
5271 
5272 	/*
5273 	 * Default setting of master trigger.
5274 	 */
5275 	ioc->diag_trigger_master.MasterData =
5276 	    (MASTER_TRIGGER_FW_FAULT + MASTER_TRIGGER_ADAPTER_RESET);
5277 
5278 	r = _base_check_for_trigger_pages_support(ioc, &trigger_flags);
5279 	if (r) {
5280 		if (r == -EAGAIN)
5281 			return r;
5282 		/*
5283 		 * Don't go for error handling when FW doesn't support
5284 		 * driver trigger pages.
5285 		 */
5286 		return 0;
5287 	}
5288 
5289 	ioc->supports_trigger_pages = 1;
5290 
5291 	/*
5292 	 * Retrieve master diag trigger values from driver trigger pg1
5293 	 * if master trigger bit enabled in TriggerFlags.
5294 	 */
5295 	if ((u16)trigger_flags &
5296 	    MPI26_DRIVER_TRIGGER0_FLAG_MASTER_TRIGGER_VALID) {
5297 		r = _base_get_master_diag_triggers(ioc);
5298 		if (r)
5299 			return r;
5300 	}
5301 
5302 	/*
5303 	 * Retrieve event diag trigger values from driver trigger pg2
5304 	 * if event trigger bit enabled in TriggerFlags.
5305 	 */
5306 	if ((u16)trigger_flags &
5307 	    MPI26_DRIVER_TRIGGER0_FLAG_MPI_EVENT_TRIGGER_VALID) {
5308 		r = _base_get_event_diag_triggers(ioc);
5309 		if (r)
5310 			return r;
5311 	}
5312 
5313 	/*
5314 	 * Retrieve scsi diag trigger values from driver trigger pg3
5315 	 * if scsi trigger bit enabled in TriggerFlags.
5316 	 */
5317 	if ((u16)trigger_flags &
5318 	    MPI26_DRIVER_TRIGGER0_FLAG_SCSI_SENSE_TRIGGER_VALID) {
5319 		r = _base_get_scsi_diag_triggers(ioc);
5320 		if (r)
5321 			return r;
5322 	}
5323 	/*
5324 	 * Retrieve mpi error diag trigger values from driver trigger pg4
5325 	 * if loginfo trigger bit enabled in TriggerFlags.
5326 	 */
5327 	if ((u16)trigger_flags &
5328 	    MPI26_DRIVER_TRIGGER0_FLAG_LOGINFO_TRIGGER_VALID) {
5329 		r = _base_get_mpi_diag_triggers(ioc);
5330 		if (r)
5331 			return r;
5332 	}
5333 	return 0;
5334 }
5335 
5336 /**
5337  * _base_update_diag_trigger_pages - Update the driver trigger pages after
5338  *			online FW update, in case updated FW supports driver
5339  *			trigger pages.
5340  * @ioc : per adapter object
5341  *
5342  * Return: nothing.
5343  */
5344 static void
5345 _base_update_diag_trigger_pages(struct MPT3SAS_ADAPTER *ioc)
5346 {
5347 
5348 	if (ioc->diag_trigger_master.MasterData)
5349 		mpt3sas_config_update_driver_trigger_pg1(ioc,
5350 		    &ioc->diag_trigger_master, 1);
5351 
5352 	if (ioc->diag_trigger_event.ValidEntries)
5353 		mpt3sas_config_update_driver_trigger_pg2(ioc,
5354 		    &ioc->diag_trigger_event, 1);
5355 
5356 	if (ioc->diag_trigger_scsi.ValidEntries)
5357 		mpt3sas_config_update_driver_trigger_pg3(ioc,
5358 		    &ioc->diag_trigger_scsi, 1);
5359 
5360 	if (ioc->diag_trigger_mpi.ValidEntries)
5361 		mpt3sas_config_update_driver_trigger_pg4(ioc,
5362 		    &ioc->diag_trigger_mpi, 1);
5363 }
5364 
5365 /**
5366  * _base_assign_fw_reported_qd	- Get FW reported QD for SAS/SATA devices.
5367  *				- On failure set default QD values.
5368  * @ioc : per adapter object
5369  *
5370  * Returns 0 for success, non-zero for failure.
5371  *
5372  */
5373 static int _base_assign_fw_reported_qd(struct MPT3SAS_ADAPTER *ioc)
5374 {
5375 	Mpi2ConfigReply_t mpi_reply;
5376 	Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL;
5377 	Mpi26PCIeIOUnitPage1_t pcie_iounit_pg1;
5378 	u16 depth;
5379 	int sz;
5380 	int rc = 0;
5381 
5382 	ioc->max_wideport_qd = MPT3SAS_SAS_QUEUE_DEPTH;
5383 	ioc->max_narrowport_qd = MPT3SAS_SAS_QUEUE_DEPTH;
5384 	ioc->max_sata_qd = MPT3SAS_SATA_QUEUE_DEPTH;
5385 	ioc->max_nvme_qd = MPT3SAS_NVME_QUEUE_DEPTH;
5386 	if (!ioc->is_gen35_ioc)
5387 		goto out;
5388 	/* sas iounit page 1 */
5389 	sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData);
5390 	sas_iounit_pg1 = kzalloc(sizeof(Mpi2SasIOUnitPage1_t), GFP_KERNEL);
5391 	if (!sas_iounit_pg1) {
5392 		pr_err("%s: failure at %s:%d/%s()!\n",
5393 		    ioc->name, __FILE__, __LINE__, __func__);
5394 		return rc;
5395 	}
5396 	rc = mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
5397 	    sas_iounit_pg1, sz);
5398 	if (rc) {
5399 		pr_err("%s: failure at %s:%d/%s()!\n",
5400 		    ioc->name, __FILE__, __LINE__, __func__);
5401 		goto out;
5402 	}
5403 
5404 	depth = le16_to_cpu(sas_iounit_pg1->SASWideMaxQueueDepth);
5405 	ioc->max_wideport_qd = (depth ? depth : MPT3SAS_SAS_QUEUE_DEPTH);
5406 
5407 	depth = le16_to_cpu(sas_iounit_pg1->SASNarrowMaxQueueDepth);
5408 	ioc->max_narrowport_qd = (depth ? depth : MPT3SAS_SAS_QUEUE_DEPTH);
5409 
5410 	depth = sas_iounit_pg1->SATAMaxQDepth;
5411 	ioc->max_sata_qd = (depth ? depth : MPT3SAS_SATA_QUEUE_DEPTH);
5412 
5413 	/* pcie iounit page 1 */
5414 	rc = mpt3sas_config_get_pcie_iounit_pg1(ioc, &mpi_reply,
5415 	    &pcie_iounit_pg1, sizeof(Mpi26PCIeIOUnitPage1_t));
5416 	if (rc) {
5417 		pr_err("%s: failure at %s:%d/%s()!\n",
5418 		    ioc->name, __FILE__, __LINE__, __func__);
5419 		goto out;
5420 	}
5421 	ioc->max_nvme_qd = (le16_to_cpu(pcie_iounit_pg1.NVMeMaxQueueDepth)) ?
5422 	    (le16_to_cpu(pcie_iounit_pg1.NVMeMaxQueueDepth)) :
5423 	    MPT3SAS_NVME_QUEUE_DEPTH;
5424 out:
5425 	dinitprintk(ioc, pr_err(
5426 	    "MaxWidePortQD: 0x%x MaxNarrowPortQD: 0x%x MaxSataQD: 0x%x MaxNvmeQD: 0x%x\n",
5427 	    ioc->max_wideport_qd, ioc->max_narrowport_qd,
5428 	    ioc->max_sata_qd, ioc->max_nvme_qd));
5429 	kfree(sas_iounit_pg1);
5430 	return rc;
5431 }
5432 
5433 /**
5434  * mpt3sas_atto_validate_nvram - validate the ATTO nvram read from mfg pg1
5435  *
5436  * @ioc : per adapter object
5437  * @n   : ptr to the ATTO nvram structure
5438  * Return: 0 for success, non-zero for failure.
5439  */
5440 static int
5441 mpt3sas_atto_validate_nvram(struct MPT3SAS_ADAPTER *ioc,
5442 			    struct ATTO_SAS_NVRAM *n)
5443 {
5444 	int r = -EINVAL;
5445 	union ATTO_SAS_ADDRESS *s1;
5446 	u32 len;
5447 	u8 *pb;
5448 	u8 ckSum;
5449 
5450 	/* validate nvram checksum */
5451 	pb = (u8 *) n;
5452 	ckSum = ATTO_SASNVR_CKSUM_SEED;
5453 	len = sizeof(struct ATTO_SAS_NVRAM);
5454 
5455 	while (len--)
5456 		ckSum = ckSum + pb[len];
5457 
5458 	if (ckSum) {
5459 		ioc_err(ioc, "Invalid ATTO NVRAM checksum\n");
5460 		return r;
5461 	}
5462 
5463 	s1 = (union ATTO_SAS_ADDRESS *) n->SasAddr;
5464 
5465 	if (n->Signature[0] != 'E'
5466 	|| n->Signature[1] != 'S'
5467 	|| n->Signature[2] != 'A'
5468 	|| n->Signature[3] != 'S')
5469 		ioc_err(ioc, "Invalid ATTO NVRAM signature\n");
5470 	else if (n->Version > ATTO_SASNVR_VERSION)
5471 		ioc_info(ioc, "Invalid ATTO NVRAM version");
5472 	else if ((n->SasAddr[7] & (ATTO_SAS_ADDR_ALIGN - 1))
5473 			|| s1->b[0] != 0x50
5474 			|| s1->b[1] != 0x01
5475 			|| s1->b[2] != 0x08
5476 			|| (s1->b[3] & 0xF0) != 0x60
5477 			|| ((s1->b[3] & 0x0F) | le32_to_cpu(s1->d[1])) == 0) {
5478 		ioc_err(ioc, "Invalid ATTO SAS address\n");
5479 	} else
5480 		r = 0;
5481 	return r;
5482 }
5483 
5484 /**
5485  * mpt3sas_atto_get_sas_addr - get the ATTO SAS address from mfg page 1
5486  *
5487  * @ioc : per adapter object
5488  * @*sas_addr : return sas address
5489  * Return: 0 for success, non-zero for failure.
5490  */
5491 static int
5492 mpt3sas_atto_get_sas_addr(struct MPT3SAS_ADAPTER *ioc, union ATTO_SAS_ADDRESS *sas_addr)
5493 {
5494 	Mpi2ManufacturingPage1_t mfg_pg1;
5495 	Mpi2ConfigReply_t mpi_reply;
5496 	struct ATTO_SAS_NVRAM *nvram;
5497 	int r;
5498 	__be64 addr;
5499 
5500 	r = mpt3sas_config_get_manufacturing_pg1(ioc, &mpi_reply, &mfg_pg1);
5501 	if (r) {
5502 		ioc_err(ioc, "Failed to read manufacturing page 1\n");
5503 		return r;
5504 	}
5505 
5506 	/* validate nvram */
5507 	nvram = (struct ATTO_SAS_NVRAM *) mfg_pg1.VPD;
5508 	r = mpt3sas_atto_validate_nvram(ioc, nvram);
5509 	if (r)
5510 		return r;
5511 
5512 	addr = *((__be64 *) nvram->SasAddr);
5513 	sas_addr->q = cpu_to_le64(be64_to_cpu(addr));
5514 	return r;
5515 }
5516 
5517 /**
5518  * mpt3sas_atto_init - perform initializaion for ATTO branded
5519  *					adapter.
5520  * @ioc : per adapter object
5521  *5
5522  * Return: 0 for success, non-zero for failure.
5523  */
5524 static int
5525 mpt3sas_atto_init(struct MPT3SAS_ADAPTER *ioc)
5526 {
5527 	int sz = 0;
5528 	Mpi2BiosPage4_t *bios_pg4 = NULL;
5529 	Mpi2ConfigReply_t mpi_reply;
5530 	int r;
5531 	int ix;
5532 	union ATTO_SAS_ADDRESS sas_addr;
5533 	union ATTO_SAS_ADDRESS temp;
5534 	union ATTO_SAS_ADDRESS bias;
5535 
5536 	r = mpt3sas_atto_get_sas_addr(ioc, &sas_addr);
5537 	if (r)
5538 		return r;
5539 
5540 	/* get header first to get size */
5541 	r = mpt3sas_config_get_bios_pg4(ioc, &mpi_reply, NULL, 0);
5542 	if (r) {
5543 		ioc_err(ioc, "Failed to read ATTO bios page 4 header.\n");
5544 		return r;
5545 	}
5546 
5547 	sz = mpi_reply.Header.PageLength * sizeof(u32);
5548 	bios_pg4 = kzalloc(sz, GFP_KERNEL);
5549 	if (!bios_pg4) {
5550 		ioc_err(ioc, "Failed to allocate memory for ATTO bios page.\n");
5551 		return -ENOMEM;
5552 	}
5553 
5554 	/* read bios page 4 */
5555 	r = mpt3sas_config_get_bios_pg4(ioc, &mpi_reply, bios_pg4, sz);
5556 	if (r) {
5557 		ioc_err(ioc, "Failed to read ATTO bios page 4\n");
5558 		goto out;
5559 	}
5560 
5561 	/* Update bios page 4 with the ATTO WWID */
5562 	bias.q = sas_addr.q;
5563 	bias.b[7] += ATTO_SAS_ADDR_DEVNAME_BIAS;
5564 
5565 	for (ix = 0; ix < bios_pg4->NumPhys; ix++) {
5566 		temp.q = sas_addr.q;
5567 		temp.b[7] += ix;
5568 		bios_pg4->Phy[ix].ReassignmentWWID = temp.q;
5569 		bios_pg4->Phy[ix].ReassignmentDeviceName = bias.q;
5570 	}
5571 	r = mpt3sas_config_set_bios_pg4(ioc, &mpi_reply, bios_pg4, sz);
5572 
5573 out:
5574 	kfree(bios_pg4);
5575 	return r;
5576 }
5577 
5578 /**
5579  * _base_static_config_pages - static start of day config pages
5580  * @ioc: per adapter object
5581  */
5582 static int
5583 _base_static_config_pages(struct MPT3SAS_ADAPTER *ioc)
5584 {
5585 	Mpi2ConfigReply_t mpi_reply;
5586 	u32 iounit_pg1_flags;
5587 	int tg_flags = 0;
5588 	int rc;
5589 	ioc->nvme_abort_timeout = 30;
5590 
5591 	rc = mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply,
5592 	    &ioc->manu_pg0);
5593 	if (rc)
5594 		return rc;
5595 	if (ioc->ir_firmware) {
5596 		rc = mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
5597 		    &ioc->manu_pg10);
5598 		if (rc)
5599 			return rc;
5600 	}
5601 
5602 	if (ioc->pdev->vendor == MPI2_MFGPAGE_VENDORID_ATTO) {
5603 		rc = mpt3sas_atto_init(ioc);
5604 		if (rc)
5605 			return rc;
5606 	}
5607 
5608 	/*
5609 	 * Ensure correct T10 PI operation if vendor left EEDPTagMode
5610 	 * flag unset in NVDATA.
5611 	 */
5612 	rc = mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply,
5613 	    &ioc->manu_pg11);
5614 	if (rc)
5615 		return rc;
5616 	if (!ioc->is_gen35_ioc && ioc->manu_pg11.EEDPTagMode == 0) {
5617 		pr_err("%s: overriding NVDATA EEDPTagMode setting\n",
5618 		    ioc->name);
5619 		ioc->manu_pg11.EEDPTagMode &= ~0x3;
5620 		ioc->manu_pg11.EEDPTagMode |= 0x1;
5621 		mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply,
5622 		    &ioc->manu_pg11);
5623 	}
5624 	if (ioc->manu_pg11.AddlFlags2 & NVME_TASK_MNGT_CUSTOM_MASK)
5625 		ioc->tm_custom_handling = 1;
5626 	else {
5627 		ioc->tm_custom_handling = 0;
5628 		if (ioc->manu_pg11.NVMeAbortTO < NVME_TASK_ABORT_MIN_TIMEOUT)
5629 			ioc->nvme_abort_timeout = NVME_TASK_ABORT_MIN_TIMEOUT;
5630 		else if (ioc->manu_pg11.NVMeAbortTO >
5631 					NVME_TASK_ABORT_MAX_TIMEOUT)
5632 			ioc->nvme_abort_timeout = NVME_TASK_ABORT_MAX_TIMEOUT;
5633 		else
5634 			ioc->nvme_abort_timeout = ioc->manu_pg11.NVMeAbortTO;
5635 	}
5636 	ioc->time_sync_interval =
5637 	    ioc->manu_pg11.TimeSyncInterval & MPT3SAS_TIMESYNC_MASK;
5638 	if (ioc->time_sync_interval) {
5639 		if (ioc->manu_pg11.TimeSyncInterval & MPT3SAS_TIMESYNC_UNIT_MASK)
5640 			ioc->time_sync_interval =
5641 			    ioc->time_sync_interval * SECONDS_PER_HOUR;
5642 		else
5643 			ioc->time_sync_interval =
5644 			    ioc->time_sync_interval * SECONDS_PER_MIN;
5645 		dinitprintk(ioc, ioc_info(ioc,
5646 		    "Driver-FW TimeSync interval is %d seconds. ManuPg11 TimeSync Unit is in %s\n",
5647 		    ioc->time_sync_interval, (ioc->manu_pg11.TimeSyncInterval &
5648 		    MPT3SAS_TIMESYNC_UNIT_MASK) ? "Hour" : "Minute"));
5649 	} else {
5650 		if (ioc->is_gen35_ioc)
5651 			ioc_warn(ioc,
5652 			    "TimeSync Interval in Manuf page-11 is not enabled. Periodic Time-Sync will be disabled\n");
5653 	}
5654 	rc = _base_assign_fw_reported_qd(ioc);
5655 	if (rc)
5656 		return rc;
5657 
5658 	/*
5659 	 * ATTO doesn't use bios page 2 and 3 for bios settings.
5660 	 */
5661 	if (ioc->pdev->vendor ==  MPI2_MFGPAGE_VENDORID_ATTO)
5662 		ioc->bios_pg3.BiosVersion = 0;
5663 	else {
5664 		rc = mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
5665 		if (rc)
5666 			return rc;
5667 		rc = mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
5668 		if (rc)
5669 			return rc;
5670 	}
5671 
5672 	rc = mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
5673 	if (rc)
5674 		return rc;
5675 	rc = mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0);
5676 	if (rc)
5677 		return rc;
5678 	rc = mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
5679 	if (rc)
5680 		return rc;
5681 	rc = mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8);
5682 	if (rc)
5683 		return rc;
5684 	_base_display_ioc_capabilities(ioc);
5685 
5686 	/*
5687 	 * Enable task_set_full handling in iounit_pg1 when the
5688 	 * facts capabilities indicate that its supported.
5689 	 */
5690 	iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
5691 	if ((ioc->facts.IOCCapabilities &
5692 	    MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING))
5693 		iounit_pg1_flags &=
5694 		    ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
5695 	else
5696 		iounit_pg1_flags |=
5697 		    MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
5698 	ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags);
5699 	rc = mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
5700 	if (rc)
5701 		return rc;
5702 
5703 	if (ioc->iounit_pg8.NumSensors)
5704 		ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors;
5705 	if (ioc->is_aero_ioc) {
5706 		rc = _base_update_ioc_page1_inlinewith_perf_mode(ioc);
5707 		if (rc)
5708 			return rc;
5709 	}
5710 	if (ioc->is_gen35_ioc) {
5711 		if (ioc->is_driver_loading) {
5712 			rc = _base_get_diag_triggers(ioc);
5713 			if (rc)
5714 				return rc;
5715 		} else {
5716 			/*
5717 			 * In case of online HBA FW update operation,
5718 			 * check whether updated FW supports the driver trigger
5719 			 * pages or not.
5720 			 * - If previous FW has not supported driver trigger
5721 			 *   pages and newer FW supports them then update these
5722 			 *   pages with current diag trigger values.
5723 			 * - If previous FW has supported driver trigger pages
5724 			 *   and new FW doesn't support them then disable
5725 			 *   support_trigger_pages flag.
5726 			 */
5727 			_base_check_for_trigger_pages_support(ioc, &tg_flags);
5728 			if (!ioc->supports_trigger_pages && tg_flags != -EFAULT)
5729 				_base_update_diag_trigger_pages(ioc);
5730 			else if (ioc->supports_trigger_pages &&
5731 			    tg_flags == -EFAULT)
5732 				ioc->supports_trigger_pages = 0;
5733 		}
5734 	}
5735 	return 0;
5736 }
5737 
5738 /**
5739  * mpt3sas_free_enclosure_list - release memory
5740  * @ioc: per adapter object
5741  *
5742  * Free memory allocated during enclosure add.
5743  */
5744 void
5745 mpt3sas_free_enclosure_list(struct MPT3SAS_ADAPTER *ioc)
5746 {
5747 	struct _enclosure_node *enclosure_dev, *enclosure_dev_next;
5748 
5749 	/* Free enclosure list */
5750 	list_for_each_entry_safe(enclosure_dev,
5751 			enclosure_dev_next, &ioc->enclosure_list, list) {
5752 		list_del(&enclosure_dev->list);
5753 		kfree(enclosure_dev);
5754 	}
5755 }
5756 
5757 /**
5758  * _base_release_memory_pools - release memory
5759  * @ioc: per adapter object
5760  *
5761  * Free memory allocated from _base_allocate_memory_pools.
5762  */
5763 static void
5764 _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
5765 {
5766 	int i = 0;
5767 	int j = 0;
5768 	int dma_alloc_count = 0;
5769 	struct chain_tracker *ct;
5770 	int count = ioc->rdpq_array_enable ? ioc->reply_queue_count : 1;
5771 
5772 	dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
5773 
5774 	if (ioc->request) {
5775 		dma_free_coherent(&ioc->pdev->dev, ioc->request_dma_sz,
5776 		    ioc->request,  ioc->request_dma);
5777 		dexitprintk(ioc,
5778 			    ioc_info(ioc, "request_pool(0x%p): free\n",
5779 				     ioc->request));
5780 		ioc->request = NULL;
5781 	}
5782 
5783 	if (ioc->sense) {
5784 		dma_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
5785 		dma_pool_destroy(ioc->sense_dma_pool);
5786 		dexitprintk(ioc,
5787 			    ioc_info(ioc, "sense_pool(0x%p): free\n",
5788 				     ioc->sense));
5789 		ioc->sense = NULL;
5790 	}
5791 
5792 	if (ioc->reply) {
5793 		dma_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
5794 		dma_pool_destroy(ioc->reply_dma_pool);
5795 		dexitprintk(ioc,
5796 			    ioc_info(ioc, "reply_pool(0x%p): free\n",
5797 				     ioc->reply));
5798 		ioc->reply = NULL;
5799 	}
5800 
5801 	if (ioc->reply_free) {
5802 		dma_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
5803 		    ioc->reply_free_dma);
5804 		dma_pool_destroy(ioc->reply_free_dma_pool);
5805 		dexitprintk(ioc,
5806 			    ioc_info(ioc, "reply_free_pool(0x%p): free\n",
5807 				     ioc->reply_free));
5808 		ioc->reply_free = NULL;
5809 	}
5810 
5811 	if (ioc->reply_post) {
5812 		dma_alloc_count = DIV_ROUND_UP(count,
5813 				RDPQ_MAX_INDEX_IN_ONE_CHUNK);
5814 		for (i = 0; i < count; i++) {
5815 			if (i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0
5816 			    && dma_alloc_count) {
5817 				if (ioc->reply_post[i].reply_post_free) {
5818 					dma_pool_free(
5819 					    ioc->reply_post_free_dma_pool,
5820 					    ioc->reply_post[i].reply_post_free,
5821 					ioc->reply_post[i].reply_post_free_dma);
5822 					dexitprintk(ioc, ioc_info(ioc,
5823 					   "reply_post_free_pool(0x%p): free\n",
5824 					   ioc->reply_post[i].reply_post_free));
5825 					ioc->reply_post[i].reply_post_free =
5826 									NULL;
5827 				}
5828 				--dma_alloc_count;
5829 			}
5830 		}
5831 		dma_pool_destroy(ioc->reply_post_free_dma_pool);
5832 		if (ioc->reply_post_free_array &&
5833 			ioc->rdpq_array_enable) {
5834 			dma_pool_free(ioc->reply_post_free_array_dma_pool,
5835 			    ioc->reply_post_free_array,
5836 			    ioc->reply_post_free_array_dma);
5837 			ioc->reply_post_free_array = NULL;
5838 		}
5839 		dma_pool_destroy(ioc->reply_post_free_array_dma_pool);
5840 		kfree(ioc->reply_post);
5841 	}
5842 
5843 	if (ioc->pcie_sgl_dma_pool) {
5844 		for (i = 0; i < ioc->scsiio_depth; i++) {
5845 			dma_pool_free(ioc->pcie_sgl_dma_pool,
5846 					ioc->pcie_sg_lookup[i].pcie_sgl,
5847 					ioc->pcie_sg_lookup[i].pcie_sgl_dma);
5848 			ioc->pcie_sg_lookup[i].pcie_sgl = NULL;
5849 		}
5850 		dma_pool_destroy(ioc->pcie_sgl_dma_pool);
5851 	}
5852 	kfree(ioc->pcie_sg_lookup);
5853 	ioc->pcie_sg_lookup = NULL;
5854 
5855 	if (ioc->config_page) {
5856 		dexitprintk(ioc,
5857 			    ioc_info(ioc, "config_page(0x%p): free\n",
5858 				     ioc->config_page));
5859 		dma_free_coherent(&ioc->pdev->dev, ioc->config_page_sz,
5860 		    ioc->config_page, ioc->config_page_dma);
5861 	}
5862 
5863 	kfree(ioc->hpr_lookup);
5864 	ioc->hpr_lookup = NULL;
5865 	kfree(ioc->internal_lookup);
5866 	ioc->internal_lookup = NULL;
5867 	if (ioc->chain_lookup) {
5868 		for (i = 0; i < ioc->scsiio_depth; i++) {
5869 			for (j = ioc->chains_per_prp_buffer;
5870 			    j < ioc->chains_needed_per_io; j++) {
5871 				ct = &ioc->chain_lookup[i].chains_per_smid[j];
5872 				if (ct && ct->chain_buffer)
5873 					dma_pool_free(ioc->chain_dma_pool,
5874 						ct->chain_buffer,
5875 						ct->chain_buffer_dma);
5876 			}
5877 			kfree(ioc->chain_lookup[i].chains_per_smid);
5878 		}
5879 		dma_pool_destroy(ioc->chain_dma_pool);
5880 		kfree(ioc->chain_lookup);
5881 		ioc->chain_lookup = NULL;
5882 	}
5883 
5884 	kfree(ioc->io_queue_num);
5885 	ioc->io_queue_num = NULL;
5886 }
5887 
5888 /**
5889  * mpt3sas_check_same_4gb_region - checks whether all reply queues in a set are
5890  *	having same upper 32bits in their base memory address.
5891  * @start_address: Base address of a reply queue set
5892  * @pool_sz: Size of single Reply Descriptor Post Queues pool size
5893  *
5894  * Return: 1 if reply queues in a set have a same upper 32bits in their base
5895  * memory address, else 0.
5896  */
5897 static int
5898 mpt3sas_check_same_4gb_region(dma_addr_t start_address, u32 pool_sz)
5899 {
5900 	dma_addr_t end_address;
5901 
5902 	end_address = start_address + pool_sz - 1;
5903 
5904 	if (upper_32_bits(start_address) == upper_32_bits(end_address))
5905 		return 1;
5906 	else
5907 		return 0;
5908 }
5909 
5910 /**
5911  * _base_reduce_hba_queue_depth- Retry with reduced queue depth
5912  * @ioc: Adapter object
5913  *
5914  * Return: 0 for success, non-zero for failure.
5915  **/
5916 static inline int
5917 _base_reduce_hba_queue_depth(struct MPT3SAS_ADAPTER *ioc)
5918 {
5919 	int reduce_sz = 64;
5920 
5921 	if ((ioc->hba_queue_depth - reduce_sz) >
5922 	    (ioc->internal_depth + INTERNAL_SCSIIO_CMDS_COUNT)) {
5923 		ioc->hba_queue_depth -= reduce_sz;
5924 		return 0;
5925 	} else
5926 		return -ENOMEM;
5927 }
5928 
5929 /**
5930  * _base_allocate_pcie_sgl_pool - Allocating DMA'able memory
5931  *			for pcie sgl pools.
5932  * @ioc: Adapter object
5933  * @sz: DMA Pool size
5934  *
5935  * Return: 0 for success, non-zero for failure.
5936  */
5937 
5938 static int
5939 _base_allocate_pcie_sgl_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz)
5940 {
5941 	int i = 0, j = 0;
5942 	struct chain_tracker *ct;
5943 
5944 	ioc->pcie_sgl_dma_pool =
5945 	    dma_pool_create("PCIe SGL pool", &ioc->pdev->dev, sz,
5946 	    ioc->page_size, 0);
5947 	if (!ioc->pcie_sgl_dma_pool) {
5948 		ioc_err(ioc, "PCIe SGL pool: dma_pool_create failed\n");
5949 		return -ENOMEM;
5950 	}
5951 
5952 	ioc->chains_per_prp_buffer = sz/ioc->chain_segment_sz;
5953 	ioc->chains_per_prp_buffer =
5954 	    min(ioc->chains_per_prp_buffer, ioc->chains_needed_per_io);
5955 	for (i = 0; i < ioc->scsiio_depth; i++) {
5956 		ioc->pcie_sg_lookup[i].pcie_sgl =
5957 		    dma_pool_alloc(ioc->pcie_sgl_dma_pool, GFP_KERNEL,
5958 		    &ioc->pcie_sg_lookup[i].pcie_sgl_dma);
5959 		if (!ioc->pcie_sg_lookup[i].pcie_sgl) {
5960 			ioc_err(ioc, "PCIe SGL pool: dma_pool_alloc failed\n");
5961 			return -EAGAIN;
5962 		}
5963 
5964 		if (!mpt3sas_check_same_4gb_region(
5965 		    ioc->pcie_sg_lookup[i].pcie_sgl_dma, sz)) {
5966 			ioc_err(ioc, "PCIE SGLs are not in same 4G !! pcie sgl (0x%p) dma = (0x%llx)\n",
5967 			    ioc->pcie_sg_lookup[i].pcie_sgl,
5968 			    (unsigned long long)
5969 			    ioc->pcie_sg_lookup[i].pcie_sgl_dma);
5970 			ioc->use_32bit_dma = true;
5971 			return -EAGAIN;
5972 		}
5973 
5974 		for (j = 0; j < ioc->chains_per_prp_buffer; j++) {
5975 			ct = &ioc->chain_lookup[i].chains_per_smid[j];
5976 			ct->chain_buffer =
5977 			    ioc->pcie_sg_lookup[i].pcie_sgl +
5978 			    (j * ioc->chain_segment_sz);
5979 			ct->chain_buffer_dma =
5980 			    ioc->pcie_sg_lookup[i].pcie_sgl_dma +
5981 			    (j * ioc->chain_segment_sz);
5982 		}
5983 	}
5984 	dinitprintk(ioc, ioc_info(ioc,
5985 	    "PCIe sgl pool depth(%d), element_size(%d), pool_size(%d kB)\n",
5986 	    ioc->scsiio_depth, sz, (sz * ioc->scsiio_depth)/1024));
5987 	dinitprintk(ioc, ioc_info(ioc,
5988 	    "Number of chains can fit in a PRP page(%d)\n",
5989 	    ioc->chains_per_prp_buffer));
5990 	return 0;
5991 }
5992 
5993 /**
5994  * _base_allocate_chain_dma_pool - Allocating DMA'able memory
5995  *			for chain dma pool.
5996  * @ioc: Adapter object
5997  * @sz: DMA Pool size
5998  *
5999  * Return: 0 for success, non-zero for failure.
6000  */
6001 static int
6002 _base_allocate_chain_dma_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz)
6003 {
6004 	int i = 0, j = 0;
6005 	struct chain_tracker *ctr;
6006 
6007 	ioc->chain_dma_pool = dma_pool_create("chain pool", &ioc->pdev->dev,
6008 	    ioc->chain_segment_sz, 16, 0);
6009 	if (!ioc->chain_dma_pool)
6010 		return -ENOMEM;
6011 
6012 	for (i = 0; i < ioc->scsiio_depth; i++) {
6013 		for (j = ioc->chains_per_prp_buffer;
6014 		    j < ioc->chains_needed_per_io; j++) {
6015 			ctr = &ioc->chain_lookup[i].chains_per_smid[j];
6016 			ctr->chain_buffer = dma_pool_alloc(ioc->chain_dma_pool,
6017 			    GFP_KERNEL, &ctr->chain_buffer_dma);
6018 			if (!ctr->chain_buffer)
6019 				return -EAGAIN;
6020 			if (!mpt3sas_check_same_4gb_region(
6021 			    ctr->chain_buffer_dma, ioc->chain_segment_sz)) {
6022 				ioc_err(ioc,
6023 				    "Chain buffers are not in same 4G !!! Chain buff (0x%p) dma = (0x%llx)\n",
6024 				    ctr->chain_buffer,
6025 				    (unsigned long long)ctr->chain_buffer_dma);
6026 				ioc->use_32bit_dma = true;
6027 				return -EAGAIN;
6028 			}
6029 		}
6030 	}
6031 	dinitprintk(ioc, ioc_info(ioc,
6032 	    "chain_lookup depth (%d), frame_size(%d), pool_size(%d kB)\n",
6033 	    ioc->scsiio_depth, ioc->chain_segment_sz, ((ioc->scsiio_depth *
6034 	    (ioc->chains_needed_per_io - ioc->chains_per_prp_buffer) *
6035 	    ioc->chain_segment_sz))/1024));
6036 	return 0;
6037 }
6038 
6039 /**
6040  * _base_allocate_sense_dma_pool - Allocating DMA'able memory
6041  *			for sense dma pool.
6042  * @ioc: Adapter object
6043  * @sz: DMA Pool size
6044  * Return: 0 for success, non-zero for failure.
6045  */
6046 static int
6047 _base_allocate_sense_dma_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz)
6048 {
6049 	ioc->sense_dma_pool =
6050 	    dma_pool_create("sense pool", &ioc->pdev->dev, sz, 4, 0);
6051 	if (!ioc->sense_dma_pool)
6052 		return -ENOMEM;
6053 	ioc->sense = dma_pool_alloc(ioc->sense_dma_pool,
6054 	    GFP_KERNEL, &ioc->sense_dma);
6055 	if (!ioc->sense)
6056 		return -EAGAIN;
6057 	if (!mpt3sas_check_same_4gb_region(ioc->sense_dma, sz)) {
6058 		dinitprintk(ioc, pr_err(
6059 		    "Bad Sense Pool! sense (0x%p) sense_dma = (0x%llx)\n",
6060 		    ioc->sense, (unsigned long long) ioc->sense_dma));
6061 		ioc->use_32bit_dma = true;
6062 		return -EAGAIN;
6063 	}
6064 	ioc_info(ioc,
6065 	    "sense pool(0x%p) - dma(0x%llx): depth(%d), element_size(%d), pool_size (%d kB)\n",
6066 	    ioc->sense, (unsigned long long)ioc->sense_dma,
6067 	    ioc->scsiio_depth, SCSI_SENSE_BUFFERSIZE, sz/1024);
6068 	return 0;
6069 }
6070 
6071 /**
6072  * _base_allocate_reply_pool - Allocating DMA'able memory
6073  *			for reply pool.
6074  * @ioc: Adapter object
6075  * @sz: DMA Pool size
6076  * Return: 0 for success, non-zero for failure.
6077  */
6078 static int
6079 _base_allocate_reply_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz)
6080 {
6081 	/* reply pool, 4 byte align */
6082 	ioc->reply_dma_pool = dma_pool_create("reply pool",
6083 	    &ioc->pdev->dev, sz, 4, 0);
6084 	if (!ioc->reply_dma_pool)
6085 		return -ENOMEM;
6086 	ioc->reply = dma_pool_alloc(ioc->reply_dma_pool, GFP_KERNEL,
6087 	    &ioc->reply_dma);
6088 	if (!ioc->reply)
6089 		return -EAGAIN;
6090 	if (!mpt3sas_check_same_4gb_region(ioc->reply_dma, sz)) {
6091 		dinitprintk(ioc, pr_err(
6092 		    "Bad Reply Pool! Reply (0x%p) Reply dma = (0x%llx)\n",
6093 		    ioc->reply, (unsigned long long) ioc->reply_dma));
6094 		ioc->use_32bit_dma = true;
6095 		return -EAGAIN;
6096 	}
6097 	ioc->reply_dma_min_address = (u32)(ioc->reply_dma);
6098 	ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz;
6099 	ioc_info(ioc,
6100 	    "reply pool(0x%p) - dma(0x%llx): depth(%d), frame_size(%d), pool_size(%d kB)\n",
6101 	    ioc->reply, (unsigned long long)ioc->reply_dma,
6102 	    ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024);
6103 	return 0;
6104 }
6105 
6106 /**
6107  * _base_allocate_reply_free_dma_pool - Allocating DMA'able memory
6108  *			for reply free dma pool.
6109  * @ioc: Adapter object
6110  * @sz: DMA Pool size
6111  * Return: 0 for success, non-zero for failure.
6112  */
6113 static int
6114 _base_allocate_reply_free_dma_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz)
6115 {
6116 	/* reply free queue, 16 byte align */
6117 	ioc->reply_free_dma_pool = dma_pool_create(
6118 	    "reply_free pool", &ioc->pdev->dev, sz, 16, 0);
6119 	if (!ioc->reply_free_dma_pool)
6120 		return -ENOMEM;
6121 	ioc->reply_free = dma_pool_alloc(ioc->reply_free_dma_pool,
6122 	    GFP_KERNEL, &ioc->reply_free_dma);
6123 	if (!ioc->reply_free)
6124 		return -EAGAIN;
6125 	if (!mpt3sas_check_same_4gb_region(ioc->reply_free_dma, sz)) {
6126 		dinitprintk(ioc,
6127 		    pr_err("Bad Reply Free Pool! Reply Free (0x%p) Reply Free dma = (0x%llx)\n",
6128 		    ioc->reply_free, (unsigned long long) ioc->reply_free_dma));
6129 		ioc->use_32bit_dma = true;
6130 		return -EAGAIN;
6131 	}
6132 	memset(ioc->reply_free, 0, sz);
6133 	dinitprintk(ioc, ioc_info(ioc,
6134 	    "reply_free pool(0x%p): depth(%d), element_size(%d), pool_size(%d kB)\n",
6135 	    ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024));
6136 	dinitprintk(ioc, ioc_info(ioc,
6137 	    "reply_free_dma (0x%llx)\n",
6138 	    (unsigned long long)ioc->reply_free_dma));
6139 	return 0;
6140 }
6141 
6142 /**
6143  * _base_allocate_reply_post_free_array - Allocating DMA'able memory
6144  *			for reply post free array.
6145  * @ioc: Adapter object
6146  * @reply_post_free_array_sz: DMA Pool size
6147  * Return: 0 for success, non-zero for failure.
6148  */
6149 
6150 static int
6151 _base_allocate_reply_post_free_array(struct MPT3SAS_ADAPTER *ioc,
6152 	u32 reply_post_free_array_sz)
6153 {
6154 	ioc->reply_post_free_array_dma_pool =
6155 	    dma_pool_create("reply_post_free_array pool",
6156 	    &ioc->pdev->dev, reply_post_free_array_sz, 16, 0);
6157 	if (!ioc->reply_post_free_array_dma_pool)
6158 		return -ENOMEM;
6159 	ioc->reply_post_free_array =
6160 	    dma_pool_alloc(ioc->reply_post_free_array_dma_pool,
6161 	    GFP_KERNEL, &ioc->reply_post_free_array_dma);
6162 	if (!ioc->reply_post_free_array)
6163 		return -EAGAIN;
6164 	if (!mpt3sas_check_same_4gb_region(ioc->reply_post_free_array_dma,
6165 	    reply_post_free_array_sz)) {
6166 		dinitprintk(ioc, pr_err(
6167 		    "Bad Reply Free Pool! Reply Free (0x%p) Reply Free dma = (0x%llx)\n",
6168 		    ioc->reply_free,
6169 		    (unsigned long long) ioc->reply_free_dma));
6170 		ioc->use_32bit_dma = true;
6171 		return -EAGAIN;
6172 	}
6173 	return 0;
6174 }
6175 /**
6176  * base_alloc_rdpq_dma_pool - Allocating DMA'able memory
6177  *                     for reply queues.
6178  * @ioc: per adapter object
6179  * @sz: DMA Pool size
6180  * Return: 0 for success, non-zero for failure.
6181  */
6182 static int
6183 base_alloc_rdpq_dma_pool(struct MPT3SAS_ADAPTER *ioc, int sz)
6184 {
6185 	int i = 0;
6186 	u32 dma_alloc_count = 0;
6187 	int reply_post_free_sz = ioc->reply_post_queue_depth *
6188 		sizeof(Mpi2DefaultReplyDescriptor_t);
6189 	int count = ioc->rdpq_array_enable ? ioc->reply_queue_count : 1;
6190 
6191 	ioc->reply_post = kcalloc(count, sizeof(struct reply_post_struct),
6192 			GFP_KERNEL);
6193 	if (!ioc->reply_post)
6194 		return -ENOMEM;
6195 	/*
6196 	 *  For INVADER_SERIES each set of 8 reply queues(0-7, 8-15, ..) and
6197 	 *  VENTURA_SERIES each set of 16 reply queues(0-15, 16-31, ..) should
6198 	 *  be within 4GB boundary i.e reply queues in a set must have same
6199 	 *  upper 32-bits in their memory address. so here driver is allocating
6200 	 *  the DMA'able memory for reply queues according.
6201 	 *  Driver uses limitation of
6202 	 *  VENTURA_SERIES to manage INVADER_SERIES as well.
6203 	 */
6204 	dma_alloc_count = DIV_ROUND_UP(count,
6205 				RDPQ_MAX_INDEX_IN_ONE_CHUNK);
6206 	ioc->reply_post_free_dma_pool =
6207 		dma_pool_create("reply_post_free pool",
6208 		    &ioc->pdev->dev, sz, 16, 0);
6209 	if (!ioc->reply_post_free_dma_pool)
6210 		return -ENOMEM;
6211 	for (i = 0; i < count; i++) {
6212 		if ((i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0) && dma_alloc_count) {
6213 			ioc->reply_post[i].reply_post_free =
6214 			    dma_pool_zalloc(ioc->reply_post_free_dma_pool,
6215 				GFP_KERNEL,
6216 				&ioc->reply_post[i].reply_post_free_dma);
6217 			if (!ioc->reply_post[i].reply_post_free)
6218 				return -ENOMEM;
6219 			/*
6220 			 * Each set of RDPQ pool must satisfy 4gb boundary
6221 			 * restriction.
6222 			 * 1) Check if allocated resources for RDPQ pool are in
6223 			 *	the same 4GB range.
6224 			 * 2) If #1 is true, continue with 64 bit DMA.
6225 			 * 3) If #1 is false, return 1. which means free all the
6226 			 * resources and set DMA mask to 32 and allocate.
6227 			 */
6228 			if (!mpt3sas_check_same_4gb_region(
6229 				ioc->reply_post[i].reply_post_free_dma, sz)) {
6230 				dinitprintk(ioc,
6231 				    ioc_err(ioc, "bad Replypost free pool(0x%p)"
6232 				    "reply_post_free_dma = (0x%llx)\n",
6233 				    ioc->reply_post[i].reply_post_free,
6234 				    (unsigned long long)
6235 				    ioc->reply_post[i].reply_post_free_dma));
6236 				return -EAGAIN;
6237 			}
6238 			dma_alloc_count--;
6239 
6240 		} else {
6241 			ioc->reply_post[i].reply_post_free =
6242 			    (Mpi2ReplyDescriptorsUnion_t *)
6243 			    ((long)ioc->reply_post[i-1].reply_post_free
6244 			    + reply_post_free_sz);
6245 			ioc->reply_post[i].reply_post_free_dma =
6246 			    (dma_addr_t)
6247 			    (ioc->reply_post[i-1].reply_post_free_dma +
6248 			    reply_post_free_sz);
6249 		}
6250 	}
6251 	return 0;
6252 }
6253 
6254 /**
6255  * _base_allocate_memory_pools - allocate start of day memory pools
6256  * @ioc: per adapter object
6257  *
6258  * Return: 0 success, anything else error.
6259  */
6260 static int
6261 _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
6262 {
6263 	struct mpt3sas_facts *facts;
6264 	u16 max_sge_elements;
6265 	u16 chains_needed_per_io;
6266 	u32 sz, total_sz, reply_post_free_sz, reply_post_free_array_sz;
6267 	u32 retry_sz;
6268 	u32 rdpq_sz = 0, sense_sz = 0;
6269 	u16 max_request_credit, nvme_blocks_needed;
6270 	unsigned short sg_tablesize;
6271 	u16 sge_size;
6272 	int i;
6273 	int ret = 0, rc = 0;
6274 
6275 	dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
6276 
6277 
6278 	retry_sz = 0;
6279 	facts = &ioc->facts;
6280 
6281 	/* command line tunables for max sgl entries */
6282 	if (max_sgl_entries != -1)
6283 		sg_tablesize = max_sgl_entries;
6284 	else {
6285 		if (ioc->hba_mpi_version_belonged == MPI2_VERSION)
6286 			sg_tablesize = MPT2SAS_SG_DEPTH;
6287 		else
6288 			sg_tablesize = MPT3SAS_SG_DEPTH;
6289 	}
6290 
6291 	/* max sgl entries <= MPT_KDUMP_MIN_PHYS_SEGMENTS in KDUMP mode */
6292 	if (reset_devices)
6293 		sg_tablesize = min_t(unsigned short, sg_tablesize,
6294 		   MPT_KDUMP_MIN_PHYS_SEGMENTS);
6295 
6296 	if (ioc->is_mcpu_endpoint)
6297 		ioc->shost->sg_tablesize = MPT_MIN_PHYS_SEGMENTS;
6298 	else {
6299 		if (sg_tablesize < MPT_MIN_PHYS_SEGMENTS)
6300 			sg_tablesize = MPT_MIN_PHYS_SEGMENTS;
6301 		else if (sg_tablesize > MPT_MAX_PHYS_SEGMENTS) {
6302 			sg_tablesize = min_t(unsigned short, sg_tablesize,
6303 					SG_MAX_SEGMENTS);
6304 			ioc_warn(ioc, "sg_tablesize(%u) is bigger than kernel defined SG_CHUNK_SIZE(%u)\n",
6305 				 sg_tablesize, MPT_MAX_PHYS_SEGMENTS);
6306 		}
6307 		ioc->shost->sg_tablesize = sg_tablesize;
6308 	}
6309 
6310 	ioc->internal_depth = min_t(int, (facts->HighPriorityCredit + (5)),
6311 		(facts->RequestCredit / 4));
6312 	if (ioc->internal_depth < INTERNAL_CMDS_COUNT) {
6313 		if (facts->RequestCredit <= (INTERNAL_CMDS_COUNT +
6314 				INTERNAL_SCSIIO_CMDS_COUNT)) {
6315 			ioc_err(ioc, "IOC doesn't have enough Request Credits, it has just %d number of credits\n",
6316 				facts->RequestCredit);
6317 			return -ENOMEM;
6318 		}
6319 		ioc->internal_depth = 10;
6320 	}
6321 
6322 	ioc->hi_priority_depth = ioc->internal_depth - (5);
6323 	/* command line tunables  for max controller queue depth */
6324 	if (max_queue_depth != -1 && max_queue_depth != 0) {
6325 		max_request_credit = min_t(u16, max_queue_depth +
6326 			ioc->internal_depth, facts->RequestCredit);
6327 		if (max_request_credit > MAX_HBA_QUEUE_DEPTH)
6328 			max_request_credit =  MAX_HBA_QUEUE_DEPTH;
6329 	} else if (reset_devices)
6330 		max_request_credit = min_t(u16, facts->RequestCredit,
6331 		    (MPT3SAS_KDUMP_SCSI_IO_DEPTH + ioc->internal_depth));
6332 	else
6333 		max_request_credit = min_t(u16, facts->RequestCredit,
6334 		    MAX_HBA_QUEUE_DEPTH);
6335 
6336 	/* Firmware maintains additional facts->HighPriorityCredit number of
6337 	 * credits for HiPriprity Request messages, so hba queue depth will be
6338 	 * sum of max_request_credit and high priority queue depth.
6339 	 */
6340 	ioc->hba_queue_depth = max_request_credit + ioc->hi_priority_depth;
6341 
6342 	/* request frame size */
6343 	ioc->request_sz = facts->IOCRequestFrameSize * 4;
6344 
6345 	/* reply frame size */
6346 	ioc->reply_sz = facts->ReplyFrameSize * 4;
6347 
6348 	/* chain segment size */
6349 	if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
6350 		if (facts->IOCMaxChainSegmentSize)
6351 			ioc->chain_segment_sz =
6352 					facts->IOCMaxChainSegmentSize *
6353 					MAX_CHAIN_ELEMT_SZ;
6354 		else
6355 		/* set to 128 bytes size if IOCMaxChainSegmentSize is zero */
6356 			ioc->chain_segment_sz = DEFAULT_NUM_FWCHAIN_ELEMTS *
6357 						    MAX_CHAIN_ELEMT_SZ;
6358 	} else
6359 		ioc->chain_segment_sz = ioc->request_sz;
6360 
6361 	/* calculate the max scatter element size */
6362 	sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee);
6363 
6364  retry_allocation:
6365 	total_sz = 0;
6366 	/* calculate number of sg elements left over in the 1st frame */
6367 	max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) -
6368 	    sizeof(Mpi2SGEIOUnion_t)) + sge_size);
6369 	ioc->max_sges_in_main_message = max_sge_elements/sge_size;
6370 
6371 	/* now do the same for a chain buffer */
6372 	max_sge_elements = ioc->chain_segment_sz - sge_size;
6373 	ioc->max_sges_in_chain_message = max_sge_elements/sge_size;
6374 
6375 	/*
6376 	 *  MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE
6377 	 */
6378 	chains_needed_per_io = ((ioc->shost->sg_tablesize -
6379 	   ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message)
6380 	    + 1;
6381 	if (chains_needed_per_io > facts->MaxChainDepth) {
6382 		chains_needed_per_io = facts->MaxChainDepth;
6383 		ioc->shost->sg_tablesize = min_t(u16,
6384 		ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message
6385 		* chains_needed_per_io), ioc->shost->sg_tablesize);
6386 	}
6387 	ioc->chains_needed_per_io = chains_needed_per_io;
6388 
6389 	/* reply free queue sizing - taking into account for 64 FW events */
6390 	ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
6391 
6392 	/* mCPU manage single counters for simplicity */
6393 	if (ioc->is_mcpu_endpoint)
6394 		ioc->reply_post_queue_depth = ioc->reply_free_queue_depth;
6395 	else {
6396 		/* calculate reply descriptor post queue depth */
6397 		ioc->reply_post_queue_depth = ioc->hba_queue_depth +
6398 			ioc->reply_free_queue_depth +  1;
6399 		/* align the reply post queue on the next 16 count boundary */
6400 		if (ioc->reply_post_queue_depth % 16)
6401 			ioc->reply_post_queue_depth += 16 -
6402 				(ioc->reply_post_queue_depth % 16);
6403 	}
6404 
6405 	if (ioc->reply_post_queue_depth >
6406 	    facts->MaxReplyDescriptorPostQueueDepth) {
6407 		ioc->reply_post_queue_depth =
6408 				facts->MaxReplyDescriptorPostQueueDepth -
6409 		    (facts->MaxReplyDescriptorPostQueueDepth % 16);
6410 		ioc->hba_queue_depth =
6411 				((ioc->reply_post_queue_depth - 64) / 2) - 1;
6412 		ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
6413 	}
6414 
6415 	ioc_info(ioc,
6416 	    "scatter gather: sge_in_main_msg(%d), sge_per_chain(%d), "
6417 	    "sge_per_io(%d), chains_per_io(%d)\n",
6418 	    ioc->max_sges_in_main_message,
6419 	    ioc->max_sges_in_chain_message,
6420 	    ioc->shost->sg_tablesize,
6421 	    ioc->chains_needed_per_io);
6422 
6423 	/* reply post queue, 16 byte align */
6424 	reply_post_free_sz = ioc->reply_post_queue_depth *
6425 	    sizeof(Mpi2DefaultReplyDescriptor_t);
6426 	rdpq_sz = reply_post_free_sz * RDPQ_MAX_INDEX_IN_ONE_CHUNK;
6427 	if ((_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable)
6428 	    || (ioc->reply_queue_count < RDPQ_MAX_INDEX_IN_ONE_CHUNK))
6429 		rdpq_sz = reply_post_free_sz * ioc->reply_queue_count;
6430 	ret = base_alloc_rdpq_dma_pool(ioc, rdpq_sz);
6431 	if (ret == -EAGAIN) {
6432 		/*
6433 		 * Free allocated bad RDPQ memory pools.
6434 		 * Change dma coherent mask to 32 bit and reallocate RDPQ
6435 		 */
6436 		_base_release_memory_pools(ioc);
6437 		ioc->use_32bit_dma = true;
6438 		if (_base_config_dma_addressing(ioc, ioc->pdev) != 0) {
6439 			ioc_err(ioc,
6440 			    "32 DMA mask failed %s\n", pci_name(ioc->pdev));
6441 			return -ENODEV;
6442 		}
6443 		if (base_alloc_rdpq_dma_pool(ioc, rdpq_sz))
6444 			return -ENOMEM;
6445 	} else if (ret == -ENOMEM)
6446 		return -ENOMEM;
6447 	total_sz = rdpq_sz * (!ioc->rdpq_array_enable ? 1 :
6448 	    DIV_ROUND_UP(ioc->reply_queue_count, RDPQ_MAX_INDEX_IN_ONE_CHUNK));
6449 	ioc->scsiio_depth = ioc->hba_queue_depth -
6450 	    ioc->hi_priority_depth - ioc->internal_depth;
6451 
6452 	/* set the scsi host can_queue depth
6453 	 * with some internal commands that could be outstanding
6454 	 */
6455 	ioc->shost->can_queue = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT;
6456 	dinitprintk(ioc,
6457 		    ioc_info(ioc, "scsi host: can_queue depth (%d)\n",
6458 			     ioc->shost->can_queue));
6459 
6460 	/* contiguous pool for request and chains, 16 byte align, one extra "
6461 	 * "frame for smid=0
6462 	 */
6463 	ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth;
6464 	sz = ((ioc->scsiio_depth + 1) * ioc->request_sz);
6465 
6466 	/* hi-priority queue */
6467 	sz += (ioc->hi_priority_depth * ioc->request_sz);
6468 
6469 	/* internal queue */
6470 	sz += (ioc->internal_depth * ioc->request_sz);
6471 
6472 	ioc->request_dma_sz = sz;
6473 	ioc->request = dma_alloc_coherent(&ioc->pdev->dev, sz,
6474 			&ioc->request_dma, GFP_KERNEL);
6475 	if (!ioc->request) {
6476 		ioc_err(ioc, "request pool: dma_alloc_coherent failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), total(%d kB)\n",
6477 			ioc->hba_queue_depth, ioc->chains_needed_per_io,
6478 			ioc->request_sz, sz / 1024);
6479 		if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH)
6480 			goto out;
6481 		retry_sz = 64;
6482 		ioc->hba_queue_depth -= retry_sz;
6483 		_base_release_memory_pools(ioc);
6484 		goto retry_allocation;
6485 	}
6486 
6487 	if (retry_sz)
6488 		ioc_err(ioc, "request pool: dma_alloc_coherent succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), total(%d kb)\n",
6489 			ioc->hba_queue_depth, ioc->chains_needed_per_io,
6490 			ioc->request_sz, sz / 1024);
6491 
6492 	/* hi-priority queue */
6493 	ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
6494 	    ioc->request_sz);
6495 	ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) *
6496 	    ioc->request_sz);
6497 
6498 	/* internal queue */
6499 	ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth *
6500 	    ioc->request_sz);
6501 	ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
6502 	    ioc->request_sz);
6503 
6504 	ioc_info(ioc,
6505 	    "request pool(0x%p) - dma(0x%llx): "
6506 	    "depth(%d), frame_size(%d), pool_size(%d kB)\n",
6507 	    ioc->request, (unsigned long long) ioc->request_dma,
6508 	    ioc->hba_queue_depth, ioc->request_sz,
6509 	    (ioc->hba_queue_depth * ioc->request_sz) / 1024);
6510 
6511 	total_sz += sz;
6512 
6513 	dinitprintk(ioc,
6514 		    ioc_info(ioc, "scsiio(0x%p): depth(%d)\n",
6515 			     ioc->request, ioc->scsiio_depth));
6516 
6517 	ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH);
6518 	sz = ioc->scsiio_depth * sizeof(struct chain_lookup);
6519 	ioc->chain_lookup = kzalloc(sz, GFP_KERNEL);
6520 	if (!ioc->chain_lookup) {
6521 		ioc_err(ioc, "chain_lookup: __get_free_pages failed\n");
6522 		goto out;
6523 	}
6524 
6525 	sz = ioc->chains_needed_per_io * sizeof(struct chain_tracker);
6526 	for (i = 0; i < ioc->scsiio_depth; i++) {
6527 		ioc->chain_lookup[i].chains_per_smid = kzalloc(sz, GFP_KERNEL);
6528 		if (!ioc->chain_lookup[i].chains_per_smid) {
6529 			ioc_err(ioc, "chain_lookup: kzalloc failed\n");
6530 			goto out;
6531 		}
6532 	}
6533 
6534 	/* initialize hi-priority queue smid's */
6535 	ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
6536 	    sizeof(struct request_tracker), GFP_KERNEL);
6537 	if (!ioc->hpr_lookup) {
6538 		ioc_err(ioc, "hpr_lookup: kcalloc failed\n");
6539 		goto out;
6540 	}
6541 	ioc->hi_priority_smid = ioc->scsiio_depth + 1;
6542 	dinitprintk(ioc,
6543 		    ioc_info(ioc, "hi_priority(0x%p): depth(%d), start smid(%d)\n",
6544 			     ioc->hi_priority,
6545 			     ioc->hi_priority_depth, ioc->hi_priority_smid));
6546 
6547 	/* initialize internal queue smid's */
6548 	ioc->internal_lookup = kcalloc(ioc->internal_depth,
6549 	    sizeof(struct request_tracker), GFP_KERNEL);
6550 	if (!ioc->internal_lookup) {
6551 		ioc_err(ioc, "internal_lookup: kcalloc failed\n");
6552 		goto out;
6553 	}
6554 	ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
6555 	dinitprintk(ioc,
6556 		    ioc_info(ioc, "internal(0x%p): depth(%d), start smid(%d)\n",
6557 			     ioc->internal,
6558 			     ioc->internal_depth, ioc->internal_smid));
6559 
6560 	ioc->io_queue_num = kcalloc(ioc->scsiio_depth,
6561 	    sizeof(u16), GFP_KERNEL);
6562 	if (!ioc->io_queue_num)
6563 		goto out;
6564 	/*
6565 	 * The number of NVMe page sized blocks needed is:
6566 	 *     (((sg_tablesize * 8) - 1) / (page_size - 8)) + 1
6567 	 * ((sg_tablesize * 8) - 1) is the max PRP's minus the first PRP entry
6568 	 * that is placed in the main message frame.  8 is the size of each PRP
6569 	 * entry or PRP list pointer entry.  8 is subtracted from page_size
6570 	 * because of the PRP list pointer entry at the end of a page, so this
6571 	 * is not counted as a PRP entry.  The 1 added page is a round up.
6572 	 *
6573 	 * To avoid allocation failures due to the amount of memory that could
6574 	 * be required for NVMe PRP's, only each set of NVMe blocks will be
6575 	 * contiguous, so a new set is allocated for each possible I/O.
6576 	 */
6577 
6578 	ioc->chains_per_prp_buffer = 0;
6579 	if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) {
6580 		nvme_blocks_needed =
6581 			(ioc->shost->sg_tablesize * NVME_PRP_SIZE) - 1;
6582 		nvme_blocks_needed /= (ioc->page_size - NVME_PRP_SIZE);
6583 		nvme_blocks_needed++;
6584 
6585 		sz = sizeof(struct pcie_sg_list) * ioc->scsiio_depth;
6586 		ioc->pcie_sg_lookup = kzalloc(sz, GFP_KERNEL);
6587 		if (!ioc->pcie_sg_lookup) {
6588 			ioc_info(ioc, "PCIe SGL lookup: kzalloc failed\n");
6589 			goto out;
6590 		}
6591 		sz = nvme_blocks_needed * ioc->page_size;
6592 		rc = _base_allocate_pcie_sgl_pool(ioc, sz);
6593 		if (rc == -ENOMEM)
6594 			return -ENOMEM;
6595 		else if (rc == -EAGAIN)
6596 			goto try_32bit_dma;
6597 		total_sz += sz * ioc->scsiio_depth;
6598 	}
6599 
6600 	rc = _base_allocate_chain_dma_pool(ioc, ioc->chain_segment_sz);
6601 	if (rc == -ENOMEM)
6602 		return -ENOMEM;
6603 	else if (rc == -EAGAIN)
6604 		goto try_32bit_dma;
6605 	total_sz += ioc->chain_segment_sz * ((ioc->chains_needed_per_io -
6606 		ioc->chains_per_prp_buffer) * ioc->scsiio_depth);
6607 	dinitprintk(ioc,
6608 	    ioc_info(ioc, "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n",
6609 	    ioc->chain_depth, ioc->chain_segment_sz,
6610 	    (ioc->chain_depth * ioc->chain_segment_sz) / 1024));
6611 	/* sense buffers, 4 byte align */
6612 	sense_sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
6613 	rc = _base_allocate_sense_dma_pool(ioc, sense_sz);
6614 	if (rc  == -ENOMEM)
6615 		return -ENOMEM;
6616 	else if (rc == -EAGAIN)
6617 		goto try_32bit_dma;
6618 	total_sz += sense_sz;
6619 	/* reply pool, 4 byte align */
6620 	sz = ioc->reply_free_queue_depth * ioc->reply_sz;
6621 	rc = _base_allocate_reply_pool(ioc, sz);
6622 	if (rc == -ENOMEM)
6623 		return -ENOMEM;
6624 	else if (rc == -EAGAIN)
6625 		goto try_32bit_dma;
6626 	total_sz += sz;
6627 
6628 	/* reply free queue, 16 byte align */
6629 	sz = ioc->reply_free_queue_depth * 4;
6630 	rc = _base_allocate_reply_free_dma_pool(ioc, sz);
6631 	if (rc  == -ENOMEM)
6632 		return -ENOMEM;
6633 	else if (rc == -EAGAIN)
6634 		goto try_32bit_dma;
6635 	dinitprintk(ioc,
6636 		    ioc_info(ioc, "reply_free_dma (0x%llx)\n",
6637 			     (unsigned long long)ioc->reply_free_dma));
6638 	total_sz += sz;
6639 	if (ioc->rdpq_array_enable) {
6640 		reply_post_free_array_sz = ioc->reply_queue_count *
6641 		    sizeof(Mpi2IOCInitRDPQArrayEntry);
6642 		rc = _base_allocate_reply_post_free_array(ioc,
6643 		    reply_post_free_array_sz);
6644 		if (rc == -ENOMEM)
6645 			return -ENOMEM;
6646 		else if (rc == -EAGAIN)
6647 			goto try_32bit_dma;
6648 	}
6649 	ioc->config_page_sz = 512;
6650 	ioc->config_page = dma_alloc_coherent(&ioc->pdev->dev,
6651 			ioc->config_page_sz, &ioc->config_page_dma, GFP_KERNEL);
6652 	if (!ioc->config_page) {
6653 		ioc_err(ioc, "config page: dma_pool_alloc failed\n");
6654 		goto out;
6655 	}
6656 
6657 	ioc_info(ioc, "config page(0x%p) - dma(0x%llx): size(%d)\n",
6658 	    ioc->config_page, (unsigned long long)ioc->config_page_dma,
6659 	    ioc->config_page_sz);
6660 	total_sz += ioc->config_page_sz;
6661 
6662 	ioc_info(ioc, "Allocated physical memory: size(%d kB)\n",
6663 		 total_sz / 1024);
6664 	ioc_info(ioc, "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n",
6665 		 ioc->shost->can_queue, facts->RequestCredit);
6666 	ioc_info(ioc, "Scatter Gather Elements per IO(%d)\n",
6667 		 ioc->shost->sg_tablesize);
6668 	return 0;
6669 
6670 try_32bit_dma:
6671 	_base_release_memory_pools(ioc);
6672 	if (ioc->use_32bit_dma && (ioc->dma_mask > 32)) {
6673 		/* Change dma coherent mask to 32 bit and reallocate */
6674 		if (_base_config_dma_addressing(ioc, ioc->pdev) != 0) {
6675 			pr_err("Setting 32 bit coherent DMA mask Failed %s\n",
6676 			    pci_name(ioc->pdev));
6677 			return -ENODEV;
6678 		}
6679 	} else if (_base_reduce_hba_queue_depth(ioc) != 0)
6680 		return -ENOMEM;
6681 	goto retry_allocation;
6682 
6683  out:
6684 	return -ENOMEM;
6685 }
6686 
6687 /**
6688  * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter.
6689  * @ioc: Pointer to MPT_ADAPTER structure
6690  * @cooked: Request raw or cooked IOC state
6691  *
6692  * Return: all IOC Doorbell register bits if cooked==0, else just the
6693  * Doorbell bits in MPI_IOC_STATE_MASK.
6694  */
6695 u32
6696 mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked)
6697 {
6698 	u32 s, sc;
6699 
6700 	s = ioc->base_readl(&ioc->chip->Doorbell);
6701 	sc = s & MPI2_IOC_STATE_MASK;
6702 	return cooked ? sc : s;
6703 }
6704 
6705 /**
6706  * _base_wait_on_iocstate - waiting on a particular ioc state
6707  * @ioc: ?
6708  * @ioc_state: controller state { READY, OPERATIONAL, or RESET }
6709  * @timeout: timeout in second
6710  *
6711  * Return: 0 for success, non-zero for failure.
6712  */
6713 static int
6714 _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout)
6715 {
6716 	u32 count, cntdn;
6717 	u32 current_state;
6718 
6719 	count = 0;
6720 	cntdn = 1000 * timeout;
6721 	do {
6722 		current_state = mpt3sas_base_get_iocstate(ioc, 1);
6723 		if (current_state == ioc_state)
6724 			return 0;
6725 		if (count && current_state == MPI2_IOC_STATE_FAULT)
6726 			break;
6727 		if (count && current_state == MPI2_IOC_STATE_COREDUMP)
6728 			break;
6729 
6730 		usleep_range(1000, 1500);
6731 		count++;
6732 	} while (--cntdn);
6733 
6734 	return current_state;
6735 }
6736 
6737 /**
6738  * _base_dump_reg_set -	This function will print hexdump of register set.
6739  * @ioc: per adapter object
6740  *
6741  * Return: nothing.
6742  */
6743 static inline void
6744 _base_dump_reg_set(struct MPT3SAS_ADAPTER *ioc)
6745 {
6746 	unsigned int i, sz = 256;
6747 	u32 __iomem *reg = (u32 __iomem *)ioc->chip;
6748 
6749 	ioc_info(ioc, "System Register set:\n");
6750 	for (i = 0; i < (sz / sizeof(u32)); i++)
6751 		pr_info("%08x: %08x\n", (i * 4), readl(&reg[i]));
6752 }
6753 
6754 /**
6755  * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
6756  * a write to the doorbell)
6757  * @ioc: per adapter object
6758  * @timeout: timeout in seconds
6759  *
6760  * Return: 0 for success, non-zero for failure.
6761  *
6762  * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
6763  */
6764 
6765 static int
6766 _base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout)
6767 {
6768 	u32 cntdn, count;
6769 	u32 int_status;
6770 
6771 	count = 0;
6772 	cntdn = 1000 * timeout;
6773 	do {
6774 		int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus);
6775 		if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
6776 			dhsprintk(ioc,
6777 				  ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
6778 					   __func__, count, timeout));
6779 			return 0;
6780 		}
6781 
6782 		usleep_range(1000, 1500);
6783 		count++;
6784 	} while (--cntdn);
6785 
6786 	ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n",
6787 		__func__, count, int_status);
6788 	return -EFAULT;
6789 }
6790 
6791 static int
6792 _base_spin_on_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout)
6793 {
6794 	u32 cntdn, count;
6795 	u32 int_status;
6796 
6797 	count = 0;
6798 	cntdn = 2000 * timeout;
6799 	do {
6800 		int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus);
6801 		if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
6802 			dhsprintk(ioc,
6803 				  ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
6804 					   __func__, count, timeout));
6805 			return 0;
6806 		}
6807 
6808 		udelay(500);
6809 		count++;
6810 	} while (--cntdn);
6811 
6812 	ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n",
6813 		__func__, count, int_status);
6814 	return -EFAULT;
6815 
6816 }
6817 
6818 /**
6819  * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell.
6820  * @ioc: per adapter object
6821  * @timeout: timeout in second
6822  *
6823  * Return: 0 for success, non-zero for failure.
6824  *
6825  * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to
6826  * doorbell.
6827  */
6828 static int
6829 _base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout)
6830 {
6831 	u32 cntdn, count;
6832 	u32 int_status;
6833 	u32 doorbell;
6834 
6835 	count = 0;
6836 	cntdn = 1000 * timeout;
6837 	do {
6838 		int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus);
6839 		if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
6840 			dhsprintk(ioc,
6841 				  ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
6842 					   __func__, count, timeout));
6843 			return 0;
6844 		} else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
6845 			doorbell = ioc->base_readl(&ioc->chip->Doorbell);
6846 			if ((doorbell & MPI2_IOC_STATE_MASK) ==
6847 			    MPI2_IOC_STATE_FAULT) {
6848 				mpt3sas_print_fault_code(ioc, doorbell);
6849 				return -EFAULT;
6850 			}
6851 			if ((doorbell & MPI2_IOC_STATE_MASK) ==
6852 			    MPI2_IOC_STATE_COREDUMP) {
6853 				mpt3sas_print_coredump_info(ioc, doorbell);
6854 				return -EFAULT;
6855 			}
6856 		} else if (int_status == 0xFFFFFFFF)
6857 			goto out;
6858 
6859 		usleep_range(1000, 1500);
6860 		count++;
6861 	} while (--cntdn);
6862 
6863  out:
6864 	ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n",
6865 		__func__, count, int_status);
6866 	return -EFAULT;
6867 }
6868 
6869 /**
6870  * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use
6871  * @ioc: per adapter object
6872  * @timeout: timeout in second
6873  *
6874  * Return: 0 for success, non-zero for failure.
6875  */
6876 static int
6877 _base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout)
6878 {
6879 	u32 cntdn, count;
6880 	u32 doorbell_reg;
6881 
6882 	count = 0;
6883 	cntdn = 1000 * timeout;
6884 	do {
6885 		doorbell_reg = ioc->base_readl(&ioc->chip->Doorbell);
6886 		if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
6887 			dhsprintk(ioc,
6888 				  ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
6889 					   __func__, count, timeout));
6890 			return 0;
6891 		}
6892 
6893 		usleep_range(1000, 1500);
6894 		count++;
6895 	} while (--cntdn);
6896 
6897 	ioc_err(ioc, "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n",
6898 		__func__, count, doorbell_reg);
6899 	return -EFAULT;
6900 }
6901 
6902 /**
6903  * _base_send_ioc_reset - send doorbell reset
6904  * @ioc: per adapter object
6905  * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
6906  * @timeout: timeout in second
6907  *
6908  * Return: 0 for success, non-zero for failure.
6909  */
6910 static int
6911 _base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout)
6912 {
6913 	u32 ioc_state;
6914 	int r = 0;
6915 	unsigned long flags;
6916 
6917 	if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
6918 		ioc_err(ioc, "%s: unknown reset_type\n", __func__);
6919 		return -EFAULT;
6920 	}
6921 
6922 	if (!(ioc->facts.IOCCapabilities &
6923 	   MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
6924 		return -EFAULT;
6925 
6926 	ioc_info(ioc, "sending message unit reset !!\n");
6927 
6928 	writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
6929 	    &ioc->chip->Doorbell);
6930 	if ((_base_wait_for_doorbell_ack(ioc, 15))) {
6931 		r = -EFAULT;
6932 		goto out;
6933 	}
6934 
6935 	ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout);
6936 	if (ioc_state) {
6937 		ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
6938 			__func__, ioc_state);
6939 		r = -EFAULT;
6940 		goto out;
6941 	}
6942  out:
6943 	if (r != 0) {
6944 		ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
6945 		spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
6946 		/*
6947 		 * Wait for IOC state CoreDump to clear only during
6948 		 * HBA initialization & release time.
6949 		 */
6950 		if ((ioc_state & MPI2_IOC_STATE_MASK) ==
6951 		    MPI2_IOC_STATE_COREDUMP && (ioc->is_driver_loading == 1 ||
6952 		    ioc->fault_reset_work_q == NULL)) {
6953 			spin_unlock_irqrestore(
6954 			    &ioc->ioc_reset_in_progress_lock, flags);
6955 			mpt3sas_print_coredump_info(ioc, ioc_state);
6956 			mpt3sas_base_wait_for_coredump_completion(ioc,
6957 			    __func__);
6958 			spin_lock_irqsave(
6959 			    &ioc->ioc_reset_in_progress_lock, flags);
6960 		}
6961 		spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
6962 	}
6963 	ioc_info(ioc, "message unit reset: %s\n",
6964 		 r == 0 ? "SUCCESS" : "FAILED");
6965 	return r;
6966 }
6967 
6968 /**
6969  * mpt3sas_wait_for_ioc - IOC's operational state is checked here.
6970  * @ioc: per adapter object
6971  * @timeout: timeout in seconds
6972  *
6973  * Return: Waits up to timeout seconds for the IOC to
6974  * become operational. Returns 0 if IOC is present
6975  * and operational; otherwise returns %-EFAULT.
6976  */
6977 
6978 int
6979 mpt3sas_wait_for_ioc(struct MPT3SAS_ADAPTER *ioc, int timeout)
6980 {
6981 	int wait_state_count = 0;
6982 	u32 ioc_state;
6983 
6984 	do {
6985 		ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
6986 		if (ioc_state == MPI2_IOC_STATE_OPERATIONAL)
6987 			break;
6988 
6989 		/*
6990 		 * Watchdog thread will be started after IOC Initialization, so
6991 		 * no need to wait here for IOC state to become operational
6992 		 * when IOC Initialization is on. Instead the driver will
6993 		 * return ETIME status, so that calling function can issue
6994 		 * diag reset operation and retry the command.
6995 		 */
6996 		if (ioc->is_driver_loading)
6997 			return -ETIME;
6998 
6999 		ssleep(1);
7000 		ioc_info(ioc, "%s: waiting for operational state(count=%d)\n",
7001 				__func__, ++wait_state_count);
7002 	} while (--timeout);
7003 	if (!timeout) {
7004 		ioc_err(ioc, "%s: failed due to ioc not operational\n", __func__);
7005 		return -EFAULT;
7006 	}
7007 	if (wait_state_count)
7008 		ioc_info(ioc, "ioc is operational\n");
7009 	return 0;
7010 }
7011 
7012 /**
7013  * _base_handshake_req_reply_wait - send request thru doorbell interface
7014  * @ioc: per adapter object
7015  * @request_bytes: request length
7016  * @request: pointer having request payload
7017  * @reply_bytes: reply length
7018  * @reply: pointer to reply payload
7019  * @timeout: timeout in second
7020  *
7021  * Return: 0 for success, non-zero for failure.
7022  */
7023 static int
7024 _base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes,
7025 	u32 *request, int reply_bytes, u16 *reply, int timeout)
7026 {
7027 	MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
7028 	int i;
7029 	u8 failed;
7030 	__le32 *mfp;
7031 
7032 	/* make sure doorbell is not in use */
7033 	if ((ioc->base_readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
7034 		ioc_err(ioc, "doorbell is in use (line=%d)\n", __LINE__);
7035 		return -EFAULT;
7036 	}
7037 
7038 	/* clear pending doorbell interrupts from previous state changes */
7039 	if (ioc->base_readl(&ioc->chip->HostInterruptStatus) &
7040 	    MPI2_HIS_IOC2SYS_DB_STATUS)
7041 		writel(0, &ioc->chip->HostInterruptStatus);
7042 
7043 	/* send message to ioc */
7044 	writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
7045 	    ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)),
7046 	    &ioc->chip->Doorbell);
7047 
7048 	if ((_base_spin_on_doorbell_int(ioc, 5))) {
7049 		ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
7050 			__LINE__);
7051 		return -EFAULT;
7052 	}
7053 	writel(0, &ioc->chip->HostInterruptStatus);
7054 
7055 	if ((_base_wait_for_doorbell_ack(ioc, 5))) {
7056 		ioc_err(ioc, "doorbell handshake ack failed (line=%d)\n",
7057 			__LINE__);
7058 		return -EFAULT;
7059 	}
7060 
7061 	/* send message 32-bits at a time */
7062 	for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) {
7063 		writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
7064 		if ((_base_wait_for_doorbell_ack(ioc, 5)))
7065 			failed = 1;
7066 	}
7067 
7068 	if (failed) {
7069 		ioc_err(ioc, "doorbell handshake sending request failed (line=%d)\n",
7070 			__LINE__);
7071 		return -EFAULT;
7072 	}
7073 
7074 	/* now wait for the reply */
7075 	if ((_base_wait_for_doorbell_int(ioc, timeout))) {
7076 		ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
7077 			__LINE__);
7078 		return -EFAULT;
7079 	}
7080 
7081 	/* read the first two 16-bits, it gives the total length of the reply */
7082 	reply[0] = le16_to_cpu(ioc->base_readl(&ioc->chip->Doorbell)
7083 	    & MPI2_DOORBELL_DATA_MASK);
7084 	writel(0, &ioc->chip->HostInterruptStatus);
7085 	if ((_base_wait_for_doorbell_int(ioc, 5))) {
7086 		ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
7087 			__LINE__);
7088 		return -EFAULT;
7089 	}
7090 	reply[1] = le16_to_cpu(ioc->base_readl(&ioc->chip->Doorbell)
7091 	    & MPI2_DOORBELL_DATA_MASK);
7092 	writel(0, &ioc->chip->HostInterruptStatus);
7093 
7094 	for (i = 2; i < default_reply->MsgLength * 2; i++)  {
7095 		if ((_base_wait_for_doorbell_int(ioc, 5))) {
7096 			ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
7097 				__LINE__);
7098 			return -EFAULT;
7099 		}
7100 		if (i >=  reply_bytes/2) /* overflow case */
7101 			ioc->base_readl(&ioc->chip->Doorbell);
7102 		else
7103 			reply[i] = le16_to_cpu(
7104 			    ioc->base_readl(&ioc->chip->Doorbell)
7105 			    & MPI2_DOORBELL_DATA_MASK);
7106 		writel(0, &ioc->chip->HostInterruptStatus);
7107 	}
7108 
7109 	_base_wait_for_doorbell_int(ioc, 5);
7110 	if (_base_wait_for_doorbell_not_used(ioc, 5) != 0) {
7111 		dhsprintk(ioc,
7112 			  ioc_info(ioc, "doorbell is in use (line=%d)\n",
7113 				   __LINE__));
7114 	}
7115 	writel(0, &ioc->chip->HostInterruptStatus);
7116 
7117 	if (ioc->logging_level & MPT_DEBUG_INIT) {
7118 		mfp = (__le32 *)reply;
7119 		pr_info("\toffset:data\n");
7120 		for (i = 0; i < reply_bytes/4; i++)
7121 			ioc_info(ioc, "\t[0x%02x]:%08x\n", i*4,
7122 			    le32_to_cpu(mfp[i]));
7123 	}
7124 	return 0;
7125 }
7126 
7127 /**
7128  * mpt3sas_base_sas_iounit_control - send sas iounit control to FW
7129  * @ioc: per adapter object
7130  * @mpi_reply: the reply payload from FW
7131  * @mpi_request: the request payload sent to FW
7132  *
7133  * The SAS IO Unit Control Request message allows the host to perform low-level
7134  * operations, such as resets on the PHYs of the IO Unit, also allows the host
7135  * to obtain the IOC assigned device handles for a device if it has other
7136  * identifying information about the device, in addition allows the host to
7137  * remove IOC resources associated with the device.
7138  *
7139  * Return: 0 for success, non-zero for failure.
7140  */
7141 int
7142 mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc,
7143 	Mpi2SasIoUnitControlReply_t *mpi_reply,
7144 	Mpi2SasIoUnitControlRequest_t *mpi_request)
7145 {
7146 	u16 smid;
7147 	u8 issue_reset = 0;
7148 	int rc;
7149 	void *request;
7150 
7151 	dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7152 
7153 	mutex_lock(&ioc->base_cmds.mutex);
7154 
7155 	if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
7156 		ioc_err(ioc, "%s: base_cmd in use\n", __func__);
7157 		rc = -EAGAIN;
7158 		goto out;
7159 	}
7160 
7161 	rc = mpt3sas_wait_for_ioc(ioc, IOC_OPERATIONAL_WAIT_COUNT);
7162 	if (rc)
7163 		goto out;
7164 
7165 	smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
7166 	if (!smid) {
7167 		ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
7168 		rc = -EAGAIN;
7169 		goto out;
7170 	}
7171 
7172 	rc = 0;
7173 	ioc->base_cmds.status = MPT3_CMD_PENDING;
7174 	request = mpt3sas_base_get_msg_frame(ioc, smid);
7175 	ioc->base_cmds.smid = smid;
7176 	memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t));
7177 	if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
7178 	    mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
7179 		ioc->ioc_link_reset_in_progress = 1;
7180 	init_completion(&ioc->base_cmds.done);
7181 	ioc->put_smid_default(ioc, smid);
7182 	wait_for_completion_timeout(&ioc->base_cmds.done,
7183 	    msecs_to_jiffies(10000));
7184 	if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
7185 	    mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) &&
7186 	    ioc->ioc_link_reset_in_progress)
7187 		ioc->ioc_link_reset_in_progress = 0;
7188 	if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
7189 		mpt3sas_check_cmd_timeout(ioc, ioc->base_cmds.status,
7190 		    mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t)/4,
7191 		    issue_reset);
7192 		goto issue_host_reset;
7193 	}
7194 	if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
7195 		memcpy(mpi_reply, ioc->base_cmds.reply,
7196 		    sizeof(Mpi2SasIoUnitControlReply_t));
7197 	else
7198 		memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t));
7199 	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
7200 	goto out;
7201 
7202  issue_host_reset:
7203 	if (issue_reset)
7204 		mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
7205 	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
7206 	rc = -EFAULT;
7207  out:
7208 	mutex_unlock(&ioc->base_cmds.mutex);
7209 	return rc;
7210 }
7211 
7212 /**
7213  * mpt3sas_base_scsi_enclosure_processor - sending request to sep device
7214  * @ioc: per adapter object
7215  * @mpi_reply: the reply payload from FW
7216  * @mpi_request: the request payload sent to FW
7217  *
7218  * The SCSI Enclosure Processor request message causes the IOC to
7219  * communicate with SES devices to control LED status signals.
7220  *
7221  * Return: 0 for success, non-zero for failure.
7222  */
7223 int
7224 mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc,
7225 	Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request)
7226 {
7227 	u16 smid;
7228 	u8 issue_reset = 0;
7229 	int rc;
7230 	void *request;
7231 
7232 	dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7233 
7234 	mutex_lock(&ioc->base_cmds.mutex);
7235 
7236 	if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
7237 		ioc_err(ioc, "%s: base_cmd in use\n", __func__);
7238 		rc = -EAGAIN;
7239 		goto out;
7240 	}
7241 
7242 	rc = mpt3sas_wait_for_ioc(ioc, IOC_OPERATIONAL_WAIT_COUNT);
7243 	if (rc)
7244 		goto out;
7245 
7246 	smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
7247 	if (!smid) {
7248 		ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
7249 		rc = -EAGAIN;
7250 		goto out;
7251 	}
7252 
7253 	rc = 0;
7254 	ioc->base_cmds.status = MPT3_CMD_PENDING;
7255 	request = mpt3sas_base_get_msg_frame(ioc, smid);
7256 	ioc->base_cmds.smid = smid;
7257 	memset(request, 0, ioc->request_sz);
7258 	memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
7259 	init_completion(&ioc->base_cmds.done);
7260 	ioc->put_smid_default(ioc, smid);
7261 	wait_for_completion_timeout(&ioc->base_cmds.done,
7262 	    msecs_to_jiffies(10000));
7263 	if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
7264 		mpt3sas_check_cmd_timeout(ioc,
7265 		    ioc->base_cmds.status, mpi_request,
7266 		    sizeof(Mpi2SepRequest_t)/4, issue_reset);
7267 		goto issue_host_reset;
7268 	}
7269 	if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
7270 		memcpy(mpi_reply, ioc->base_cmds.reply,
7271 		    sizeof(Mpi2SepReply_t));
7272 	else
7273 		memset(mpi_reply, 0, sizeof(Mpi2SepReply_t));
7274 	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
7275 	goto out;
7276 
7277  issue_host_reset:
7278 	if (issue_reset)
7279 		mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
7280 	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
7281 	rc = -EFAULT;
7282  out:
7283 	mutex_unlock(&ioc->base_cmds.mutex);
7284 	return rc;
7285 }
7286 
7287 /**
7288  * _base_get_port_facts - obtain port facts reply and save in ioc
7289  * @ioc: per adapter object
7290  * @port: ?
7291  *
7292  * Return: 0 for success, non-zero for failure.
7293  */
7294 static int
7295 _base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port)
7296 {
7297 	Mpi2PortFactsRequest_t mpi_request;
7298 	Mpi2PortFactsReply_t mpi_reply;
7299 	struct mpt3sas_port_facts *pfacts;
7300 	int mpi_reply_sz, mpi_request_sz, r;
7301 
7302 	dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7303 
7304 	mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
7305 	mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
7306 	memset(&mpi_request, 0, mpi_request_sz);
7307 	mpi_request.Function = MPI2_FUNCTION_PORT_FACTS;
7308 	mpi_request.PortNumber = port;
7309 	r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
7310 	    (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5);
7311 
7312 	if (r != 0) {
7313 		ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r);
7314 		return r;
7315 	}
7316 
7317 	pfacts = &ioc->pfacts[port];
7318 	memset(pfacts, 0, sizeof(struct mpt3sas_port_facts));
7319 	pfacts->PortNumber = mpi_reply.PortNumber;
7320 	pfacts->VP_ID = mpi_reply.VP_ID;
7321 	pfacts->VF_ID = mpi_reply.VF_ID;
7322 	pfacts->MaxPostedCmdBuffers =
7323 	    le16_to_cpu(mpi_reply.MaxPostedCmdBuffers);
7324 
7325 	return 0;
7326 }
7327 
7328 /**
7329  * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL
7330  * @ioc: per adapter object
7331  * @timeout:
7332  *
7333  * Return: 0 for success, non-zero for failure.
7334  */
7335 static int
7336 _base_wait_for_iocstate(struct MPT3SAS_ADAPTER *ioc, int timeout)
7337 {
7338 	u32 ioc_state;
7339 	int rc;
7340 
7341 	dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7342 
7343 	if (ioc->pci_error_recovery) {
7344 		dfailprintk(ioc,
7345 			    ioc_info(ioc, "%s: host in pci error recovery\n",
7346 				     __func__));
7347 		return -EFAULT;
7348 	}
7349 
7350 	ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
7351 	dhsprintk(ioc,
7352 		  ioc_info(ioc, "%s: ioc_state(0x%08x)\n",
7353 			   __func__, ioc_state));
7354 
7355 	if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) ||
7356 	    (ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
7357 		return 0;
7358 
7359 	if (ioc_state & MPI2_DOORBELL_USED) {
7360 		dhsprintk(ioc, ioc_info(ioc, "unexpected doorbell active!\n"));
7361 		goto issue_diag_reset;
7362 	}
7363 
7364 	if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
7365 		mpt3sas_print_fault_code(ioc, ioc_state &
7366 		    MPI2_DOORBELL_DATA_MASK);
7367 		goto issue_diag_reset;
7368 	} else if ((ioc_state & MPI2_IOC_STATE_MASK) ==
7369 	    MPI2_IOC_STATE_COREDUMP) {
7370 		ioc_info(ioc,
7371 		    "%s: Skipping the diag reset here. (ioc_state=0x%x)\n",
7372 		    __func__, ioc_state);
7373 		return -EFAULT;
7374 	}
7375 
7376 	ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout);
7377 	if (ioc_state) {
7378 		dfailprintk(ioc,
7379 			    ioc_info(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
7380 				     __func__, ioc_state));
7381 		return -EFAULT;
7382 	}
7383 
7384  issue_diag_reset:
7385 	rc = _base_diag_reset(ioc);
7386 	return rc;
7387 }
7388 
7389 /**
7390  * _base_get_ioc_facts - obtain ioc facts reply and save in ioc
7391  * @ioc: per adapter object
7392  *
7393  * Return: 0 for success, non-zero for failure.
7394  */
7395 static int
7396 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc)
7397 {
7398 	Mpi2IOCFactsRequest_t mpi_request;
7399 	Mpi2IOCFactsReply_t mpi_reply;
7400 	struct mpt3sas_facts *facts;
7401 	int mpi_reply_sz, mpi_request_sz, r;
7402 
7403 	dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7404 
7405 	r = _base_wait_for_iocstate(ioc, 10);
7406 	if (r) {
7407 		dfailprintk(ioc,
7408 			    ioc_info(ioc, "%s: failed getting to correct state\n",
7409 				     __func__));
7410 		return r;
7411 	}
7412 	mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
7413 	mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t);
7414 	memset(&mpi_request, 0, mpi_request_sz);
7415 	mpi_request.Function = MPI2_FUNCTION_IOC_FACTS;
7416 	r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
7417 	    (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5);
7418 
7419 	if (r != 0) {
7420 		ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r);
7421 		return r;
7422 	}
7423 
7424 	facts = &ioc->facts;
7425 	memset(facts, 0, sizeof(struct mpt3sas_facts));
7426 	facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion);
7427 	facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion);
7428 	facts->VP_ID = mpi_reply.VP_ID;
7429 	facts->VF_ID = mpi_reply.VF_ID;
7430 	facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions);
7431 	facts->MaxChainDepth = mpi_reply.MaxChainDepth;
7432 	facts->WhoInit = mpi_reply.WhoInit;
7433 	facts->NumberOfPorts = mpi_reply.NumberOfPorts;
7434 	facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors;
7435 	if (ioc->msix_enable && (facts->MaxMSIxVectors <=
7436 	    MAX_COMBINED_MSIX_VECTORS(ioc->is_gen35_ioc)))
7437 		ioc->combined_reply_queue = 0;
7438 	facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);
7439 	facts->MaxReplyDescriptorPostQueueDepth =
7440 	    le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);
7441 	facts->ProductID = le16_to_cpu(mpi_reply.ProductID);
7442 	facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities);
7443 	if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID))
7444 		ioc->ir_firmware = 1;
7445 	if ((facts->IOCCapabilities &
7446 	      MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE) && (!reset_devices))
7447 		ioc->rdpq_array_capable = 1;
7448 	if ((facts->IOCCapabilities & MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ)
7449 	    && ioc->is_aero_ioc)
7450 		ioc->atomic_desc_capable = 1;
7451 	facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
7452 	facts->IOCRequestFrameSize =
7453 	    le16_to_cpu(mpi_reply.IOCRequestFrameSize);
7454 	if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
7455 		facts->IOCMaxChainSegmentSize =
7456 			le16_to_cpu(mpi_reply.IOCMaxChainSegmentSize);
7457 	}
7458 	facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators);
7459 	facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets);
7460 	ioc->shost->max_id = -1;
7461 	facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders);
7462 	facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures);
7463 	facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags);
7464 	facts->HighPriorityCredit =
7465 	    le16_to_cpu(mpi_reply.HighPriorityCredit);
7466 	facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
7467 	facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
7468 	facts->CurrentHostPageSize = mpi_reply.CurrentHostPageSize;
7469 
7470 	/*
7471 	 * Get the Page Size from IOC Facts. If it's 0, default to 4k.
7472 	 */
7473 	ioc->page_size = 1 << facts->CurrentHostPageSize;
7474 	if (ioc->page_size == 1) {
7475 		ioc_info(ioc, "CurrentHostPageSize is 0: Setting default host page size to 4k\n");
7476 		ioc->page_size = 1 << MPT3SAS_HOST_PAGE_SIZE_4K;
7477 	}
7478 	dinitprintk(ioc,
7479 		    ioc_info(ioc, "CurrentHostPageSize(%d)\n",
7480 			     facts->CurrentHostPageSize));
7481 
7482 	dinitprintk(ioc,
7483 		    ioc_info(ioc, "hba queue depth(%d), max chains per io(%d)\n",
7484 			     facts->RequestCredit, facts->MaxChainDepth));
7485 	dinitprintk(ioc,
7486 		    ioc_info(ioc, "request frame size(%d), reply frame size(%d)\n",
7487 			     facts->IOCRequestFrameSize * 4,
7488 			     facts->ReplyFrameSize * 4));
7489 	return 0;
7490 }
7491 
7492 /**
7493  * _base_send_ioc_init - send ioc_init to firmware
7494  * @ioc: per adapter object
7495  *
7496  * Return: 0 for success, non-zero for failure.
7497  */
7498 static int
7499 _base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc)
7500 {
7501 	Mpi2IOCInitRequest_t mpi_request;
7502 	Mpi2IOCInitReply_t mpi_reply;
7503 	int i, r = 0;
7504 	ktime_t current_time;
7505 	u16 ioc_status;
7506 	u32 reply_post_free_array_sz = 0;
7507 
7508 	dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7509 
7510 	memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
7511 	mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
7512 	mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
7513 	mpi_request.VF_ID = 0; /* TODO */
7514 	mpi_request.VP_ID = 0;
7515 	mpi_request.MsgVersion = cpu_to_le16(ioc->hba_mpi_version_belonged);
7516 	mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
7517 	mpi_request.HostPageSize = MPT3SAS_HOST_PAGE_SIZE_4K;
7518 
7519 	if (_base_is_controller_msix_enabled(ioc))
7520 		mpi_request.HostMSIxVectors = ioc->reply_queue_count;
7521 	mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4);
7522 	mpi_request.ReplyDescriptorPostQueueDepth =
7523 	    cpu_to_le16(ioc->reply_post_queue_depth);
7524 	mpi_request.ReplyFreeQueueDepth =
7525 	    cpu_to_le16(ioc->reply_free_queue_depth);
7526 
7527 	mpi_request.SenseBufferAddressHigh =
7528 	    cpu_to_le32((u64)ioc->sense_dma >> 32);
7529 	mpi_request.SystemReplyAddressHigh =
7530 	    cpu_to_le32((u64)ioc->reply_dma >> 32);
7531 	mpi_request.SystemRequestFrameBaseAddress =
7532 	    cpu_to_le64((u64)ioc->request_dma);
7533 	mpi_request.ReplyFreeQueueAddress =
7534 	    cpu_to_le64((u64)ioc->reply_free_dma);
7535 
7536 	if (ioc->rdpq_array_enable) {
7537 		reply_post_free_array_sz = ioc->reply_queue_count *
7538 		    sizeof(Mpi2IOCInitRDPQArrayEntry);
7539 		memset(ioc->reply_post_free_array, 0, reply_post_free_array_sz);
7540 		for (i = 0; i < ioc->reply_queue_count; i++)
7541 			ioc->reply_post_free_array[i].RDPQBaseAddress =
7542 			    cpu_to_le64(
7543 				(u64)ioc->reply_post[i].reply_post_free_dma);
7544 		mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE;
7545 		mpi_request.ReplyDescriptorPostQueueAddress =
7546 		    cpu_to_le64((u64)ioc->reply_post_free_array_dma);
7547 	} else {
7548 		mpi_request.ReplyDescriptorPostQueueAddress =
7549 		    cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma);
7550 	}
7551 
7552 	/*
7553 	 * Set the flag to enable CoreDump state feature in IOC firmware.
7554 	 */
7555 	mpi_request.ConfigurationFlags |=
7556 	    cpu_to_le16(MPI26_IOCINIT_CFGFLAGS_COREDUMP_ENABLE);
7557 
7558 	/* This time stamp specifies number of milliseconds
7559 	 * since epoch ~ midnight January 1, 1970.
7560 	 */
7561 	current_time = ktime_get_real();
7562 	mpi_request.TimeStamp = cpu_to_le64(ktime_to_ms(current_time));
7563 
7564 	if (ioc->logging_level & MPT_DEBUG_INIT) {
7565 		__le32 *mfp;
7566 		int i;
7567 
7568 		mfp = (__le32 *)&mpi_request;
7569 		ioc_info(ioc, "\toffset:data\n");
7570 		for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
7571 			ioc_info(ioc, "\t[0x%02x]:%08x\n", i*4,
7572 			    le32_to_cpu(mfp[i]));
7573 	}
7574 
7575 	r = _base_handshake_req_reply_wait(ioc,
7576 	    sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request,
7577 	    sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 30);
7578 
7579 	if (r != 0) {
7580 		ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r);
7581 		return r;
7582 	}
7583 
7584 	ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
7585 	if (ioc_status != MPI2_IOCSTATUS_SUCCESS ||
7586 	    mpi_reply.IOCLogInfo) {
7587 		ioc_err(ioc, "%s: failed\n", __func__);
7588 		r = -EIO;
7589 	}
7590 
7591 	/* Reset TimeSync Counter*/
7592 	ioc->timestamp_update_count = 0;
7593 	return r;
7594 }
7595 
7596 /**
7597  * mpt3sas_port_enable_done - command completion routine for port enable
7598  * @ioc: per adapter object
7599  * @smid: system request message index
7600  * @msix_index: MSIX table index supplied by the OS
7601  * @reply: reply message frame(lower 32bit addr)
7602  *
7603  * Return: 1 meaning mf should be freed from _base_interrupt
7604  *          0 means the mf is freed from this function.
7605  */
7606 u8
7607 mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
7608 	u32 reply)
7609 {
7610 	MPI2DefaultReply_t *mpi_reply;
7611 	u16 ioc_status;
7612 
7613 	if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED)
7614 		return 1;
7615 
7616 	mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
7617 	if (!mpi_reply)
7618 		return 1;
7619 
7620 	if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE)
7621 		return 1;
7622 
7623 	ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING;
7624 	ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE;
7625 	ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID;
7626 	memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
7627 	ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
7628 	if (ioc_status != MPI2_IOCSTATUS_SUCCESS)
7629 		ioc->port_enable_failed = 1;
7630 
7631 	if (ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE_ASYNC) {
7632 		ioc->port_enable_cmds.status &= ~MPT3_CMD_COMPLETE_ASYNC;
7633 		if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
7634 			mpt3sas_port_enable_complete(ioc);
7635 			return 1;
7636 		} else {
7637 			ioc->start_scan_failed = ioc_status;
7638 			ioc->start_scan = 0;
7639 			return 1;
7640 		}
7641 	}
7642 	complete(&ioc->port_enable_cmds.done);
7643 	return 1;
7644 }
7645 
7646 /**
7647  * _base_send_port_enable - send port_enable(discovery stuff) to firmware
7648  * @ioc: per adapter object
7649  *
7650  * Return: 0 for success, non-zero for failure.
7651  */
7652 static int
7653 _base_send_port_enable(struct MPT3SAS_ADAPTER *ioc)
7654 {
7655 	Mpi2PortEnableRequest_t *mpi_request;
7656 	Mpi2PortEnableReply_t *mpi_reply;
7657 	int r = 0;
7658 	u16 smid;
7659 	u16 ioc_status;
7660 
7661 	ioc_info(ioc, "sending port enable !!\n");
7662 
7663 	if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
7664 		ioc_err(ioc, "%s: internal command already in use\n", __func__);
7665 		return -EAGAIN;
7666 	}
7667 
7668 	smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
7669 	if (!smid) {
7670 		ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
7671 		return -EAGAIN;
7672 	}
7673 
7674 	ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
7675 	mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
7676 	ioc->port_enable_cmds.smid = smid;
7677 	memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
7678 	mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
7679 
7680 	init_completion(&ioc->port_enable_cmds.done);
7681 	ioc->put_smid_default(ioc, smid);
7682 	wait_for_completion_timeout(&ioc->port_enable_cmds.done, 300*HZ);
7683 	if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) {
7684 		ioc_err(ioc, "%s: timeout\n", __func__);
7685 		_debug_dump_mf(mpi_request,
7686 		    sizeof(Mpi2PortEnableRequest_t)/4);
7687 		if (ioc->port_enable_cmds.status & MPT3_CMD_RESET)
7688 			r = -EFAULT;
7689 		else
7690 			r = -ETIME;
7691 		goto out;
7692 	}
7693 
7694 	mpi_reply = ioc->port_enable_cmds.reply;
7695 	ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
7696 	if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
7697 		ioc_err(ioc, "%s: failed with (ioc_status=0x%08x)\n",
7698 			__func__, ioc_status);
7699 		r = -EFAULT;
7700 		goto out;
7701 	}
7702 
7703  out:
7704 	ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
7705 	ioc_info(ioc, "port enable: %s\n", r == 0 ? "SUCCESS" : "FAILED");
7706 	return r;
7707 }
7708 
7709 /**
7710  * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply)
7711  * @ioc: per adapter object
7712  *
7713  * Return: 0 for success, non-zero for failure.
7714  */
7715 int
7716 mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc)
7717 {
7718 	Mpi2PortEnableRequest_t *mpi_request;
7719 	u16 smid;
7720 
7721 	ioc_info(ioc, "sending port enable !!\n");
7722 
7723 	if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
7724 		ioc_err(ioc, "%s: internal command already in use\n", __func__);
7725 		return -EAGAIN;
7726 	}
7727 
7728 	smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
7729 	if (!smid) {
7730 		ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
7731 		return -EAGAIN;
7732 	}
7733 	ioc->drv_internal_flags |= MPT_DRV_INTERNAL_FIRST_PE_ISSUED;
7734 	ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
7735 	ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE_ASYNC;
7736 	mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
7737 	ioc->port_enable_cmds.smid = smid;
7738 	memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
7739 	mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
7740 
7741 	ioc->put_smid_default(ioc, smid);
7742 	return 0;
7743 }
7744 
7745 /**
7746  * _base_determine_wait_on_discovery - desposition
7747  * @ioc: per adapter object
7748  *
7749  * Decide whether to wait on discovery to complete. Used to either
7750  * locate boot device, or report volumes ahead of physical devices.
7751  *
7752  * Return: 1 for wait, 0 for don't wait.
7753  */
7754 static int
7755 _base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc)
7756 {
7757 	/* We wait for discovery to complete if IR firmware is loaded.
7758 	 * The sas topology events arrive before PD events, so we need time to
7759 	 * turn on the bit in ioc->pd_handles to indicate PD
7760 	 * Also, it maybe required to report Volumes ahead of physical
7761 	 * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set.
7762 	 */
7763 	if (ioc->ir_firmware)
7764 		return 1;
7765 
7766 	/* if no Bios, then we don't need to wait */
7767 	if (!ioc->bios_pg3.BiosVersion)
7768 		return 0;
7769 
7770 	/* Bios is present, then we drop down here.
7771 	 *
7772 	 * If there any entries in the Bios Page 2, then we wait
7773 	 * for discovery to complete.
7774 	 */
7775 
7776 	/* Current Boot Device */
7777 	if ((ioc->bios_pg2.CurrentBootDeviceForm &
7778 	    MPI2_BIOSPAGE2_FORM_MASK) ==
7779 	    MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
7780 	/* Request Boot Device */
7781 	   (ioc->bios_pg2.ReqBootDeviceForm &
7782 	    MPI2_BIOSPAGE2_FORM_MASK) ==
7783 	    MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
7784 	/* Alternate Request Boot Device */
7785 	   (ioc->bios_pg2.ReqAltBootDeviceForm &
7786 	    MPI2_BIOSPAGE2_FORM_MASK) ==
7787 	    MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED)
7788 		return 0;
7789 
7790 	return 1;
7791 }
7792 
7793 /**
7794  * _base_unmask_events - turn on notification for this event
7795  * @ioc: per adapter object
7796  * @event: firmware event
7797  *
7798  * The mask is stored in ioc->event_masks.
7799  */
7800 static void
7801 _base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event)
7802 {
7803 	u32 desired_event;
7804 
7805 	if (event >= 128)
7806 		return;
7807 
7808 	desired_event = (1 << (event % 32));
7809 
7810 	if (event < 32)
7811 		ioc->event_masks[0] &= ~desired_event;
7812 	else if (event < 64)
7813 		ioc->event_masks[1] &= ~desired_event;
7814 	else if (event < 96)
7815 		ioc->event_masks[2] &= ~desired_event;
7816 	else if (event < 128)
7817 		ioc->event_masks[3] &= ~desired_event;
7818 }
7819 
7820 /**
7821  * _base_event_notification - send event notification
7822  * @ioc: per adapter object
7823  *
7824  * Return: 0 for success, non-zero for failure.
7825  */
7826 static int
7827 _base_event_notification(struct MPT3SAS_ADAPTER *ioc)
7828 {
7829 	Mpi2EventNotificationRequest_t *mpi_request;
7830 	u16 smid;
7831 	int r = 0;
7832 	int i, issue_diag_reset = 0;
7833 
7834 	dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7835 
7836 	if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
7837 		ioc_err(ioc, "%s: internal command already in use\n", __func__);
7838 		return -EAGAIN;
7839 	}
7840 
7841 	smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
7842 	if (!smid) {
7843 		ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
7844 		return -EAGAIN;
7845 	}
7846 	ioc->base_cmds.status = MPT3_CMD_PENDING;
7847 	mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
7848 	ioc->base_cmds.smid = smid;
7849 	memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t));
7850 	mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
7851 	mpi_request->VF_ID = 0; /* TODO */
7852 	mpi_request->VP_ID = 0;
7853 	for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
7854 		mpi_request->EventMasks[i] =
7855 		    cpu_to_le32(ioc->event_masks[i]);
7856 	init_completion(&ioc->base_cmds.done);
7857 	ioc->put_smid_default(ioc, smid);
7858 	wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
7859 	if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
7860 		ioc_err(ioc, "%s: timeout\n", __func__);
7861 		_debug_dump_mf(mpi_request,
7862 		    sizeof(Mpi2EventNotificationRequest_t)/4);
7863 		if (ioc->base_cmds.status & MPT3_CMD_RESET)
7864 			r = -EFAULT;
7865 		else
7866 			issue_diag_reset = 1;
7867 
7868 	} else
7869 		dinitprintk(ioc, ioc_info(ioc, "%s: complete\n", __func__));
7870 	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
7871 
7872 	if (issue_diag_reset) {
7873 		if (ioc->drv_internal_flags & MPT_DRV_INTERNAL_FIRST_PE_ISSUED)
7874 			return -EFAULT;
7875 		if (mpt3sas_base_check_for_fault_and_issue_reset(ioc))
7876 			return -EFAULT;
7877 		r = -EAGAIN;
7878 	}
7879 	return r;
7880 }
7881 
7882 /**
7883  * mpt3sas_base_validate_event_type - validating event types
7884  * @ioc: per adapter object
7885  * @event_type: firmware event
7886  *
7887  * This will turn on firmware event notification when application
7888  * ask for that event. We don't mask events that are already enabled.
7889  */
7890 void
7891 mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type)
7892 {
7893 	int i, j;
7894 	u32 event_mask, desired_event;
7895 	u8 send_update_to_fw;
7896 
7897 	for (i = 0, send_update_to_fw = 0; i <
7898 	    MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) {
7899 		event_mask = ~event_type[i];
7900 		desired_event = 1;
7901 		for (j = 0; j < 32; j++) {
7902 			if (!(event_mask & desired_event) &&
7903 			    (ioc->event_masks[i] & desired_event)) {
7904 				ioc->event_masks[i] &= ~desired_event;
7905 				send_update_to_fw = 1;
7906 			}
7907 			desired_event = (desired_event << 1);
7908 		}
7909 	}
7910 
7911 	if (!send_update_to_fw)
7912 		return;
7913 
7914 	mutex_lock(&ioc->base_cmds.mutex);
7915 	_base_event_notification(ioc);
7916 	mutex_unlock(&ioc->base_cmds.mutex);
7917 }
7918 
7919 /**
7920  * _base_diag_reset - the "big hammer" start of day reset
7921  * @ioc: per adapter object
7922  *
7923  * Return: 0 for success, non-zero for failure.
7924  */
7925 static int
7926 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc)
7927 {
7928 	u32 host_diagnostic;
7929 	u32 ioc_state;
7930 	u32 count;
7931 	u32 hcb_size;
7932 
7933 	ioc_info(ioc, "sending diag reset !!\n");
7934 
7935 	pci_cfg_access_lock(ioc->pdev);
7936 
7937 	drsprintk(ioc, ioc_info(ioc, "clear interrupts\n"));
7938 
7939 	count = 0;
7940 	do {
7941 		/* Write magic sequence to WriteSequence register
7942 		 * Loop until in diagnostic mode
7943 		 */
7944 		drsprintk(ioc, ioc_info(ioc, "write magic sequence\n"));
7945 		writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
7946 		writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
7947 		writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
7948 		writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
7949 		writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
7950 		writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
7951 		writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
7952 
7953 		/* wait 100 msec */
7954 		msleep(100);
7955 
7956 		if (count++ > 20) {
7957 			ioc_info(ioc,
7958 			    "Stop writing magic sequence after 20 retries\n");
7959 			_base_dump_reg_set(ioc);
7960 			goto out;
7961 		}
7962 
7963 		host_diagnostic = ioc->base_readl(&ioc->chip->HostDiagnostic);
7964 		drsprintk(ioc,
7965 			  ioc_info(ioc, "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
7966 				   count, host_diagnostic));
7967 
7968 	} while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
7969 
7970 	hcb_size = ioc->base_readl(&ioc->chip->HCBSize);
7971 
7972 	drsprintk(ioc, ioc_info(ioc, "diag reset: issued\n"));
7973 	writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
7974 	     &ioc->chip->HostDiagnostic);
7975 
7976 	/*This delay allows the chip PCIe hardware time to finish reset tasks*/
7977 	msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
7978 
7979 	/* Approximately 300 second max wait */
7980 	for (count = 0; count < (300000000 /
7981 		MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
7982 
7983 		host_diagnostic = ioc->base_readl(&ioc->chip->HostDiagnostic);
7984 
7985 		if (host_diagnostic == 0xFFFFFFFF) {
7986 			ioc_info(ioc,
7987 			    "Invalid host diagnostic register value\n");
7988 			_base_dump_reg_set(ioc);
7989 			goto out;
7990 		}
7991 		if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
7992 			break;
7993 
7994 		msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC / 1000);
7995 	}
7996 
7997 	if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
7998 
7999 		drsprintk(ioc,
8000 			  ioc_info(ioc, "restart the adapter assuming the HCB Address points to good F/W\n"));
8001 		host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
8002 		host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
8003 		writel(host_diagnostic, &ioc->chip->HostDiagnostic);
8004 
8005 		drsprintk(ioc, ioc_info(ioc, "re-enable the HCDW\n"));
8006 		writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
8007 		    &ioc->chip->HCBSize);
8008 	}
8009 
8010 	drsprintk(ioc, ioc_info(ioc, "restart the adapter\n"));
8011 	writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
8012 	    &ioc->chip->HostDiagnostic);
8013 
8014 	drsprintk(ioc,
8015 		  ioc_info(ioc, "disable writes to the diagnostic register\n"));
8016 	writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
8017 
8018 	drsprintk(ioc, ioc_info(ioc, "Wait for FW to go to the READY state\n"));
8019 	ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20);
8020 	if (ioc_state) {
8021 		ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
8022 			__func__, ioc_state);
8023 		_base_dump_reg_set(ioc);
8024 		goto out;
8025 	}
8026 
8027 	pci_cfg_access_unlock(ioc->pdev);
8028 	ioc_info(ioc, "diag reset: SUCCESS\n");
8029 	return 0;
8030 
8031  out:
8032 	pci_cfg_access_unlock(ioc->pdev);
8033 	ioc_err(ioc, "diag reset: FAILED\n");
8034 	return -EFAULT;
8035 }
8036 
8037 /**
8038  * mpt3sas_base_make_ioc_ready - put controller in READY state
8039  * @ioc: per adapter object
8040  * @type: FORCE_BIG_HAMMER or SOFT_RESET
8041  *
8042  * Return: 0 for success, non-zero for failure.
8043  */
8044 int
8045 mpt3sas_base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, enum reset_type type)
8046 {
8047 	u32 ioc_state;
8048 	int rc;
8049 	int count;
8050 
8051 	dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
8052 
8053 	if (ioc->pci_error_recovery)
8054 		return 0;
8055 
8056 	ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
8057 	dhsprintk(ioc,
8058 		  ioc_info(ioc, "%s: ioc_state(0x%08x)\n",
8059 			   __func__, ioc_state));
8060 
8061 	/* if in RESET state, it should move to READY state shortly */
8062 	count = 0;
8063 	if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
8064 		while ((ioc_state & MPI2_IOC_STATE_MASK) !=
8065 		    MPI2_IOC_STATE_READY) {
8066 			if (count++ == 10) {
8067 				ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
8068 					__func__, ioc_state);
8069 				return -EFAULT;
8070 			}
8071 			ssleep(1);
8072 			ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
8073 		}
8074 	}
8075 
8076 	if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY)
8077 		return 0;
8078 
8079 	if (ioc_state & MPI2_DOORBELL_USED) {
8080 		ioc_info(ioc, "unexpected doorbell active!\n");
8081 		goto issue_diag_reset;
8082 	}
8083 
8084 	if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
8085 		mpt3sas_print_fault_code(ioc, ioc_state &
8086 		    MPI2_DOORBELL_DATA_MASK);
8087 		goto issue_diag_reset;
8088 	}
8089 
8090 	if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_COREDUMP) {
8091 		/*
8092 		 * if host reset is invoked while watch dog thread is waiting
8093 		 * for IOC state to be changed to Fault state then driver has
8094 		 * to wait here for CoreDump state to clear otherwise reset
8095 		 * will be issued to the FW and FW move the IOC state to
8096 		 * reset state without copying the FW logs to coredump region.
8097 		 */
8098 		if (ioc->ioc_coredump_loop != MPT3SAS_COREDUMP_LOOP_DONE) {
8099 			mpt3sas_print_coredump_info(ioc, ioc_state &
8100 			    MPI2_DOORBELL_DATA_MASK);
8101 			mpt3sas_base_wait_for_coredump_completion(ioc,
8102 			    __func__);
8103 		}
8104 		goto issue_diag_reset;
8105 	}
8106 
8107 	if (type == FORCE_BIG_HAMMER)
8108 		goto issue_diag_reset;
8109 
8110 	if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
8111 		if (!(_base_send_ioc_reset(ioc,
8112 		    MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15))) {
8113 			return 0;
8114 	}
8115 
8116  issue_diag_reset:
8117 	rc = _base_diag_reset(ioc);
8118 	return rc;
8119 }
8120 
8121 /**
8122  * _base_make_ioc_operational - put controller in OPERATIONAL state
8123  * @ioc: per adapter object
8124  *
8125  * Return: 0 for success, non-zero for failure.
8126  */
8127 static int
8128 _base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc)
8129 {
8130 	int r, i, index, rc;
8131 	unsigned long	flags;
8132 	u32 reply_address;
8133 	u16 smid;
8134 	struct _tr_list *delayed_tr, *delayed_tr_next;
8135 	struct _sc_list *delayed_sc, *delayed_sc_next;
8136 	struct _event_ack_list *delayed_event_ack, *delayed_event_ack_next;
8137 	u8 hide_flag;
8138 	struct adapter_reply_queue *reply_q;
8139 	Mpi2ReplyDescriptorsUnion_t *reply_post_free_contig;
8140 
8141 	dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
8142 
8143 	/* clean the delayed target reset list */
8144 	list_for_each_entry_safe(delayed_tr, delayed_tr_next,
8145 	    &ioc->delayed_tr_list, list) {
8146 		list_del(&delayed_tr->list);
8147 		kfree(delayed_tr);
8148 	}
8149 
8150 
8151 	list_for_each_entry_safe(delayed_tr, delayed_tr_next,
8152 	    &ioc->delayed_tr_volume_list, list) {
8153 		list_del(&delayed_tr->list);
8154 		kfree(delayed_tr);
8155 	}
8156 
8157 	list_for_each_entry_safe(delayed_sc, delayed_sc_next,
8158 	    &ioc->delayed_sc_list, list) {
8159 		list_del(&delayed_sc->list);
8160 		kfree(delayed_sc);
8161 	}
8162 
8163 	list_for_each_entry_safe(delayed_event_ack, delayed_event_ack_next,
8164 	    &ioc->delayed_event_ack_list, list) {
8165 		list_del(&delayed_event_ack->list);
8166 		kfree(delayed_event_ack);
8167 	}
8168 
8169 	spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
8170 
8171 	/* hi-priority queue */
8172 	INIT_LIST_HEAD(&ioc->hpr_free_list);
8173 	smid = ioc->hi_priority_smid;
8174 	for (i = 0; i < ioc->hi_priority_depth; i++, smid++) {
8175 		ioc->hpr_lookup[i].cb_idx = 0xFF;
8176 		ioc->hpr_lookup[i].smid = smid;
8177 		list_add_tail(&ioc->hpr_lookup[i].tracker_list,
8178 		    &ioc->hpr_free_list);
8179 	}
8180 
8181 	/* internal queue */
8182 	INIT_LIST_HEAD(&ioc->internal_free_list);
8183 	smid = ioc->internal_smid;
8184 	for (i = 0; i < ioc->internal_depth; i++, smid++) {
8185 		ioc->internal_lookup[i].cb_idx = 0xFF;
8186 		ioc->internal_lookup[i].smid = smid;
8187 		list_add_tail(&ioc->internal_lookup[i].tracker_list,
8188 		    &ioc->internal_free_list);
8189 	}
8190 
8191 	spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
8192 
8193 	/* initialize Reply Free Queue */
8194 	for (i = 0, reply_address = (u32)ioc->reply_dma ;
8195 	    i < ioc->reply_free_queue_depth ; i++, reply_address +=
8196 	    ioc->reply_sz) {
8197 		ioc->reply_free[i] = cpu_to_le32(reply_address);
8198 		if (ioc->is_mcpu_endpoint)
8199 			_base_clone_reply_to_sys_mem(ioc,
8200 					reply_address, i);
8201 	}
8202 
8203 	/* initialize reply queues */
8204 	if (ioc->is_driver_loading)
8205 		_base_assign_reply_queues(ioc);
8206 
8207 	/* initialize Reply Post Free Queue */
8208 	index = 0;
8209 	reply_post_free_contig = ioc->reply_post[0].reply_post_free;
8210 	list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
8211 		/*
8212 		 * If RDPQ is enabled, switch to the next allocation.
8213 		 * Otherwise advance within the contiguous region.
8214 		 */
8215 		if (ioc->rdpq_array_enable) {
8216 			reply_q->reply_post_free =
8217 				ioc->reply_post[index++].reply_post_free;
8218 		} else {
8219 			reply_q->reply_post_free = reply_post_free_contig;
8220 			reply_post_free_contig += ioc->reply_post_queue_depth;
8221 		}
8222 
8223 		reply_q->reply_post_host_index = 0;
8224 		for (i = 0; i < ioc->reply_post_queue_depth; i++)
8225 			reply_q->reply_post_free[i].Words =
8226 			    cpu_to_le64(ULLONG_MAX);
8227 		if (!_base_is_controller_msix_enabled(ioc))
8228 			goto skip_init_reply_post_free_queue;
8229 	}
8230  skip_init_reply_post_free_queue:
8231 
8232 	r = _base_send_ioc_init(ioc);
8233 	if (r) {
8234 		/*
8235 		 * No need to check IOC state for fault state & issue
8236 		 * diag reset during host reset. This check is need
8237 		 * only during driver load time.
8238 		 */
8239 		if (!ioc->is_driver_loading)
8240 			return r;
8241 
8242 		rc = mpt3sas_base_check_for_fault_and_issue_reset(ioc);
8243 		if (rc || (_base_send_ioc_init(ioc)))
8244 			return r;
8245 	}
8246 
8247 	/* initialize reply free host index */
8248 	ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
8249 	writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
8250 
8251 	/* initialize reply post host index */
8252 	list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
8253 		if (ioc->combined_reply_queue)
8254 			writel((reply_q->msix_index & 7)<<
8255 			   MPI2_RPHI_MSIX_INDEX_SHIFT,
8256 			   ioc->replyPostRegisterIndex[reply_q->msix_index/8]);
8257 		else
8258 			writel(reply_q->msix_index <<
8259 				MPI2_RPHI_MSIX_INDEX_SHIFT,
8260 				&ioc->chip->ReplyPostHostIndex);
8261 
8262 		if (!_base_is_controller_msix_enabled(ioc))
8263 			goto skip_init_reply_post_host_index;
8264 	}
8265 
8266  skip_init_reply_post_host_index:
8267 
8268 	mpt3sas_base_unmask_interrupts(ioc);
8269 
8270 	if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
8271 		r = _base_display_fwpkg_version(ioc);
8272 		if (r)
8273 			return r;
8274 	}
8275 
8276 	r = _base_static_config_pages(ioc);
8277 	if (r)
8278 		return r;
8279 
8280 	r = _base_event_notification(ioc);
8281 	if (r)
8282 		return r;
8283 
8284 	if (!ioc->shost_recovery) {
8285 
8286 		if (ioc->is_warpdrive && ioc->manu_pg10.OEMIdentifier
8287 		    == 0x80) {
8288 			hide_flag = (u8) (
8289 			    le32_to_cpu(ioc->manu_pg10.OEMSpecificFlags0) &
8290 			    MFG_PAGE10_HIDE_SSDS_MASK);
8291 			if (hide_flag != MFG_PAGE10_HIDE_SSDS_MASK)
8292 				ioc->mfg_pg10_hide_flag = hide_flag;
8293 		}
8294 
8295 		ioc->wait_for_discovery_to_complete =
8296 		    _base_determine_wait_on_discovery(ioc);
8297 
8298 		return r; /* scan_start and scan_finished support */
8299 	}
8300 
8301 	r = _base_send_port_enable(ioc);
8302 	if (r)
8303 		return r;
8304 
8305 	return r;
8306 }
8307 
8308 /**
8309  * mpt3sas_base_free_resources - free resources controller resources
8310  * @ioc: per adapter object
8311  */
8312 void
8313 mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc)
8314 {
8315 	dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
8316 
8317 	/* synchronizing freeing resource with pci_access_mutex lock */
8318 	mutex_lock(&ioc->pci_access_mutex);
8319 	if (ioc->chip_phys && ioc->chip) {
8320 		mpt3sas_base_mask_interrupts(ioc);
8321 		ioc->shost_recovery = 1;
8322 		mpt3sas_base_make_ioc_ready(ioc, SOFT_RESET);
8323 		ioc->shost_recovery = 0;
8324 	}
8325 
8326 	mpt3sas_base_unmap_resources(ioc);
8327 	mutex_unlock(&ioc->pci_access_mutex);
8328 	return;
8329 }
8330 
8331 /**
8332  * mpt3sas_base_attach - attach controller instance
8333  * @ioc: per adapter object
8334  *
8335  * Return: 0 for success, non-zero for failure.
8336  */
8337 int
8338 mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
8339 {
8340 	int r, i, rc;
8341 	int cpu_id, last_cpu_id = 0;
8342 
8343 	dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
8344 
8345 	/* setup cpu_msix_table */
8346 	ioc->cpu_count = num_online_cpus();
8347 	for_each_online_cpu(cpu_id)
8348 		last_cpu_id = cpu_id;
8349 	ioc->cpu_msix_table_sz = last_cpu_id + 1;
8350 	ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL);
8351 	ioc->reply_queue_count = 1;
8352 	if (!ioc->cpu_msix_table) {
8353 		ioc_info(ioc, "Allocation for cpu_msix_table failed!!!\n");
8354 		r = -ENOMEM;
8355 		goto out_free_resources;
8356 	}
8357 
8358 	if (ioc->is_warpdrive) {
8359 		ioc->reply_post_host_index = kcalloc(ioc->cpu_msix_table_sz,
8360 		    sizeof(resource_size_t *), GFP_KERNEL);
8361 		if (!ioc->reply_post_host_index) {
8362 			ioc_info(ioc, "Allocation for reply_post_host_index failed!!!\n");
8363 			r = -ENOMEM;
8364 			goto out_free_resources;
8365 		}
8366 	}
8367 
8368 	ioc->smp_affinity_enable = smp_affinity_enable;
8369 
8370 	ioc->rdpq_array_enable_assigned = 0;
8371 	ioc->use_32bit_dma = false;
8372 	ioc->dma_mask = 64;
8373 	if (ioc->is_aero_ioc)
8374 		ioc->base_readl = &_base_readl_aero;
8375 	else
8376 		ioc->base_readl = &_base_readl;
8377 	r = mpt3sas_base_map_resources(ioc);
8378 	if (r)
8379 		goto out_free_resources;
8380 
8381 	pci_set_drvdata(ioc->pdev, ioc->shost);
8382 	r = _base_get_ioc_facts(ioc);
8383 	if (r) {
8384 		rc = mpt3sas_base_check_for_fault_and_issue_reset(ioc);
8385 		if (rc || (_base_get_ioc_facts(ioc)))
8386 			goto out_free_resources;
8387 	}
8388 
8389 	switch (ioc->hba_mpi_version_belonged) {
8390 	case MPI2_VERSION:
8391 		ioc->build_sg_scmd = &_base_build_sg_scmd;
8392 		ioc->build_sg = &_base_build_sg;
8393 		ioc->build_zero_len_sge = &_base_build_zero_len_sge;
8394 		ioc->get_msix_index_for_smlio = &_base_get_msix_index;
8395 		break;
8396 	case MPI25_VERSION:
8397 	case MPI26_VERSION:
8398 		/*
8399 		 * In SAS3.0,
8400 		 * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and
8401 		 * Target Status - all require the IEEE formatted scatter gather
8402 		 * elements.
8403 		 */
8404 		ioc->build_sg_scmd = &_base_build_sg_scmd_ieee;
8405 		ioc->build_sg = &_base_build_sg_ieee;
8406 		ioc->build_nvme_prp = &_base_build_nvme_prp;
8407 		ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee;
8408 		ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t);
8409 		if (ioc->high_iops_queues)
8410 			ioc->get_msix_index_for_smlio =
8411 					&_base_get_high_iops_msix_index;
8412 		else
8413 			ioc->get_msix_index_for_smlio = &_base_get_msix_index;
8414 		break;
8415 	}
8416 	if (ioc->atomic_desc_capable) {
8417 		ioc->put_smid_default = &_base_put_smid_default_atomic;
8418 		ioc->put_smid_scsi_io = &_base_put_smid_scsi_io_atomic;
8419 		ioc->put_smid_fast_path =
8420 				&_base_put_smid_fast_path_atomic;
8421 		ioc->put_smid_hi_priority =
8422 				&_base_put_smid_hi_priority_atomic;
8423 	} else {
8424 		ioc->put_smid_default = &_base_put_smid_default;
8425 		ioc->put_smid_fast_path = &_base_put_smid_fast_path;
8426 		ioc->put_smid_hi_priority = &_base_put_smid_hi_priority;
8427 		if (ioc->is_mcpu_endpoint)
8428 			ioc->put_smid_scsi_io =
8429 				&_base_put_smid_mpi_ep_scsi_io;
8430 		else
8431 			ioc->put_smid_scsi_io = &_base_put_smid_scsi_io;
8432 	}
8433 	/*
8434 	 * These function pointers for other requests that don't
8435 	 * the require IEEE scatter gather elements.
8436 	 *
8437 	 * For example Configuration Pages and SAS IOUNIT Control don't.
8438 	 */
8439 	ioc->build_sg_mpi = &_base_build_sg;
8440 	ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge;
8441 
8442 	r = mpt3sas_base_make_ioc_ready(ioc, SOFT_RESET);
8443 	if (r)
8444 		goto out_free_resources;
8445 
8446 	ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts,
8447 	    sizeof(struct mpt3sas_port_facts), GFP_KERNEL);
8448 	if (!ioc->pfacts) {
8449 		r = -ENOMEM;
8450 		goto out_free_resources;
8451 	}
8452 
8453 	for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
8454 		r = _base_get_port_facts(ioc, i);
8455 		if (r) {
8456 			rc = mpt3sas_base_check_for_fault_and_issue_reset(ioc);
8457 			if (rc || (_base_get_port_facts(ioc, i)))
8458 				goto out_free_resources;
8459 		}
8460 	}
8461 
8462 	r = _base_allocate_memory_pools(ioc);
8463 	if (r)
8464 		goto out_free_resources;
8465 
8466 	if (irqpoll_weight > 0)
8467 		ioc->thresh_hold = irqpoll_weight;
8468 	else
8469 		ioc->thresh_hold = ioc->hba_queue_depth/4;
8470 
8471 	_base_init_irqpolls(ioc);
8472 	init_waitqueue_head(&ioc->reset_wq);
8473 
8474 	/* allocate memory pd handle bitmask list */
8475 	ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
8476 	if (ioc->facts.MaxDevHandle % 8)
8477 		ioc->pd_handles_sz++;
8478 	ioc->pd_handles = kzalloc(ioc->pd_handles_sz,
8479 	    GFP_KERNEL);
8480 	if (!ioc->pd_handles) {
8481 		r = -ENOMEM;
8482 		goto out_free_resources;
8483 	}
8484 	ioc->blocking_handles = kzalloc(ioc->pd_handles_sz,
8485 	    GFP_KERNEL);
8486 	if (!ioc->blocking_handles) {
8487 		r = -ENOMEM;
8488 		goto out_free_resources;
8489 	}
8490 
8491 	/* allocate memory for pending OS device add list */
8492 	ioc->pend_os_device_add_sz = (ioc->facts.MaxDevHandle / 8);
8493 	if (ioc->facts.MaxDevHandle % 8)
8494 		ioc->pend_os_device_add_sz++;
8495 	ioc->pend_os_device_add = kzalloc(ioc->pend_os_device_add_sz,
8496 	    GFP_KERNEL);
8497 	if (!ioc->pend_os_device_add) {
8498 		r = -ENOMEM;
8499 		goto out_free_resources;
8500 	}
8501 
8502 	ioc->device_remove_in_progress_sz = ioc->pend_os_device_add_sz;
8503 	ioc->device_remove_in_progress =
8504 		kzalloc(ioc->device_remove_in_progress_sz, GFP_KERNEL);
8505 	if (!ioc->device_remove_in_progress) {
8506 		r = -ENOMEM;
8507 		goto out_free_resources;
8508 	}
8509 
8510 	ioc->fwfault_debug = mpt3sas_fwfault_debug;
8511 
8512 	/* base internal command bits */
8513 	mutex_init(&ioc->base_cmds.mutex);
8514 	ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
8515 	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
8516 
8517 	/* port_enable command bits */
8518 	ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
8519 	ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
8520 
8521 	/* transport internal command bits */
8522 	ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
8523 	ioc->transport_cmds.status = MPT3_CMD_NOT_USED;
8524 	mutex_init(&ioc->transport_cmds.mutex);
8525 
8526 	/* scsih internal command bits */
8527 	ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
8528 	ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
8529 	mutex_init(&ioc->scsih_cmds.mutex);
8530 
8531 	/* task management internal command bits */
8532 	ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
8533 	ioc->tm_cmds.status = MPT3_CMD_NOT_USED;
8534 	mutex_init(&ioc->tm_cmds.mutex);
8535 
8536 	/* config page internal command bits */
8537 	ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
8538 	ioc->config_cmds.status = MPT3_CMD_NOT_USED;
8539 	mutex_init(&ioc->config_cmds.mutex);
8540 
8541 	/* ctl module internal command bits */
8542 	ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
8543 	ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
8544 	ioc->ctl_cmds.status = MPT3_CMD_NOT_USED;
8545 	mutex_init(&ioc->ctl_cmds.mutex);
8546 
8547 	if (!ioc->base_cmds.reply || !ioc->port_enable_cmds.reply ||
8548 	    !ioc->transport_cmds.reply || !ioc->scsih_cmds.reply ||
8549 	    !ioc->tm_cmds.reply || !ioc->config_cmds.reply ||
8550 	    !ioc->ctl_cmds.reply || !ioc->ctl_cmds.sense) {
8551 		r = -ENOMEM;
8552 		goto out_free_resources;
8553 	}
8554 
8555 	for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
8556 		ioc->event_masks[i] = -1;
8557 
8558 	/* here we enable the events we care about */
8559 	_base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY);
8560 	_base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE);
8561 	_base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
8562 	_base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE);
8563 	_base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE);
8564 	_base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST);
8565 	_base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME);
8566 	_base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK);
8567 	_base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS);
8568 	_base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED);
8569 	_base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD);
8570 	_base_unmask_events(ioc, MPI2_EVENT_ACTIVE_CABLE_EXCEPTION);
8571 	_base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR);
8572 	if (ioc->hba_mpi_version_belonged == MPI26_VERSION) {
8573 		if (ioc->is_gen35_ioc) {
8574 			_base_unmask_events(ioc,
8575 				MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE);
8576 			_base_unmask_events(ioc, MPI2_EVENT_PCIE_ENUMERATION);
8577 			_base_unmask_events(ioc,
8578 				MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST);
8579 		}
8580 	}
8581 	r = _base_make_ioc_operational(ioc);
8582 	if (r == -EAGAIN) {
8583 		r = _base_make_ioc_operational(ioc);
8584 		if (r)
8585 			goto out_free_resources;
8586 	}
8587 
8588 	/*
8589 	 * Copy current copy of IOCFacts in prev_fw_facts
8590 	 * and it will be used during online firmware upgrade.
8591 	 */
8592 	memcpy(&ioc->prev_fw_facts, &ioc->facts,
8593 	    sizeof(struct mpt3sas_facts));
8594 
8595 	ioc->non_operational_loop = 0;
8596 	ioc->ioc_coredump_loop = 0;
8597 	ioc->got_task_abort_from_ioctl = 0;
8598 	return 0;
8599 
8600  out_free_resources:
8601 
8602 	ioc->remove_host = 1;
8603 
8604 	mpt3sas_base_free_resources(ioc);
8605 	_base_release_memory_pools(ioc);
8606 	pci_set_drvdata(ioc->pdev, NULL);
8607 	kfree(ioc->cpu_msix_table);
8608 	if (ioc->is_warpdrive)
8609 		kfree(ioc->reply_post_host_index);
8610 	kfree(ioc->pd_handles);
8611 	kfree(ioc->blocking_handles);
8612 	kfree(ioc->device_remove_in_progress);
8613 	kfree(ioc->pend_os_device_add);
8614 	kfree(ioc->tm_cmds.reply);
8615 	kfree(ioc->transport_cmds.reply);
8616 	kfree(ioc->scsih_cmds.reply);
8617 	kfree(ioc->config_cmds.reply);
8618 	kfree(ioc->base_cmds.reply);
8619 	kfree(ioc->port_enable_cmds.reply);
8620 	kfree(ioc->ctl_cmds.reply);
8621 	kfree(ioc->ctl_cmds.sense);
8622 	kfree(ioc->pfacts);
8623 	ioc->ctl_cmds.reply = NULL;
8624 	ioc->base_cmds.reply = NULL;
8625 	ioc->tm_cmds.reply = NULL;
8626 	ioc->scsih_cmds.reply = NULL;
8627 	ioc->transport_cmds.reply = NULL;
8628 	ioc->config_cmds.reply = NULL;
8629 	ioc->pfacts = NULL;
8630 	return r;
8631 }
8632 
8633 
8634 /**
8635  * mpt3sas_base_detach - remove controller instance
8636  * @ioc: per adapter object
8637  */
8638 void
8639 mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc)
8640 {
8641 	dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
8642 
8643 	mpt3sas_base_stop_watchdog(ioc);
8644 	mpt3sas_base_free_resources(ioc);
8645 	_base_release_memory_pools(ioc);
8646 	mpt3sas_free_enclosure_list(ioc);
8647 	pci_set_drvdata(ioc->pdev, NULL);
8648 	kfree(ioc->cpu_msix_table);
8649 	if (ioc->is_warpdrive)
8650 		kfree(ioc->reply_post_host_index);
8651 	kfree(ioc->pd_handles);
8652 	kfree(ioc->blocking_handles);
8653 	kfree(ioc->device_remove_in_progress);
8654 	kfree(ioc->pend_os_device_add);
8655 	kfree(ioc->pfacts);
8656 	kfree(ioc->ctl_cmds.reply);
8657 	kfree(ioc->ctl_cmds.sense);
8658 	kfree(ioc->base_cmds.reply);
8659 	kfree(ioc->port_enable_cmds.reply);
8660 	kfree(ioc->tm_cmds.reply);
8661 	kfree(ioc->transport_cmds.reply);
8662 	kfree(ioc->scsih_cmds.reply);
8663 	kfree(ioc->config_cmds.reply);
8664 }
8665 
8666 /**
8667  * _base_pre_reset_handler - pre reset handler
8668  * @ioc: per adapter object
8669  */
8670 static void _base_pre_reset_handler(struct MPT3SAS_ADAPTER *ioc)
8671 {
8672 	mpt3sas_scsih_pre_reset_handler(ioc);
8673 	mpt3sas_ctl_pre_reset_handler(ioc);
8674 	dtmprintk(ioc, ioc_info(ioc, "%s: MPT3_IOC_PRE_RESET\n", __func__));
8675 }
8676 
8677 /**
8678  * _base_clear_outstanding_mpt_commands - clears outstanding mpt commands
8679  * @ioc: per adapter object
8680  */
8681 static void
8682 _base_clear_outstanding_mpt_commands(struct MPT3SAS_ADAPTER *ioc)
8683 {
8684 	dtmprintk(ioc,
8685 	    ioc_info(ioc, "%s: clear outstanding mpt cmds\n", __func__));
8686 	if (ioc->transport_cmds.status & MPT3_CMD_PENDING) {
8687 		ioc->transport_cmds.status |= MPT3_CMD_RESET;
8688 		mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid);
8689 		complete(&ioc->transport_cmds.done);
8690 	}
8691 	if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
8692 		ioc->base_cmds.status |= MPT3_CMD_RESET;
8693 		mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid);
8694 		complete(&ioc->base_cmds.done);
8695 	}
8696 	if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
8697 		ioc->port_enable_failed = 1;
8698 		ioc->port_enable_cmds.status |= MPT3_CMD_RESET;
8699 		mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid);
8700 		if (ioc->is_driver_loading) {
8701 			ioc->start_scan_failed =
8702 				MPI2_IOCSTATUS_INTERNAL_ERROR;
8703 			ioc->start_scan = 0;
8704 		} else {
8705 			complete(&ioc->port_enable_cmds.done);
8706 		}
8707 	}
8708 	if (ioc->config_cmds.status & MPT3_CMD_PENDING) {
8709 		ioc->config_cmds.status |= MPT3_CMD_RESET;
8710 		mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid);
8711 		ioc->config_cmds.smid = USHRT_MAX;
8712 		complete(&ioc->config_cmds.done);
8713 	}
8714 }
8715 
8716 /**
8717  * _base_clear_outstanding_commands - clear all outstanding commands
8718  * @ioc: per adapter object
8719  */
8720 static void _base_clear_outstanding_commands(struct MPT3SAS_ADAPTER *ioc)
8721 {
8722 	mpt3sas_scsih_clear_outstanding_scsi_tm_commands(ioc);
8723 	mpt3sas_ctl_clear_outstanding_ioctls(ioc);
8724 	_base_clear_outstanding_mpt_commands(ioc);
8725 }
8726 
8727 /**
8728  * _base_reset_done_handler - reset done handler
8729  * @ioc: per adapter object
8730  */
8731 static void _base_reset_done_handler(struct MPT3SAS_ADAPTER *ioc)
8732 {
8733 	mpt3sas_scsih_reset_done_handler(ioc);
8734 	mpt3sas_ctl_reset_done_handler(ioc);
8735 	dtmprintk(ioc, ioc_info(ioc, "%s: MPT3_IOC_DONE_RESET\n", __func__));
8736 }
8737 
8738 /**
8739  * mpt3sas_wait_for_commands_to_complete - reset controller
8740  * @ioc: Pointer to MPT_ADAPTER structure
8741  *
8742  * This function is waiting 10s for all pending commands to complete
8743  * prior to putting controller in reset.
8744  */
8745 void
8746 mpt3sas_wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc)
8747 {
8748 	u32 ioc_state;
8749 
8750 	ioc->pending_io_count = 0;
8751 
8752 	ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
8753 	if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL)
8754 		return;
8755 
8756 	/* pending command count */
8757 	ioc->pending_io_count = scsi_host_busy(ioc->shost);
8758 
8759 	if (!ioc->pending_io_count)
8760 		return;
8761 
8762 	/* wait for pending commands to complete */
8763 	wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ);
8764 }
8765 
8766 /**
8767  * _base_check_ioc_facts_changes - Look for increase/decrease of IOCFacts
8768  *     attributes during online firmware upgrade and update the corresponding
8769  *     IOC variables accordingly.
8770  *
8771  * @ioc: Pointer to MPT_ADAPTER structure
8772  */
8773 static int
8774 _base_check_ioc_facts_changes(struct MPT3SAS_ADAPTER *ioc)
8775 {
8776 	u16 pd_handles_sz;
8777 	void *pd_handles = NULL, *blocking_handles = NULL;
8778 	void *pend_os_device_add = NULL, *device_remove_in_progress = NULL;
8779 	struct mpt3sas_facts *old_facts = &ioc->prev_fw_facts;
8780 
8781 	if (ioc->facts.MaxDevHandle > old_facts->MaxDevHandle) {
8782 		pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
8783 		if (ioc->facts.MaxDevHandle % 8)
8784 			pd_handles_sz++;
8785 
8786 		pd_handles = krealloc(ioc->pd_handles, pd_handles_sz,
8787 		    GFP_KERNEL);
8788 		if (!pd_handles) {
8789 			ioc_info(ioc,
8790 			    "Unable to allocate the memory for pd_handles of sz: %d\n",
8791 			    pd_handles_sz);
8792 			return -ENOMEM;
8793 		}
8794 		memset(pd_handles + ioc->pd_handles_sz, 0,
8795 		    (pd_handles_sz - ioc->pd_handles_sz));
8796 		ioc->pd_handles = pd_handles;
8797 
8798 		blocking_handles = krealloc(ioc->blocking_handles,
8799 		    pd_handles_sz, GFP_KERNEL);
8800 		if (!blocking_handles) {
8801 			ioc_info(ioc,
8802 			    "Unable to allocate the memory for "
8803 			    "blocking_handles of sz: %d\n",
8804 			    pd_handles_sz);
8805 			return -ENOMEM;
8806 		}
8807 		memset(blocking_handles + ioc->pd_handles_sz, 0,
8808 		    (pd_handles_sz - ioc->pd_handles_sz));
8809 		ioc->blocking_handles = blocking_handles;
8810 		ioc->pd_handles_sz = pd_handles_sz;
8811 
8812 		pend_os_device_add = krealloc(ioc->pend_os_device_add,
8813 		    pd_handles_sz, GFP_KERNEL);
8814 		if (!pend_os_device_add) {
8815 			ioc_info(ioc,
8816 			    "Unable to allocate the memory for pend_os_device_add of sz: %d\n",
8817 			    pd_handles_sz);
8818 			return -ENOMEM;
8819 		}
8820 		memset(pend_os_device_add + ioc->pend_os_device_add_sz, 0,
8821 		    (pd_handles_sz - ioc->pend_os_device_add_sz));
8822 		ioc->pend_os_device_add = pend_os_device_add;
8823 		ioc->pend_os_device_add_sz = pd_handles_sz;
8824 
8825 		device_remove_in_progress = krealloc(
8826 		    ioc->device_remove_in_progress, pd_handles_sz, GFP_KERNEL);
8827 		if (!device_remove_in_progress) {
8828 			ioc_info(ioc,
8829 			    "Unable to allocate the memory for "
8830 			    "device_remove_in_progress of sz: %d\n "
8831 			    , pd_handles_sz);
8832 			return -ENOMEM;
8833 		}
8834 		memset(device_remove_in_progress +
8835 		    ioc->device_remove_in_progress_sz, 0,
8836 		    (pd_handles_sz - ioc->device_remove_in_progress_sz));
8837 		ioc->device_remove_in_progress = device_remove_in_progress;
8838 		ioc->device_remove_in_progress_sz = pd_handles_sz;
8839 	}
8840 
8841 	memcpy(&ioc->prev_fw_facts, &ioc->facts, sizeof(struct mpt3sas_facts));
8842 	return 0;
8843 }
8844 
8845 /**
8846  * mpt3sas_base_hard_reset_handler - reset controller
8847  * @ioc: Pointer to MPT_ADAPTER structure
8848  * @type: FORCE_BIG_HAMMER or SOFT_RESET
8849  *
8850  * Return: 0 for success, non-zero for failure.
8851  */
8852 int
8853 mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc,
8854 	enum reset_type type)
8855 {
8856 	int r;
8857 	unsigned long flags;
8858 	u32 ioc_state;
8859 	u8 is_fault = 0, is_trigger = 0;
8860 
8861 	dtmprintk(ioc, ioc_info(ioc, "%s: enter\n", __func__));
8862 
8863 	if (ioc->pci_error_recovery) {
8864 		ioc_err(ioc, "%s: pci error recovery reset\n", __func__);
8865 		r = 0;
8866 		goto out_unlocked;
8867 	}
8868 
8869 	if (mpt3sas_fwfault_debug)
8870 		mpt3sas_halt_firmware(ioc);
8871 
8872 	/* wait for an active reset in progress to complete */
8873 	mutex_lock(&ioc->reset_in_progress_mutex);
8874 
8875 	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
8876 	ioc->shost_recovery = 1;
8877 	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
8878 
8879 	if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
8880 	    MPT3_DIAG_BUFFER_IS_REGISTERED) &&
8881 	    (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
8882 	    MPT3_DIAG_BUFFER_IS_RELEASED))) {
8883 		is_trigger = 1;
8884 		ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
8885 		if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT ||
8886 		    (ioc_state & MPI2_IOC_STATE_MASK) ==
8887 		    MPI2_IOC_STATE_COREDUMP) {
8888 			is_fault = 1;
8889 			ioc->htb_rel.trigger_info_dwords[1] =
8890 			    (ioc_state & MPI2_DOORBELL_DATA_MASK);
8891 		}
8892 	}
8893 	_base_pre_reset_handler(ioc);
8894 	mpt3sas_wait_for_commands_to_complete(ioc);
8895 	mpt3sas_base_mask_interrupts(ioc);
8896 	mpt3sas_base_pause_mq_polling(ioc);
8897 	r = mpt3sas_base_make_ioc_ready(ioc, type);
8898 	if (r)
8899 		goto out;
8900 	_base_clear_outstanding_commands(ioc);
8901 
8902 	/* If this hard reset is called while port enable is active, then
8903 	 * there is no reason to call make_ioc_operational
8904 	 */
8905 	if (ioc->is_driver_loading && ioc->port_enable_failed) {
8906 		ioc->remove_host = 1;
8907 		r = -EFAULT;
8908 		goto out;
8909 	}
8910 	r = _base_get_ioc_facts(ioc);
8911 	if (r)
8912 		goto out;
8913 
8914 	r = _base_check_ioc_facts_changes(ioc);
8915 	if (r) {
8916 		ioc_info(ioc,
8917 		    "Some of the parameters got changed in this new firmware"
8918 		    " image and it requires system reboot\n");
8919 		goto out;
8920 	}
8921 	if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable)
8922 		panic("%s: Issue occurred with flashing controller firmware."
8923 		      "Please reboot the system and ensure that the correct"
8924 		      " firmware version is running\n", ioc->name);
8925 
8926 	r = _base_make_ioc_operational(ioc);
8927 	if (!r)
8928 		_base_reset_done_handler(ioc);
8929 
8930  out:
8931 	ioc_info(ioc, "%s: %s\n", __func__, r == 0 ? "SUCCESS" : "FAILED");
8932 
8933 	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
8934 	ioc->shost_recovery = 0;
8935 	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
8936 	ioc->ioc_reset_count++;
8937 	mutex_unlock(&ioc->reset_in_progress_mutex);
8938 	mpt3sas_base_resume_mq_polling(ioc);
8939 
8940  out_unlocked:
8941 	if ((r == 0) && is_trigger) {
8942 		if (is_fault)
8943 			mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT);
8944 		else
8945 			mpt3sas_trigger_master(ioc,
8946 			    MASTER_TRIGGER_ADAPTER_RESET);
8947 	}
8948 	dtmprintk(ioc, ioc_info(ioc, "%s: exit\n", __func__));
8949 	return r;
8950 }
8951