1 /*
2  * This is the Fusion MPT base driver providing common API layer interface
3  * for access to MPT (Message Passing Technology) firmware.
4  *
5  * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c
6  * Copyright (C) 2012-2014  LSI Corporation
7  * Copyright (C) 2013-2014 Avago Technologies
8  *  (mailto: MPT-FusionLinux.pdl@avagotech.com)
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License
12  * as published by the Free Software Foundation; either version 2
13  * of the License, or (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * NO WARRANTY
21  * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
22  * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
23  * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
24  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
25  * solely responsible for determining the appropriateness of using and
26  * distributing the Program and assumes all risks associated with its
27  * exercise of rights under this Agreement, including but not limited to
28  * the risks and costs of program errors, damage to or loss of data,
29  * programs or equipment, and unavailability or interruption of operations.
30 
31  * DISCLAIMER OF LIABILITY
32  * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
33  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34  * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
35  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
36  * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
37  * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
38  * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
39 
40  * You should have received a copy of the GNU General Public License
41  * along with this program; if not, write to the Free Software
42  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301,
43  * USA.
44  */
45 
46 #include <linux/kernel.h>
47 #include <linux/module.h>
48 #include <linux/errno.h>
49 #include <linux/init.h>
50 #include <linux/slab.h>
51 #include <linux/types.h>
52 #include <linux/pci.h>
53 #include <linux/kdev_t.h>
54 #include <linux/blkdev.h>
55 #include <linux/delay.h>
56 #include <linux/interrupt.h>
57 #include <linux/dma-mapping.h>
58 #include <linux/io.h>
59 #include <linux/time.h>
60 #include <linux/ktime.h>
61 #include <linux/kthread.h>
62 #include <asm/page.h>        /* To get host page size per arch */
63 #include <linux/aer.h>
64 
65 
66 #include "mpt3sas_base.h"
67 
68 static MPT_CALLBACK	mpt_callbacks[MPT_MAX_CALLBACKS];
69 
70 
71 #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */
72 
73  /* maximum controller queue depth */
74 #define MAX_HBA_QUEUE_DEPTH	30000
75 #define MAX_CHAIN_DEPTH		100000
76 static int max_queue_depth = -1;
77 module_param(max_queue_depth, int, 0444);
78 MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
79 
80 static int max_sgl_entries = -1;
81 module_param(max_sgl_entries, int, 0444);
82 MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
83 
84 static int msix_disable = -1;
85 module_param(msix_disable, int, 0444);
86 MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
87 
88 static int smp_affinity_enable = 1;
89 module_param(smp_affinity_enable, int, 0444);
90 MODULE_PARM_DESC(smp_affinity_enable, "SMP affinity feature enable/disable Default: enable(1)");
91 
92 static int max_msix_vectors = -1;
93 module_param(max_msix_vectors, int, 0444);
94 MODULE_PARM_DESC(max_msix_vectors,
95 	" max msix vectors");
96 
97 static int irqpoll_weight = -1;
98 module_param(irqpoll_weight, int, 0444);
99 MODULE_PARM_DESC(irqpoll_weight,
100 	"irq poll weight (default= one fourth of HBA queue depth)");
101 
102 static int mpt3sas_fwfault_debug;
103 MODULE_PARM_DESC(mpt3sas_fwfault_debug,
104 	" enable detection of firmware fault and halt firmware - (default=0)");
105 
106 static int perf_mode = -1;
107 module_param(perf_mode, int, 0444);
108 MODULE_PARM_DESC(perf_mode,
109 	"Performance mode (only for Aero/Sea Generation), options:\n\t\t"
110 	"0 - balanced: high iops mode is enabled &\n\t\t"
111 	"interrupt coalescing is enabled only on high iops queues,\n\t\t"
112 	"1 - iops: high iops mode is disabled &\n\t\t"
113 	"interrupt coalescing is enabled on all queues,\n\t\t"
114 	"2 - latency: high iops mode is disabled &\n\t\t"
115 	"interrupt coalescing is enabled on all queues with timeout value 0xA,\n"
116 	"\t\tdefault - default perf_mode is 'balanced'"
117 	);
118 
119 static int poll_queues;
120 module_param(poll_queues, int, 0444);
121 MODULE_PARM_DESC(poll_queues, "Number of queues to be use for io_uring poll mode.\n\t\t"
122 	"This parameter is effective only if host_tagset_enable=1. &\n\t\t"
123 	"when poll_queues are enabled then &\n\t\t"
124 	"perf_mode is set to latency mode. &\n\t\t"
125 	);
126 
127 enum mpt3sas_perf_mode {
128 	MPT_PERF_MODE_DEFAULT	= -1,
129 	MPT_PERF_MODE_BALANCED	= 0,
130 	MPT_PERF_MODE_IOPS	= 1,
131 	MPT_PERF_MODE_LATENCY	= 2,
132 };
133 
134 static int
135 _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc,
136 		u32 ioc_state, int timeout);
137 static int
138 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc);
139 static void
140 _base_clear_outstanding_commands(struct MPT3SAS_ADAPTER *ioc);
141 
142 /**
143  * mpt3sas_base_check_cmd_timeout - Function
144  *		to check timeout and command termination due
145  *		to Host reset.
146  *
147  * @ioc:	per adapter object.
148  * @status:	Status of issued command.
149  * @mpi_request:mf request pointer.
150  * @sz:		size of buffer.
151  *
152  * Return: 1/0 Reset to be done or Not
153  */
154 u8
155 mpt3sas_base_check_cmd_timeout(struct MPT3SAS_ADAPTER *ioc,
156 		u8 status, void *mpi_request, int sz)
157 {
158 	u8 issue_reset = 0;
159 
160 	if (!(status & MPT3_CMD_RESET))
161 		issue_reset = 1;
162 
163 	ioc_err(ioc, "Command %s\n",
164 		issue_reset == 0 ? "terminated due to Host Reset" : "Timeout");
165 	_debug_dump_mf(mpi_request, sz);
166 
167 	return issue_reset;
168 }
169 
170 /**
171  * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug.
172  * @val: ?
173  * @kp: ?
174  *
175  * Return: ?
176  */
177 static int
178 _scsih_set_fwfault_debug(const char *val, const struct kernel_param *kp)
179 {
180 	int ret = param_set_int(val, kp);
181 	struct MPT3SAS_ADAPTER *ioc;
182 
183 	if (ret)
184 		return ret;
185 
186 	/* global ioc spinlock to protect controller list on list operations */
187 	pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug);
188 	spin_lock(&gioc_lock);
189 	list_for_each_entry(ioc, &mpt3sas_ioc_list, list)
190 		ioc->fwfault_debug = mpt3sas_fwfault_debug;
191 	spin_unlock(&gioc_lock);
192 	return 0;
193 }
194 module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug,
195 	param_get_int, &mpt3sas_fwfault_debug, 0644);
196 
197 /**
198  * _base_readl_aero - retry readl for max three times.
199  * @addr: MPT Fusion system interface register address
200  *
201  * Retry the readl() for max three times if it gets zero value
202  * while reading the system interface register.
203  */
204 static inline u32
205 _base_readl_aero(const volatile void __iomem *addr)
206 {
207 	u32 i = 0, ret_val;
208 
209 	do {
210 		ret_val = readl(addr);
211 		i++;
212 	} while (ret_val == 0 && i < 3);
213 
214 	return ret_val;
215 }
216 
217 static inline u32
218 _base_readl(const volatile void __iomem *addr)
219 {
220 	return readl(addr);
221 }
222 
223 /**
224  * _base_clone_reply_to_sys_mem - copies reply to reply free iomem
225  *				  in BAR0 space.
226  *
227  * @ioc: per adapter object
228  * @reply: reply message frame(lower 32bit addr)
229  * @index: System request message index.
230  */
231 static void
232 _base_clone_reply_to_sys_mem(struct MPT3SAS_ADAPTER *ioc, u32 reply,
233 		u32 index)
234 {
235 	/*
236 	 * 256 is offset within sys register.
237 	 * 256 offset MPI frame starts. Max MPI frame supported is 32.
238 	 * 32 * 128 = 4K. From here, Clone of reply free for mcpu starts
239 	 */
240 	u16 cmd_credit = ioc->facts.RequestCredit + 1;
241 	void __iomem *reply_free_iomem = (void __iomem *)ioc->chip +
242 			MPI_FRAME_START_OFFSET +
243 			(cmd_credit * ioc->request_sz) + (index * sizeof(u32));
244 
245 	writel(reply, reply_free_iomem);
246 }
247 
248 /**
249  * _base_clone_mpi_to_sys_mem - Writes/copies MPI frames
250  *				to system/BAR0 region.
251  *
252  * @dst_iomem: Pointer to the destination location in BAR0 space.
253  * @src: Pointer to the Source data.
254  * @size: Size of data to be copied.
255  */
256 static void
257 _base_clone_mpi_to_sys_mem(void *dst_iomem, void *src, u32 size)
258 {
259 	int i;
260 	u32 *src_virt_mem = (u32 *)src;
261 
262 	for (i = 0; i < size/4; i++)
263 		writel((u32)src_virt_mem[i],
264 				(void __iomem *)dst_iomem + (i * 4));
265 }
266 
267 /**
268  * _base_clone_to_sys_mem - Writes/copies data to system/BAR0 region
269  *
270  * @dst_iomem: Pointer to the destination location in BAR0 space.
271  * @src: Pointer to the Source data.
272  * @size: Size of data to be copied.
273  */
274 static void
275 _base_clone_to_sys_mem(void __iomem *dst_iomem, void *src, u32 size)
276 {
277 	int i;
278 	u32 *src_virt_mem = (u32 *)(src);
279 
280 	for (i = 0; i < size/4; i++)
281 		writel((u32)src_virt_mem[i],
282 			(void __iomem *)dst_iomem + (i * 4));
283 }
284 
285 /**
286  * _base_get_chain - Calculates and Returns virtual chain address
287  *			 for the provided smid in BAR0 space.
288  *
289  * @ioc: per adapter object
290  * @smid: system request message index
291  * @sge_chain_count: Scatter gather chain count.
292  *
293  * Return: the chain address.
294  */
295 static inline void __iomem*
296 _base_get_chain(struct MPT3SAS_ADAPTER *ioc, u16 smid,
297 		u8 sge_chain_count)
298 {
299 	void __iomem *base_chain, *chain_virt;
300 	u16 cmd_credit = ioc->facts.RequestCredit + 1;
301 
302 	base_chain  = (void __iomem *)ioc->chip + MPI_FRAME_START_OFFSET +
303 		(cmd_credit * ioc->request_sz) +
304 		REPLY_FREE_POOL_SIZE;
305 	chain_virt = base_chain + (smid * ioc->facts.MaxChainDepth *
306 			ioc->request_sz) + (sge_chain_count * ioc->request_sz);
307 	return chain_virt;
308 }
309 
310 /**
311  * _base_get_chain_phys - Calculates and Returns physical address
312  *			in BAR0 for scatter gather chains, for
313  *			the provided smid.
314  *
315  * @ioc: per adapter object
316  * @smid: system request message index
317  * @sge_chain_count: Scatter gather chain count.
318  *
319  * Return: Physical chain address.
320  */
321 static inline phys_addr_t
322 _base_get_chain_phys(struct MPT3SAS_ADAPTER *ioc, u16 smid,
323 		u8 sge_chain_count)
324 {
325 	phys_addr_t base_chain_phys, chain_phys;
326 	u16 cmd_credit = ioc->facts.RequestCredit + 1;
327 
328 	base_chain_phys  = ioc->chip_phys + MPI_FRAME_START_OFFSET +
329 		(cmd_credit * ioc->request_sz) +
330 		REPLY_FREE_POOL_SIZE;
331 	chain_phys = base_chain_phys + (smid * ioc->facts.MaxChainDepth *
332 			ioc->request_sz) + (sge_chain_count * ioc->request_sz);
333 	return chain_phys;
334 }
335 
336 /**
337  * _base_get_buffer_bar0 - Calculates and Returns BAR0 mapped Host
338  *			buffer address for the provided smid.
339  *			(Each smid can have 64K starts from 17024)
340  *
341  * @ioc: per adapter object
342  * @smid: system request message index
343  *
344  * Return: Pointer to buffer location in BAR0.
345  */
346 
347 static void __iomem *
348 _base_get_buffer_bar0(struct MPT3SAS_ADAPTER *ioc, u16 smid)
349 {
350 	u16 cmd_credit = ioc->facts.RequestCredit + 1;
351 	// Added extra 1 to reach end of chain.
352 	void __iomem *chain_end = _base_get_chain(ioc,
353 			cmd_credit + 1,
354 			ioc->facts.MaxChainDepth);
355 	return chain_end + (smid * 64 * 1024);
356 }
357 
358 /**
359  * _base_get_buffer_phys_bar0 - Calculates and Returns BAR0 mapped
360  *		Host buffer Physical address for the provided smid.
361  *		(Each smid can have 64K starts from 17024)
362  *
363  * @ioc: per adapter object
364  * @smid: system request message index
365  *
366  * Return: Pointer to buffer location in BAR0.
367  */
368 static phys_addr_t
369 _base_get_buffer_phys_bar0(struct MPT3SAS_ADAPTER *ioc, u16 smid)
370 {
371 	u16 cmd_credit = ioc->facts.RequestCredit + 1;
372 	phys_addr_t chain_end_phys = _base_get_chain_phys(ioc,
373 			cmd_credit + 1,
374 			ioc->facts.MaxChainDepth);
375 	return chain_end_phys + (smid * 64 * 1024);
376 }
377 
378 /**
379  * _base_get_chain_buffer_dma_to_chain_buffer - Iterates chain
380  *			lookup list and Provides chain_buffer
381  *			address for the matching dma address.
382  *			(Each smid can have 64K starts from 17024)
383  *
384  * @ioc: per adapter object
385  * @chain_buffer_dma: Chain buffer dma address.
386  *
387  * Return: Pointer to chain buffer. Or Null on Failure.
388  */
389 static void *
390 _base_get_chain_buffer_dma_to_chain_buffer(struct MPT3SAS_ADAPTER *ioc,
391 		dma_addr_t chain_buffer_dma)
392 {
393 	u16 index, j;
394 	struct chain_tracker *ct;
395 
396 	for (index = 0; index < ioc->scsiio_depth; index++) {
397 		for (j = 0; j < ioc->chains_needed_per_io; j++) {
398 			ct = &ioc->chain_lookup[index].chains_per_smid[j];
399 			if (ct && ct->chain_buffer_dma == chain_buffer_dma)
400 				return ct->chain_buffer;
401 		}
402 	}
403 	ioc_info(ioc, "Provided chain_buffer_dma address is not in the lookup list\n");
404 	return NULL;
405 }
406 
407 /**
408  * _clone_sg_entries -	MPI EP's scsiio and config requests
409  *			are handled here. Base function for
410  *			double buffering, before submitting
411  *			the requests.
412  *
413  * @ioc: per adapter object.
414  * @mpi_request: mf request pointer.
415  * @smid: system request message index.
416  */
417 static void _clone_sg_entries(struct MPT3SAS_ADAPTER *ioc,
418 		void *mpi_request, u16 smid)
419 {
420 	Mpi2SGESimple32_t *sgel, *sgel_next;
421 	u32  sgl_flags, sge_chain_count = 0;
422 	bool is_write = false;
423 	u16 i = 0;
424 	void __iomem *buffer_iomem;
425 	phys_addr_t buffer_iomem_phys;
426 	void __iomem *buff_ptr;
427 	phys_addr_t buff_ptr_phys;
428 	void __iomem *dst_chain_addr[MCPU_MAX_CHAINS_PER_IO];
429 	void *src_chain_addr[MCPU_MAX_CHAINS_PER_IO];
430 	phys_addr_t dst_addr_phys;
431 	MPI2RequestHeader_t *request_hdr;
432 	struct scsi_cmnd *scmd;
433 	struct scatterlist *sg_scmd = NULL;
434 	int is_scsiio_req = 0;
435 
436 	request_hdr = (MPI2RequestHeader_t *) mpi_request;
437 
438 	if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST) {
439 		Mpi25SCSIIORequest_t *scsiio_request =
440 			(Mpi25SCSIIORequest_t *)mpi_request;
441 		sgel = (Mpi2SGESimple32_t *) &scsiio_request->SGL;
442 		is_scsiio_req = 1;
443 	} else if (request_hdr->Function == MPI2_FUNCTION_CONFIG) {
444 		Mpi2ConfigRequest_t  *config_req =
445 			(Mpi2ConfigRequest_t *)mpi_request;
446 		sgel = (Mpi2SGESimple32_t *) &config_req->PageBufferSGE;
447 	} else
448 		return;
449 
450 	/* From smid we can get scsi_cmd, once we have sg_scmd,
451 	 * we just need to get sg_virt and sg_next to get virtual
452 	 * address associated with sgel->Address.
453 	 */
454 
455 	if (is_scsiio_req) {
456 		/* Get scsi_cmd using smid */
457 		scmd = mpt3sas_scsih_scsi_lookup_get(ioc, smid);
458 		if (scmd == NULL) {
459 			ioc_err(ioc, "scmd is NULL\n");
460 			return;
461 		}
462 
463 		/* Get sg_scmd from scmd provided */
464 		sg_scmd = scsi_sglist(scmd);
465 	}
466 
467 	/*
468 	 * 0 - 255	System register
469 	 * 256 - 4352	MPI Frame. (This is based on maxCredit 32)
470 	 * 4352 - 4864	Reply_free pool (512 byte is reserved
471 	 *		considering maxCredit 32. Reply need extra
472 	 *		room, for mCPU case kept four times of
473 	 *		maxCredit).
474 	 * 4864 - 17152	SGE chain element. (32cmd * 3 chain of
475 	 *		128 byte size = 12288)
476 	 * 17152 - x	Host buffer mapped with smid.
477 	 *		(Each smid can have 64K Max IO.)
478 	 * BAR0+Last 1K MSIX Addr and Data
479 	 * Total size in use 2113664 bytes of 4MB BAR0
480 	 */
481 
482 	buffer_iomem = _base_get_buffer_bar0(ioc, smid);
483 	buffer_iomem_phys = _base_get_buffer_phys_bar0(ioc, smid);
484 
485 	buff_ptr = buffer_iomem;
486 	buff_ptr_phys = buffer_iomem_phys;
487 	WARN_ON(buff_ptr_phys > U32_MAX);
488 
489 	if (le32_to_cpu(sgel->FlagsLength) &
490 			(MPI2_SGE_FLAGS_HOST_TO_IOC << MPI2_SGE_FLAGS_SHIFT))
491 		is_write = true;
492 
493 	for (i = 0; i < MPT_MIN_PHYS_SEGMENTS + ioc->facts.MaxChainDepth; i++) {
494 
495 		sgl_flags =
496 		    (le32_to_cpu(sgel->FlagsLength) >> MPI2_SGE_FLAGS_SHIFT);
497 
498 		switch (sgl_flags & MPI2_SGE_FLAGS_ELEMENT_MASK) {
499 		case MPI2_SGE_FLAGS_CHAIN_ELEMENT:
500 			/*
501 			 * Helper function which on passing
502 			 * chain_buffer_dma returns chain_buffer. Get
503 			 * the virtual address for sgel->Address
504 			 */
505 			sgel_next =
506 				_base_get_chain_buffer_dma_to_chain_buffer(ioc,
507 						le32_to_cpu(sgel->Address));
508 			if (sgel_next == NULL)
509 				return;
510 			/*
511 			 * This is coping 128 byte chain
512 			 * frame (not a host buffer)
513 			 */
514 			dst_chain_addr[sge_chain_count] =
515 				_base_get_chain(ioc,
516 					smid, sge_chain_count);
517 			src_chain_addr[sge_chain_count] =
518 						(void *) sgel_next;
519 			dst_addr_phys = _base_get_chain_phys(ioc,
520 						smid, sge_chain_count);
521 			WARN_ON(dst_addr_phys > U32_MAX);
522 			sgel->Address =
523 				cpu_to_le32(lower_32_bits(dst_addr_phys));
524 			sgel = sgel_next;
525 			sge_chain_count++;
526 			break;
527 		case MPI2_SGE_FLAGS_SIMPLE_ELEMENT:
528 			if (is_write) {
529 				if (is_scsiio_req) {
530 					_base_clone_to_sys_mem(buff_ptr,
531 					    sg_virt(sg_scmd),
532 					    (le32_to_cpu(sgel->FlagsLength) &
533 					    0x00ffffff));
534 					/*
535 					 * FIXME: this relies on a a zero
536 					 * PCI mem_offset.
537 					 */
538 					sgel->Address =
539 					    cpu_to_le32((u32)buff_ptr_phys);
540 				} else {
541 					_base_clone_to_sys_mem(buff_ptr,
542 					    ioc->config_vaddr,
543 					    (le32_to_cpu(sgel->FlagsLength) &
544 					    0x00ffffff));
545 					sgel->Address =
546 					    cpu_to_le32((u32)buff_ptr_phys);
547 				}
548 			}
549 			buff_ptr += (le32_to_cpu(sgel->FlagsLength) &
550 			    0x00ffffff);
551 			buff_ptr_phys += (le32_to_cpu(sgel->FlagsLength) &
552 			    0x00ffffff);
553 			if ((le32_to_cpu(sgel->FlagsLength) &
554 			    (MPI2_SGE_FLAGS_END_OF_BUFFER
555 					<< MPI2_SGE_FLAGS_SHIFT)))
556 				goto eob_clone_chain;
557 			else {
558 				/*
559 				 * Every single element in MPT will have
560 				 * associated sg_next. Better to sanity that
561 				 * sg_next is not NULL, but it will be a bug
562 				 * if it is null.
563 				 */
564 				if (is_scsiio_req) {
565 					sg_scmd = sg_next(sg_scmd);
566 					if (sg_scmd)
567 						sgel++;
568 					else
569 						goto eob_clone_chain;
570 				}
571 			}
572 			break;
573 		}
574 	}
575 
576 eob_clone_chain:
577 	for (i = 0; i < sge_chain_count; i++) {
578 		if (is_scsiio_req)
579 			_base_clone_to_sys_mem(dst_chain_addr[i],
580 				src_chain_addr[i], ioc->request_sz);
581 	}
582 }
583 
584 /**
585  *  mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc
586  * @arg: input argument, used to derive ioc
587  *
588  * Return:
589  * 0 if controller is removed from pci subsystem.
590  * -1 for other case.
591  */
592 static int mpt3sas_remove_dead_ioc_func(void *arg)
593 {
594 	struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg;
595 	struct pci_dev *pdev;
596 
597 	if (!ioc)
598 		return -1;
599 
600 	pdev = ioc->pdev;
601 	if (!pdev)
602 		return -1;
603 	pci_stop_and_remove_bus_device_locked(pdev);
604 	return 0;
605 }
606 
607 /**
608  * _base_sync_drv_fw_timestamp - Sync Drive-Fw TimeStamp.
609  * @ioc: Per Adapter Object
610  *
611  * Return: nothing.
612  */
613 static void _base_sync_drv_fw_timestamp(struct MPT3SAS_ADAPTER *ioc)
614 {
615 	Mpi26IoUnitControlRequest_t *mpi_request;
616 	Mpi26IoUnitControlReply_t *mpi_reply;
617 	u16 smid;
618 	ktime_t current_time;
619 	u64 TimeStamp = 0;
620 	u8 issue_reset = 0;
621 
622 	mutex_lock(&ioc->scsih_cmds.mutex);
623 	if (ioc->scsih_cmds.status != MPT3_CMD_NOT_USED) {
624 		ioc_err(ioc, "scsih_cmd in use %s\n", __func__);
625 		goto out;
626 	}
627 	ioc->scsih_cmds.status = MPT3_CMD_PENDING;
628 	smid = mpt3sas_base_get_smid(ioc, ioc->scsih_cb_idx);
629 	if (!smid) {
630 		ioc_err(ioc, "Failed obtaining a smid %s\n", __func__);
631 		ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
632 		goto out;
633 	}
634 	mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
635 	ioc->scsih_cmds.smid = smid;
636 	memset(mpi_request, 0, sizeof(Mpi26IoUnitControlRequest_t));
637 	mpi_request->Function = MPI2_FUNCTION_IO_UNIT_CONTROL;
638 	mpi_request->Operation = MPI26_CTRL_OP_SET_IOC_PARAMETER;
639 	mpi_request->IOCParameter = MPI26_SET_IOC_PARAMETER_SYNC_TIMESTAMP;
640 	current_time = ktime_get_real();
641 	TimeStamp = ktime_to_ms(current_time);
642 	mpi_request->Reserved7 = cpu_to_le32(TimeStamp >> 32);
643 	mpi_request->IOCParameterValue = cpu_to_le32(TimeStamp & 0xFFFFFFFF);
644 	init_completion(&ioc->scsih_cmds.done);
645 	ioc->put_smid_default(ioc, smid);
646 	dinitprintk(ioc, ioc_info(ioc,
647 	    "Io Unit Control Sync TimeStamp (sending), @time %lld ms\n",
648 	    TimeStamp));
649 	wait_for_completion_timeout(&ioc->scsih_cmds.done,
650 		MPT3SAS_TIMESYNC_TIMEOUT_SECONDS*HZ);
651 	if (!(ioc->scsih_cmds.status & MPT3_CMD_COMPLETE)) {
652 		mpt3sas_check_cmd_timeout(ioc,
653 		    ioc->scsih_cmds.status, mpi_request,
654 		    sizeof(Mpi2SasIoUnitControlRequest_t)/4, issue_reset);
655 		goto issue_host_reset;
656 	}
657 	if (ioc->scsih_cmds.status & MPT3_CMD_REPLY_VALID) {
658 		mpi_reply = ioc->scsih_cmds.reply;
659 		dinitprintk(ioc, ioc_info(ioc,
660 		    "Io Unit Control sync timestamp (complete): ioc_status(0x%04x), loginfo(0x%08x)\n",
661 		    le16_to_cpu(mpi_reply->IOCStatus),
662 		    le32_to_cpu(mpi_reply->IOCLogInfo)));
663 	}
664 issue_host_reset:
665 	if (issue_reset)
666 		mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
667 	ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
668 out:
669 	mutex_unlock(&ioc->scsih_cmds.mutex);
670 }
671 
672 /**
673  * _base_fault_reset_work - workq handling ioc fault conditions
674  * @work: input argument, used to derive ioc
675  *
676  * Context: sleep.
677  */
678 static void
679 _base_fault_reset_work(struct work_struct *work)
680 {
681 	struct MPT3SAS_ADAPTER *ioc =
682 	    container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work);
683 	unsigned long	 flags;
684 	u32 doorbell;
685 	int rc;
686 	struct task_struct *p;
687 
688 
689 	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
690 	if ((ioc->shost_recovery && (ioc->ioc_coredump_loop == 0)) ||
691 			ioc->pci_error_recovery)
692 		goto rearm_timer;
693 	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
694 
695 	doorbell = mpt3sas_base_get_iocstate(ioc, 0);
696 	if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) {
697 		ioc_err(ioc, "SAS host is non-operational !!!!\n");
698 
699 		/* It may be possible that EEH recovery can resolve some of
700 		 * pci bus failure issues rather removing the dead ioc function
701 		 * by considering controller is in a non-operational state. So
702 		 * here priority is given to the EEH recovery. If it doesn't
703 		 * not resolve this issue, mpt3sas driver will consider this
704 		 * controller to non-operational state and remove the dead ioc
705 		 * function.
706 		 */
707 		if (ioc->non_operational_loop++ < 5) {
708 			spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock,
709 							 flags);
710 			goto rearm_timer;
711 		}
712 
713 		/*
714 		 * Call _scsih_flush_pending_cmds callback so that we flush all
715 		 * pending commands back to OS. This call is required to avoid
716 		 * deadlock at block layer. Dead IOC will fail to do diag reset,
717 		 * and this call is safe since dead ioc will never return any
718 		 * command back from HW.
719 		 */
720 		mpt3sas_base_pause_mq_polling(ioc);
721 		ioc->schedule_dead_ioc_flush_running_cmds(ioc);
722 		/*
723 		 * Set remove_host flag early since kernel thread will
724 		 * take some time to execute.
725 		 */
726 		ioc->remove_host = 1;
727 		/*Remove the Dead Host */
728 		p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc,
729 		    "%s_dead_ioc_%d", ioc->driver_name, ioc->id);
730 		if (IS_ERR(p))
731 			ioc_err(ioc, "%s: Running mpt3sas_dead_ioc thread failed !!!!\n",
732 				__func__);
733 		else
734 			ioc_err(ioc, "%s: Running mpt3sas_dead_ioc thread success !!!!\n",
735 				__func__);
736 		return; /* don't rearm timer */
737 	}
738 
739 	if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_COREDUMP) {
740 		u8 timeout = (ioc->manu_pg11.CoreDumpTOSec) ?
741 		    ioc->manu_pg11.CoreDumpTOSec :
742 		    MPT3SAS_DEFAULT_COREDUMP_TIMEOUT_SECONDS;
743 
744 		timeout /= (FAULT_POLLING_INTERVAL/1000);
745 
746 		if (ioc->ioc_coredump_loop == 0) {
747 			mpt3sas_print_coredump_info(ioc,
748 			    doorbell & MPI2_DOORBELL_DATA_MASK);
749 			/* do not accept any IOs and disable the interrupts */
750 			spin_lock_irqsave(
751 			    &ioc->ioc_reset_in_progress_lock, flags);
752 			ioc->shost_recovery = 1;
753 			spin_unlock_irqrestore(
754 			    &ioc->ioc_reset_in_progress_lock, flags);
755 			mpt3sas_base_mask_interrupts(ioc);
756 			mpt3sas_base_pause_mq_polling(ioc);
757 			_base_clear_outstanding_commands(ioc);
758 		}
759 
760 		ioc_info(ioc, "%s: CoreDump loop %d.",
761 		    __func__, ioc->ioc_coredump_loop);
762 
763 		/* Wait until CoreDump completes or times out */
764 		if (ioc->ioc_coredump_loop++ < timeout) {
765 			spin_lock_irqsave(
766 			    &ioc->ioc_reset_in_progress_lock, flags);
767 			goto rearm_timer;
768 		}
769 	}
770 
771 	if (ioc->ioc_coredump_loop) {
772 		if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_COREDUMP)
773 			ioc_err(ioc, "%s: CoreDump completed. LoopCount: %d",
774 			    __func__, ioc->ioc_coredump_loop);
775 		else
776 			ioc_err(ioc, "%s: CoreDump Timed out. LoopCount: %d",
777 			    __func__, ioc->ioc_coredump_loop);
778 		ioc->ioc_coredump_loop = MPT3SAS_COREDUMP_LOOP_DONE;
779 	}
780 	ioc->non_operational_loop = 0;
781 	if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) {
782 		rc = mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
783 		ioc_warn(ioc, "%s: hard reset: %s\n",
784 			 __func__, rc == 0 ? "success" : "failed");
785 		doorbell = mpt3sas_base_get_iocstate(ioc, 0);
786 		if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
787 			mpt3sas_print_fault_code(ioc, doorbell &
788 			    MPI2_DOORBELL_DATA_MASK);
789 		} else if ((doorbell & MPI2_IOC_STATE_MASK) ==
790 		    MPI2_IOC_STATE_COREDUMP)
791 			mpt3sas_print_coredump_info(ioc, doorbell &
792 			    MPI2_DOORBELL_DATA_MASK);
793 		if (rc && (doorbell & MPI2_IOC_STATE_MASK) !=
794 		    MPI2_IOC_STATE_OPERATIONAL)
795 			return; /* don't rearm timer */
796 	}
797 	ioc->ioc_coredump_loop = 0;
798 	if (ioc->time_sync_interval &&
799 	    ++ioc->timestamp_update_count >= ioc->time_sync_interval) {
800 		ioc->timestamp_update_count = 0;
801 		_base_sync_drv_fw_timestamp(ioc);
802 	}
803 	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
804  rearm_timer:
805 	if (ioc->fault_reset_work_q)
806 		queue_delayed_work(ioc->fault_reset_work_q,
807 		    &ioc->fault_reset_work,
808 		    msecs_to_jiffies(FAULT_POLLING_INTERVAL));
809 	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
810 }
811 
812 /**
813  * mpt3sas_base_start_watchdog - start the fault_reset_work_q
814  * @ioc: per adapter object
815  *
816  * Context: sleep.
817  */
818 void
819 mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc)
820 {
821 	unsigned long	 flags;
822 
823 	if (ioc->fault_reset_work_q)
824 		return;
825 
826 	ioc->timestamp_update_count = 0;
827 	/* initialize fault polling */
828 
829 	INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
830 	snprintf(ioc->fault_reset_work_q_name,
831 	    sizeof(ioc->fault_reset_work_q_name), "poll_%s%d_status",
832 	    ioc->driver_name, ioc->id);
833 	ioc->fault_reset_work_q =
834 		create_singlethread_workqueue(ioc->fault_reset_work_q_name);
835 	if (!ioc->fault_reset_work_q) {
836 		ioc_err(ioc, "%s: failed (line=%d)\n", __func__, __LINE__);
837 		return;
838 	}
839 	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
840 	if (ioc->fault_reset_work_q)
841 		queue_delayed_work(ioc->fault_reset_work_q,
842 		    &ioc->fault_reset_work,
843 		    msecs_to_jiffies(FAULT_POLLING_INTERVAL));
844 	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
845 }
846 
847 /**
848  * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q
849  * @ioc: per adapter object
850  *
851  * Context: sleep.
852  */
853 void
854 mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc)
855 {
856 	unsigned long flags;
857 	struct workqueue_struct *wq;
858 
859 	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
860 	wq = ioc->fault_reset_work_q;
861 	ioc->fault_reset_work_q = NULL;
862 	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
863 	if (wq) {
864 		if (!cancel_delayed_work_sync(&ioc->fault_reset_work))
865 			flush_workqueue(wq);
866 		destroy_workqueue(wq);
867 	}
868 }
869 
870 /**
871  * mpt3sas_base_fault_info - verbose translation of firmware FAULT code
872  * @ioc: per adapter object
873  * @fault_code: fault code
874  */
875 void
876 mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code)
877 {
878 	ioc_err(ioc, "fault_state(0x%04x)!\n", fault_code);
879 }
880 
881 /**
882  * mpt3sas_base_coredump_info - verbose translation of firmware CoreDump state
883  * @ioc: per adapter object
884  * @fault_code: fault code
885  *
886  * Return: nothing.
887  */
888 void
889 mpt3sas_base_coredump_info(struct MPT3SAS_ADAPTER *ioc, u16 fault_code)
890 {
891 	ioc_err(ioc, "coredump_state(0x%04x)!\n", fault_code);
892 }
893 
894 /**
895  * mpt3sas_base_wait_for_coredump_completion - Wait until coredump
896  * completes or times out
897  * @ioc: per adapter object
898  * @caller: caller function name
899  *
900  * Return: 0 for success, non-zero for failure.
901  */
902 int
903 mpt3sas_base_wait_for_coredump_completion(struct MPT3SAS_ADAPTER *ioc,
904 		const char *caller)
905 {
906 	u8 timeout = (ioc->manu_pg11.CoreDumpTOSec) ?
907 			ioc->manu_pg11.CoreDumpTOSec :
908 			MPT3SAS_DEFAULT_COREDUMP_TIMEOUT_SECONDS;
909 
910 	int ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_FAULT,
911 					timeout);
912 
913 	if (ioc_state)
914 		ioc_err(ioc,
915 		    "%s: CoreDump timed out. (ioc_state=0x%x)\n",
916 		    caller, ioc_state);
917 	else
918 		ioc_info(ioc,
919 		    "%s: CoreDump completed. (ioc_state=0x%x)\n",
920 		    caller, ioc_state);
921 
922 	return ioc_state;
923 }
924 
925 /**
926  * mpt3sas_halt_firmware - halt's mpt controller firmware
927  * @ioc: per adapter object
928  *
929  * For debugging timeout related issues.  Writing 0xCOFFEE00
930  * to the doorbell register will halt controller firmware. With
931  * the purpose to stop both driver and firmware, the enduser can
932  * obtain a ring buffer from controller UART.
933  */
934 void
935 mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc)
936 {
937 	u32 doorbell;
938 
939 	if (!ioc->fwfault_debug)
940 		return;
941 
942 	dump_stack();
943 
944 	doorbell = ioc->base_readl(&ioc->chip->Doorbell);
945 	if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
946 		mpt3sas_print_fault_code(ioc, doorbell &
947 		    MPI2_DOORBELL_DATA_MASK);
948 	} else if ((doorbell & MPI2_IOC_STATE_MASK) ==
949 	    MPI2_IOC_STATE_COREDUMP) {
950 		mpt3sas_print_coredump_info(ioc, doorbell &
951 		    MPI2_DOORBELL_DATA_MASK);
952 	} else {
953 		writel(0xC0FFEE00, &ioc->chip->Doorbell);
954 		ioc_err(ioc, "Firmware is halted due to command timeout\n");
955 	}
956 
957 	if (ioc->fwfault_debug == 2)
958 		for (;;)
959 			;
960 	else
961 		panic("panic in %s\n", __func__);
962 }
963 
964 /**
965  * _base_sas_ioc_info - verbose translation of the ioc status
966  * @ioc: per adapter object
967  * @mpi_reply: reply mf payload returned from firmware
968  * @request_hdr: request mf
969  */
970 static void
971 _base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
972 	MPI2RequestHeader_t *request_hdr)
973 {
974 	u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
975 	    MPI2_IOCSTATUS_MASK;
976 	char *desc = NULL;
977 	u16 frame_sz;
978 	char *func_str = NULL;
979 
980 	/* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */
981 	if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
982 	    request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
983 	    request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
984 		return;
985 
986 	if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE)
987 		return;
988 	/*
989 	 * Older Firmware version doesn't support driver trigger pages.
990 	 * So, skip displaying 'config invalid type' type
991 	 * of error message.
992 	 */
993 	if (request_hdr->Function == MPI2_FUNCTION_CONFIG) {
994 		Mpi2ConfigRequest_t *rqst = (Mpi2ConfigRequest_t *)request_hdr;
995 
996 		if ((rqst->ExtPageType ==
997 		    MPI2_CONFIG_EXTPAGETYPE_DRIVER_PERSISTENT_TRIGGER) &&
998 		    !(ioc->logging_level & MPT_DEBUG_CONFIG)) {
999 			return;
1000 		}
1001 	}
1002 
1003 	switch (ioc_status) {
1004 
1005 /****************************************************************************
1006 *  Common IOCStatus values for all replies
1007 ****************************************************************************/
1008 
1009 	case MPI2_IOCSTATUS_INVALID_FUNCTION:
1010 		desc = "invalid function";
1011 		break;
1012 	case MPI2_IOCSTATUS_BUSY:
1013 		desc = "busy";
1014 		break;
1015 	case MPI2_IOCSTATUS_INVALID_SGL:
1016 		desc = "invalid sgl";
1017 		break;
1018 	case MPI2_IOCSTATUS_INTERNAL_ERROR:
1019 		desc = "internal error";
1020 		break;
1021 	case MPI2_IOCSTATUS_INVALID_VPID:
1022 		desc = "invalid vpid";
1023 		break;
1024 	case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
1025 		desc = "insufficient resources";
1026 		break;
1027 	case MPI2_IOCSTATUS_INSUFFICIENT_POWER:
1028 		desc = "insufficient power";
1029 		break;
1030 	case MPI2_IOCSTATUS_INVALID_FIELD:
1031 		desc = "invalid field";
1032 		break;
1033 	case MPI2_IOCSTATUS_INVALID_STATE:
1034 		desc = "invalid state";
1035 		break;
1036 	case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
1037 		desc = "op state not supported";
1038 		break;
1039 
1040 /****************************************************************************
1041 *  Config IOCStatus values
1042 ****************************************************************************/
1043 
1044 	case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
1045 		desc = "config invalid action";
1046 		break;
1047 	case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
1048 		desc = "config invalid type";
1049 		break;
1050 	case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
1051 		desc = "config invalid page";
1052 		break;
1053 	case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
1054 		desc = "config invalid data";
1055 		break;
1056 	case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
1057 		desc = "config no defaults";
1058 		break;
1059 	case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
1060 		desc = "config cant commit";
1061 		break;
1062 
1063 /****************************************************************************
1064 *  SCSI IO Reply
1065 ****************************************************************************/
1066 
1067 	case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
1068 	case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
1069 	case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
1070 	case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
1071 	case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
1072 	case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
1073 	case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
1074 	case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
1075 	case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
1076 	case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
1077 	case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
1078 	case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
1079 		break;
1080 
1081 /****************************************************************************
1082 *  For use by SCSI Initiator and SCSI Target end-to-end data protection
1083 ****************************************************************************/
1084 
1085 	case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
1086 		desc = "eedp guard error";
1087 		break;
1088 	case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
1089 		desc = "eedp ref tag error";
1090 		break;
1091 	case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
1092 		desc = "eedp app tag error";
1093 		break;
1094 
1095 /****************************************************************************
1096 *  SCSI Target values
1097 ****************************************************************************/
1098 
1099 	case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
1100 		desc = "target invalid io index";
1101 		break;
1102 	case MPI2_IOCSTATUS_TARGET_ABORTED:
1103 		desc = "target aborted";
1104 		break;
1105 	case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
1106 		desc = "target no conn retryable";
1107 		break;
1108 	case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
1109 		desc = "target no connection";
1110 		break;
1111 	case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
1112 		desc = "target xfer count mismatch";
1113 		break;
1114 	case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
1115 		desc = "target data offset error";
1116 		break;
1117 	case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
1118 		desc = "target too much write data";
1119 		break;
1120 	case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
1121 		desc = "target iu too short";
1122 		break;
1123 	case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
1124 		desc = "target ack nak timeout";
1125 		break;
1126 	case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
1127 		desc = "target nak received";
1128 		break;
1129 
1130 /****************************************************************************
1131 *  Serial Attached SCSI values
1132 ****************************************************************************/
1133 
1134 	case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
1135 		desc = "smp request failed";
1136 		break;
1137 	case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
1138 		desc = "smp data overrun";
1139 		break;
1140 
1141 /****************************************************************************
1142 *  Diagnostic Buffer Post / Diagnostic Release values
1143 ****************************************************************************/
1144 
1145 	case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
1146 		desc = "diagnostic released";
1147 		break;
1148 	default:
1149 		break;
1150 	}
1151 
1152 	if (!desc)
1153 		return;
1154 
1155 	switch (request_hdr->Function) {
1156 	case MPI2_FUNCTION_CONFIG:
1157 		frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
1158 		func_str = "config_page";
1159 		break;
1160 	case MPI2_FUNCTION_SCSI_TASK_MGMT:
1161 		frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
1162 		func_str = "task_mgmt";
1163 		break;
1164 	case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
1165 		frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
1166 		func_str = "sas_iounit_ctl";
1167 		break;
1168 	case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
1169 		frame_sz = sizeof(Mpi2SepRequest_t);
1170 		func_str = "enclosure";
1171 		break;
1172 	case MPI2_FUNCTION_IOC_INIT:
1173 		frame_sz = sizeof(Mpi2IOCInitRequest_t);
1174 		func_str = "ioc_init";
1175 		break;
1176 	case MPI2_FUNCTION_PORT_ENABLE:
1177 		frame_sz = sizeof(Mpi2PortEnableRequest_t);
1178 		func_str = "port_enable";
1179 		break;
1180 	case MPI2_FUNCTION_SMP_PASSTHROUGH:
1181 		frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
1182 		func_str = "smp_passthru";
1183 		break;
1184 	case MPI2_FUNCTION_NVME_ENCAPSULATED:
1185 		frame_sz = sizeof(Mpi26NVMeEncapsulatedRequest_t) +
1186 		    ioc->sge_size;
1187 		func_str = "nvme_encapsulated";
1188 		break;
1189 	default:
1190 		frame_sz = 32;
1191 		func_str = "unknown";
1192 		break;
1193 	}
1194 
1195 	ioc_warn(ioc, "ioc_status: %s(0x%04x), request(0x%p),(%s)\n",
1196 		 desc, ioc_status, request_hdr, func_str);
1197 
1198 	_debug_dump_mf(request_hdr, frame_sz/4);
1199 }
1200 
1201 /**
1202  * _base_display_event_data - verbose translation of firmware asyn events
1203  * @ioc: per adapter object
1204  * @mpi_reply: reply mf payload returned from firmware
1205  */
1206 static void
1207 _base_display_event_data(struct MPT3SAS_ADAPTER *ioc,
1208 	Mpi2EventNotificationReply_t *mpi_reply)
1209 {
1210 	char *desc = NULL;
1211 	u16 event;
1212 
1213 	if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
1214 		return;
1215 
1216 	event = le16_to_cpu(mpi_reply->Event);
1217 
1218 	switch (event) {
1219 	case MPI2_EVENT_LOG_DATA:
1220 		desc = "Log Data";
1221 		break;
1222 	case MPI2_EVENT_STATE_CHANGE:
1223 		desc = "Status Change";
1224 		break;
1225 	case MPI2_EVENT_HARD_RESET_RECEIVED:
1226 		desc = "Hard Reset Received";
1227 		break;
1228 	case MPI2_EVENT_EVENT_CHANGE:
1229 		desc = "Event Change";
1230 		break;
1231 	case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
1232 		desc = "Device Status Change";
1233 		break;
1234 	case MPI2_EVENT_IR_OPERATION_STATUS:
1235 		if (!ioc->hide_ir_msg)
1236 			desc = "IR Operation Status";
1237 		break;
1238 	case MPI2_EVENT_SAS_DISCOVERY:
1239 	{
1240 		Mpi2EventDataSasDiscovery_t *event_data =
1241 		    (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
1242 		ioc_info(ioc, "Discovery: (%s)",
1243 			 event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED ?
1244 			 "start" : "stop");
1245 		if (event_data->DiscoveryStatus)
1246 			pr_cont(" discovery_status(0x%08x)",
1247 			    le32_to_cpu(event_data->DiscoveryStatus));
1248 		pr_cont("\n");
1249 		return;
1250 	}
1251 	case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
1252 		desc = "SAS Broadcast Primitive";
1253 		break;
1254 	case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
1255 		desc = "SAS Init Device Status Change";
1256 		break;
1257 	case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
1258 		desc = "SAS Init Table Overflow";
1259 		break;
1260 	case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
1261 		desc = "SAS Topology Change List";
1262 		break;
1263 	case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
1264 		desc = "SAS Enclosure Device Status Change";
1265 		break;
1266 	case MPI2_EVENT_IR_VOLUME:
1267 		if (!ioc->hide_ir_msg)
1268 			desc = "IR Volume";
1269 		break;
1270 	case MPI2_EVENT_IR_PHYSICAL_DISK:
1271 		if (!ioc->hide_ir_msg)
1272 			desc = "IR Physical Disk";
1273 		break;
1274 	case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
1275 		if (!ioc->hide_ir_msg)
1276 			desc = "IR Configuration Change List";
1277 		break;
1278 	case MPI2_EVENT_LOG_ENTRY_ADDED:
1279 		if (!ioc->hide_ir_msg)
1280 			desc = "Log Entry Added";
1281 		break;
1282 	case MPI2_EVENT_TEMP_THRESHOLD:
1283 		desc = "Temperature Threshold";
1284 		break;
1285 	case MPI2_EVENT_ACTIVE_CABLE_EXCEPTION:
1286 		desc = "Cable Event";
1287 		break;
1288 	case MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR:
1289 		desc = "SAS Device Discovery Error";
1290 		break;
1291 	case MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE:
1292 		desc = "PCIE Device Status Change";
1293 		break;
1294 	case MPI2_EVENT_PCIE_ENUMERATION:
1295 	{
1296 		Mpi26EventDataPCIeEnumeration_t *event_data =
1297 			(Mpi26EventDataPCIeEnumeration_t *)mpi_reply->EventData;
1298 		ioc_info(ioc, "PCIE Enumeration: (%s)",
1299 			 event_data->ReasonCode == MPI26_EVENT_PCIE_ENUM_RC_STARTED ?
1300 			 "start" : "stop");
1301 		if (event_data->EnumerationStatus)
1302 			pr_cont("enumeration_status(0x%08x)",
1303 				le32_to_cpu(event_data->EnumerationStatus));
1304 		pr_cont("\n");
1305 		return;
1306 	}
1307 	case MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST:
1308 		desc = "PCIE Topology Change List";
1309 		break;
1310 	}
1311 
1312 	if (!desc)
1313 		return;
1314 
1315 	ioc_info(ioc, "%s\n", desc);
1316 }
1317 
1318 /**
1319  * _base_sas_log_info - verbose translation of firmware log info
1320  * @ioc: per adapter object
1321  * @log_info: log info
1322  */
1323 static void
1324 _base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info)
1325 {
1326 	union loginfo_type {
1327 		u32	loginfo;
1328 		struct {
1329 			u32	subcode:16;
1330 			u32	code:8;
1331 			u32	originator:4;
1332 			u32	bus_type:4;
1333 		} dw;
1334 	};
1335 	union loginfo_type sas_loginfo;
1336 	char *originator_str = NULL;
1337 
1338 	sas_loginfo.loginfo = log_info;
1339 	if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
1340 		return;
1341 
1342 	/* each nexus loss loginfo */
1343 	if (log_info == 0x31170000)
1344 		return;
1345 
1346 	/* eat the loginfos associated with task aborts */
1347 	if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info ==
1348 	    0x31140000 || log_info == 0x31130000))
1349 		return;
1350 
1351 	switch (sas_loginfo.dw.originator) {
1352 	case 0:
1353 		originator_str = "IOP";
1354 		break;
1355 	case 1:
1356 		originator_str = "PL";
1357 		break;
1358 	case 2:
1359 		if (!ioc->hide_ir_msg)
1360 			originator_str = "IR";
1361 		else
1362 			originator_str = "WarpDrive";
1363 		break;
1364 	}
1365 
1366 	ioc_warn(ioc, "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n",
1367 		 log_info,
1368 		 originator_str, sas_loginfo.dw.code, sas_loginfo.dw.subcode);
1369 }
1370 
1371 /**
1372  * _base_display_reply_info - handle reply descriptors depending on IOC Status
1373  * @ioc: per adapter object
1374  * @smid: system request message index
1375  * @msix_index: MSIX table index supplied by the OS
1376  * @reply: reply message frame (lower 32bit addr)
1377  */
1378 static void
1379 _base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
1380 	u32 reply)
1381 {
1382 	MPI2DefaultReply_t *mpi_reply;
1383 	u16 ioc_status;
1384 	u32 loginfo = 0;
1385 
1386 	mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
1387 	if (unlikely(!mpi_reply)) {
1388 		ioc_err(ioc, "mpi_reply not valid at %s:%d/%s()!\n",
1389 			__FILE__, __LINE__, __func__);
1390 		return;
1391 	}
1392 	ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
1393 
1394 	if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
1395 	    (ioc->logging_level & MPT_DEBUG_REPLY)) {
1396 		_base_sas_ioc_info(ioc , mpi_reply,
1397 		   mpt3sas_base_get_msg_frame(ioc, smid));
1398 	}
1399 
1400 	if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
1401 		loginfo = le32_to_cpu(mpi_reply->IOCLogInfo);
1402 		_base_sas_log_info(ioc, loginfo);
1403 	}
1404 
1405 	if (ioc_status || loginfo) {
1406 		ioc_status &= MPI2_IOCSTATUS_MASK;
1407 		mpt3sas_trigger_mpi(ioc, ioc_status, loginfo);
1408 	}
1409 }
1410 
1411 /**
1412  * mpt3sas_base_done - base internal command completion routine
1413  * @ioc: per adapter object
1414  * @smid: system request message index
1415  * @msix_index: MSIX table index supplied by the OS
1416  * @reply: reply message frame(lower 32bit addr)
1417  *
1418  * Return:
1419  * 1 meaning mf should be freed from _base_interrupt
1420  * 0 means the mf is freed from this function.
1421  */
1422 u8
1423 mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
1424 	u32 reply)
1425 {
1426 	MPI2DefaultReply_t *mpi_reply;
1427 
1428 	mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
1429 	if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
1430 		return mpt3sas_check_for_pending_internal_cmds(ioc, smid);
1431 
1432 	if (ioc->base_cmds.status == MPT3_CMD_NOT_USED)
1433 		return 1;
1434 
1435 	ioc->base_cmds.status |= MPT3_CMD_COMPLETE;
1436 	if (mpi_reply) {
1437 		ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID;
1438 		memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
1439 	}
1440 	ioc->base_cmds.status &= ~MPT3_CMD_PENDING;
1441 
1442 	complete(&ioc->base_cmds.done);
1443 	return 1;
1444 }
1445 
1446 /**
1447  * _base_async_event - main callback handler for firmware asyn events
1448  * @ioc: per adapter object
1449  * @msix_index: MSIX table index supplied by the OS
1450  * @reply: reply message frame(lower 32bit addr)
1451  *
1452  * Return:
1453  * 1 meaning mf should be freed from _base_interrupt
1454  * 0 means the mf is freed from this function.
1455  */
1456 static u8
1457 _base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
1458 {
1459 	Mpi2EventNotificationReply_t *mpi_reply;
1460 	Mpi2EventAckRequest_t *ack_request;
1461 	u16 smid;
1462 	struct _event_ack_list *delayed_event_ack;
1463 
1464 	mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
1465 	if (!mpi_reply)
1466 		return 1;
1467 	if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
1468 		return 1;
1469 
1470 	_base_display_event_data(ioc, mpi_reply);
1471 
1472 	if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
1473 		goto out;
1474 	smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
1475 	if (!smid) {
1476 		delayed_event_ack = kzalloc(sizeof(*delayed_event_ack),
1477 					GFP_ATOMIC);
1478 		if (!delayed_event_ack)
1479 			goto out;
1480 		INIT_LIST_HEAD(&delayed_event_ack->list);
1481 		delayed_event_ack->Event = mpi_reply->Event;
1482 		delayed_event_ack->EventContext = mpi_reply->EventContext;
1483 		list_add_tail(&delayed_event_ack->list,
1484 				&ioc->delayed_event_ack_list);
1485 		dewtprintk(ioc,
1486 			   ioc_info(ioc, "DELAYED: EVENT ACK: event (0x%04x)\n",
1487 				    le16_to_cpu(mpi_reply->Event)));
1488 		goto out;
1489 	}
1490 
1491 	ack_request = mpt3sas_base_get_msg_frame(ioc, smid);
1492 	memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
1493 	ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
1494 	ack_request->Event = mpi_reply->Event;
1495 	ack_request->EventContext = mpi_reply->EventContext;
1496 	ack_request->VF_ID = 0;  /* TODO */
1497 	ack_request->VP_ID = 0;
1498 	ioc->put_smid_default(ioc, smid);
1499 
1500  out:
1501 
1502 	/* scsih callback handler */
1503 	mpt3sas_scsih_event_callback(ioc, msix_index, reply);
1504 
1505 	/* ctl callback handler */
1506 	mpt3sas_ctl_event_callback(ioc, msix_index, reply);
1507 
1508 	return 1;
1509 }
1510 
1511 static struct scsiio_tracker *
1512 _get_st_from_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1513 {
1514 	struct scsi_cmnd *cmd;
1515 
1516 	if (WARN_ON(!smid) ||
1517 	    WARN_ON(smid >= ioc->hi_priority_smid))
1518 		return NULL;
1519 
1520 	cmd = mpt3sas_scsih_scsi_lookup_get(ioc, smid);
1521 	if (cmd)
1522 		return scsi_cmd_priv(cmd);
1523 
1524 	return NULL;
1525 }
1526 
1527 /**
1528  * _base_get_cb_idx - obtain the callback index
1529  * @ioc: per adapter object
1530  * @smid: system request message index
1531  *
1532  * Return: callback index.
1533  */
1534 static u8
1535 _base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1536 {
1537 	int i;
1538 	u16 ctl_smid = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT + 1;
1539 	u8 cb_idx = 0xFF;
1540 
1541 	if (smid < ioc->hi_priority_smid) {
1542 		struct scsiio_tracker *st;
1543 
1544 		if (smid < ctl_smid) {
1545 			st = _get_st_from_smid(ioc, smid);
1546 			if (st)
1547 				cb_idx = st->cb_idx;
1548 		} else if (smid == ctl_smid)
1549 			cb_idx = ioc->ctl_cb_idx;
1550 	} else if (smid < ioc->internal_smid) {
1551 		i = smid - ioc->hi_priority_smid;
1552 		cb_idx = ioc->hpr_lookup[i].cb_idx;
1553 	} else if (smid <= ioc->hba_queue_depth) {
1554 		i = smid - ioc->internal_smid;
1555 		cb_idx = ioc->internal_lookup[i].cb_idx;
1556 	}
1557 	return cb_idx;
1558 }
1559 
1560 /**
1561  * mpt3sas_base_pause_mq_polling - pause polling on the mq poll queues
1562  *				when driver is flushing out the IOs.
1563  * @ioc: per adapter object
1564  *
1565  * Pause polling on the mq poll (io uring) queues when driver is flushing
1566  * out the IOs. Otherwise we may see the race condition of completing the same
1567  * IO from two paths.
1568  *
1569  * Returns nothing.
1570  */
1571 void
1572 mpt3sas_base_pause_mq_polling(struct MPT3SAS_ADAPTER *ioc)
1573 {
1574 	int iopoll_q_count =
1575 	    ioc->reply_queue_count - ioc->iopoll_q_start_index;
1576 	int qid;
1577 
1578 	for (qid = 0; qid < iopoll_q_count; qid++)
1579 		atomic_set(&ioc->io_uring_poll_queues[qid].pause, 1);
1580 
1581 	/*
1582 	 * wait for current poll to complete.
1583 	 */
1584 	for (qid = 0; qid < iopoll_q_count; qid++) {
1585 		while (atomic_read(&ioc->io_uring_poll_queues[qid].busy)) {
1586 			cpu_relax();
1587 			udelay(500);
1588 		}
1589 	}
1590 }
1591 
1592 /**
1593  * mpt3sas_base_resume_mq_polling - Resume polling on mq poll queues.
1594  * @ioc: per adapter object
1595  *
1596  * Returns nothing.
1597  */
1598 void
1599 mpt3sas_base_resume_mq_polling(struct MPT3SAS_ADAPTER *ioc)
1600 {
1601 	int iopoll_q_count =
1602 	    ioc->reply_queue_count - ioc->iopoll_q_start_index;
1603 	int qid;
1604 
1605 	for (qid = 0; qid < iopoll_q_count; qid++)
1606 		atomic_set(&ioc->io_uring_poll_queues[qid].pause, 0);
1607 }
1608 
1609 /**
1610  * mpt3sas_base_mask_interrupts - disable interrupts
1611  * @ioc: per adapter object
1612  *
1613  * Disabling ResetIRQ, Reply and Doorbell Interrupts
1614  */
1615 void
1616 mpt3sas_base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc)
1617 {
1618 	u32 him_register;
1619 
1620 	ioc->mask_interrupts = 1;
1621 	him_register = ioc->base_readl(&ioc->chip->HostInterruptMask);
1622 	him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
1623 	writel(him_register, &ioc->chip->HostInterruptMask);
1624 	ioc->base_readl(&ioc->chip->HostInterruptMask);
1625 }
1626 
1627 /**
1628  * mpt3sas_base_unmask_interrupts - enable interrupts
1629  * @ioc: per adapter object
1630  *
1631  * Enabling only Reply Interrupts
1632  */
1633 void
1634 mpt3sas_base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc)
1635 {
1636 	u32 him_register;
1637 
1638 	him_register = ioc->base_readl(&ioc->chip->HostInterruptMask);
1639 	him_register &= ~MPI2_HIM_RIM;
1640 	writel(him_register, &ioc->chip->HostInterruptMask);
1641 	ioc->mask_interrupts = 0;
1642 }
1643 
1644 union reply_descriptor {
1645 	u64 word;
1646 	struct {
1647 		u32 low;
1648 		u32 high;
1649 	} u;
1650 };
1651 
1652 static u32 base_mod64(u64 dividend, u32 divisor)
1653 {
1654 	u32 remainder;
1655 
1656 	if (!divisor)
1657 		pr_err("mpt3sas: DIVISOR is zero, in div fn\n");
1658 	remainder = do_div(dividend, divisor);
1659 	return remainder;
1660 }
1661 
1662 /**
1663  * _base_process_reply_queue - Process reply descriptors from reply
1664  *		descriptor post queue.
1665  * @reply_q: per IRQ's reply queue object.
1666  *
1667  * Return: number of reply descriptors processed from reply
1668  *		descriptor queue.
1669  */
1670 static int
1671 _base_process_reply_queue(struct adapter_reply_queue *reply_q)
1672 {
1673 	union reply_descriptor rd;
1674 	u64 completed_cmds;
1675 	u8 request_descript_type;
1676 	u16 smid;
1677 	u8 cb_idx;
1678 	u32 reply;
1679 	u8 msix_index = reply_q->msix_index;
1680 	struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
1681 	Mpi2ReplyDescriptorsUnion_t *rpf;
1682 	u8 rc;
1683 
1684 	completed_cmds = 0;
1685 	if (!atomic_add_unless(&reply_q->busy, 1, 1))
1686 		return completed_cmds;
1687 
1688 	rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index];
1689 	request_descript_type = rpf->Default.ReplyFlags
1690 	     & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1691 	if (request_descript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) {
1692 		atomic_dec(&reply_q->busy);
1693 		return completed_cmds;
1694 	}
1695 
1696 	cb_idx = 0xFF;
1697 	do {
1698 		rd.word = le64_to_cpu(rpf->Words);
1699 		if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
1700 			goto out;
1701 		reply = 0;
1702 		smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
1703 		if (request_descript_type ==
1704 		    MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS ||
1705 		    request_descript_type ==
1706 		    MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS ||
1707 		    request_descript_type ==
1708 		    MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS) {
1709 			cb_idx = _base_get_cb_idx(ioc, smid);
1710 			if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
1711 			    (likely(mpt_callbacks[cb_idx] != NULL))) {
1712 				rc = mpt_callbacks[cb_idx](ioc, smid,
1713 				    msix_index, 0);
1714 				if (rc)
1715 					mpt3sas_base_free_smid(ioc, smid);
1716 			}
1717 		} else if (request_descript_type ==
1718 		    MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
1719 			reply = le32_to_cpu(
1720 			    rpf->AddressReply.ReplyFrameAddress);
1721 			if (reply > ioc->reply_dma_max_address ||
1722 			    reply < ioc->reply_dma_min_address)
1723 				reply = 0;
1724 			if (smid) {
1725 				cb_idx = _base_get_cb_idx(ioc, smid);
1726 				if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
1727 				    (likely(mpt_callbacks[cb_idx] != NULL))) {
1728 					rc = mpt_callbacks[cb_idx](ioc, smid,
1729 					    msix_index, reply);
1730 					if (reply)
1731 						_base_display_reply_info(ioc,
1732 						    smid, msix_index, reply);
1733 					if (rc)
1734 						mpt3sas_base_free_smid(ioc,
1735 						    smid);
1736 				}
1737 			} else {
1738 				_base_async_event(ioc, msix_index, reply);
1739 			}
1740 
1741 			/* reply free queue handling */
1742 			if (reply) {
1743 				ioc->reply_free_host_index =
1744 				    (ioc->reply_free_host_index ==
1745 				    (ioc->reply_free_queue_depth - 1)) ?
1746 				    0 : ioc->reply_free_host_index + 1;
1747 				ioc->reply_free[ioc->reply_free_host_index] =
1748 				    cpu_to_le32(reply);
1749 				if (ioc->is_mcpu_endpoint)
1750 					_base_clone_reply_to_sys_mem(ioc,
1751 						reply,
1752 						ioc->reply_free_host_index);
1753 				writel(ioc->reply_free_host_index,
1754 				    &ioc->chip->ReplyFreeHostIndex);
1755 			}
1756 		}
1757 
1758 		rpf->Words = cpu_to_le64(ULLONG_MAX);
1759 		reply_q->reply_post_host_index =
1760 		    (reply_q->reply_post_host_index ==
1761 		    (ioc->reply_post_queue_depth - 1)) ? 0 :
1762 		    reply_q->reply_post_host_index + 1;
1763 		request_descript_type =
1764 		    reply_q->reply_post_free[reply_q->reply_post_host_index].
1765 		    Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1766 		completed_cmds++;
1767 		/* Update the reply post host index after continuously
1768 		 * processing the threshold number of Reply Descriptors.
1769 		 * So that FW can find enough entries to post the Reply
1770 		 * Descriptors in the reply descriptor post queue.
1771 		 */
1772 		if (completed_cmds >= ioc->thresh_hold) {
1773 			if (ioc->combined_reply_queue) {
1774 				writel(reply_q->reply_post_host_index |
1775 						((msix_index  & 7) <<
1776 						 MPI2_RPHI_MSIX_INDEX_SHIFT),
1777 				    ioc->replyPostRegisterIndex[msix_index/8]);
1778 			} else {
1779 				writel(reply_q->reply_post_host_index |
1780 						(msix_index <<
1781 						 MPI2_RPHI_MSIX_INDEX_SHIFT),
1782 						&ioc->chip->ReplyPostHostIndex);
1783 			}
1784 			if (!reply_q->is_iouring_poll_q &&
1785 			    !reply_q->irq_poll_scheduled) {
1786 				reply_q->irq_poll_scheduled = true;
1787 				irq_poll_sched(&reply_q->irqpoll);
1788 			}
1789 			atomic_dec(&reply_q->busy);
1790 			return completed_cmds;
1791 		}
1792 		if (request_descript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
1793 			goto out;
1794 		if (!reply_q->reply_post_host_index)
1795 			rpf = reply_q->reply_post_free;
1796 		else
1797 			rpf++;
1798 	} while (1);
1799 
1800  out:
1801 
1802 	if (!completed_cmds) {
1803 		atomic_dec(&reply_q->busy);
1804 		return completed_cmds;
1805 	}
1806 
1807 	if (ioc->is_warpdrive) {
1808 		writel(reply_q->reply_post_host_index,
1809 		ioc->reply_post_host_index[msix_index]);
1810 		atomic_dec(&reply_q->busy);
1811 		return completed_cmds;
1812 	}
1813 
1814 	/* Update Reply Post Host Index.
1815 	 * For those HBA's which support combined reply queue feature
1816 	 * 1. Get the correct Supplemental Reply Post Host Index Register.
1817 	 *    i.e. (msix_index / 8)th entry from Supplemental Reply Post Host
1818 	 *    Index Register address bank i.e replyPostRegisterIndex[],
1819 	 * 2. Then update this register with new reply host index value
1820 	 *    in ReplyPostIndex field and the MSIxIndex field with
1821 	 *    msix_index value reduced to a value between 0 and 7,
1822 	 *    using a modulo 8 operation. Since each Supplemental Reply Post
1823 	 *    Host Index Register supports 8 MSI-X vectors.
1824 	 *
1825 	 * For other HBA's just update the Reply Post Host Index register with
1826 	 * new reply host index value in ReplyPostIndex Field and msix_index
1827 	 * value in MSIxIndex field.
1828 	 */
1829 	if (ioc->combined_reply_queue)
1830 		writel(reply_q->reply_post_host_index | ((msix_index  & 7) <<
1831 			MPI2_RPHI_MSIX_INDEX_SHIFT),
1832 			ioc->replyPostRegisterIndex[msix_index/8]);
1833 	else
1834 		writel(reply_q->reply_post_host_index | (msix_index <<
1835 			MPI2_RPHI_MSIX_INDEX_SHIFT),
1836 			&ioc->chip->ReplyPostHostIndex);
1837 	atomic_dec(&reply_q->busy);
1838 	return completed_cmds;
1839 }
1840 
1841 /**
1842  * mpt3sas_blk_mq_poll - poll the blk mq poll queue
1843  * @shost: Scsi_Host object
1844  * @queue_num: hw ctx queue number
1845  *
1846  * Return number of entries that has been processed from poll queue.
1847  */
1848 int mpt3sas_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num)
1849 {
1850 	struct MPT3SAS_ADAPTER *ioc =
1851 	    (struct MPT3SAS_ADAPTER *)shost->hostdata;
1852 	struct adapter_reply_queue *reply_q;
1853 	int num_entries = 0;
1854 	int qid = queue_num - ioc->iopoll_q_start_index;
1855 
1856 	if (atomic_read(&ioc->io_uring_poll_queues[qid].pause) ||
1857 	    !atomic_add_unless(&ioc->io_uring_poll_queues[qid].busy, 1, 1))
1858 		return 0;
1859 
1860 	reply_q = ioc->io_uring_poll_queues[qid].reply_q;
1861 
1862 	num_entries = _base_process_reply_queue(reply_q);
1863 	atomic_dec(&ioc->io_uring_poll_queues[qid].busy);
1864 
1865 	return num_entries;
1866 }
1867 
1868 /**
1869  * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
1870  * @irq: irq number (not used)
1871  * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
1872  *
1873  * Return: IRQ_HANDLED if processed, else IRQ_NONE.
1874  */
1875 static irqreturn_t
1876 _base_interrupt(int irq, void *bus_id)
1877 {
1878 	struct adapter_reply_queue *reply_q = bus_id;
1879 	struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
1880 
1881 	if (ioc->mask_interrupts)
1882 		return IRQ_NONE;
1883 	if (reply_q->irq_poll_scheduled)
1884 		return IRQ_HANDLED;
1885 	return ((_base_process_reply_queue(reply_q) > 0) ?
1886 			IRQ_HANDLED : IRQ_NONE);
1887 }
1888 
1889 /**
1890  * _base_irqpoll - IRQ poll callback handler
1891  * @irqpoll: irq_poll object
1892  * @budget: irq poll weight
1893  *
1894  * Return: number of reply descriptors processed
1895  */
1896 static int
1897 _base_irqpoll(struct irq_poll *irqpoll, int budget)
1898 {
1899 	struct adapter_reply_queue *reply_q;
1900 	int num_entries = 0;
1901 
1902 	reply_q = container_of(irqpoll, struct adapter_reply_queue,
1903 			irqpoll);
1904 	if (reply_q->irq_line_enable) {
1905 		disable_irq_nosync(reply_q->os_irq);
1906 		reply_q->irq_line_enable = false;
1907 	}
1908 	num_entries = _base_process_reply_queue(reply_q);
1909 	if (num_entries < budget) {
1910 		irq_poll_complete(irqpoll);
1911 		reply_q->irq_poll_scheduled = false;
1912 		reply_q->irq_line_enable = true;
1913 		enable_irq(reply_q->os_irq);
1914 		/*
1915 		 * Go for one more round of processing the
1916 		 * reply descriptor post queue in case the HBA
1917 		 * Firmware has posted some reply descriptors
1918 		 * while reenabling the IRQ.
1919 		 */
1920 		_base_process_reply_queue(reply_q);
1921 	}
1922 
1923 	return num_entries;
1924 }
1925 
1926 /**
1927  * _base_init_irqpolls - initliaze IRQ polls
1928  * @ioc: per adapter object
1929  *
1930  * Return: nothing
1931  */
1932 static void
1933 _base_init_irqpolls(struct MPT3SAS_ADAPTER *ioc)
1934 {
1935 	struct adapter_reply_queue *reply_q, *next;
1936 
1937 	if (list_empty(&ioc->reply_queue_list))
1938 		return;
1939 
1940 	list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
1941 		if (reply_q->is_iouring_poll_q)
1942 			continue;
1943 		irq_poll_init(&reply_q->irqpoll,
1944 			ioc->hba_queue_depth/4, _base_irqpoll);
1945 		reply_q->irq_poll_scheduled = false;
1946 		reply_q->irq_line_enable = true;
1947 		reply_q->os_irq = pci_irq_vector(ioc->pdev,
1948 		    reply_q->msix_index);
1949 	}
1950 }
1951 
1952 /**
1953  * _base_is_controller_msix_enabled - is controller support muli-reply queues
1954  * @ioc: per adapter object
1955  *
1956  * Return: Whether or not MSI/X is enabled.
1957  */
1958 static inline int
1959 _base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc)
1960 {
1961 	return (ioc->facts.IOCCapabilities &
1962 	    MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable;
1963 }
1964 
1965 /**
1966  * mpt3sas_base_sync_reply_irqs - flush pending MSIX interrupts
1967  * @ioc: per adapter object
1968  * @poll: poll over reply descriptor pools incase interrupt for
1969  *		timed-out SCSI command got delayed
1970  * Context: non-ISR context
1971  *
1972  * Called when a Task Management request has completed.
1973  */
1974 void
1975 mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc, u8 poll)
1976 {
1977 	struct adapter_reply_queue *reply_q;
1978 
1979 	/* If MSIX capability is turned off
1980 	 * then multi-queues are not enabled
1981 	 */
1982 	if (!_base_is_controller_msix_enabled(ioc))
1983 		return;
1984 
1985 	list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1986 		if (ioc->shost_recovery || ioc->remove_host ||
1987 				ioc->pci_error_recovery)
1988 			return;
1989 		/* TMs are on msix_index == 0 */
1990 		if (reply_q->msix_index == 0)
1991 			continue;
1992 
1993 		if (reply_q->is_iouring_poll_q) {
1994 			_base_process_reply_queue(reply_q);
1995 			continue;
1996 		}
1997 
1998 		synchronize_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index));
1999 		if (reply_q->irq_poll_scheduled) {
2000 			/* Calling irq_poll_disable will wait for any pending
2001 			 * callbacks to have completed.
2002 			 */
2003 			irq_poll_disable(&reply_q->irqpoll);
2004 			irq_poll_enable(&reply_q->irqpoll);
2005 			/* check how the scheduled poll has ended,
2006 			 * clean up only if necessary
2007 			 */
2008 			if (reply_q->irq_poll_scheduled) {
2009 				reply_q->irq_poll_scheduled = false;
2010 				reply_q->irq_line_enable = true;
2011 				enable_irq(reply_q->os_irq);
2012 			}
2013 		}
2014 	}
2015 	if (poll)
2016 		_base_process_reply_queue(reply_q);
2017 }
2018 
2019 /**
2020  * mpt3sas_base_release_callback_handler - clear interrupt callback handler
2021  * @cb_idx: callback index
2022  */
2023 void
2024 mpt3sas_base_release_callback_handler(u8 cb_idx)
2025 {
2026 	mpt_callbacks[cb_idx] = NULL;
2027 }
2028 
2029 /**
2030  * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler
2031  * @cb_func: callback function
2032  *
2033  * Return: Index of @cb_func.
2034  */
2035 u8
2036 mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func)
2037 {
2038 	u8 cb_idx;
2039 
2040 	for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
2041 		if (mpt_callbacks[cb_idx] == NULL)
2042 			break;
2043 
2044 	mpt_callbacks[cb_idx] = cb_func;
2045 	return cb_idx;
2046 }
2047 
2048 /**
2049  * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler
2050  */
2051 void
2052 mpt3sas_base_initialize_callback_handler(void)
2053 {
2054 	u8 cb_idx;
2055 
2056 	for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
2057 		mpt3sas_base_release_callback_handler(cb_idx);
2058 }
2059 
2060 
2061 /**
2062  * _base_build_zero_len_sge - build zero length sg entry
2063  * @ioc: per adapter object
2064  * @paddr: virtual address for SGE
2065  *
2066  * Create a zero length scatter gather entry to insure the IOCs hardware has
2067  * something to use if the target device goes brain dead and tries
2068  * to send data even when none is asked for.
2069  */
2070 static void
2071 _base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr)
2072 {
2073 	u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
2074 	    MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
2075 	    MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
2076 	    MPI2_SGE_FLAGS_SHIFT);
2077 	ioc->base_add_sg_single(paddr, flags_length, -1);
2078 }
2079 
2080 /**
2081  * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr.
2082  * @paddr: virtual address for SGE
2083  * @flags_length: SGE flags and data transfer length
2084  * @dma_addr: Physical address
2085  */
2086 static void
2087 _base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
2088 {
2089 	Mpi2SGESimple32_t *sgel = paddr;
2090 
2091 	flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
2092 	    MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
2093 	sgel->FlagsLength = cpu_to_le32(flags_length);
2094 	sgel->Address = cpu_to_le32(dma_addr);
2095 }
2096 
2097 
2098 /**
2099  * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr.
2100  * @paddr: virtual address for SGE
2101  * @flags_length: SGE flags and data transfer length
2102  * @dma_addr: Physical address
2103  */
2104 static void
2105 _base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
2106 {
2107 	Mpi2SGESimple64_t *sgel = paddr;
2108 
2109 	flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
2110 	    MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
2111 	sgel->FlagsLength = cpu_to_le32(flags_length);
2112 	sgel->Address = cpu_to_le64(dma_addr);
2113 }
2114 
2115 /**
2116  * _base_get_chain_buffer_tracker - obtain chain tracker
2117  * @ioc: per adapter object
2118  * @scmd: SCSI commands of the IO request
2119  *
2120  * Return: chain tracker from chain_lookup table using key as
2121  * smid and smid's chain_offset.
2122  */
2123 static struct chain_tracker *
2124 _base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc,
2125 			       struct scsi_cmnd *scmd)
2126 {
2127 	struct chain_tracker *chain_req;
2128 	struct scsiio_tracker *st = scsi_cmd_priv(scmd);
2129 	u16 smid = st->smid;
2130 	u8 chain_offset =
2131 	   atomic_read(&ioc->chain_lookup[smid - 1].chain_offset);
2132 
2133 	if (chain_offset == ioc->chains_needed_per_io)
2134 		return NULL;
2135 
2136 	chain_req = &ioc->chain_lookup[smid - 1].chains_per_smid[chain_offset];
2137 	atomic_inc(&ioc->chain_lookup[smid - 1].chain_offset);
2138 	return chain_req;
2139 }
2140 
2141 
2142 /**
2143  * _base_build_sg - build generic sg
2144  * @ioc: per adapter object
2145  * @psge: virtual address for SGE
2146  * @data_out_dma: physical address for WRITES
2147  * @data_out_sz: data xfer size for WRITES
2148  * @data_in_dma: physical address for READS
2149  * @data_in_sz: data xfer size for READS
2150  */
2151 static void
2152 _base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge,
2153 	dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
2154 	size_t data_in_sz)
2155 {
2156 	u32 sgl_flags;
2157 
2158 	if (!data_out_sz && !data_in_sz) {
2159 		_base_build_zero_len_sge(ioc, psge);
2160 		return;
2161 	}
2162 
2163 	if (data_out_sz && data_in_sz) {
2164 		/* WRITE sgel first */
2165 		sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
2166 		    MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC);
2167 		sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
2168 		ioc->base_add_sg_single(psge, sgl_flags |
2169 		    data_out_sz, data_out_dma);
2170 
2171 		/* incr sgel */
2172 		psge += ioc->sge_size;
2173 
2174 		/* READ sgel last */
2175 		sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
2176 		    MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
2177 		    MPI2_SGE_FLAGS_END_OF_LIST);
2178 		sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
2179 		ioc->base_add_sg_single(psge, sgl_flags |
2180 		    data_in_sz, data_in_dma);
2181 	} else if (data_out_sz) /* WRITE */ {
2182 		sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
2183 		    MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
2184 		    MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC);
2185 		sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
2186 		ioc->base_add_sg_single(psge, sgl_flags |
2187 		    data_out_sz, data_out_dma);
2188 	} else if (data_in_sz) /* READ */ {
2189 		sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
2190 		    MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
2191 		    MPI2_SGE_FLAGS_END_OF_LIST);
2192 		sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
2193 		ioc->base_add_sg_single(psge, sgl_flags |
2194 		    data_in_sz, data_in_dma);
2195 	}
2196 }
2197 
2198 /* IEEE format sgls */
2199 
2200 /**
2201  * _base_build_nvme_prp - This function is called for NVMe end devices to build
2202  *                        a native SGL (NVMe PRP).
2203  * @ioc: per adapter object
2204  * @smid: system request message index for getting asscociated SGL
2205  * @nvme_encap_request: the NVMe request msg frame pointer
2206  * @data_out_dma: physical address for WRITES
2207  * @data_out_sz: data xfer size for WRITES
2208  * @data_in_dma: physical address for READS
2209  * @data_in_sz: data xfer size for READS
2210  *
2211  * The native SGL is built starting in the first PRP
2212  * entry of the NVMe message (PRP1).  If the data buffer is small enough to be
2213  * described entirely using PRP1, then PRP2 is not used.  If needed, PRP2 is
2214  * used to describe a larger data buffer.  If the data buffer is too large to
2215  * describe using the two PRP entriess inside the NVMe message, then PRP1
2216  * describes the first data memory segment, and PRP2 contains a pointer to a PRP
2217  * list located elsewhere in memory to describe the remaining data memory
2218  * segments.  The PRP list will be contiguous.
2219  *
2220  * The native SGL for NVMe devices is a Physical Region Page (PRP).  A PRP
2221  * consists of a list of PRP entries to describe a number of noncontigous
2222  * physical memory segments as a single memory buffer, just as a SGL does.  Note
2223  * however, that this function is only used by the IOCTL call, so the memory
2224  * given will be guaranteed to be contiguous.  There is no need to translate
2225  * non-contiguous SGL into a PRP in this case.  All PRPs will describe
2226  * contiguous space that is one page size each.
2227  *
2228  * Each NVMe message contains two PRP entries.  The first (PRP1) either contains
2229  * a PRP list pointer or a PRP element, depending upon the command.  PRP2
2230  * contains the second PRP element if the memory being described fits within 2
2231  * PRP entries, or a PRP list pointer if the PRP spans more than two entries.
2232  *
2233  * A PRP list pointer contains the address of a PRP list, structured as a linear
2234  * array of PRP entries.  Each PRP entry in this list describes a segment of
2235  * physical memory.
2236  *
2237  * Each 64-bit PRP entry comprises an address and an offset field.  The address
2238  * always points at the beginning of a 4KB physical memory page, and the offset
2239  * describes where within that 4KB page the memory segment begins.  Only the
2240  * first element in a PRP list may contain a non-zero offset, implying that all
2241  * memory segments following the first begin at the start of a 4KB page.
2242  *
2243  * Each PRP element normally describes 4KB of physical memory, with exceptions
2244  * for the first and last elements in the list.  If the memory being described
2245  * by the list begins at a non-zero offset within the first 4KB page, then the
2246  * first PRP element will contain a non-zero offset indicating where the region
2247  * begins within the 4KB page.  The last memory segment may end before the end
2248  * of the 4KB segment, depending upon the overall size of the memory being
2249  * described by the PRP list.
2250  *
2251  * Since PRP entries lack any indication of size, the overall data buffer length
2252  * is used to determine where the end of the data memory buffer is located, and
2253  * how many PRP entries are required to describe it.
2254  */
2255 static void
2256 _base_build_nvme_prp(struct MPT3SAS_ADAPTER *ioc, u16 smid,
2257 	Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request,
2258 	dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
2259 	size_t data_in_sz)
2260 {
2261 	int		prp_size = NVME_PRP_SIZE;
2262 	__le64		*prp_entry, *prp1_entry, *prp2_entry;
2263 	__le64		*prp_page;
2264 	dma_addr_t	prp_entry_dma, prp_page_dma, dma_addr;
2265 	u32		offset, entry_len;
2266 	u32		page_mask_result, page_mask;
2267 	size_t		length;
2268 	struct mpt3sas_nvme_cmd *nvme_cmd =
2269 		(void *)nvme_encap_request->NVMe_Command;
2270 
2271 	/*
2272 	 * Not all commands require a data transfer. If no data, just return
2273 	 * without constructing any PRP.
2274 	 */
2275 	if (!data_in_sz && !data_out_sz)
2276 		return;
2277 	prp1_entry = &nvme_cmd->prp1;
2278 	prp2_entry = &nvme_cmd->prp2;
2279 	prp_entry = prp1_entry;
2280 	/*
2281 	 * For the PRP entries, use the specially allocated buffer of
2282 	 * contiguous memory.
2283 	 */
2284 	prp_page = (__le64 *)mpt3sas_base_get_pcie_sgl(ioc, smid);
2285 	prp_page_dma = mpt3sas_base_get_pcie_sgl_dma(ioc, smid);
2286 
2287 	/*
2288 	 * Check if we are within 1 entry of a page boundary we don't
2289 	 * want our first entry to be a PRP List entry.
2290 	 */
2291 	page_mask = ioc->page_size - 1;
2292 	page_mask_result = (uintptr_t)((u8 *)prp_page + prp_size) & page_mask;
2293 	if (!page_mask_result) {
2294 		/* Bump up to next page boundary. */
2295 		prp_page = (__le64 *)((u8 *)prp_page + prp_size);
2296 		prp_page_dma = prp_page_dma + prp_size;
2297 	}
2298 
2299 	/*
2300 	 * Set PRP physical pointer, which initially points to the current PRP
2301 	 * DMA memory page.
2302 	 */
2303 	prp_entry_dma = prp_page_dma;
2304 
2305 	/* Get physical address and length of the data buffer. */
2306 	if (data_in_sz) {
2307 		dma_addr = data_in_dma;
2308 		length = data_in_sz;
2309 	} else {
2310 		dma_addr = data_out_dma;
2311 		length = data_out_sz;
2312 	}
2313 
2314 	/* Loop while the length is not zero. */
2315 	while (length) {
2316 		/*
2317 		 * Check if we need to put a list pointer here if we are at
2318 		 * page boundary - prp_size (8 bytes).
2319 		 */
2320 		page_mask_result = (prp_entry_dma + prp_size) & page_mask;
2321 		if (!page_mask_result) {
2322 			/*
2323 			 * This is the last entry in a PRP List, so we need to
2324 			 * put a PRP list pointer here.  What this does is:
2325 			 *   - bump the current memory pointer to the next
2326 			 *     address, which will be the next full page.
2327 			 *   - set the PRP Entry to point to that page.  This
2328 			 *     is now the PRP List pointer.
2329 			 *   - bump the PRP Entry pointer the start of the
2330 			 *     next page.  Since all of this PRP memory is
2331 			 *     contiguous, no need to get a new page - it's
2332 			 *     just the next address.
2333 			 */
2334 			prp_entry_dma++;
2335 			*prp_entry = cpu_to_le64(prp_entry_dma);
2336 			prp_entry++;
2337 		}
2338 
2339 		/* Need to handle if entry will be part of a page. */
2340 		offset = dma_addr & page_mask;
2341 		entry_len = ioc->page_size - offset;
2342 
2343 		if (prp_entry == prp1_entry) {
2344 			/*
2345 			 * Must fill in the first PRP pointer (PRP1) before
2346 			 * moving on.
2347 			 */
2348 			*prp1_entry = cpu_to_le64(dma_addr);
2349 
2350 			/*
2351 			 * Now point to the second PRP entry within the
2352 			 * command (PRP2).
2353 			 */
2354 			prp_entry = prp2_entry;
2355 		} else if (prp_entry == prp2_entry) {
2356 			/*
2357 			 * Should the PRP2 entry be a PRP List pointer or just
2358 			 * a regular PRP pointer?  If there is more than one
2359 			 * more page of data, must use a PRP List pointer.
2360 			 */
2361 			if (length > ioc->page_size) {
2362 				/*
2363 				 * PRP2 will contain a PRP List pointer because
2364 				 * more PRP's are needed with this command. The
2365 				 * list will start at the beginning of the
2366 				 * contiguous buffer.
2367 				 */
2368 				*prp2_entry = cpu_to_le64(prp_entry_dma);
2369 
2370 				/*
2371 				 * The next PRP Entry will be the start of the
2372 				 * first PRP List.
2373 				 */
2374 				prp_entry = prp_page;
2375 			} else {
2376 				/*
2377 				 * After this, the PRP Entries are complete.
2378 				 * This command uses 2 PRP's and no PRP list.
2379 				 */
2380 				*prp2_entry = cpu_to_le64(dma_addr);
2381 			}
2382 		} else {
2383 			/*
2384 			 * Put entry in list and bump the addresses.
2385 			 *
2386 			 * After PRP1 and PRP2 are filled in, this will fill in
2387 			 * all remaining PRP entries in a PRP List, one per
2388 			 * each time through the loop.
2389 			 */
2390 			*prp_entry = cpu_to_le64(dma_addr);
2391 			prp_entry++;
2392 			prp_entry_dma++;
2393 		}
2394 
2395 		/*
2396 		 * Bump the phys address of the command's data buffer by the
2397 		 * entry_len.
2398 		 */
2399 		dma_addr += entry_len;
2400 
2401 		/* Decrement length accounting for last partial page. */
2402 		if (entry_len > length)
2403 			length = 0;
2404 		else
2405 			length -= entry_len;
2406 	}
2407 }
2408 
2409 /**
2410  * base_make_prp_nvme - Prepare PRPs (Physical Region Page) -
2411  *			SGLs specific to NVMe drives only
2412  *
2413  * @ioc:		per adapter object
2414  * @scmd:		SCSI command from the mid-layer
2415  * @mpi_request:	mpi request
2416  * @smid:		msg Index
2417  * @sge_count:		scatter gather element count.
2418  *
2419  * Return:		true: PRPs are built
2420  *			false: IEEE SGLs needs to be built
2421  */
2422 static void
2423 base_make_prp_nvme(struct MPT3SAS_ADAPTER *ioc,
2424 		struct scsi_cmnd *scmd,
2425 		Mpi25SCSIIORequest_t *mpi_request,
2426 		u16 smid, int sge_count)
2427 {
2428 	int sge_len, num_prp_in_chain = 0;
2429 	Mpi25IeeeSgeChain64_t *main_chain_element, *ptr_first_sgl;
2430 	__le64 *curr_buff;
2431 	dma_addr_t msg_dma, sge_addr, offset;
2432 	u32 page_mask, page_mask_result;
2433 	struct scatterlist *sg_scmd;
2434 	u32 first_prp_len;
2435 	int data_len = scsi_bufflen(scmd);
2436 	u32 nvme_pg_size;
2437 
2438 	nvme_pg_size = max_t(u32, ioc->page_size, NVME_PRP_PAGE_SIZE);
2439 	/*
2440 	 * Nvme has a very convoluted prp format.  One prp is required
2441 	 * for each page or partial page. Driver need to split up OS sg_list
2442 	 * entries if it is longer than one page or cross a page
2443 	 * boundary.  Driver also have to insert a PRP list pointer entry as
2444 	 * the last entry in each physical page of the PRP list.
2445 	 *
2446 	 * NOTE: The first PRP "entry" is actually placed in the first
2447 	 * SGL entry in the main message as IEEE 64 format.  The 2nd
2448 	 * entry in the main message is the chain element, and the rest
2449 	 * of the PRP entries are built in the contiguous pcie buffer.
2450 	 */
2451 	page_mask = nvme_pg_size - 1;
2452 
2453 	/*
2454 	 * Native SGL is needed.
2455 	 * Put a chain element in main message frame that points to the first
2456 	 * chain buffer.
2457 	 *
2458 	 * NOTE:  The ChainOffset field must be 0 when using a chain pointer to
2459 	 *        a native SGL.
2460 	 */
2461 
2462 	/* Set main message chain element pointer */
2463 	main_chain_element = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL;
2464 	/*
2465 	 * For NVMe the chain element needs to be the 2nd SG entry in the main
2466 	 * message.
2467 	 */
2468 	main_chain_element = (Mpi25IeeeSgeChain64_t *)
2469 		((u8 *)main_chain_element + sizeof(MPI25_IEEE_SGE_CHAIN64));
2470 
2471 	/*
2472 	 * For the PRP entries, use the specially allocated buffer of
2473 	 * contiguous memory.  Normal chain buffers can't be used
2474 	 * because each chain buffer would need to be the size of an OS
2475 	 * page (4k).
2476 	 */
2477 	curr_buff = mpt3sas_base_get_pcie_sgl(ioc, smid);
2478 	msg_dma = mpt3sas_base_get_pcie_sgl_dma(ioc, smid);
2479 
2480 	main_chain_element->Address = cpu_to_le64(msg_dma);
2481 	main_chain_element->NextChainOffset = 0;
2482 	main_chain_element->Flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
2483 			MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
2484 			MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP;
2485 
2486 	/* Build first prp, sge need not to be page aligned*/
2487 	ptr_first_sgl = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL;
2488 	sg_scmd = scsi_sglist(scmd);
2489 	sge_addr = sg_dma_address(sg_scmd);
2490 	sge_len = sg_dma_len(sg_scmd);
2491 
2492 	offset = sge_addr & page_mask;
2493 	first_prp_len = nvme_pg_size - offset;
2494 
2495 	ptr_first_sgl->Address = cpu_to_le64(sge_addr);
2496 	ptr_first_sgl->Length = cpu_to_le32(first_prp_len);
2497 
2498 	data_len -= first_prp_len;
2499 
2500 	if (sge_len > first_prp_len) {
2501 		sge_addr += first_prp_len;
2502 		sge_len -= first_prp_len;
2503 	} else if (data_len && (sge_len == first_prp_len)) {
2504 		sg_scmd = sg_next(sg_scmd);
2505 		sge_addr = sg_dma_address(sg_scmd);
2506 		sge_len = sg_dma_len(sg_scmd);
2507 	}
2508 
2509 	for (;;) {
2510 		offset = sge_addr & page_mask;
2511 
2512 		/* Put PRP pointer due to page boundary*/
2513 		page_mask_result = (uintptr_t)(curr_buff + 1) & page_mask;
2514 		if (unlikely(!page_mask_result)) {
2515 			scmd_printk(KERN_NOTICE,
2516 				scmd, "page boundary curr_buff: 0x%p\n",
2517 				curr_buff);
2518 			msg_dma += 8;
2519 			*curr_buff = cpu_to_le64(msg_dma);
2520 			curr_buff++;
2521 			num_prp_in_chain++;
2522 		}
2523 
2524 		*curr_buff = cpu_to_le64(sge_addr);
2525 		curr_buff++;
2526 		msg_dma += 8;
2527 		num_prp_in_chain++;
2528 
2529 		sge_addr += nvme_pg_size;
2530 		sge_len -= nvme_pg_size;
2531 		data_len -= nvme_pg_size;
2532 
2533 		if (data_len <= 0)
2534 			break;
2535 
2536 		if (sge_len > 0)
2537 			continue;
2538 
2539 		sg_scmd = sg_next(sg_scmd);
2540 		sge_addr = sg_dma_address(sg_scmd);
2541 		sge_len = sg_dma_len(sg_scmd);
2542 	}
2543 
2544 	main_chain_element->Length =
2545 		cpu_to_le32(num_prp_in_chain * sizeof(u64));
2546 	return;
2547 }
2548 
2549 static bool
2550 base_is_prp_possible(struct MPT3SAS_ADAPTER *ioc,
2551 	struct _pcie_device *pcie_device, struct scsi_cmnd *scmd, int sge_count)
2552 {
2553 	u32 data_length = 0;
2554 	bool build_prp = true;
2555 
2556 	data_length = scsi_bufflen(scmd);
2557 	if (pcie_device &&
2558 	    (mpt3sas_scsih_is_pcie_scsi_device(pcie_device->device_info))) {
2559 		build_prp = false;
2560 		return build_prp;
2561 	}
2562 
2563 	/* If Datalenth is <= 16K and number of SGE’s entries are <= 2
2564 	 * we built IEEE SGL
2565 	 */
2566 	if ((data_length <= NVME_PRP_PAGE_SIZE*4) && (sge_count <= 2))
2567 		build_prp = false;
2568 
2569 	return build_prp;
2570 }
2571 
2572 /**
2573  * _base_check_pcie_native_sgl - This function is called for PCIe end devices to
2574  * determine if the driver needs to build a native SGL.  If so, that native
2575  * SGL is built in the special contiguous buffers allocated especially for
2576  * PCIe SGL creation.  If the driver will not build a native SGL, return
2577  * TRUE and a normal IEEE SGL will be built.  Currently this routine
2578  * supports NVMe.
2579  * @ioc: per adapter object
2580  * @mpi_request: mf request pointer
2581  * @smid: system request message index
2582  * @scmd: scsi command
2583  * @pcie_device: points to the PCIe device's info
2584  *
2585  * Return: 0 if native SGL was built, 1 if no SGL was built
2586  */
2587 static int
2588 _base_check_pcie_native_sgl(struct MPT3SAS_ADAPTER *ioc,
2589 	Mpi25SCSIIORequest_t *mpi_request, u16 smid, struct scsi_cmnd *scmd,
2590 	struct _pcie_device *pcie_device)
2591 {
2592 	int sges_left;
2593 
2594 	/* Get the SG list pointer and info. */
2595 	sges_left = scsi_dma_map(scmd);
2596 	if (sges_left < 0) {
2597 		sdev_printk(KERN_ERR, scmd->device,
2598 			"scsi_dma_map failed: request for %d bytes!\n",
2599 			scsi_bufflen(scmd));
2600 		return 1;
2601 	}
2602 
2603 	/* Check if we need to build a native SG list. */
2604 	if (!base_is_prp_possible(ioc, pcie_device,
2605 				scmd, sges_left)) {
2606 		/* We built a native SG list, just return. */
2607 		goto out;
2608 	}
2609 
2610 	/*
2611 	 * Build native NVMe PRP.
2612 	 */
2613 	base_make_prp_nvme(ioc, scmd, mpi_request,
2614 			smid, sges_left);
2615 
2616 	return 0;
2617 out:
2618 	scsi_dma_unmap(scmd);
2619 	return 1;
2620 }
2621 
2622 /**
2623  * _base_add_sg_single_ieee - add sg element for IEEE format
2624  * @paddr: virtual address for SGE
2625  * @flags: SGE flags
2626  * @chain_offset: number of 128 byte elements from start of segment
2627  * @length: data transfer length
2628  * @dma_addr: Physical address
2629  */
2630 static void
2631 _base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length,
2632 	dma_addr_t dma_addr)
2633 {
2634 	Mpi25IeeeSgeChain64_t *sgel = paddr;
2635 
2636 	sgel->Flags = flags;
2637 	sgel->NextChainOffset = chain_offset;
2638 	sgel->Length = cpu_to_le32(length);
2639 	sgel->Address = cpu_to_le64(dma_addr);
2640 }
2641 
2642 /**
2643  * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format
2644  * @ioc: per adapter object
2645  * @paddr: virtual address for SGE
2646  *
2647  * Create a zero length scatter gather entry to insure the IOCs hardware has
2648  * something to use if the target device goes brain dead and tries
2649  * to send data even when none is asked for.
2650  */
2651 static void
2652 _base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr)
2653 {
2654 	u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2655 		MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
2656 		MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
2657 
2658 	_base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1);
2659 }
2660 
2661 /**
2662  * _base_build_sg_scmd - main sg creation routine
2663  *		pcie_device is unused here!
2664  * @ioc: per adapter object
2665  * @scmd: scsi command
2666  * @smid: system request message index
2667  * @unused: unused pcie_device pointer
2668  * Context: none.
2669  *
2670  * The main routine that builds scatter gather table from a given
2671  * scsi request sent via the .queuecommand main handler.
2672  *
2673  * Return: 0 success, anything else error
2674  */
2675 static int
2676 _base_build_sg_scmd(struct MPT3SAS_ADAPTER *ioc,
2677 	struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *unused)
2678 {
2679 	Mpi2SCSIIORequest_t *mpi_request;
2680 	dma_addr_t chain_dma;
2681 	struct scatterlist *sg_scmd;
2682 	void *sg_local, *chain;
2683 	u32 chain_offset;
2684 	u32 chain_length;
2685 	u32 chain_flags;
2686 	int sges_left;
2687 	u32 sges_in_segment;
2688 	u32 sgl_flags;
2689 	u32 sgl_flags_last_element;
2690 	u32 sgl_flags_end_buffer;
2691 	struct chain_tracker *chain_req;
2692 
2693 	mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
2694 
2695 	/* init scatter gather flags */
2696 	sgl_flags = MPI2_SGE_FLAGS_SIMPLE_ELEMENT;
2697 	if (scmd->sc_data_direction == DMA_TO_DEVICE)
2698 		sgl_flags |= MPI2_SGE_FLAGS_HOST_TO_IOC;
2699 	sgl_flags_last_element = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT)
2700 	    << MPI2_SGE_FLAGS_SHIFT;
2701 	sgl_flags_end_buffer = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT |
2702 	    MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST)
2703 	    << MPI2_SGE_FLAGS_SHIFT;
2704 	sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
2705 
2706 	sg_scmd = scsi_sglist(scmd);
2707 	sges_left = scsi_dma_map(scmd);
2708 	if (sges_left < 0) {
2709 		sdev_printk(KERN_ERR, scmd->device,
2710 		 "scsi_dma_map failed: request for %d bytes!\n",
2711 		 scsi_bufflen(scmd));
2712 		return -ENOMEM;
2713 	}
2714 
2715 	sg_local = &mpi_request->SGL;
2716 	sges_in_segment = ioc->max_sges_in_main_message;
2717 	if (sges_left <= sges_in_segment)
2718 		goto fill_in_last_segment;
2719 
2720 	mpi_request->ChainOffset = (offsetof(Mpi2SCSIIORequest_t, SGL) +
2721 	    (sges_in_segment * ioc->sge_size))/4;
2722 
2723 	/* fill in main message segment when there is a chain following */
2724 	while (sges_in_segment) {
2725 		if (sges_in_segment == 1)
2726 			ioc->base_add_sg_single(sg_local,
2727 			    sgl_flags_last_element | sg_dma_len(sg_scmd),
2728 			    sg_dma_address(sg_scmd));
2729 		else
2730 			ioc->base_add_sg_single(sg_local, sgl_flags |
2731 			    sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2732 		sg_scmd = sg_next(sg_scmd);
2733 		sg_local += ioc->sge_size;
2734 		sges_left--;
2735 		sges_in_segment--;
2736 	}
2737 
2738 	/* initializing the chain flags and pointers */
2739 	chain_flags = MPI2_SGE_FLAGS_CHAIN_ELEMENT << MPI2_SGE_FLAGS_SHIFT;
2740 	chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
2741 	if (!chain_req)
2742 		return -1;
2743 	chain = chain_req->chain_buffer;
2744 	chain_dma = chain_req->chain_buffer_dma;
2745 	do {
2746 		sges_in_segment = (sges_left <=
2747 		    ioc->max_sges_in_chain_message) ? sges_left :
2748 		    ioc->max_sges_in_chain_message;
2749 		chain_offset = (sges_left == sges_in_segment) ?
2750 		    0 : (sges_in_segment * ioc->sge_size)/4;
2751 		chain_length = sges_in_segment * ioc->sge_size;
2752 		if (chain_offset) {
2753 			chain_offset = chain_offset <<
2754 			    MPI2_SGE_CHAIN_OFFSET_SHIFT;
2755 			chain_length += ioc->sge_size;
2756 		}
2757 		ioc->base_add_sg_single(sg_local, chain_flags | chain_offset |
2758 		    chain_length, chain_dma);
2759 		sg_local = chain;
2760 		if (!chain_offset)
2761 			goto fill_in_last_segment;
2762 
2763 		/* fill in chain segments */
2764 		while (sges_in_segment) {
2765 			if (sges_in_segment == 1)
2766 				ioc->base_add_sg_single(sg_local,
2767 				    sgl_flags_last_element |
2768 				    sg_dma_len(sg_scmd),
2769 				    sg_dma_address(sg_scmd));
2770 			else
2771 				ioc->base_add_sg_single(sg_local, sgl_flags |
2772 				    sg_dma_len(sg_scmd),
2773 				    sg_dma_address(sg_scmd));
2774 			sg_scmd = sg_next(sg_scmd);
2775 			sg_local += ioc->sge_size;
2776 			sges_left--;
2777 			sges_in_segment--;
2778 		}
2779 
2780 		chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
2781 		if (!chain_req)
2782 			return -1;
2783 		chain = chain_req->chain_buffer;
2784 		chain_dma = chain_req->chain_buffer_dma;
2785 	} while (1);
2786 
2787 
2788  fill_in_last_segment:
2789 
2790 	/* fill the last segment */
2791 	while (sges_left) {
2792 		if (sges_left == 1)
2793 			ioc->base_add_sg_single(sg_local, sgl_flags_end_buffer |
2794 			    sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2795 		else
2796 			ioc->base_add_sg_single(sg_local, sgl_flags |
2797 			    sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2798 		sg_scmd = sg_next(sg_scmd);
2799 		sg_local += ioc->sge_size;
2800 		sges_left--;
2801 	}
2802 
2803 	return 0;
2804 }
2805 
2806 /**
2807  * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format
2808  * @ioc: per adapter object
2809  * @scmd: scsi command
2810  * @smid: system request message index
2811  * @pcie_device: Pointer to pcie_device. If set, the pcie native sgl will be
2812  * constructed on need.
2813  * Context: none.
2814  *
2815  * The main routine that builds scatter gather table from a given
2816  * scsi request sent via the .queuecommand main handler.
2817  *
2818  * Return: 0 success, anything else error
2819  */
2820 static int
2821 _base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc,
2822 	struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *pcie_device)
2823 {
2824 	Mpi25SCSIIORequest_t *mpi_request;
2825 	dma_addr_t chain_dma;
2826 	struct scatterlist *sg_scmd;
2827 	void *sg_local, *chain;
2828 	u32 chain_offset;
2829 	u32 chain_length;
2830 	int sges_left;
2831 	u32 sges_in_segment;
2832 	u8 simple_sgl_flags;
2833 	u8 simple_sgl_flags_last;
2834 	u8 chain_sgl_flags;
2835 	struct chain_tracker *chain_req;
2836 
2837 	mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
2838 
2839 	/* init scatter gather flags */
2840 	simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2841 	    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2842 	simple_sgl_flags_last = simple_sgl_flags |
2843 	    MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
2844 	chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
2845 	    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2846 
2847 	/* Check if we need to build a native SG list. */
2848 	if ((pcie_device) && (_base_check_pcie_native_sgl(ioc, mpi_request,
2849 			smid, scmd, pcie_device) == 0)) {
2850 		/* We built a native SG list, just return. */
2851 		return 0;
2852 	}
2853 
2854 	sg_scmd = scsi_sglist(scmd);
2855 	sges_left = scsi_dma_map(scmd);
2856 	if (sges_left < 0) {
2857 		sdev_printk(KERN_ERR, scmd->device,
2858 			"scsi_dma_map failed: request for %d bytes!\n",
2859 			scsi_bufflen(scmd));
2860 		return -ENOMEM;
2861 	}
2862 
2863 	sg_local = &mpi_request->SGL;
2864 	sges_in_segment = (ioc->request_sz -
2865 		   offsetof(Mpi25SCSIIORequest_t, SGL))/ioc->sge_size_ieee;
2866 	if (sges_left <= sges_in_segment)
2867 		goto fill_in_last_segment;
2868 
2869 	mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) +
2870 	    (offsetof(Mpi25SCSIIORequest_t, SGL)/ioc->sge_size_ieee);
2871 
2872 	/* fill in main message segment when there is a chain following */
2873 	while (sges_in_segment > 1) {
2874 		_base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
2875 		    sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2876 		sg_scmd = sg_next(sg_scmd);
2877 		sg_local += ioc->sge_size_ieee;
2878 		sges_left--;
2879 		sges_in_segment--;
2880 	}
2881 
2882 	/* initializing the pointers */
2883 	chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
2884 	if (!chain_req)
2885 		return -1;
2886 	chain = chain_req->chain_buffer;
2887 	chain_dma = chain_req->chain_buffer_dma;
2888 	do {
2889 		sges_in_segment = (sges_left <=
2890 		    ioc->max_sges_in_chain_message) ? sges_left :
2891 		    ioc->max_sges_in_chain_message;
2892 		chain_offset = (sges_left == sges_in_segment) ?
2893 		    0 : sges_in_segment;
2894 		chain_length = sges_in_segment * ioc->sge_size_ieee;
2895 		if (chain_offset)
2896 			chain_length += ioc->sge_size_ieee;
2897 		_base_add_sg_single_ieee(sg_local, chain_sgl_flags,
2898 		    chain_offset, chain_length, chain_dma);
2899 
2900 		sg_local = chain;
2901 		if (!chain_offset)
2902 			goto fill_in_last_segment;
2903 
2904 		/* fill in chain segments */
2905 		while (sges_in_segment) {
2906 			_base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
2907 			    sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2908 			sg_scmd = sg_next(sg_scmd);
2909 			sg_local += ioc->sge_size_ieee;
2910 			sges_left--;
2911 			sges_in_segment--;
2912 		}
2913 
2914 		chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
2915 		if (!chain_req)
2916 			return -1;
2917 		chain = chain_req->chain_buffer;
2918 		chain_dma = chain_req->chain_buffer_dma;
2919 	} while (1);
2920 
2921 
2922  fill_in_last_segment:
2923 
2924 	/* fill the last segment */
2925 	while (sges_left > 0) {
2926 		if (sges_left == 1)
2927 			_base_add_sg_single_ieee(sg_local,
2928 			    simple_sgl_flags_last, 0, sg_dma_len(sg_scmd),
2929 			    sg_dma_address(sg_scmd));
2930 		else
2931 			_base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
2932 			    sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2933 		sg_scmd = sg_next(sg_scmd);
2934 		sg_local += ioc->sge_size_ieee;
2935 		sges_left--;
2936 	}
2937 
2938 	return 0;
2939 }
2940 
2941 /**
2942  * _base_build_sg_ieee - build generic sg for IEEE format
2943  * @ioc: per adapter object
2944  * @psge: virtual address for SGE
2945  * @data_out_dma: physical address for WRITES
2946  * @data_out_sz: data xfer size for WRITES
2947  * @data_in_dma: physical address for READS
2948  * @data_in_sz: data xfer size for READS
2949  */
2950 static void
2951 _base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge,
2952 	dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
2953 	size_t data_in_sz)
2954 {
2955 	u8 sgl_flags;
2956 
2957 	if (!data_out_sz && !data_in_sz) {
2958 		_base_build_zero_len_sge_ieee(ioc, psge);
2959 		return;
2960 	}
2961 
2962 	if (data_out_sz && data_in_sz) {
2963 		/* WRITE sgel first */
2964 		sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2965 		    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2966 		_base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
2967 		    data_out_dma);
2968 
2969 		/* incr sgel */
2970 		psge += ioc->sge_size_ieee;
2971 
2972 		/* READ sgel last */
2973 		sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
2974 		_base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
2975 		    data_in_dma);
2976 	} else if (data_out_sz) /* WRITE */ {
2977 		sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2978 		    MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
2979 		    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2980 		_base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
2981 		    data_out_dma);
2982 	} else if (data_in_sz) /* READ */ {
2983 		sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2984 		    MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
2985 		    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2986 		_base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
2987 		    data_in_dma);
2988 	}
2989 }
2990 
2991 #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
2992 
2993 /**
2994  * _base_config_dma_addressing - set dma addressing
2995  * @ioc: per adapter object
2996  * @pdev: PCI device struct
2997  *
2998  * Return: 0 for success, non-zero for failure.
2999  */
3000 static int
3001 _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
3002 {
3003 	struct sysinfo s;
3004 
3005 	if (ioc->is_mcpu_endpoint ||
3006 	    sizeof(dma_addr_t) == 4 || ioc->use_32bit_dma ||
3007 	    dma_get_required_mask(&pdev->dev) <= 32)
3008 		ioc->dma_mask = 32;
3009 	/* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */
3010 	else if (ioc->hba_mpi_version_belonged > MPI2_VERSION)
3011 		ioc->dma_mask = 63;
3012 	else
3013 		ioc->dma_mask = 64;
3014 
3015 	if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(ioc->dma_mask)) ||
3016 	    dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(ioc->dma_mask)))
3017 		return -ENODEV;
3018 
3019 	if (ioc->dma_mask > 32) {
3020 		ioc->base_add_sg_single = &_base_add_sg_single_64;
3021 		ioc->sge_size = sizeof(Mpi2SGESimple64_t);
3022 	} else {
3023 		ioc->base_add_sg_single = &_base_add_sg_single_32;
3024 		ioc->sge_size = sizeof(Mpi2SGESimple32_t);
3025 	}
3026 
3027 	si_meminfo(&s);
3028 	ioc_info(ioc, "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
3029 		ioc->dma_mask, convert_to_kb(s.totalram));
3030 
3031 	return 0;
3032 }
3033 
3034 /**
3035  * _base_check_enable_msix - checks MSIX capabable.
3036  * @ioc: per adapter object
3037  *
3038  * Check to see if card is capable of MSIX, and set number
3039  * of available msix vectors
3040  */
3041 static int
3042 _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)
3043 {
3044 	int base;
3045 	u16 message_control;
3046 
3047 	/* Check whether controller SAS2008 B0 controller,
3048 	 * if it is SAS2008 B0 controller use IO-APIC instead of MSIX
3049 	 */
3050 	if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 &&
3051 	    ioc->pdev->revision == SAS2_PCI_DEVICE_B0_REVISION) {
3052 		return -EINVAL;
3053 	}
3054 
3055 	base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
3056 	if (!base) {
3057 		dfailprintk(ioc, ioc_info(ioc, "msix not supported\n"));
3058 		return -EINVAL;
3059 	}
3060 
3061 	/* get msix vector count */
3062 	/* NUMA_IO not supported for older controllers */
3063 	if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 ||
3064 	    ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 ||
3065 	    ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 ||
3066 	    ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 ||
3067 	    ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 ||
3068 	    ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 ||
3069 	    ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2)
3070 		ioc->msix_vector_count = 1;
3071 	else {
3072 		pci_read_config_word(ioc->pdev, base + 2, &message_control);
3073 		ioc->msix_vector_count = (message_control & 0x3FF) + 1;
3074 	}
3075 	dinitprintk(ioc, ioc_info(ioc, "msix is supported, vector_count(%d)\n",
3076 				  ioc->msix_vector_count));
3077 	return 0;
3078 }
3079 
3080 /**
3081  * mpt3sas_base_free_irq - free irq
3082  * @ioc: per adapter object
3083  *
3084  * Freeing respective reply_queue from the list.
3085  */
3086 void
3087 mpt3sas_base_free_irq(struct MPT3SAS_ADAPTER *ioc)
3088 {
3089 	struct adapter_reply_queue *reply_q, *next;
3090 
3091 	if (list_empty(&ioc->reply_queue_list))
3092 		return;
3093 
3094 	list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
3095 		list_del(&reply_q->list);
3096 		if (reply_q->is_iouring_poll_q) {
3097 			kfree(reply_q);
3098 			continue;
3099 		}
3100 
3101 		if (ioc->smp_affinity_enable)
3102 			irq_set_affinity_hint(pci_irq_vector(ioc->pdev,
3103 			    reply_q->msix_index), NULL);
3104 		free_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index),
3105 			 reply_q);
3106 		kfree(reply_q);
3107 	}
3108 }
3109 
3110 /**
3111  * _base_request_irq - request irq
3112  * @ioc: per adapter object
3113  * @index: msix index into vector table
3114  *
3115  * Inserting respective reply_queue into the list.
3116  */
3117 static int
3118 _base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index)
3119 {
3120 	struct pci_dev *pdev = ioc->pdev;
3121 	struct adapter_reply_queue *reply_q;
3122 	int r, qid;
3123 
3124 	reply_q =  kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL);
3125 	if (!reply_q) {
3126 		ioc_err(ioc, "unable to allocate memory %zu!\n",
3127 			sizeof(struct adapter_reply_queue));
3128 		return -ENOMEM;
3129 	}
3130 	reply_q->ioc = ioc;
3131 	reply_q->msix_index = index;
3132 
3133 	atomic_set(&reply_q->busy, 0);
3134 
3135 	if (index >= ioc->iopoll_q_start_index) {
3136 		qid = index - ioc->iopoll_q_start_index;
3137 		snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-mq-poll%d",
3138 		    ioc->driver_name, ioc->id, qid);
3139 		reply_q->is_iouring_poll_q = 1;
3140 		ioc->io_uring_poll_queues[qid].reply_q = reply_q;
3141 		goto out;
3142 	}
3143 
3144 
3145 	if (ioc->msix_enable)
3146 		snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d",
3147 		    ioc->driver_name, ioc->id, index);
3148 	else
3149 		snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d",
3150 		    ioc->driver_name, ioc->id);
3151 	r = request_irq(pci_irq_vector(pdev, index), _base_interrupt,
3152 			IRQF_SHARED, reply_q->name, reply_q);
3153 	if (r) {
3154 		pr_err("%s: unable to allocate interrupt %d!\n",
3155 		       reply_q->name, pci_irq_vector(pdev, index));
3156 		kfree(reply_q);
3157 		return -EBUSY;
3158 	}
3159 out:
3160 	INIT_LIST_HEAD(&reply_q->list);
3161 	list_add_tail(&reply_q->list, &ioc->reply_queue_list);
3162 	return 0;
3163 }
3164 
3165 /**
3166  * _base_assign_reply_queues - assigning msix index for each cpu
3167  * @ioc: per adapter object
3168  *
3169  * The enduser would need to set the affinity via /proc/irq/#/smp_affinity
3170  *
3171  * It would nice if we could call irq_set_affinity, however it is not
3172  * an exported symbol
3173  */
3174 static void
3175 _base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc)
3176 {
3177 	unsigned int cpu, nr_cpus, nr_msix, index = 0;
3178 	struct adapter_reply_queue *reply_q;
3179 	int local_numa_node;
3180 	int iopoll_q_count = ioc->reply_queue_count -
3181 	    ioc->iopoll_q_start_index;
3182 
3183 	if (!_base_is_controller_msix_enabled(ioc))
3184 		return;
3185 
3186 	if (ioc->msix_load_balance)
3187 		return;
3188 
3189 	memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz);
3190 
3191 	nr_cpus = num_online_cpus();
3192 	nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count,
3193 					       ioc->facts.MaxMSIxVectors);
3194 	if (!nr_msix)
3195 		return;
3196 
3197 	if (ioc->smp_affinity_enable) {
3198 
3199 		/*
3200 		 * set irq affinity to local numa node for those irqs
3201 		 * corresponding to high iops queues.
3202 		 */
3203 		if (ioc->high_iops_queues) {
3204 			local_numa_node = dev_to_node(&ioc->pdev->dev);
3205 			for (index = 0; index < ioc->high_iops_queues;
3206 			    index++) {
3207 				irq_set_affinity_hint(pci_irq_vector(ioc->pdev,
3208 				    index), cpumask_of_node(local_numa_node));
3209 			}
3210 		}
3211 
3212 		list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
3213 			const cpumask_t *mask;
3214 
3215 			if (reply_q->msix_index < ioc->high_iops_queues ||
3216 			    reply_q->msix_index >= ioc->iopoll_q_start_index)
3217 				continue;
3218 
3219 			mask = pci_irq_get_affinity(ioc->pdev,
3220 			    reply_q->msix_index);
3221 			if (!mask) {
3222 				ioc_warn(ioc, "no affinity for msi %x\n",
3223 					 reply_q->msix_index);
3224 				goto fall_back;
3225 			}
3226 
3227 			for_each_cpu_and(cpu, mask, cpu_online_mask) {
3228 				if (cpu >= ioc->cpu_msix_table_sz)
3229 					break;
3230 				ioc->cpu_msix_table[cpu] = reply_q->msix_index;
3231 			}
3232 		}
3233 		return;
3234 	}
3235 
3236 fall_back:
3237 	cpu = cpumask_first(cpu_online_mask);
3238 	nr_msix -= (ioc->high_iops_queues - iopoll_q_count);
3239 	index = 0;
3240 
3241 	list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
3242 		unsigned int i, group = nr_cpus / nr_msix;
3243 
3244 		if (reply_q->msix_index < ioc->high_iops_queues ||
3245 		    reply_q->msix_index >= ioc->iopoll_q_start_index)
3246 			continue;
3247 
3248 		if (cpu >= nr_cpus)
3249 			break;
3250 
3251 		if (index < nr_cpus % nr_msix)
3252 			group++;
3253 
3254 		for (i = 0 ; i < group ; i++) {
3255 			ioc->cpu_msix_table[cpu] = reply_q->msix_index;
3256 			cpu = cpumask_next(cpu, cpu_online_mask);
3257 		}
3258 		index++;
3259 	}
3260 }
3261 
3262 /**
3263  * _base_check_and_enable_high_iops_queues - enable high iops mode
3264  * @ioc: per adapter object
3265  * @hba_msix_vector_count: msix vectors supported by HBA
3266  *
3267  * Enable high iops queues only if
3268  *  - HBA is a SEA/AERO controller and
3269  *  - MSI-Xs vector supported by the HBA is 128 and
3270  *  - total CPU count in the system >=16 and
3271  *  - loaded driver with default max_msix_vectors module parameter and
3272  *  - system booted in non kdump mode
3273  *
3274  * Return: nothing.
3275  */
3276 static void
3277 _base_check_and_enable_high_iops_queues(struct MPT3SAS_ADAPTER *ioc,
3278 		int hba_msix_vector_count)
3279 {
3280 	u16 lnksta, speed;
3281 
3282 	/*
3283 	 * Disable high iops queues if io uring poll queues are enabled.
3284 	 */
3285 	if (perf_mode == MPT_PERF_MODE_IOPS ||
3286 	    perf_mode == MPT_PERF_MODE_LATENCY ||
3287 	    ioc->io_uring_poll_queues) {
3288 		ioc->high_iops_queues = 0;
3289 		return;
3290 	}
3291 
3292 	if (perf_mode == MPT_PERF_MODE_DEFAULT) {
3293 
3294 		pcie_capability_read_word(ioc->pdev, PCI_EXP_LNKSTA, &lnksta);
3295 		speed = lnksta & PCI_EXP_LNKSTA_CLS;
3296 
3297 		if (speed < 0x4) {
3298 			ioc->high_iops_queues = 0;
3299 			return;
3300 		}
3301 	}
3302 
3303 	if (!reset_devices && ioc->is_aero_ioc &&
3304 	    hba_msix_vector_count == MPT3SAS_GEN35_MAX_MSIX_QUEUES &&
3305 	    num_online_cpus() >= MPT3SAS_HIGH_IOPS_REPLY_QUEUES &&
3306 	    max_msix_vectors == -1)
3307 		ioc->high_iops_queues = MPT3SAS_HIGH_IOPS_REPLY_QUEUES;
3308 	else
3309 		ioc->high_iops_queues = 0;
3310 }
3311 
3312 /**
3313  * mpt3sas_base_disable_msix - disables msix
3314  * @ioc: per adapter object
3315  *
3316  */
3317 void
3318 mpt3sas_base_disable_msix(struct MPT3SAS_ADAPTER *ioc)
3319 {
3320 	if (!ioc->msix_enable)
3321 		return;
3322 	pci_free_irq_vectors(ioc->pdev);
3323 	ioc->msix_enable = 0;
3324 	kfree(ioc->io_uring_poll_queues);
3325 }
3326 
3327 /**
3328  * _base_alloc_irq_vectors - allocate msix vectors
3329  * @ioc: per adapter object
3330  *
3331  */
3332 static int
3333 _base_alloc_irq_vectors(struct MPT3SAS_ADAPTER *ioc)
3334 {
3335 	int i, irq_flags = PCI_IRQ_MSIX;
3336 	struct irq_affinity desc = { .pre_vectors = ioc->high_iops_queues };
3337 	struct irq_affinity *descp = &desc;
3338 	/*
3339 	 * Don't allocate msix vectors for poll_queues.
3340 	 * msix_vectors is always within a range of FW supported reply queue.
3341 	 */
3342 	int nr_msix_vectors = ioc->iopoll_q_start_index;
3343 
3344 
3345 	if (ioc->smp_affinity_enable)
3346 		irq_flags |= PCI_IRQ_AFFINITY | PCI_IRQ_ALL_TYPES;
3347 	else
3348 		descp = NULL;
3349 
3350 	ioc_info(ioc, " %d %d %d\n", ioc->high_iops_queues,
3351 	    ioc->reply_queue_count, nr_msix_vectors);
3352 
3353 	i = pci_alloc_irq_vectors_affinity(ioc->pdev,
3354 	    ioc->high_iops_queues,
3355 	    nr_msix_vectors, irq_flags, descp);
3356 
3357 	return i;
3358 }
3359 
3360 /**
3361  * _base_enable_msix - enables msix, failback to io_apic
3362  * @ioc: per adapter object
3363  *
3364  */
3365 static int
3366 _base_enable_msix(struct MPT3SAS_ADAPTER *ioc)
3367 {
3368 	int r;
3369 	int i, local_max_msix_vectors;
3370 	u8 try_msix = 0;
3371 	int iopoll_q_count = 0;
3372 
3373 	ioc->msix_load_balance = false;
3374 
3375 	if (msix_disable == -1 || msix_disable == 0)
3376 		try_msix = 1;
3377 
3378 	if (!try_msix)
3379 		goto try_ioapic;
3380 
3381 	if (_base_check_enable_msix(ioc) != 0)
3382 		goto try_ioapic;
3383 
3384 	ioc_info(ioc, "MSI-X vectors supported: %d\n", ioc->msix_vector_count);
3385 	pr_info("\t no of cores: %d, max_msix_vectors: %d\n",
3386 		ioc->cpu_count, max_msix_vectors);
3387 
3388 	ioc->reply_queue_count =
3389 		min_t(int, ioc->cpu_count, ioc->msix_vector_count);
3390 
3391 	if (!ioc->rdpq_array_enable && max_msix_vectors == -1)
3392 		local_max_msix_vectors = (reset_devices) ? 1 : 8;
3393 	else
3394 		local_max_msix_vectors = max_msix_vectors;
3395 
3396 	if (local_max_msix_vectors == 0)
3397 		goto try_ioapic;
3398 
3399 	/*
3400 	 * Enable msix_load_balance only if combined reply queue mode is
3401 	 * disabled on SAS3 & above generation HBA devices.
3402 	 */
3403 	if (!ioc->combined_reply_queue &&
3404 	    ioc->hba_mpi_version_belonged != MPI2_VERSION) {
3405 		ioc_info(ioc,
3406 		    "combined ReplyQueue is off, Enabling msix load balance\n");
3407 		ioc->msix_load_balance = true;
3408 	}
3409 
3410 	/*
3411 	 * smp affinity setting is not need when msix load balance
3412 	 * is enabled.
3413 	 */
3414 	if (ioc->msix_load_balance)
3415 		ioc->smp_affinity_enable = 0;
3416 
3417 	if (!ioc->smp_affinity_enable || ioc->reply_queue_count <= 1)
3418 		ioc->shost->host_tagset = 0;
3419 
3420 	/*
3421 	 * Enable io uring poll queues only if host_tagset is enabled.
3422 	 */
3423 	if (ioc->shost->host_tagset)
3424 		iopoll_q_count = poll_queues;
3425 
3426 	if (iopoll_q_count) {
3427 		ioc->io_uring_poll_queues = kcalloc(iopoll_q_count,
3428 		    sizeof(struct io_uring_poll_queue), GFP_KERNEL);
3429 		if (!ioc->io_uring_poll_queues)
3430 			iopoll_q_count = 0;
3431 	}
3432 
3433 	if (ioc->is_aero_ioc)
3434 		_base_check_and_enable_high_iops_queues(ioc,
3435 		    ioc->msix_vector_count);
3436 
3437 	/*
3438 	 * Add high iops queues count to reply queue count if high iops queues
3439 	 * are enabled.
3440 	 */
3441 	ioc->reply_queue_count = min_t(int,
3442 	    ioc->reply_queue_count + ioc->high_iops_queues,
3443 	    ioc->msix_vector_count);
3444 
3445 	/*
3446 	 * Adjust the reply queue count incase reply queue count
3447 	 * exceeds the user provided MSIx vectors count.
3448 	 */
3449 	if (local_max_msix_vectors > 0)
3450 		ioc->reply_queue_count = min_t(int, local_max_msix_vectors,
3451 		    ioc->reply_queue_count);
3452 	/*
3453 	 * Add io uring poll queues count to reply queues count
3454 	 * if io uring is enabled in driver.
3455 	 */
3456 	if (iopoll_q_count) {
3457 		if (ioc->reply_queue_count < (iopoll_q_count + MPT3_MIN_IRQS))
3458 			iopoll_q_count = 0;
3459 		ioc->reply_queue_count = min_t(int,
3460 		    ioc->reply_queue_count + iopoll_q_count,
3461 		    ioc->msix_vector_count);
3462 	}
3463 
3464 	/*
3465 	 * Starting index of io uring poll queues in reply queue list.
3466 	 */
3467 	ioc->iopoll_q_start_index =
3468 	    ioc->reply_queue_count - iopoll_q_count;
3469 
3470 	r = _base_alloc_irq_vectors(ioc);
3471 	if (r < 0) {
3472 		ioc_info(ioc, "pci_alloc_irq_vectors failed (r=%d) !!!\n", r);
3473 		goto try_ioapic;
3474 	}
3475 
3476 	/*
3477 	 * Adjust the reply queue count if the allocated
3478 	 * MSIx vectors is less then the requested number
3479 	 * of MSIx vectors.
3480 	 */
3481 	if (r < ioc->iopoll_q_start_index) {
3482 		ioc->reply_queue_count = r + iopoll_q_count;
3483 		ioc->iopoll_q_start_index =
3484 		    ioc->reply_queue_count - iopoll_q_count;
3485 	}
3486 
3487 	ioc->msix_enable = 1;
3488 	for (i = 0; i < ioc->reply_queue_count; i++) {
3489 		r = _base_request_irq(ioc, i);
3490 		if (r) {
3491 			mpt3sas_base_free_irq(ioc);
3492 			mpt3sas_base_disable_msix(ioc);
3493 			goto try_ioapic;
3494 		}
3495 	}
3496 
3497 	ioc_info(ioc, "High IOPs queues : %s\n",
3498 			ioc->high_iops_queues ? "enabled" : "disabled");
3499 
3500 	return 0;
3501 
3502 /* failback to io_apic interrupt routing */
3503  try_ioapic:
3504 	ioc->high_iops_queues = 0;
3505 	ioc_info(ioc, "High IOPs queues : disabled\n");
3506 	ioc->reply_queue_count = 1;
3507 	ioc->iopoll_q_start_index = ioc->reply_queue_count - 0;
3508 	r = pci_alloc_irq_vectors(ioc->pdev, 1, 1, PCI_IRQ_LEGACY);
3509 	if (r < 0) {
3510 		dfailprintk(ioc,
3511 			    ioc_info(ioc, "pci_alloc_irq_vector(legacy) failed (r=%d) !!!\n",
3512 				     r));
3513 	} else
3514 		r = _base_request_irq(ioc, 0);
3515 
3516 	return r;
3517 }
3518 
3519 /**
3520  * mpt3sas_base_unmap_resources - free controller resources
3521  * @ioc: per adapter object
3522  */
3523 static void
3524 mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc)
3525 {
3526 	struct pci_dev *pdev = ioc->pdev;
3527 
3528 	dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
3529 
3530 	mpt3sas_base_free_irq(ioc);
3531 	mpt3sas_base_disable_msix(ioc);
3532 
3533 	kfree(ioc->replyPostRegisterIndex);
3534 	ioc->replyPostRegisterIndex = NULL;
3535 
3536 
3537 	if (ioc->chip_phys) {
3538 		iounmap(ioc->chip);
3539 		ioc->chip_phys = 0;
3540 	}
3541 
3542 	if (pci_is_enabled(pdev)) {
3543 		pci_release_selected_regions(ioc->pdev, ioc->bars);
3544 		pci_disable_pcie_error_reporting(pdev);
3545 		pci_disable_device(pdev);
3546 	}
3547 }
3548 
3549 static int
3550 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc);
3551 
3552 /**
3553  * mpt3sas_base_check_for_fault_and_issue_reset - check if IOC is in fault state
3554  *     and if it is in fault state then issue diag reset.
3555  * @ioc: per adapter object
3556  *
3557  * Return: 0 for success, non-zero for failure.
3558  */
3559 int
3560 mpt3sas_base_check_for_fault_and_issue_reset(struct MPT3SAS_ADAPTER *ioc)
3561 {
3562 	u32 ioc_state;
3563 	int rc = -EFAULT;
3564 
3565 	dinitprintk(ioc, pr_info("%s\n", __func__));
3566 	if (ioc->pci_error_recovery)
3567 		return 0;
3568 	ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
3569 	dhsprintk(ioc, pr_info("%s: ioc_state(0x%08x)\n", __func__, ioc_state));
3570 
3571 	if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
3572 		mpt3sas_print_fault_code(ioc, ioc_state &
3573 		    MPI2_DOORBELL_DATA_MASK);
3574 		mpt3sas_base_mask_interrupts(ioc);
3575 		rc = _base_diag_reset(ioc);
3576 	} else if ((ioc_state & MPI2_IOC_STATE_MASK) ==
3577 	    MPI2_IOC_STATE_COREDUMP) {
3578 		mpt3sas_print_coredump_info(ioc, ioc_state &
3579 		     MPI2_DOORBELL_DATA_MASK);
3580 		mpt3sas_base_wait_for_coredump_completion(ioc, __func__);
3581 		mpt3sas_base_mask_interrupts(ioc);
3582 		rc = _base_diag_reset(ioc);
3583 	}
3584 
3585 	return rc;
3586 }
3587 
3588 /**
3589  * mpt3sas_base_map_resources - map in controller resources (io/irq/memap)
3590  * @ioc: per adapter object
3591  *
3592  * Return: 0 for success, non-zero for failure.
3593  */
3594 int
3595 mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
3596 {
3597 	struct pci_dev *pdev = ioc->pdev;
3598 	u32 memap_sz;
3599 	u32 pio_sz;
3600 	int i, r = 0, rc;
3601 	u64 pio_chip = 0;
3602 	phys_addr_t chip_phys = 0;
3603 	struct adapter_reply_queue *reply_q;
3604 	int iopoll_q_count = 0;
3605 
3606 	dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
3607 
3608 	ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
3609 	if (pci_enable_device_mem(pdev)) {
3610 		ioc_warn(ioc, "pci_enable_device_mem: failed\n");
3611 		ioc->bars = 0;
3612 		return -ENODEV;
3613 	}
3614 
3615 
3616 	if (pci_request_selected_regions(pdev, ioc->bars,
3617 	    ioc->driver_name)) {
3618 		ioc_warn(ioc, "pci_request_selected_regions: failed\n");
3619 		ioc->bars = 0;
3620 		r = -ENODEV;
3621 		goto out_fail;
3622 	}
3623 
3624 /* AER (Advanced Error Reporting) hooks */
3625 	pci_enable_pcie_error_reporting(pdev);
3626 
3627 	pci_set_master(pdev);
3628 
3629 
3630 	if (_base_config_dma_addressing(ioc, pdev) != 0) {
3631 		ioc_warn(ioc, "no suitable DMA mask for %s\n", pci_name(pdev));
3632 		r = -ENODEV;
3633 		goto out_fail;
3634 	}
3635 
3636 	for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) &&
3637 	     (!memap_sz || !pio_sz); i++) {
3638 		if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
3639 			if (pio_sz)
3640 				continue;
3641 			pio_chip = (u64)pci_resource_start(pdev, i);
3642 			pio_sz = pci_resource_len(pdev, i);
3643 		} else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3644 			if (memap_sz)
3645 				continue;
3646 			ioc->chip_phys = pci_resource_start(pdev, i);
3647 			chip_phys = ioc->chip_phys;
3648 			memap_sz = pci_resource_len(pdev, i);
3649 			ioc->chip = ioremap(ioc->chip_phys, memap_sz);
3650 		}
3651 	}
3652 
3653 	if (ioc->chip == NULL) {
3654 		ioc_err(ioc,
3655 		    "unable to map adapter memory! or resource not found\n");
3656 		r = -EINVAL;
3657 		goto out_fail;
3658 	}
3659 
3660 	mpt3sas_base_mask_interrupts(ioc);
3661 
3662 	r = _base_get_ioc_facts(ioc);
3663 	if (r) {
3664 		rc = mpt3sas_base_check_for_fault_and_issue_reset(ioc);
3665 		if (rc || (_base_get_ioc_facts(ioc)))
3666 			goto out_fail;
3667 	}
3668 
3669 	if (!ioc->rdpq_array_enable_assigned) {
3670 		ioc->rdpq_array_enable = ioc->rdpq_array_capable;
3671 		ioc->rdpq_array_enable_assigned = 1;
3672 	}
3673 
3674 	r = _base_enable_msix(ioc);
3675 	if (r)
3676 		goto out_fail;
3677 
3678 	iopoll_q_count = ioc->reply_queue_count - ioc->iopoll_q_start_index;
3679 	for (i = 0; i < iopoll_q_count; i++) {
3680 		atomic_set(&ioc->io_uring_poll_queues[i].busy, 0);
3681 		atomic_set(&ioc->io_uring_poll_queues[i].pause, 0);
3682 	}
3683 
3684 	if (!ioc->is_driver_loading)
3685 		_base_init_irqpolls(ioc);
3686 	/* Use the Combined reply queue feature only for SAS3 C0 & higher
3687 	 * revision HBAs and also only when reply queue count is greater than 8
3688 	 */
3689 	if (ioc->combined_reply_queue) {
3690 		/* Determine the Supplemental Reply Post Host Index Registers
3691 		 * Addresse. Supplemental Reply Post Host Index Registers
3692 		 * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and
3693 		 * each register is at offset bytes of
3694 		 * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one.
3695 		 */
3696 		ioc->replyPostRegisterIndex = kcalloc(
3697 		     ioc->combined_reply_index_count,
3698 		     sizeof(resource_size_t *), GFP_KERNEL);
3699 		if (!ioc->replyPostRegisterIndex) {
3700 			ioc_err(ioc,
3701 			    "allocation for replyPostRegisterIndex failed!\n");
3702 			r = -ENOMEM;
3703 			goto out_fail;
3704 		}
3705 
3706 		for (i = 0; i < ioc->combined_reply_index_count; i++) {
3707 			ioc->replyPostRegisterIndex[i] = (resource_size_t *)
3708 			     ((u8 __force *)&ioc->chip->Doorbell +
3709 			     MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET +
3710 			     (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET));
3711 		}
3712 	}
3713 
3714 	if (ioc->is_warpdrive) {
3715 		ioc->reply_post_host_index[0] = (resource_size_t __iomem *)
3716 		    &ioc->chip->ReplyPostHostIndex;
3717 
3718 		for (i = 1; i < ioc->cpu_msix_table_sz; i++)
3719 			ioc->reply_post_host_index[i] =
3720 			(resource_size_t __iomem *)
3721 			((u8 __iomem *)&ioc->chip->Doorbell + (0x4000 + ((i - 1)
3722 			* 4)));
3723 	}
3724 
3725 	list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
3726 		if (reply_q->msix_index >= ioc->iopoll_q_start_index) {
3727 			pr_info("%s: enabled: index: %d\n",
3728 			    reply_q->name, reply_q->msix_index);
3729 			continue;
3730 		}
3731 
3732 		pr_info("%s: %s enabled: IRQ %d\n",
3733 			reply_q->name,
3734 			ioc->msix_enable ? "PCI-MSI-X" : "IO-APIC",
3735 			pci_irq_vector(ioc->pdev, reply_q->msix_index));
3736 	}
3737 
3738 	ioc_info(ioc, "iomem(%pap), mapped(0x%p), size(%d)\n",
3739 		 &chip_phys, ioc->chip, memap_sz);
3740 	ioc_info(ioc, "ioport(0x%016llx), size(%d)\n",
3741 		 (unsigned long long)pio_chip, pio_sz);
3742 
3743 	/* Save PCI configuration state for recovery from PCI AER/EEH errors */
3744 	pci_save_state(pdev);
3745 	return 0;
3746 
3747  out_fail:
3748 	mpt3sas_base_unmap_resources(ioc);
3749 	return r;
3750 }
3751 
3752 /**
3753  * mpt3sas_base_get_msg_frame - obtain request mf pointer
3754  * @ioc: per adapter object
3755  * @smid: system request message index(smid zero is invalid)
3756  *
3757  * Return: virt pointer to message frame.
3758  */
3759 void *
3760 mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3761 {
3762 	return (void *)(ioc->request + (smid * ioc->request_sz));
3763 }
3764 
3765 /**
3766  * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr
3767  * @ioc: per adapter object
3768  * @smid: system request message index
3769  *
3770  * Return: virt pointer to sense buffer.
3771  */
3772 void *
3773 mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3774 {
3775 	return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
3776 }
3777 
3778 /**
3779  * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr
3780  * @ioc: per adapter object
3781  * @smid: system request message index
3782  *
3783  * Return: phys pointer to the low 32bit address of the sense buffer.
3784  */
3785 __le32
3786 mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3787 {
3788 	return cpu_to_le32(ioc->sense_dma + ((smid - 1) *
3789 	    SCSI_SENSE_BUFFERSIZE));
3790 }
3791 
3792 /**
3793  * mpt3sas_base_get_pcie_sgl - obtain a PCIe SGL virt addr
3794  * @ioc: per adapter object
3795  * @smid: system request message index
3796  *
3797  * Return: virt pointer to a PCIe SGL.
3798  */
3799 void *
3800 mpt3sas_base_get_pcie_sgl(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3801 {
3802 	return (void *)(ioc->pcie_sg_lookup[smid - 1].pcie_sgl);
3803 }
3804 
3805 /**
3806  * mpt3sas_base_get_pcie_sgl_dma - obtain a PCIe SGL dma addr
3807  * @ioc: per adapter object
3808  * @smid: system request message index
3809  *
3810  * Return: phys pointer to the address of the PCIe buffer.
3811  */
3812 dma_addr_t
3813 mpt3sas_base_get_pcie_sgl_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3814 {
3815 	return ioc->pcie_sg_lookup[smid - 1].pcie_sgl_dma;
3816 }
3817 
3818 /**
3819  * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address
3820  * @ioc: per adapter object
3821  * @phys_addr: lower 32 physical addr of the reply
3822  *
3823  * Converts 32bit lower physical addr into a virt address.
3824  */
3825 void *
3826 mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr)
3827 {
3828 	if (!phys_addr)
3829 		return NULL;
3830 	return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
3831 }
3832 
3833 /**
3834  * _base_get_msix_index - get the msix index
3835  * @ioc: per adapter object
3836  * @scmd: scsi_cmnd object
3837  *
3838  * Return: msix index of general reply queues,
3839  * i.e. reply queue on which IO request's reply
3840  * should be posted by the HBA firmware.
3841  */
3842 static inline u8
3843 _base_get_msix_index(struct MPT3SAS_ADAPTER *ioc,
3844 	struct scsi_cmnd *scmd)
3845 {
3846 	/* Enables reply_queue load balancing */
3847 	if (ioc->msix_load_balance)
3848 		return ioc->reply_queue_count ?
3849 		    base_mod64(atomic64_add_return(1,
3850 		    &ioc->total_io_cnt), ioc->reply_queue_count) : 0;
3851 
3852 	if (scmd && ioc->shost->nr_hw_queues > 1) {
3853 		u32 tag = blk_mq_unique_tag(scsi_cmd_to_rq(scmd));
3854 
3855 		return blk_mq_unique_tag_to_hwq(tag) +
3856 			ioc->high_iops_queues;
3857 	}
3858 
3859 	return ioc->cpu_msix_table[raw_smp_processor_id()];
3860 }
3861 
3862 /**
3863  * _base_get_high_iops_msix_index - get the msix index of
3864  *				high iops queues
3865  * @ioc: per adapter object
3866  * @scmd: scsi_cmnd object
3867  *
3868  * Return: msix index of high iops reply queues.
3869  * i.e. high iops reply queue on which IO request's
3870  * reply should be posted by the HBA firmware.
3871  */
3872 static inline u8
3873 _base_get_high_iops_msix_index(struct MPT3SAS_ADAPTER *ioc,
3874 	struct scsi_cmnd *scmd)
3875 {
3876 	/**
3877 	 * Round robin the IO interrupts among the high iops
3878 	 * reply queues in terms of batch count 16 when outstanding
3879 	 * IOs on the target device is >=8.
3880 	 */
3881 
3882 	if (scsi_device_busy(scmd->device) > MPT3SAS_DEVICE_HIGH_IOPS_DEPTH)
3883 		return base_mod64((
3884 		    atomic64_add_return(1, &ioc->high_iops_outstanding) /
3885 		    MPT3SAS_HIGH_IOPS_BATCH_COUNT),
3886 		    MPT3SAS_HIGH_IOPS_REPLY_QUEUES);
3887 
3888 	return _base_get_msix_index(ioc, scmd);
3889 }
3890 
3891 /**
3892  * mpt3sas_base_get_smid - obtain a free smid from internal queue
3893  * @ioc: per adapter object
3894  * @cb_idx: callback index
3895  *
3896  * Return: smid (zero is invalid)
3897  */
3898 u16
3899 mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
3900 {
3901 	unsigned long flags;
3902 	struct request_tracker *request;
3903 	u16 smid;
3904 
3905 	spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
3906 	if (list_empty(&ioc->internal_free_list)) {
3907 		spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3908 		ioc_err(ioc, "%s: smid not available\n", __func__);
3909 		return 0;
3910 	}
3911 
3912 	request = list_entry(ioc->internal_free_list.next,
3913 	    struct request_tracker, tracker_list);
3914 	request->cb_idx = cb_idx;
3915 	smid = request->smid;
3916 	list_del(&request->tracker_list);
3917 	spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3918 	return smid;
3919 }
3920 
3921 /**
3922  * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue
3923  * @ioc: per adapter object
3924  * @cb_idx: callback index
3925  * @scmd: pointer to scsi command object
3926  *
3927  * Return: smid (zero is invalid)
3928  */
3929 u16
3930 mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx,
3931 	struct scsi_cmnd *scmd)
3932 {
3933 	struct scsiio_tracker *request = scsi_cmd_priv(scmd);
3934 	u16 smid;
3935 	u32 tag, unique_tag;
3936 
3937 	unique_tag = blk_mq_unique_tag(scsi_cmd_to_rq(scmd));
3938 	tag = blk_mq_unique_tag_to_tag(unique_tag);
3939 
3940 	/*
3941 	 * Store hw queue number corresponding to the tag.
3942 	 * This hw queue number is used later to determine
3943 	 * the unique_tag using the logic below. This unique_tag
3944 	 * is used to retrieve the scmd pointer corresponding
3945 	 * to tag using scsi_host_find_tag() API.
3946 	 *
3947 	 * tag = smid - 1;
3948 	 * unique_tag = ioc->io_queue_num[tag] << BLK_MQ_UNIQUE_TAG_BITS | tag;
3949 	 */
3950 	ioc->io_queue_num[tag] = blk_mq_unique_tag_to_hwq(unique_tag);
3951 
3952 	smid = tag + 1;
3953 	request->cb_idx = cb_idx;
3954 	request->smid = smid;
3955 	request->scmd = scmd;
3956 	INIT_LIST_HEAD(&request->chain_list);
3957 	return smid;
3958 }
3959 
3960 /**
3961  * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue
3962  * @ioc: per adapter object
3963  * @cb_idx: callback index
3964  *
3965  * Return: smid (zero is invalid)
3966  */
3967 u16
3968 mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
3969 {
3970 	unsigned long flags;
3971 	struct request_tracker *request;
3972 	u16 smid;
3973 
3974 	spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
3975 	if (list_empty(&ioc->hpr_free_list)) {
3976 		spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3977 		return 0;
3978 	}
3979 
3980 	request = list_entry(ioc->hpr_free_list.next,
3981 	    struct request_tracker, tracker_list);
3982 	request->cb_idx = cb_idx;
3983 	smid = request->smid;
3984 	list_del(&request->tracker_list);
3985 	spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3986 	return smid;
3987 }
3988 
3989 static void
3990 _base_recovery_check(struct MPT3SAS_ADAPTER *ioc)
3991 {
3992 	/*
3993 	 * See _wait_for_commands_to_complete() call with regards to this code.
3994 	 */
3995 	if (ioc->shost_recovery && ioc->pending_io_count) {
3996 		ioc->pending_io_count = scsi_host_busy(ioc->shost);
3997 		if (ioc->pending_io_count == 0)
3998 			wake_up(&ioc->reset_wq);
3999 	}
4000 }
4001 
4002 void mpt3sas_base_clear_st(struct MPT3SAS_ADAPTER *ioc,
4003 			   struct scsiio_tracker *st)
4004 {
4005 	if (WARN_ON(st->smid == 0))
4006 		return;
4007 	st->cb_idx = 0xFF;
4008 	st->direct_io = 0;
4009 	st->scmd = NULL;
4010 	atomic_set(&ioc->chain_lookup[st->smid - 1].chain_offset, 0);
4011 	st->smid = 0;
4012 }
4013 
4014 /**
4015  * mpt3sas_base_free_smid - put smid back on free_list
4016  * @ioc: per adapter object
4017  * @smid: system request message index
4018  */
4019 void
4020 mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
4021 {
4022 	unsigned long flags;
4023 	int i;
4024 
4025 	if (smid < ioc->hi_priority_smid) {
4026 		struct scsiio_tracker *st;
4027 		void *request;
4028 
4029 		st = _get_st_from_smid(ioc, smid);
4030 		if (!st) {
4031 			_base_recovery_check(ioc);
4032 			return;
4033 		}
4034 
4035 		/* Clear MPI request frame */
4036 		request = mpt3sas_base_get_msg_frame(ioc, smid);
4037 		memset(request, 0, ioc->request_sz);
4038 
4039 		mpt3sas_base_clear_st(ioc, st);
4040 		_base_recovery_check(ioc);
4041 		ioc->io_queue_num[smid - 1] = 0;
4042 		return;
4043 	}
4044 
4045 	spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
4046 	if (smid < ioc->internal_smid) {
4047 		/* hi-priority */
4048 		i = smid - ioc->hi_priority_smid;
4049 		ioc->hpr_lookup[i].cb_idx = 0xFF;
4050 		list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list);
4051 	} else if (smid <= ioc->hba_queue_depth) {
4052 		/* internal queue */
4053 		i = smid - ioc->internal_smid;
4054 		ioc->internal_lookup[i].cb_idx = 0xFF;
4055 		list_add(&ioc->internal_lookup[i].tracker_list,
4056 		    &ioc->internal_free_list);
4057 	}
4058 	spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
4059 }
4060 
4061 /**
4062  * _base_mpi_ep_writeq - 32 bit write to MMIO
4063  * @b: data payload
4064  * @addr: address in MMIO space
4065  * @writeq_lock: spin lock
4066  *
4067  * This special handling for MPI EP to take care of 32 bit
4068  * environment where its not quarenteed to send the entire word
4069  * in one transfer.
4070  */
4071 static inline void
4072 _base_mpi_ep_writeq(__u64 b, volatile void __iomem *addr,
4073 					spinlock_t *writeq_lock)
4074 {
4075 	unsigned long flags;
4076 
4077 	spin_lock_irqsave(writeq_lock, flags);
4078 	__raw_writel((u32)(b), addr);
4079 	__raw_writel((u32)(b >> 32), (addr + 4));
4080 	spin_unlock_irqrestore(writeq_lock, flags);
4081 }
4082 
4083 /**
4084  * _base_writeq - 64 bit write to MMIO
4085  * @b: data payload
4086  * @addr: address in MMIO space
4087  * @writeq_lock: spin lock
4088  *
4089  * Glue for handling an atomic 64 bit word to MMIO. This special handling takes
4090  * care of 32 bit environment where its not quarenteed to send the entire word
4091  * in one transfer.
4092  */
4093 #if defined(writeq) && defined(CONFIG_64BIT)
4094 static inline void
4095 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
4096 {
4097 	wmb();
4098 	__raw_writeq(b, addr);
4099 	barrier();
4100 }
4101 #else
4102 static inline void
4103 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
4104 {
4105 	_base_mpi_ep_writeq(b, addr, writeq_lock);
4106 }
4107 #endif
4108 
4109 /**
4110  * _base_set_and_get_msix_index - get the msix index and assign to msix_io
4111  *                                variable of scsi tracker
4112  * @ioc: per adapter object
4113  * @smid: system request message index
4114  *
4115  * Return: msix index.
4116  */
4117 static u8
4118 _base_set_and_get_msix_index(struct MPT3SAS_ADAPTER *ioc, u16 smid)
4119 {
4120 	struct scsiio_tracker *st = NULL;
4121 
4122 	if (smid < ioc->hi_priority_smid)
4123 		st = _get_st_from_smid(ioc, smid);
4124 
4125 	if (st == NULL)
4126 		return  _base_get_msix_index(ioc, NULL);
4127 
4128 	st->msix_io = ioc->get_msix_index_for_smlio(ioc, st->scmd);
4129 	return st->msix_io;
4130 }
4131 
4132 /**
4133  * _base_put_smid_mpi_ep_scsi_io - send SCSI_IO request to firmware
4134  * @ioc: per adapter object
4135  * @smid: system request message index
4136  * @handle: device handle
4137  */
4138 static void
4139 _base_put_smid_mpi_ep_scsi_io(struct MPT3SAS_ADAPTER *ioc,
4140 	u16 smid, u16 handle)
4141 {
4142 	Mpi2RequestDescriptorUnion_t descriptor;
4143 	u64 *request = (u64 *)&descriptor;
4144 	void *mpi_req_iomem;
4145 	__le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid);
4146 
4147 	_clone_sg_entries(ioc, (void *) mfp, smid);
4148 	mpi_req_iomem = (void __force *)ioc->chip +
4149 			MPI_FRAME_START_OFFSET + (smid * ioc->request_sz);
4150 	_base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp,
4151 					ioc->request_sz);
4152 	descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
4153 	descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4154 	descriptor.SCSIIO.SMID = cpu_to_le16(smid);
4155 	descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
4156 	descriptor.SCSIIO.LMID = 0;
4157 	_base_mpi_ep_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
4158 	    &ioc->scsi_lookup_lock);
4159 }
4160 
4161 /**
4162  * _base_put_smid_scsi_io - send SCSI_IO request to firmware
4163  * @ioc: per adapter object
4164  * @smid: system request message index
4165  * @handle: device handle
4166  */
4167 static void
4168 _base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle)
4169 {
4170 	Mpi2RequestDescriptorUnion_t descriptor;
4171 	u64 *request = (u64 *)&descriptor;
4172 
4173 
4174 	descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
4175 	descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4176 	descriptor.SCSIIO.SMID = cpu_to_le16(smid);
4177 	descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
4178 	descriptor.SCSIIO.LMID = 0;
4179 	_base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
4180 	    &ioc->scsi_lookup_lock);
4181 }
4182 
4183 /**
4184  * _base_put_smid_fast_path - send fast path request to firmware
4185  * @ioc: per adapter object
4186  * @smid: system request message index
4187  * @handle: device handle
4188  */
4189 static void
4190 _base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid,
4191 	u16 handle)
4192 {
4193 	Mpi2RequestDescriptorUnion_t descriptor;
4194 	u64 *request = (u64 *)&descriptor;
4195 
4196 	descriptor.SCSIIO.RequestFlags =
4197 	    MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
4198 	descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4199 	descriptor.SCSIIO.SMID = cpu_to_le16(smid);
4200 	descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
4201 	descriptor.SCSIIO.LMID = 0;
4202 	_base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
4203 	    &ioc->scsi_lookup_lock);
4204 }
4205 
4206 /**
4207  * _base_put_smid_hi_priority - send Task Management request to firmware
4208  * @ioc: per adapter object
4209  * @smid: system request message index
4210  * @msix_task: msix_task will be same as msix of IO in case of task abort else 0
4211  */
4212 static void
4213 _base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid,
4214 	u16 msix_task)
4215 {
4216 	Mpi2RequestDescriptorUnion_t descriptor;
4217 	void *mpi_req_iomem;
4218 	u64 *request;
4219 
4220 	if (ioc->is_mcpu_endpoint) {
4221 		__le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid);
4222 
4223 		/* TBD 256 is offset within sys register. */
4224 		mpi_req_iomem = (void __force *)ioc->chip
4225 					+ MPI_FRAME_START_OFFSET
4226 					+ (smid * ioc->request_sz);
4227 		_base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp,
4228 							ioc->request_sz);
4229 	}
4230 
4231 	request = (u64 *)&descriptor;
4232 
4233 	descriptor.HighPriority.RequestFlags =
4234 	    MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
4235 	descriptor.HighPriority.MSIxIndex =  msix_task;
4236 	descriptor.HighPriority.SMID = cpu_to_le16(smid);
4237 	descriptor.HighPriority.LMID = 0;
4238 	descriptor.HighPriority.Reserved1 = 0;
4239 	if (ioc->is_mcpu_endpoint)
4240 		_base_mpi_ep_writeq(*request,
4241 				&ioc->chip->RequestDescriptorPostLow,
4242 				&ioc->scsi_lookup_lock);
4243 	else
4244 		_base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
4245 		    &ioc->scsi_lookup_lock);
4246 }
4247 
4248 /**
4249  * mpt3sas_base_put_smid_nvme_encap - send NVMe encapsulated request to
4250  *  firmware
4251  * @ioc: per adapter object
4252  * @smid: system request message index
4253  */
4254 void
4255 mpt3sas_base_put_smid_nvme_encap(struct MPT3SAS_ADAPTER *ioc, u16 smid)
4256 {
4257 	Mpi2RequestDescriptorUnion_t descriptor;
4258 	u64 *request = (u64 *)&descriptor;
4259 
4260 	descriptor.Default.RequestFlags =
4261 		MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED;
4262 	descriptor.Default.MSIxIndex =  _base_set_and_get_msix_index(ioc, smid);
4263 	descriptor.Default.SMID = cpu_to_le16(smid);
4264 	descriptor.Default.LMID = 0;
4265 	descriptor.Default.DescriptorTypeDependent = 0;
4266 	_base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
4267 	    &ioc->scsi_lookup_lock);
4268 }
4269 
4270 /**
4271  * _base_put_smid_default - Default, primarily used for config pages
4272  * @ioc: per adapter object
4273  * @smid: system request message index
4274  */
4275 static void
4276 _base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid)
4277 {
4278 	Mpi2RequestDescriptorUnion_t descriptor;
4279 	void *mpi_req_iomem;
4280 	u64 *request;
4281 
4282 	if (ioc->is_mcpu_endpoint) {
4283 		__le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid);
4284 
4285 		_clone_sg_entries(ioc, (void *) mfp, smid);
4286 		/* TBD 256 is offset within sys register */
4287 		mpi_req_iomem = (void __force *)ioc->chip +
4288 			MPI_FRAME_START_OFFSET + (smid * ioc->request_sz);
4289 		_base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp,
4290 							ioc->request_sz);
4291 	}
4292 	request = (u64 *)&descriptor;
4293 	descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
4294 	descriptor.Default.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4295 	descriptor.Default.SMID = cpu_to_le16(smid);
4296 	descriptor.Default.LMID = 0;
4297 	descriptor.Default.DescriptorTypeDependent = 0;
4298 	if (ioc->is_mcpu_endpoint)
4299 		_base_mpi_ep_writeq(*request,
4300 				&ioc->chip->RequestDescriptorPostLow,
4301 				&ioc->scsi_lookup_lock);
4302 	else
4303 		_base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
4304 				&ioc->scsi_lookup_lock);
4305 }
4306 
4307 /**
4308  * _base_put_smid_scsi_io_atomic - send SCSI_IO request to firmware using
4309  *   Atomic Request Descriptor
4310  * @ioc: per adapter object
4311  * @smid: system request message index
4312  * @handle: device handle, unused in this function, for function type match
4313  *
4314  * Return: nothing.
4315  */
4316 static void
4317 _base_put_smid_scsi_io_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
4318 	u16 handle)
4319 {
4320 	Mpi26AtomicRequestDescriptor_t descriptor;
4321 	u32 *request = (u32 *)&descriptor;
4322 
4323 	descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
4324 	descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4325 	descriptor.SMID = cpu_to_le16(smid);
4326 
4327 	writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
4328 }
4329 
4330 /**
4331  * _base_put_smid_fast_path_atomic - send fast path request to firmware
4332  * using Atomic Request Descriptor
4333  * @ioc: per adapter object
4334  * @smid: system request message index
4335  * @handle: device handle, unused in this function, for function type match
4336  * Return: nothing
4337  */
4338 static void
4339 _base_put_smid_fast_path_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
4340 	u16 handle)
4341 {
4342 	Mpi26AtomicRequestDescriptor_t descriptor;
4343 	u32 *request = (u32 *)&descriptor;
4344 
4345 	descriptor.RequestFlags = MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
4346 	descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4347 	descriptor.SMID = cpu_to_le16(smid);
4348 
4349 	writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
4350 }
4351 
4352 /**
4353  * _base_put_smid_hi_priority_atomic - send Task Management request to
4354  * firmware using Atomic Request Descriptor
4355  * @ioc: per adapter object
4356  * @smid: system request message index
4357  * @msix_task: msix_task will be same as msix of IO in case of task abort else 0
4358  *
4359  * Return: nothing.
4360  */
4361 static void
4362 _base_put_smid_hi_priority_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
4363 	u16 msix_task)
4364 {
4365 	Mpi26AtomicRequestDescriptor_t descriptor;
4366 	u32 *request = (u32 *)&descriptor;
4367 
4368 	descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
4369 	descriptor.MSIxIndex = msix_task;
4370 	descriptor.SMID = cpu_to_le16(smid);
4371 
4372 	writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
4373 }
4374 
4375 /**
4376  * _base_put_smid_default_atomic - Default, primarily used for config pages
4377  * use Atomic Request Descriptor
4378  * @ioc: per adapter object
4379  * @smid: system request message index
4380  *
4381  * Return: nothing.
4382  */
4383 static void
4384 _base_put_smid_default_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid)
4385 {
4386 	Mpi26AtomicRequestDescriptor_t descriptor;
4387 	u32 *request = (u32 *)&descriptor;
4388 
4389 	descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
4390 	descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4391 	descriptor.SMID = cpu_to_le16(smid);
4392 
4393 	writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
4394 }
4395 
4396 /**
4397  * _base_display_OEMs_branding - Display branding string
4398  * @ioc: per adapter object
4399  */
4400 static void
4401 _base_display_OEMs_branding(struct MPT3SAS_ADAPTER *ioc)
4402 {
4403 	if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL)
4404 		return;
4405 
4406 	switch (ioc->pdev->subsystem_vendor) {
4407 	case PCI_VENDOR_ID_INTEL:
4408 		switch (ioc->pdev->device) {
4409 		case MPI2_MFGPAGE_DEVID_SAS2008:
4410 			switch (ioc->pdev->subsystem_device) {
4411 			case MPT2SAS_INTEL_RMS2LL080_SSDID:
4412 				ioc_info(ioc, "%s\n",
4413 					 MPT2SAS_INTEL_RMS2LL080_BRANDING);
4414 				break;
4415 			case MPT2SAS_INTEL_RMS2LL040_SSDID:
4416 				ioc_info(ioc, "%s\n",
4417 					 MPT2SAS_INTEL_RMS2LL040_BRANDING);
4418 				break;
4419 			case MPT2SAS_INTEL_SSD910_SSDID:
4420 				ioc_info(ioc, "%s\n",
4421 					 MPT2SAS_INTEL_SSD910_BRANDING);
4422 				break;
4423 			default:
4424 				ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
4425 					 ioc->pdev->subsystem_device);
4426 				break;
4427 			}
4428 			break;
4429 		case MPI2_MFGPAGE_DEVID_SAS2308_2:
4430 			switch (ioc->pdev->subsystem_device) {
4431 			case MPT2SAS_INTEL_RS25GB008_SSDID:
4432 				ioc_info(ioc, "%s\n",
4433 					 MPT2SAS_INTEL_RS25GB008_BRANDING);
4434 				break;
4435 			case MPT2SAS_INTEL_RMS25JB080_SSDID:
4436 				ioc_info(ioc, "%s\n",
4437 					 MPT2SAS_INTEL_RMS25JB080_BRANDING);
4438 				break;
4439 			case MPT2SAS_INTEL_RMS25JB040_SSDID:
4440 				ioc_info(ioc, "%s\n",
4441 					 MPT2SAS_INTEL_RMS25JB040_BRANDING);
4442 				break;
4443 			case MPT2SAS_INTEL_RMS25KB080_SSDID:
4444 				ioc_info(ioc, "%s\n",
4445 					 MPT2SAS_INTEL_RMS25KB080_BRANDING);
4446 				break;
4447 			case MPT2SAS_INTEL_RMS25KB040_SSDID:
4448 				ioc_info(ioc, "%s\n",
4449 					 MPT2SAS_INTEL_RMS25KB040_BRANDING);
4450 				break;
4451 			case MPT2SAS_INTEL_RMS25LB040_SSDID:
4452 				ioc_info(ioc, "%s\n",
4453 					 MPT2SAS_INTEL_RMS25LB040_BRANDING);
4454 				break;
4455 			case MPT2SAS_INTEL_RMS25LB080_SSDID:
4456 				ioc_info(ioc, "%s\n",
4457 					 MPT2SAS_INTEL_RMS25LB080_BRANDING);
4458 				break;
4459 			default:
4460 				ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
4461 					 ioc->pdev->subsystem_device);
4462 				break;
4463 			}
4464 			break;
4465 		case MPI25_MFGPAGE_DEVID_SAS3008:
4466 			switch (ioc->pdev->subsystem_device) {
4467 			case MPT3SAS_INTEL_RMS3JC080_SSDID:
4468 				ioc_info(ioc, "%s\n",
4469 					 MPT3SAS_INTEL_RMS3JC080_BRANDING);
4470 				break;
4471 
4472 			case MPT3SAS_INTEL_RS3GC008_SSDID:
4473 				ioc_info(ioc, "%s\n",
4474 					 MPT3SAS_INTEL_RS3GC008_BRANDING);
4475 				break;
4476 			case MPT3SAS_INTEL_RS3FC044_SSDID:
4477 				ioc_info(ioc, "%s\n",
4478 					 MPT3SAS_INTEL_RS3FC044_BRANDING);
4479 				break;
4480 			case MPT3SAS_INTEL_RS3UC080_SSDID:
4481 				ioc_info(ioc, "%s\n",
4482 					 MPT3SAS_INTEL_RS3UC080_BRANDING);
4483 				break;
4484 			default:
4485 				ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
4486 					 ioc->pdev->subsystem_device);
4487 				break;
4488 			}
4489 			break;
4490 		default:
4491 			ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
4492 				 ioc->pdev->subsystem_device);
4493 			break;
4494 		}
4495 		break;
4496 	case PCI_VENDOR_ID_DELL:
4497 		switch (ioc->pdev->device) {
4498 		case MPI2_MFGPAGE_DEVID_SAS2008:
4499 			switch (ioc->pdev->subsystem_device) {
4500 			case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID:
4501 				ioc_info(ioc, "%s\n",
4502 					 MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING);
4503 				break;
4504 			case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID:
4505 				ioc_info(ioc, "%s\n",
4506 					 MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING);
4507 				break;
4508 			case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID:
4509 				ioc_info(ioc, "%s\n",
4510 					 MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING);
4511 				break;
4512 			case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID:
4513 				ioc_info(ioc, "%s\n",
4514 					 MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING);
4515 				break;
4516 			case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID:
4517 				ioc_info(ioc, "%s\n",
4518 					 MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING);
4519 				break;
4520 			case MPT2SAS_DELL_PERC_H200_SSDID:
4521 				ioc_info(ioc, "%s\n",
4522 					 MPT2SAS_DELL_PERC_H200_BRANDING);
4523 				break;
4524 			case MPT2SAS_DELL_6GBPS_SAS_SSDID:
4525 				ioc_info(ioc, "%s\n",
4526 					 MPT2SAS_DELL_6GBPS_SAS_BRANDING);
4527 				break;
4528 			default:
4529 				ioc_info(ioc, "Dell 6Gbps HBA: Subsystem ID: 0x%X\n",
4530 					 ioc->pdev->subsystem_device);
4531 				break;
4532 			}
4533 			break;
4534 		case MPI25_MFGPAGE_DEVID_SAS3008:
4535 			switch (ioc->pdev->subsystem_device) {
4536 			case MPT3SAS_DELL_12G_HBA_SSDID:
4537 				ioc_info(ioc, "%s\n",
4538 					 MPT3SAS_DELL_12G_HBA_BRANDING);
4539 				break;
4540 			default:
4541 				ioc_info(ioc, "Dell 12Gbps HBA: Subsystem ID: 0x%X\n",
4542 					 ioc->pdev->subsystem_device);
4543 				break;
4544 			}
4545 			break;
4546 		default:
4547 			ioc_info(ioc, "Dell HBA: Subsystem ID: 0x%X\n",
4548 				 ioc->pdev->subsystem_device);
4549 			break;
4550 		}
4551 		break;
4552 	case PCI_VENDOR_ID_CISCO:
4553 		switch (ioc->pdev->device) {
4554 		case MPI25_MFGPAGE_DEVID_SAS3008:
4555 			switch (ioc->pdev->subsystem_device) {
4556 			case MPT3SAS_CISCO_12G_8E_HBA_SSDID:
4557 				ioc_info(ioc, "%s\n",
4558 					 MPT3SAS_CISCO_12G_8E_HBA_BRANDING);
4559 				break;
4560 			case MPT3SAS_CISCO_12G_8I_HBA_SSDID:
4561 				ioc_info(ioc, "%s\n",
4562 					 MPT3SAS_CISCO_12G_8I_HBA_BRANDING);
4563 				break;
4564 			case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
4565 				ioc_info(ioc, "%s\n",
4566 					 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
4567 				break;
4568 			default:
4569 				ioc_info(ioc, "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
4570 					 ioc->pdev->subsystem_device);
4571 				break;
4572 			}
4573 			break;
4574 		case MPI25_MFGPAGE_DEVID_SAS3108_1:
4575 			switch (ioc->pdev->subsystem_device) {
4576 			case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
4577 				ioc_info(ioc, "%s\n",
4578 					 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
4579 				break;
4580 			case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID:
4581 				ioc_info(ioc, "%s\n",
4582 					 MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING);
4583 				break;
4584 			default:
4585 				ioc_info(ioc, "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
4586 					 ioc->pdev->subsystem_device);
4587 				break;
4588 			}
4589 			break;
4590 		default:
4591 			ioc_info(ioc, "Cisco SAS HBA: Subsystem ID: 0x%X\n",
4592 				 ioc->pdev->subsystem_device);
4593 			break;
4594 		}
4595 		break;
4596 	case MPT2SAS_HP_3PAR_SSVID:
4597 		switch (ioc->pdev->device) {
4598 		case MPI2_MFGPAGE_DEVID_SAS2004:
4599 			switch (ioc->pdev->subsystem_device) {
4600 			case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID:
4601 				ioc_info(ioc, "%s\n",
4602 					 MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING);
4603 				break;
4604 			default:
4605 				ioc_info(ioc, "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
4606 					 ioc->pdev->subsystem_device);
4607 				break;
4608 			}
4609 			break;
4610 		case MPI2_MFGPAGE_DEVID_SAS2308_2:
4611 			switch (ioc->pdev->subsystem_device) {
4612 			case MPT2SAS_HP_2_4_INTERNAL_SSDID:
4613 				ioc_info(ioc, "%s\n",
4614 					 MPT2SAS_HP_2_4_INTERNAL_BRANDING);
4615 				break;
4616 			case MPT2SAS_HP_2_4_EXTERNAL_SSDID:
4617 				ioc_info(ioc, "%s\n",
4618 					 MPT2SAS_HP_2_4_EXTERNAL_BRANDING);
4619 				break;
4620 			case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID:
4621 				ioc_info(ioc, "%s\n",
4622 					 MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING);
4623 				break;
4624 			case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID:
4625 				ioc_info(ioc, "%s\n",
4626 					 MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING);
4627 				break;
4628 			default:
4629 				ioc_info(ioc, "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
4630 					 ioc->pdev->subsystem_device);
4631 				break;
4632 			}
4633 			break;
4634 		default:
4635 			ioc_info(ioc, "HP SAS HBA: Subsystem ID: 0x%X\n",
4636 				 ioc->pdev->subsystem_device);
4637 			break;
4638 		}
4639 		break;
4640 	default:
4641 		break;
4642 	}
4643 }
4644 
4645 /**
4646  * _base_display_fwpkg_version - sends FWUpload request to pull FWPkg
4647  *				version from FW Image Header.
4648  * @ioc: per adapter object
4649  *
4650  * Return: 0 for success, non-zero for failure.
4651  */
4652 	static int
4653 _base_display_fwpkg_version(struct MPT3SAS_ADAPTER *ioc)
4654 {
4655 	Mpi2FWImageHeader_t *fw_img_hdr;
4656 	Mpi26ComponentImageHeader_t *cmp_img_hdr;
4657 	Mpi25FWUploadRequest_t *mpi_request;
4658 	Mpi2FWUploadReply_t mpi_reply;
4659 	int r = 0, issue_diag_reset = 0;
4660 	u32  package_version = 0;
4661 	void *fwpkg_data = NULL;
4662 	dma_addr_t fwpkg_data_dma;
4663 	u16 smid, ioc_status;
4664 	size_t data_length;
4665 
4666 	dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
4667 
4668 	if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
4669 		ioc_err(ioc, "%s: internal command already in use\n", __func__);
4670 		return -EAGAIN;
4671 	}
4672 
4673 	data_length = sizeof(Mpi2FWImageHeader_t);
4674 	fwpkg_data = dma_alloc_coherent(&ioc->pdev->dev, data_length,
4675 			&fwpkg_data_dma, GFP_KERNEL);
4676 	if (!fwpkg_data) {
4677 		ioc_err(ioc,
4678 		    "Memory allocation for fwpkg data failed at %s:%d/%s()!\n",
4679 			__FILE__, __LINE__, __func__);
4680 		return -ENOMEM;
4681 	}
4682 
4683 	smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4684 	if (!smid) {
4685 		ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
4686 		r = -EAGAIN;
4687 		goto out;
4688 	}
4689 
4690 	ioc->base_cmds.status = MPT3_CMD_PENDING;
4691 	mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4692 	ioc->base_cmds.smid = smid;
4693 	memset(mpi_request, 0, sizeof(Mpi25FWUploadRequest_t));
4694 	mpi_request->Function = MPI2_FUNCTION_FW_UPLOAD;
4695 	mpi_request->ImageType = MPI2_FW_UPLOAD_ITYPE_FW_FLASH;
4696 	mpi_request->ImageSize = cpu_to_le32(data_length);
4697 	ioc->build_sg(ioc, &mpi_request->SGL, 0, 0, fwpkg_data_dma,
4698 			data_length);
4699 	init_completion(&ioc->base_cmds.done);
4700 	ioc->put_smid_default(ioc, smid);
4701 	/* Wait for 15 seconds */
4702 	wait_for_completion_timeout(&ioc->base_cmds.done,
4703 			FW_IMG_HDR_READ_TIMEOUT*HZ);
4704 	ioc_info(ioc, "%s: complete\n", __func__);
4705 	if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4706 		ioc_err(ioc, "%s: timeout\n", __func__);
4707 		_debug_dump_mf(mpi_request,
4708 				sizeof(Mpi25FWUploadRequest_t)/4);
4709 		issue_diag_reset = 1;
4710 	} else {
4711 		memset(&mpi_reply, 0, sizeof(Mpi2FWUploadReply_t));
4712 		if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) {
4713 			memcpy(&mpi_reply, ioc->base_cmds.reply,
4714 					sizeof(Mpi2FWUploadReply_t));
4715 			ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
4716 						MPI2_IOCSTATUS_MASK;
4717 			if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
4718 				fw_img_hdr = (Mpi2FWImageHeader_t *)fwpkg_data;
4719 				if (le32_to_cpu(fw_img_hdr->Signature) ==
4720 				    MPI26_IMAGE_HEADER_SIGNATURE0_MPI26) {
4721 					cmp_img_hdr =
4722 					    (Mpi26ComponentImageHeader_t *)
4723 					    (fwpkg_data);
4724 					package_version =
4725 					    le32_to_cpu(
4726 					    cmp_img_hdr->ApplicationSpecific);
4727 				} else
4728 					package_version =
4729 					    le32_to_cpu(
4730 					    fw_img_hdr->PackageVersion.Word);
4731 				if (package_version)
4732 					ioc_info(ioc,
4733 					"FW Package Ver(%02d.%02d.%02d.%02d)\n",
4734 					((package_version) & 0xFF000000) >> 24,
4735 					((package_version) & 0x00FF0000) >> 16,
4736 					((package_version) & 0x0000FF00) >> 8,
4737 					(package_version) & 0x000000FF);
4738 			} else {
4739 				_debug_dump_mf(&mpi_reply,
4740 						sizeof(Mpi2FWUploadReply_t)/4);
4741 			}
4742 		}
4743 	}
4744 	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4745 out:
4746 	if (fwpkg_data)
4747 		dma_free_coherent(&ioc->pdev->dev, data_length, fwpkg_data,
4748 				fwpkg_data_dma);
4749 	if (issue_diag_reset) {
4750 		if (ioc->drv_internal_flags & MPT_DRV_INTERNAL_FIRST_PE_ISSUED)
4751 			return -EFAULT;
4752 		if (mpt3sas_base_check_for_fault_and_issue_reset(ioc))
4753 			return -EFAULT;
4754 		r = -EAGAIN;
4755 	}
4756 	return r;
4757 }
4758 
4759 /**
4760  * _base_display_ioc_capabilities - Display IOC's capabilities.
4761  * @ioc: per adapter object
4762  */
4763 static void
4764 _base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc)
4765 {
4766 	int i = 0;
4767 	char desc[16];
4768 	u32 iounit_pg1_flags;
4769 	u32 bios_version;
4770 
4771 	bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion);
4772 	strncpy(desc, ioc->manu_pg0.ChipName, 16);
4773 	ioc_info(ioc, "%s: FWVersion(%02d.%02d.%02d.%02d), ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
4774 		 desc,
4775 		 (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
4776 		 (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
4777 		 (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
4778 		 ioc->facts.FWVersion.Word & 0x000000FF,
4779 		 ioc->pdev->revision,
4780 		 (bios_version & 0xFF000000) >> 24,
4781 		 (bios_version & 0x00FF0000) >> 16,
4782 		 (bios_version & 0x0000FF00) >> 8,
4783 		 bios_version & 0x000000FF);
4784 
4785 	_base_display_OEMs_branding(ioc);
4786 
4787 	if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) {
4788 		pr_info("%sNVMe", i ? "," : "");
4789 		i++;
4790 	}
4791 
4792 	ioc_info(ioc, "Protocol=(");
4793 
4794 	if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
4795 		pr_cont("Initiator");
4796 		i++;
4797 	}
4798 
4799 	if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
4800 		pr_cont("%sTarget", i ? "," : "");
4801 		i++;
4802 	}
4803 
4804 	i = 0;
4805 	pr_cont("), Capabilities=(");
4806 
4807 	if (!ioc->hide_ir_msg) {
4808 		if (ioc->facts.IOCCapabilities &
4809 		    MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
4810 			pr_cont("Raid");
4811 			i++;
4812 		}
4813 	}
4814 
4815 	if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
4816 		pr_cont("%sTLR", i ? "," : "");
4817 		i++;
4818 	}
4819 
4820 	if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
4821 		pr_cont("%sMulticast", i ? "," : "");
4822 		i++;
4823 	}
4824 
4825 	if (ioc->facts.IOCCapabilities &
4826 	    MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
4827 		pr_cont("%sBIDI Target", i ? "," : "");
4828 		i++;
4829 	}
4830 
4831 	if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
4832 		pr_cont("%sEEDP", i ? "," : "");
4833 		i++;
4834 	}
4835 
4836 	if (ioc->facts.IOCCapabilities &
4837 	    MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
4838 		pr_cont("%sSnapshot Buffer", i ? "," : "");
4839 		i++;
4840 	}
4841 
4842 	if (ioc->facts.IOCCapabilities &
4843 	    MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
4844 		pr_cont("%sDiag Trace Buffer", i ? "," : "");
4845 		i++;
4846 	}
4847 
4848 	if (ioc->facts.IOCCapabilities &
4849 	    MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
4850 		pr_cont("%sDiag Extended Buffer", i ? "," : "");
4851 		i++;
4852 	}
4853 
4854 	if (ioc->facts.IOCCapabilities &
4855 	    MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
4856 		pr_cont("%sTask Set Full", i ? "," : "");
4857 		i++;
4858 	}
4859 
4860 	iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
4861 	if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
4862 		pr_cont("%sNCQ", i ? "," : "");
4863 		i++;
4864 	}
4865 
4866 	pr_cont(")\n");
4867 }
4868 
4869 /**
4870  * mpt3sas_base_update_missing_delay - change the missing delay timers
4871  * @ioc: per adapter object
4872  * @device_missing_delay: amount of time till device is reported missing
4873  * @io_missing_delay: interval IO is returned when there is a missing device
4874  *
4875  * Passed on the command line, this function will modify the device missing
4876  * delay, as well as the io missing delay. This should be called at driver
4877  * load time.
4878  */
4879 void
4880 mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc,
4881 	u16 device_missing_delay, u8 io_missing_delay)
4882 {
4883 	u16 dmd, dmd_new, dmd_orignal;
4884 	u8 io_missing_delay_original;
4885 	u16 sz;
4886 	Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL;
4887 	Mpi2ConfigReply_t mpi_reply;
4888 	u8 num_phys = 0;
4889 	u16 ioc_status;
4890 
4891 	mpt3sas_config_get_number_hba_phys(ioc, &num_phys);
4892 	if (!num_phys)
4893 		return;
4894 
4895 	sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys *
4896 	    sizeof(Mpi2SasIOUnit1PhyData_t));
4897 	sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL);
4898 	if (!sas_iounit_pg1) {
4899 		ioc_err(ioc, "failure at %s:%d/%s()!\n",
4900 			__FILE__, __LINE__, __func__);
4901 		goto out;
4902 	}
4903 	if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
4904 	    sas_iounit_pg1, sz))) {
4905 		ioc_err(ioc, "failure at %s:%d/%s()!\n",
4906 			__FILE__, __LINE__, __func__);
4907 		goto out;
4908 	}
4909 	ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
4910 	    MPI2_IOCSTATUS_MASK;
4911 	if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
4912 		ioc_err(ioc, "failure at %s:%d/%s()!\n",
4913 			__FILE__, __LINE__, __func__);
4914 		goto out;
4915 	}
4916 
4917 	/* device missing delay */
4918 	dmd = sas_iounit_pg1->ReportDeviceMissingDelay;
4919 	if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
4920 		dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
4921 	else
4922 		dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
4923 	dmd_orignal = dmd;
4924 	if (device_missing_delay > 0x7F) {
4925 		dmd = (device_missing_delay > 0x7F0) ? 0x7F0 :
4926 		    device_missing_delay;
4927 		dmd = dmd / 16;
4928 		dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16;
4929 	} else
4930 		dmd = device_missing_delay;
4931 	sas_iounit_pg1->ReportDeviceMissingDelay = dmd;
4932 
4933 	/* io missing delay */
4934 	io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay;
4935 	sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay;
4936 
4937 	if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1,
4938 	    sz)) {
4939 		if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
4940 			dmd_new = (dmd &
4941 			    MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
4942 		else
4943 			dmd_new =
4944 		    dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
4945 		ioc_info(ioc, "device_missing_delay: old(%d), new(%d)\n",
4946 			 dmd_orignal, dmd_new);
4947 		ioc_info(ioc, "ioc_missing_delay: old(%d), new(%d)\n",
4948 			 io_missing_delay_original,
4949 			 io_missing_delay);
4950 		ioc->device_missing_delay = dmd_new;
4951 		ioc->io_missing_delay = io_missing_delay;
4952 	}
4953 
4954 out:
4955 	kfree(sas_iounit_pg1);
4956 }
4957 
4958 /**
4959  * _base_update_ioc_page1_inlinewith_perf_mode - Update IOC Page1 fields
4960  *    according to performance mode.
4961  * @ioc : per adapter object
4962  *
4963  * Return: zero on success; otherwise return EAGAIN error code asking the
4964  * caller to retry.
4965  */
4966 static int
4967 _base_update_ioc_page1_inlinewith_perf_mode(struct MPT3SAS_ADAPTER *ioc)
4968 {
4969 	Mpi2IOCPage1_t ioc_pg1;
4970 	Mpi2ConfigReply_t mpi_reply;
4971 	int rc;
4972 
4973 	rc = mpt3sas_config_get_ioc_pg1(ioc, &mpi_reply, &ioc->ioc_pg1_copy);
4974 	if (rc)
4975 		return rc;
4976 	memcpy(&ioc_pg1, &ioc->ioc_pg1_copy, sizeof(Mpi2IOCPage1_t));
4977 
4978 	switch (perf_mode) {
4979 	case MPT_PERF_MODE_DEFAULT:
4980 	case MPT_PERF_MODE_BALANCED:
4981 		if (ioc->high_iops_queues) {
4982 			ioc_info(ioc,
4983 				"Enable interrupt coalescing only for first\t"
4984 				"%d reply queues\n",
4985 				MPT3SAS_HIGH_IOPS_REPLY_QUEUES);
4986 			/*
4987 			 * If 31st bit is zero then interrupt coalescing is
4988 			 * enabled for all reply descriptor post queues.
4989 			 * If 31st bit is set to one then user can
4990 			 * enable/disable interrupt coalescing on per reply
4991 			 * descriptor post queue group(8) basis. So to enable
4992 			 * interrupt coalescing only on first reply descriptor
4993 			 * post queue group 31st bit and zero th bit is enabled.
4994 			 */
4995 			ioc_pg1.ProductSpecific = cpu_to_le32(0x80000000 |
4996 			    ((1 << MPT3SAS_HIGH_IOPS_REPLY_QUEUES/8) - 1));
4997 			rc = mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1);
4998 			if (rc)
4999 				return rc;
5000 			ioc_info(ioc, "performance mode: balanced\n");
5001 			return 0;
5002 		}
5003 		fallthrough;
5004 	case MPT_PERF_MODE_LATENCY:
5005 		/*
5006 		 * Enable interrupt coalescing on all reply queues
5007 		 * with timeout value 0xA
5008 		 */
5009 		ioc_pg1.CoalescingTimeout = cpu_to_le32(0xa);
5010 		ioc_pg1.Flags |= cpu_to_le32(MPI2_IOCPAGE1_REPLY_COALESCING);
5011 		ioc_pg1.ProductSpecific = 0;
5012 		rc = mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1);
5013 		if (rc)
5014 			return rc;
5015 		ioc_info(ioc, "performance mode: latency\n");
5016 		break;
5017 	case MPT_PERF_MODE_IOPS:
5018 		/*
5019 		 * Enable interrupt coalescing on all reply queues.
5020 		 */
5021 		ioc_info(ioc,
5022 		    "performance mode: iops with coalescing timeout: 0x%x\n",
5023 		    le32_to_cpu(ioc_pg1.CoalescingTimeout));
5024 		ioc_pg1.Flags |= cpu_to_le32(MPI2_IOCPAGE1_REPLY_COALESCING);
5025 		ioc_pg1.ProductSpecific = 0;
5026 		rc = mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1);
5027 		if (rc)
5028 			return rc;
5029 		break;
5030 	}
5031 	return 0;
5032 }
5033 
5034 /**
5035  * _base_get_event_diag_triggers - get event diag trigger values from
5036  *				persistent pages
5037  * @ioc : per adapter object
5038  *
5039  * Return: nothing.
5040  */
5041 static int
5042 _base_get_event_diag_triggers(struct MPT3SAS_ADAPTER *ioc)
5043 {
5044 	Mpi26DriverTriggerPage2_t trigger_pg2;
5045 	struct SL_WH_EVENT_TRIGGER_T *event_tg;
5046 	MPI26_DRIVER_MPI_EVENT_TIGGER_ENTRY *mpi_event_tg;
5047 	Mpi2ConfigReply_t mpi_reply;
5048 	int r = 0, i = 0;
5049 	u16 count = 0;
5050 	u16 ioc_status;
5051 
5052 	r = mpt3sas_config_get_driver_trigger_pg2(ioc, &mpi_reply,
5053 	    &trigger_pg2);
5054 	if (r)
5055 		return r;
5056 
5057 	ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
5058 	    MPI2_IOCSTATUS_MASK;
5059 	if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
5060 		dinitprintk(ioc,
5061 		    ioc_err(ioc,
5062 		    "%s: Failed to get trigger pg2, ioc_status(0x%04x)\n",
5063 		   __func__, ioc_status));
5064 		return 0;
5065 	}
5066 
5067 	if (le16_to_cpu(trigger_pg2.NumMPIEventTrigger)) {
5068 		count = le16_to_cpu(trigger_pg2.NumMPIEventTrigger);
5069 		count = min_t(u16, NUM_VALID_ENTRIES, count);
5070 		ioc->diag_trigger_event.ValidEntries = count;
5071 
5072 		event_tg = &ioc->diag_trigger_event.EventTriggerEntry[0];
5073 		mpi_event_tg = &trigger_pg2.MPIEventTriggers[0];
5074 		for (i = 0; i < count; i++) {
5075 			event_tg->EventValue = le16_to_cpu(
5076 			    mpi_event_tg->MPIEventCode);
5077 			event_tg->LogEntryQualifier = le16_to_cpu(
5078 			    mpi_event_tg->MPIEventCodeSpecific);
5079 			event_tg++;
5080 			mpi_event_tg++;
5081 		}
5082 	}
5083 	return 0;
5084 }
5085 
5086 /**
5087  * _base_get_scsi_diag_triggers - get scsi diag trigger values from
5088  *				persistent pages
5089  * @ioc : per adapter object
5090  *
5091  * Return: 0 on success; otherwise return failure status.
5092  */
5093 static int
5094 _base_get_scsi_diag_triggers(struct MPT3SAS_ADAPTER *ioc)
5095 {
5096 	Mpi26DriverTriggerPage3_t trigger_pg3;
5097 	struct SL_WH_SCSI_TRIGGER_T *scsi_tg;
5098 	MPI26_DRIVER_SCSI_SENSE_TIGGER_ENTRY *mpi_scsi_tg;
5099 	Mpi2ConfigReply_t mpi_reply;
5100 	int r = 0, i = 0;
5101 	u16 count = 0;
5102 	u16 ioc_status;
5103 
5104 	r = mpt3sas_config_get_driver_trigger_pg3(ioc, &mpi_reply,
5105 	    &trigger_pg3);
5106 	if (r)
5107 		return r;
5108 
5109 	ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
5110 	    MPI2_IOCSTATUS_MASK;
5111 	if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
5112 		dinitprintk(ioc,
5113 		    ioc_err(ioc,
5114 		    "%s: Failed to get trigger pg3, ioc_status(0x%04x)\n",
5115 		    __func__, ioc_status));
5116 		return 0;
5117 	}
5118 
5119 	if (le16_to_cpu(trigger_pg3.NumSCSISenseTrigger)) {
5120 		count = le16_to_cpu(trigger_pg3.NumSCSISenseTrigger);
5121 		count = min_t(u16, NUM_VALID_ENTRIES, count);
5122 		ioc->diag_trigger_scsi.ValidEntries = count;
5123 
5124 		scsi_tg = &ioc->diag_trigger_scsi.SCSITriggerEntry[0];
5125 		mpi_scsi_tg = &trigger_pg3.SCSISenseTriggers[0];
5126 		for (i = 0; i < count; i++) {
5127 			scsi_tg->ASCQ = mpi_scsi_tg->ASCQ;
5128 			scsi_tg->ASC = mpi_scsi_tg->ASC;
5129 			scsi_tg->SenseKey = mpi_scsi_tg->SenseKey;
5130 
5131 			scsi_tg++;
5132 			mpi_scsi_tg++;
5133 		}
5134 	}
5135 	return 0;
5136 }
5137 
5138 /**
5139  * _base_get_mpi_diag_triggers - get mpi diag trigger values from
5140  *				persistent pages
5141  * @ioc : per adapter object
5142  *
5143  * Return: 0 on success; otherwise return failure status.
5144  */
5145 static int
5146 _base_get_mpi_diag_triggers(struct MPT3SAS_ADAPTER *ioc)
5147 {
5148 	Mpi26DriverTriggerPage4_t trigger_pg4;
5149 	struct SL_WH_MPI_TRIGGER_T *status_tg;
5150 	MPI26_DRIVER_IOCSTATUS_LOGINFO_TIGGER_ENTRY *mpi_status_tg;
5151 	Mpi2ConfigReply_t mpi_reply;
5152 	int r = 0, i = 0;
5153 	u16 count = 0;
5154 	u16 ioc_status;
5155 
5156 	r = mpt3sas_config_get_driver_trigger_pg4(ioc, &mpi_reply,
5157 	    &trigger_pg4);
5158 	if (r)
5159 		return r;
5160 
5161 	ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
5162 	    MPI2_IOCSTATUS_MASK;
5163 	if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
5164 		dinitprintk(ioc,
5165 		    ioc_err(ioc,
5166 		    "%s: Failed to get trigger pg4, ioc_status(0x%04x)\n",
5167 		    __func__, ioc_status));
5168 		return 0;
5169 	}
5170 
5171 	if (le16_to_cpu(trigger_pg4.NumIOCStatusLogInfoTrigger)) {
5172 		count = le16_to_cpu(trigger_pg4.NumIOCStatusLogInfoTrigger);
5173 		count = min_t(u16, NUM_VALID_ENTRIES, count);
5174 		ioc->diag_trigger_mpi.ValidEntries = count;
5175 
5176 		status_tg = &ioc->diag_trigger_mpi.MPITriggerEntry[0];
5177 		mpi_status_tg = &trigger_pg4.IOCStatusLoginfoTriggers[0];
5178 
5179 		for (i = 0; i < count; i++) {
5180 			status_tg->IOCStatus = le16_to_cpu(
5181 			    mpi_status_tg->IOCStatus);
5182 			status_tg->IocLogInfo = le32_to_cpu(
5183 			    mpi_status_tg->LogInfo);
5184 
5185 			status_tg++;
5186 			mpi_status_tg++;
5187 		}
5188 	}
5189 	return 0;
5190 }
5191 
5192 /**
5193  * _base_get_master_diag_triggers - get master diag trigger values from
5194  *				persistent pages
5195  * @ioc : per adapter object
5196  *
5197  * Return: nothing.
5198  */
5199 static int
5200 _base_get_master_diag_triggers(struct MPT3SAS_ADAPTER *ioc)
5201 {
5202 	Mpi26DriverTriggerPage1_t trigger_pg1;
5203 	Mpi2ConfigReply_t mpi_reply;
5204 	int r;
5205 	u16 ioc_status;
5206 
5207 	r = mpt3sas_config_get_driver_trigger_pg1(ioc, &mpi_reply,
5208 	    &trigger_pg1);
5209 	if (r)
5210 		return r;
5211 
5212 	ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
5213 	    MPI2_IOCSTATUS_MASK;
5214 	if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
5215 		dinitprintk(ioc,
5216 		    ioc_err(ioc,
5217 		    "%s: Failed to get trigger pg1, ioc_status(0x%04x)\n",
5218 		   __func__, ioc_status));
5219 		return 0;
5220 	}
5221 
5222 	if (le16_to_cpu(trigger_pg1.NumMasterTrigger))
5223 		ioc->diag_trigger_master.MasterData |=
5224 		    le32_to_cpu(
5225 		    trigger_pg1.MasterTriggers[0].MasterTriggerFlags);
5226 	return 0;
5227 }
5228 
5229 /**
5230  * _base_check_for_trigger_pages_support - checks whether HBA FW supports
5231  *					driver trigger pages or not
5232  * @ioc : per adapter object
5233  * @trigger_flags : address where trigger page0's TriggerFlags value is copied
5234  *
5235  * Return: trigger flags mask if HBA FW supports driver trigger pages;
5236  * otherwise returns %-EFAULT if driver trigger pages are not supported by FW or
5237  * return EAGAIN if diag reset occurred due to FW fault and asking the
5238  * caller to retry the command.
5239  *
5240  */
5241 static int
5242 _base_check_for_trigger_pages_support(struct MPT3SAS_ADAPTER *ioc, u32 *trigger_flags)
5243 {
5244 	Mpi26DriverTriggerPage0_t trigger_pg0;
5245 	int r = 0;
5246 	Mpi2ConfigReply_t mpi_reply;
5247 	u16 ioc_status;
5248 
5249 	r = mpt3sas_config_get_driver_trigger_pg0(ioc, &mpi_reply,
5250 	    &trigger_pg0);
5251 	if (r)
5252 		return r;
5253 
5254 	ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
5255 	    MPI2_IOCSTATUS_MASK;
5256 	if (ioc_status != MPI2_IOCSTATUS_SUCCESS)
5257 		return -EFAULT;
5258 
5259 	*trigger_flags = le16_to_cpu(trigger_pg0.TriggerFlags);
5260 	return 0;
5261 }
5262 
5263 /**
5264  * _base_get_diag_triggers - Retrieve diag trigger values from
5265  *				persistent pages.
5266  * @ioc : per adapter object
5267  *
5268  * Return: zero on success; otherwise return EAGAIN error codes
5269  * asking the caller to retry.
5270  */
5271 static int
5272 _base_get_diag_triggers(struct MPT3SAS_ADAPTER *ioc)
5273 {
5274 	int trigger_flags;
5275 	int r;
5276 
5277 	/*
5278 	 * Default setting of master trigger.
5279 	 */
5280 	ioc->diag_trigger_master.MasterData =
5281 	    (MASTER_TRIGGER_FW_FAULT + MASTER_TRIGGER_ADAPTER_RESET);
5282 
5283 	r = _base_check_for_trigger_pages_support(ioc, &trigger_flags);
5284 	if (r) {
5285 		if (r == -EAGAIN)
5286 			return r;
5287 		/*
5288 		 * Don't go for error handling when FW doesn't support
5289 		 * driver trigger pages.
5290 		 */
5291 		return 0;
5292 	}
5293 
5294 	ioc->supports_trigger_pages = 1;
5295 
5296 	/*
5297 	 * Retrieve master diag trigger values from driver trigger pg1
5298 	 * if master trigger bit enabled in TriggerFlags.
5299 	 */
5300 	if ((u16)trigger_flags &
5301 	    MPI26_DRIVER_TRIGGER0_FLAG_MASTER_TRIGGER_VALID) {
5302 		r = _base_get_master_diag_triggers(ioc);
5303 		if (r)
5304 			return r;
5305 	}
5306 
5307 	/*
5308 	 * Retrieve event diag trigger values from driver trigger pg2
5309 	 * if event trigger bit enabled in TriggerFlags.
5310 	 */
5311 	if ((u16)trigger_flags &
5312 	    MPI26_DRIVER_TRIGGER0_FLAG_MPI_EVENT_TRIGGER_VALID) {
5313 		r = _base_get_event_diag_triggers(ioc);
5314 		if (r)
5315 			return r;
5316 	}
5317 
5318 	/*
5319 	 * Retrieve scsi diag trigger values from driver trigger pg3
5320 	 * if scsi trigger bit enabled in TriggerFlags.
5321 	 */
5322 	if ((u16)trigger_flags &
5323 	    MPI26_DRIVER_TRIGGER0_FLAG_SCSI_SENSE_TRIGGER_VALID) {
5324 		r = _base_get_scsi_diag_triggers(ioc);
5325 		if (r)
5326 			return r;
5327 	}
5328 	/*
5329 	 * Retrieve mpi error diag trigger values from driver trigger pg4
5330 	 * if loginfo trigger bit enabled in TriggerFlags.
5331 	 */
5332 	if ((u16)trigger_flags &
5333 	    MPI26_DRIVER_TRIGGER0_FLAG_LOGINFO_TRIGGER_VALID) {
5334 		r = _base_get_mpi_diag_triggers(ioc);
5335 		if (r)
5336 			return r;
5337 	}
5338 	return 0;
5339 }
5340 
5341 /**
5342  * _base_update_diag_trigger_pages - Update the driver trigger pages after
5343  *			online FW update, in case updated FW supports driver
5344  *			trigger pages.
5345  * @ioc : per adapter object
5346  *
5347  * Return: nothing.
5348  */
5349 static void
5350 _base_update_diag_trigger_pages(struct MPT3SAS_ADAPTER *ioc)
5351 {
5352 
5353 	if (ioc->diag_trigger_master.MasterData)
5354 		mpt3sas_config_update_driver_trigger_pg1(ioc,
5355 		    &ioc->diag_trigger_master, 1);
5356 
5357 	if (ioc->diag_trigger_event.ValidEntries)
5358 		mpt3sas_config_update_driver_trigger_pg2(ioc,
5359 		    &ioc->diag_trigger_event, 1);
5360 
5361 	if (ioc->diag_trigger_scsi.ValidEntries)
5362 		mpt3sas_config_update_driver_trigger_pg3(ioc,
5363 		    &ioc->diag_trigger_scsi, 1);
5364 
5365 	if (ioc->diag_trigger_mpi.ValidEntries)
5366 		mpt3sas_config_update_driver_trigger_pg4(ioc,
5367 		    &ioc->diag_trigger_mpi, 1);
5368 }
5369 
5370 /**
5371  * _base_assign_fw_reported_qd	- Get FW reported QD for SAS/SATA devices.
5372  *				- On failure set default QD values.
5373  * @ioc : per adapter object
5374  *
5375  * Returns 0 for success, non-zero for failure.
5376  *
5377  */
5378 static int _base_assign_fw_reported_qd(struct MPT3SAS_ADAPTER *ioc)
5379 {
5380 	Mpi2ConfigReply_t mpi_reply;
5381 	Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL;
5382 	Mpi26PCIeIOUnitPage1_t pcie_iounit_pg1;
5383 	int sz;
5384 	int rc = 0;
5385 
5386 	ioc->max_wideport_qd = MPT3SAS_SAS_QUEUE_DEPTH;
5387 	ioc->max_narrowport_qd = MPT3SAS_SAS_QUEUE_DEPTH;
5388 	ioc->max_sata_qd = MPT3SAS_SATA_QUEUE_DEPTH;
5389 	ioc->max_nvme_qd = MPT3SAS_NVME_QUEUE_DEPTH;
5390 	if (!ioc->is_gen35_ioc)
5391 		goto out;
5392 	/* sas iounit page 1 */
5393 	sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData);
5394 	sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL);
5395 	if (!sas_iounit_pg1) {
5396 		pr_err("%s: failure at %s:%d/%s()!\n",
5397 		    ioc->name, __FILE__, __LINE__, __func__);
5398 		return rc;
5399 	}
5400 	rc = mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
5401 	    sas_iounit_pg1, sz);
5402 	if (rc) {
5403 		pr_err("%s: failure at %s:%d/%s()!\n",
5404 		    ioc->name, __FILE__, __LINE__, __func__);
5405 		goto out;
5406 	}
5407 	ioc->max_wideport_qd =
5408 	    (le16_to_cpu(sas_iounit_pg1->SASWideMaxQueueDepth)) ?
5409 	    le16_to_cpu(sas_iounit_pg1->SASWideMaxQueueDepth) :
5410 	    MPT3SAS_SAS_QUEUE_DEPTH;
5411 	ioc->max_narrowport_qd =
5412 	    (le16_to_cpu(sas_iounit_pg1->SASNarrowMaxQueueDepth)) ?
5413 	    le16_to_cpu(sas_iounit_pg1->SASNarrowMaxQueueDepth) :
5414 	    MPT3SAS_SAS_QUEUE_DEPTH;
5415 	ioc->max_sata_qd = (sas_iounit_pg1->SATAMaxQDepth) ?
5416 	    sas_iounit_pg1->SATAMaxQDepth : MPT3SAS_SATA_QUEUE_DEPTH;
5417 	/* pcie iounit page 1 */
5418 	rc = mpt3sas_config_get_pcie_iounit_pg1(ioc, &mpi_reply,
5419 	    &pcie_iounit_pg1, sizeof(Mpi26PCIeIOUnitPage1_t));
5420 	if (rc) {
5421 		pr_err("%s: failure at %s:%d/%s()!\n",
5422 		    ioc->name, __FILE__, __LINE__, __func__);
5423 		goto out;
5424 	}
5425 	ioc->max_nvme_qd = (le16_to_cpu(pcie_iounit_pg1.NVMeMaxQueueDepth)) ?
5426 	    (le16_to_cpu(pcie_iounit_pg1.NVMeMaxQueueDepth)) :
5427 	    MPT3SAS_NVME_QUEUE_DEPTH;
5428 out:
5429 	dinitprintk(ioc, pr_err(
5430 	    "MaxWidePortQD: 0x%x MaxNarrowPortQD: 0x%x MaxSataQD: 0x%x MaxNvmeQD: 0x%x\n",
5431 	    ioc->max_wideport_qd, ioc->max_narrowport_qd,
5432 	    ioc->max_sata_qd, ioc->max_nvme_qd));
5433 	kfree(sas_iounit_pg1);
5434 	return rc;
5435 }
5436 
5437 /**
5438  * _base_static_config_pages - static start of day config pages
5439  * @ioc: per adapter object
5440  */
5441 static int
5442 _base_static_config_pages(struct MPT3SAS_ADAPTER *ioc)
5443 {
5444 	Mpi2ConfigReply_t mpi_reply;
5445 	u32 iounit_pg1_flags;
5446 	int tg_flags = 0;
5447 	int rc;
5448 	ioc->nvme_abort_timeout = 30;
5449 
5450 	rc = mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply,
5451 	    &ioc->manu_pg0);
5452 	if (rc)
5453 		return rc;
5454 	if (ioc->ir_firmware) {
5455 		rc = mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
5456 		    &ioc->manu_pg10);
5457 		if (rc)
5458 			return rc;
5459 	}
5460 	/*
5461 	 * Ensure correct T10 PI operation if vendor left EEDPTagMode
5462 	 * flag unset in NVDATA.
5463 	 */
5464 	rc = mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply,
5465 	    &ioc->manu_pg11);
5466 	if (rc)
5467 		return rc;
5468 	if (!ioc->is_gen35_ioc && ioc->manu_pg11.EEDPTagMode == 0) {
5469 		pr_err("%s: overriding NVDATA EEDPTagMode setting\n",
5470 		    ioc->name);
5471 		ioc->manu_pg11.EEDPTagMode &= ~0x3;
5472 		ioc->manu_pg11.EEDPTagMode |= 0x1;
5473 		mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply,
5474 		    &ioc->manu_pg11);
5475 	}
5476 	if (ioc->manu_pg11.AddlFlags2 & NVME_TASK_MNGT_CUSTOM_MASK)
5477 		ioc->tm_custom_handling = 1;
5478 	else {
5479 		ioc->tm_custom_handling = 0;
5480 		if (ioc->manu_pg11.NVMeAbortTO < NVME_TASK_ABORT_MIN_TIMEOUT)
5481 			ioc->nvme_abort_timeout = NVME_TASK_ABORT_MIN_TIMEOUT;
5482 		else if (ioc->manu_pg11.NVMeAbortTO >
5483 					NVME_TASK_ABORT_MAX_TIMEOUT)
5484 			ioc->nvme_abort_timeout = NVME_TASK_ABORT_MAX_TIMEOUT;
5485 		else
5486 			ioc->nvme_abort_timeout = ioc->manu_pg11.NVMeAbortTO;
5487 	}
5488 	ioc->time_sync_interval =
5489 	    ioc->manu_pg11.TimeSyncInterval & MPT3SAS_TIMESYNC_MASK;
5490 	if (ioc->time_sync_interval) {
5491 		if (ioc->manu_pg11.TimeSyncInterval & MPT3SAS_TIMESYNC_UNIT_MASK)
5492 			ioc->time_sync_interval =
5493 			    ioc->time_sync_interval * SECONDS_PER_HOUR;
5494 		else
5495 			ioc->time_sync_interval =
5496 			    ioc->time_sync_interval * SECONDS_PER_MIN;
5497 		dinitprintk(ioc, ioc_info(ioc,
5498 		    "Driver-FW TimeSync interval is %d seconds. ManuPg11 TimeSync Unit is in %s\n",
5499 		    ioc->time_sync_interval, (ioc->manu_pg11.TimeSyncInterval &
5500 		    MPT3SAS_TIMESYNC_UNIT_MASK) ? "Hour" : "Minute"));
5501 	} else {
5502 		if (ioc->is_gen35_ioc)
5503 			ioc_warn(ioc,
5504 			    "TimeSync Interval in Manuf page-11 is not enabled. Periodic Time-Sync will be disabled\n");
5505 	}
5506 	rc = _base_assign_fw_reported_qd(ioc);
5507 	if (rc)
5508 		return rc;
5509 	rc = mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
5510 	if (rc)
5511 		return rc;
5512 	rc = mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
5513 	if (rc)
5514 		return rc;
5515 	rc = mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
5516 	if (rc)
5517 		return rc;
5518 	rc = mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0);
5519 	if (rc)
5520 		return rc;
5521 	rc = mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
5522 	if (rc)
5523 		return rc;
5524 	rc = mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8);
5525 	if (rc)
5526 		return rc;
5527 	_base_display_ioc_capabilities(ioc);
5528 
5529 	/*
5530 	 * Enable task_set_full handling in iounit_pg1 when the
5531 	 * facts capabilities indicate that its supported.
5532 	 */
5533 	iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
5534 	if ((ioc->facts.IOCCapabilities &
5535 	    MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING))
5536 		iounit_pg1_flags &=
5537 		    ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
5538 	else
5539 		iounit_pg1_flags |=
5540 		    MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
5541 	ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags);
5542 	rc = mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
5543 	if (rc)
5544 		return rc;
5545 
5546 	if (ioc->iounit_pg8.NumSensors)
5547 		ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors;
5548 	if (ioc->is_aero_ioc) {
5549 		rc = _base_update_ioc_page1_inlinewith_perf_mode(ioc);
5550 		if (rc)
5551 			return rc;
5552 	}
5553 	if (ioc->is_gen35_ioc) {
5554 		if (ioc->is_driver_loading) {
5555 			rc = _base_get_diag_triggers(ioc);
5556 			if (rc)
5557 				return rc;
5558 		} else {
5559 			/*
5560 			 * In case of online HBA FW update operation,
5561 			 * check whether updated FW supports the driver trigger
5562 			 * pages or not.
5563 			 * - If previous FW has not supported driver trigger
5564 			 *   pages and newer FW supports them then update these
5565 			 *   pages with current diag trigger values.
5566 			 * - If previous FW has supported driver trigger pages
5567 			 *   and new FW doesn't support them then disable
5568 			 *   support_trigger_pages flag.
5569 			 */
5570 			_base_check_for_trigger_pages_support(ioc, &tg_flags);
5571 			if (!ioc->supports_trigger_pages && tg_flags != -EFAULT)
5572 				_base_update_diag_trigger_pages(ioc);
5573 			else if (ioc->supports_trigger_pages &&
5574 			    tg_flags == -EFAULT)
5575 				ioc->supports_trigger_pages = 0;
5576 		}
5577 	}
5578 	return 0;
5579 }
5580 
5581 /**
5582  * mpt3sas_free_enclosure_list - release memory
5583  * @ioc: per adapter object
5584  *
5585  * Free memory allocated during enclosure add.
5586  */
5587 void
5588 mpt3sas_free_enclosure_list(struct MPT3SAS_ADAPTER *ioc)
5589 {
5590 	struct _enclosure_node *enclosure_dev, *enclosure_dev_next;
5591 
5592 	/* Free enclosure list */
5593 	list_for_each_entry_safe(enclosure_dev,
5594 			enclosure_dev_next, &ioc->enclosure_list, list) {
5595 		list_del(&enclosure_dev->list);
5596 		kfree(enclosure_dev);
5597 	}
5598 }
5599 
5600 /**
5601  * _base_release_memory_pools - release memory
5602  * @ioc: per adapter object
5603  *
5604  * Free memory allocated from _base_allocate_memory_pools.
5605  */
5606 static void
5607 _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
5608 {
5609 	int i = 0;
5610 	int j = 0;
5611 	int dma_alloc_count = 0;
5612 	struct chain_tracker *ct;
5613 	int count = ioc->rdpq_array_enable ? ioc->reply_queue_count : 1;
5614 
5615 	dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
5616 
5617 	if (ioc->request) {
5618 		dma_free_coherent(&ioc->pdev->dev, ioc->request_dma_sz,
5619 		    ioc->request,  ioc->request_dma);
5620 		dexitprintk(ioc,
5621 			    ioc_info(ioc, "request_pool(0x%p): free\n",
5622 				     ioc->request));
5623 		ioc->request = NULL;
5624 	}
5625 
5626 	if (ioc->sense) {
5627 		dma_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
5628 		dma_pool_destroy(ioc->sense_dma_pool);
5629 		dexitprintk(ioc,
5630 			    ioc_info(ioc, "sense_pool(0x%p): free\n",
5631 				     ioc->sense));
5632 		ioc->sense = NULL;
5633 	}
5634 
5635 	if (ioc->reply) {
5636 		dma_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
5637 		dma_pool_destroy(ioc->reply_dma_pool);
5638 		dexitprintk(ioc,
5639 			    ioc_info(ioc, "reply_pool(0x%p): free\n",
5640 				     ioc->reply));
5641 		ioc->reply = NULL;
5642 	}
5643 
5644 	if (ioc->reply_free) {
5645 		dma_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
5646 		    ioc->reply_free_dma);
5647 		dma_pool_destroy(ioc->reply_free_dma_pool);
5648 		dexitprintk(ioc,
5649 			    ioc_info(ioc, "reply_free_pool(0x%p): free\n",
5650 				     ioc->reply_free));
5651 		ioc->reply_free = NULL;
5652 	}
5653 
5654 	if (ioc->reply_post) {
5655 		dma_alloc_count = DIV_ROUND_UP(count,
5656 				RDPQ_MAX_INDEX_IN_ONE_CHUNK);
5657 		for (i = 0; i < count; i++) {
5658 			if (i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0
5659 			    && dma_alloc_count) {
5660 				if (ioc->reply_post[i].reply_post_free) {
5661 					dma_pool_free(
5662 					    ioc->reply_post_free_dma_pool,
5663 					    ioc->reply_post[i].reply_post_free,
5664 					ioc->reply_post[i].reply_post_free_dma);
5665 					dexitprintk(ioc, ioc_info(ioc,
5666 					   "reply_post_free_pool(0x%p): free\n",
5667 					   ioc->reply_post[i].reply_post_free));
5668 					ioc->reply_post[i].reply_post_free =
5669 									NULL;
5670 				}
5671 				--dma_alloc_count;
5672 			}
5673 		}
5674 		dma_pool_destroy(ioc->reply_post_free_dma_pool);
5675 		if (ioc->reply_post_free_array &&
5676 			ioc->rdpq_array_enable) {
5677 			dma_pool_free(ioc->reply_post_free_array_dma_pool,
5678 			    ioc->reply_post_free_array,
5679 			    ioc->reply_post_free_array_dma);
5680 			ioc->reply_post_free_array = NULL;
5681 		}
5682 		dma_pool_destroy(ioc->reply_post_free_array_dma_pool);
5683 		kfree(ioc->reply_post);
5684 	}
5685 
5686 	if (ioc->pcie_sgl_dma_pool) {
5687 		for (i = 0; i < ioc->scsiio_depth; i++) {
5688 			dma_pool_free(ioc->pcie_sgl_dma_pool,
5689 					ioc->pcie_sg_lookup[i].pcie_sgl,
5690 					ioc->pcie_sg_lookup[i].pcie_sgl_dma);
5691 			ioc->pcie_sg_lookup[i].pcie_sgl = NULL;
5692 		}
5693 		dma_pool_destroy(ioc->pcie_sgl_dma_pool);
5694 	}
5695 	if (ioc->config_page) {
5696 		dexitprintk(ioc,
5697 			    ioc_info(ioc, "config_page(0x%p): free\n",
5698 				     ioc->config_page));
5699 		dma_free_coherent(&ioc->pdev->dev, ioc->config_page_sz,
5700 		    ioc->config_page, ioc->config_page_dma);
5701 	}
5702 
5703 	kfree(ioc->hpr_lookup);
5704 	ioc->hpr_lookup = NULL;
5705 	kfree(ioc->internal_lookup);
5706 	ioc->internal_lookup = NULL;
5707 	if (ioc->chain_lookup) {
5708 		for (i = 0; i < ioc->scsiio_depth; i++) {
5709 			for (j = ioc->chains_per_prp_buffer;
5710 			    j < ioc->chains_needed_per_io; j++) {
5711 				ct = &ioc->chain_lookup[i].chains_per_smid[j];
5712 				if (ct && ct->chain_buffer)
5713 					dma_pool_free(ioc->chain_dma_pool,
5714 						ct->chain_buffer,
5715 						ct->chain_buffer_dma);
5716 			}
5717 			kfree(ioc->chain_lookup[i].chains_per_smid);
5718 		}
5719 		dma_pool_destroy(ioc->chain_dma_pool);
5720 		kfree(ioc->chain_lookup);
5721 		ioc->chain_lookup = NULL;
5722 	}
5723 
5724 	kfree(ioc->io_queue_num);
5725 	ioc->io_queue_num = NULL;
5726 }
5727 
5728 /**
5729  * mpt3sas_check_same_4gb_region - checks whether all reply queues in a set are
5730  *	having same upper 32bits in their base memory address.
5731  * @reply_pool_start_address: Base address of a reply queue set
5732  * @pool_sz: Size of single Reply Descriptor Post Queues pool size
5733  *
5734  * Return: 1 if reply queues in a set have a same upper 32bits in their base
5735  * memory address, else 0.
5736  */
5737 
5738 static int
5739 mpt3sas_check_same_4gb_region(long reply_pool_start_address, u32 pool_sz)
5740 {
5741 	long reply_pool_end_address;
5742 
5743 	reply_pool_end_address = reply_pool_start_address + pool_sz;
5744 
5745 	if (upper_32_bits(reply_pool_start_address) ==
5746 		upper_32_bits(reply_pool_end_address))
5747 		return 1;
5748 	else
5749 		return 0;
5750 }
5751 
5752 /**
5753  * _base_reduce_hba_queue_depth- Retry with reduced queue depth
5754  * @ioc: Adapter object
5755  *
5756  * Return: 0 for success, non-zero for failure.
5757  **/
5758 static inline int
5759 _base_reduce_hba_queue_depth(struct MPT3SAS_ADAPTER *ioc)
5760 {
5761 	int reduce_sz = 64;
5762 
5763 	if ((ioc->hba_queue_depth - reduce_sz) >
5764 	    (ioc->internal_depth + INTERNAL_SCSIIO_CMDS_COUNT)) {
5765 		ioc->hba_queue_depth -= reduce_sz;
5766 		return 0;
5767 	} else
5768 		return -ENOMEM;
5769 }
5770 
5771 /**
5772  * _base_allocate_pcie_sgl_pool - Allocating DMA'able memory
5773  *			for pcie sgl pools.
5774  * @ioc: Adapter object
5775  * @sz: DMA Pool size
5776  *
5777  * Return: 0 for success, non-zero for failure.
5778  */
5779 
5780 static int
5781 _base_allocate_pcie_sgl_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz)
5782 {
5783 	int i = 0, j = 0;
5784 	struct chain_tracker *ct;
5785 
5786 	ioc->pcie_sgl_dma_pool =
5787 	    dma_pool_create("PCIe SGL pool", &ioc->pdev->dev, sz,
5788 	    ioc->page_size, 0);
5789 	if (!ioc->pcie_sgl_dma_pool) {
5790 		ioc_err(ioc, "PCIe SGL pool: dma_pool_create failed\n");
5791 		return -ENOMEM;
5792 	}
5793 
5794 	ioc->chains_per_prp_buffer = sz/ioc->chain_segment_sz;
5795 	ioc->chains_per_prp_buffer =
5796 	    min(ioc->chains_per_prp_buffer, ioc->chains_needed_per_io);
5797 	for (i = 0; i < ioc->scsiio_depth; i++) {
5798 		ioc->pcie_sg_lookup[i].pcie_sgl =
5799 		    dma_pool_alloc(ioc->pcie_sgl_dma_pool, GFP_KERNEL,
5800 		    &ioc->pcie_sg_lookup[i].pcie_sgl_dma);
5801 		if (!ioc->pcie_sg_lookup[i].pcie_sgl) {
5802 			ioc_err(ioc, "PCIe SGL pool: dma_pool_alloc failed\n");
5803 			return -EAGAIN;
5804 		}
5805 
5806 		if (!mpt3sas_check_same_4gb_region(
5807 		    (long)ioc->pcie_sg_lookup[i].pcie_sgl, sz)) {
5808 			ioc_err(ioc, "PCIE SGLs are not in same 4G !! pcie sgl (0x%p) dma = (0x%llx)\n",
5809 			    ioc->pcie_sg_lookup[i].pcie_sgl,
5810 			    (unsigned long long)
5811 			    ioc->pcie_sg_lookup[i].pcie_sgl_dma);
5812 			ioc->use_32bit_dma = true;
5813 			return -EAGAIN;
5814 		}
5815 
5816 		for (j = 0; j < ioc->chains_per_prp_buffer; j++) {
5817 			ct = &ioc->chain_lookup[i].chains_per_smid[j];
5818 			ct->chain_buffer =
5819 			    ioc->pcie_sg_lookup[i].pcie_sgl +
5820 			    (j * ioc->chain_segment_sz);
5821 			ct->chain_buffer_dma =
5822 			    ioc->pcie_sg_lookup[i].pcie_sgl_dma +
5823 			    (j * ioc->chain_segment_sz);
5824 		}
5825 	}
5826 	dinitprintk(ioc, ioc_info(ioc,
5827 	    "PCIe sgl pool depth(%d), element_size(%d), pool_size(%d kB)\n",
5828 	    ioc->scsiio_depth, sz, (sz * ioc->scsiio_depth)/1024));
5829 	dinitprintk(ioc, ioc_info(ioc,
5830 	    "Number of chains can fit in a PRP page(%d)\n",
5831 	    ioc->chains_per_prp_buffer));
5832 	return 0;
5833 }
5834 
5835 /**
5836  * _base_allocate_chain_dma_pool - Allocating DMA'able memory
5837  *			for chain dma pool.
5838  * @ioc: Adapter object
5839  * @sz: DMA Pool size
5840  *
5841  * Return: 0 for success, non-zero for failure.
5842  */
5843 static int
5844 _base_allocate_chain_dma_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz)
5845 {
5846 	int i = 0, j = 0;
5847 	struct chain_tracker *ctr;
5848 
5849 	ioc->chain_dma_pool = dma_pool_create("chain pool", &ioc->pdev->dev,
5850 	    ioc->chain_segment_sz, 16, 0);
5851 	if (!ioc->chain_dma_pool)
5852 		return -ENOMEM;
5853 
5854 	for (i = 0; i < ioc->scsiio_depth; i++) {
5855 		for (j = ioc->chains_per_prp_buffer;
5856 		    j < ioc->chains_needed_per_io; j++) {
5857 			ctr = &ioc->chain_lookup[i].chains_per_smid[j];
5858 			ctr->chain_buffer = dma_pool_alloc(ioc->chain_dma_pool,
5859 			    GFP_KERNEL, &ctr->chain_buffer_dma);
5860 			if (!ctr->chain_buffer)
5861 				return -EAGAIN;
5862 			if (!mpt3sas_check_same_4gb_region((long)
5863 			    ctr->chain_buffer, ioc->chain_segment_sz)) {
5864 				ioc_err(ioc,
5865 				    "Chain buffers are not in same 4G !!! Chain buff (0x%p) dma = (0x%llx)\n",
5866 				    ctr->chain_buffer,
5867 				    (unsigned long long)ctr->chain_buffer_dma);
5868 				ioc->use_32bit_dma = true;
5869 				return -EAGAIN;
5870 			}
5871 		}
5872 	}
5873 	dinitprintk(ioc, ioc_info(ioc,
5874 	    "chain_lookup depth (%d), frame_size(%d), pool_size(%d kB)\n",
5875 	    ioc->scsiio_depth, ioc->chain_segment_sz, ((ioc->scsiio_depth *
5876 	    (ioc->chains_needed_per_io - ioc->chains_per_prp_buffer) *
5877 	    ioc->chain_segment_sz))/1024));
5878 	return 0;
5879 }
5880 
5881 /**
5882  * _base_allocate_sense_dma_pool - Allocating DMA'able memory
5883  *			for sense dma pool.
5884  * @ioc: Adapter object
5885  * @sz: DMA Pool size
5886  * Return: 0 for success, non-zero for failure.
5887  */
5888 static int
5889 _base_allocate_sense_dma_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz)
5890 {
5891 	ioc->sense_dma_pool =
5892 	    dma_pool_create("sense pool", &ioc->pdev->dev, sz, 4, 0);
5893 	if (!ioc->sense_dma_pool)
5894 		return -ENOMEM;
5895 	ioc->sense = dma_pool_alloc(ioc->sense_dma_pool,
5896 	    GFP_KERNEL, &ioc->sense_dma);
5897 	if (!ioc->sense)
5898 		return -EAGAIN;
5899 	if (!mpt3sas_check_same_4gb_region((long)ioc->sense, sz)) {
5900 		dinitprintk(ioc, pr_err(
5901 		    "Bad Sense Pool! sense (0x%p) sense_dma = (0x%llx)\n",
5902 		    ioc->sense, (unsigned long long) ioc->sense_dma));
5903 		ioc->use_32bit_dma = true;
5904 		return -EAGAIN;
5905 	}
5906 	ioc_info(ioc,
5907 	    "sense pool(0x%p) - dma(0x%llx): depth(%d), element_size(%d), pool_size (%d kB)\n",
5908 	    ioc->sense, (unsigned long long)ioc->sense_dma,
5909 	    ioc->scsiio_depth, SCSI_SENSE_BUFFERSIZE, sz/1024);
5910 	return 0;
5911 }
5912 
5913 /**
5914  * _base_allocate_reply_pool - Allocating DMA'able memory
5915  *			for reply pool.
5916  * @ioc: Adapter object
5917  * @sz: DMA Pool size
5918  * Return: 0 for success, non-zero for failure.
5919  */
5920 static int
5921 _base_allocate_reply_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz)
5922 {
5923 	/* reply pool, 4 byte align */
5924 	ioc->reply_dma_pool = dma_pool_create("reply pool",
5925 	    &ioc->pdev->dev, sz, 4, 0);
5926 	if (!ioc->reply_dma_pool)
5927 		return -ENOMEM;
5928 	ioc->reply = dma_pool_alloc(ioc->reply_dma_pool, GFP_KERNEL,
5929 	    &ioc->reply_dma);
5930 	if (!ioc->reply)
5931 		return -EAGAIN;
5932 	if (!mpt3sas_check_same_4gb_region((long)ioc->reply_free, sz)) {
5933 		dinitprintk(ioc, pr_err(
5934 		    "Bad Reply Pool! Reply (0x%p) Reply dma = (0x%llx)\n",
5935 		    ioc->reply, (unsigned long long) ioc->reply_dma));
5936 		ioc->use_32bit_dma = true;
5937 		return -EAGAIN;
5938 	}
5939 	ioc->reply_dma_min_address = (u32)(ioc->reply_dma);
5940 	ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz;
5941 	ioc_info(ioc,
5942 	    "reply pool(0x%p) - dma(0x%llx): depth(%d), frame_size(%d), pool_size(%d kB)\n",
5943 	    ioc->reply, (unsigned long long)ioc->reply_dma,
5944 	    ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024);
5945 	return 0;
5946 }
5947 
5948 /**
5949  * _base_allocate_reply_free_dma_pool - Allocating DMA'able memory
5950  *			for reply free dma pool.
5951  * @ioc: Adapter object
5952  * @sz: DMA Pool size
5953  * Return: 0 for success, non-zero for failure.
5954  */
5955 static int
5956 _base_allocate_reply_free_dma_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz)
5957 {
5958 	/* reply free queue, 16 byte align */
5959 	ioc->reply_free_dma_pool = dma_pool_create(
5960 	    "reply_free pool", &ioc->pdev->dev, sz, 16, 0);
5961 	if (!ioc->reply_free_dma_pool)
5962 		return -ENOMEM;
5963 	ioc->reply_free = dma_pool_alloc(ioc->reply_free_dma_pool,
5964 	    GFP_KERNEL, &ioc->reply_free_dma);
5965 	if (!ioc->reply_free)
5966 		return -EAGAIN;
5967 	if (!mpt3sas_check_same_4gb_region((long)ioc->reply_free, sz)) {
5968 		dinitprintk(ioc,
5969 		    pr_err("Bad Reply Free Pool! Reply Free (0x%p) Reply Free dma = (0x%llx)\n",
5970 		    ioc->reply_free, (unsigned long long) ioc->reply_free_dma));
5971 		ioc->use_32bit_dma = true;
5972 		return -EAGAIN;
5973 	}
5974 	memset(ioc->reply_free, 0, sz);
5975 	dinitprintk(ioc, ioc_info(ioc,
5976 	    "reply_free pool(0x%p): depth(%d), element_size(%d), pool_size(%d kB)\n",
5977 	    ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024));
5978 	dinitprintk(ioc, ioc_info(ioc,
5979 	    "reply_free_dma (0x%llx)\n",
5980 	    (unsigned long long)ioc->reply_free_dma));
5981 	return 0;
5982 }
5983 
5984 /**
5985  * _base_allocate_reply_post_free_array - Allocating DMA'able memory
5986  *			for reply post free array.
5987  * @ioc: Adapter object
5988  * @reply_post_free_array_sz: DMA Pool size
5989  * Return: 0 for success, non-zero for failure.
5990  */
5991 
5992 static int
5993 _base_allocate_reply_post_free_array(struct MPT3SAS_ADAPTER *ioc,
5994 	u32 reply_post_free_array_sz)
5995 {
5996 	ioc->reply_post_free_array_dma_pool =
5997 	    dma_pool_create("reply_post_free_array pool",
5998 	    &ioc->pdev->dev, reply_post_free_array_sz, 16, 0);
5999 	if (!ioc->reply_post_free_array_dma_pool)
6000 		return -ENOMEM;
6001 	ioc->reply_post_free_array =
6002 	    dma_pool_alloc(ioc->reply_post_free_array_dma_pool,
6003 	    GFP_KERNEL, &ioc->reply_post_free_array_dma);
6004 	if (!ioc->reply_post_free_array)
6005 		return -EAGAIN;
6006 	if (!mpt3sas_check_same_4gb_region((long)ioc->reply_post_free_array,
6007 	    reply_post_free_array_sz)) {
6008 		dinitprintk(ioc, pr_err(
6009 		    "Bad Reply Free Pool! Reply Free (0x%p) Reply Free dma = (0x%llx)\n",
6010 		    ioc->reply_free,
6011 		    (unsigned long long) ioc->reply_free_dma));
6012 		ioc->use_32bit_dma = true;
6013 		return -EAGAIN;
6014 	}
6015 	return 0;
6016 }
6017 /**
6018  * base_alloc_rdpq_dma_pool - Allocating DMA'able memory
6019  *                     for reply queues.
6020  * @ioc: per adapter object
6021  * @sz: DMA Pool size
6022  * Return: 0 for success, non-zero for failure.
6023  */
6024 static int
6025 base_alloc_rdpq_dma_pool(struct MPT3SAS_ADAPTER *ioc, int sz)
6026 {
6027 	int i = 0;
6028 	u32 dma_alloc_count = 0;
6029 	int reply_post_free_sz = ioc->reply_post_queue_depth *
6030 		sizeof(Mpi2DefaultReplyDescriptor_t);
6031 	int count = ioc->rdpq_array_enable ? ioc->reply_queue_count : 1;
6032 
6033 	ioc->reply_post = kcalloc(count, sizeof(struct reply_post_struct),
6034 			GFP_KERNEL);
6035 	if (!ioc->reply_post)
6036 		return -ENOMEM;
6037 	/*
6038 	 *  For INVADER_SERIES each set of 8 reply queues(0-7, 8-15, ..) and
6039 	 *  VENTURA_SERIES each set of 16 reply queues(0-15, 16-31, ..) should
6040 	 *  be within 4GB boundary i.e reply queues in a set must have same
6041 	 *  upper 32-bits in their memory address. so here driver is allocating
6042 	 *  the DMA'able memory for reply queues according.
6043 	 *  Driver uses limitation of
6044 	 *  VENTURA_SERIES to manage INVADER_SERIES as well.
6045 	 */
6046 	dma_alloc_count = DIV_ROUND_UP(count,
6047 				RDPQ_MAX_INDEX_IN_ONE_CHUNK);
6048 	ioc->reply_post_free_dma_pool =
6049 		dma_pool_create("reply_post_free pool",
6050 		    &ioc->pdev->dev, sz, 16, 0);
6051 	if (!ioc->reply_post_free_dma_pool)
6052 		return -ENOMEM;
6053 	for (i = 0; i < count; i++) {
6054 		if ((i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0) && dma_alloc_count) {
6055 			ioc->reply_post[i].reply_post_free =
6056 			    dma_pool_zalloc(ioc->reply_post_free_dma_pool,
6057 				GFP_KERNEL,
6058 				&ioc->reply_post[i].reply_post_free_dma);
6059 			if (!ioc->reply_post[i].reply_post_free)
6060 				return -ENOMEM;
6061 			/*
6062 			 * Each set of RDPQ pool must satisfy 4gb boundary
6063 			 * restriction.
6064 			 * 1) Check if allocated resources for RDPQ pool are in
6065 			 *	the same 4GB range.
6066 			 * 2) If #1 is true, continue with 64 bit DMA.
6067 			 * 3) If #1 is false, return 1. which means free all the
6068 			 * resources and set DMA mask to 32 and allocate.
6069 			 */
6070 			if (!mpt3sas_check_same_4gb_region(
6071 				(long)ioc->reply_post[i].reply_post_free, sz)) {
6072 				dinitprintk(ioc,
6073 				    ioc_err(ioc, "bad Replypost free pool(0x%p)"
6074 				    "reply_post_free_dma = (0x%llx)\n",
6075 				    ioc->reply_post[i].reply_post_free,
6076 				    (unsigned long long)
6077 				    ioc->reply_post[i].reply_post_free_dma));
6078 				return -EAGAIN;
6079 			}
6080 			dma_alloc_count--;
6081 
6082 		} else {
6083 			ioc->reply_post[i].reply_post_free =
6084 			    (Mpi2ReplyDescriptorsUnion_t *)
6085 			    ((long)ioc->reply_post[i-1].reply_post_free
6086 			    + reply_post_free_sz);
6087 			ioc->reply_post[i].reply_post_free_dma =
6088 			    (dma_addr_t)
6089 			    (ioc->reply_post[i-1].reply_post_free_dma +
6090 			    reply_post_free_sz);
6091 		}
6092 	}
6093 	return 0;
6094 }
6095 
6096 /**
6097  * _base_allocate_memory_pools - allocate start of day memory pools
6098  * @ioc: per adapter object
6099  *
6100  * Return: 0 success, anything else error.
6101  */
6102 static int
6103 _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
6104 {
6105 	struct mpt3sas_facts *facts;
6106 	u16 max_sge_elements;
6107 	u16 chains_needed_per_io;
6108 	u32 sz, total_sz, reply_post_free_sz, reply_post_free_array_sz;
6109 	u32 retry_sz;
6110 	u32 rdpq_sz = 0, sense_sz = 0;
6111 	u16 max_request_credit, nvme_blocks_needed;
6112 	unsigned short sg_tablesize;
6113 	u16 sge_size;
6114 	int i;
6115 	int ret = 0, rc = 0;
6116 
6117 	dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
6118 
6119 
6120 	retry_sz = 0;
6121 	facts = &ioc->facts;
6122 
6123 	/* command line tunables for max sgl entries */
6124 	if (max_sgl_entries != -1)
6125 		sg_tablesize = max_sgl_entries;
6126 	else {
6127 		if (ioc->hba_mpi_version_belonged == MPI2_VERSION)
6128 			sg_tablesize = MPT2SAS_SG_DEPTH;
6129 		else
6130 			sg_tablesize = MPT3SAS_SG_DEPTH;
6131 	}
6132 
6133 	/* max sgl entries <= MPT_KDUMP_MIN_PHYS_SEGMENTS in KDUMP mode */
6134 	if (reset_devices)
6135 		sg_tablesize = min_t(unsigned short, sg_tablesize,
6136 		   MPT_KDUMP_MIN_PHYS_SEGMENTS);
6137 
6138 	if (ioc->is_mcpu_endpoint)
6139 		ioc->shost->sg_tablesize = MPT_MIN_PHYS_SEGMENTS;
6140 	else {
6141 		if (sg_tablesize < MPT_MIN_PHYS_SEGMENTS)
6142 			sg_tablesize = MPT_MIN_PHYS_SEGMENTS;
6143 		else if (sg_tablesize > MPT_MAX_PHYS_SEGMENTS) {
6144 			sg_tablesize = min_t(unsigned short, sg_tablesize,
6145 					SG_MAX_SEGMENTS);
6146 			ioc_warn(ioc, "sg_tablesize(%u) is bigger than kernel defined SG_CHUNK_SIZE(%u)\n",
6147 				 sg_tablesize, MPT_MAX_PHYS_SEGMENTS);
6148 		}
6149 		ioc->shost->sg_tablesize = sg_tablesize;
6150 	}
6151 
6152 	ioc->internal_depth = min_t(int, (facts->HighPriorityCredit + (5)),
6153 		(facts->RequestCredit / 4));
6154 	if (ioc->internal_depth < INTERNAL_CMDS_COUNT) {
6155 		if (facts->RequestCredit <= (INTERNAL_CMDS_COUNT +
6156 				INTERNAL_SCSIIO_CMDS_COUNT)) {
6157 			ioc_err(ioc, "IOC doesn't have enough Request Credits, it has just %d number of credits\n",
6158 				facts->RequestCredit);
6159 			return -ENOMEM;
6160 		}
6161 		ioc->internal_depth = 10;
6162 	}
6163 
6164 	ioc->hi_priority_depth = ioc->internal_depth - (5);
6165 	/* command line tunables  for max controller queue depth */
6166 	if (max_queue_depth != -1 && max_queue_depth != 0) {
6167 		max_request_credit = min_t(u16, max_queue_depth +
6168 			ioc->internal_depth, facts->RequestCredit);
6169 		if (max_request_credit > MAX_HBA_QUEUE_DEPTH)
6170 			max_request_credit =  MAX_HBA_QUEUE_DEPTH;
6171 	} else if (reset_devices)
6172 		max_request_credit = min_t(u16, facts->RequestCredit,
6173 		    (MPT3SAS_KDUMP_SCSI_IO_DEPTH + ioc->internal_depth));
6174 	else
6175 		max_request_credit = min_t(u16, facts->RequestCredit,
6176 		    MAX_HBA_QUEUE_DEPTH);
6177 
6178 	/* Firmware maintains additional facts->HighPriorityCredit number of
6179 	 * credits for HiPriprity Request messages, so hba queue depth will be
6180 	 * sum of max_request_credit and high priority queue depth.
6181 	 */
6182 	ioc->hba_queue_depth = max_request_credit + ioc->hi_priority_depth;
6183 
6184 	/* request frame size */
6185 	ioc->request_sz = facts->IOCRequestFrameSize * 4;
6186 
6187 	/* reply frame size */
6188 	ioc->reply_sz = facts->ReplyFrameSize * 4;
6189 
6190 	/* chain segment size */
6191 	if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
6192 		if (facts->IOCMaxChainSegmentSize)
6193 			ioc->chain_segment_sz =
6194 					facts->IOCMaxChainSegmentSize *
6195 					MAX_CHAIN_ELEMT_SZ;
6196 		else
6197 		/* set to 128 bytes size if IOCMaxChainSegmentSize is zero */
6198 			ioc->chain_segment_sz = DEFAULT_NUM_FWCHAIN_ELEMTS *
6199 						    MAX_CHAIN_ELEMT_SZ;
6200 	} else
6201 		ioc->chain_segment_sz = ioc->request_sz;
6202 
6203 	/* calculate the max scatter element size */
6204 	sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee);
6205 
6206  retry_allocation:
6207 	total_sz = 0;
6208 	/* calculate number of sg elements left over in the 1st frame */
6209 	max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) -
6210 	    sizeof(Mpi2SGEIOUnion_t)) + sge_size);
6211 	ioc->max_sges_in_main_message = max_sge_elements/sge_size;
6212 
6213 	/* now do the same for a chain buffer */
6214 	max_sge_elements = ioc->chain_segment_sz - sge_size;
6215 	ioc->max_sges_in_chain_message = max_sge_elements/sge_size;
6216 
6217 	/*
6218 	 *  MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE
6219 	 */
6220 	chains_needed_per_io = ((ioc->shost->sg_tablesize -
6221 	   ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message)
6222 	    + 1;
6223 	if (chains_needed_per_io > facts->MaxChainDepth) {
6224 		chains_needed_per_io = facts->MaxChainDepth;
6225 		ioc->shost->sg_tablesize = min_t(u16,
6226 		ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message
6227 		* chains_needed_per_io), ioc->shost->sg_tablesize);
6228 	}
6229 	ioc->chains_needed_per_io = chains_needed_per_io;
6230 
6231 	/* reply free queue sizing - taking into account for 64 FW events */
6232 	ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
6233 
6234 	/* mCPU manage single counters for simplicity */
6235 	if (ioc->is_mcpu_endpoint)
6236 		ioc->reply_post_queue_depth = ioc->reply_free_queue_depth;
6237 	else {
6238 		/* calculate reply descriptor post queue depth */
6239 		ioc->reply_post_queue_depth = ioc->hba_queue_depth +
6240 			ioc->reply_free_queue_depth +  1;
6241 		/* align the reply post queue on the next 16 count boundary */
6242 		if (ioc->reply_post_queue_depth % 16)
6243 			ioc->reply_post_queue_depth += 16 -
6244 				(ioc->reply_post_queue_depth % 16);
6245 	}
6246 
6247 	if (ioc->reply_post_queue_depth >
6248 	    facts->MaxReplyDescriptorPostQueueDepth) {
6249 		ioc->reply_post_queue_depth =
6250 				facts->MaxReplyDescriptorPostQueueDepth -
6251 		    (facts->MaxReplyDescriptorPostQueueDepth % 16);
6252 		ioc->hba_queue_depth =
6253 				((ioc->reply_post_queue_depth - 64) / 2) - 1;
6254 		ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
6255 	}
6256 
6257 	ioc_info(ioc,
6258 	    "scatter gather: sge_in_main_msg(%d), sge_per_chain(%d), "
6259 	    "sge_per_io(%d), chains_per_io(%d)\n",
6260 	    ioc->max_sges_in_main_message,
6261 	    ioc->max_sges_in_chain_message,
6262 	    ioc->shost->sg_tablesize,
6263 	    ioc->chains_needed_per_io);
6264 
6265 	/* reply post queue, 16 byte align */
6266 	reply_post_free_sz = ioc->reply_post_queue_depth *
6267 	    sizeof(Mpi2DefaultReplyDescriptor_t);
6268 	rdpq_sz = reply_post_free_sz * RDPQ_MAX_INDEX_IN_ONE_CHUNK;
6269 	if ((_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable)
6270 	    || (ioc->reply_queue_count < RDPQ_MAX_INDEX_IN_ONE_CHUNK))
6271 		rdpq_sz = reply_post_free_sz * ioc->reply_queue_count;
6272 	ret = base_alloc_rdpq_dma_pool(ioc, rdpq_sz);
6273 	if (ret == -EAGAIN) {
6274 		/*
6275 		 * Free allocated bad RDPQ memory pools.
6276 		 * Change dma coherent mask to 32 bit and reallocate RDPQ
6277 		 */
6278 		_base_release_memory_pools(ioc);
6279 		ioc->use_32bit_dma = true;
6280 		if (_base_config_dma_addressing(ioc, ioc->pdev) != 0) {
6281 			ioc_err(ioc,
6282 			    "32 DMA mask failed %s\n", pci_name(ioc->pdev));
6283 			return -ENODEV;
6284 		}
6285 		if (base_alloc_rdpq_dma_pool(ioc, rdpq_sz))
6286 			return -ENOMEM;
6287 	} else if (ret == -ENOMEM)
6288 		return -ENOMEM;
6289 	total_sz = rdpq_sz * (!ioc->rdpq_array_enable ? 1 :
6290 	    DIV_ROUND_UP(ioc->reply_queue_count, RDPQ_MAX_INDEX_IN_ONE_CHUNK));
6291 	ioc->scsiio_depth = ioc->hba_queue_depth -
6292 	    ioc->hi_priority_depth - ioc->internal_depth;
6293 
6294 	/* set the scsi host can_queue depth
6295 	 * with some internal commands that could be outstanding
6296 	 */
6297 	ioc->shost->can_queue = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT;
6298 	dinitprintk(ioc,
6299 		    ioc_info(ioc, "scsi host: can_queue depth (%d)\n",
6300 			     ioc->shost->can_queue));
6301 
6302 	/* contiguous pool for request and chains, 16 byte align, one extra "
6303 	 * "frame for smid=0
6304 	 */
6305 	ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth;
6306 	sz = ((ioc->scsiio_depth + 1) * ioc->request_sz);
6307 
6308 	/* hi-priority queue */
6309 	sz += (ioc->hi_priority_depth * ioc->request_sz);
6310 
6311 	/* internal queue */
6312 	sz += (ioc->internal_depth * ioc->request_sz);
6313 
6314 	ioc->request_dma_sz = sz;
6315 	ioc->request = dma_alloc_coherent(&ioc->pdev->dev, sz,
6316 			&ioc->request_dma, GFP_KERNEL);
6317 	if (!ioc->request) {
6318 		ioc_err(ioc, "request pool: dma_alloc_coherent failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), total(%d kB)\n",
6319 			ioc->hba_queue_depth, ioc->chains_needed_per_io,
6320 			ioc->request_sz, sz / 1024);
6321 		if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH)
6322 			goto out;
6323 		retry_sz = 64;
6324 		ioc->hba_queue_depth -= retry_sz;
6325 		_base_release_memory_pools(ioc);
6326 		goto retry_allocation;
6327 	}
6328 
6329 	if (retry_sz)
6330 		ioc_err(ioc, "request pool: dma_alloc_coherent succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), total(%d kb)\n",
6331 			ioc->hba_queue_depth, ioc->chains_needed_per_io,
6332 			ioc->request_sz, sz / 1024);
6333 
6334 	/* hi-priority queue */
6335 	ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
6336 	    ioc->request_sz);
6337 	ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) *
6338 	    ioc->request_sz);
6339 
6340 	/* internal queue */
6341 	ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth *
6342 	    ioc->request_sz);
6343 	ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
6344 	    ioc->request_sz);
6345 
6346 	ioc_info(ioc,
6347 	    "request pool(0x%p) - dma(0x%llx): "
6348 	    "depth(%d), frame_size(%d), pool_size(%d kB)\n",
6349 	    ioc->request, (unsigned long long) ioc->request_dma,
6350 	    ioc->hba_queue_depth, ioc->request_sz,
6351 	    (ioc->hba_queue_depth * ioc->request_sz) / 1024);
6352 
6353 	total_sz += sz;
6354 
6355 	dinitprintk(ioc,
6356 		    ioc_info(ioc, "scsiio(0x%p): depth(%d)\n",
6357 			     ioc->request, ioc->scsiio_depth));
6358 
6359 	ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH);
6360 	sz = ioc->scsiio_depth * sizeof(struct chain_lookup);
6361 	ioc->chain_lookup = kzalloc(sz, GFP_KERNEL);
6362 	if (!ioc->chain_lookup) {
6363 		ioc_err(ioc, "chain_lookup: __get_free_pages failed\n");
6364 		goto out;
6365 	}
6366 
6367 	sz = ioc->chains_needed_per_io * sizeof(struct chain_tracker);
6368 	for (i = 0; i < ioc->scsiio_depth; i++) {
6369 		ioc->chain_lookup[i].chains_per_smid = kzalloc(sz, GFP_KERNEL);
6370 		if (!ioc->chain_lookup[i].chains_per_smid) {
6371 			ioc_err(ioc, "chain_lookup: kzalloc failed\n");
6372 			goto out;
6373 		}
6374 	}
6375 
6376 	/* initialize hi-priority queue smid's */
6377 	ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
6378 	    sizeof(struct request_tracker), GFP_KERNEL);
6379 	if (!ioc->hpr_lookup) {
6380 		ioc_err(ioc, "hpr_lookup: kcalloc failed\n");
6381 		goto out;
6382 	}
6383 	ioc->hi_priority_smid = ioc->scsiio_depth + 1;
6384 	dinitprintk(ioc,
6385 		    ioc_info(ioc, "hi_priority(0x%p): depth(%d), start smid(%d)\n",
6386 			     ioc->hi_priority,
6387 			     ioc->hi_priority_depth, ioc->hi_priority_smid));
6388 
6389 	/* initialize internal queue smid's */
6390 	ioc->internal_lookup = kcalloc(ioc->internal_depth,
6391 	    sizeof(struct request_tracker), GFP_KERNEL);
6392 	if (!ioc->internal_lookup) {
6393 		ioc_err(ioc, "internal_lookup: kcalloc failed\n");
6394 		goto out;
6395 	}
6396 	ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
6397 	dinitprintk(ioc,
6398 		    ioc_info(ioc, "internal(0x%p): depth(%d), start smid(%d)\n",
6399 			     ioc->internal,
6400 			     ioc->internal_depth, ioc->internal_smid));
6401 
6402 	ioc->io_queue_num = kcalloc(ioc->scsiio_depth,
6403 	    sizeof(u16), GFP_KERNEL);
6404 	if (!ioc->io_queue_num)
6405 		goto out;
6406 	/*
6407 	 * The number of NVMe page sized blocks needed is:
6408 	 *     (((sg_tablesize * 8) - 1) / (page_size - 8)) + 1
6409 	 * ((sg_tablesize * 8) - 1) is the max PRP's minus the first PRP entry
6410 	 * that is placed in the main message frame.  8 is the size of each PRP
6411 	 * entry or PRP list pointer entry.  8 is subtracted from page_size
6412 	 * because of the PRP list pointer entry at the end of a page, so this
6413 	 * is not counted as a PRP entry.  The 1 added page is a round up.
6414 	 *
6415 	 * To avoid allocation failures due to the amount of memory that could
6416 	 * be required for NVMe PRP's, only each set of NVMe blocks will be
6417 	 * contiguous, so a new set is allocated for each possible I/O.
6418 	 */
6419 
6420 	ioc->chains_per_prp_buffer = 0;
6421 	if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) {
6422 		nvme_blocks_needed =
6423 			(ioc->shost->sg_tablesize * NVME_PRP_SIZE) - 1;
6424 		nvme_blocks_needed /= (ioc->page_size - NVME_PRP_SIZE);
6425 		nvme_blocks_needed++;
6426 
6427 		sz = sizeof(struct pcie_sg_list) * ioc->scsiio_depth;
6428 		ioc->pcie_sg_lookup = kzalloc(sz, GFP_KERNEL);
6429 		if (!ioc->pcie_sg_lookup) {
6430 			ioc_info(ioc, "PCIe SGL lookup: kzalloc failed\n");
6431 			goto out;
6432 		}
6433 		sz = nvme_blocks_needed * ioc->page_size;
6434 		rc = _base_allocate_pcie_sgl_pool(ioc, sz);
6435 		if (rc == -ENOMEM)
6436 			return -ENOMEM;
6437 		else if (rc == -EAGAIN)
6438 			goto try_32bit_dma;
6439 		total_sz += sz * ioc->scsiio_depth;
6440 	}
6441 
6442 	rc = _base_allocate_chain_dma_pool(ioc, ioc->chain_segment_sz);
6443 	if (rc == -ENOMEM)
6444 		return -ENOMEM;
6445 	else if (rc == -EAGAIN)
6446 		goto try_32bit_dma;
6447 	total_sz += ioc->chain_segment_sz * ((ioc->chains_needed_per_io -
6448 		ioc->chains_per_prp_buffer) * ioc->scsiio_depth);
6449 	dinitprintk(ioc,
6450 	    ioc_info(ioc, "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n",
6451 	    ioc->chain_depth, ioc->chain_segment_sz,
6452 	    (ioc->chain_depth * ioc->chain_segment_sz) / 1024));
6453 	/* sense buffers, 4 byte align */
6454 	sense_sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
6455 	rc = _base_allocate_sense_dma_pool(ioc, sense_sz);
6456 	if (rc  == -ENOMEM)
6457 		return -ENOMEM;
6458 	else if (rc == -EAGAIN)
6459 		goto try_32bit_dma;
6460 	total_sz += sense_sz;
6461 	ioc_info(ioc,
6462 	    "sense pool(0x%p)- dma(0x%llx): depth(%d),"
6463 	    "element_size(%d), pool_size(%d kB)\n",
6464 	    ioc->sense, (unsigned long long)ioc->sense_dma, ioc->scsiio_depth,
6465 	    SCSI_SENSE_BUFFERSIZE, sz / 1024);
6466 	/* reply pool, 4 byte align */
6467 	sz = ioc->reply_free_queue_depth * ioc->reply_sz;
6468 	rc = _base_allocate_reply_pool(ioc, sz);
6469 	if (rc == -ENOMEM)
6470 		return -ENOMEM;
6471 	else if (rc == -EAGAIN)
6472 		goto try_32bit_dma;
6473 	total_sz += sz;
6474 
6475 	/* reply free queue, 16 byte align */
6476 	sz = ioc->reply_free_queue_depth * 4;
6477 	rc = _base_allocate_reply_free_dma_pool(ioc, sz);
6478 	if (rc  == -ENOMEM)
6479 		return -ENOMEM;
6480 	else if (rc == -EAGAIN)
6481 		goto try_32bit_dma;
6482 	dinitprintk(ioc,
6483 		    ioc_info(ioc, "reply_free_dma (0x%llx)\n",
6484 			     (unsigned long long)ioc->reply_free_dma));
6485 	total_sz += sz;
6486 	if (ioc->rdpq_array_enable) {
6487 		reply_post_free_array_sz = ioc->reply_queue_count *
6488 		    sizeof(Mpi2IOCInitRDPQArrayEntry);
6489 		rc = _base_allocate_reply_post_free_array(ioc,
6490 		    reply_post_free_array_sz);
6491 		if (rc == -ENOMEM)
6492 			return -ENOMEM;
6493 		else if (rc == -EAGAIN)
6494 			goto try_32bit_dma;
6495 	}
6496 	ioc->config_page_sz = 512;
6497 	ioc->config_page = dma_alloc_coherent(&ioc->pdev->dev,
6498 			ioc->config_page_sz, &ioc->config_page_dma, GFP_KERNEL);
6499 	if (!ioc->config_page) {
6500 		ioc_err(ioc, "config page: dma_pool_alloc failed\n");
6501 		goto out;
6502 	}
6503 
6504 	ioc_info(ioc, "config page(0x%p) - dma(0x%llx): size(%d)\n",
6505 	    ioc->config_page, (unsigned long long)ioc->config_page_dma,
6506 	    ioc->config_page_sz);
6507 	total_sz += ioc->config_page_sz;
6508 
6509 	ioc_info(ioc, "Allocated physical memory: size(%d kB)\n",
6510 		 total_sz / 1024);
6511 	ioc_info(ioc, "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n",
6512 		 ioc->shost->can_queue, facts->RequestCredit);
6513 	ioc_info(ioc, "Scatter Gather Elements per IO(%d)\n",
6514 		 ioc->shost->sg_tablesize);
6515 	return 0;
6516 
6517 try_32bit_dma:
6518 	_base_release_memory_pools(ioc);
6519 	if (ioc->use_32bit_dma && (ioc->dma_mask > 32)) {
6520 		/* Change dma coherent mask to 32 bit and reallocate */
6521 		if (_base_config_dma_addressing(ioc, ioc->pdev) != 0) {
6522 			pr_err("Setting 32 bit coherent DMA mask Failed %s\n",
6523 			    pci_name(ioc->pdev));
6524 			return -ENODEV;
6525 		}
6526 	} else if (_base_reduce_hba_queue_depth(ioc) != 0)
6527 		return -ENOMEM;
6528 	goto retry_allocation;
6529 
6530  out:
6531 	return -ENOMEM;
6532 }
6533 
6534 /**
6535  * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter.
6536  * @ioc: Pointer to MPT_ADAPTER structure
6537  * @cooked: Request raw or cooked IOC state
6538  *
6539  * Return: all IOC Doorbell register bits if cooked==0, else just the
6540  * Doorbell bits in MPI_IOC_STATE_MASK.
6541  */
6542 u32
6543 mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked)
6544 {
6545 	u32 s, sc;
6546 
6547 	s = ioc->base_readl(&ioc->chip->Doorbell);
6548 	sc = s & MPI2_IOC_STATE_MASK;
6549 	return cooked ? sc : s;
6550 }
6551 
6552 /**
6553  * _base_wait_on_iocstate - waiting on a particular ioc state
6554  * @ioc: ?
6555  * @ioc_state: controller state { READY, OPERATIONAL, or RESET }
6556  * @timeout: timeout in second
6557  *
6558  * Return: 0 for success, non-zero for failure.
6559  */
6560 static int
6561 _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout)
6562 {
6563 	u32 count, cntdn;
6564 	u32 current_state;
6565 
6566 	count = 0;
6567 	cntdn = 1000 * timeout;
6568 	do {
6569 		current_state = mpt3sas_base_get_iocstate(ioc, 1);
6570 		if (current_state == ioc_state)
6571 			return 0;
6572 		if (count && current_state == MPI2_IOC_STATE_FAULT)
6573 			break;
6574 		if (count && current_state == MPI2_IOC_STATE_COREDUMP)
6575 			break;
6576 
6577 		usleep_range(1000, 1500);
6578 		count++;
6579 	} while (--cntdn);
6580 
6581 	return current_state;
6582 }
6583 
6584 /**
6585  * _base_dump_reg_set -	This function will print hexdump of register set.
6586  * @ioc: per adapter object
6587  *
6588  * Return: nothing.
6589  */
6590 static inline void
6591 _base_dump_reg_set(struct MPT3SAS_ADAPTER *ioc)
6592 {
6593 	unsigned int i, sz = 256;
6594 	u32 __iomem *reg = (u32 __iomem *)ioc->chip;
6595 
6596 	ioc_info(ioc, "System Register set:\n");
6597 	for (i = 0; i < (sz / sizeof(u32)); i++)
6598 		pr_info("%08x: %08x\n", (i * 4), readl(&reg[i]));
6599 }
6600 
6601 /**
6602  * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
6603  * a write to the doorbell)
6604  * @ioc: per adapter object
6605  * @timeout: timeout in seconds
6606  *
6607  * Return: 0 for success, non-zero for failure.
6608  *
6609  * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
6610  */
6611 
6612 static int
6613 _base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout)
6614 {
6615 	u32 cntdn, count;
6616 	u32 int_status;
6617 
6618 	count = 0;
6619 	cntdn = 1000 * timeout;
6620 	do {
6621 		int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus);
6622 		if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
6623 			dhsprintk(ioc,
6624 				  ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
6625 					   __func__, count, timeout));
6626 			return 0;
6627 		}
6628 
6629 		usleep_range(1000, 1500);
6630 		count++;
6631 	} while (--cntdn);
6632 
6633 	ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n",
6634 		__func__, count, int_status);
6635 	return -EFAULT;
6636 }
6637 
6638 static int
6639 _base_spin_on_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout)
6640 {
6641 	u32 cntdn, count;
6642 	u32 int_status;
6643 
6644 	count = 0;
6645 	cntdn = 2000 * timeout;
6646 	do {
6647 		int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus);
6648 		if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
6649 			dhsprintk(ioc,
6650 				  ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
6651 					   __func__, count, timeout));
6652 			return 0;
6653 		}
6654 
6655 		udelay(500);
6656 		count++;
6657 	} while (--cntdn);
6658 
6659 	ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n",
6660 		__func__, count, int_status);
6661 	return -EFAULT;
6662 
6663 }
6664 
6665 /**
6666  * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell.
6667  * @ioc: per adapter object
6668  * @timeout: timeout in second
6669  *
6670  * Return: 0 for success, non-zero for failure.
6671  *
6672  * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to
6673  * doorbell.
6674  */
6675 static int
6676 _base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout)
6677 {
6678 	u32 cntdn, count;
6679 	u32 int_status;
6680 	u32 doorbell;
6681 
6682 	count = 0;
6683 	cntdn = 1000 * timeout;
6684 	do {
6685 		int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus);
6686 		if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
6687 			dhsprintk(ioc,
6688 				  ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
6689 					   __func__, count, timeout));
6690 			return 0;
6691 		} else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
6692 			doorbell = ioc->base_readl(&ioc->chip->Doorbell);
6693 			if ((doorbell & MPI2_IOC_STATE_MASK) ==
6694 			    MPI2_IOC_STATE_FAULT) {
6695 				mpt3sas_print_fault_code(ioc, doorbell);
6696 				return -EFAULT;
6697 			}
6698 			if ((doorbell & MPI2_IOC_STATE_MASK) ==
6699 			    MPI2_IOC_STATE_COREDUMP) {
6700 				mpt3sas_print_coredump_info(ioc, doorbell);
6701 				return -EFAULT;
6702 			}
6703 		} else if (int_status == 0xFFFFFFFF)
6704 			goto out;
6705 
6706 		usleep_range(1000, 1500);
6707 		count++;
6708 	} while (--cntdn);
6709 
6710  out:
6711 	ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n",
6712 		__func__, count, int_status);
6713 	return -EFAULT;
6714 }
6715 
6716 /**
6717  * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use
6718  * @ioc: per adapter object
6719  * @timeout: timeout in second
6720  *
6721  * Return: 0 for success, non-zero for failure.
6722  */
6723 static int
6724 _base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout)
6725 {
6726 	u32 cntdn, count;
6727 	u32 doorbell_reg;
6728 
6729 	count = 0;
6730 	cntdn = 1000 * timeout;
6731 	do {
6732 		doorbell_reg = ioc->base_readl(&ioc->chip->Doorbell);
6733 		if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
6734 			dhsprintk(ioc,
6735 				  ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
6736 					   __func__, count, timeout));
6737 			return 0;
6738 		}
6739 
6740 		usleep_range(1000, 1500);
6741 		count++;
6742 	} while (--cntdn);
6743 
6744 	ioc_err(ioc, "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n",
6745 		__func__, count, doorbell_reg);
6746 	return -EFAULT;
6747 }
6748 
6749 /**
6750  * _base_send_ioc_reset - send doorbell reset
6751  * @ioc: per adapter object
6752  * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
6753  * @timeout: timeout in second
6754  *
6755  * Return: 0 for success, non-zero for failure.
6756  */
6757 static int
6758 _base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout)
6759 {
6760 	u32 ioc_state;
6761 	int r = 0;
6762 	unsigned long flags;
6763 
6764 	if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
6765 		ioc_err(ioc, "%s: unknown reset_type\n", __func__);
6766 		return -EFAULT;
6767 	}
6768 
6769 	if (!(ioc->facts.IOCCapabilities &
6770 	   MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
6771 		return -EFAULT;
6772 
6773 	ioc_info(ioc, "sending message unit reset !!\n");
6774 
6775 	writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
6776 	    &ioc->chip->Doorbell);
6777 	if ((_base_wait_for_doorbell_ack(ioc, 15))) {
6778 		r = -EFAULT;
6779 		goto out;
6780 	}
6781 
6782 	ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout);
6783 	if (ioc_state) {
6784 		ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
6785 			__func__, ioc_state);
6786 		r = -EFAULT;
6787 		goto out;
6788 	}
6789  out:
6790 	if (r != 0) {
6791 		ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
6792 		spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
6793 		/*
6794 		 * Wait for IOC state CoreDump to clear only during
6795 		 * HBA initialization & release time.
6796 		 */
6797 		if ((ioc_state & MPI2_IOC_STATE_MASK) ==
6798 		    MPI2_IOC_STATE_COREDUMP && (ioc->is_driver_loading == 1 ||
6799 		    ioc->fault_reset_work_q == NULL)) {
6800 			spin_unlock_irqrestore(
6801 			    &ioc->ioc_reset_in_progress_lock, flags);
6802 			mpt3sas_print_coredump_info(ioc, ioc_state);
6803 			mpt3sas_base_wait_for_coredump_completion(ioc,
6804 			    __func__);
6805 			spin_lock_irqsave(
6806 			    &ioc->ioc_reset_in_progress_lock, flags);
6807 		}
6808 		spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
6809 	}
6810 	ioc_info(ioc, "message unit reset: %s\n",
6811 		 r == 0 ? "SUCCESS" : "FAILED");
6812 	return r;
6813 }
6814 
6815 /**
6816  * mpt3sas_wait_for_ioc - IOC's operational state is checked here.
6817  * @ioc: per adapter object
6818  * @timeout: timeout in seconds
6819  *
6820  * Return: Waits up to timeout seconds for the IOC to
6821  * become operational. Returns 0 if IOC is present
6822  * and operational; otherwise returns %-EFAULT.
6823  */
6824 
6825 int
6826 mpt3sas_wait_for_ioc(struct MPT3SAS_ADAPTER *ioc, int timeout)
6827 {
6828 	int wait_state_count = 0;
6829 	u32 ioc_state;
6830 
6831 	do {
6832 		ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
6833 		if (ioc_state == MPI2_IOC_STATE_OPERATIONAL)
6834 			break;
6835 
6836 		/*
6837 		 * Watchdog thread will be started after IOC Initialization, so
6838 		 * no need to wait here for IOC state to become operational
6839 		 * when IOC Initialization is on. Instead the driver will
6840 		 * return ETIME status, so that calling function can issue
6841 		 * diag reset operation and retry the command.
6842 		 */
6843 		if (ioc->is_driver_loading)
6844 			return -ETIME;
6845 
6846 		ssleep(1);
6847 		ioc_info(ioc, "%s: waiting for operational state(count=%d)\n",
6848 				__func__, ++wait_state_count);
6849 	} while (--timeout);
6850 	if (!timeout) {
6851 		ioc_err(ioc, "%s: failed due to ioc not operational\n", __func__);
6852 		return -EFAULT;
6853 	}
6854 	if (wait_state_count)
6855 		ioc_info(ioc, "ioc is operational\n");
6856 	return 0;
6857 }
6858 
6859 /**
6860  * _base_handshake_req_reply_wait - send request thru doorbell interface
6861  * @ioc: per adapter object
6862  * @request_bytes: request length
6863  * @request: pointer having request payload
6864  * @reply_bytes: reply length
6865  * @reply: pointer to reply payload
6866  * @timeout: timeout in second
6867  *
6868  * Return: 0 for success, non-zero for failure.
6869  */
6870 static int
6871 _base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes,
6872 	u32 *request, int reply_bytes, u16 *reply, int timeout)
6873 {
6874 	MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
6875 	int i;
6876 	u8 failed;
6877 	__le32 *mfp;
6878 
6879 	/* make sure doorbell is not in use */
6880 	if ((ioc->base_readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
6881 		ioc_err(ioc, "doorbell is in use (line=%d)\n", __LINE__);
6882 		return -EFAULT;
6883 	}
6884 
6885 	/* clear pending doorbell interrupts from previous state changes */
6886 	if (ioc->base_readl(&ioc->chip->HostInterruptStatus) &
6887 	    MPI2_HIS_IOC2SYS_DB_STATUS)
6888 		writel(0, &ioc->chip->HostInterruptStatus);
6889 
6890 	/* send message to ioc */
6891 	writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
6892 	    ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)),
6893 	    &ioc->chip->Doorbell);
6894 
6895 	if ((_base_spin_on_doorbell_int(ioc, 5))) {
6896 		ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
6897 			__LINE__);
6898 		return -EFAULT;
6899 	}
6900 	writel(0, &ioc->chip->HostInterruptStatus);
6901 
6902 	if ((_base_wait_for_doorbell_ack(ioc, 5))) {
6903 		ioc_err(ioc, "doorbell handshake ack failed (line=%d)\n",
6904 			__LINE__);
6905 		return -EFAULT;
6906 	}
6907 
6908 	/* send message 32-bits at a time */
6909 	for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) {
6910 		writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
6911 		if ((_base_wait_for_doorbell_ack(ioc, 5)))
6912 			failed = 1;
6913 	}
6914 
6915 	if (failed) {
6916 		ioc_err(ioc, "doorbell handshake sending request failed (line=%d)\n",
6917 			__LINE__);
6918 		return -EFAULT;
6919 	}
6920 
6921 	/* now wait for the reply */
6922 	if ((_base_wait_for_doorbell_int(ioc, timeout))) {
6923 		ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
6924 			__LINE__);
6925 		return -EFAULT;
6926 	}
6927 
6928 	/* read the first two 16-bits, it gives the total length of the reply */
6929 	reply[0] = le16_to_cpu(ioc->base_readl(&ioc->chip->Doorbell)
6930 	    & MPI2_DOORBELL_DATA_MASK);
6931 	writel(0, &ioc->chip->HostInterruptStatus);
6932 	if ((_base_wait_for_doorbell_int(ioc, 5))) {
6933 		ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
6934 			__LINE__);
6935 		return -EFAULT;
6936 	}
6937 	reply[1] = le16_to_cpu(ioc->base_readl(&ioc->chip->Doorbell)
6938 	    & MPI2_DOORBELL_DATA_MASK);
6939 	writel(0, &ioc->chip->HostInterruptStatus);
6940 
6941 	for (i = 2; i < default_reply->MsgLength * 2; i++)  {
6942 		if ((_base_wait_for_doorbell_int(ioc, 5))) {
6943 			ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
6944 				__LINE__);
6945 			return -EFAULT;
6946 		}
6947 		if (i >=  reply_bytes/2) /* overflow case */
6948 			ioc->base_readl(&ioc->chip->Doorbell);
6949 		else
6950 			reply[i] = le16_to_cpu(
6951 			    ioc->base_readl(&ioc->chip->Doorbell)
6952 			    & MPI2_DOORBELL_DATA_MASK);
6953 		writel(0, &ioc->chip->HostInterruptStatus);
6954 	}
6955 
6956 	_base_wait_for_doorbell_int(ioc, 5);
6957 	if (_base_wait_for_doorbell_not_used(ioc, 5) != 0) {
6958 		dhsprintk(ioc,
6959 			  ioc_info(ioc, "doorbell is in use (line=%d)\n",
6960 				   __LINE__));
6961 	}
6962 	writel(0, &ioc->chip->HostInterruptStatus);
6963 
6964 	if (ioc->logging_level & MPT_DEBUG_INIT) {
6965 		mfp = (__le32 *)reply;
6966 		pr_info("\toffset:data\n");
6967 		for (i = 0; i < reply_bytes/4; i++)
6968 			ioc_info(ioc, "\t[0x%02x]:%08x\n", i*4,
6969 			    le32_to_cpu(mfp[i]));
6970 	}
6971 	return 0;
6972 }
6973 
6974 /**
6975  * mpt3sas_base_sas_iounit_control - send sas iounit control to FW
6976  * @ioc: per adapter object
6977  * @mpi_reply: the reply payload from FW
6978  * @mpi_request: the request payload sent to FW
6979  *
6980  * The SAS IO Unit Control Request message allows the host to perform low-level
6981  * operations, such as resets on the PHYs of the IO Unit, also allows the host
6982  * to obtain the IOC assigned device handles for a device if it has other
6983  * identifying information about the device, in addition allows the host to
6984  * remove IOC resources associated with the device.
6985  *
6986  * Return: 0 for success, non-zero for failure.
6987  */
6988 int
6989 mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc,
6990 	Mpi2SasIoUnitControlReply_t *mpi_reply,
6991 	Mpi2SasIoUnitControlRequest_t *mpi_request)
6992 {
6993 	u16 smid;
6994 	u8 issue_reset = 0;
6995 	int rc;
6996 	void *request;
6997 
6998 	dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
6999 
7000 	mutex_lock(&ioc->base_cmds.mutex);
7001 
7002 	if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
7003 		ioc_err(ioc, "%s: base_cmd in use\n", __func__);
7004 		rc = -EAGAIN;
7005 		goto out;
7006 	}
7007 
7008 	rc = mpt3sas_wait_for_ioc(ioc, IOC_OPERATIONAL_WAIT_COUNT);
7009 	if (rc)
7010 		goto out;
7011 
7012 	smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
7013 	if (!smid) {
7014 		ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
7015 		rc = -EAGAIN;
7016 		goto out;
7017 	}
7018 
7019 	rc = 0;
7020 	ioc->base_cmds.status = MPT3_CMD_PENDING;
7021 	request = mpt3sas_base_get_msg_frame(ioc, smid);
7022 	ioc->base_cmds.smid = smid;
7023 	memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t));
7024 	if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
7025 	    mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
7026 		ioc->ioc_link_reset_in_progress = 1;
7027 	init_completion(&ioc->base_cmds.done);
7028 	ioc->put_smid_default(ioc, smid);
7029 	wait_for_completion_timeout(&ioc->base_cmds.done,
7030 	    msecs_to_jiffies(10000));
7031 	if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
7032 	    mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) &&
7033 	    ioc->ioc_link_reset_in_progress)
7034 		ioc->ioc_link_reset_in_progress = 0;
7035 	if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
7036 		mpt3sas_check_cmd_timeout(ioc, ioc->base_cmds.status,
7037 		    mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t)/4,
7038 		    issue_reset);
7039 		goto issue_host_reset;
7040 	}
7041 	if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
7042 		memcpy(mpi_reply, ioc->base_cmds.reply,
7043 		    sizeof(Mpi2SasIoUnitControlReply_t));
7044 	else
7045 		memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t));
7046 	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
7047 	goto out;
7048 
7049  issue_host_reset:
7050 	if (issue_reset)
7051 		mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
7052 	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
7053 	rc = -EFAULT;
7054  out:
7055 	mutex_unlock(&ioc->base_cmds.mutex);
7056 	return rc;
7057 }
7058 
7059 /**
7060  * mpt3sas_base_scsi_enclosure_processor - sending request to sep device
7061  * @ioc: per adapter object
7062  * @mpi_reply: the reply payload from FW
7063  * @mpi_request: the request payload sent to FW
7064  *
7065  * The SCSI Enclosure Processor request message causes the IOC to
7066  * communicate with SES devices to control LED status signals.
7067  *
7068  * Return: 0 for success, non-zero for failure.
7069  */
7070 int
7071 mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc,
7072 	Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request)
7073 {
7074 	u16 smid;
7075 	u8 issue_reset = 0;
7076 	int rc;
7077 	void *request;
7078 
7079 	dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7080 
7081 	mutex_lock(&ioc->base_cmds.mutex);
7082 
7083 	if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
7084 		ioc_err(ioc, "%s: base_cmd in use\n", __func__);
7085 		rc = -EAGAIN;
7086 		goto out;
7087 	}
7088 
7089 	rc = mpt3sas_wait_for_ioc(ioc, IOC_OPERATIONAL_WAIT_COUNT);
7090 	if (rc)
7091 		goto out;
7092 
7093 	smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
7094 	if (!smid) {
7095 		ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
7096 		rc = -EAGAIN;
7097 		goto out;
7098 	}
7099 
7100 	rc = 0;
7101 	ioc->base_cmds.status = MPT3_CMD_PENDING;
7102 	request = mpt3sas_base_get_msg_frame(ioc, smid);
7103 	ioc->base_cmds.smid = smid;
7104 	memset(request, 0, ioc->request_sz);
7105 	memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
7106 	init_completion(&ioc->base_cmds.done);
7107 	ioc->put_smid_default(ioc, smid);
7108 	wait_for_completion_timeout(&ioc->base_cmds.done,
7109 	    msecs_to_jiffies(10000));
7110 	if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
7111 		mpt3sas_check_cmd_timeout(ioc,
7112 		    ioc->base_cmds.status, mpi_request,
7113 		    sizeof(Mpi2SepRequest_t)/4, issue_reset);
7114 		goto issue_host_reset;
7115 	}
7116 	if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
7117 		memcpy(mpi_reply, ioc->base_cmds.reply,
7118 		    sizeof(Mpi2SepReply_t));
7119 	else
7120 		memset(mpi_reply, 0, sizeof(Mpi2SepReply_t));
7121 	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
7122 	goto out;
7123 
7124  issue_host_reset:
7125 	if (issue_reset)
7126 		mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
7127 	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
7128 	rc = -EFAULT;
7129  out:
7130 	mutex_unlock(&ioc->base_cmds.mutex);
7131 	return rc;
7132 }
7133 
7134 /**
7135  * _base_get_port_facts - obtain port facts reply and save in ioc
7136  * @ioc: per adapter object
7137  * @port: ?
7138  *
7139  * Return: 0 for success, non-zero for failure.
7140  */
7141 static int
7142 _base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port)
7143 {
7144 	Mpi2PortFactsRequest_t mpi_request;
7145 	Mpi2PortFactsReply_t mpi_reply;
7146 	struct mpt3sas_port_facts *pfacts;
7147 	int mpi_reply_sz, mpi_request_sz, r;
7148 
7149 	dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7150 
7151 	mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
7152 	mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
7153 	memset(&mpi_request, 0, mpi_request_sz);
7154 	mpi_request.Function = MPI2_FUNCTION_PORT_FACTS;
7155 	mpi_request.PortNumber = port;
7156 	r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
7157 	    (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5);
7158 
7159 	if (r != 0) {
7160 		ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r);
7161 		return r;
7162 	}
7163 
7164 	pfacts = &ioc->pfacts[port];
7165 	memset(pfacts, 0, sizeof(struct mpt3sas_port_facts));
7166 	pfacts->PortNumber = mpi_reply.PortNumber;
7167 	pfacts->VP_ID = mpi_reply.VP_ID;
7168 	pfacts->VF_ID = mpi_reply.VF_ID;
7169 	pfacts->MaxPostedCmdBuffers =
7170 	    le16_to_cpu(mpi_reply.MaxPostedCmdBuffers);
7171 
7172 	return 0;
7173 }
7174 
7175 /**
7176  * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL
7177  * @ioc: per adapter object
7178  * @timeout:
7179  *
7180  * Return: 0 for success, non-zero for failure.
7181  */
7182 static int
7183 _base_wait_for_iocstate(struct MPT3SAS_ADAPTER *ioc, int timeout)
7184 {
7185 	u32 ioc_state;
7186 	int rc;
7187 
7188 	dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7189 
7190 	if (ioc->pci_error_recovery) {
7191 		dfailprintk(ioc,
7192 			    ioc_info(ioc, "%s: host in pci error recovery\n",
7193 				     __func__));
7194 		return -EFAULT;
7195 	}
7196 
7197 	ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
7198 	dhsprintk(ioc,
7199 		  ioc_info(ioc, "%s: ioc_state(0x%08x)\n",
7200 			   __func__, ioc_state));
7201 
7202 	if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) ||
7203 	    (ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
7204 		return 0;
7205 
7206 	if (ioc_state & MPI2_DOORBELL_USED) {
7207 		dhsprintk(ioc, ioc_info(ioc, "unexpected doorbell active!\n"));
7208 		goto issue_diag_reset;
7209 	}
7210 
7211 	if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
7212 		mpt3sas_print_fault_code(ioc, ioc_state &
7213 		    MPI2_DOORBELL_DATA_MASK);
7214 		goto issue_diag_reset;
7215 	} else if ((ioc_state & MPI2_IOC_STATE_MASK) ==
7216 	    MPI2_IOC_STATE_COREDUMP) {
7217 		ioc_info(ioc,
7218 		    "%s: Skipping the diag reset here. (ioc_state=0x%x)\n",
7219 		    __func__, ioc_state);
7220 		return -EFAULT;
7221 	}
7222 
7223 	ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout);
7224 	if (ioc_state) {
7225 		dfailprintk(ioc,
7226 			    ioc_info(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
7227 				     __func__, ioc_state));
7228 		return -EFAULT;
7229 	}
7230 
7231  issue_diag_reset:
7232 	rc = _base_diag_reset(ioc);
7233 	return rc;
7234 }
7235 
7236 /**
7237  * _base_get_ioc_facts - obtain ioc facts reply and save in ioc
7238  * @ioc: per adapter object
7239  *
7240  * Return: 0 for success, non-zero for failure.
7241  */
7242 static int
7243 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc)
7244 {
7245 	Mpi2IOCFactsRequest_t mpi_request;
7246 	Mpi2IOCFactsReply_t mpi_reply;
7247 	struct mpt3sas_facts *facts;
7248 	int mpi_reply_sz, mpi_request_sz, r;
7249 
7250 	dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7251 
7252 	r = _base_wait_for_iocstate(ioc, 10);
7253 	if (r) {
7254 		dfailprintk(ioc,
7255 			    ioc_info(ioc, "%s: failed getting to correct state\n",
7256 				     __func__));
7257 		return r;
7258 	}
7259 	mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
7260 	mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t);
7261 	memset(&mpi_request, 0, mpi_request_sz);
7262 	mpi_request.Function = MPI2_FUNCTION_IOC_FACTS;
7263 	r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
7264 	    (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5);
7265 
7266 	if (r != 0) {
7267 		ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r);
7268 		return r;
7269 	}
7270 
7271 	facts = &ioc->facts;
7272 	memset(facts, 0, sizeof(struct mpt3sas_facts));
7273 	facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion);
7274 	facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion);
7275 	facts->VP_ID = mpi_reply.VP_ID;
7276 	facts->VF_ID = mpi_reply.VF_ID;
7277 	facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions);
7278 	facts->MaxChainDepth = mpi_reply.MaxChainDepth;
7279 	facts->WhoInit = mpi_reply.WhoInit;
7280 	facts->NumberOfPorts = mpi_reply.NumberOfPorts;
7281 	facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors;
7282 	if (ioc->msix_enable && (facts->MaxMSIxVectors <=
7283 	    MAX_COMBINED_MSIX_VECTORS(ioc->is_gen35_ioc)))
7284 		ioc->combined_reply_queue = 0;
7285 	facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);
7286 	facts->MaxReplyDescriptorPostQueueDepth =
7287 	    le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);
7288 	facts->ProductID = le16_to_cpu(mpi_reply.ProductID);
7289 	facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities);
7290 	if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID))
7291 		ioc->ir_firmware = 1;
7292 	if ((facts->IOCCapabilities &
7293 	      MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE) && (!reset_devices))
7294 		ioc->rdpq_array_capable = 1;
7295 	if ((facts->IOCCapabilities & MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ)
7296 	    && ioc->is_aero_ioc)
7297 		ioc->atomic_desc_capable = 1;
7298 	facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
7299 	facts->IOCRequestFrameSize =
7300 	    le16_to_cpu(mpi_reply.IOCRequestFrameSize);
7301 	if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
7302 		facts->IOCMaxChainSegmentSize =
7303 			le16_to_cpu(mpi_reply.IOCMaxChainSegmentSize);
7304 	}
7305 	facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators);
7306 	facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets);
7307 	ioc->shost->max_id = -1;
7308 	facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders);
7309 	facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures);
7310 	facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags);
7311 	facts->HighPriorityCredit =
7312 	    le16_to_cpu(mpi_reply.HighPriorityCredit);
7313 	facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
7314 	facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
7315 	facts->CurrentHostPageSize = mpi_reply.CurrentHostPageSize;
7316 
7317 	/*
7318 	 * Get the Page Size from IOC Facts. If it's 0, default to 4k.
7319 	 */
7320 	ioc->page_size = 1 << facts->CurrentHostPageSize;
7321 	if (ioc->page_size == 1) {
7322 		ioc_info(ioc, "CurrentHostPageSize is 0: Setting default host page size to 4k\n");
7323 		ioc->page_size = 1 << MPT3SAS_HOST_PAGE_SIZE_4K;
7324 	}
7325 	dinitprintk(ioc,
7326 		    ioc_info(ioc, "CurrentHostPageSize(%d)\n",
7327 			     facts->CurrentHostPageSize));
7328 
7329 	dinitprintk(ioc,
7330 		    ioc_info(ioc, "hba queue depth(%d), max chains per io(%d)\n",
7331 			     facts->RequestCredit, facts->MaxChainDepth));
7332 	dinitprintk(ioc,
7333 		    ioc_info(ioc, "request frame size(%d), reply frame size(%d)\n",
7334 			     facts->IOCRequestFrameSize * 4,
7335 			     facts->ReplyFrameSize * 4));
7336 	return 0;
7337 }
7338 
7339 /**
7340  * _base_send_ioc_init - send ioc_init to firmware
7341  * @ioc: per adapter object
7342  *
7343  * Return: 0 for success, non-zero for failure.
7344  */
7345 static int
7346 _base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc)
7347 {
7348 	Mpi2IOCInitRequest_t mpi_request;
7349 	Mpi2IOCInitReply_t mpi_reply;
7350 	int i, r = 0;
7351 	ktime_t current_time;
7352 	u16 ioc_status;
7353 	u32 reply_post_free_array_sz = 0;
7354 
7355 	dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7356 
7357 	memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
7358 	mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
7359 	mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
7360 	mpi_request.VF_ID = 0; /* TODO */
7361 	mpi_request.VP_ID = 0;
7362 	mpi_request.MsgVersion = cpu_to_le16(ioc->hba_mpi_version_belonged);
7363 	mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
7364 	mpi_request.HostPageSize = MPT3SAS_HOST_PAGE_SIZE_4K;
7365 
7366 	if (_base_is_controller_msix_enabled(ioc))
7367 		mpi_request.HostMSIxVectors = ioc->reply_queue_count;
7368 	mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4);
7369 	mpi_request.ReplyDescriptorPostQueueDepth =
7370 	    cpu_to_le16(ioc->reply_post_queue_depth);
7371 	mpi_request.ReplyFreeQueueDepth =
7372 	    cpu_to_le16(ioc->reply_free_queue_depth);
7373 
7374 	mpi_request.SenseBufferAddressHigh =
7375 	    cpu_to_le32((u64)ioc->sense_dma >> 32);
7376 	mpi_request.SystemReplyAddressHigh =
7377 	    cpu_to_le32((u64)ioc->reply_dma >> 32);
7378 	mpi_request.SystemRequestFrameBaseAddress =
7379 	    cpu_to_le64((u64)ioc->request_dma);
7380 	mpi_request.ReplyFreeQueueAddress =
7381 	    cpu_to_le64((u64)ioc->reply_free_dma);
7382 
7383 	if (ioc->rdpq_array_enable) {
7384 		reply_post_free_array_sz = ioc->reply_queue_count *
7385 		    sizeof(Mpi2IOCInitRDPQArrayEntry);
7386 		memset(ioc->reply_post_free_array, 0, reply_post_free_array_sz);
7387 		for (i = 0; i < ioc->reply_queue_count; i++)
7388 			ioc->reply_post_free_array[i].RDPQBaseAddress =
7389 			    cpu_to_le64(
7390 				(u64)ioc->reply_post[i].reply_post_free_dma);
7391 		mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE;
7392 		mpi_request.ReplyDescriptorPostQueueAddress =
7393 		    cpu_to_le64((u64)ioc->reply_post_free_array_dma);
7394 	} else {
7395 		mpi_request.ReplyDescriptorPostQueueAddress =
7396 		    cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma);
7397 	}
7398 
7399 	/*
7400 	 * Set the flag to enable CoreDump state feature in IOC firmware.
7401 	 */
7402 	mpi_request.ConfigurationFlags |=
7403 	    cpu_to_le16(MPI26_IOCINIT_CFGFLAGS_COREDUMP_ENABLE);
7404 
7405 	/* This time stamp specifies number of milliseconds
7406 	 * since epoch ~ midnight January 1, 1970.
7407 	 */
7408 	current_time = ktime_get_real();
7409 	mpi_request.TimeStamp = cpu_to_le64(ktime_to_ms(current_time));
7410 
7411 	if (ioc->logging_level & MPT_DEBUG_INIT) {
7412 		__le32 *mfp;
7413 		int i;
7414 
7415 		mfp = (__le32 *)&mpi_request;
7416 		ioc_info(ioc, "\toffset:data\n");
7417 		for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
7418 			ioc_info(ioc, "\t[0x%02x]:%08x\n", i*4,
7419 			    le32_to_cpu(mfp[i]));
7420 	}
7421 
7422 	r = _base_handshake_req_reply_wait(ioc,
7423 	    sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request,
7424 	    sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 30);
7425 
7426 	if (r != 0) {
7427 		ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r);
7428 		return r;
7429 	}
7430 
7431 	ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
7432 	if (ioc_status != MPI2_IOCSTATUS_SUCCESS ||
7433 	    mpi_reply.IOCLogInfo) {
7434 		ioc_err(ioc, "%s: failed\n", __func__);
7435 		r = -EIO;
7436 	}
7437 
7438 	/* Reset TimeSync Counter*/
7439 	ioc->timestamp_update_count = 0;
7440 	return r;
7441 }
7442 
7443 /**
7444  * mpt3sas_port_enable_done - command completion routine for port enable
7445  * @ioc: per adapter object
7446  * @smid: system request message index
7447  * @msix_index: MSIX table index supplied by the OS
7448  * @reply: reply message frame(lower 32bit addr)
7449  *
7450  * Return: 1 meaning mf should be freed from _base_interrupt
7451  *          0 means the mf is freed from this function.
7452  */
7453 u8
7454 mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
7455 	u32 reply)
7456 {
7457 	MPI2DefaultReply_t *mpi_reply;
7458 	u16 ioc_status;
7459 
7460 	if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED)
7461 		return 1;
7462 
7463 	mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
7464 	if (!mpi_reply)
7465 		return 1;
7466 
7467 	if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE)
7468 		return 1;
7469 
7470 	ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING;
7471 	ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE;
7472 	ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID;
7473 	memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
7474 	ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
7475 	if (ioc_status != MPI2_IOCSTATUS_SUCCESS)
7476 		ioc->port_enable_failed = 1;
7477 
7478 	if (ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE_ASYNC) {
7479 		ioc->port_enable_cmds.status &= ~MPT3_CMD_COMPLETE_ASYNC;
7480 		if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
7481 			mpt3sas_port_enable_complete(ioc);
7482 			return 1;
7483 		} else {
7484 			ioc->start_scan_failed = ioc_status;
7485 			ioc->start_scan = 0;
7486 			return 1;
7487 		}
7488 	}
7489 	complete(&ioc->port_enable_cmds.done);
7490 	return 1;
7491 }
7492 
7493 /**
7494  * _base_send_port_enable - send port_enable(discovery stuff) to firmware
7495  * @ioc: per adapter object
7496  *
7497  * Return: 0 for success, non-zero for failure.
7498  */
7499 static int
7500 _base_send_port_enable(struct MPT3SAS_ADAPTER *ioc)
7501 {
7502 	Mpi2PortEnableRequest_t *mpi_request;
7503 	Mpi2PortEnableReply_t *mpi_reply;
7504 	int r = 0;
7505 	u16 smid;
7506 	u16 ioc_status;
7507 
7508 	ioc_info(ioc, "sending port enable !!\n");
7509 
7510 	if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
7511 		ioc_err(ioc, "%s: internal command already in use\n", __func__);
7512 		return -EAGAIN;
7513 	}
7514 
7515 	smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
7516 	if (!smid) {
7517 		ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
7518 		return -EAGAIN;
7519 	}
7520 
7521 	ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
7522 	mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
7523 	ioc->port_enable_cmds.smid = smid;
7524 	memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
7525 	mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
7526 
7527 	init_completion(&ioc->port_enable_cmds.done);
7528 	ioc->put_smid_default(ioc, smid);
7529 	wait_for_completion_timeout(&ioc->port_enable_cmds.done, 300*HZ);
7530 	if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) {
7531 		ioc_err(ioc, "%s: timeout\n", __func__);
7532 		_debug_dump_mf(mpi_request,
7533 		    sizeof(Mpi2PortEnableRequest_t)/4);
7534 		if (ioc->port_enable_cmds.status & MPT3_CMD_RESET)
7535 			r = -EFAULT;
7536 		else
7537 			r = -ETIME;
7538 		goto out;
7539 	}
7540 
7541 	mpi_reply = ioc->port_enable_cmds.reply;
7542 	ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
7543 	if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
7544 		ioc_err(ioc, "%s: failed with (ioc_status=0x%08x)\n",
7545 			__func__, ioc_status);
7546 		r = -EFAULT;
7547 		goto out;
7548 	}
7549 
7550  out:
7551 	ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
7552 	ioc_info(ioc, "port enable: %s\n", r == 0 ? "SUCCESS" : "FAILED");
7553 	return r;
7554 }
7555 
7556 /**
7557  * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply)
7558  * @ioc: per adapter object
7559  *
7560  * Return: 0 for success, non-zero for failure.
7561  */
7562 int
7563 mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc)
7564 {
7565 	Mpi2PortEnableRequest_t *mpi_request;
7566 	u16 smid;
7567 
7568 	ioc_info(ioc, "sending port enable !!\n");
7569 
7570 	if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
7571 		ioc_err(ioc, "%s: internal command already in use\n", __func__);
7572 		return -EAGAIN;
7573 	}
7574 
7575 	smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
7576 	if (!smid) {
7577 		ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
7578 		return -EAGAIN;
7579 	}
7580 	ioc->drv_internal_flags |= MPT_DRV_INTERNAL_FIRST_PE_ISSUED;
7581 	ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
7582 	ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE_ASYNC;
7583 	mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
7584 	ioc->port_enable_cmds.smid = smid;
7585 	memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
7586 	mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
7587 
7588 	ioc->put_smid_default(ioc, smid);
7589 	return 0;
7590 }
7591 
7592 /**
7593  * _base_determine_wait_on_discovery - desposition
7594  * @ioc: per adapter object
7595  *
7596  * Decide whether to wait on discovery to complete. Used to either
7597  * locate boot device, or report volumes ahead of physical devices.
7598  *
7599  * Return: 1 for wait, 0 for don't wait.
7600  */
7601 static int
7602 _base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc)
7603 {
7604 	/* We wait for discovery to complete if IR firmware is loaded.
7605 	 * The sas topology events arrive before PD events, so we need time to
7606 	 * turn on the bit in ioc->pd_handles to indicate PD
7607 	 * Also, it maybe required to report Volumes ahead of physical
7608 	 * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set.
7609 	 */
7610 	if (ioc->ir_firmware)
7611 		return 1;
7612 
7613 	/* if no Bios, then we don't need to wait */
7614 	if (!ioc->bios_pg3.BiosVersion)
7615 		return 0;
7616 
7617 	/* Bios is present, then we drop down here.
7618 	 *
7619 	 * If there any entries in the Bios Page 2, then we wait
7620 	 * for discovery to complete.
7621 	 */
7622 
7623 	/* Current Boot Device */
7624 	if ((ioc->bios_pg2.CurrentBootDeviceForm &
7625 	    MPI2_BIOSPAGE2_FORM_MASK) ==
7626 	    MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
7627 	/* Request Boot Device */
7628 	   (ioc->bios_pg2.ReqBootDeviceForm &
7629 	    MPI2_BIOSPAGE2_FORM_MASK) ==
7630 	    MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
7631 	/* Alternate Request Boot Device */
7632 	   (ioc->bios_pg2.ReqAltBootDeviceForm &
7633 	    MPI2_BIOSPAGE2_FORM_MASK) ==
7634 	    MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED)
7635 		return 0;
7636 
7637 	return 1;
7638 }
7639 
7640 /**
7641  * _base_unmask_events - turn on notification for this event
7642  * @ioc: per adapter object
7643  * @event: firmware event
7644  *
7645  * The mask is stored in ioc->event_masks.
7646  */
7647 static void
7648 _base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event)
7649 {
7650 	u32 desired_event;
7651 
7652 	if (event >= 128)
7653 		return;
7654 
7655 	desired_event = (1 << (event % 32));
7656 
7657 	if (event < 32)
7658 		ioc->event_masks[0] &= ~desired_event;
7659 	else if (event < 64)
7660 		ioc->event_masks[1] &= ~desired_event;
7661 	else if (event < 96)
7662 		ioc->event_masks[2] &= ~desired_event;
7663 	else if (event < 128)
7664 		ioc->event_masks[3] &= ~desired_event;
7665 }
7666 
7667 /**
7668  * _base_event_notification - send event notification
7669  * @ioc: per adapter object
7670  *
7671  * Return: 0 for success, non-zero for failure.
7672  */
7673 static int
7674 _base_event_notification(struct MPT3SAS_ADAPTER *ioc)
7675 {
7676 	Mpi2EventNotificationRequest_t *mpi_request;
7677 	u16 smid;
7678 	int r = 0;
7679 	int i, issue_diag_reset = 0;
7680 
7681 	dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7682 
7683 	if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
7684 		ioc_err(ioc, "%s: internal command already in use\n", __func__);
7685 		return -EAGAIN;
7686 	}
7687 
7688 	smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
7689 	if (!smid) {
7690 		ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
7691 		return -EAGAIN;
7692 	}
7693 	ioc->base_cmds.status = MPT3_CMD_PENDING;
7694 	mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
7695 	ioc->base_cmds.smid = smid;
7696 	memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t));
7697 	mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
7698 	mpi_request->VF_ID = 0; /* TODO */
7699 	mpi_request->VP_ID = 0;
7700 	for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
7701 		mpi_request->EventMasks[i] =
7702 		    cpu_to_le32(ioc->event_masks[i]);
7703 	init_completion(&ioc->base_cmds.done);
7704 	ioc->put_smid_default(ioc, smid);
7705 	wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
7706 	if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
7707 		ioc_err(ioc, "%s: timeout\n", __func__);
7708 		_debug_dump_mf(mpi_request,
7709 		    sizeof(Mpi2EventNotificationRequest_t)/4);
7710 		if (ioc->base_cmds.status & MPT3_CMD_RESET)
7711 			r = -EFAULT;
7712 		else
7713 			issue_diag_reset = 1;
7714 
7715 	} else
7716 		dinitprintk(ioc, ioc_info(ioc, "%s: complete\n", __func__));
7717 	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
7718 
7719 	if (issue_diag_reset) {
7720 		if (ioc->drv_internal_flags & MPT_DRV_INTERNAL_FIRST_PE_ISSUED)
7721 			return -EFAULT;
7722 		if (mpt3sas_base_check_for_fault_and_issue_reset(ioc))
7723 			return -EFAULT;
7724 		r = -EAGAIN;
7725 	}
7726 	return r;
7727 }
7728 
7729 /**
7730  * mpt3sas_base_validate_event_type - validating event types
7731  * @ioc: per adapter object
7732  * @event_type: firmware event
7733  *
7734  * This will turn on firmware event notification when application
7735  * ask for that event. We don't mask events that are already enabled.
7736  */
7737 void
7738 mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type)
7739 {
7740 	int i, j;
7741 	u32 event_mask, desired_event;
7742 	u8 send_update_to_fw;
7743 
7744 	for (i = 0, send_update_to_fw = 0; i <
7745 	    MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) {
7746 		event_mask = ~event_type[i];
7747 		desired_event = 1;
7748 		for (j = 0; j < 32; j++) {
7749 			if (!(event_mask & desired_event) &&
7750 			    (ioc->event_masks[i] & desired_event)) {
7751 				ioc->event_masks[i] &= ~desired_event;
7752 				send_update_to_fw = 1;
7753 			}
7754 			desired_event = (desired_event << 1);
7755 		}
7756 	}
7757 
7758 	if (!send_update_to_fw)
7759 		return;
7760 
7761 	mutex_lock(&ioc->base_cmds.mutex);
7762 	_base_event_notification(ioc);
7763 	mutex_unlock(&ioc->base_cmds.mutex);
7764 }
7765 
7766 /**
7767  * _base_diag_reset - the "big hammer" start of day reset
7768  * @ioc: per adapter object
7769  *
7770  * Return: 0 for success, non-zero for failure.
7771  */
7772 static int
7773 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc)
7774 {
7775 	u32 host_diagnostic;
7776 	u32 ioc_state;
7777 	u32 count;
7778 	u32 hcb_size;
7779 
7780 	ioc_info(ioc, "sending diag reset !!\n");
7781 
7782 	pci_cfg_access_lock(ioc->pdev);
7783 
7784 	drsprintk(ioc, ioc_info(ioc, "clear interrupts\n"));
7785 
7786 	count = 0;
7787 	do {
7788 		/* Write magic sequence to WriteSequence register
7789 		 * Loop until in diagnostic mode
7790 		 */
7791 		drsprintk(ioc, ioc_info(ioc, "write magic sequence\n"));
7792 		writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
7793 		writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
7794 		writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
7795 		writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
7796 		writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
7797 		writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
7798 		writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
7799 
7800 		/* wait 100 msec */
7801 		msleep(100);
7802 
7803 		if (count++ > 20) {
7804 			ioc_info(ioc,
7805 			    "Stop writing magic sequence after 20 retries\n");
7806 			_base_dump_reg_set(ioc);
7807 			goto out;
7808 		}
7809 
7810 		host_diagnostic = ioc->base_readl(&ioc->chip->HostDiagnostic);
7811 		drsprintk(ioc,
7812 			  ioc_info(ioc, "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
7813 				   count, host_diagnostic));
7814 
7815 	} while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
7816 
7817 	hcb_size = ioc->base_readl(&ioc->chip->HCBSize);
7818 
7819 	drsprintk(ioc, ioc_info(ioc, "diag reset: issued\n"));
7820 	writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
7821 	     &ioc->chip->HostDiagnostic);
7822 
7823 	/*This delay allows the chip PCIe hardware time to finish reset tasks*/
7824 	msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
7825 
7826 	/* Approximately 300 second max wait */
7827 	for (count = 0; count < (300000000 /
7828 		MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
7829 
7830 		host_diagnostic = ioc->base_readl(&ioc->chip->HostDiagnostic);
7831 
7832 		if (host_diagnostic == 0xFFFFFFFF) {
7833 			ioc_info(ioc,
7834 			    "Invalid host diagnostic register value\n");
7835 			_base_dump_reg_set(ioc);
7836 			goto out;
7837 		}
7838 		if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
7839 			break;
7840 
7841 		msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC / 1000);
7842 	}
7843 
7844 	if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
7845 
7846 		drsprintk(ioc,
7847 			  ioc_info(ioc, "restart the adapter assuming the HCB Address points to good F/W\n"));
7848 		host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
7849 		host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
7850 		writel(host_diagnostic, &ioc->chip->HostDiagnostic);
7851 
7852 		drsprintk(ioc, ioc_info(ioc, "re-enable the HCDW\n"));
7853 		writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
7854 		    &ioc->chip->HCBSize);
7855 	}
7856 
7857 	drsprintk(ioc, ioc_info(ioc, "restart the adapter\n"));
7858 	writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
7859 	    &ioc->chip->HostDiagnostic);
7860 
7861 	drsprintk(ioc,
7862 		  ioc_info(ioc, "disable writes to the diagnostic register\n"));
7863 	writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
7864 
7865 	drsprintk(ioc, ioc_info(ioc, "Wait for FW to go to the READY state\n"));
7866 	ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20);
7867 	if (ioc_state) {
7868 		ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
7869 			__func__, ioc_state);
7870 		_base_dump_reg_set(ioc);
7871 		goto out;
7872 	}
7873 
7874 	pci_cfg_access_unlock(ioc->pdev);
7875 	ioc_info(ioc, "diag reset: SUCCESS\n");
7876 	return 0;
7877 
7878  out:
7879 	pci_cfg_access_unlock(ioc->pdev);
7880 	ioc_err(ioc, "diag reset: FAILED\n");
7881 	return -EFAULT;
7882 }
7883 
7884 /**
7885  * mpt3sas_base_make_ioc_ready - put controller in READY state
7886  * @ioc: per adapter object
7887  * @type: FORCE_BIG_HAMMER or SOFT_RESET
7888  *
7889  * Return: 0 for success, non-zero for failure.
7890  */
7891 int
7892 mpt3sas_base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, enum reset_type type)
7893 {
7894 	u32 ioc_state;
7895 	int rc;
7896 	int count;
7897 
7898 	dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7899 
7900 	if (ioc->pci_error_recovery)
7901 		return 0;
7902 
7903 	ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
7904 	dhsprintk(ioc,
7905 		  ioc_info(ioc, "%s: ioc_state(0x%08x)\n",
7906 			   __func__, ioc_state));
7907 
7908 	/* if in RESET state, it should move to READY state shortly */
7909 	count = 0;
7910 	if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
7911 		while ((ioc_state & MPI2_IOC_STATE_MASK) !=
7912 		    MPI2_IOC_STATE_READY) {
7913 			if (count++ == 10) {
7914 				ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
7915 					__func__, ioc_state);
7916 				return -EFAULT;
7917 			}
7918 			ssleep(1);
7919 			ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
7920 		}
7921 	}
7922 
7923 	if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY)
7924 		return 0;
7925 
7926 	if (ioc_state & MPI2_DOORBELL_USED) {
7927 		ioc_info(ioc, "unexpected doorbell active!\n");
7928 		goto issue_diag_reset;
7929 	}
7930 
7931 	if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
7932 		mpt3sas_print_fault_code(ioc, ioc_state &
7933 		    MPI2_DOORBELL_DATA_MASK);
7934 		goto issue_diag_reset;
7935 	}
7936 
7937 	if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_COREDUMP) {
7938 		/*
7939 		 * if host reset is invoked while watch dog thread is waiting
7940 		 * for IOC state to be changed to Fault state then driver has
7941 		 * to wait here for CoreDump state to clear otherwise reset
7942 		 * will be issued to the FW and FW move the IOC state to
7943 		 * reset state without copying the FW logs to coredump region.
7944 		 */
7945 		if (ioc->ioc_coredump_loop != MPT3SAS_COREDUMP_LOOP_DONE) {
7946 			mpt3sas_print_coredump_info(ioc, ioc_state &
7947 			    MPI2_DOORBELL_DATA_MASK);
7948 			mpt3sas_base_wait_for_coredump_completion(ioc,
7949 			    __func__);
7950 		}
7951 		goto issue_diag_reset;
7952 	}
7953 
7954 	if (type == FORCE_BIG_HAMMER)
7955 		goto issue_diag_reset;
7956 
7957 	if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
7958 		if (!(_base_send_ioc_reset(ioc,
7959 		    MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15))) {
7960 			return 0;
7961 	}
7962 
7963  issue_diag_reset:
7964 	rc = _base_diag_reset(ioc);
7965 	return rc;
7966 }
7967 
7968 /**
7969  * _base_make_ioc_operational - put controller in OPERATIONAL state
7970  * @ioc: per adapter object
7971  *
7972  * Return: 0 for success, non-zero for failure.
7973  */
7974 static int
7975 _base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc)
7976 {
7977 	int r, i, index, rc;
7978 	unsigned long	flags;
7979 	u32 reply_address;
7980 	u16 smid;
7981 	struct _tr_list *delayed_tr, *delayed_tr_next;
7982 	struct _sc_list *delayed_sc, *delayed_sc_next;
7983 	struct _event_ack_list *delayed_event_ack, *delayed_event_ack_next;
7984 	u8 hide_flag;
7985 	struct adapter_reply_queue *reply_q;
7986 	Mpi2ReplyDescriptorsUnion_t *reply_post_free_contig;
7987 
7988 	dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7989 
7990 	/* clean the delayed target reset list */
7991 	list_for_each_entry_safe(delayed_tr, delayed_tr_next,
7992 	    &ioc->delayed_tr_list, list) {
7993 		list_del(&delayed_tr->list);
7994 		kfree(delayed_tr);
7995 	}
7996 
7997 
7998 	list_for_each_entry_safe(delayed_tr, delayed_tr_next,
7999 	    &ioc->delayed_tr_volume_list, list) {
8000 		list_del(&delayed_tr->list);
8001 		kfree(delayed_tr);
8002 	}
8003 
8004 	list_for_each_entry_safe(delayed_sc, delayed_sc_next,
8005 	    &ioc->delayed_sc_list, list) {
8006 		list_del(&delayed_sc->list);
8007 		kfree(delayed_sc);
8008 	}
8009 
8010 	list_for_each_entry_safe(delayed_event_ack, delayed_event_ack_next,
8011 	    &ioc->delayed_event_ack_list, list) {
8012 		list_del(&delayed_event_ack->list);
8013 		kfree(delayed_event_ack);
8014 	}
8015 
8016 	spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
8017 
8018 	/* hi-priority queue */
8019 	INIT_LIST_HEAD(&ioc->hpr_free_list);
8020 	smid = ioc->hi_priority_smid;
8021 	for (i = 0; i < ioc->hi_priority_depth; i++, smid++) {
8022 		ioc->hpr_lookup[i].cb_idx = 0xFF;
8023 		ioc->hpr_lookup[i].smid = smid;
8024 		list_add_tail(&ioc->hpr_lookup[i].tracker_list,
8025 		    &ioc->hpr_free_list);
8026 	}
8027 
8028 	/* internal queue */
8029 	INIT_LIST_HEAD(&ioc->internal_free_list);
8030 	smid = ioc->internal_smid;
8031 	for (i = 0; i < ioc->internal_depth; i++, smid++) {
8032 		ioc->internal_lookup[i].cb_idx = 0xFF;
8033 		ioc->internal_lookup[i].smid = smid;
8034 		list_add_tail(&ioc->internal_lookup[i].tracker_list,
8035 		    &ioc->internal_free_list);
8036 	}
8037 
8038 	spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
8039 
8040 	/* initialize Reply Free Queue */
8041 	for (i = 0, reply_address = (u32)ioc->reply_dma ;
8042 	    i < ioc->reply_free_queue_depth ; i++, reply_address +=
8043 	    ioc->reply_sz) {
8044 		ioc->reply_free[i] = cpu_to_le32(reply_address);
8045 		if (ioc->is_mcpu_endpoint)
8046 			_base_clone_reply_to_sys_mem(ioc,
8047 					reply_address, i);
8048 	}
8049 
8050 	/* initialize reply queues */
8051 	if (ioc->is_driver_loading)
8052 		_base_assign_reply_queues(ioc);
8053 
8054 	/* initialize Reply Post Free Queue */
8055 	index = 0;
8056 	reply_post_free_contig = ioc->reply_post[0].reply_post_free;
8057 	list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
8058 		/*
8059 		 * If RDPQ is enabled, switch to the next allocation.
8060 		 * Otherwise advance within the contiguous region.
8061 		 */
8062 		if (ioc->rdpq_array_enable) {
8063 			reply_q->reply_post_free =
8064 				ioc->reply_post[index++].reply_post_free;
8065 		} else {
8066 			reply_q->reply_post_free = reply_post_free_contig;
8067 			reply_post_free_contig += ioc->reply_post_queue_depth;
8068 		}
8069 
8070 		reply_q->reply_post_host_index = 0;
8071 		for (i = 0; i < ioc->reply_post_queue_depth; i++)
8072 			reply_q->reply_post_free[i].Words =
8073 			    cpu_to_le64(ULLONG_MAX);
8074 		if (!_base_is_controller_msix_enabled(ioc))
8075 			goto skip_init_reply_post_free_queue;
8076 	}
8077  skip_init_reply_post_free_queue:
8078 
8079 	r = _base_send_ioc_init(ioc);
8080 	if (r) {
8081 		/*
8082 		 * No need to check IOC state for fault state & issue
8083 		 * diag reset during host reset. This check is need
8084 		 * only during driver load time.
8085 		 */
8086 		if (!ioc->is_driver_loading)
8087 			return r;
8088 
8089 		rc = mpt3sas_base_check_for_fault_and_issue_reset(ioc);
8090 		if (rc || (_base_send_ioc_init(ioc)))
8091 			return r;
8092 	}
8093 
8094 	/* initialize reply free host index */
8095 	ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
8096 	writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
8097 
8098 	/* initialize reply post host index */
8099 	list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
8100 		if (ioc->combined_reply_queue)
8101 			writel((reply_q->msix_index & 7)<<
8102 			   MPI2_RPHI_MSIX_INDEX_SHIFT,
8103 			   ioc->replyPostRegisterIndex[reply_q->msix_index/8]);
8104 		else
8105 			writel(reply_q->msix_index <<
8106 				MPI2_RPHI_MSIX_INDEX_SHIFT,
8107 				&ioc->chip->ReplyPostHostIndex);
8108 
8109 		if (!_base_is_controller_msix_enabled(ioc))
8110 			goto skip_init_reply_post_host_index;
8111 	}
8112 
8113  skip_init_reply_post_host_index:
8114 
8115 	mpt3sas_base_unmask_interrupts(ioc);
8116 
8117 	if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
8118 		r = _base_display_fwpkg_version(ioc);
8119 		if (r)
8120 			return r;
8121 	}
8122 
8123 	r = _base_static_config_pages(ioc);
8124 	if (r)
8125 		return r;
8126 
8127 	r = _base_event_notification(ioc);
8128 	if (r)
8129 		return r;
8130 
8131 	if (!ioc->shost_recovery) {
8132 
8133 		if (ioc->is_warpdrive && ioc->manu_pg10.OEMIdentifier
8134 		    == 0x80) {
8135 			hide_flag = (u8) (
8136 			    le32_to_cpu(ioc->manu_pg10.OEMSpecificFlags0) &
8137 			    MFG_PAGE10_HIDE_SSDS_MASK);
8138 			if (hide_flag != MFG_PAGE10_HIDE_SSDS_MASK)
8139 				ioc->mfg_pg10_hide_flag = hide_flag;
8140 		}
8141 
8142 		ioc->wait_for_discovery_to_complete =
8143 		    _base_determine_wait_on_discovery(ioc);
8144 
8145 		return r; /* scan_start and scan_finished support */
8146 	}
8147 
8148 	r = _base_send_port_enable(ioc);
8149 	if (r)
8150 		return r;
8151 
8152 	return r;
8153 }
8154 
8155 /**
8156  * mpt3sas_base_free_resources - free resources controller resources
8157  * @ioc: per adapter object
8158  */
8159 void
8160 mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc)
8161 {
8162 	dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
8163 
8164 	/* synchronizing freeing resource with pci_access_mutex lock */
8165 	mutex_lock(&ioc->pci_access_mutex);
8166 	if (ioc->chip_phys && ioc->chip) {
8167 		mpt3sas_base_mask_interrupts(ioc);
8168 		ioc->shost_recovery = 1;
8169 		mpt3sas_base_make_ioc_ready(ioc, SOFT_RESET);
8170 		ioc->shost_recovery = 0;
8171 	}
8172 
8173 	mpt3sas_base_unmap_resources(ioc);
8174 	mutex_unlock(&ioc->pci_access_mutex);
8175 	return;
8176 }
8177 
8178 /**
8179  * mpt3sas_base_attach - attach controller instance
8180  * @ioc: per adapter object
8181  *
8182  * Return: 0 for success, non-zero for failure.
8183  */
8184 int
8185 mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
8186 {
8187 	int r, i, rc;
8188 	int cpu_id, last_cpu_id = 0;
8189 
8190 	dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
8191 
8192 	/* setup cpu_msix_table */
8193 	ioc->cpu_count = num_online_cpus();
8194 	for_each_online_cpu(cpu_id)
8195 		last_cpu_id = cpu_id;
8196 	ioc->cpu_msix_table_sz = last_cpu_id + 1;
8197 	ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL);
8198 	ioc->reply_queue_count = 1;
8199 	if (!ioc->cpu_msix_table) {
8200 		ioc_info(ioc, "Allocation for cpu_msix_table failed!!!\n");
8201 		r = -ENOMEM;
8202 		goto out_free_resources;
8203 	}
8204 
8205 	if (ioc->is_warpdrive) {
8206 		ioc->reply_post_host_index = kcalloc(ioc->cpu_msix_table_sz,
8207 		    sizeof(resource_size_t *), GFP_KERNEL);
8208 		if (!ioc->reply_post_host_index) {
8209 			ioc_info(ioc, "Allocation for reply_post_host_index failed!!!\n");
8210 			r = -ENOMEM;
8211 			goto out_free_resources;
8212 		}
8213 	}
8214 
8215 	ioc->smp_affinity_enable = smp_affinity_enable;
8216 
8217 	ioc->rdpq_array_enable_assigned = 0;
8218 	ioc->use_32bit_dma = false;
8219 	ioc->dma_mask = 64;
8220 	if (ioc->is_aero_ioc)
8221 		ioc->base_readl = &_base_readl_aero;
8222 	else
8223 		ioc->base_readl = &_base_readl;
8224 	r = mpt3sas_base_map_resources(ioc);
8225 	if (r)
8226 		goto out_free_resources;
8227 
8228 	pci_set_drvdata(ioc->pdev, ioc->shost);
8229 	r = _base_get_ioc_facts(ioc);
8230 	if (r) {
8231 		rc = mpt3sas_base_check_for_fault_and_issue_reset(ioc);
8232 		if (rc || (_base_get_ioc_facts(ioc)))
8233 			goto out_free_resources;
8234 	}
8235 
8236 	switch (ioc->hba_mpi_version_belonged) {
8237 	case MPI2_VERSION:
8238 		ioc->build_sg_scmd = &_base_build_sg_scmd;
8239 		ioc->build_sg = &_base_build_sg;
8240 		ioc->build_zero_len_sge = &_base_build_zero_len_sge;
8241 		ioc->get_msix_index_for_smlio = &_base_get_msix_index;
8242 		break;
8243 	case MPI25_VERSION:
8244 	case MPI26_VERSION:
8245 		/*
8246 		 * In SAS3.0,
8247 		 * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and
8248 		 * Target Status - all require the IEEE formatted scatter gather
8249 		 * elements.
8250 		 */
8251 		ioc->build_sg_scmd = &_base_build_sg_scmd_ieee;
8252 		ioc->build_sg = &_base_build_sg_ieee;
8253 		ioc->build_nvme_prp = &_base_build_nvme_prp;
8254 		ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee;
8255 		ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t);
8256 		if (ioc->high_iops_queues)
8257 			ioc->get_msix_index_for_smlio =
8258 					&_base_get_high_iops_msix_index;
8259 		else
8260 			ioc->get_msix_index_for_smlio = &_base_get_msix_index;
8261 		break;
8262 	}
8263 	if (ioc->atomic_desc_capable) {
8264 		ioc->put_smid_default = &_base_put_smid_default_atomic;
8265 		ioc->put_smid_scsi_io = &_base_put_smid_scsi_io_atomic;
8266 		ioc->put_smid_fast_path =
8267 				&_base_put_smid_fast_path_atomic;
8268 		ioc->put_smid_hi_priority =
8269 				&_base_put_smid_hi_priority_atomic;
8270 	} else {
8271 		ioc->put_smid_default = &_base_put_smid_default;
8272 		ioc->put_smid_fast_path = &_base_put_smid_fast_path;
8273 		ioc->put_smid_hi_priority = &_base_put_smid_hi_priority;
8274 		if (ioc->is_mcpu_endpoint)
8275 			ioc->put_smid_scsi_io =
8276 				&_base_put_smid_mpi_ep_scsi_io;
8277 		else
8278 			ioc->put_smid_scsi_io = &_base_put_smid_scsi_io;
8279 	}
8280 	/*
8281 	 * These function pointers for other requests that don't
8282 	 * the require IEEE scatter gather elements.
8283 	 *
8284 	 * For example Configuration Pages and SAS IOUNIT Control don't.
8285 	 */
8286 	ioc->build_sg_mpi = &_base_build_sg;
8287 	ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge;
8288 
8289 	r = mpt3sas_base_make_ioc_ready(ioc, SOFT_RESET);
8290 	if (r)
8291 		goto out_free_resources;
8292 
8293 	ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts,
8294 	    sizeof(struct mpt3sas_port_facts), GFP_KERNEL);
8295 	if (!ioc->pfacts) {
8296 		r = -ENOMEM;
8297 		goto out_free_resources;
8298 	}
8299 
8300 	for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
8301 		r = _base_get_port_facts(ioc, i);
8302 		if (r) {
8303 			rc = mpt3sas_base_check_for_fault_and_issue_reset(ioc);
8304 			if (rc || (_base_get_port_facts(ioc, i)))
8305 				goto out_free_resources;
8306 		}
8307 	}
8308 
8309 	r = _base_allocate_memory_pools(ioc);
8310 	if (r)
8311 		goto out_free_resources;
8312 
8313 	if (irqpoll_weight > 0)
8314 		ioc->thresh_hold = irqpoll_weight;
8315 	else
8316 		ioc->thresh_hold = ioc->hba_queue_depth/4;
8317 
8318 	_base_init_irqpolls(ioc);
8319 	init_waitqueue_head(&ioc->reset_wq);
8320 
8321 	/* allocate memory pd handle bitmask list */
8322 	ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
8323 	if (ioc->facts.MaxDevHandle % 8)
8324 		ioc->pd_handles_sz++;
8325 	ioc->pd_handles = kzalloc(ioc->pd_handles_sz,
8326 	    GFP_KERNEL);
8327 	if (!ioc->pd_handles) {
8328 		r = -ENOMEM;
8329 		goto out_free_resources;
8330 	}
8331 	ioc->blocking_handles = kzalloc(ioc->pd_handles_sz,
8332 	    GFP_KERNEL);
8333 	if (!ioc->blocking_handles) {
8334 		r = -ENOMEM;
8335 		goto out_free_resources;
8336 	}
8337 
8338 	/* allocate memory for pending OS device add list */
8339 	ioc->pend_os_device_add_sz = (ioc->facts.MaxDevHandle / 8);
8340 	if (ioc->facts.MaxDevHandle % 8)
8341 		ioc->pend_os_device_add_sz++;
8342 	ioc->pend_os_device_add = kzalloc(ioc->pend_os_device_add_sz,
8343 	    GFP_KERNEL);
8344 	if (!ioc->pend_os_device_add) {
8345 		r = -ENOMEM;
8346 		goto out_free_resources;
8347 	}
8348 
8349 	ioc->device_remove_in_progress_sz = ioc->pend_os_device_add_sz;
8350 	ioc->device_remove_in_progress =
8351 		kzalloc(ioc->device_remove_in_progress_sz, GFP_KERNEL);
8352 	if (!ioc->device_remove_in_progress) {
8353 		r = -ENOMEM;
8354 		goto out_free_resources;
8355 	}
8356 
8357 	ioc->fwfault_debug = mpt3sas_fwfault_debug;
8358 
8359 	/* base internal command bits */
8360 	mutex_init(&ioc->base_cmds.mutex);
8361 	ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
8362 	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
8363 
8364 	/* port_enable command bits */
8365 	ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
8366 	ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
8367 
8368 	/* transport internal command bits */
8369 	ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
8370 	ioc->transport_cmds.status = MPT3_CMD_NOT_USED;
8371 	mutex_init(&ioc->transport_cmds.mutex);
8372 
8373 	/* scsih internal command bits */
8374 	ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
8375 	ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
8376 	mutex_init(&ioc->scsih_cmds.mutex);
8377 
8378 	/* task management internal command bits */
8379 	ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
8380 	ioc->tm_cmds.status = MPT3_CMD_NOT_USED;
8381 	mutex_init(&ioc->tm_cmds.mutex);
8382 
8383 	/* config page internal command bits */
8384 	ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
8385 	ioc->config_cmds.status = MPT3_CMD_NOT_USED;
8386 	mutex_init(&ioc->config_cmds.mutex);
8387 
8388 	/* ctl module internal command bits */
8389 	ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
8390 	ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
8391 	ioc->ctl_cmds.status = MPT3_CMD_NOT_USED;
8392 	mutex_init(&ioc->ctl_cmds.mutex);
8393 
8394 	if (!ioc->base_cmds.reply || !ioc->port_enable_cmds.reply ||
8395 	    !ioc->transport_cmds.reply || !ioc->scsih_cmds.reply ||
8396 	    !ioc->tm_cmds.reply || !ioc->config_cmds.reply ||
8397 	    !ioc->ctl_cmds.reply || !ioc->ctl_cmds.sense) {
8398 		r = -ENOMEM;
8399 		goto out_free_resources;
8400 	}
8401 
8402 	for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
8403 		ioc->event_masks[i] = -1;
8404 
8405 	/* here we enable the events we care about */
8406 	_base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY);
8407 	_base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE);
8408 	_base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
8409 	_base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE);
8410 	_base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE);
8411 	_base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST);
8412 	_base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME);
8413 	_base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK);
8414 	_base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS);
8415 	_base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED);
8416 	_base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD);
8417 	_base_unmask_events(ioc, MPI2_EVENT_ACTIVE_CABLE_EXCEPTION);
8418 	_base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR);
8419 	if (ioc->hba_mpi_version_belonged == MPI26_VERSION) {
8420 		if (ioc->is_gen35_ioc) {
8421 			_base_unmask_events(ioc,
8422 				MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE);
8423 			_base_unmask_events(ioc, MPI2_EVENT_PCIE_ENUMERATION);
8424 			_base_unmask_events(ioc,
8425 				MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST);
8426 		}
8427 	}
8428 	r = _base_make_ioc_operational(ioc);
8429 	if (r == -EAGAIN) {
8430 		r = _base_make_ioc_operational(ioc);
8431 		if (r)
8432 			goto out_free_resources;
8433 	}
8434 
8435 	/*
8436 	 * Copy current copy of IOCFacts in prev_fw_facts
8437 	 * and it will be used during online firmware upgrade.
8438 	 */
8439 	memcpy(&ioc->prev_fw_facts, &ioc->facts,
8440 	    sizeof(struct mpt3sas_facts));
8441 
8442 	ioc->non_operational_loop = 0;
8443 	ioc->ioc_coredump_loop = 0;
8444 	ioc->got_task_abort_from_ioctl = 0;
8445 	return 0;
8446 
8447  out_free_resources:
8448 
8449 	ioc->remove_host = 1;
8450 
8451 	mpt3sas_base_free_resources(ioc);
8452 	_base_release_memory_pools(ioc);
8453 	pci_set_drvdata(ioc->pdev, NULL);
8454 	kfree(ioc->cpu_msix_table);
8455 	if (ioc->is_warpdrive)
8456 		kfree(ioc->reply_post_host_index);
8457 	kfree(ioc->pd_handles);
8458 	kfree(ioc->blocking_handles);
8459 	kfree(ioc->device_remove_in_progress);
8460 	kfree(ioc->pend_os_device_add);
8461 	kfree(ioc->tm_cmds.reply);
8462 	kfree(ioc->transport_cmds.reply);
8463 	kfree(ioc->scsih_cmds.reply);
8464 	kfree(ioc->config_cmds.reply);
8465 	kfree(ioc->base_cmds.reply);
8466 	kfree(ioc->port_enable_cmds.reply);
8467 	kfree(ioc->ctl_cmds.reply);
8468 	kfree(ioc->ctl_cmds.sense);
8469 	kfree(ioc->pfacts);
8470 	ioc->ctl_cmds.reply = NULL;
8471 	ioc->base_cmds.reply = NULL;
8472 	ioc->tm_cmds.reply = NULL;
8473 	ioc->scsih_cmds.reply = NULL;
8474 	ioc->transport_cmds.reply = NULL;
8475 	ioc->config_cmds.reply = NULL;
8476 	ioc->pfacts = NULL;
8477 	return r;
8478 }
8479 
8480 
8481 /**
8482  * mpt3sas_base_detach - remove controller instance
8483  * @ioc: per adapter object
8484  */
8485 void
8486 mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc)
8487 {
8488 	dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
8489 
8490 	mpt3sas_base_stop_watchdog(ioc);
8491 	mpt3sas_base_free_resources(ioc);
8492 	_base_release_memory_pools(ioc);
8493 	mpt3sas_free_enclosure_list(ioc);
8494 	pci_set_drvdata(ioc->pdev, NULL);
8495 	kfree(ioc->cpu_msix_table);
8496 	if (ioc->is_warpdrive)
8497 		kfree(ioc->reply_post_host_index);
8498 	kfree(ioc->pd_handles);
8499 	kfree(ioc->blocking_handles);
8500 	kfree(ioc->device_remove_in_progress);
8501 	kfree(ioc->pend_os_device_add);
8502 	kfree(ioc->pfacts);
8503 	kfree(ioc->ctl_cmds.reply);
8504 	kfree(ioc->ctl_cmds.sense);
8505 	kfree(ioc->base_cmds.reply);
8506 	kfree(ioc->port_enable_cmds.reply);
8507 	kfree(ioc->tm_cmds.reply);
8508 	kfree(ioc->transport_cmds.reply);
8509 	kfree(ioc->scsih_cmds.reply);
8510 	kfree(ioc->config_cmds.reply);
8511 }
8512 
8513 /**
8514  * _base_pre_reset_handler - pre reset handler
8515  * @ioc: per adapter object
8516  */
8517 static void _base_pre_reset_handler(struct MPT3SAS_ADAPTER *ioc)
8518 {
8519 	mpt3sas_scsih_pre_reset_handler(ioc);
8520 	mpt3sas_ctl_pre_reset_handler(ioc);
8521 	dtmprintk(ioc, ioc_info(ioc, "%s: MPT3_IOC_PRE_RESET\n", __func__));
8522 }
8523 
8524 /**
8525  * _base_clear_outstanding_mpt_commands - clears outstanding mpt commands
8526  * @ioc: per adapter object
8527  */
8528 static void
8529 _base_clear_outstanding_mpt_commands(struct MPT3SAS_ADAPTER *ioc)
8530 {
8531 	dtmprintk(ioc,
8532 	    ioc_info(ioc, "%s: clear outstanding mpt cmds\n", __func__));
8533 	if (ioc->transport_cmds.status & MPT3_CMD_PENDING) {
8534 		ioc->transport_cmds.status |= MPT3_CMD_RESET;
8535 		mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid);
8536 		complete(&ioc->transport_cmds.done);
8537 	}
8538 	if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
8539 		ioc->base_cmds.status |= MPT3_CMD_RESET;
8540 		mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid);
8541 		complete(&ioc->base_cmds.done);
8542 	}
8543 	if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
8544 		ioc->port_enable_failed = 1;
8545 		ioc->port_enable_cmds.status |= MPT3_CMD_RESET;
8546 		mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid);
8547 		if (ioc->is_driver_loading) {
8548 			ioc->start_scan_failed =
8549 				MPI2_IOCSTATUS_INTERNAL_ERROR;
8550 			ioc->start_scan = 0;
8551 		} else {
8552 			complete(&ioc->port_enable_cmds.done);
8553 		}
8554 	}
8555 	if (ioc->config_cmds.status & MPT3_CMD_PENDING) {
8556 		ioc->config_cmds.status |= MPT3_CMD_RESET;
8557 		mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid);
8558 		ioc->config_cmds.smid = USHRT_MAX;
8559 		complete(&ioc->config_cmds.done);
8560 	}
8561 }
8562 
8563 /**
8564  * _base_clear_outstanding_commands - clear all outstanding commands
8565  * @ioc: per adapter object
8566  */
8567 static void _base_clear_outstanding_commands(struct MPT3SAS_ADAPTER *ioc)
8568 {
8569 	mpt3sas_scsih_clear_outstanding_scsi_tm_commands(ioc);
8570 	mpt3sas_ctl_clear_outstanding_ioctls(ioc);
8571 	_base_clear_outstanding_mpt_commands(ioc);
8572 }
8573 
8574 /**
8575  * _base_reset_done_handler - reset done handler
8576  * @ioc: per adapter object
8577  */
8578 static void _base_reset_done_handler(struct MPT3SAS_ADAPTER *ioc)
8579 {
8580 	mpt3sas_scsih_reset_done_handler(ioc);
8581 	mpt3sas_ctl_reset_done_handler(ioc);
8582 	dtmprintk(ioc, ioc_info(ioc, "%s: MPT3_IOC_DONE_RESET\n", __func__));
8583 }
8584 
8585 /**
8586  * mpt3sas_wait_for_commands_to_complete - reset controller
8587  * @ioc: Pointer to MPT_ADAPTER structure
8588  *
8589  * This function is waiting 10s for all pending commands to complete
8590  * prior to putting controller in reset.
8591  */
8592 void
8593 mpt3sas_wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc)
8594 {
8595 	u32 ioc_state;
8596 
8597 	ioc->pending_io_count = 0;
8598 
8599 	ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
8600 	if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL)
8601 		return;
8602 
8603 	/* pending command count */
8604 	ioc->pending_io_count = scsi_host_busy(ioc->shost);
8605 
8606 	if (!ioc->pending_io_count)
8607 		return;
8608 
8609 	/* wait for pending commands to complete */
8610 	wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ);
8611 }
8612 
8613 /**
8614  * _base_check_ioc_facts_changes - Look for increase/decrease of IOCFacts
8615  *     attributes during online firmware upgrade and update the corresponding
8616  *     IOC variables accordingly.
8617  *
8618  * @ioc: Pointer to MPT_ADAPTER structure
8619  */
8620 static int
8621 _base_check_ioc_facts_changes(struct MPT3SAS_ADAPTER *ioc)
8622 {
8623 	u16 pd_handles_sz;
8624 	void *pd_handles = NULL, *blocking_handles = NULL;
8625 	void *pend_os_device_add = NULL, *device_remove_in_progress = NULL;
8626 	struct mpt3sas_facts *old_facts = &ioc->prev_fw_facts;
8627 
8628 	if (ioc->facts.MaxDevHandle > old_facts->MaxDevHandle) {
8629 		pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
8630 		if (ioc->facts.MaxDevHandle % 8)
8631 			pd_handles_sz++;
8632 
8633 		pd_handles = krealloc(ioc->pd_handles, pd_handles_sz,
8634 		    GFP_KERNEL);
8635 		if (!pd_handles) {
8636 			ioc_info(ioc,
8637 			    "Unable to allocate the memory for pd_handles of sz: %d\n",
8638 			    pd_handles_sz);
8639 			return -ENOMEM;
8640 		}
8641 		memset(pd_handles + ioc->pd_handles_sz, 0,
8642 		    (pd_handles_sz - ioc->pd_handles_sz));
8643 		ioc->pd_handles = pd_handles;
8644 
8645 		blocking_handles = krealloc(ioc->blocking_handles,
8646 		    pd_handles_sz, GFP_KERNEL);
8647 		if (!blocking_handles) {
8648 			ioc_info(ioc,
8649 			    "Unable to allocate the memory for "
8650 			    "blocking_handles of sz: %d\n",
8651 			    pd_handles_sz);
8652 			return -ENOMEM;
8653 		}
8654 		memset(blocking_handles + ioc->pd_handles_sz, 0,
8655 		    (pd_handles_sz - ioc->pd_handles_sz));
8656 		ioc->blocking_handles = blocking_handles;
8657 		ioc->pd_handles_sz = pd_handles_sz;
8658 
8659 		pend_os_device_add = krealloc(ioc->pend_os_device_add,
8660 		    pd_handles_sz, GFP_KERNEL);
8661 		if (!pend_os_device_add) {
8662 			ioc_info(ioc,
8663 			    "Unable to allocate the memory for pend_os_device_add of sz: %d\n",
8664 			    pd_handles_sz);
8665 			return -ENOMEM;
8666 		}
8667 		memset(pend_os_device_add + ioc->pend_os_device_add_sz, 0,
8668 		    (pd_handles_sz - ioc->pend_os_device_add_sz));
8669 		ioc->pend_os_device_add = pend_os_device_add;
8670 		ioc->pend_os_device_add_sz = pd_handles_sz;
8671 
8672 		device_remove_in_progress = krealloc(
8673 		    ioc->device_remove_in_progress, pd_handles_sz, GFP_KERNEL);
8674 		if (!device_remove_in_progress) {
8675 			ioc_info(ioc,
8676 			    "Unable to allocate the memory for "
8677 			    "device_remove_in_progress of sz: %d\n "
8678 			    , pd_handles_sz);
8679 			return -ENOMEM;
8680 		}
8681 		memset(device_remove_in_progress +
8682 		    ioc->device_remove_in_progress_sz, 0,
8683 		    (pd_handles_sz - ioc->device_remove_in_progress_sz));
8684 		ioc->device_remove_in_progress = device_remove_in_progress;
8685 		ioc->device_remove_in_progress_sz = pd_handles_sz;
8686 	}
8687 
8688 	memcpy(&ioc->prev_fw_facts, &ioc->facts, sizeof(struct mpt3sas_facts));
8689 	return 0;
8690 }
8691 
8692 /**
8693  * mpt3sas_base_hard_reset_handler - reset controller
8694  * @ioc: Pointer to MPT_ADAPTER structure
8695  * @type: FORCE_BIG_HAMMER or SOFT_RESET
8696  *
8697  * Return: 0 for success, non-zero for failure.
8698  */
8699 int
8700 mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc,
8701 	enum reset_type type)
8702 {
8703 	int r;
8704 	unsigned long flags;
8705 	u32 ioc_state;
8706 	u8 is_fault = 0, is_trigger = 0;
8707 
8708 	dtmprintk(ioc, ioc_info(ioc, "%s: enter\n", __func__));
8709 
8710 	if (ioc->pci_error_recovery) {
8711 		ioc_err(ioc, "%s: pci error recovery reset\n", __func__);
8712 		r = 0;
8713 		goto out_unlocked;
8714 	}
8715 
8716 	if (mpt3sas_fwfault_debug)
8717 		mpt3sas_halt_firmware(ioc);
8718 
8719 	/* wait for an active reset in progress to complete */
8720 	mutex_lock(&ioc->reset_in_progress_mutex);
8721 
8722 	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
8723 	ioc->shost_recovery = 1;
8724 	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
8725 
8726 	if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
8727 	    MPT3_DIAG_BUFFER_IS_REGISTERED) &&
8728 	    (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
8729 	    MPT3_DIAG_BUFFER_IS_RELEASED))) {
8730 		is_trigger = 1;
8731 		ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
8732 		if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT ||
8733 		    (ioc_state & MPI2_IOC_STATE_MASK) ==
8734 		    MPI2_IOC_STATE_COREDUMP) {
8735 			is_fault = 1;
8736 			ioc->htb_rel.trigger_info_dwords[1] =
8737 			    (ioc_state & MPI2_DOORBELL_DATA_MASK);
8738 		}
8739 	}
8740 	_base_pre_reset_handler(ioc);
8741 	mpt3sas_wait_for_commands_to_complete(ioc);
8742 	mpt3sas_base_mask_interrupts(ioc);
8743 	mpt3sas_base_pause_mq_polling(ioc);
8744 	r = mpt3sas_base_make_ioc_ready(ioc, type);
8745 	if (r)
8746 		goto out;
8747 	_base_clear_outstanding_commands(ioc);
8748 
8749 	/* If this hard reset is called while port enable is active, then
8750 	 * there is no reason to call make_ioc_operational
8751 	 */
8752 	if (ioc->is_driver_loading && ioc->port_enable_failed) {
8753 		ioc->remove_host = 1;
8754 		r = -EFAULT;
8755 		goto out;
8756 	}
8757 	r = _base_get_ioc_facts(ioc);
8758 	if (r)
8759 		goto out;
8760 
8761 	r = _base_check_ioc_facts_changes(ioc);
8762 	if (r) {
8763 		ioc_info(ioc,
8764 		    "Some of the parameters got changed in this new firmware"
8765 		    " image and it requires system reboot\n");
8766 		goto out;
8767 	}
8768 	if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable)
8769 		panic("%s: Issue occurred with flashing controller firmware."
8770 		      "Please reboot the system and ensure that the correct"
8771 		      " firmware version is running\n", ioc->name);
8772 
8773 	r = _base_make_ioc_operational(ioc);
8774 	if (!r)
8775 		_base_reset_done_handler(ioc);
8776 
8777  out:
8778 	ioc_info(ioc, "%s: %s\n", __func__, r == 0 ? "SUCCESS" : "FAILED");
8779 
8780 	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
8781 	ioc->shost_recovery = 0;
8782 	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
8783 	ioc->ioc_reset_count++;
8784 	mutex_unlock(&ioc->reset_in_progress_mutex);
8785 	mpt3sas_base_resume_mq_polling(ioc);
8786 
8787  out_unlocked:
8788 	if ((r == 0) && is_trigger) {
8789 		if (is_fault)
8790 			mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT);
8791 		else
8792 			mpt3sas_trigger_master(ioc,
8793 			    MASTER_TRIGGER_ADAPTER_RESET);
8794 	}
8795 	dtmprintk(ioc, ioc_info(ioc, "%s: exit\n", __func__));
8796 	return r;
8797 }
8798