1 /* 2 * This is the Fusion MPT base driver providing common API layer interface 3 * for access to MPT (Message Passing Technology) firmware. 4 * 5 * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c 6 * Copyright (C) 2012-2014 LSI Corporation 7 * Copyright (C) 2013-2014 Avago Technologies 8 * (mailto: MPT-FusionLinux.pdl@avagotech.com) 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 2 13 * of the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * NO WARRANTY 21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR 22 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT 23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, 24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is 25 * solely responsible for determining the appropriateness of using and 26 * distributing the Program and assumes all risks associated with its 27 * exercise of rights under this Agreement, including but not limited to 28 * the risks and costs of program errors, damage to or loss of data, 29 * programs or equipment, and unavailability or interruption of operations. 30 31 * DISCLAIMER OF LIABILITY 32 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY 33 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND 35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 36 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 37 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED 38 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES 39 40 * You should have received a copy of the GNU General Public License 41 * along with this program; if not, write to the Free Software 42 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, 43 * USA. 44 */ 45 46 #include <linux/kernel.h> 47 #include <linux/module.h> 48 #include <linux/errno.h> 49 #include <linux/init.h> 50 #include <linux/slab.h> 51 #include <linux/types.h> 52 #include <linux/pci.h> 53 #include <linux/kdev_t.h> 54 #include <linux/blkdev.h> 55 #include <linux/delay.h> 56 #include <linux/interrupt.h> 57 #include <linux/dma-mapping.h> 58 #include <linux/io.h> 59 #include <linux/time.h> 60 #include <linux/ktime.h> 61 #include <linux/kthread.h> 62 #include <linux/aer.h> 63 64 65 #include "mpt3sas_base.h" 66 67 static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS]; 68 69 70 #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */ 71 72 /* maximum controller queue depth */ 73 #define MAX_HBA_QUEUE_DEPTH 30000 74 #define MAX_CHAIN_DEPTH 100000 75 static int max_queue_depth = -1; 76 module_param(max_queue_depth, int, 0); 77 MODULE_PARM_DESC(max_queue_depth, " max controller queue depth "); 78 79 static int max_sgl_entries = -1; 80 module_param(max_sgl_entries, int, 0); 81 MODULE_PARM_DESC(max_sgl_entries, " max sg entries "); 82 83 static int msix_disable = -1; 84 module_param(msix_disable, int, 0); 85 MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)"); 86 87 static int smp_affinity_enable = 1; 88 module_param(smp_affinity_enable, int, S_IRUGO); 89 MODULE_PARM_DESC(smp_affinity_enable, "SMP affinity feature enable/disbale Default: enable(1)"); 90 91 static int max_msix_vectors = -1; 92 module_param(max_msix_vectors, int, 0); 93 MODULE_PARM_DESC(max_msix_vectors, 94 " max msix vectors"); 95 96 static int mpt3sas_fwfault_debug; 97 MODULE_PARM_DESC(mpt3sas_fwfault_debug, 98 " enable detection of firmware fault and halt firmware - (default=0)"); 99 100 static int 101 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc); 102 103 /** 104 * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug. 105 * 106 */ 107 static int 108 _scsih_set_fwfault_debug(const char *val, struct kernel_param *kp) 109 { 110 int ret = param_set_int(val, kp); 111 struct MPT3SAS_ADAPTER *ioc; 112 113 if (ret) 114 return ret; 115 116 /* global ioc spinlock to protect controller list on list operations */ 117 pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug); 118 spin_lock(&gioc_lock); 119 list_for_each_entry(ioc, &mpt3sas_ioc_list, list) 120 ioc->fwfault_debug = mpt3sas_fwfault_debug; 121 spin_unlock(&gioc_lock); 122 return 0; 123 } 124 module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug, 125 param_get_int, &mpt3sas_fwfault_debug, 0644); 126 127 /** 128 * mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc 129 * @arg: input argument, used to derive ioc 130 * 131 * Return 0 if controller is removed from pci subsystem. 132 * Return -1 for other case. 133 */ 134 static int mpt3sas_remove_dead_ioc_func(void *arg) 135 { 136 struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg; 137 struct pci_dev *pdev; 138 139 if ((ioc == NULL)) 140 return -1; 141 142 pdev = ioc->pdev; 143 if ((pdev == NULL)) 144 return -1; 145 pci_stop_and_remove_bus_device_locked(pdev); 146 return 0; 147 } 148 149 /** 150 * _base_fault_reset_work - workq handling ioc fault conditions 151 * @work: input argument, used to derive ioc 152 * Context: sleep. 153 * 154 * Return nothing. 155 */ 156 static void 157 _base_fault_reset_work(struct work_struct *work) 158 { 159 struct MPT3SAS_ADAPTER *ioc = 160 container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work); 161 unsigned long flags; 162 u32 doorbell; 163 int rc; 164 struct task_struct *p; 165 166 167 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 168 if (ioc->shost_recovery || ioc->pci_error_recovery) 169 goto rearm_timer; 170 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 171 172 doorbell = mpt3sas_base_get_iocstate(ioc, 0); 173 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) { 174 pr_err(MPT3SAS_FMT "SAS host is non-operational !!!!\n", 175 ioc->name); 176 177 /* It may be possible that EEH recovery can resolve some of 178 * pci bus failure issues rather removing the dead ioc function 179 * by considering controller is in a non-operational state. So 180 * here priority is given to the EEH recovery. If it doesn't 181 * not resolve this issue, mpt3sas driver will consider this 182 * controller to non-operational state and remove the dead ioc 183 * function. 184 */ 185 if (ioc->non_operational_loop++ < 5) { 186 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, 187 flags); 188 goto rearm_timer; 189 } 190 191 /* 192 * Call _scsih_flush_pending_cmds callback so that we flush all 193 * pending commands back to OS. This call is required to aovid 194 * deadlock at block layer. Dead IOC will fail to do diag reset, 195 * and this call is safe since dead ioc will never return any 196 * command back from HW. 197 */ 198 ioc->schedule_dead_ioc_flush_running_cmds(ioc); 199 /* 200 * Set remove_host flag early since kernel thread will 201 * take some time to execute. 202 */ 203 ioc->remove_host = 1; 204 /*Remove the Dead Host */ 205 p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc, 206 "%s_dead_ioc_%d", ioc->driver_name, ioc->id); 207 if (IS_ERR(p)) 208 pr_err(MPT3SAS_FMT 209 "%s: Running mpt3sas_dead_ioc thread failed !!!!\n", 210 ioc->name, __func__); 211 else 212 pr_err(MPT3SAS_FMT 213 "%s: Running mpt3sas_dead_ioc thread success !!!!\n", 214 ioc->name, __func__); 215 return; /* don't rearm timer */ 216 } 217 218 ioc->non_operational_loop = 0; 219 220 if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) { 221 rc = mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER); 222 pr_warn(MPT3SAS_FMT "%s: hard reset: %s\n", ioc->name, 223 __func__, (rc == 0) ? "success" : "failed"); 224 doorbell = mpt3sas_base_get_iocstate(ioc, 0); 225 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) 226 mpt3sas_base_fault_info(ioc, doorbell & 227 MPI2_DOORBELL_DATA_MASK); 228 if (rc && (doorbell & MPI2_IOC_STATE_MASK) != 229 MPI2_IOC_STATE_OPERATIONAL) 230 return; /* don't rearm timer */ 231 } 232 233 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 234 rearm_timer: 235 if (ioc->fault_reset_work_q) 236 queue_delayed_work(ioc->fault_reset_work_q, 237 &ioc->fault_reset_work, 238 msecs_to_jiffies(FAULT_POLLING_INTERVAL)); 239 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 240 } 241 242 /** 243 * mpt3sas_base_start_watchdog - start the fault_reset_work_q 244 * @ioc: per adapter object 245 * Context: sleep. 246 * 247 * Return nothing. 248 */ 249 void 250 mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc) 251 { 252 unsigned long flags; 253 254 if (ioc->fault_reset_work_q) 255 return; 256 257 /* initialize fault polling */ 258 259 INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work); 260 snprintf(ioc->fault_reset_work_q_name, 261 sizeof(ioc->fault_reset_work_q_name), "poll_%s%d_status", 262 ioc->driver_name, ioc->id); 263 ioc->fault_reset_work_q = 264 create_singlethread_workqueue(ioc->fault_reset_work_q_name); 265 if (!ioc->fault_reset_work_q) { 266 pr_err(MPT3SAS_FMT "%s: failed (line=%d)\n", 267 ioc->name, __func__, __LINE__); 268 return; 269 } 270 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 271 if (ioc->fault_reset_work_q) 272 queue_delayed_work(ioc->fault_reset_work_q, 273 &ioc->fault_reset_work, 274 msecs_to_jiffies(FAULT_POLLING_INTERVAL)); 275 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 276 } 277 278 /** 279 * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q 280 * @ioc: per adapter object 281 * Context: sleep. 282 * 283 * Return nothing. 284 */ 285 void 286 mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc) 287 { 288 unsigned long flags; 289 struct workqueue_struct *wq; 290 291 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 292 wq = ioc->fault_reset_work_q; 293 ioc->fault_reset_work_q = NULL; 294 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 295 if (wq) { 296 if (!cancel_delayed_work_sync(&ioc->fault_reset_work)) 297 flush_workqueue(wq); 298 destroy_workqueue(wq); 299 } 300 } 301 302 /** 303 * mpt3sas_base_fault_info - verbose translation of firmware FAULT code 304 * @ioc: per adapter object 305 * @fault_code: fault code 306 * 307 * Return nothing. 308 */ 309 void 310 mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code) 311 { 312 pr_err(MPT3SAS_FMT "fault_state(0x%04x)!\n", 313 ioc->name, fault_code); 314 } 315 316 /** 317 * mpt3sas_halt_firmware - halt's mpt controller firmware 318 * @ioc: per adapter object 319 * 320 * For debugging timeout related issues. Writing 0xCOFFEE00 321 * to the doorbell register will halt controller firmware. With 322 * the purpose to stop both driver and firmware, the enduser can 323 * obtain a ring buffer from controller UART. 324 */ 325 void 326 mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc) 327 { 328 u32 doorbell; 329 330 if (!ioc->fwfault_debug) 331 return; 332 333 dump_stack(); 334 335 doorbell = readl(&ioc->chip->Doorbell); 336 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) 337 mpt3sas_base_fault_info(ioc , doorbell); 338 else { 339 writel(0xC0FFEE00, &ioc->chip->Doorbell); 340 pr_err(MPT3SAS_FMT "Firmware is halted due to command timeout\n", 341 ioc->name); 342 } 343 344 if (ioc->fwfault_debug == 2) 345 for (;;) 346 ; 347 else 348 panic("panic in %s\n", __func__); 349 } 350 351 /** 352 * _base_sas_ioc_info - verbose translation of the ioc status 353 * @ioc: per adapter object 354 * @mpi_reply: reply mf payload returned from firmware 355 * @request_hdr: request mf 356 * 357 * Return nothing. 358 */ 359 static void 360 _base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply, 361 MPI2RequestHeader_t *request_hdr) 362 { 363 u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & 364 MPI2_IOCSTATUS_MASK; 365 char *desc = NULL; 366 u16 frame_sz; 367 char *func_str = NULL; 368 369 /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */ 370 if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST || 371 request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH || 372 request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION) 373 return; 374 375 if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE) 376 return; 377 378 switch (ioc_status) { 379 380 /**************************************************************************** 381 * Common IOCStatus values for all replies 382 ****************************************************************************/ 383 384 case MPI2_IOCSTATUS_INVALID_FUNCTION: 385 desc = "invalid function"; 386 break; 387 case MPI2_IOCSTATUS_BUSY: 388 desc = "busy"; 389 break; 390 case MPI2_IOCSTATUS_INVALID_SGL: 391 desc = "invalid sgl"; 392 break; 393 case MPI2_IOCSTATUS_INTERNAL_ERROR: 394 desc = "internal error"; 395 break; 396 case MPI2_IOCSTATUS_INVALID_VPID: 397 desc = "invalid vpid"; 398 break; 399 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES: 400 desc = "insufficient resources"; 401 break; 402 case MPI2_IOCSTATUS_INSUFFICIENT_POWER: 403 desc = "insufficient power"; 404 break; 405 case MPI2_IOCSTATUS_INVALID_FIELD: 406 desc = "invalid field"; 407 break; 408 case MPI2_IOCSTATUS_INVALID_STATE: 409 desc = "invalid state"; 410 break; 411 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED: 412 desc = "op state not supported"; 413 break; 414 415 /**************************************************************************** 416 * Config IOCStatus values 417 ****************************************************************************/ 418 419 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION: 420 desc = "config invalid action"; 421 break; 422 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE: 423 desc = "config invalid type"; 424 break; 425 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE: 426 desc = "config invalid page"; 427 break; 428 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA: 429 desc = "config invalid data"; 430 break; 431 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS: 432 desc = "config no defaults"; 433 break; 434 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT: 435 desc = "config cant commit"; 436 break; 437 438 /**************************************************************************** 439 * SCSI IO Reply 440 ****************************************************************************/ 441 442 case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR: 443 case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE: 444 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE: 445 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN: 446 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN: 447 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR: 448 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR: 449 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED: 450 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: 451 case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED: 452 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED: 453 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED: 454 break; 455 456 /**************************************************************************** 457 * For use by SCSI Initiator and SCSI Target end-to-end data protection 458 ****************************************************************************/ 459 460 case MPI2_IOCSTATUS_EEDP_GUARD_ERROR: 461 desc = "eedp guard error"; 462 break; 463 case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR: 464 desc = "eedp ref tag error"; 465 break; 466 case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR: 467 desc = "eedp app tag error"; 468 break; 469 470 /**************************************************************************** 471 * SCSI Target values 472 ****************************************************************************/ 473 474 case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX: 475 desc = "target invalid io index"; 476 break; 477 case MPI2_IOCSTATUS_TARGET_ABORTED: 478 desc = "target aborted"; 479 break; 480 case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE: 481 desc = "target no conn retryable"; 482 break; 483 case MPI2_IOCSTATUS_TARGET_NO_CONNECTION: 484 desc = "target no connection"; 485 break; 486 case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH: 487 desc = "target xfer count mismatch"; 488 break; 489 case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR: 490 desc = "target data offset error"; 491 break; 492 case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA: 493 desc = "target too much write data"; 494 break; 495 case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT: 496 desc = "target iu too short"; 497 break; 498 case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT: 499 desc = "target ack nak timeout"; 500 break; 501 case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED: 502 desc = "target nak received"; 503 break; 504 505 /**************************************************************************** 506 * Serial Attached SCSI values 507 ****************************************************************************/ 508 509 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED: 510 desc = "smp request failed"; 511 break; 512 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN: 513 desc = "smp data overrun"; 514 break; 515 516 /**************************************************************************** 517 * Diagnostic Buffer Post / Diagnostic Release values 518 ****************************************************************************/ 519 520 case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED: 521 desc = "diagnostic released"; 522 break; 523 default: 524 break; 525 } 526 527 if (!desc) 528 return; 529 530 switch (request_hdr->Function) { 531 case MPI2_FUNCTION_CONFIG: 532 frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size; 533 func_str = "config_page"; 534 break; 535 case MPI2_FUNCTION_SCSI_TASK_MGMT: 536 frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t); 537 func_str = "task_mgmt"; 538 break; 539 case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL: 540 frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t); 541 func_str = "sas_iounit_ctl"; 542 break; 543 case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR: 544 frame_sz = sizeof(Mpi2SepRequest_t); 545 func_str = "enclosure"; 546 break; 547 case MPI2_FUNCTION_IOC_INIT: 548 frame_sz = sizeof(Mpi2IOCInitRequest_t); 549 func_str = "ioc_init"; 550 break; 551 case MPI2_FUNCTION_PORT_ENABLE: 552 frame_sz = sizeof(Mpi2PortEnableRequest_t); 553 func_str = "port_enable"; 554 break; 555 case MPI2_FUNCTION_SMP_PASSTHROUGH: 556 frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size; 557 func_str = "smp_passthru"; 558 break; 559 default: 560 frame_sz = 32; 561 func_str = "unknown"; 562 break; 563 } 564 565 pr_warn(MPT3SAS_FMT "ioc_status: %s(0x%04x), request(0x%p),(%s)\n", 566 ioc->name, desc, ioc_status, request_hdr, func_str); 567 568 _debug_dump_mf(request_hdr, frame_sz/4); 569 } 570 571 /** 572 * _base_display_event_data - verbose translation of firmware asyn events 573 * @ioc: per adapter object 574 * @mpi_reply: reply mf payload returned from firmware 575 * 576 * Return nothing. 577 */ 578 static void 579 _base_display_event_data(struct MPT3SAS_ADAPTER *ioc, 580 Mpi2EventNotificationReply_t *mpi_reply) 581 { 582 char *desc = NULL; 583 u16 event; 584 585 if (!(ioc->logging_level & MPT_DEBUG_EVENTS)) 586 return; 587 588 event = le16_to_cpu(mpi_reply->Event); 589 590 switch (event) { 591 case MPI2_EVENT_LOG_DATA: 592 desc = "Log Data"; 593 break; 594 case MPI2_EVENT_STATE_CHANGE: 595 desc = "Status Change"; 596 break; 597 case MPI2_EVENT_HARD_RESET_RECEIVED: 598 desc = "Hard Reset Received"; 599 break; 600 case MPI2_EVENT_EVENT_CHANGE: 601 desc = "Event Change"; 602 break; 603 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE: 604 desc = "Device Status Change"; 605 break; 606 case MPI2_EVENT_IR_OPERATION_STATUS: 607 if (!ioc->hide_ir_msg) 608 desc = "IR Operation Status"; 609 break; 610 case MPI2_EVENT_SAS_DISCOVERY: 611 { 612 Mpi2EventDataSasDiscovery_t *event_data = 613 (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData; 614 pr_info(MPT3SAS_FMT "Discovery: (%s)", ioc->name, 615 (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ? 616 "start" : "stop"); 617 if (event_data->DiscoveryStatus) 618 pr_info("discovery_status(0x%08x)", 619 le32_to_cpu(event_data->DiscoveryStatus)); 620 pr_info("\n"); 621 return; 622 } 623 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE: 624 desc = "SAS Broadcast Primitive"; 625 break; 626 case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE: 627 desc = "SAS Init Device Status Change"; 628 break; 629 case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW: 630 desc = "SAS Init Table Overflow"; 631 break; 632 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 633 desc = "SAS Topology Change List"; 634 break; 635 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE: 636 desc = "SAS Enclosure Device Status Change"; 637 break; 638 case MPI2_EVENT_IR_VOLUME: 639 if (!ioc->hide_ir_msg) 640 desc = "IR Volume"; 641 break; 642 case MPI2_EVENT_IR_PHYSICAL_DISK: 643 if (!ioc->hide_ir_msg) 644 desc = "IR Physical Disk"; 645 break; 646 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST: 647 if (!ioc->hide_ir_msg) 648 desc = "IR Configuration Change List"; 649 break; 650 case MPI2_EVENT_LOG_ENTRY_ADDED: 651 if (!ioc->hide_ir_msg) 652 desc = "Log Entry Added"; 653 break; 654 case MPI2_EVENT_TEMP_THRESHOLD: 655 desc = "Temperature Threshold"; 656 break; 657 case MPI2_EVENT_ACTIVE_CABLE_EXCEPTION: 658 desc = "Active cable exception"; 659 break; 660 } 661 662 if (!desc) 663 return; 664 665 pr_info(MPT3SAS_FMT "%s\n", ioc->name, desc); 666 } 667 668 /** 669 * _base_sas_log_info - verbose translation of firmware log info 670 * @ioc: per adapter object 671 * @log_info: log info 672 * 673 * Return nothing. 674 */ 675 static void 676 _base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info) 677 { 678 union loginfo_type { 679 u32 loginfo; 680 struct { 681 u32 subcode:16; 682 u32 code:8; 683 u32 originator:4; 684 u32 bus_type:4; 685 } dw; 686 }; 687 union loginfo_type sas_loginfo; 688 char *originator_str = NULL; 689 690 sas_loginfo.loginfo = log_info; 691 if (sas_loginfo.dw.bus_type != 3 /*SAS*/) 692 return; 693 694 /* each nexus loss loginfo */ 695 if (log_info == 0x31170000) 696 return; 697 698 /* eat the loginfos associated with task aborts */ 699 if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info == 700 0x31140000 || log_info == 0x31130000)) 701 return; 702 703 switch (sas_loginfo.dw.originator) { 704 case 0: 705 originator_str = "IOP"; 706 break; 707 case 1: 708 originator_str = "PL"; 709 break; 710 case 2: 711 if (!ioc->hide_ir_msg) 712 originator_str = "IR"; 713 else 714 originator_str = "WarpDrive"; 715 break; 716 } 717 718 pr_warn(MPT3SAS_FMT 719 "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n", 720 ioc->name, log_info, 721 originator_str, sas_loginfo.dw.code, 722 sas_loginfo.dw.subcode); 723 } 724 725 /** 726 * _base_display_reply_info - 727 * @ioc: per adapter object 728 * @smid: system request message index 729 * @msix_index: MSIX table index supplied by the OS 730 * @reply: reply message frame(lower 32bit addr) 731 * 732 * Return nothing. 733 */ 734 static void 735 _base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, 736 u32 reply) 737 { 738 MPI2DefaultReply_t *mpi_reply; 739 u16 ioc_status; 740 u32 loginfo = 0; 741 742 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); 743 if (unlikely(!mpi_reply)) { 744 pr_err(MPT3SAS_FMT "mpi_reply not valid at %s:%d/%s()!\n", 745 ioc->name, __FILE__, __LINE__, __func__); 746 return; 747 } 748 ioc_status = le16_to_cpu(mpi_reply->IOCStatus); 749 750 if ((ioc_status & MPI2_IOCSTATUS_MASK) && 751 (ioc->logging_level & MPT_DEBUG_REPLY)) { 752 _base_sas_ioc_info(ioc , mpi_reply, 753 mpt3sas_base_get_msg_frame(ioc, smid)); 754 } 755 756 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 757 loginfo = le32_to_cpu(mpi_reply->IOCLogInfo); 758 _base_sas_log_info(ioc, loginfo); 759 } 760 761 if (ioc_status || loginfo) { 762 ioc_status &= MPI2_IOCSTATUS_MASK; 763 mpt3sas_trigger_mpi(ioc, ioc_status, loginfo); 764 } 765 } 766 767 /** 768 * mpt3sas_base_done - base internal command completion routine 769 * @ioc: per adapter object 770 * @smid: system request message index 771 * @msix_index: MSIX table index supplied by the OS 772 * @reply: reply message frame(lower 32bit addr) 773 * 774 * Return 1 meaning mf should be freed from _base_interrupt 775 * 0 means the mf is freed from this function. 776 */ 777 u8 778 mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, 779 u32 reply) 780 { 781 MPI2DefaultReply_t *mpi_reply; 782 783 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); 784 if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK) 785 return mpt3sas_check_for_pending_internal_cmds(ioc, smid); 786 787 if (ioc->base_cmds.status == MPT3_CMD_NOT_USED) 788 return 1; 789 790 ioc->base_cmds.status |= MPT3_CMD_COMPLETE; 791 if (mpi_reply) { 792 ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID; 793 memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4); 794 } 795 ioc->base_cmds.status &= ~MPT3_CMD_PENDING; 796 797 complete(&ioc->base_cmds.done); 798 return 1; 799 } 800 801 /** 802 * _base_async_event - main callback handler for firmware asyn events 803 * @ioc: per adapter object 804 * @msix_index: MSIX table index supplied by the OS 805 * @reply: reply message frame(lower 32bit addr) 806 * 807 * Return 1 meaning mf should be freed from _base_interrupt 808 * 0 means the mf is freed from this function. 809 */ 810 static u8 811 _base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply) 812 { 813 Mpi2EventNotificationReply_t *mpi_reply; 814 Mpi2EventAckRequest_t *ack_request; 815 u16 smid; 816 struct _event_ack_list *delayed_event_ack; 817 818 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); 819 if (!mpi_reply) 820 return 1; 821 if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION) 822 return 1; 823 824 _base_display_event_data(ioc, mpi_reply); 825 826 if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED)) 827 goto out; 828 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 829 if (!smid) { 830 delayed_event_ack = kzalloc(sizeof(*delayed_event_ack), 831 GFP_ATOMIC); 832 if (!delayed_event_ack) 833 goto out; 834 INIT_LIST_HEAD(&delayed_event_ack->list); 835 delayed_event_ack->Event = mpi_reply->Event; 836 delayed_event_ack->EventContext = mpi_reply->EventContext; 837 list_add_tail(&delayed_event_ack->list, 838 &ioc->delayed_event_ack_list); 839 dewtprintk(ioc, pr_info(MPT3SAS_FMT 840 "DELAYED: EVENT ACK: event (0x%04x)\n", 841 ioc->name, le16_to_cpu(mpi_reply->Event))); 842 goto out; 843 } 844 845 ack_request = mpt3sas_base_get_msg_frame(ioc, smid); 846 memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t)); 847 ack_request->Function = MPI2_FUNCTION_EVENT_ACK; 848 ack_request->Event = mpi_reply->Event; 849 ack_request->EventContext = mpi_reply->EventContext; 850 ack_request->VF_ID = 0; /* TODO */ 851 ack_request->VP_ID = 0; 852 ioc->put_smid_default(ioc, smid); 853 854 out: 855 856 /* scsih callback handler */ 857 mpt3sas_scsih_event_callback(ioc, msix_index, reply); 858 859 /* ctl callback handler */ 860 mpt3sas_ctl_event_callback(ioc, msix_index, reply); 861 862 return 1; 863 } 864 865 /** 866 * _base_get_cb_idx - obtain the callback index 867 * @ioc: per adapter object 868 * @smid: system request message index 869 * 870 * Return callback index. 871 */ 872 static u8 873 _base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid) 874 { 875 int i; 876 u8 cb_idx; 877 878 if (smid < ioc->hi_priority_smid) { 879 i = smid - 1; 880 cb_idx = ioc->scsi_lookup[i].cb_idx; 881 } else if (smid < ioc->internal_smid) { 882 i = smid - ioc->hi_priority_smid; 883 cb_idx = ioc->hpr_lookup[i].cb_idx; 884 } else if (smid <= ioc->hba_queue_depth) { 885 i = smid - ioc->internal_smid; 886 cb_idx = ioc->internal_lookup[i].cb_idx; 887 } else 888 cb_idx = 0xFF; 889 return cb_idx; 890 } 891 892 /** 893 * _base_mask_interrupts - disable interrupts 894 * @ioc: per adapter object 895 * 896 * Disabling ResetIRQ, Reply and Doorbell Interrupts 897 * 898 * Return nothing. 899 */ 900 static void 901 _base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc) 902 { 903 u32 him_register; 904 905 ioc->mask_interrupts = 1; 906 him_register = readl(&ioc->chip->HostInterruptMask); 907 him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK; 908 writel(him_register, &ioc->chip->HostInterruptMask); 909 readl(&ioc->chip->HostInterruptMask); 910 } 911 912 /** 913 * _base_unmask_interrupts - enable interrupts 914 * @ioc: per adapter object 915 * 916 * Enabling only Reply Interrupts 917 * 918 * Return nothing. 919 */ 920 static void 921 _base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc) 922 { 923 u32 him_register; 924 925 him_register = readl(&ioc->chip->HostInterruptMask); 926 him_register &= ~MPI2_HIM_RIM; 927 writel(him_register, &ioc->chip->HostInterruptMask); 928 ioc->mask_interrupts = 0; 929 } 930 931 union reply_descriptor { 932 u64 word; 933 struct { 934 u32 low; 935 u32 high; 936 } u; 937 }; 938 939 /** 940 * _base_interrupt - MPT adapter (IOC) specific interrupt handler. 941 * @irq: irq number (not used) 942 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure 943 * @r: pt_regs pointer (not used) 944 * 945 * Return IRQ_HANDLE if processed, else IRQ_NONE. 946 */ 947 static irqreturn_t 948 _base_interrupt(int irq, void *bus_id) 949 { 950 struct adapter_reply_queue *reply_q = bus_id; 951 union reply_descriptor rd; 952 u32 completed_cmds; 953 u8 request_desript_type; 954 u16 smid; 955 u8 cb_idx; 956 u32 reply; 957 u8 msix_index = reply_q->msix_index; 958 struct MPT3SAS_ADAPTER *ioc = reply_q->ioc; 959 Mpi2ReplyDescriptorsUnion_t *rpf; 960 u8 rc; 961 962 if (ioc->mask_interrupts) 963 return IRQ_NONE; 964 965 if (!atomic_add_unless(&reply_q->busy, 1, 1)) 966 return IRQ_NONE; 967 968 rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index]; 969 request_desript_type = rpf->Default.ReplyFlags 970 & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 971 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) { 972 atomic_dec(&reply_q->busy); 973 return IRQ_NONE; 974 } 975 976 completed_cmds = 0; 977 cb_idx = 0xFF; 978 do { 979 rd.word = le64_to_cpu(rpf->Words); 980 if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX) 981 goto out; 982 reply = 0; 983 smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1); 984 if (request_desript_type == 985 MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS || 986 request_desript_type == 987 MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) { 988 cb_idx = _base_get_cb_idx(ioc, smid); 989 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) && 990 (likely(mpt_callbacks[cb_idx] != NULL))) { 991 rc = mpt_callbacks[cb_idx](ioc, smid, 992 msix_index, 0); 993 if (rc) 994 mpt3sas_base_free_smid(ioc, smid); 995 } 996 } else if (request_desript_type == 997 MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) { 998 reply = le32_to_cpu( 999 rpf->AddressReply.ReplyFrameAddress); 1000 if (reply > ioc->reply_dma_max_address || 1001 reply < ioc->reply_dma_min_address) 1002 reply = 0; 1003 if (smid) { 1004 cb_idx = _base_get_cb_idx(ioc, smid); 1005 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) && 1006 (likely(mpt_callbacks[cb_idx] != NULL))) { 1007 rc = mpt_callbacks[cb_idx](ioc, smid, 1008 msix_index, reply); 1009 if (reply) 1010 _base_display_reply_info(ioc, 1011 smid, msix_index, reply); 1012 if (rc) 1013 mpt3sas_base_free_smid(ioc, 1014 smid); 1015 } 1016 } else { 1017 _base_async_event(ioc, msix_index, reply); 1018 } 1019 1020 /* reply free queue handling */ 1021 if (reply) { 1022 ioc->reply_free_host_index = 1023 (ioc->reply_free_host_index == 1024 (ioc->reply_free_queue_depth - 1)) ? 1025 0 : ioc->reply_free_host_index + 1; 1026 ioc->reply_free[ioc->reply_free_host_index] = 1027 cpu_to_le32(reply); 1028 wmb(); 1029 writel(ioc->reply_free_host_index, 1030 &ioc->chip->ReplyFreeHostIndex); 1031 } 1032 } 1033 1034 rpf->Words = cpu_to_le64(ULLONG_MAX); 1035 reply_q->reply_post_host_index = 1036 (reply_q->reply_post_host_index == 1037 (ioc->reply_post_queue_depth - 1)) ? 0 : 1038 reply_q->reply_post_host_index + 1; 1039 request_desript_type = 1040 reply_q->reply_post_free[reply_q->reply_post_host_index]. 1041 Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 1042 completed_cmds++; 1043 /* Update the reply post host index after continuously 1044 * processing the threshold number of Reply Descriptors. 1045 * So that FW can find enough entries to post the Reply 1046 * Descriptors in the reply descriptor post queue. 1047 */ 1048 if (completed_cmds > ioc->hba_queue_depth/3) { 1049 if (ioc->combined_reply_queue) { 1050 writel(reply_q->reply_post_host_index | 1051 ((msix_index & 7) << 1052 MPI2_RPHI_MSIX_INDEX_SHIFT), 1053 ioc->replyPostRegisterIndex[msix_index/8]); 1054 } else { 1055 writel(reply_q->reply_post_host_index | 1056 (msix_index << 1057 MPI2_RPHI_MSIX_INDEX_SHIFT), 1058 &ioc->chip->ReplyPostHostIndex); 1059 } 1060 completed_cmds = 1; 1061 } 1062 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) 1063 goto out; 1064 if (!reply_q->reply_post_host_index) 1065 rpf = reply_q->reply_post_free; 1066 else 1067 rpf++; 1068 } while (1); 1069 1070 out: 1071 1072 if (!completed_cmds) { 1073 atomic_dec(&reply_q->busy); 1074 return IRQ_NONE; 1075 } 1076 1077 wmb(); 1078 if (ioc->is_warpdrive) { 1079 writel(reply_q->reply_post_host_index, 1080 ioc->reply_post_host_index[msix_index]); 1081 atomic_dec(&reply_q->busy); 1082 return IRQ_HANDLED; 1083 } 1084 1085 /* Update Reply Post Host Index. 1086 * For those HBA's which support combined reply queue feature 1087 * 1. Get the correct Supplemental Reply Post Host Index Register. 1088 * i.e. (msix_index / 8)th entry from Supplemental Reply Post Host 1089 * Index Register address bank i.e replyPostRegisterIndex[], 1090 * 2. Then update this register with new reply host index value 1091 * in ReplyPostIndex field and the MSIxIndex field with 1092 * msix_index value reduced to a value between 0 and 7, 1093 * using a modulo 8 operation. Since each Supplemental Reply Post 1094 * Host Index Register supports 8 MSI-X vectors. 1095 * 1096 * For other HBA's just update the Reply Post Host Index register with 1097 * new reply host index value in ReplyPostIndex Field and msix_index 1098 * value in MSIxIndex field. 1099 */ 1100 if (ioc->combined_reply_queue) 1101 writel(reply_q->reply_post_host_index | ((msix_index & 7) << 1102 MPI2_RPHI_MSIX_INDEX_SHIFT), 1103 ioc->replyPostRegisterIndex[msix_index/8]); 1104 else 1105 writel(reply_q->reply_post_host_index | (msix_index << 1106 MPI2_RPHI_MSIX_INDEX_SHIFT), 1107 &ioc->chip->ReplyPostHostIndex); 1108 atomic_dec(&reply_q->busy); 1109 return IRQ_HANDLED; 1110 } 1111 1112 /** 1113 * _base_is_controller_msix_enabled - is controller support muli-reply queues 1114 * @ioc: per adapter object 1115 * 1116 */ 1117 static inline int 1118 _base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc) 1119 { 1120 return (ioc->facts.IOCCapabilities & 1121 MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable; 1122 } 1123 1124 /** 1125 * mpt3sas_base_sync_reply_irqs - flush pending MSIX interrupts 1126 * @ioc: per adapter object 1127 * Context: non ISR conext 1128 * 1129 * Called when a Task Management request has completed. 1130 * 1131 * Return nothing. 1132 */ 1133 void 1134 mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc) 1135 { 1136 struct adapter_reply_queue *reply_q; 1137 1138 /* If MSIX capability is turned off 1139 * then multi-queues are not enabled 1140 */ 1141 if (!_base_is_controller_msix_enabled(ioc)) 1142 return; 1143 1144 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 1145 if (ioc->shost_recovery || ioc->remove_host || 1146 ioc->pci_error_recovery) 1147 return; 1148 /* TMs are on msix_index == 0 */ 1149 if (reply_q->msix_index == 0) 1150 continue; 1151 synchronize_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index)); 1152 } 1153 } 1154 1155 /** 1156 * mpt3sas_base_release_callback_handler - clear interrupt callback handler 1157 * @cb_idx: callback index 1158 * 1159 * Return nothing. 1160 */ 1161 void 1162 mpt3sas_base_release_callback_handler(u8 cb_idx) 1163 { 1164 mpt_callbacks[cb_idx] = NULL; 1165 } 1166 1167 /** 1168 * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler 1169 * @cb_func: callback function 1170 * 1171 * Returns cb_func. 1172 */ 1173 u8 1174 mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func) 1175 { 1176 u8 cb_idx; 1177 1178 for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--) 1179 if (mpt_callbacks[cb_idx] == NULL) 1180 break; 1181 1182 mpt_callbacks[cb_idx] = cb_func; 1183 return cb_idx; 1184 } 1185 1186 /** 1187 * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler 1188 * 1189 * Return nothing. 1190 */ 1191 void 1192 mpt3sas_base_initialize_callback_handler(void) 1193 { 1194 u8 cb_idx; 1195 1196 for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++) 1197 mpt3sas_base_release_callback_handler(cb_idx); 1198 } 1199 1200 1201 /** 1202 * _base_build_zero_len_sge - build zero length sg entry 1203 * @ioc: per adapter object 1204 * @paddr: virtual address for SGE 1205 * 1206 * Create a zero length scatter gather entry to insure the IOCs hardware has 1207 * something to use if the target device goes brain dead and tries 1208 * to send data even when none is asked for. 1209 * 1210 * Return nothing. 1211 */ 1212 static void 1213 _base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr) 1214 { 1215 u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT | 1216 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST | 1217 MPI2_SGE_FLAGS_SIMPLE_ELEMENT) << 1218 MPI2_SGE_FLAGS_SHIFT); 1219 ioc->base_add_sg_single(paddr, flags_length, -1); 1220 } 1221 1222 /** 1223 * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr. 1224 * @paddr: virtual address for SGE 1225 * @flags_length: SGE flags and data transfer length 1226 * @dma_addr: Physical address 1227 * 1228 * Return nothing. 1229 */ 1230 static void 1231 _base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr) 1232 { 1233 Mpi2SGESimple32_t *sgel = paddr; 1234 1235 flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING | 1236 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT; 1237 sgel->FlagsLength = cpu_to_le32(flags_length); 1238 sgel->Address = cpu_to_le32(dma_addr); 1239 } 1240 1241 1242 /** 1243 * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr. 1244 * @paddr: virtual address for SGE 1245 * @flags_length: SGE flags and data transfer length 1246 * @dma_addr: Physical address 1247 * 1248 * Return nothing. 1249 */ 1250 static void 1251 _base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr) 1252 { 1253 Mpi2SGESimple64_t *sgel = paddr; 1254 1255 flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING | 1256 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT; 1257 sgel->FlagsLength = cpu_to_le32(flags_length); 1258 sgel->Address = cpu_to_le64(dma_addr); 1259 } 1260 1261 /** 1262 * _base_get_chain_buffer_tracker - obtain chain tracker 1263 * @ioc: per adapter object 1264 * @smid: smid associated to an IO request 1265 * 1266 * Returns chain tracker(from ioc->free_chain_list) 1267 */ 1268 static struct chain_tracker * 1269 _base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc, u16 smid) 1270 { 1271 struct chain_tracker *chain_req; 1272 unsigned long flags; 1273 1274 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 1275 if (list_empty(&ioc->free_chain_list)) { 1276 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 1277 dfailprintk(ioc, pr_warn(MPT3SAS_FMT 1278 "chain buffers not available\n", ioc->name)); 1279 return NULL; 1280 } 1281 chain_req = list_entry(ioc->free_chain_list.next, 1282 struct chain_tracker, tracker_list); 1283 list_del_init(&chain_req->tracker_list); 1284 list_add_tail(&chain_req->tracker_list, 1285 &ioc->scsi_lookup[smid - 1].chain_list); 1286 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 1287 return chain_req; 1288 } 1289 1290 1291 /** 1292 * _base_build_sg - build generic sg 1293 * @ioc: per adapter object 1294 * @psge: virtual address for SGE 1295 * @data_out_dma: physical address for WRITES 1296 * @data_out_sz: data xfer size for WRITES 1297 * @data_in_dma: physical address for READS 1298 * @data_in_sz: data xfer size for READS 1299 * 1300 * Return nothing. 1301 */ 1302 static void 1303 _base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge, 1304 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma, 1305 size_t data_in_sz) 1306 { 1307 u32 sgl_flags; 1308 1309 if (!data_out_sz && !data_in_sz) { 1310 _base_build_zero_len_sge(ioc, psge); 1311 return; 1312 } 1313 1314 if (data_out_sz && data_in_sz) { 1315 /* WRITE sgel first */ 1316 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 1317 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC); 1318 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 1319 ioc->base_add_sg_single(psge, sgl_flags | 1320 data_out_sz, data_out_dma); 1321 1322 /* incr sgel */ 1323 psge += ioc->sge_size; 1324 1325 /* READ sgel last */ 1326 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 1327 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | 1328 MPI2_SGE_FLAGS_END_OF_LIST); 1329 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 1330 ioc->base_add_sg_single(psge, sgl_flags | 1331 data_in_sz, data_in_dma); 1332 } else if (data_out_sz) /* WRITE */ { 1333 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 1334 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | 1335 MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC); 1336 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 1337 ioc->base_add_sg_single(psge, sgl_flags | 1338 data_out_sz, data_out_dma); 1339 } else if (data_in_sz) /* READ */ { 1340 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 1341 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | 1342 MPI2_SGE_FLAGS_END_OF_LIST); 1343 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 1344 ioc->base_add_sg_single(psge, sgl_flags | 1345 data_in_sz, data_in_dma); 1346 } 1347 } 1348 1349 /* IEEE format sgls */ 1350 1351 /** 1352 * _base_add_sg_single_ieee - add sg element for IEEE format 1353 * @paddr: virtual address for SGE 1354 * @flags: SGE flags 1355 * @chain_offset: number of 128 byte elements from start of segment 1356 * @length: data transfer length 1357 * @dma_addr: Physical address 1358 * 1359 * Return nothing. 1360 */ 1361 static void 1362 _base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length, 1363 dma_addr_t dma_addr) 1364 { 1365 Mpi25IeeeSgeChain64_t *sgel = paddr; 1366 1367 sgel->Flags = flags; 1368 sgel->NextChainOffset = chain_offset; 1369 sgel->Length = cpu_to_le32(length); 1370 sgel->Address = cpu_to_le64(dma_addr); 1371 } 1372 1373 /** 1374 * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format 1375 * @ioc: per adapter object 1376 * @paddr: virtual address for SGE 1377 * 1378 * Create a zero length scatter gather entry to insure the IOCs hardware has 1379 * something to use if the target device goes brain dead and tries 1380 * to send data even when none is asked for. 1381 * 1382 * Return nothing. 1383 */ 1384 static void 1385 _base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr) 1386 { 1387 u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 1388 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR | 1389 MPI25_IEEE_SGE_FLAGS_END_OF_LIST); 1390 1391 _base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1); 1392 } 1393 1394 /** 1395 * _base_build_sg_scmd - main sg creation routine 1396 * @ioc: per adapter object 1397 * @scmd: scsi command 1398 * @smid: system request message index 1399 * Context: none. 1400 * 1401 * The main routine that builds scatter gather table from a given 1402 * scsi request sent via the .queuecommand main handler. 1403 * 1404 * Returns 0 success, anything else error 1405 */ 1406 static int 1407 _base_build_sg_scmd(struct MPT3SAS_ADAPTER *ioc, 1408 struct scsi_cmnd *scmd, u16 smid) 1409 { 1410 Mpi2SCSIIORequest_t *mpi_request; 1411 dma_addr_t chain_dma; 1412 struct scatterlist *sg_scmd; 1413 void *sg_local, *chain; 1414 u32 chain_offset; 1415 u32 chain_length; 1416 u32 chain_flags; 1417 int sges_left; 1418 u32 sges_in_segment; 1419 u32 sgl_flags; 1420 u32 sgl_flags_last_element; 1421 u32 sgl_flags_end_buffer; 1422 struct chain_tracker *chain_req; 1423 1424 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 1425 1426 /* init scatter gather flags */ 1427 sgl_flags = MPI2_SGE_FLAGS_SIMPLE_ELEMENT; 1428 if (scmd->sc_data_direction == DMA_TO_DEVICE) 1429 sgl_flags |= MPI2_SGE_FLAGS_HOST_TO_IOC; 1430 sgl_flags_last_element = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT) 1431 << MPI2_SGE_FLAGS_SHIFT; 1432 sgl_flags_end_buffer = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT | 1433 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST) 1434 << MPI2_SGE_FLAGS_SHIFT; 1435 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 1436 1437 sg_scmd = scsi_sglist(scmd); 1438 sges_left = scsi_dma_map(scmd); 1439 if (sges_left < 0) { 1440 sdev_printk(KERN_ERR, scmd->device, 1441 "pci_map_sg failed: request for %d bytes!\n", 1442 scsi_bufflen(scmd)); 1443 return -ENOMEM; 1444 } 1445 1446 sg_local = &mpi_request->SGL; 1447 sges_in_segment = ioc->max_sges_in_main_message; 1448 if (sges_left <= sges_in_segment) 1449 goto fill_in_last_segment; 1450 1451 mpi_request->ChainOffset = (offsetof(Mpi2SCSIIORequest_t, SGL) + 1452 (sges_in_segment * ioc->sge_size))/4; 1453 1454 /* fill in main message segment when there is a chain following */ 1455 while (sges_in_segment) { 1456 if (sges_in_segment == 1) 1457 ioc->base_add_sg_single(sg_local, 1458 sgl_flags_last_element | sg_dma_len(sg_scmd), 1459 sg_dma_address(sg_scmd)); 1460 else 1461 ioc->base_add_sg_single(sg_local, sgl_flags | 1462 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 1463 sg_scmd = sg_next(sg_scmd); 1464 sg_local += ioc->sge_size; 1465 sges_left--; 1466 sges_in_segment--; 1467 } 1468 1469 /* initializing the chain flags and pointers */ 1470 chain_flags = MPI2_SGE_FLAGS_CHAIN_ELEMENT << MPI2_SGE_FLAGS_SHIFT; 1471 chain_req = _base_get_chain_buffer_tracker(ioc, smid); 1472 if (!chain_req) 1473 return -1; 1474 chain = chain_req->chain_buffer; 1475 chain_dma = chain_req->chain_buffer_dma; 1476 do { 1477 sges_in_segment = (sges_left <= 1478 ioc->max_sges_in_chain_message) ? sges_left : 1479 ioc->max_sges_in_chain_message; 1480 chain_offset = (sges_left == sges_in_segment) ? 1481 0 : (sges_in_segment * ioc->sge_size)/4; 1482 chain_length = sges_in_segment * ioc->sge_size; 1483 if (chain_offset) { 1484 chain_offset = chain_offset << 1485 MPI2_SGE_CHAIN_OFFSET_SHIFT; 1486 chain_length += ioc->sge_size; 1487 } 1488 ioc->base_add_sg_single(sg_local, chain_flags | chain_offset | 1489 chain_length, chain_dma); 1490 sg_local = chain; 1491 if (!chain_offset) 1492 goto fill_in_last_segment; 1493 1494 /* fill in chain segments */ 1495 while (sges_in_segment) { 1496 if (sges_in_segment == 1) 1497 ioc->base_add_sg_single(sg_local, 1498 sgl_flags_last_element | 1499 sg_dma_len(sg_scmd), 1500 sg_dma_address(sg_scmd)); 1501 else 1502 ioc->base_add_sg_single(sg_local, sgl_flags | 1503 sg_dma_len(sg_scmd), 1504 sg_dma_address(sg_scmd)); 1505 sg_scmd = sg_next(sg_scmd); 1506 sg_local += ioc->sge_size; 1507 sges_left--; 1508 sges_in_segment--; 1509 } 1510 1511 chain_req = _base_get_chain_buffer_tracker(ioc, smid); 1512 if (!chain_req) 1513 return -1; 1514 chain = chain_req->chain_buffer; 1515 chain_dma = chain_req->chain_buffer_dma; 1516 } while (1); 1517 1518 1519 fill_in_last_segment: 1520 1521 /* fill the last segment */ 1522 while (sges_left) { 1523 if (sges_left == 1) 1524 ioc->base_add_sg_single(sg_local, sgl_flags_end_buffer | 1525 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 1526 else 1527 ioc->base_add_sg_single(sg_local, sgl_flags | 1528 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 1529 sg_scmd = sg_next(sg_scmd); 1530 sg_local += ioc->sge_size; 1531 sges_left--; 1532 } 1533 1534 return 0; 1535 } 1536 1537 /** 1538 * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format 1539 * @ioc: per adapter object 1540 * @scmd: scsi command 1541 * @smid: system request message index 1542 * Context: none. 1543 * 1544 * The main routine that builds scatter gather table from a given 1545 * scsi request sent via the .queuecommand main handler. 1546 * 1547 * Returns 0 success, anything else error 1548 */ 1549 static int 1550 _base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc, 1551 struct scsi_cmnd *scmd, u16 smid) 1552 { 1553 Mpi2SCSIIORequest_t *mpi_request; 1554 dma_addr_t chain_dma; 1555 struct scatterlist *sg_scmd; 1556 void *sg_local, *chain; 1557 u32 chain_offset; 1558 u32 chain_length; 1559 int sges_left; 1560 u32 sges_in_segment; 1561 u8 simple_sgl_flags; 1562 u8 simple_sgl_flags_last; 1563 u8 chain_sgl_flags; 1564 struct chain_tracker *chain_req; 1565 1566 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 1567 1568 /* init scatter gather flags */ 1569 simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 1570 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 1571 simple_sgl_flags_last = simple_sgl_flags | 1572 MPI25_IEEE_SGE_FLAGS_END_OF_LIST; 1573 chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | 1574 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 1575 1576 sg_scmd = scsi_sglist(scmd); 1577 sges_left = scsi_dma_map(scmd); 1578 if (sges_left < 0) { 1579 sdev_printk(KERN_ERR, scmd->device, 1580 "pci_map_sg failed: request for %d bytes!\n", 1581 scsi_bufflen(scmd)); 1582 return -ENOMEM; 1583 } 1584 1585 sg_local = &mpi_request->SGL; 1586 sges_in_segment = (ioc->request_sz - 1587 offsetof(Mpi2SCSIIORequest_t, SGL))/ioc->sge_size_ieee; 1588 if (sges_left <= sges_in_segment) 1589 goto fill_in_last_segment; 1590 1591 mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) + 1592 (offsetof(Mpi2SCSIIORequest_t, SGL)/ioc->sge_size_ieee); 1593 1594 /* fill in main message segment when there is a chain following */ 1595 while (sges_in_segment > 1) { 1596 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, 1597 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 1598 sg_scmd = sg_next(sg_scmd); 1599 sg_local += ioc->sge_size_ieee; 1600 sges_left--; 1601 sges_in_segment--; 1602 } 1603 1604 /* initializing the pointers */ 1605 chain_req = _base_get_chain_buffer_tracker(ioc, smid); 1606 if (!chain_req) 1607 return -1; 1608 chain = chain_req->chain_buffer; 1609 chain_dma = chain_req->chain_buffer_dma; 1610 do { 1611 sges_in_segment = (sges_left <= 1612 ioc->max_sges_in_chain_message) ? sges_left : 1613 ioc->max_sges_in_chain_message; 1614 chain_offset = (sges_left == sges_in_segment) ? 1615 0 : sges_in_segment; 1616 chain_length = sges_in_segment * ioc->sge_size_ieee; 1617 if (chain_offset) 1618 chain_length += ioc->sge_size_ieee; 1619 _base_add_sg_single_ieee(sg_local, chain_sgl_flags, 1620 chain_offset, chain_length, chain_dma); 1621 1622 sg_local = chain; 1623 if (!chain_offset) 1624 goto fill_in_last_segment; 1625 1626 /* fill in chain segments */ 1627 while (sges_in_segment) { 1628 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, 1629 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 1630 sg_scmd = sg_next(sg_scmd); 1631 sg_local += ioc->sge_size_ieee; 1632 sges_left--; 1633 sges_in_segment--; 1634 } 1635 1636 chain_req = _base_get_chain_buffer_tracker(ioc, smid); 1637 if (!chain_req) 1638 return -1; 1639 chain = chain_req->chain_buffer; 1640 chain_dma = chain_req->chain_buffer_dma; 1641 } while (1); 1642 1643 1644 fill_in_last_segment: 1645 1646 /* fill the last segment */ 1647 while (sges_left > 0) { 1648 if (sges_left == 1) 1649 _base_add_sg_single_ieee(sg_local, 1650 simple_sgl_flags_last, 0, sg_dma_len(sg_scmd), 1651 sg_dma_address(sg_scmd)); 1652 else 1653 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, 1654 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 1655 sg_scmd = sg_next(sg_scmd); 1656 sg_local += ioc->sge_size_ieee; 1657 sges_left--; 1658 } 1659 1660 return 0; 1661 } 1662 1663 /** 1664 * _base_build_sg_ieee - build generic sg for IEEE format 1665 * @ioc: per adapter object 1666 * @psge: virtual address for SGE 1667 * @data_out_dma: physical address for WRITES 1668 * @data_out_sz: data xfer size for WRITES 1669 * @data_in_dma: physical address for READS 1670 * @data_in_sz: data xfer size for READS 1671 * 1672 * Return nothing. 1673 */ 1674 static void 1675 _base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge, 1676 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma, 1677 size_t data_in_sz) 1678 { 1679 u8 sgl_flags; 1680 1681 if (!data_out_sz && !data_in_sz) { 1682 _base_build_zero_len_sge_ieee(ioc, psge); 1683 return; 1684 } 1685 1686 if (data_out_sz && data_in_sz) { 1687 /* WRITE sgel first */ 1688 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 1689 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 1690 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz, 1691 data_out_dma); 1692 1693 /* incr sgel */ 1694 psge += ioc->sge_size_ieee; 1695 1696 /* READ sgel last */ 1697 sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST; 1698 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz, 1699 data_in_dma); 1700 } else if (data_out_sz) /* WRITE */ { 1701 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 1702 MPI25_IEEE_SGE_FLAGS_END_OF_LIST | 1703 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 1704 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz, 1705 data_out_dma); 1706 } else if (data_in_sz) /* READ */ { 1707 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 1708 MPI25_IEEE_SGE_FLAGS_END_OF_LIST | 1709 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 1710 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz, 1711 data_in_dma); 1712 } 1713 } 1714 1715 #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10)) 1716 1717 /** 1718 * _base_config_dma_addressing - set dma addressing 1719 * @ioc: per adapter object 1720 * @pdev: PCI device struct 1721 * 1722 * Returns 0 for success, non-zero for failure. 1723 */ 1724 static int 1725 _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev) 1726 { 1727 struct sysinfo s; 1728 u64 consistent_dma_mask; 1729 1730 if (ioc->dma_mask) 1731 consistent_dma_mask = DMA_BIT_MASK(64); 1732 else 1733 consistent_dma_mask = DMA_BIT_MASK(32); 1734 1735 if (sizeof(dma_addr_t) > 4) { 1736 const uint64_t required_mask = 1737 dma_get_required_mask(&pdev->dev); 1738 if ((required_mask > DMA_BIT_MASK(32)) && 1739 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && 1740 !pci_set_consistent_dma_mask(pdev, consistent_dma_mask)) { 1741 ioc->base_add_sg_single = &_base_add_sg_single_64; 1742 ioc->sge_size = sizeof(Mpi2SGESimple64_t); 1743 ioc->dma_mask = 64; 1744 goto out; 1745 } 1746 } 1747 1748 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) 1749 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { 1750 ioc->base_add_sg_single = &_base_add_sg_single_32; 1751 ioc->sge_size = sizeof(Mpi2SGESimple32_t); 1752 ioc->dma_mask = 32; 1753 } else 1754 return -ENODEV; 1755 1756 out: 1757 si_meminfo(&s); 1758 pr_info(MPT3SAS_FMT 1759 "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n", 1760 ioc->name, ioc->dma_mask, convert_to_kb(s.totalram)); 1761 1762 return 0; 1763 } 1764 1765 static int 1766 _base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc, 1767 struct pci_dev *pdev) 1768 { 1769 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { 1770 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) 1771 return -ENODEV; 1772 } 1773 return 0; 1774 } 1775 1776 /** 1777 * _base_check_enable_msix - checks MSIX capabable. 1778 * @ioc: per adapter object 1779 * 1780 * Check to see if card is capable of MSIX, and set number 1781 * of available msix vectors 1782 */ 1783 static int 1784 _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc) 1785 { 1786 int base; 1787 u16 message_control; 1788 1789 /* Check whether controller SAS2008 B0 controller, 1790 * if it is SAS2008 B0 controller use IO-APIC instead of MSIX 1791 */ 1792 if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 && 1793 ioc->pdev->revision == SAS2_PCI_DEVICE_B0_REVISION) { 1794 return -EINVAL; 1795 } 1796 1797 base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX); 1798 if (!base) { 1799 dfailprintk(ioc, pr_info(MPT3SAS_FMT "msix not supported\n", 1800 ioc->name)); 1801 return -EINVAL; 1802 } 1803 1804 /* get msix vector count */ 1805 /* NUMA_IO not supported for older controllers */ 1806 if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 || 1807 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 || 1808 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 || 1809 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 || 1810 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 || 1811 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 || 1812 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2) 1813 ioc->msix_vector_count = 1; 1814 else { 1815 pci_read_config_word(ioc->pdev, base + 2, &message_control); 1816 ioc->msix_vector_count = (message_control & 0x3FF) + 1; 1817 } 1818 dinitprintk(ioc, pr_info(MPT3SAS_FMT 1819 "msix is supported, vector_count(%d)\n", 1820 ioc->name, ioc->msix_vector_count)); 1821 return 0; 1822 } 1823 1824 /** 1825 * _base_free_irq - free irq 1826 * @ioc: per adapter object 1827 * 1828 * Freeing respective reply_queue from the list. 1829 */ 1830 static void 1831 _base_free_irq(struct MPT3SAS_ADAPTER *ioc) 1832 { 1833 struct adapter_reply_queue *reply_q, *next; 1834 1835 if (list_empty(&ioc->reply_queue_list)) 1836 return; 1837 1838 list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) { 1839 list_del(&reply_q->list); 1840 free_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index), 1841 reply_q); 1842 kfree(reply_q); 1843 } 1844 } 1845 1846 /** 1847 * _base_request_irq - request irq 1848 * @ioc: per adapter object 1849 * @index: msix index into vector table 1850 * 1851 * Inserting respective reply_queue into the list. 1852 */ 1853 static int 1854 _base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index) 1855 { 1856 struct pci_dev *pdev = ioc->pdev; 1857 struct adapter_reply_queue *reply_q; 1858 int r; 1859 1860 reply_q = kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL); 1861 if (!reply_q) { 1862 pr_err(MPT3SAS_FMT "unable to allocate memory %d!\n", 1863 ioc->name, (int)sizeof(struct adapter_reply_queue)); 1864 return -ENOMEM; 1865 } 1866 reply_q->ioc = ioc; 1867 reply_q->msix_index = index; 1868 1869 atomic_set(&reply_q->busy, 0); 1870 if (ioc->msix_enable) 1871 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d", 1872 ioc->driver_name, ioc->id, index); 1873 else 1874 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d", 1875 ioc->driver_name, ioc->id); 1876 r = request_irq(pci_irq_vector(pdev, index), _base_interrupt, 1877 IRQF_SHARED, reply_q->name, reply_q); 1878 if (r) { 1879 pr_err(MPT3SAS_FMT "unable to allocate interrupt %d!\n", 1880 reply_q->name, pci_irq_vector(pdev, index)); 1881 kfree(reply_q); 1882 return -EBUSY; 1883 } 1884 1885 INIT_LIST_HEAD(&reply_q->list); 1886 list_add_tail(&reply_q->list, &ioc->reply_queue_list); 1887 return 0; 1888 } 1889 1890 /** 1891 * _base_assign_reply_queues - assigning msix index for each cpu 1892 * @ioc: per adapter object 1893 * 1894 * The enduser would need to set the affinity via /proc/irq/#/smp_affinity 1895 * 1896 * It would nice if we could call irq_set_affinity, however it is not 1897 * an exported symbol 1898 */ 1899 static void 1900 _base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc) 1901 { 1902 unsigned int cpu, nr_cpus, nr_msix, index = 0; 1903 struct adapter_reply_queue *reply_q; 1904 1905 if (!_base_is_controller_msix_enabled(ioc)) 1906 return; 1907 1908 memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz); 1909 1910 nr_cpus = num_online_cpus(); 1911 nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count, 1912 ioc->facts.MaxMSIxVectors); 1913 if (!nr_msix) 1914 return; 1915 1916 if (smp_affinity_enable) { 1917 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 1918 const cpumask_t *mask = pci_irq_get_affinity(ioc->pdev, 1919 reply_q->msix_index); 1920 if (!mask) { 1921 pr_warn(MPT3SAS_FMT "no affinity for msi %x\n", 1922 ioc->name, reply_q->msix_index); 1923 continue; 1924 } 1925 1926 for_each_cpu(cpu, mask) 1927 ioc->cpu_msix_table[cpu] = reply_q->msix_index; 1928 } 1929 return; 1930 } 1931 cpu = cpumask_first(cpu_online_mask); 1932 1933 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 1934 1935 unsigned int i, group = nr_cpus / nr_msix; 1936 1937 if (cpu >= nr_cpus) 1938 break; 1939 1940 if (index < nr_cpus % nr_msix) 1941 group++; 1942 1943 for (i = 0 ; i < group ; i++) { 1944 ioc->cpu_msix_table[cpu] = reply_q->msix_index; 1945 cpu = cpumask_next(cpu, cpu_online_mask); 1946 } 1947 index++; 1948 } 1949 } 1950 1951 /** 1952 * _base_disable_msix - disables msix 1953 * @ioc: per adapter object 1954 * 1955 */ 1956 static void 1957 _base_disable_msix(struct MPT3SAS_ADAPTER *ioc) 1958 { 1959 if (!ioc->msix_enable) 1960 return; 1961 pci_disable_msix(ioc->pdev); 1962 ioc->msix_enable = 0; 1963 } 1964 1965 /** 1966 * _base_enable_msix - enables msix, failback to io_apic 1967 * @ioc: per adapter object 1968 * 1969 */ 1970 static int 1971 _base_enable_msix(struct MPT3SAS_ADAPTER *ioc) 1972 { 1973 int r; 1974 int i, local_max_msix_vectors; 1975 u8 try_msix = 0; 1976 unsigned int irq_flags = PCI_IRQ_MSIX; 1977 1978 if (msix_disable == -1 || msix_disable == 0) 1979 try_msix = 1; 1980 1981 if (!try_msix) 1982 goto try_ioapic; 1983 1984 if (_base_check_enable_msix(ioc) != 0) 1985 goto try_ioapic; 1986 1987 ioc->reply_queue_count = min_t(int, ioc->cpu_count, 1988 ioc->msix_vector_count); 1989 1990 printk(MPT3SAS_FMT "MSI-X vectors supported: %d, no of cores" 1991 ": %d, max_msix_vectors: %d\n", ioc->name, ioc->msix_vector_count, 1992 ioc->cpu_count, max_msix_vectors); 1993 1994 if (!ioc->rdpq_array_enable && max_msix_vectors == -1) 1995 local_max_msix_vectors = 8; 1996 else 1997 local_max_msix_vectors = max_msix_vectors; 1998 1999 if (local_max_msix_vectors > 0) 2000 ioc->reply_queue_count = min_t(int, local_max_msix_vectors, 2001 ioc->reply_queue_count); 2002 else if (local_max_msix_vectors == 0) 2003 goto try_ioapic; 2004 2005 if (ioc->msix_vector_count < ioc->cpu_count) 2006 smp_affinity_enable = 0; 2007 2008 if (smp_affinity_enable) 2009 irq_flags |= PCI_IRQ_AFFINITY; 2010 2011 r = pci_alloc_irq_vectors(ioc->pdev, 1, ioc->reply_queue_count, 2012 irq_flags); 2013 if (r < 0) { 2014 dfailprintk(ioc, pr_info(MPT3SAS_FMT 2015 "pci_alloc_irq_vectors failed (r=%d) !!!\n", 2016 ioc->name, r)); 2017 goto try_ioapic; 2018 } 2019 2020 ioc->msix_enable = 1; 2021 ioc->reply_queue_count = r; 2022 for (i = 0; i < ioc->reply_queue_count; i++) { 2023 r = _base_request_irq(ioc, i); 2024 if (r) { 2025 _base_free_irq(ioc); 2026 _base_disable_msix(ioc); 2027 goto try_ioapic; 2028 } 2029 } 2030 2031 return 0; 2032 2033 /* failback to io_apic interrupt routing */ 2034 try_ioapic: 2035 2036 ioc->reply_queue_count = 1; 2037 r = pci_alloc_irq_vectors(ioc->pdev, 1, 1, PCI_IRQ_LEGACY); 2038 if (r < 0) { 2039 dfailprintk(ioc, pr_info(MPT3SAS_FMT 2040 "pci_alloc_irq_vector(legacy) failed (r=%d) !!!\n", 2041 ioc->name, r)); 2042 } else 2043 r = _base_request_irq(ioc, 0); 2044 2045 return r; 2046 } 2047 2048 /** 2049 * mpt3sas_base_unmap_resources - free controller resources 2050 * @ioc: per adapter object 2051 */ 2052 static void 2053 mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc) 2054 { 2055 struct pci_dev *pdev = ioc->pdev; 2056 2057 dexitprintk(ioc, printk(MPT3SAS_FMT "%s\n", 2058 ioc->name, __func__)); 2059 2060 _base_free_irq(ioc); 2061 _base_disable_msix(ioc); 2062 2063 if (ioc->combined_reply_queue) { 2064 kfree(ioc->replyPostRegisterIndex); 2065 ioc->replyPostRegisterIndex = NULL; 2066 } 2067 2068 if (ioc->chip_phys) { 2069 iounmap(ioc->chip); 2070 ioc->chip_phys = 0; 2071 } 2072 2073 if (pci_is_enabled(pdev)) { 2074 pci_release_selected_regions(ioc->pdev, ioc->bars); 2075 pci_disable_pcie_error_reporting(pdev); 2076 pci_disable_device(pdev); 2077 } 2078 } 2079 2080 /** 2081 * mpt3sas_base_map_resources - map in controller resources (io/irq/memap) 2082 * @ioc: per adapter object 2083 * 2084 * Returns 0 for success, non-zero for failure. 2085 */ 2086 int 2087 mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc) 2088 { 2089 struct pci_dev *pdev = ioc->pdev; 2090 u32 memap_sz; 2091 u32 pio_sz; 2092 int i, r = 0; 2093 u64 pio_chip = 0; 2094 u64 chip_phys = 0; 2095 struct adapter_reply_queue *reply_q; 2096 2097 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", 2098 ioc->name, __func__)); 2099 2100 ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM); 2101 if (pci_enable_device_mem(pdev)) { 2102 pr_warn(MPT3SAS_FMT "pci_enable_device_mem: failed\n", 2103 ioc->name); 2104 ioc->bars = 0; 2105 return -ENODEV; 2106 } 2107 2108 2109 if (pci_request_selected_regions(pdev, ioc->bars, 2110 ioc->driver_name)) { 2111 pr_warn(MPT3SAS_FMT "pci_request_selected_regions: failed\n", 2112 ioc->name); 2113 ioc->bars = 0; 2114 r = -ENODEV; 2115 goto out_fail; 2116 } 2117 2118 /* AER (Advanced Error Reporting) hooks */ 2119 pci_enable_pcie_error_reporting(pdev); 2120 2121 pci_set_master(pdev); 2122 2123 2124 if (_base_config_dma_addressing(ioc, pdev) != 0) { 2125 pr_warn(MPT3SAS_FMT "no suitable DMA mask for %s\n", 2126 ioc->name, pci_name(pdev)); 2127 r = -ENODEV; 2128 goto out_fail; 2129 } 2130 2131 for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) && 2132 (!memap_sz || !pio_sz); i++) { 2133 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) { 2134 if (pio_sz) 2135 continue; 2136 pio_chip = (u64)pci_resource_start(pdev, i); 2137 pio_sz = pci_resource_len(pdev, i); 2138 } else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) { 2139 if (memap_sz) 2140 continue; 2141 ioc->chip_phys = pci_resource_start(pdev, i); 2142 chip_phys = (u64)ioc->chip_phys; 2143 memap_sz = pci_resource_len(pdev, i); 2144 ioc->chip = ioremap(ioc->chip_phys, memap_sz); 2145 } 2146 } 2147 2148 if (ioc->chip == NULL) { 2149 pr_err(MPT3SAS_FMT "unable to map adapter memory! " 2150 " or resource not found\n", ioc->name); 2151 r = -EINVAL; 2152 goto out_fail; 2153 } 2154 2155 _base_mask_interrupts(ioc); 2156 2157 r = _base_get_ioc_facts(ioc); 2158 if (r) 2159 goto out_fail; 2160 2161 if (!ioc->rdpq_array_enable_assigned) { 2162 ioc->rdpq_array_enable = ioc->rdpq_array_capable; 2163 ioc->rdpq_array_enable_assigned = 1; 2164 } 2165 2166 r = _base_enable_msix(ioc); 2167 if (r) 2168 goto out_fail; 2169 2170 /* Use the Combined reply queue feature only for SAS3 C0 & higher 2171 * revision HBAs and also only when reply queue count is greater than 8 2172 */ 2173 if (ioc->combined_reply_queue && ioc->reply_queue_count > 8) { 2174 /* Determine the Supplemental Reply Post Host Index Registers 2175 * Addresse. Supplemental Reply Post Host Index Registers 2176 * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and 2177 * each register is at offset bytes of 2178 * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one. 2179 */ 2180 ioc->replyPostRegisterIndex = kcalloc( 2181 ioc->combined_reply_index_count, 2182 sizeof(resource_size_t *), GFP_KERNEL); 2183 if (!ioc->replyPostRegisterIndex) { 2184 dfailprintk(ioc, printk(MPT3SAS_FMT 2185 "allocation for reply Post Register Index failed!!!\n", 2186 ioc->name)); 2187 r = -ENOMEM; 2188 goto out_fail; 2189 } 2190 2191 for (i = 0; i < ioc->combined_reply_index_count; i++) { 2192 ioc->replyPostRegisterIndex[i] = (resource_size_t *) 2193 ((u8 *)&ioc->chip->Doorbell + 2194 MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET + 2195 (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET)); 2196 } 2197 } else 2198 ioc->combined_reply_queue = 0; 2199 2200 if (ioc->is_warpdrive) { 2201 ioc->reply_post_host_index[0] = (resource_size_t __iomem *) 2202 &ioc->chip->ReplyPostHostIndex; 2203 2204 for (i = 1; i < ioc->cpu_msix_table_sz; i++) 2205 ioc->reply_post_host_index[i] = 2206 (resource_size_t __iomem *) 2207 ((u8 __iomem *)&ioc->chip->Doorbell + (0x4000 + ((i - 1) 2208 * 4))); 2209 } 2210 2211 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) 2212 pr_info(MPT3SAS_FMT "%s: IRQ %d\n", 2213 reply_q->name, ((ioc->msix_enable) ? "PCI-MSI-X enabled" : 2214 "IO-APIC enabled"), 2215 pci_irq_vector(ioc->pdev, reply_q->msix_index)); 2216 2217 pr_info(MPT3SAS_FMT "iomem(0x%016llx), mapped(0x%p), size(%d)\n", 2218 ioc->name, (unsigned long long)chip_phys, ioc->chip, memap_sz); 2219 pr_info(MPT3SAS_FMT "ioport(0x%016llx), size(%d)\n", 2220 ioc->name, (unsigned long long)pio_chip, pio_sz); 2221 2222 /* Save PCI configuration state for recovery from PCI AER/EEH errors */ 2223 pci_save_state(pdev); 2224 return 0; 2225 2226 out_fail: 2227 mpt3sas_base_unmap_resources(ioc); 2228 return r; 2229 } 2230 2231 /** 2232 * mpt3sas_base_get_msg_frame - obtain request mf pointer 2233 * @ioc: per adapter object 2234 * @smid: system request message index(smid zero is invalid) 2235 * 2236 * Returns virt pointer to message frame. 2237 */ 2238 void * 2239 mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid) 2240 { 2241 return (void *)(ioc->request + (smid * ioc->request_sz)); 2242 } 2243 2244 /** 2245 * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr 2246 * @ioc: per adapter object 2247 * @smid: system request message index 2248 * 2249 * Returns virt pointer to sense buffer. 2250 */ 2251 void * 2252 mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid) 2253 { 2254 return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE)); 2255 } 2256 2257 /** 2258 * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr 2259 * @ioc: per adapter object 2260 * @smid: system request message index 2261 * 2262 * Returns phys pointer to the low 32bit address of the sense buffer. 2263 */ 2264 __le32 2265 mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid) 2266 { 2267 return cpu_to_le32(ioc->sense_dma + ((smid - 1) * 2268 SCSI_SENSE_BUFFERSIZE)); 2269 } 2270 2271 /** 2272 * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address 2273 * @ioc: per adapter object 2274 * @phys_addr: lower 32 physical addr of the reply 2275 * 2276 * Converts 32bit lower physical addr into a virt address. 2277 */ 2278 void * 2279 mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr) 2280 { 2281 if (!phys_addr) 2282 return NULL; 2283 return ioc->reply + (phys_addr - (u32)ioc->reply_dma); 2284 } 2285 2286 static inline u8 2287 _base_get_msix_index(struct MPT3SAS_ADAPTER *ioc) 2288 { 2289 return ioc->cpu_msix_table[raw_smp_processor_id()]; 2290 } 2291 2292 /** 2293 * mpt3sas_base_get_smid - obtain a free smid from internal queue 2294 * @ioc: per adapter object 2295 * @cb_idx: callback index 2296 * 2297 * Returns smid (zero is invalid) 2298 */ 2299 u16 2300 mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx) 2301 { 2302 unsigned long flags; 2303 struct request_tracker *request; 2304 u16 smid; 2305 2306 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 2307 if (list_empty(&ioc->internal_free_list)) { 2308 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2309 pr_err(MPT3SAS_FMT "%s: smid not available\n", 2310 ioc->name, __func__); 2311 return 0; 2312 } 2313 2314 request = list_entry(ioc->internal_free_list.next, 2315 struct request_tracker, tracker_list); 2316 request->cb_idx = cb_idx; 2317 smid = request->smid; 2318 list_del(&request->tracker_list); 2319 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2320 return smid; 2321 } 2322 2323 /** 2324 * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue 2325 * @ioc: per adapter object 2326 * @cb_idx: callback index 2327 * @scmd: pointer to scsi command object 2328 * 2329 * Returns smid (zero is invalid) 2330 */ 2331 u16 2332 mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx, 2333 struct scsi_cmnd *scmd) 2334 { 2335 unsigned long flags; 2336 struct scsiio_tracker *request; 2337 u16 smid; 2338 2339 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 2340 if (list_empty(&ioc->free_list)) { 2341 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2342 pr_err(MPT3SAS_FMT "%s: smid not available\n", 2343 ioc->name, __func__); 2344 return 0; 2345 } 2346 2347 request = list_entry(ioc->free_list.next, 2348 struct scsiio_tracker, tracker_list); 2349 request->scmd = scmd; 2350 request->cb_idx = cb_idx; 2351 smid = request->smid; 2352 request->msix_io = _base_get_msix_index(ioc); 2353 list_del(&request->tracker_list); 2354 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2355 return smid; 2356 } 2357 2358 /** 2359 * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue 2360 * @ioc: per adapter object 2361 * @cb_idx: callback index 2362 * 2363 * Returns smid (zero is invalid) 2364 */ 2365 u16 2366 mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx) 2367 { 2368 unsigned long flags; 2369 struct request_tracker *request; 2370 u16 smid; 2371 2372 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 2373 if (list_empty(&ioc->hpr_free_list)) { 2374 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2375 return 0; 2376 } 2377 2378 request = list_entry(ioc->hpr_free_list.next, 2379 struct request_tracker, tracker_list); 2380 request->cb_idx = cb_idx; 2381 smid = request->smid; 2382 list_del(&request->tracker_list); 2383 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2384 return smid; 2385 } 2386 2387 /** 2388 * mpt3sas_base_free_smid - put smid back on free_list 2389 * @ioc: per adapter object 2390 * @smid: system request message index 2391 * 2392 * Return nothing. 2393 */ 2394 void 2395 mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid) 2396 { 2397 unsigned long flags; 2398 int i; 2399 struct chain_tracker *chain_req, *next; 2400 2401 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 2402 if (smid < ioc->hi_priority_smid) { 2403 /* scsiio queue */ 2404 i = smid - 1; 2405 if (!list_empty(&ioc->scsi_lookup[i].chain_list)) { 2406 list_for_each_entry_safe(chain_req, next, 2407 &ioc->scsi_lookup[i].chain_list, tracker_list) { 2408 list_del_init(&chain_req->tracker_list); 2409 list_add(&chain_req->tracker_list, 2410 &ioc->free_chain_list); 2411 } 2412 } 2413 ioc->scsi_lookup[i].cb_idx = 0xFF; 2414 ioc->scsi_lookup[i].scmd = NULL; 2415 ioc->scsi_lookup[i].direct_io = 0; 2416 list_add(&ioc->scsi_lookup[i].tracker_list, &ioc->free_list); 2417 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2418 2419 /* 2420 * See _wait_for_commands_to_complete() call with regards 2421 * to this code. 2422 */ 2423 if (ioc->shost_recovery && ioc->pending_io_count) { 2424 if (ioc->pending_io_count == 1) 2425 wake_up(&ioc->reset_wq); 2426 ioc->pending_io_count--; 2427 } 2428 return; 2429 } else if (smid < ioc->internal_smid) { 2430 /* hi-priority */ 2431 i = smid - ioc->hi_priority_smid; 2432 ioc->hpr_lookup[i].cb_idx = 0xFF; 2433 list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list); 2434 } else if (smid <= ioc->hba_queue_depth) { 2435 /* internal queue */ 2436 i = smid - ioc->internal_smid; 2437 ioc->internal_lookup[i].cb_idx = 0xFF; 2438 list_add(&ioc->internal_lookup[i].tracker_list, 2439 &ioc->internal_free_list); 2440 } 2441 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2442 } 2443 2444 /** 2445 * _base_writeq - 64 bit write to MMIO 2446 * @ioc: per adapter object 2447 * @b: data payload 2448 * @addr: address in MMIO space 2449 * @writeq_lock: spin lock 2450 * 2451 * Glue for handling an atomic 64 bit word to MMIO. This special handling takes 2452 * care of 32 bit environment where its not quarenteed to send the entire word 2453 * in one transfer. 2454 */ 2455 #if defined(writeq) && defined(CONFIG_64BIT) 2456 static inline void 2457 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock) 2458 { 2459 writeq(cpu_to_le64(b), addr); 2460 } 2461 #else 2462 static inline void 2463 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock) 2464 { 2465 unsigned long flags; 2466 __u64 data_out = cpu_to_le64(b); 2467 2468 spin_lock_irqsave(writeq_lock, flags); 2469 writel((u32)(data_out), addr); 2470 writel((u32)(data_out >> 32), (addr + 4)); 2471 spin_unlock_irqrestore(writeq_lock, flags); 2472 } 2473 #endif 2474 2475 /** 2476 * _base_put_smid_scsi_io - send SCSI_IO request to firmware 2477 * @ioc: per adapter object 2478 * @smid: system request message index 2479 * @handle: device handle 2480 * 2481 * Return nothing. 2482 */ 2483 static void 2484 _base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle) 2485 { 2486 Mpi2RequestDescriptorUnion_t descriptor; 2487 u64 *request = (u64 *)&descriptor; 2488 2489 2490 descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; 2491 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc); 2492 descriptor.SCSIIO.SMID = cpu_to_le16(smid); 2493 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle); 2494 descriptor.SCSIIO.LMID = 0; 2495 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 2496 &ioc->scsi_lookup_lock); 2497 } 2498 2499 /** 2500 * _base_put_smid_fast_path - send fast path request to firmware 2501 * @ioc: per adapter object 2502 * @smid: system request message index 2503 * @handle: device handle 2504 * 2505 * Return nothing. 2506 */ 2507 static void 2508 _base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid, 2509 u16 handle) 2510 { 2511 Mpi2RequestDescriptorUnion_t descriptor; 2512 u64 *request = (u64 *)&descriptor; 2513 2514 descriptor.SCSIIO.RequestFlags = 2515 MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO; 2516 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc); 2517 descriptor.SCSIIO.SMID = cpu_to_le16(smid); 2518 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle); 2519 descriptor.SCSIIO.LMID = 0; 2520 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 2521 &ioc->scsi_lookup_lock); 2522 } 2523 2524 /** 2525 * _base_put_smid_hi_priority - send Task Management request to firmware 2526 * @ioc: per adapter object 2527 * @smid: system request message index 2528 * @msix_task: msix_task will be same as msix of IO incase of task abort else 0. 2529 * Return nothing. 2530 */ 2531 static void 2532 _base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid, 2533 u16 msix_task) 2534 { 2535 Mpi2RequestDescriptorUnion_t descriptor; 2536 u64 *request = (u64 *)&descriptor; 2537 2538 descriptor.HighPriority.RequestFlags = 2539 MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY; 2540 descriptor.HighPriority.MSIxIndex = msix_task; 2541 descriptor.HighPriority.SMID = cpu_to_le16(smid); 2542 descriptor.HighPriority.LMID = 0; 2543 descriptor.HighPriority.Reserved1 = 0; 2544 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 2545 &ioc->scsi_lookup_lock); 2546 } 2547 2548 /** 2549 * _base_put_smid_default - Default, primarily used for config pages 2550 * @ioc: per adapter object 2551 * @smid: system request message index 2552 * 2553 * Return nothing. 2554 */ 2555 static void 2556 _base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid) 2557 { 2558 Mpi2RequestDescriptorUnion_t descriptor; 2559 u64 *request = (u64 *)&descriptor; 2560 2561 descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 2562 descriptor.Default.MSIxIndex = _base_get_msix_index(ioc); 2563 descriptor.Default.SMID = cpu_to_le16(smid); 2564 descriptor.Default.LMID = 0; 2565 descriptor.Default.DescriptorTypeDependent = 0; 2566 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 2567 &ioc->scsi_lookup_lock); 2568 } 2569 2570 /** 2571 * _base_put_smid_scsi_io_atomic - send SCSI_IO request to firmware using 2572 * Atomic Request Descriptor 2573 * @ioc: per adapter object 2574 * @smid: system request message index 2575 * @handle: device handle, unused in this function, for function type match 2576 * 2577 * Return nothing. 2578 */ 2579 static void 2580 _base_put_smid_scsi_io_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid, 2581 u16 handle) 2582 { 2583 Mpi26AtomicRequestDescriptor_t descriptor; 2584 u32 *request = (u32 *)&descriptor; 2585 2586 descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; 2587 descriptor.MSIxIndex = _base_get_msix_index(ioc); 2588 descriptor.SMID = cpu_to_le16(smid); 2589 2590 writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost); 2591 } 2592 2593 /** 2594 * _base_put_smid_fast_path_atomic - send fast path request to firmware 2595 * using Atomic Request Descriptor 2596 * @ioc: per adapter object 2597 * @smid: system request message index 2598 * @handle: device handle, unused in this function, for function type match 2599 * Return nothing 2600 */ 2601 static void 2602 _base_put_smid_fast_path_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid, 2603 u16 handle) 2604 { 2605 Mpi26AtomicRequestDescriptor_t descriptor; 2606 u32 *request = (u32 *)&descriptor; 2607 2608 descriptor.RequestFlags = MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO; 2609 descriptor.MSIxIndex = _base_get_msix_index(ioc); 2610 descriptor.SMID = cpu_to_le16(smid); 2611 2612 writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost); 2613 } 2614 2615 /** 2616 * _base_put_smid_hi_priority_atomic - send Task Management request to 2617 * firmware using Atomic Request Descriptor 2618 * @ioc: per adapter object 2619 * @smid: system request message index 2620 * @msix_task: msix_task will be same as msix of IO incase of task abort else 0 2621 * 2622 * Return nothing. 2623 */ 2624 static void 2625 _base_put_smid_hi_priority_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid, 2626 u16 msix_task) 2627 { 2628 Mpi26AtomicRequestDescriptor_t descriptor; 2629 u32 *request = (u32 *)&descriptor; 2630 2631 descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY; 2632 descriptor.MSIxIndex = msix_task; 2633 descriptor.SMID = cpu_to_le16(smid); 2634 2635 writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost); 2636 } 2637 2638 /** 2639 * _base_put_smid_default - Default, primarily used for config pages 2640 * use Atomic Request Descriptor 2641 * @ioc: per adapter object 2642 * @smid: system request message index 2643 * 2644 * Return nothing. 2645 */ 2646 static void 2647 _base_put_smid_default_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid) 2648 { 2649 Mpi26AtomicRequestDescriptor_t descriptor; 2650 u32 *request = (u32 *)&descriptor; 2651 2652 descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 2653 descriptor.MSIxIndex = _base_get_msix_index(ioc); 2654 descriptor.SMID = cpu_to_le16(smid); 2655 2656 writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost); 2657 } 2658 2659 /** 2660 * _base_display_OEMs_branding - Display branding string 2661 * @ioc: per adapter object 2662 * 2663 * Return nothing. 2664 */ 2665 static void 2666 _base_display_OEMs_branding(struct MPT3SAS_ADAPTER *ioc) 2667 { 2668 if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL) 2669 return; 2670 2671 switch (ioc->pdev->subsystem_vendor) { 2672 case PCI_VENDOR_ID_INTEL: 2673 switch (ioc->pdev->device) { 2674 case MPI2_MFGPAGE_DEVID_SAS2008: 2675 switch (ioc->pdev->subsystem_device) { 2676 case MPT2SAS_INTEL_RMS2LL080_SSDID: 2677 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2678 MPT2SAS_INTEL_RMS2LL080_BRANDING); 2679 break; 2680 case MPT2SAS_INTEL_RMS2LL040_SSDID: 2681 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2682 MPT2SAS_INTEL_RMS2LL040_BRANDING); 2683 break; 2684 case MPT2SAS_INTEL_SSD910_SSDID: 2685 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2686 MPT2SAS_INTEL_SSD910_BRANDING); 2687 break; 2688 default: 2689 pr_info(MPT3SAS_FMT 2690 "Intel(R) Controller: Subsystem ID: 0x%X\n", 2691 ioc->name, ioc->pdev->subsystem_device); 2692 break; 2693 } 2694 case MPI2_MFGPAGE_DEVID_SAS2308_2: 2695 switch (ioc->pdev->subsystem_device) { 2696 case MPT2SAS_INTEL_RS25GB008_SSDID: 2697 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2698 MPT2SAS_INTEL_RS25GB008_BRANDING); 2699 break; 2700 case MPT2SAS_INTEL_RMS25JB080_SSDID: 2701 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2702 MPT2SAS_INTEL_RMS25JB080_BRANDING); 2703 break; 2704 case MPT2SAS_INTEL_RMS25JB040_SSDID: 2705 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2706 MPT2SAS_INTEL_RMS25JB040_BRANDING); 2707 break; 2708 case MPT2SAS_INTEL_RMS25KB080_SSDID: 2709 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2710 MPT2SAS_INTEL_RMS25KB080_BRANDING); 2711 break; 2712 case MPT2SAS_INTEL_RMS25KB040_SSDID: 2713 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2714 MPT2SAS_INTEL_RMS25KB040_BRANDING); 2715 break; 2716 case MPT2SAS_INTEL_RMS25LB040_SSDID: 2717 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2718 MPT2SAS_INTEL_RMS25LB040_BRANDING); 2719 break; 2720 case MPT2SAS_INTEL_RMS25LB080_SSDID: 2721 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2722 MPT2SAS_INTEL_RMS25LB080_BRANDING); 2723 break; 2724 default: 2725 pr_info(MPT3SAS_FMT 2726 "Intel(R) Controller: Subsystem ID: 0x%X\n", 2727 ioc->name, ioc->pdev->subsystem_device); 2728 break; 2729 } 2730 case MPI25_MFGPAGE_DEVID_SAS3008: 2731 switch (ioc->pdev->subsystem_device) { 2732 case MPT3SAS_INTEL_RMS3JC080_SSDID: 2733 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2734 MPT3SAS_INTEL_RMS3JC080_BRANDING); 2735 break; 2736 2737 case MPT3SAS_INTEL_RS3GC008_SSDID: 2738 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2739 MPT3SAS_INTEL_RS3GC008_BRANDING); 2740 break; 2741 case MPT3SAS_INTEL_RS3FC044_SSDID: 2742 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2743 MPT3SAS_INTEL_RS3FC044_BRANDING); 2744 break; 2745 case MPT3SAS_INTEL_RS3UC080_SSDID: 2746 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2747 MPT3SAS_INTEL_RS3UC080_BRANDING); 2748 break; 2749 default: 2750 pr_info(MPT3SAS_FMT 2751 "Intel(R) Controller: Subsystem ID: 0x%X\n", 2752 ioc->name, ioc->pdev->subsystem_device); 2753 break; 2754 } 2755 break; 2756 default: 2757 pr_info(MPT3SAS_FMT 2758 "Intel(R) Controller: Subsystem ID: 0x%X\n", 2759 ioc->name, ioc->pdev->subsystem_device); 2760 break; 2761 } 2762 break; 2763 case PCI_VENDOR_ID_DELL: 2764 switch (ioc->pdev->device) { 2765 case MPI2_MFGPAGE_DEVID_SAS2008: 2766 switch (ioc->pdev->subsystem_device) { 2767 case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID: 2768 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2769 MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING); 2770 break; 2771 case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID: 2772 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2773 MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING); 2774 break; 2775 case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID: 2776 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2777 MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING); 2778 break; 2779 case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID: 2780 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2781 MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING); 2782 break; 2783 case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID: 2784 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2785 MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING); 2786 break; 2787 case MPT2SAS_DELL_PERC_H200_SSDID: 2788 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2789 MPT2SAS_DELL_PERC_H200_BRANDING); 2790 break; 2791 case MPT2SAS_DELL_6GBPS_SAS_SSDID: 2792 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2793 MPT2SAS_DELL_6GBPS_SAS_BRANDING); 2794 break; 2795 default: 2796 pr_info(MPT3SAS_FMT 2797 "Dell 6Gbps HBA: Subsystem ID: 0x%X\n", 2798 ioc->name, ioc->pdev->subsystem_device); 2799 break; 2800 } 2801 break; 2802 case MPI25_MFGPAGE_DEVID_SAS3008: 2803 switch (ioc->pdev->subsystem_device) { 2804 case MPT3SAS_DELL_12G_HBA_SSDID: 2805 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2806 MPT3SAS_DELL_12G_HBA_BRANDING); 2807 break; 2808 default: 2809 pr_info(MPT3SAS_FMT 2810 "Dell 12Gbps HBA: Subsystem ID: 0x%X\n", 2811 ioc->name, ioc->pdev->subsystem_device); 2812 break; 2813 } 2814 break; 2815 default: 2816 pr_info(MPT3SAS_FMT 2817 "Dell HBA: Subsystem ID: 0x%X\n", ioc->name, 2818 ioc->pdev->subsystem_device); 2819 break; 2820 } 2821 break; 2822 case PCI_VENDOR_ID_CISCO: 2823 switch (ioc->pdev->device) { 2824 case MPI25_MFGPAGE_DEVID_SAS3008: 2825 switch (ioc->pdev->subsystem_device) { 2826 case MPT3SAS_CISCO_12G_8E_HBA_SSDID: 2827 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2828 MPT3SAS_CISCO_12G_8E_HBA_BRANDING); 2829 break; 2830 case MPT3SAS_CISCO_12G_8I_HBA_SSDID: 2831 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2832 MPT3SAS_CISCO_12G_8I_HBA_BRANDING); 2833 break; 2834 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID: 2835 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2836 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING); 2837 break; 2838 default: 2839 pr_info(MPT3SAS_FMT 2840 "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n", 2841 ioc->name, ioc->pdev->subsystem_device); 2842 break; 2843 } 2844 break; 2845 case MPI25_MFGPAGE_DEVID_SAS3108_1: 2846 switch (ioc->pdev->subsystem_device) { 2847 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID: 2848 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2849 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING); 2850 break; 2851 case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID: 2852 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2853 MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING 2854 ); 2855 break; 2856 default: 2857 pr_info(MPT3SAS_FMT 2858 "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n", 2859 ioc->name, ioc->pdev->subsystem_device); 2860 break; 2861 } 2862 break; 2863 default: 2864 pr_info(MPT3SAS_FMT 2865 "Cisco SAS HBA: Subsystem ID: 0x%X\n", 2866 ioc->name, ioc->pdev->subsystem_device); 2867 break; 2868 } 2869 break; 2870 case MPT2SAS_HP_3PAR_SSVID: 2871 switch (ioc->pdev->device) { 2872 case MPI2_MFGPAGE_DEVID_SAS2004: 2873 switch (ioc->pdev->subsystem_device) { 2874 case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID: 2875 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2876 MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING); 2877 break; 2878 default: 2879 pr_info(MPT3SAS_FMT 2880 "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n", 2881 ioc->name, ioc->pdev->subsystem_device); 2882 break; 2883 } 2884 case MPI2_MFGPAGE_DEVID_SAS2308_2: 2885 switch (ioc->pdev->subsystem_device) { 2886 case MPT2SAS_HP_2_4_INTERNAL_SSDID: 2887 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2888 MPT2SAS_HP_2_4_INTERNAL_BRANDING); 2889 break; 2890 case MPT2SAS_HP_2_4_EXTERNAL_SSDID: 2891 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2892 MPT2SAS_HP_2_4_EXTERNAL_BRANDING); 2893 break; 2894 case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID: 2895 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2896 MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING); 2897 break; 2898 case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID: 2899 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2900 MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING); 2901 break; 2902 default: 2903 pr_info(MPT3SAS_FMT 2904 "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n", 2905 ioc->name, ioc->pdev->subsystem_device); 2906 break; 2907 } 2908 default: 2909 pr_info(MPT3SAS_FMT 2910 "HP SAS HBA: Subsystem ID: 0x%X\n", 2911 ioc->name, ioc->pdev->subsystem_device); 2912 break; 2913 } 2914 default: 2915 break; 2916 } 2917 } 2918 2919 /** 2920 * _base_display_ioc_capabilities - Disply IOC's capabilities. 2921 * @ioc: per adapter object 2922 * 2923 * Return nothing. 2924 */ 2925 static void 2926 _base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc) 2927 { 2928 int i = 0; 2929 char desc[16]; 2930 u32 iounit_pg1_flags; 2931 u32 bios_version; 2932 2933 bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion); 2934 strncpy(desc, ioc->manu_pg0.ChipName, 16); 2935 pr_info(MPT3SAS_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "\ 2936 "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n", 2937 ioc->name, desc, 2938 (ioc->facts.FWVersion.Word & 0xFF000000) >> 24, 2939 (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16, 2940 (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8, 2941 ioc->facts.FWVersion.Word & 0x000000FF, 2942 ioc->pdev->revision, 2943 (bios_version & 0xFF000000) >> 24, 2944 (bios_version & 0x00FF0000) >> 16, 2945 (bios_version & 0x0000FF00) >> 8, 2946 bios_version & 0x000000FF); 2947 2948 _base_display_OEMs_branding(ioc); 2949 2950 pr_info(MPT3SAS_FMT "Protocol=(", ioc->name); 2951 2952 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) { 2953 pr_info("Initiator"); 2954 i++; 2955 } 2956 2957 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) { 2958 pr_info("%sTarget", i ? "," : ""); 2959 i++; 2960 } 2961 2962 i = 0; 2963 pr_info("), "); 2964 pr_info("Capabilities=("); 2965 2966 if (!ioc->hide_ir_msg) { 2967 if (ioc->facts.IOCCapabilities & 2968 MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) { 2969 pr_info("Raid"); 2970 i++; 2971 } 2972 } 2973 2974 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) { 2975 pr_info("%sTLR", i ? "," : ""); 2976 i++; 2977 } 2978 2979 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) { 2980 pr_info("%sMulticast", i ? "," : ""); 2981 i++; 2982 } 2983 2984 if (ioc->facts.IOCCapabilities & 2985 MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) { 2986 pr_info("%sBIDI Target", i ? "," : ""); 2987 i++; 2988 } 2989 2990 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) { 2991 pr_info("%sEEDP", i ? "," : ""); 2992 i++; 2993 } 2994 2995 if (ioc->facts.IOCCapabilities & 2996 MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) { 2997 pr_info("%sSnapshot Buffer", i ? "," : ""); 2998 i++; 2999 } 3000 3001 if (ioc->facts.IOCCapabilities & 3002 MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) { 3003 pr_info("%sDiag Trace Buffer", i ? "," : ""); 3004 i++; 3005 } 3006 3007 if (ioc->facts.IOCCapabilities & 3008 MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) { 3009 pr_info("%sDiag Extended Buffer", i ? "," : ""); 3010 i++; 3011 } 3012 3013 if (ioc->facts.IOCCapabilities & 3014 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) { 3015 pr_info("%sTask Set Full", i ? "," : ""); 3016 i++; 3017 } 3018 3019 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags); 3020 if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) { 3021 pr_info("%sNCQ", i ? "," : ""); 3022 i++; 3023 } 3024 3025 pr_info(")\n"); 3026 } 3027 3028 /** 3029 * mpt3sas_base_update_missing_delay - change the missing delay timers 3030 * @ioc: per adapter object 3031 * @device_missing_delay: amount of time till device is reported missing 3032 * @io_missing_delay: interval IO is returned when there is a missing device 3033 * 3034 * Return nothing. 3035 * 3036 * Passed on the command line, this function will modify the device missing 3037 * delay, as well as the io missing delay. This should be called at driver 3038 * load time. 3039 */ 3040 void 3041 mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc, 3042 u16 device_missing_delay, u8 io_missing_delay) 3043 { 3044 u16 dmd, dmd_new, dmd_orignal; 3045 u8 io_missing_delay_original; 3046 u16 sz; 3047 Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL; 3048 Mpi2ConfigReply_t mpi_reply; 3049 u8 num_phys = 0; 3050 u16 ioc_status; 3051 3052 mpt3sas_config_get_number_hba_phys(ioc, &num_phys); 3053 if (!num_phys) 3054 return; 3055 3056 sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys * 3057 sizeof(Mpi2SasIOUnit1PhyData_t)); 3058 sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL); 3059 if (!sas_iounit_pg1) { 3060 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n", 3061 ioc->name, __FILE__, __LINE__, __func__); 3062 goto out; 3063 } 3064 if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply, 3065 sas_iounit_pg1, sz))) { 3066 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n", 3067 ioc->name, __FILE__, __LINE__, __func__); 3068 goto out; 3069 } 3070 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & 3071 MPI2_IOCSTATUS_MASK; 3072 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 3073 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n", 3074 ioc->name, __FILE__, __LINE__, __func__); 3075 goto out; 3076 } 3077 3078 /* device missing delay */ 3079 dmd = sas_iounit_pg1->ReportDeviceMissingDelay; 3080 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16) 3081 dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16; 3082 else 3083 dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK; 3084 dmd_orignal = dmd; 3085 if (device_missing_delay > 0x7F) { 3086 dmd = (device_missing_delay > 0x7F0) ? 0x7F0 : 3087 device_missing_delay; 3088 dmd = dmd / 16; 3089 dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16; 3090 } else 3091 dmd = device_missing_delay; 3092 sas_iounit_pg1->ReportDeviceMissingDelay = dmd; 3093 3094 /* io missing delay */ 3095 io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay; 3096 sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay; 3097 3098 if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1, 3099 sz)) { 3100 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16) 3101 dmd_new = (dmd & 3102 MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16; 3103 else 3104 dmd_new = 3105 dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK; 3106 pr_info(MPT3SAS_FMT "device_missing_delay: old(%d), new(%d)\n", 3107 ioc->name, dmd_orignal, dmd_new); 3108 pr_info(MPT3SAS_FMT "ioc_missing_delay: old(%d), new(%d)\n", 3109 ioc->name, io_missing_delay_original, 3110 io_missing_delay); 3111 ioc->device_missing_delay = dmd_new; 3112 ioc->io_missing_delay = io_missing_delay; 3113 } 3114 3115 out: 3116 kfree(sas_iounit_pg1); 3117 } 3118 /** 3119 * _base_static_config_pages - static start of day config pages 3120 * @ioc: per adapter object 3121 * 3122 * Return nothing. 3123 */ 3124 static void 3125 _base_static_config_pages(struct MPT3SAS_ADAPTER *ioc) 3126 { 3127 Mpi2ConfigReply_t mpi_reply; 3128 u32 iounit_pg1_flags; 3129 3130 mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0); 3131 if (ioc->ir_firmware) 3132 mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply, 3133 &ioc->manu_pg10); 3134 3135 /* 3136 * Ensure correct T10 PI operation if vendor left EEDPTagMode 3137 * flag unset in NVDATA. 3138 */ 3139 mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply, &ioc->manu_pg11); 3140 if (ioc->manu_pg11.EEDPTagMode == 0) { 3141 pr_err("%s: overriding NVDATA EEDPTagMode setting\n", 3142 ioc->name); 3143 ioc->manu_pg11.EEDPTagMode &= ~0x3; 3144 ioc->manu_pg11.EEDPTagMode |= 0x1; 3145 mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply, 3146 &ioc->manu_pg11); 3147 } 3148 3149 mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2); 3150 mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3); 3151 mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8); 3152 mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0); 3153 mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1); 3154 mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8); 3155 _base_display_ioc_capabilities(ioc); 3156 3157 /* 3158 * Enable task_set_full handling in iounit_pg1 when the 3159 * facts capabilities indicate that its supported. 3160 */ 3161 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags); 3162 if ((ioc->facts.IOCCapabilities & 3163 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING)) 3164 iounit_pg1_flags &= 3165 ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING; 3166 else 3167 iounit_pg1_flags |= 3168 MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING; 3169 ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags); 3170 mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1); 3171 3172 if (ioc->iounit_pg8.NumSensors) 3173 ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors; 3174 } 3175 3176 /** 3177 * _base_release_memory_pools - release memory 3178 * @ioc: per adapter object 3179 * 3180 * Free memory allocated from _base_allocate_memory_pools. 3181 * 3182 * Return nothing. 3183 */ 3184 static void 3185 _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc) 3186 { 3187 int i = 0; 3188 struct reply_post_struct *rps; 3189 3190 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3191 __func__)); 3192 3193 if (ioc->request) { 3194 pci_free_consistent(ioc->pdev, ioc->request_dma_sz, 3195 ioc->request, ioc->request_dma); 3196 dexitprintk(ioc, pr_info(MPT3SAS_FMT 3197 "request_pool(0x%p): free\n", 3198 ioc->name, ioc->request)); 3199 ioc->request = NULL; 3200 } 3201 3202 if (ioc->sense) { 3203 pci_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma); 3204 if (ioc->sense_dma_pool) 3205 pci_pool_destroy(ioc->sense_dma_pool); 3206 dexitprintk(ioc, pr_info(MPT3SAS_FMT 3207 "sense_pool(0x%p): free\n", 3208 ioc->name, ioc->sense)); 3209 ioc->sense = NULL; 3210 } 3211 3212 if (ioc->reply) { 3213 pci_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma); 3214 if (ioc->reply_dma_pool) 3215 pci_pool_destroy(ioc->reply_dma_pool); 3216 dexitprintk(ioc, pr_info(MPT3SAS_FMT 3217 "reply_pool(0x%p): free\n", 3218 ioc->name, ioc->reply)); 3219 ioc->reply = NULL; 3220 } 3221 3222 if (ioc->reply_free) { 3223 pci_pool_free(ioc->reply_free_dma_pool, ioc->reply_free, 3224 ioc->reply_free_dma); 3225 if (ioc->reply_free_dma_pool) 3226 pci_pool_destroy(ioc->reply_free_dma_pool); 3227 dexitprintk(ioc, pr_info(MPT3SAS_FMT 3228 "reply_free_pool(0x%p): free\n", 3229 ioc->name, ioc->reply_free)); 3230 ioc->reply_free = NULL; 3231 } 3232 3233 if (ioc->reply_post) { 3234 do { 3235 rps = &ioc->reply_post[i]; 3236 if (rps->reply_post_free) { 3237 pci_pool_free( 3238 ioc->reply_post_free_dma_pool, 3239 rps->reply_post_free, 3240 rps->reply_post_free_dma); 3241 dexitprintk(ioc, pr_info(MPT3SAS_FMT 3242 "reply_post_free_pool(0x%p): free\n", 3243 ioc->name, rps->reply_post_free)); 3244 rps->reply_post_free = NULL; 3245 } 3246 } while (ioc->rdpq_array_enable && 3247 (++i < ioc->reply_queue_count)); 3248 3249 if (ioc->reply_post_free_dma_pool) 3250 pci_pool_destroy(ioc->reply_post_free_dma_pool); 3251 kfree(ioc->reply_post); 3252 } 3253 3254 if (ioc->config_page) { 3255 dexitprintk(ioc, pr_info(MPT3SAS_FMT 3256 "config_page(0x%p): free\n", ioc->name, 3257 ioc->config_page)); 3258 pci_free_consistent(ioc->pdev, ioc->config_page_sz, 3259 ioc->config_page, ioc->config_page_dma); 3260 } 3261 3262 if (ioc->scsi_lookup) { 3263 free_pages((ulong)ioc->scsi_lookup, ioc->scsi_lookup_pages); 3264 ioc->scsi_lookup = NULL; 3265 } 3266 kfree(ioc->hpr_lookup); 3267 kfree(ioc->internal_lookup); 3268 if (ioc->chain_lookup) { 3269 for (i = 0; i < ioc->chain_depth; i++) { 3270 if (ioc->chain_lookup[i].chain_buffer) 3271 pci_pool_free(ioc->chain_dma_pool, 3272 ioc->chain_lookup[i].chain_buffer, 3273 ioc->chain_lookup[i].chain_buffer_dma); 3274 } 3275 if (ioc->chain_dma_pool) 3276 pci_pool_destroy(ioc->chain_dma_pool); 3277 free_pages((ulong)ioc->chain_lookup, ioc->chain_pages); 3278 ioc->chain_lookup = NULL; 3279 } 3280 } 3281 3282 /** 3283 * _base_allocate_memory_pools - allocate start of day memory pools 3284 * @ioc: per adapter object 3285 * 3286 * Returns 0 success, anything else error 3287 */ 3288 static int 3289 _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) 3290 { 3291 struct mpt3sas_facts *facts; 3292 u16 max_sge_elements; 3293 u16 chains_needed_per_io; 3294 u32 sz, total_sz, reply_post_free_sz; 3295 u32 retry_sz; 3296 u16 max_request_credit; 3297 unsigned short sg_tablesize; 3298 u16 sge_size; 3299 int i; 3300 3301 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3302 __func__)); 3303 3304 3305 retry_sz = 0; 3306 facts = &ioc->facts; 3307 3308 /* command line tunables for max sgl entries */ 3309 if (max_sgl_entries != -1) 3310 sg_tablesize = max_sgl_entries; 3311 else { 3312 if (ioc->hba_mpi_version_belonged == MPI2_VERSION) 3313 sg_tablesize = MPT2SAS_SG_DEPTH; 3314 else 3315 sg_tablesize = MPT3SAS_SG_DEPTH; 3316 } 3317 3318 if (sg_tablesize < MPT_MIN_PHYS_SEGMENTS) 3319 sg_tablesize = MPT_MIN_PHYS_SEGMENTS; 3320 else if (sg_tablesize > MPT_MAX_PHYS_SEGMENTS) { 3321 sg_tablesize = min_t(unsigned short, sg_tablesize, 3322 SG_MAX_SEGMENTS); 3323 pr_warn(MPT3SAS_FMT 3324 "sg_tablesize(%u) is bigger than kernel" 3325 " defined SG_CHUNK_SIZE(%u)\n", ioc->name, 3326 sg_tablesize, MPT_MAX_PHYS_SEGMENTS); 3327 } 3328 ioc->shost->sg_tablesize = sg_tablesize; 3329 3330 ioc->internal_depth = min_t(int, (facts->HighPriorityCredit + (5)), 3331 (facts->RequestCredit / 4)); 3332 if (ioc->internal_depth < INTERNAL_CMDS_COUNT) { 3333 if (facts->RequestCredit <= (INTERNAL_CMDS_COUNT + 3334 INTERNAL_SCSIIO_CMDS_COUNT)) { 3335 pr_err(MPT3SAS_FMT "IOC doesn't have enough Request \ 3336 Credits, it has just %d number of credits\n", 3337 ioc->name, facts->RequestCredit); 3338 return -ENOMEM; 3339 } 3340 ioc->internal_depth = 10; 3341 } 3342 3343 ioc->hi_priority_depth = ioc->internal_depth - (5); 3344 /* command line tunables for max controller queue depth */ 3345 if (max_queue_depth != -1 && max_queue_depth != 0) { 3346 max_request_credit = min_t(u16, max_queue_depth + 3347 ioc->internal_depth, facts->RequestCredit); 3348 if (max_request_credit > MAX_HBA_QUEUE_DEPTH) 3349 max_request_credit = MAX_HBA_QUEUE_DEPTH; 3350 } else 3351 max_request_credit = min_t(u16, facts->RequestCredit, 3352 MAX_HBA_QUEUE_DEPTH); 3353 3354 /* Firmware maintains additional facts->HighPriorityCredit number of 3355 * credits for HiPriprity Request messages, so hba queue depth will be 3356 * sum of max_request_credit and high priority queue depth. 3357 */ 3358 ioc->hba_queue_depth = max_request_credit + ioc->hi_priority_depth; 3359 3360 /* request frame size */ 3361 ioc->request_sz = facts->IOCRequestFrameSize * 4; 3362 3363 /* reply frame size */ 3364 ioc->reply_sz = facts->ReplyFrameSize * 4; 3365 3366 /* chain segment size */ 3367 if (ioc->hba_mpi_version_belonged != MPI2_VERSION) { 3368 if (facts->IOCMaxChainSegmentSize) 3369 ioc->chain_segment_sz = 3370 facts->IOCMaxChainSegmentSize * 3371 MAX_CHAIN_ELEMT_SZ; 3372 else 3373 /* set to 128 bytes size if IOCMaxChainSegmentSize is zero */ 3374 ioc->chain_segment_sz = DEFAULT_NUM_FWCHAIN_ELEMTS * 3375 MAX_CHAIN_ELEMT_SZ; 3376 } else 3377 ioc->chain_segment_sz = ioc->request_sz; 3378 3379 /* calculate the max scatter element size */ 3380 sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee); 3381 3382 retry_allocation: 3383 total_sz = 0; 3384 /* calculate number of sg elements left over in the 1st frame */ 3385 max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) - 3386 sizeof(Mpi2SGEIOUnion_t)) + sge_size); 3387 ioc->max_sges_in_main_message = max_sge_elements/sge_size; 3388 3389 /* now do the same for a chain buffer */ 3390 max_sge_elements = ioc->chain_segment_sz - sge_size; 3391 ioc->max_sges_in_chain_message = max_sge_elements/sge_size; 3392 3393 /* 3394 * MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE 3395 */ 3396 chains_needed_per_io = ((ioc->shost->sg_tablesize - 3397 ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message) 3398 + 1; 3399 if (chains_needed_per_io > facts->MaxChainDepth) { 3400 chains_needed_per_io = facts->MaxChainDepth; 3401 ioc->shost->sg_tablesize = min_t(u16, 3402 ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message 3403 * chains_needed_per_io), ioc->shost->sg_tablesize); 3404 } 3405 ioc->chains_needed_per_io = chains_needed_per_io; 3406 3407 /* reply free queue sizing - taking into account for 64 FW events */ 3408 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64; 3409 3410 /* calculate reply descriptor post queue depth */ 3411 ioc->reply_post_queue_depth = ioc->hba_queue_depth + 3412 ioc->reply_free_queue_depth + 1 ; 3413 /* align the reply post queue on the next 16 count boundary */ 3414 if (ioc->reply_post_queue_depth % 16) 3415 ioc->reply_post_queue_depth += 16 - 3416 (ioc->reply_post_queue_depth % 16); 3417 3418 if (ioc->reply_post_queue_depth > 3419 facts->MaxReplyDescriptorPostQueueDepth) { 3420 ioc->reply_post_queue_depth = 3421 facts->MaxReplyDescriptorPostQueueDepth - 3422 (facts->MaxReplyDescriptorPostQueueDepth % 16); 3423 ioc->hba_queue_depth = 3424 ((ioc->reply_post_queue_depth - 64) / 2) - 1; 3425 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64; 3426 } 3427 3428 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scatter gather: " \ 3429 "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), " 3430 "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message, 3431 ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize, 3432 ioc->chains_needed_per_io)); 3433 3434 /* reply post queue, 16 byte align */ 3435 reply_post_free_sz = ioc->reply_post_queue_depth * 3436 sizeof(Mpi2DefaultReplyDescriptor_t); 3437 3438 sz = reply_post_free_sz; 3439 if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable) 3440 sz *= ioc->reply_queue_count; 3441 3442 ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ? 3443 (ioc->reply_queue_count):1, 3444 sizeof(struct reply_post_struct), GFP_KERNEL); 3445 3446 if (!ioc->reply_post) { 3447 pr_err(MPT3SAS_FMT "reply_post_free pool: kcalloc failed\n", 3448 ioc->name); 3449 goto out; 3450 } 3451 ioc->reply_post_free_dma_pool = pci_pool_create("reply_post_free pool", 3452 ioc->pdev, sz, 16, 0); 3453 if (!ioc->reply_post_free_dma_pool) { 3454 pr_err(MPT3SAS_FMT 3455 "reply_post_free pool: pci_pool_create failed\n", 3456 ioc->name); 3457 goto out; 3458 } 3459 i = 0; 3460 do { 3461 ioc->reply_post[i].reply_post_free = 3462 pci_pool_alloc(ioc->reply_post_free_dma_pool, 3463 GFP_KERNEL, 3464 &ioc->reply_post[i].reply_post_free_dma); 3465 if (!ioc->reply_post[i].reply_post_free) { 3466 pr_err(MPT3SAS_FMT 3467 "reply_post_free pool: pci_pool_alloc failed\n", 3468 ioc->name); 3469 goto out; 3470 } 3471 memset(ioc->reply_post[i].reply_post_free, 0, sz); 3472 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3473 "reply post free pool (0x%p): depth(%d)," 3474 "element_size(%d), pool_size(%d kB)\n", ioc->name, 3475 ioc->reply_post[i].reply_post_free, 3476 ioc->reply_post_queue_depth, 8, sz/1024)); 3477 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3478 "reply_post_free_dma = (0x%llx)\n", ioc->name, 3479 (unsigned long long) 3480 ioc->reply_post[i].reply_post_free_dma)); 3481 total_sz += sz; 3482 } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count)); 3483 3484 if (ioc->dma_mask == 64) { 3485 if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) { 3486 pr_warn(MPT3SAS_FMT 3487 "no suitable consistent DMA mask for %s\n", 3488 ioc->name, pci_name(ioc->pdev)); 3489 goto out; 3490 } 3491 } 3492 3493 ioc->scsiio_depth = ioc->hba_queue_depth - 3494 ioc->hi_priority_depth - ioc->internal_depth; 3495 3496 /* set the scsi host can_queue depth 3497 * with some internal commands that could be outstanding 3498 */ 3499 ioc->shost->can_queue = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT; 3500 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3501 "scsi host: can_queue depth (%d)\n", 3502 ioc->name, ioc->shost->can_queue)); 3503 3504 3505 /* contiguous pool for request and chains, 16 byte align, one extra " 3506 * "frame for smid=0 3507 */ 3508 ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth; 3509 sz = ((ioc->scsiio_depth + 1) * ioc->request_sz); 3510 3511 /* hi-priority queue */ 3512 sz += (ioc->hi_priority_depth * ioc->request_sz); 3513 3514 /* internal queue */ 3515 sz += (ioc->internal_depth * ioc->request_sz); 3516 3517 ioc->request_dma_sz = sz; 3518 ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma); 3519 if (!ioc->request) { 3520 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \ 3521 "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), " 3522 "total(%d kB)\n", ioc->name, ioc->hba_queue_depth, 3523 ioc->chains_needed_per_io, ioc->request_sz, sz/1024); 3524 if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH) 3525 goto out; 3526 retry_sz = 64; 3527 ioc->hba_queue_depth -= retry_sz; 3528 _base_release_memory_pools(ioc); 3529 goto retry_allocation; 3530 } 3531 3532 if (retry_sz) 3533 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \ 3534 "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), " 3535 "total(%d kb)\n", ioc->name, ioc->hba_queue_depth, 3536 ioc->chains_needed_per_io, ioc->request_sz, sz/1024); 3537 3538 /* hi-priority queue */ 3539 ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) * 3540 ioc->request_sz); 3541 ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) * 3542 ioc->request_sz); 3543 3544 /* internal queue */ 3545 ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth * 3546 ioc->request_sz); 3547 ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth * 3548 ioc->request_sz); 3549 3550 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3551 "request pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n", 3552 ioc->name, ioc->request, ioc->hba_queue_depth, ioc->request_sz, 3553 (ioc->hba_queue_depth * ioc->request_sz)/1024)); 3554 3555 dinitprintk(ioc, pr_info(MPT3SAS_FMT "request pool: dma(0x%llx)\n", 3556 ioc->name, (unsigned long long) ioc->request_dma)); 3557 total_sz += sz; 3558 3559 sz = ioc->scsiio_depth * sizeof(struct scsiio_tracker); 3560 ioc->scsi_lookup_pages = get_order(sz); 3561 ioc->scsi_lookup = (struct scsiio_tracker *)__get_free_pages( 3562 GFP_KERNEL, ioc->scsi_lookup_pages); 3563 if (!ioc->scsi_lookup) { 3564 pr_err(MPT3SAS_FMT "scsi_lookup: get_free_pages failed, sz(%d)\n", 3565 ioc->name, (int)sz); 3566 goto out; 3567 } 3568 3569 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scsiio(0x%p): depth(%d)\n", 3570 ioc->name, ioc->request, ioc->scsiio_depth)); 3571 3572 ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH); 3573 sz = ioc->chain_depth * sizeof(struct chain_tracker); 3574 ioc->chain_pages = get_order(sz); 3575 ioc->chain_lookup = (struct chain_tracker *)__get_free_pages( 3576 GFP_KERNEL, ioc->chain_pages); 3577 if (!ioc->chain_lookup) { 3578 pr_err(MPT3SAS_FMT "chain_lookup: __get_free_pages failed\n", 3579 ioc->name); 3580 goto out; 3581 } 3582 ioc->chain_dma_pool = pci_pool_create("chain pool", ioc->pdev, 3583 ioc->chain_segment_sz, 16, 0); 3584 if (!ioc->chain_dma_pool) { 3585 pr_err(MPT3SAS_FMT "chain_dma_pool: pci_pool_create failed\n", 3586 ioc->name); 3587 goto out; 3588 } 3589 for (i = 0; i < ioc->chain_depth; i++) { 3590 ioc->chain_lookup[i].chain_buffer = pci_pool_alloc( 3591 ioc->chain_dma_pool , GFP_KERNEL, 3592 &ioc->chain_lookup[i].chain_buffer_dma); 3593 if (!ioc->chain_lookup[i].chain_buffer) { 3594 ioc->chain_depth = i; 3595 goto chain_done; 3596 } 3597 total_sz += ioc->chain_segment_sz; 3598 } 3599 chain_done: 3600 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3601 "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n", 3602 ioc->name, ioc->chain_depth, ioc->chain_segment_sz, 3603 ((ioc->chain_depth * ioc->chain_segment_sz))/1024)); 3604 3605 /* initialize hi-priority queue smid's */ 3606 ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth, 3607 sizeof(struct request_tracker), GFP_KERNEL); 3608 if (!ioc->hpr_lookup) { 3609 pr_err(MPT3SAS_FMT "hpr_lookup: kcalloc failed\n", 3610 ioc->name); 3611 goto out; 3612 } 3613 ioc->hi_priority_smid = ioc->scsiio_depth + 1; 3614 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3615 "hi_priority(0x%p): depth(%d), start smid(%d)\n", 3616 ioc->name, ioc->hi_priority, 3617 ioc->hi_priority_depth, ioc->hi_priority_smid)); 3618 3619 /* initialize internal queue smid's */ 3620 ioc->internal_lookup = kcalloc(ioc->internal_depth, 3621 sizeof(struct request_tracker), GFP_KERNEL); 3622 if (!ioc->internal_lookup) { 3623 pr_err(MPT3SAS_FMT "internal_lookup: kcalloc failed\n", 3624 ioc->name); 3625 goto out; 3626 } 3627 ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth; 3628 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3629 "internal(0x%p): depth(%d), start smid(%d)\n", 3630 ioc->name, ioc->internal, 3631 ioc->internal_depth, ioc->internal_smid)); 3632 3633 /* sense buffers, 4 byte align */ 3634 sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE; 3635 ioc->sense_dma_pool = pci_pool_create("sense pool", ioc->pdev, sz, 4, 3636 0); 3637 if (!ioc->sense_dma_pool) { 3638 pr_err(MPT3SAS_FMT "sense pool: pci_pool_create failed\n", 3639 ioc->name); 3640 goto out; 3641 } 3642 ioc->sense = pci_pool_alloc(ioc->sense_dma_pool , GFP_KERNEL, 3643 &ioc->sense_dma); 3644 if (!ioc->sense) { 3645 pr_err(MPT3SAS_FMT "sense pool: pci_pool_alloc failed\n", 3646 ioc->name); 3647 goto out; 3648 } 3649 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3650 "sense pool(0x%p): depth(%d), element_size(%d), pool_size" 3651 "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth, 3652 SCSI_SENSE_BUFFERSIZE, sz/1024)); 3653 dinitprintk(ioc, pr_info(MPT3SAS_FMT "sense_dma(0x%llx)\n", 3654 ioc->name, (unsigned long long)ioc->sense_dma)); 3655 total_sz += sz; 3656 3657 /* reply pool, 4 byte align */ 3658 sz = ioc->reply_free_queue_depth * ioc->reply_sz; 3659 ioc->reply_dma_pool = pci_pool_create("reply pool", ioc->pdev, sz, 4, 3660 0); 3661 if (!ioc->reply_dma_pool) { 3662 pr_err(MPT3SAS_FMT "reply pool: pci_pool_create failed\n", 3663 ioc->name); 3664 goto out; 3665 } 3666 ioc->reply = pci_pool_alloc(ioc->reply_dma_pool , GFP_KERNEL, 3667 &ioc->reply_dma); 3668 if (!ioc->reply) { 3669 pr_err(MPT3SAS_FMT "reply pool: pci_pool_alloc failed\n", 3670 ioc->name); 3671 goto out; 3672 } 3673 ioc->reply_dma_min_address = (u32)(ioc->reply_dma); 3674 ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz; 3675 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3676 "reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n", 3677 ioc->name, ioc->reply, 3678 ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024)); 3679 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_dma(0x%llx)\n", 3680 ioc->name, (unsigned long long)ioc->reply_dma)); 3681 total_sz += sz; 3682 3683 /* reply free queue, 16 byte align */ 3684 sz = ioc->reply_free_queue_depth * 4; 3685 ioc->reply_free_dma_pool = pci_pool_create("reply_free pool", 3686 ioc->pdev, sz, 16, 0); 3687 if (!ioc->reply_free_dma_pool) { 3688 pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_create failed\n", 3689 ioc->name); 3690 goto out; 3691 } 3692 ioc->reply_free = pci_pool_alloc(ioc->reply_free_dma_pool , GFP_KERNEL, 3693 &ioc->reply_free_dma); 3694 if (!ioc->reply_free) { 3695 pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_alloc failed\n", 3696 ioc->name); 3697 goto out; 3698 } 3699 memset(ioc->reply_free, 0, sz); 3700 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_free pool(0x%p): " \ 3701 "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name, 3702 ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024)); 3703 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3704 "reply_free_dma (0x%llx)\n", 3705 ioc->name, (unsigned long long)ioc->reply_free_dma)); 3706 total_sz += sz; 3707 3708 ioc->config_page_sz = 512; 3709 ioc->config_page = pci_alloc_consistent(ioc->pdev, 3710 ioc->config_page_sz, &ioc->config_page_dma); 3711 if (!ioc->config_page) { 3712 pr_err(MPT3SAS_FMT 3713 "config page: pci_pool_alloc failed\n", 3714 ioc->name); 3715 goto out; 3716 } 3717 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3718 "config page(0x%p): size(%d)\n", 3719 ioc->name, ioc->config_page, ioc->config_page_sz)); 3720 dinitprintk(ioc, pr_info(MPT3SAS_FMT "config_page_dma(0x%llx)\n", 3721 ioc->name, (unsigned long long)ioc->config_page_dma)); 3722 total_sz += ioc->config_page_sz; 3723 3724 pr_info(MPT3SAS_FMT "Allocated physical memory: size(%d kB)\n", 3725 ioc->name, total_sz/1024); 3726 pr_info(MPT3SAS_FMT 3727 "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n", 3728 ioc->name, ioc->shost->can_queue, facts->RequestCredit); 3729 pr_info(MPT3SAS_FMT "Scatter Gather Elements per IO(%d)\n", 3730 ioc->name, ioc->shost->sg_tablesize); 3731 return 0; 3732 3733 out: 3734 return -ENOMEM; 3735 } 3736 3737 /** 3738 * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter. 3739 * @ioc: Pointer to MPT_ADAPTER structure 3740 * @cooked: Request raw or cooked IOC state 3741 * 3742 * Returns all IOC Doorbell register bits if cooked==0, else just the 3743 * Doorbell bits in MPI_IOC_STATE_MASK. 3744 */ 3745 u32 3746 mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked) 3747 { 3748 u32 s, sc; 3749 3750 s = readl(&ioc->chip->Doorbell); 3751 sc = s & MPI2_IOC_STATE_MASK; 3752 return cooked ? sc : s; 3753 } 3754 3755 /** 3756 * _base_wait_on_iocstate - waiting on a particular ioc state 3757 * @ioc_state: controller state { READY, OPERATIONAL, or RESET } 3758 * @timeout: timeout in second 3759 * 3760 * Returns 0 for success, non-zero for failure. 3761 */ 3762 static int 3763 _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout) 3764 { 3765 u32 count, cntdn; 3766 u32 current_state; 3767 3768 count = 0; 3769 cntdn = 1000 * timeout; 3770 do { 3771 current_state = mpt3sas_base_get_iocstate(ioc, 1); 3772 if (current_state == ioc_state) 3773 return 0; 3774 if (count && current_state == MPI2_IOC_STATE_FAULT) 3775 break; 3776 3777 usleep_range(1000, 1500); 3778 count++; 3779 } while (--cntdn); 3780 3781 return current_state; 3782 } 3783 3784 /** 3785 * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by 3786 * a write to the doorbell) 3787 * @ioc: per adapter object 3788 * @timeout: timeout in second 3789 * 3790 * Returns 0 for success, non-zero for failure. 3791 * 3792 * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell. 3793 */ 3794 static int 3795 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc); 3796 3797 static int 3798 _base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout) 3799 { 3800 u32 cntdn, count; 3801 u32 int_status; 3802 3803 count = 0; 3804 cntdn = 1000 * timeout; 3805 do { 3806 int_status = readl(&ioc->chip->HostInterruptStatus); 3807 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { 3808 dhsprintk(ioc, pr_info(MPT3SAS_FMT 3809 "%s: successful count(%d), timeout(%d)\n", 3810 ioc->name, __func__, count, timeout)); 3811 return 0; 3812 } 3813 3814 usleep_range(1000, 1500); 3815 count++; 3816 } while (--cntdn); 3817 3818 pr_err(MPT3SAS_FMT 3819 "%s: failed due to timeout count(%d), int_status(%x)!\n", 3820 ioc->name, __func__, count, int_status); 3821 return -EFAULT; 3822 } 3823 3824 static int 3825 _base_spin_on_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout) 3826 { 3827 u32 cntdn, count; 3828 u32 int_status; 3829 3830 count = 0; 3831 cntdn = 2000 * timeout; 3832 do { 3833 int_status = readl(&ioc->chip->HostInterruptStatus); 3834 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { 3835 dhsprintk(ioc, pr_info(MPT3SAS_FMT 3836 "%s: successful count(%d), timeout(%d)\n", 3837 ioc->name, __func__, count, timeout)); 3838 return 0; 3839 } 3840 3841 udelay(500); 3842 count++; 3843 } while (--cntdn); 3844 3845 pr_err(MPT3SAS_FMT 3846 "%s: failed due to timeout count(%d), int_status(%x)!\n", 3847 ioc->name, __func__, count, int_status); 3848 return -EFAULT; 3849 3850 } 3851 3852 /** 3853 * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell. 3854 * @ioc: per adapter object 3855 * @timeout: timeout in second 3856 * 3857 * Returns 0 for success, non-zero for failure. 3858 * 3859 * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to 3860 * doorbell. 3861 */ 3862 static int 3863 _base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout) 3864 { 3865 u32 cntdn, count; 3866 u32 int_status; 3867 u32 doorbell; 3868 3869 count = 0; 3870 cntdn = 1000 * timeout; 3871 do { 3872 int_status = readl(&ioc->chip->HostInterruptStatus); 3873 if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) { 3874 dhsprintk(ioc, pr_info(MPT3SAS_FMT 3875 "%s: successful count(%d), timeout(%d)\n", 3876 ioc->name, __func__, count, timeout)); 3877 return 0; 3878 } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { 3879 doorbell = readl(&ioc->chip->Doorbell); 3880 if ((doorbell & MPI2_IOC_STATE_MASK) == 3881 MPI2_IOC_STATE_FAULT) { 3882 mpt3sas_base_fault_info(ioc , doorbell); 3883 return -EFAULT; 3884 } 3885 } else if (int_status == 0xFFFFFFFF) 3886 goto out; 3887 3888 usleep_range(1000, 1500); 3889 count++; 3890 } while (--cntdn); 3891 3892 out: 3893 pr_err(MPT3SAS_FMT 3894 "%s: failed due to timeout count(%d), int_status(%x)!\n", 3895 ioc->name, __func__, count, int_status); 3896 return -EFAULT; 3897 } 3898 3899 /** 3900 * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use 3901 * @ioc: per adapter object 3902 * @timeout: timeout in second 3903 * 3904 * Returns 0 for success, non-zero for failure. 3905 * 3906 */ 3907 static int 3908 _base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout) 3909 { 3910 u32 cntdn, count; 3911 u32 doorbell_reg; 3912 3913 count = 0; 3914 cntdn = 1000 * timeout; 3915 do { 3916 doorbell_reg = readl(&ioc->chip->Doorbell); 3917 if (!(doorbell_reg & MPI2_DOORBELL_USED)) { 3918 dhsprintk(ioc, pr_info(MPT3SAS_FMT 3919 "%s: successful count(%d), timeout(%d)\n", 3920 ioc->name, __func__, count, timeout)); 3921 return 0; 3922 } 3923 3924 usleep_range(1000, 1500); 3925 count++; 3926 } while (--cntdn); 3927 3928 pr_err(MPT3SAS_FMT 3929 "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n", 3930 ioc->name, __func__, count, doorbell_reg); 3931 return -EFAULT; 3932 } 3933 3934 /** 3935 * _base_send_ioc_reset - send doorbell reset 3936 * @ioc: per adapter object 3937 * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET 3938 * @timeout: timeout in second 3939 * 3940 * Returns 0 for success, non-zero for failure. 3941 */ 3942 static int 3943 _base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout) 3944 { 3945 u32 ioc_state; 3946 int r = 0; 3947 3948 if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) { 3949 pr_err(MPT3SAS_FMT "%s: unknown reset_type\n", 3950 ioc->name, __func__); 3951 return -EFAULT; 3952 } 3953 3954 if (!(ioc->facts.IOCCapabilities & 3955 MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY)) 3956 return -EFAULT; 3957 3958 pr_info(MPT3SAS_FMT "sending message unit reset !!\n", ioc->name); 3959 3960 writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT, 3961 &ioc->chip->Doorbell); 3962 if ((_base_wait_for_doorbell_ack(ioc, 15))) { 3963 r = -EFAULT; 3964 goto out; 3965 } 3966 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout); 3967 if (ioc_state) { 3968 pr_err(MPT3SAS_FMT 3969 "%s: failed going to ready state (ioc_state=0x%x)\n", 3970 ioc->name, __func__, ioc_state); 3971 r = -EFAULT; 3972 goto out; 3973 } 3974 out: 3975 pr_info(MPT3SAS_FMT "message unit reset: %s\n", 3976 ioc->name, ((r == 0) ? "SUCCESS" : "FAILED")); 3977 return r; 3978 } 3979 3980 /** 3981 * _base_handshake_req_reply_wait - send request thru doorbell interface 3982 * @ioc: per adapter object 3983 * @request_bytes: request length 3984 * @request: pointer having request payload 3985 * @reply_bytes: reply length 3986 * @reply: pointer to reply payload 3987 * @timeout: timeout in second 3988 * 3989 * Returns 0 for success, non-zero for failure. 3990 */ 3991 static int 3992 _base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes, 3993 u32 *request, int reply_bytes, u16 *reply, int timeout) 3994 { 3995 MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply; 3996 int i; 3997 u8 failed; 3998 __le32 *mfp; 3999 4000 /* make sure doorbell is not in use */ 4001 if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) { 4002 pr_err(MPT3SAS_FMT 4003 "doorbell is in use (line=%d)\n", 4004 ioc->name, __LINE__); 4005 return -EFAULT; 4006 } 4007 4008 /* clear pending doorbell interrupts from previous state changes */ 4009 if (readl(&ioc->chip->HostInterruptStatus) & 4010 MPI2_HIS_IOC2SYS_DB_STATUS) 4011 writel(0, &ioc->chip->HostInterruptStatus); 4012 4013 /* send message to ioc */ 4014 writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) | 4015 ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)), 4016 &ioc->chip->Doorbell); 4017 4018 if ((_base_spin_on_doorbell_int(ioc, 5))) { 4019 pr_err(MPT3SAS_FMT 4020 "doorbell handshake int failed (line=%d)\n", 4021 ioc->name, __LINE__); 4022 return -EFAULT; 4023 } 4024 writel(0, &ioc->chip->HostInterruptStatus); 4025 4026 if ((_base_wait_for_doorbell_ack(ioc, 5))) { 4027 pr_err(MPT3SAS_FMT 4028 "doorbell handshake ack failed (line=%d)\n", 4029 ioc->name, __LINE__); 4030 return -EFAULT; 4031 } 4032 4033 /* send message 32-bits at a time */ 4034 for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) { 4035 writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell); 4036 if ((_base_wait_for_doorbell_ack(ioc, 5))) 4037 failed = 1; 4038 } 4039 4040 if (failed) { 4041 pr_err(MPT3SAS_FMT 4042 "doorbell handshake sending request failed (line=%d)\n", 4043 ioc->name, __LINE__); 4044 return -EFAULT; 4045 } 4046 4047 /* now wait for the reply */ 4048 if ((_base_wait_for_doorbell_int(ioc, timeout))) { 4049 pr_err(MPT3SAS_FMT 4050 "doorbell handshake int failed (line=%d)\n", 4051 ioc->name, __LINE__); 4052 return -EFAULT; 4053 } 4054 4055 /* read the first two 16-bits, it gives the total length of the reply */ 4056 reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell) 4057 & MPI2_DOORBELL_DATA_MASK); 4058 writel(0, &ioc->chip->HostInterruptStatus); 4059 if ((_base_wait_for_doorbell_int(ioc, 5))) { 4060 pr_err(MPT3SAS_FMT 4061 "doorbell handshake int failed (line=%d)\n", 4062 ioc->name, __LINE__); 4063 return -EFAULT; 4064 } 4065 reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell) 4066 & MPI2_DOORBELL_DATA_MASK); 4067 writel(0, &ioc->chip->HostInterruptStatus); 4068 4069 for (i = 2; i < default_reply->MsgLength * 2; i++) { 4070 if ((_base_wait_for_doorbell_int(ioc, 5))) { 4071 pr_err(MPT3SAS_FMT 4072 "doorbell handshake int failed (line=%d)\n", 4073 ioc->name, __LINE__); 4074 return -EFAULT; 4075 } 4076 if (i >= reply_bytes/2) /* overflow case */ 4077 readl(&ioc->chip->Doorbell); 4078 else 4079 reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell) 4080 & MPI2_DOORBELL_DATA_MASK); 4081 writel(0, &ioc->chip->HostInterruptStatus); 4082 } 4083 4084 _base_wait_for_doorbell_int(ioc, 5); 4085 if (_base_wait_for_doorbell_not_used(ioc, 5) != 0) { 4086 dhsprintk(ioc, pr_info(MPT3SAS_FMT 4087 "doorbell is in use (line=%d)\n", ioc->name, __LINE__)); 4088 } 4089 writel(0, &ioc->chip->HostInterruptStatus); 4090 4091 if (ioc->logging_level & MPT_DEBUG_INIT) { 4092 mfp = (__le32 *)reply; 4093 pr_info("\toffset:data\n"); 4094 for (i = 0; i < reply_bytes/4; i++) 4095 pr_info("\t[0x%02x]:%08x\n", i*4, 4096 le32_to_cpu(mfp[i])); 4097 } 4098 return 0; 4099 } 4100 4101 /** 4102 * mpt3sas_base_sas_iounit_control - send sas iounit control to FW 4103 * @ioc: per adapter object 4104 * @mpi_reply: the reply payload from FW 4105 * @mpi_request: the request payload sent to FW 4106 * 4107 * The SAS IO Unit Control Request message allows the host to perform low-level 4108 * operations, such as resets on the PHYs of the IO Unit, also allows the host 4109 * to obtain the IOC assigned device handles for a device if it has other 4110 * identifying information about the device, in addition allows the host to 4111 * remove IOC resources associated with the device. 4112 * 4113 * Returns 0 for success, non-zero for failure. 4114 */ 4115 int 4116 mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc, 4117 Mpi2SasIoUnitControlReply_t *mpi_reply, 4118 Mpi2SasIoUnitControlRequest_t *mpi_request) 4119 { 4120 u16 smid; 4121 u32 ioc_state; 4122 bool issue_reset = false; 4123 int rc; 4124 void *request; 4125 u16 wait_state_count; 4126 4127 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 4128 __func__)); 4129 4130 mutex_lock(&ioc->base_cmds.mutex); 4131 4132 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) { 4133 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n", 4134 ioc->name, __func__); 4135 rc = -EAGAIN; 4136 goto out; 4137 } 4138 4139 wait_state_count = 0; 4140 ioc_state = mpt3sas_base_get_iocstate(ioc, 1); 4141 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) { 4142 if (wait_state_count++ == 10) { 4143 pr_err(MPT3SAS_FMT 4144 "%s: failed due to ioc not operational\n", 4145 ioc->name, __func__); 4146 rc = -EFAULT; 4147 goto out; 4148 } 4149 ssleep(1); 4150 ioc_state = mpt3sas_base_get_iocstate(ioc, 1); 4151 pr_info(MPT3SAS_FMT 4152 "%s: waiting for operational state(count=%d)\n", 4153 ioc->name, __func__, wait_state_count); 4154 } 4155 4156 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 4157 if (!smid) { 4158 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", 4159 ioc->name, __func__); 4160 rc = -EAGAIN; 4161 goto out; 4162 } 4163 4164 rc = 0; 4165 ioc->base_cmds.status = MPT3_CMD_PENDING; 4166 request = mpt3sas_base_get_msg_frame(ioc, smid); 4167 ioc->base_cmds.smid = smid; 4168 memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t)); 4169 if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET || 4170 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) 4171 ioc->ioc_link_reset_in_progress = 1; 4172 init_completion(&ioc->base_cmds.done); 4173 ioc->put_smid_default(ioc, smid); 4174 wait_for_completion_timeout(&ioc->base_cmds.done, 4175 msecs_to_jiffies(10000)); 4176 if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET || 4177 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) && 4178 ioc->ioc_link_reset_in_progress) 4179 ioc->ioc_link_reset_in_progress = 0; 4180 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { 4181 pr_err(MPT3SAS_FMT "%s: timeout\n", 4182 ioc->name, __func__); 4183 _debug_dump_mf(mpi_request, 4184 sizeof(Mpi2SasIoUnitControlRequest_t)/4); 4185 if (!(ioc->base_cmds.status & MPT3_CMD_RESET)) 4186 issue_reset = true; 4187 goto issue_host_reset; 4188 } 4189 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) 4190 memcpy(mpi_reply, ioc->base_cmds.reply, 4191 sizeof(Mpi2SasIoUnitControlReply_t)); 4192 else 4193 memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t)); 4194 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 4195 goto out; 4196 4197 issue_host_reset: 4198 if (issue_reset) 4199 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER); 4200 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 4201 rc = -EFAULT; 4202 out: 4203 mutex_unlock(&ioc->base_cmds.mutex); 4204 return rc; 4205 } 4206 4207 /** 4208 * mpt3sas_base_scsi_enclosure_processor - sending request to sep device 4209 * @ioc: per adapter object 4210 * @mpi_reply: the reply payload from FW 4211 * @mpi_request: the request payload sent to FW 4212 * 4213 * The SCSI Enclosure Processor request message causes the IOC to 4214 * communicate with SES devices to control LED status signals. 4215 * 4216 * Returns 0 for success, non-zero for failure. 4217 */ 4218 int 4219 mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc, 4220 Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request) 4221 { 4222 u16 smid; 4223 u32 ioc_state; 4224 bool issue_reset = false; 4225 int rc; 4226 void *request; 4227 u16 wait_state_count; 4228 4229 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 4230 __func__)); 4231 4232 mutex_lock(&ioc->base_cmds.mutex); 4233 4234 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) { 4235 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n", 4236 ioc->name, __func__); 4237 rc = -EAGAIN; 4238 goto out; 4239 } 4240 4241 wait_state_count = 0; 4242 ioc_state = mpt3sas_base_get_iocstate(ioc, 1); 4243 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) { 4244 if (wait_state_count++ == 10) { 4245 pr_err(MPT3SAS_FMT 4246 "%s: failed due to ioc not operational\n", 4247 ioc->name, __func__); 4248 rc = -EFAULT; 4249 goto out; 4250 } 4251 ssleep(1); 4252 ioc_state = mpt3sas_base_get_iocstate(ioc, 1); 4253 pr_info(MPT3SAS_FMT 4254 "%s: waiting for operational state(count=%d)\n", 4255 ioc->name, 4256 __func__, wait_state_count); 4257 } 4258 4259 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 4260 if (!smid) { 4261 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", 4262 ioc->name, __func__); 4263 rc = -EAGAIN; 4264 goto out; 4265 } 4266 4267 rc = 0; 4268 ioc->base_cmds.status = MPT3_CMD_PENDING; 4269 request = mpt3sas_base_get_msg_frame(ioc, smid); 4270 ioc->base_cmds.smid = smid; 4271 memcpy(request, mpi_request, sizeof(Mpi2SepReply_t)); 4272 init_completion(&ioc->base_cmds.done); 4273 ioc->put_smid_default(ioc, smid); 4274 wait_for_completion_timeout(&ioc->base_cmds.done, 4275 msecs_to_jiffies(10000)); 4276 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { 4277 pr_err(MPT3SAS_FMT "%s: timeout\n", 4278 ioc->name, __func__); 4279 _debug_dump_mf(mpi_request, 4280 sizeof(Mpi2SepRequest_t)/4); 4281 if (!(ioc->base_cmds.status & MPT3_CMD_RESET)) 4282 issue_reset = false; 4283 goto issue_host_reset; 4284 } 4285 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) 4286 memcpy(mpi_reply, ioc->base_cmds.reply, 4287 sizeof(Mpi2SepReply_t)); 4288 else 4289 memset(mpi_reply, 0, sizeof(Mpi2SepReply_t)); 4290 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 4291 goto out; 4292 4293 issue_host_reset: 4294 if (issue_reset) 4295 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER); 4296 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 4297 rc = -EFAULT; 4298 out: 4299 mutex_unlock(&ioc->base_cmds.mutex); 4300 return rc; 4301 } 4302 4303 /** 4304 * _base_get_port_facts - obtain port facts reply and save in ioc 4305 * @ioc: per adapter object 4306 * 4307 * Returns 0 for success, non-zero for failure. 4308 */ 4309 static int 4310 _base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port) 4311 { 4312 Mpi2PortFactsRequest_t mpi_request; 4313 Mpi2PortFactsReply_t mpi_reply; 4314 struct mpt3sas_port_facts *pfacts; 4315 int mpi_reply_sz, mpi_request_sz, r; 4316 4317 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 4318 __func__)); 4319 4320 mpi_reply_sz = sizeof(Mpi2PortFactsReply_t); 4321 mpi_request_sz = sizeof(Mpi2PortFactsRequest_t); 4322 memset(&mpi_request, 0, mpi_request_sz); 4323 mpi_request.Function = MPI2_FUNCTION_PORT_FACTS; 4324 mpi_request.PortNumber = port; 4325 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz, 4326 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5); 4327 4328 if (r != 0) { 4329 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n", 4330 ioc->name, __func__, r); 4331 return r; 4332 } 4333 4334 pfacts = &ioc->pfacts[port]; 4335 memset(pfacts, 0, sizeof(struct mpt3sas_port_facts)); 4336 pfacts->PortNumber = mpi_reply.PortNumber; 4337 pfacts->VP_ID = mpi_reply.VP_ID; 4338 pfacts->VF_ID = mpi_reply.VF_ID; 4339 pfacts->MaxPostedCmdBuffers = 4340 le16_to_cpu(mpi_reply.MaxPostedCmdBuffers); 4341 4342 return 0; 4343 } 4344 4345 /** 4346 * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL 4347 * @ioc: per adapter object 4348 * @timeout: 4349 * 4350 * Returns 0 for success, non-zero for failure. 4351 */ 4352 static int 4353 _base_wait_for_iocstate(struct MPT3SAS_ADAPTER *ioc, int timeout) 4354 { 4355 u32 ioc_state; 4356 int rc; 4357 4358 dinitprintk(ioc, printk(MPT3SAS_FMT "%s\n", ioc->name, 4359 __func__)); 4360 4361 if (ioc->pci_error_recovery) { 4362 dfailprintk(ioc, printk(MPT3SAS_FMT 4363 "%s: host in pci error recovery\n", ioc->name, __func__)); 4364 return -EFAULT; 4365 } 4366 4367 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 4368 dhsprintk(ioc, printk(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n", 4369 ioc->name, __func__, ioc_state)); 4370 4371 if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) || 4372 (ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL) 4373 return 0; 4374 4375 if (ioc_state & MPI2_DOORBELL_USED) { 4376 dhsprintk(ioc, printk(MPT3SAS_FMT 4377 "unexpected doorbell active!\n", ioc->name)); 4378 goto issue_diag_reset; 4379 } 4380 4381 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { 4382 mpt3sas_base_fault_info(ioc, ioc_state & 4383 MPI2_DOORBELL_DATA_MASK); 4384 goto issue_diag_reset; 4385 } 4386 4387 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout); 4388 if (ioc_state) { 4389 dfailprintk(ioc, printk(MPT3SAS_FMT 4390 "%s: failed going to ready state (ioc_state=0x%x)\n", 4391 ioc->name, __func__, ioc_state)); 4392 return -EFAULT; 4393 } 4394 4395 issue_diag_reset: 4396 rc = _base_diag_reset(ioc); 4397 return rc; 4398 } 4399 4400 /** 4401 * _base_get_ioc_facts - obtain ioc facts reply and save in ioc 4402 * @ioc: per adapter object 4403 * 4404 * Returns 0 for success, non-zero for failure. 4405 */ 4406 static int 4407 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc) 4408 { 4409 Mpi2IOCFactsRequest_t mpi_request; 4410 Mpi2IOCFactsReply_t mpi_reply; 4411 struct mpt3sas_facts *facts; 4412 int mpi_reply_sz, mpi_request_sz, r; 4413 4414 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 4415 __func__)); 4416 4417 r = _base_wait_for_iocstate(ioc, 10); 4418 if (r) { 4419 dfailprintk(ioc, printk(MPT3SAS_FMT 4420 "%s: failed getting to correct state\n", 4421 ioc->name, __func__)); 4422 return r; 4423 } 4424 mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t); 4425 mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t); 4426 memset(&mpi_request, 0, mpi_request_sz); 4427 mpi_request.Function = MPI2_FUNCTION_IOC_FACTS; 4428 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz, 4429 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5); 4430 4431 if (r != 0) { 4432 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n", 4433 ioc->name, __func__, r); 4434 return r; 4435 } 4436 4437 facts = &ioc->facts; 4438 memset(facts, 0, sizeof(struct mpt3sas_facts)); 4439 facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion); 4440 facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion); 4441 facts->VP_ID = mpi_reply.VP_ID; 4442 facts->VF_ID = mpi_reply.VF_ID; 4443 facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions); 4444 facts->MaxChainDepth = mpi_reply.MaxChainDepth; 4445 facts->WhoInit = mpi_reply.WhoInit; 4446 facts->NumberOfPorts = mpi_reply.NumberOfPorts; 4447 facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors; 4448 facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit); 4449 facts->MaxReplyDescriptorPostQueueDepth = 4450 le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth); 4451 facts->ProductID = le16_to_cpu(mpi_reply.ProductID); 4452 facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities); 4453 if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID)) 4454 ioc->ir_firmware = 1; 4455 if ((facts->IOCCapabilities & 4456 MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE)) 4457 ioc->rdpq_array_capable = 1; 4458 if (facts->IOCCapabilities & MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ) 4459 ioc->atomic_desc_capable = 1; 4460 facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word); 4461 facts->IOCRequestFrameSize = 4462 le16_to_cpu(mpi_reply.IOCRequestFrameSize); 4463 if (ioc->hba_mpi_version_belonged != MPI2_VERSION) { 4464 facts->IOCMaxChainSegmentSize = 4465 le16_to_cpu(mpi_reply.IOCMaxChainSegmentSize); 4466 } 4467 facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators); 4468 facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets); 4469 ioc->shost->max_id = -1; 4470 facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders); 4471 facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures); 4472 facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags); 4473 facts->HighPriorityCredit = 4474 le16_to_cpu(mpi_reply.HighPriorityCredit); 4475 facts->ReplyFrameSize = mpi_reply.ReplyFrameSize; 4476 facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle); 4477 4478 dinitprintk(ioc, pr_info(MPT3SAS_FMT 4479 "hba queue depth(%d), max chains per io(%d)\n", 4480 ioc->name, facts->RequestCredit, 4481 facts->MaxChainDepth)); 4482 dinitprintk(ioc, pr_info(MPT3SAS_FMT 4483 "request frame size(%d), reply frame size(%d)\n", ioc->name, 4484 facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4)); 4485 return 0; 4486 } 4487 4488 /** 4489 * _base_send_ioc_init - send ioc_init to firmware 4490 * @ioc: per adapter object 4491 * 4492 * Returns 0 for success, non-zero for failure. 4493 */ 4494 static int 4495 _base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc) 4496 { 4497 Mpi2IOCInitRequest_t mpi_request; 4498 Mpi2IOCInitReply_t mpi_reply; 4499 int i, r = 0; 4500 ktime_t current_time; 4501 u16 ioc_status; 4502 u32 reply_post_free_array_sz = 0; 4503 Mpi2IOCInitRDPQArrayEntry *reply_post_free_array = NULL; 4504 dma_addr_t reply_post_free_array_dma; 4505 4506 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 4507 __func__)); 4508 4509 memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t)); 4510 mpi_request.Function = MPI2_FUNCTION_IOC_INIT; 4511 mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER; 4512 mpi_request.VF_ID = 0; /* TODO */ 4513 mpi_request.VP_ID = 0; 4514 mpi_request.MsgVersion = cpu_to_le16(ioc->hba_mpi_version_belonged); 4515 mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION); 4516 4517 if (_base_is_controller_msix_enabled(ioc)) 4518 mpi_request.HostMSIxVectors = ioc->reply_queue_count; 4519 mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4); 4520 mpi_request.ReplyDescriptorPostQueueDepth = 4521 cpu_to_le16(ioc->reply_post_queue_depth); 4522 mpi_request.ReplyFreeQueueDepth = 4523 cpu_to_le16(ioc->reply_free_queue_depth); 4524 4525 mpi_request.SenseBufferAddressHigh = 4526 cpu_to_le32((u64)ioc->sense_dma >> 32); 4527 mpi_request.SystemReplyAddressHigh = 4528 cpu_to_le32((u64)ioc->reply_dma >> 32); 4529 mpi_request.SystemRequestFrameBaseAddress = 4530 cpu_to_le64((u64)ioc->request_dma); 4531 mpi_request.ReplyFreeQueueAddress = 4532 cpu_to_le64((u64)ioc->reply_free_dma); 4533 4534 if (ioc->rdpq_array_enable) { 4535 reply_post_free_array_sz = ioc->reply_queue_count * 4536 sizeof(Mpi2IOCInitRDPQArrayEntry); 4537 reply_post_free_array = pci_alloc_consistent(ioc->pdev, 4538 reply_post_free_array_sz, &reply_post_free_array_dma); 4539 if (!reply_post_free_array) { 4540 pr_err(MPT3SAS_FMT 4541 "reply_post_free_array: pci_alloc_consistent failed\n", 4542 ioc->name); 4543 r = -ENOMEM; 4544 goto out; 4545 } 4546 memset(reply_post_free_array, 0, reply_post_free_array_sz); 4547 for (i = 0; i < ioc->reply_queue_count; i++) 4548 reply_post_free_array[i].RDPQBaseAddress = 4549 cpu_to_le64( 4550 (u64)ioc->reply_post[i].reply_post_free_dma); 4551 mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE; 4552 mpi_request.ReplyDescriptorPostQueueAddress = 4553 cpu_to_le64((u64)reply_post_free_array_dma); 4554 } else { 4555 mpi_request.ReplyDescriptorPostQueueAddress = 4556 cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma); 4557 } 4558 4559 /* This time stamp specifies number of milliseconds 4560 * since epoch ~ midnight January 1, 1970. 4561 */ 4562 current_time = ktime_get_real(); 4563 mpi_request.TimeStamp = cpu_to_le64(ktime_to_ms(current_time)); 4564 4565 if (ioc->logging_level & MPT_DEBUG_INIT) { 4566 __le32 *mfp; 4567 int i; 4568 4569 mfp = (__le32 *)&mpi_request; 4570 pr_info("\toffset:data\n"); 4571 for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++) 4572 pr_info("\t[0x%02x]:%08x\n", i*4, 4573 le32_to_cpu(mfp[i])); 4574 } 4575 4576 r = _base_handshake_req_reply_wait(ioc, 4577 sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request, 4578 sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10); 4579 4580 if (r != 0) { 4581 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n", 4582 ioc->name, __func__, r); 4583 goto out; 4584 } 4585 4586 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK; 4587 if (ioc_status != MPI2_IOCSTATUS_SUCCESS || 4588 mpi_reply.IOCLogInfo) { 4589 pr_err(MPT3SAS_FMT "%s: failed\n", ioc->name, __func__); 4590 r = -EIO; 4591 } 4592 4593 out: 4594 if (reply_post_free_array) 4595 pci_free_consistent(ioc->pdev, reply_post_free_array_sz, 4596 reply_post_free_array, 4597 reply_post_free_array_dma); 4598 return r; 4599 } 4600 4601 /** 4602 * mpt3sas_port_enable_done - command completion routine for port enable 4603 * @ioc: per adapter object 4604 * @smid: system request message index 4605 * @msix_index: MSIX table index supplied by the OS 4606 * @reply: reply message frame(lower 32bit addr) 4607 * 4608 * Return 1 meaning mf should be freed from _base_interrupt 4609 * 0 means the mf is freed from this function. 4610 */ 4611 u8 4612 mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, 4613 u32 reply) 4614 { 4615 MPI2DefaultReply_t *mpi_reply; 4616 u16 ioc_status; 4617 4618 if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED) 4619 return 1; 4620 4621 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); 4622 if (!mpi_reply) 4623 return 1; 4624 4625 if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE) 4626 return 1; 4627 4628 ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING; 4629 ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE; 4630 ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID; 4631 memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4); 4632 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK; 4633 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) 4634 ioc->port_enable_failed = 1; 4635 4636 if (ioc->is_driver_loading) { 4637 if (ioc_status == MPI2_IOCSTATUS_SUCCESS) { 4638 mpt3sas_port_enable_complete(ioc); 4639 return 1; 4640 } else { 4641 ioc->start_scan_failed = ioc_status; 4642 ioc->start_scan = 0; 4643 return 1; 4644 } 4645 } 4646 complete(&ioc->port_enable_cmds.done); 4647 return 1; 4648 } 4649 4650 /** 4651 * _base_send_port_enable - send port_enable(discovery stuff) to firmware 4652 * @ioc: per adapter object 4653 * 4654 * Returns 0 for success, non-zero for failure. 4655 */ 4656 static int 4657 _base_send_port_enable(struct MPT3SAS_ADAPTER *ioc) 4658 { 4659 Mpi2PortEnableRequest_t *mpi_request; 4660 Mpi2PortEnableReply_t *mpi_reply; 4661 int r = 0; 4662 u16 smid; 4663 u16 ioc_status; 4664 4665 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name); 4666 4667 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { 4668 pr_err(MPT3SAS_FMT "%s: internal command already in use\n", 4669 ioc->name, __func__); 4670 return -EAGAIN; 4671 } 4672 4673 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx); 4674 if (!smid) { 4675 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", 4676 ioc->name, __func__); 4677 return -EAGAIN; 4678 } 4679 4680 ioc->port_enable_cmds.status = MPT3_CMD_PENDING; 4681 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 4682 ioc->port_enable_cmds.smid = smid; 4683 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t)); 4684 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE; 4685 4686 init_completion(&ioc->port_enable_cmds.done); 4687 ioc->put_smid_default(ioc, smid); 4688 wait_for_completion_timeout(&ioc->port_enable_cmds.done, 300*HZ); 4689 if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) { 4690 pr_err(MPT3SAS_FMT "%s: timeout\n", 4691 ioc->name, __func__); 4692 _debug_dump_mf(mpi_request, 4693 sizeof(Mpi2PortEnableRequest_t)/4); 4694 if (ioc->port_enable_cmds.status & MPT3_CMD_RESET) 4695 r = -EFAULT; 4696 else 4697 r = -ETIME; 4698 goto out; 4699 } 4700 4701 mpi_reply = ioc->port_enable_cmds.reply; 4702 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK; 4703 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 4704 pr_err(MPT3SAS_FMT "%s: failed with (ioc_status=0x%08x)\n", 4705 ioc->name, __func__, ioc_status); 4706 r = -EFAULT; 4707 goto out; 4708 } 4709 4710 out: 4711 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED; 4712 pr_info(MPT3SAS_FMT "port enable: %s\n", ioc->name, ((r == 0) ? 4713 "SUCCESS" : "FAILED")); 4714 return r; 4715 } 4716 4717 /** 4718 * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply) 4719 * @ioc: per adapter object 4720 * 4721 * Returns 0 for success, non-zero for failure. 4722 */ 4723 int 4724 mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc) 4725 { 4726 Mpi2PortEnableRequest_t *mpi_request; 4727 u16 smid; 4728 4729 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name); 4730 4731 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { 4732 pr_err(MPT3SAS_FMT "%s: internal command already in use\n", 4733 ioc->name, __func__); 4734 return -EAGAIN; 4735 } 4736 4737 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx); 4738 if (!smid) { 4739 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", 4740 ioc->name, __func__); 4741 return -EAGAIN; 4742 } 4743 4744 ioc->port_enable_cmds.status = MPT3_CMD_PENDING; 4745 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 4746 ioc->port_enable_cmds.smid = smid; 4747 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t)); 4748 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE; 4749 4750 ioc->put_smid_default(ioc, smid); 4751 return 0; 4752 } 4753 4754 /** 4755 * _base_determine_wait_on_discovery - desposition 4756 * @ioc: per adapter object 4757 * 4758 * Decide whether to wait on discovery to complete. Used to either 4759 * locate boot device, or report volumes ahead of physical devices. 4760 * 4761 * Returns 1 for wait, 0 for don't wait 4762 */ 4763 static int 4764 _base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc) 4765 { 4766 /* We wait for discovery to complete if IR firmware is loaded. 4767 * The sas topology events arrive before PD events, so we need time to 4768 * turn on the bit in ioc->pd_handles to indicate PD 4769 * Also, it maybe required to report Volumes ahead of physical 4770 * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set. 4771 */ 4772 if (ioc->ir_firmware) 4773 return 1; 4774 4775 /* if no Bios, then we don't need to wait */ 4776 if (!ioc->bios_pg3.BiosVersion) 4777 return 0; 4778 4779 /* Bios is present, then we drop down here. 4780 * 4781 * If there any entries in the Bios Page 2, then we wait 4782 * for discovery to complete. 4783 */ 4784 4785 /* Current Boot Device */ 4786 if ((ioc->bios_pg2.CurrentBootDeviceForm & 4787 MPI2_BIOSPAGE2_FORM_MASK) == 4788 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED && 4789 /* Request Boot Device */ 4790 (ioc->bios_pg2.ReqBootDeviceForm & 4791 MPI2_BIOSPAGE2_FORM_MASK) == 4792 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED && 4793 /* Alternate Request Boot Device */ 4794 (ioc->bios_pg2.ReqAltBootDeviceForm & 4795 MPI2_BIOSPAGE2_FORM_MASK) == 4796 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED) 4797 return 0; 4798 4799 return 1; 4800 } 4801 4802 /** 4803 * _base_unmask_events - turn on notification for this event 4804 * @ioc: per adapter object 4805 * @event: firmware event 4806 * 4807 * The mask is stored in ioc->event_masks. 4808 */ 4809 static void 4810 _base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event) 4811 { 4812 u32 desired_event; 4813 4814 if (event >= 128) 4815 return; 4816 4817 desired_event = (1 << (event % 32)); 4818 4819 if (event < 32) 4820 ioc->event_masks[0] &= ~desired_event; 4821 else if (event < 64) 4822 ioc->event_masks[1] &= ~desired_event; 4823 else if (event < 96) 4824 ioc->event_masks[2] &= ~desired_event; 4825 else if (event < 128) 4826 ioc->event_masks[3] &= ~desired_event; 4827 } 4828 4829 /** 4830 * _base_event_notification - send event notification 4831 * @ioc: per adapter object 4832 * 4833 * Returns 0 for success, non-zero for failure. 4834 */ 4835 static int 4836 _base_event_notification(struct MPT3SAS_ADAPTER *ioc) 4837 { 4838 Mpi2EventNotificationRequest_t *mpi_request; 4839 u16 smid; 4840 int r = 0; 4841 int i; 4842 4843 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 4844 __func__)); 4845 4846 if (ioc->base_cmds.status & MPT3_CMD_PENDING) { 4847 pr_err(MPT3SAS_FMT "%s: internal command already in use\n", 4848 ioc->name, __func__); 4849 return -EAGAIN; 4850 } 4851 4852 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 4853 if (!smid) { 4854 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", 4855 ioc->name, __func__); 4856 return -EAGAIN; 4857 } 4858 ioc->base_cmds.status = MPT3_CMD_PENDING; 4859 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 4860 ioc->base_cmds.smid = smid; 4861 memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t)); 4862 mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION; 4863 mpi_request->VF_ID = 0; /* TODO */ 4864 mpi_request->VP_ID = 0; 4865 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 4866 mpi_request->EventMasks[i] = 4867 cpu_to_le32(ioc->event_masks[i]); 4868 init_completion(&ioc->base_cmds.done); 4869 ioc->put_smid_default(ioc, smid); 4870 wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ); 4871 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { 4872 pr_err(MPT3SAS_FMT "%s: timeout\n", 4873 ioc->name, __func__); 4874 _debug_dump_mf(mpi_request, 4875 sizeof(Mpi2EventNotificationRequest_t)/4); 4876 if (ioc->base_cmds.status & MPT3_CMD_RESET) 4877 r = -EFAULT; 4878 else 4879 r = -ETIME; 4880 } else 4881 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s: complete\n", 4882 ioc->name, __func__)); 4883 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 4884 return r; 4885 } 4886 4887 /** 4888 * mpt3sas_base_validate_event_type - validating event types 4889 * @ioc: per adapter object 4890 * @event: firmware event 4891 * 4892 * This will turn on firmware event notification when application 4893 * ask for that event. We don't mask events that are already enabled. 4894 */ 4895 void 4896 mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type) 4897 { 4898 int i, j; 4899 u32 event_mask, desired_event; 4900 u8 send_update_to_fw; 4901 4902 for (i = 0, send_update_to_fw = 0; i < 4903 MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) { 4904 event_mask = ~event_type[i]; 4905 desired_event = 1; 4906 for (j = 0; j < 32; j++) { 4907 if (!(event_mask & desired_event) && 4908 (ioc->event_masks[i] & desired_event)) { 4909 ioc->event_masks[i] &= ~desired_event; 4910 send_update_to_fw = 1; 4911 } 4912 desired_event = (desired_event << 1); 4913 } 4914 } 4915 4916 if (!send_update_to_fw) 4917 return; 4918 4919 mutex_lock(&ioc->base_cmds.mutex); 4920 _base_event_notification(ioc); 4921 mutex_unlock(&ioc->base_cmds.mutex); 4922 } 4923 4924 /** 4925 * _base_diag_reset - the "big hammer" start of day reset 4926 * @ioc: per adapter object 4927 * 4928 * Returns 0 for success, non-zero for failure. 4929 */ 4930 static int 4931 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc) 4932 { 4933 u32 host_diagnostic; 4934 u32 ioc_state; 4935 u32 count; 4936 u32 hcb_size; 4937 4938 pr_info(MPT3SAS_FMT "sending diag reset !!\n", ioc->name); 4939 4940 drsprintk(ioc, pr_info(MPT3SAS_FMT "clear interrupts\n", 4941 ioc->name)); 4942 4943 count = 0; 4944 do { 4945 /* Write magic sequence to WriteSequence register 4946 * Loop until in diagnostic mode 4947 */ 4948 drsprintk(ioc, pr_info(MPT3SAS_FMT 4949 "write magic sequence\n", ioc->name)); 4950 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence); 4951 writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence); 4952 writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence); 4953 writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence); 4954 writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence); 4955 writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence); 4956 writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence); 4957 4958 /* wait 100 msec */ 4959 msleep(100); 4960 4961 if (count++ > 20) 4962 goto out; 4963 4964 host_diagnostic = readl(&ioc->chip->HostDiagnostic); 4965 drsprintk(ioc, pr_info(MPT3SAS_FMT 4966 "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n", 4967 ioc->name, count, host_diagnostic)); 4968 4969 } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0); 4970 4971 hcb_size = readl(&ioc->chip->HCBSize); 4972 4973 drsprintk(ioc, pr_info(MPT3SAS_FMT "diag reset: issued\n", 4974 ioc->name)); 4975 writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER, 4976 &ioc->chip->HostDiagnostic); 4977 4978 /*This delay allows the chip PCIe hardware time to finish reset tasks*/ 4979 msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000); 4980 4981 /* Approximately 300 second max wait */ 4982 for (count = 0; count < (300000000 / 4983 MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) { 4984 4985 host_diagnostic = readl(&ioc->chip->HostDiagnostic); 4986 4987 if (host_diagnostic == 0xFFFFFFFF) 4988 goto out; 4989 if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER)) 4990 break; 4991 4992 msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC / 1000); 4993 } 4994 4995 if (host_diagnostic & MPI2_DIAG_HCB_MODE) { 4996 4997 drsprintk(ioc, pr_info(MPT3SAS_FMT 4998 "restart the adapter assuming the HCB Address points to good F/W\n", 4999 ioc->name)); 5000 host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK; 5001 host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW; 5002 writel(host_diagnostic, &ioc->chip->HostDiagnostic); 5003 5004 drsprintk(ioc, pr_info(MPT3SAS_FMT 5005 "re-enable the HCDW\n", ioc->name)); 5006 writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE, 5007 &ioc->chip->HCBSize); 5008 } 5009 5010 drsprintk(ioc, pr_info(MPT3SAS_FMT "restart the adapter\n", 5011 ioc->name)); 5012 writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET, 5013 &ioc->chip->HostDiagnostic); 5014 5015 drsprintk(ioc, pr_info(MPT3SAS_FMT 5016 "disable writes to the diagnostic register\n", ioc->name)); 5017 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence); 5018 5019 drsprintk(ioc, pr_info(MPT3SAS_FMT 5020 "Wait for FW to go to the READY state\n", ioc->name)); 5021 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20); 5022 if (ioc_state) { 5023 pr_err(MPT3SAS_FMT 5024 "%s: failed going to ready state (ioc_state=0x%x)\n", 5025 ioc->name, __func__, ioc_state); 5026 goto out; 5027 } 5028 5029 pr_info(MPT3SAS_FMT "diag reset: SUCCESS\n", ioc->name); 5030 return 0; 5031 5032 out: 5033 pr_err(MPT3SAS_FMT "diag reset: FAILED\n", ioc->name); 5034 return -EFAULT; 5035 } 5036 5037 /** 5038 * _base_make_ioc_ready - put controller in READY state 5039 * @ioc: per adapter object 5040 * @type: FORCE_BIG_HAMMER or SOFT_RESET 5041 * 5042 * Returns 0 for success, non-zero for failure. 5043 */ 5044 static int 5045 _base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, enum reset_type type) 5046 { 5047 u32 ioc_state; 5048 int rc; 5049 int count; 5050 5051 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 5052 __func__)); 5053 5054 if (ioc->pci_error_recovery) 5055 return 0; 5056 5057 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 5058 dhsprintk(ioc, pr_info(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n", 5059 ioc->name, __func__, ioc_state)); 5060 5061 /* if in RESET state, it should move to READY state shortly */ 5062 count = 0; 5063 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) { 5064 while ((ioc_state & MPI2_IOC_STATE_MASK) != 5065 MPI2_IOC_STATE_READY) { 5066 if (count++ == 10) { 5067 pr_err(MPT3SAS_FMT 5068 "%s: failed going to ready state (ioc_state=0x%x)\n", 5069 ioc->name, __func__, ioc_state); 5070 return -EFAULT; 5071 } 5072 ssleep(1); 5073 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 5074 } 5075 } 5076 5077 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) 5078 return 0; 5079 5080 if (ioc_state & MPI2_DOORBELL_USED) { 5081 dhsprintk(ioc, pr_info(MPT3SAS_FMT 5082 "unexpected doorbell active!\n", 5083 ioc->name)); 5084 goto issue_diag_reset; 5085 } 5086 5087 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { 5088 mpt3sas_base_fault_info(ioc, ioc_state & 5089 MPI2_DOORBELL_DATA_MASK); 5090 goto issue_diag_reset; 5091 } 5092 5093 if (type == FORCE_BIG_HAMMER) 5094 goto issue_diag_reset; 5095 5096 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL) 5097 if (!(_base_send_ioc_reset(ioc, 5098 MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15))) { 5099 return 0; 5100 } 5101 5102 issue_diag_reset: 5103 rc = _base_diag_reset(ioc); 5104 return rc; 5105 } 5106 5107 /** 5108 * _base_make_ioc_operational - put controller in OPERATIONAL state 5109 * @ioc: per adapter object 5110 * 5111 * Returns 0 for success, non-zero for failure. 5112 */ 5113 static int 5114 _base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc) 5115 { 5116 int r, i, index; 5117 unsigned long flags; 5118 u32 reply_address; 5119 u16 smid; 5120 struct _tr_list *delayed_tr, *delayed_tr_next; 5121 struct _sc_list *delayed_sc, *delayed_sc_next; 5122 struct _event_ack_list *delayed_event_ack, *delayed_event_ack_next; 5123 u8 hide_flag; 5124 struct adapter_reply_queue *reply_q; 5125 Mpi2ReplyDescriptorsUnion_t *reply_post_free_contig; 5126 5127 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 5128 __func__)); 5129 5130 /* clean the delayed target reset list */ 5131 list_for_each_entry_safe(delayed_tr, delayed_tr_next, 5132 &ioc->delayed_tr_list, list) { 5133 list_del(&delayed_tr->list); 5134 kfree(delayed_tr); 5135 } 5136 5137 5138 list_for_each_entry_safe(delayed_tr, delayed_tr_next, 5139 &ioc->delayed_tr_volume_list, list) { 5140 list_del(&delayed_tr->list); 5141 kfree(delayed_tr); 5142 } 5143 5144 list_for_each_entry_safe(delayed_sc, delayed_sc_next, 5145 &ioc->delayed_sc_list, list) { 5146 list_del(&delayed_sc->list); 5147 kfree(delayed_sc); 5148 } 5149 5150 list_for_each_entry_safe(delayed_event_ack, delayed_event_ack_next, 5151 &ioc->delayed_event_ack_list, list) { 5152 list_del(&delayed_event_ack->list); 5153 kfree(delayed_event_ack); 5154 } 5155 5156 /* initialize the scsi lookup free list */ 5157 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 5158 INIT_LIST_HEAD(&ioc->free_list); 5159 smid = 1; 5160 for (i = 0; i < ioc->scsiio_depth; i++, smid++) { 5161 INIT_LIST_HEAD(&ioc->scsi_lookup[i].chain_list); 5162 ioc->scsi_lookup[i].cb_idx = 0xFF; 5163 ioc->scsi_lookup[i].smid = smid; 5164 ioc->scsi_lookup[i].scmd = NULL; 5165 ioc->scsi_lookup[i].direct_io = 0; 5166 list_add_tail(&ioc->scsi_lookup[i].tracker_list, 5167 &ioc->free_list); 5168 } 5169 5170 /* hi-priority queue */ 5171 INIT_LIST_HEAD(&ioc->hpr_free_list); 5172 smid = ioc->hi_priority_smid; 5173 for (i = 0; i < ioc->hi_priority_depth; i++, smid++) { 5174 ioc->hpr_lookup[i].cb_idx = 0xFF; 5175 ioc->hpr_lookup[i].smid = smid; 5176 list_add_tail(&ioc->hpr_lookup[i].tracker_list, 5177 &ioc->hpr_free_list); 5178 } 5179 5180 /* internal queue */ 5181 INIT_LIST_HEAD(&ioc->internal_free_list); 5182 smid = ioc->internal_smid; 5183 for (i = 0; i < ioc->internal_depth; i++, smid++) { 5184 ioc->internal_lookup[i].cb_idx = 0xFF; 5185 ioc->internal_lookup[i].smid = smid; 5186 list_add_tail(&ioc->internal_lookup[i].tracker_list, 5187 &ioc->internal_free_list); 5188 } 5189 5190 /* chain pool */ 5191 INIT_LIST_HEAD(&ioc->free_chain_list); 5192 for (i = 0; i < ioc->chain_depth; i++) 5193 list_add_tail(&ioc->chain_lookup[i].tracker_list, 5194 &ioc->free_chain_list); 5195 5196 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 5197 5198 /* initialize Reply Free Queue */ 5199 for (i = 0, reply_address = (u32)ioc->reply_dma ; 5200 i < ioc->reply_free_queue_depth ; i++, reply_address += 5201 ioc->reply_sz) 5202 ioc->reply_free[i] = cpu_to_le32(reply_address); 5203 5204 /* initialize reply queues */ 5205 if (ioc->is_driver_loading) 5206 _base_assign_reply_queues(ioc); 5207 5208 /* initialize Reply Post Free Queue */ 5209 index = 0; 5210 reply_post_free_contig = ioc->reply_post[0].reply_post_free; 5211 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 5212 /* 5213 * If RDPQ is enabled, switch to the next allocation. 5214 * Otherwise advance within the contiguous region. 5215 */ 5216 if (ioc->rdpq_array_enable) { 5217 reply_q->reply_post_free = 5218 ioc->reply_post[index++].reply_post_free; 5219 } else { 5220 reply_q->reply_post_free = reply_post_free_contig; 5221 reply_post_free_contig += ioc->reply_post_queue_depth; 5222 } 5223 5224 reply_q->reply_post_host_index = 0; 5225 for (i = 0; i < ioc->reply_post_queue_depth; i++) 5226 reply_q->reply_post_free[i].Words = 5227 cpu_to_le64(ULLONG_MAX); 5228 if (!_base_is_controller_msix_enabled(ioc)) 5229 goto skip_init_reply_post_free_queue; 5230 } 5231 skip_init_reply_post_free_queue: 5232 5233 r = _base_send_ioc_init(ioc); 5234 if (r) 5235 return r; 5236 5237 /* initialize reply free host index */ 5238 ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1; 5239 writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex); 5240 5241 /* initialize reply post host index */ 5242 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 5243 if (ioc->combined_reply_queue) 5244 writel((reply_q->msix_index & 7)<< 5245 MPI2_RPHI_MSIX_INDEX_SHIFT, 5246 ioc->replyPostRegisterIndex[reply_q->msix_index/8]); 5247 else 5248 writel(reply_q->msix_index << 5249 MPI2_RPHI_MSIX_INDEX_SHIFT, 5250 &ioc->chip->ReplyPostHostIndex); 5251 5252 if (!_base_is_controller_msix_enabled(ioc)) 5253 goto skip_init_reply_post_host_index; 5254 } 5255 5256 skip_init_reply_post_host_index: 5257 5258 _base_unmask_interrupts(ioc); 5259 r = _base_event_notification(ioc); 5260 if (r) 5261 return r; 5262 5263 _base_static_config_pages(ioc); 5264 5265 if (ioc->is_driver_loading) { 5266 5267 if (ioc->is_warpdrive && ioc->manu_pg10.OEMIdentifier 5268 == 0x80) { 5269 hide_flag = (u8) ( 5270 le32_to_cpu(ioc->manu_pg10.OEMSpecificFlags0) & 5271 MFG_PAGE10_HIDE_SSDS_MASK); 5272 if (hide_flag != MFG_PAGE10_HIDE_SSDS_MASK) 5273 ioc->mfg_pg10_hide_flag = hide_flag; 5274 } 5275 5276 ioc->wait_for_discovery_to_complete = 5277 _base_determine_wait_on_discovery(ioc); 5278 5279 return r; /* scan_start and scan_finished support */ 5280 } 5281 5282 r = _base_send_port_enable(ioc); 5283 if (r) 5284 return r; 5285 5286 return r; 5287 } 5288 5289 /** 5290 * mpt3sas_base_free_resources - free resources controller resources 5291 * @ioc: per adapter object 5292 * 5293 * Return nothing. 5294 */ 5295 void 5296 mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc) 5297 { 5298 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 5299 __func__)); 5300 5301 /* synchronizing freeing resource with pci_access_mutex lock */ 5302 mutex_lock(&ioc->pci_access_mutex); 5303 if (ioc->chip_phys && ioc->chip) { 5304 _base_mask_interrupts(ioc); 5305 ioc->shost_recovery = 1; 5306 _base_make_ioc_ready(ioc, SOFT_RESET); 5307 ioc->shost_recovery = 0; 5308 } 5309 5310 mpt3sas_base_unmap_resources(ioc); 5311 mutex_unlock(&ioc->pci_access_mutex); 5312 return; 5313 } 5314 5315 /** 5316 * mpt3sas_base_attach - attach controller instance 5317 * @ioc: per adapter object 5318 * 5319 * Returns 0 for success, non-zero for failure. 5320 */ 5321 int 5322 mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc) 5323 { 5324 int r, i; 5325 int cpu_id, last_cpu_id = 0; 5326 5327 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 5328 __func__)); 5329 5330 /* setup cpu_msix_table */ 5331 ioc->cpu_count = num_online_cpus(); 5332 for_each_online_cpu(cpu_id) 5333 last_cpu_id = cpu_id; 5334 ioc->cpu_msix_table_sz = last_cpu_id + 1; 5335 ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL); 5336 ioc->reply_queue_count = 1; 5337 if (!ioc->cpu_msix_table) { 5338 dfailprintk(ioc, pr_info(MPT3SAS_FMT 5339 "allocation for cpu_msix_table failed!!!\n", 5340 ioc->name)); 5341 r = -ENOMEM; 5342 goto out_free_resources; 5343 } 5344 5345 if (ioc->is_warpdrive) { 5346 ioc->reply_post_host_index = kcalloc(ioc->cpu_msix_table_sz, 5347 sizeof(resource_size_t *), GFP_KERNEL); 5348 if (!ioc->reply_post_host_index) { 5349 dfailprintk(ioc, pr_info(MPT3SAS_FMT "allocation " 5350 "for reply_post_host_index failed!!!\n", 5351 ioc->name)); 5352 r = -ENOMEM; 5353 goto out_free_resources; 5354 } 5355 } 5356 5357 ioc->rdpq_array_enable_assigned = 0; 5358 ioc->dma_mask = 0; 5359 r = mpt3sas_base_map_resources(ioc); 5360 if (r) 5361 goto out_free_resources; 5362 5363 pci_set_drvdata(ioc->pdev, ioc->shost); 5364 r = _base_get_ioc_facts(ioc); 5365 if (r) 5366 goto out_free_resources; 5367 5368 switch (ioc->hba_mpi_version_belonged) { 5369 case MPI2_VERSION: 5370 ioc->build_sg_scmd = &_base_build_sg_scmd; 5371 ioc->build_sg = &_base_build_sg; 5372 ioc->build_zero_len_sge = &_base_build_zero_len_sge; 5373 break; 5374 case MPI25_VERSION: 5375 case MPI26_VERSION: 5376 /* 5377 * In SAS3.0, 5378 * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and 5379 * Target Status - all require the IEEE formated scatter gather 5380 * elements. 5381 */ 5382 ioc->build_sg_scmd = &_base_build_sg_scmd_ieee; 5383 ioc->build_sg = &_base_build_sg_ieee; 5384 ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee; 5385 ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t); 5386 5387 break; 5388 } 5389 5390 if (ioc->atomic_desc_capable) { 5391 ioc->put_smid_default = &_base_put_smid_default_atomic; 5392 ioc->put_smid_scsi_io = &_base_put_smid_scsi_io_atomic; 5393 ioc->put_smid_fast_path = &_base_put_smid_fast_path_atomic; 5394 ioc->put_smid_hi_priority = &_base_put_smid_hi_priority_atomic; 5395 } else { 5396 ioc->put_smid_default = &_base_put_smid_default; 5397 ioc->put_smid_scsi_io = &_base_put_smid_scsi_io; 5398 ioc->put_smid_fast_path = &_base_put_smid_fast_path; 5399 ioc->put_smid_hi_priority = &_base_put_smid_hi_priority; 5400 } 5401 5402 5403 /* 5404 * These function pointers for other requests that don't 5405 * the require IEEE scatter gather elements. 5406 * 5407 * For example Configuration Pages and SAS IOUNIT Control don't. 5408 */ 5409 ioc->build_sg_mpi = &_base_build_sg; 5410 ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge; 5411 5412 r = _base_make_ioc_ready(ioc, SOFT_RESET); 5413 if (r) 5414 goto out_free_resources; 5415 5416 ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts, 5417 sizeof(struct mpt3sas_port_facts), GFP_KERNEL); 5418 if (!ioc->pfacts) { 5419 r = -ENOMEM; 5420 goto out_free_resources; 5421 } 5422 5423 for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) { 5424 r = _base_get_port_facts(ioc, i); 5425 if (r) 5426 goto out_free_resources; 5427 } 5428 5429 r = _base_allocate_memory_pools(ioc); 5430 if (r) 5431 goto out_free_resources; 5432 5433 init_waitqueue_head(&ioc->reset_wq); 5434 5435 /* allocate memory pd handle bitmask list */ 5436 ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8); 5437 if (ioc->facts.MaxDevHandle % 8) 5438 ioc->pd_handles_sz++; 5439 ioc->pd_handles = kzalloc(ioc->pd_handles_sz, 5440 GFP_KERNEL); 5441 if (!ioc->pd_handles) { 5442 r = -ENOMEM; 5443 goto out_free_resources; 5444 } 5445 ioc->blocking_handles = kzalloc(ioc->pd_handles_sz, 5446 GFP_KERNEL); 5447 if (!ioc->blocking_handles) { 5448 r = -ENOMEM; 5449 goto out_free_resources; 5450 } 5451 5452 /* allocate memory for pending OS device add list */ 5453 ioc->pend_os_device_add_sz = (ioc->facts.MaxDevHandle / 8); 5454 if (ioc->facts.MaxDevHandle % 8) 5455 ioc->pend_os_device_add_sz++; 5456 ioc->pend_os_device_add = kzalloc(ioc->pend_os_device_add_sz, 5457 GFP_KERNEL); 5458 if (!ioc->pend_os_device_add) 5459 goto out_free_resources; 5460 5461 ioc->device_remove_in_progress_sz = ioc->pend_os_device_add_sz; 5462 ioc->device_remove_in_progress = 5463 kzalloc(ioc->device_remove_in_progress_sz, GFP_KERNEL); 5464 if (!ioc->device_remove_in_progress) 5465 goto out_free_resources; 5466 5467 ioc->fwfault_debug = mpt3sas_fwfault_debug; 5468 5469 /* base internal command bits */ 5470 mutex_init(&ioc->base_cmds.mutex); 5471 ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 5472 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 5473 5474 /* port_enable command bits */ 5475 ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 5476 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED; 5477 5478 /* transport internal command bits */ 5479 ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 5480 ioc->transport_cmds.status = MPT3_CMD_NOT_USED; 5481 mutex_init(&ioc->transport_cmds.mutex); 5482 5483 /* scsih internal command bits */ 5484 ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 5485 ioc->scsih_cmds.status = MPT3_CMD_NOT_USED; 5486 mutex_init(&ioc->scsih_cmds.mutex); 5487 5488 /* task management internal command bits */ 5489 ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 5490 ioc->tm_cmds.status = MPT3_CMD_NOT_USED; 5491 mutex_init(&ioc->tm_cmds.mutex); 5492 5493 /* config page internal command bits */ 5494 ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 5495 ioc->config_cmds.status = MPT3_CMD_NOT_USED; 5496 mutex_init(&ioc->config_cmds.mutex); 5497 5498 /* ctl module internal command bits */ 5499 ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 5500 ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL); 5501 ioc->ctl_cmds.status = MPT3_CMD_NOT_USED; 5502 mutex_init(&ioc->ctl_cmds.mutex); 5503 5504 if (!ioc->base_cmds.reply || !ioc->transport_cmds.reply || 5505 !ioc->scsih_cmds.reply || !ioc->tm_cmds.reply || 5506 !ioc->config_cmds.reply || !ioc->ctl_cmds.reply || 5507 !ioc->ctl_cmds.sense) { 5508 r = -ENOMEM; 5509 goto out_free_resources; 5510 } 5511 5512 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 5513 ioc->event_masks[i] = -1; 5514 5515 /* here we enable the events we care about */ 5516 _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY); 5517 _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE); 5518 _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST); 5519 _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE); 5520 _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE); 5521 _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST); 5522 _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME); 5523 _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK); 5524 _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS); 5525 _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED); 5526 _base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD); 5527 if (ioc->hba_mpi_version_belonged == MPI26_VERSION) 5528 _base_unmask_events(ioc, MPI2_EVENT_ACTIVE_CABLE_EXCEPTION); 5529 5530 r = _base_make_ioc_operational(ioc); 5531 if (r) 5532 goto out_free_resources; 5533 5534 ioc->non_operational_loop = 0; 5535 ioc->got_task_abort_from_ioctl = 0; 5536 return 0; 5537 5538 out_free_resources: 5539 5540 ioc->remove_host = 1; 5541 5542 mpt3sas_base_free_resources(ioc); 5543 _base_release_memory_pools(ioc); 5544 pci_set_drvdata(ioc->pdev, NULL); 5545 kfree(ioc->cpu_msix_table); 5546 if (ioc->is_warpdrive) 5547 kfree(ioc->reply_post_host_index); 5548 kfree(ioc->pd_handles); 5549 kfree(ioc->blocking_handles); 5550 kfree(ioc->device_remove_in_progress); 5551 kfree(ioc->pend_os_device_add); 5552 kfree(ioc->tm_cmds.reply); 5553 kfree(ioc->transport_cmds.reply); 5554 kfree(ioc->scsih_cmds.reply); 5555 kfree(ioc->config_cmds.reply); 5556 kfree(ioc->base_cmds.reply); 5557 kfree(ioc->port_enable_cmds.reply); 5558 kfree(ioc->ctl_cmds.reply); 5559 kfree(ioc->ctl_cmds.sense); 5560 kfree(ioc->pfacts); 5561 ioc->ctl_cmds.reply = NULL; 5562 ioc->base_cmds.reply = NULL; 5563 ioc->tm_cmds.reply = NULL; 5564 ioc->scsih_cmds.reply = NULL; 5565 ioc->transport_cmds.reply = NULL; 5566 ioc->config_cmds.reply = NULL; 5567 ioc->pfacts = NULL; 5568 return r; 5569 } 5570 5571 5572 /** 5573 * mpt3sas_base_detach - remove controller instance 5574 * @ioc: per adapter object 5575 * 5576 * Return nothing. 5577 */ 5578 void 5579 mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc) 5580 { 5581 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 5582 __func__)); 5583 5584 mpt3sas_base_stop_watchdog(ioc); 5585 mpt3sas_base_free_resources(ioc); 5586 _base_release_memory_pools(ioc); 5587 pci_set_drvdata(ioc->pdev, NULL); 5588 kfree(ioc->cpu_msix_table); 5589 if (ioc->is_warpdrive) 5590 kfree(ioc->reply_post_host_index); 5591 kfree(ioc->pd_handles); 5592 kfree(ioc->blocking_handles); 5593 kfree(ioc->device_remove_in_progress); 5594 kfree(ioc->pend_os_device_add); 5595 kfree(ioc->pfacts); 5596 kfree(ioc->ctl_cmds.reply); 5597 kfree(ioc->ctl_cmds.sense); 5598 kfree(ioc->base_cmds.reply); 5599 kfree(ioc->port_enable_cmds.reply); 5600 kfree(ioc->tm_cmds.reply); 5601 kfree(ioc->transport_cmds.reply); 5602 kfree(ioc->scsih_cmds.reply); 5603 kfree(ioc->config_cmds.reply); 5604 } 5605 5606 /** 5607 * _base_reset_handler - reset callback handler (for base) 5608 * @ioc: per adapter object 5609 * @reset_phase: phase 5610 * 5611 * The handler for doing any required cleanup or initialization. 5612 * 5613 * The reset phase can be MPT3_IOC_PRE_RESET, MPT3_IOC_AFTER_RESET, 5614 * MPT3_IOC_DONE_RESET 5615 * 5616 * Return nothing. 5617 */ 5618 static void 5619 _base_reset_handler(struct MPT3SAS_ADAPTER *ioc, int reset_phase) 5620 { 5621 mpt3sas_scsih_reset_handler(ioc, reset_phase); 5622 mpt3sas_ctl_reset_handler(ioc, reset_phase); 5623 switch (reset_phase) { 5624 case MPT3_IOC_PRE_RESET: 5625 dtmprintk(ioc, pr_info(MPT3SAS_FMT 5626 "%s: MPT3_IOC_PRE_RESET\n", ioc->name, __func__)); 5627 break; 5628 case MPT3_IOC_AFTER_RESET: 5629 dtmprintk(ioc, pr_info(MPT3SAS_FMT 5630 "%s: MPT3_IOC_AFTER_RESET\n", ioc->name, __func__)); 5631 if (ioc->transport_cmds.status & MPT3_CMD_PENDING) { 5632 ioc->transport_cmds.status |= MPT3_CMD_RESET; 5633 mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid); 5634 complete(&ioc->transport_cmds.done); 5635 } 5636 if (ioc->base_cmds.status & MPT3_CMD_PENDING) { 5637 ioc->base_cmds.status |= MPT3_CMD_RESET; 5638 mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid); 5639 complete(&ioc->base_cmds.done); 5640 } 5641 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { 5642 ioc->port_enable_failed = 1; 5643 ioc->port_enable_cmds.status |= MPT3_CMD_RESET; 5644 mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid); 5645 if (ioc->is_driver_loading) { 5646 ioc->start_scan_failed = 5647 MPI2_IOCSTATUS_INTERNAL_ERROR; 5648 ioc->start_scan = 0; 5649 ioc->port_enable_cmds.status = 5650 MPT3_CMD_NOT_USED; 5651 } else 5652 complete(&ioc->port_enable_cmds.done); 5653 } 5654 if (ioc->config_cmds.status & MPT3_CMD_PENDING) { 5655 ioc->config_cmds.status |= MPT3_CMD_RESET; 5656 mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid); 5657 ioc->config_cmds.smid = USHRT_MAX; 5658 complete(&ioc->config_cmds.done); 5659 } 5660 break; 5661 case MPT3_IOC_DONE_RESET: 5662 dtmprintk(ioc, pr_info(MPT3SAS_FMT 5663 "%s: MPT3_IOC_DONE_RESET\n", ioc->name, __func__)); 5664 break; 5665 } 5666 } 5667 5668 /** 5669 * _wait_for_commands_to_complete - reset controller 5670 * @ioc: Pointer to MPT_ADAPTER structure 5671 * 5672 * This function waiting(3s) for all pending commands to complete 5673 * prior to putting controller in reset. 5674 */ 5675 static void 5676 _wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc) 5677 { 5678 u32 ioc_state; 5679 unsigned long flags; 5680 u16 i; 5681 5682 ioc->pending_io_count = 0; 5683 5684 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 5685 if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) 5686 return; 5687 5688 /* pending command count */ 5689 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 5690 for (i = 0; i < ioc->scsiio_depth; i++) 5691 if (ioc->scsi_lookup[i].cb_idx != 0xFF) 5692 ioc->pending_io_count++; 5693 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 5694 5695 if (!ioc->pending_io_count) 5696 return; 5697 5698 /* wait for pending commands to complete */ 5699 wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ); 5700 } 5701 5702 /** 5703 * mpt3sas_base_hard_reset_handler - reset controller 5704 * @ioc: Pointer to MPT_ADAPTER structure 5705 * @type: FORCE_BIG_HAMMER or SOFT_RESET 5706 * 5707 * Returns 0 for success, non-zero for failure. 5708 */ 5709 int 5710 mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc, 5711 enum reset_type type) 5712 { 5713 int r; 5714 unsigned long flags; 5715 u32 ioc_state; 5716 u8 is_fault = 0, is_trigger = 0; 5717 5718 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: enter\n", ioc->name, 5719 __func__)); 5720 5721 if (ioc->pci_error_recovery) { 5722 pr_err(MPT3SAS_FMT "%s: pci error recovery reset\n", 5723 ioc->name, __func__); 5724 r = 0; 5725 goto out_unlocked; 5726 } 5727 5728 if (mpt3sas_fwfault_debug) 5729 mpt3sas_halt_firmware(ioc); 5730 5731 /* wait for an active reset in progress to complete */ 5732 if (!mutex_trylock(&ioc->reset_in_progress_mutex)) { 5733 do { 5734 ssleep(1); 5735 } while (ioc->shost_recovery == 1); 5736 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name, 5737 __func__)); 5738 return ioc->ioc_reset_in_progress_status; 5739 } 5740 5741 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 5742 ioc->shost_recovery = 1; 5743 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 5744 5745 if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] & 5746 MPT3_DIAG_BUFFER_IS_REGISTERED) && 5747 (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] & 5748 MPT3_DIAG_BUFFER_IS_RELEASED))) { 5749 is_trigger = 1; 5750 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 5751 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) 5752 is_fault = 1; 5753 } 5754 _base_reset_handler(ioc, MPT3_IOC_PRE_RESET); 5755 _wait_for_commands_to_complete(ioc); 5756 _base_mask_interrupts(ioc); 5757 r = _base_make_ioc_ready(ioc, type); 5758 if (r) 5759 goto out; 5760 _base_reset_handler(ioc, MPT3_IOC_AFTER_RESET); 5761 5762 /* If this hard reset is called while port enable is active, then 5763 * there is no reason to call make_ioc_operational 5764 */ 5765 if (ioc->is_driver_loading && ioc->port_enable_failed) { 5766 ioc->remove_host = 1; 5767 r = -EFAULT; 5768 goto out; 5769 } 5770 r = _base_get_ioc_facts(ioc); 5771 if (r) 5772 goto out; 5773 5774 if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable) 5775 panic("%s: Issue occurred with flashing controller firmware." 5776 "Please reboot the system and ensure that the correct" 5777 " firmware version is running\n", ioc->name); 5778 5779 r = _base_make_ioc_operational(ioc); 5780 if (!r) 5781 _base_reset_handler(ioc, MPT3_IOC_DONE_RESET); 5782 5783 out: 5784 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: %s\n", 5785 ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED"))); 5786 5787 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 5788 ioc->ioc_reset_in_progress_status = r; 5789 ioc->shost_recovery = 0; 5790 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 5791 ioc->ioc_reset_count++; 5792 mutex_unlock(&ioc->reset_in_progress_mutex); 5793 5794 out_unlocked: 5795 if ((r == 0) && is_trigger) { 5796 if (is_fault) 5797 mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT); 5798 else 5799 mpt3sas_trigger_master(ioc, 5800 MASTER_TRIGGER_ADAPTER_RESET); 5801 } 5802 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name, 5803 __func__)); 5804 return r; 5805 } 5806