1 /*
2  * This is the Fusion MPT base driver providing common API layer interface
3  * for access to MPT (Message Passing Technology) firmware.
4  *
5  * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c
6  * Copyright (C) 2012-2014  LSI Corporation
7  * Copyright (C) 2013-2014 Avago Technologies
8  *  (mailto: MPT-FusionLinux.pdl@avagotech.com)
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License
12  * as published by the Free Software Foundation; either version 2
13  * of the License, or (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * NO WARRANTY
21  * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
22  * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
23  * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
24  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
25  * solely responsible for determining the appropriateness of using and
26  * distributing the Program and assumes all risks associated with its
27  * exercise of rights under this Agreement, including but not limited to
28  * the risks and costs of program errors, damage to or loss of data,
29  * programs or equipment, and unavailability or interruption of operations.
30 
31  * DISCLAIMER OF LIABILITY
32  * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
33  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34  * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
35  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
36  * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
37  * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
38  * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
39 
40  * You should have received a copy of the GNU General Public License
41  * along with this program; if not, write to the Free Software
42  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301,
43  * USA.
44  */
45 
46 #include <linux/kernel.h>
47 #include <linux/module.h>
48 #include <linux/errno.h>
49 #include <linux/init.h>
50 #include <linux/slab.h>
51 #include <linux/types.h>
52 #include <linux/pci.h>
53 #include <linux/kdev_t.h>
54 #include <linux/blkdev.h>
55 #include <linux/delay.h>
56 #include <linux/interrupt.h>
57 #include <linux/dma-mapping.h>
58 #include <linux/io.h>
59 #include <linux/time.h>
60 #include <linux/ktime.h>
61 #include <linux/kthread.h>
62 #include <linux/aer.h>
63 
64 
65 #include "mpt3sas_base.h"
66 
67 static MPT_CALLBACK	mpt_callbacks[MPT_MAX_CALLBACKS];
68 
69 
70 #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */
71 
72  /* maximum controller queue depth */
73 #define MAX_HBA_QUEUE_DEPTH	30000
74 #define MAX_CHAIN_DEPTH		100000
75 static int max_queue_depth = -1;
76 module_param(max_queue_depth, int, 0);
77 MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
78 
79 static int max_sgl_entries = -1;
80 module_param(max_sgl_entries, int, 0);
81 MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
82 
83 static int msix_disable = -1;
84 module_param(msix_disable, int, 0);
85 MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
86 
87 static int smp_affinity_enable = 1;
88 module_param(smp_affinity_enable, int, S_IRUGO);
89 MODULE_PARM_DESC(smp_affinity_enable, "SMP affinity feature enable/disbale Default: enable(1)");
90 
91 static int max_msix_vectors = -1;
92 module_param(max_msix_vectors, int, 0);
93 MODULE_PARM_DESC(max_msix_vectors,
94 	" max msix vectors");
95 
96 static int mpt3sas_fwfault_debug;
97 MODULE_PARM_DESC(mpt3sas_fwfault_debug,
98 	" enable detection of firmware fault and halt firmware - (default=0)");
99 
100 static int
101 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc, int sleep_flag);
102 
103 /**
104  * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug.
105  *
106  */
107 static int
108 _scsih_set_fwfault_debug(const char *val, struct kernel_param *kp)
109 {
110 	int ret = param_set_int(val, kp);
111 	struct MPT3SAS_ADAPTER *ioc;
112 
113 	if (ret)
114 		return ret;
115 
116 	/* global ioc spinlock to protect controller list on list operations */
117 	pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug);
118 	spin_lock(&gioc_lock);
119 	list_for_each_entry(ioc, &mpt3sas_ioc_list, list)
120 		ioc->fwfault_debug = mpt3sas_fwfault_debug;
121 	spin_unlock(&gioc_lock);
122 	return 0;
123 }
124 module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug,
125 	param_get_int, &mpt3sas_fwfault_debug, 0644);
126 
127 /**
128  *  mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc
129  * @arg: input argument, used to derive ioc
130  *
131  * Return 0 if controller is removed from pci subsystem.
132  * Return -1 for other case.
133  */
134 static int mpt3sas_remove_dead_ioc_func(void *arg)
135 {
136 	struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg;
137 	struct pci_dev *pdev;
138 
139 	if ((ioc == NULL))
140 		return -1;
141 
142 	pdev = ioc->pdev;
143 	if ((pdev == NULL))
144 		return -1;
145 	pci_stop_and_remove_bus_device_locked(pdev);
146 	return 0;
147 }
148 
149 /**
150  * _base_fault_reset_work - workq handling ioc fault conditions
151  * @work: input argument, used to derive ioc
152  * Context: sleep.
153  *
154  * Return nothing.
155  */
156 static void
157 _base_fault_reset_work(struct work_struct *work)
158 {
159 	struct MPT3SAS_ADAPTER *ioc =
160 	    container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work);
161 	unsigned long	 flags;
162 	u32 doorbell;
163 	int rc;
164 	struct task_struct *p;
165 
166 
167 	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
168 	if (ioc->shost_recovery || ioc->pci_error_recovery)
169 		goto rearm_timer;
170 	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
171 
172 	doorbell = mpt3sas_base_get_iocstate(ioc, 0);
173 	if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) {
174 		pr_err(MPT3SAS_FMT "SAS host is non-operational !!!!\n",
175 		    ioc->name);
176 
177 		/* It may be possible that EEH recovery can resolve some of
178 		 * pci bus failure issues rather removing the dead ioc function
179 		 * by considering controller is in a non-operational state. So
180 		 * here priority is given to the EEH recovery. If it doesn't
181 		 * not resolve this issue, mpt3sas driver will consider this
182 		 * controller to non-operational state and remove the dead ioc
183 		 * function.
184 		 */
185 		if (ioc->non_operational_loop++ < 5) {
186 			spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock,
187 							 flags);
188 			goto rearm_timer;
189 		}
190 
191 		/*
192 		 * Call _scsih_flush_pending_cmds callback so that we flush all
193 		 * pending commands back to OS. This call is required to aovid
194 		 * deadlock at block layer. Dead IOC will fail to do diag reset,
195 		 * and this call is safe since dead ioc will never return any
196 		 * command back from HW.
197 		 */
198 		ioc->schedule_dead_ioc_flush_running_cmds(ioc);
199 		/*
200 		 * Set remove_host flag early since kernel thread will
201 		 * take some time to execute.
202 		 */
203 		ioc->remove_host = 1;
204 		/*Remove the Dead Host */
205 		p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc,
206 		    "%s_dead_ioc_%d", ioc->driver_name, ioc->id);
207 		if (IS_ERR(p))
208 			pr_err(MPT3SAS_FMT
209 			"%s: Running mpt3sas_dead_ioc thread failed !!!!\n",
210 			ioc->name, __func__);
211 		else
212 			pr_err(MPT3SAS_FMT
213 			"%s: Running mpt3sas_dead_ioc thread success !!!!\n",
214 			ioc->name, __func__);
215 		return; /* don't rearm timer */
216 	}
217 
218 	ioc->non_operational_loop = 0;
219 
220 	if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) {
221 		rc = mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
222 		    FORCE_BIG_HAMMER);
223 		pr_warn(MPT3SAS_FMT "%s: hard reset: %s\n", ioc->name,
224 		    __func__, (rc == 0) ? "success" : "failed");
225 		doorbell = mpt3sas_base_get_iocstate(ioc, 0);
226 		if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
227 			mpt3sas_base_fault_info(ioc, doorbell &
228 			    MPI2_DOORBELL_DATA_MASK);
229 		if (rc && (doorbell & MPI2_IOC_STATE_MASK) !=
230 		    MPI2_IOC_STATE_OPERATIONAL)
231 			return; /* don't rearm timer */
232 	}
233 
234 	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
235  rearm_timer:
236 	if (ioc->fault_reset_work_q)
237 		queue_delayed_work(ioc->fault_reset_work_q,
238 		    &ioc->fault_reset_work,
239 		    msecs_to_jiffies(FAULT_POLLING_INTERVAL));
240 	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
241 }
242 
243 /**
244  * mpt3sas_base_start_watchdog - start the fault_reset_work_q
245  * @ioc: per adapter object
246  * Context: sleep.
247  *
248  * Return nothing.
249  */
250 void
251 mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc)
252 {
253 	unsigned long	 flags;
254 
255 	if (ioc->fault_reset_work_q)
256 		return;
257 
258 	/* initialize fault polling */
259 
260 	INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
261 	snprintf(ioc->fault_reset_work_q_name,
262 	    sizeof(ioc->fault_reset_work_q_name), "poll_%s%d_status",
263 	    ioc->driver_name, ioc->id);
264 	ioc->fault_reset_work_q =
265 		create_singlethread_workqueue(ioc->fault_reset_work_q_name);
266 	if (!ioc->fault_reset_work_q) {
267 		pr_err(MPT3SAS_FMT "%s: failed (line=%d)\n",
268 		    ioc->name, __func__, __LINE__);
269 			return;
270 	}
271 	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
272 	if (ioc->fault_reset_work_q)
273 		queue_delayed_work(ioc->fault_reset_work_q,
274 		    &ioc->fault_reset_work,
275 		    msecs_to_jiffies(FAULT_POLLING_INTERVAL));
276 	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
277 }
278 
279 /**
280  * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q
281  * @ioc: per adapter object
282  * Context: sleep.
283  *
284  * Return nothing.
285  */
286 void
287 mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc)
288 {
289 	unsigned long flags;
290 	struct workqueue_struct *wq;
291 
292 	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
293 	wq = ioc->fault_reset_work_q;
294 	ioc->fault_reset_work_q = NULL;
295 	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
296 	if (wq) {
297 		if (!cancel_delayed_work_sync(&ioc->fault_reset_work))
298 			flush_workqueue(wq);
299 		destroy_workqueue(wq);
300 	}
301 }
302 
303 /**
304  * mpt3sas_base_fault_info - verbose translation of firmware FAULT code
305  * @ioc: per adapter object
306  * @fault_code: fault code
307  *
308  * Return nothing.
309  */
310 void
311 mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code)
312 {
313 	pr_err(MPT3SAS_FMT "fault_state(0x%04x)!\n",
314 	    ioc->name, fault_code);
315 }
316 
317 /**
318  * mpt3sas_halt_firmware - halt's mpt controller firmware
319  * @ioc: per adapter object
320  *
321  * For debugging timeout related issues.  Writing 0xCOFFEE00
322  * to the doorbell register will halt controller firmware. With
323  * the purpose to stop both driver and firmware, the enduser can
324  * obtain a ring buffer from controller UART.
325  */
326 void
327 mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc)
328 {
329 	u32 doorbell;
330 
331 	if (!ioc->fwfault_debug)
332 		return;
333 
334 	dump_stack();
335 
336 	doorbell = readl(&ioc->chip->Doorbell);
337 	if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
338 		mpt3sas_base_fault_info(ioc , doorbell);
339 	else {
340 		writel(0xC0FFEE00, &ioc->chip->Doorbell);
341 		pr_err(MPT3SAS_FMT "Firmware is halted due to command timeout\n",
342 			ioc->name);
343 	}
344 
345 	if (ioc->fwfault_debug == 2)
346 		for (;;)
347 			;
348 	else
349 		panic("panic in %s\n", __func__);
350 }
351 
352 /**
353  * _base_sas_ioc_info - verbose translation of the ioc status
354  * @ioc: per adapter object
355  * @mpi_reply: reply mf payload returned from firmware
356  * @request_hdr: request mf
357  *
358  * Return nothing.
359  */
360 static void
361 _base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
362 	MPI2RequestHeader_t *request_hdr)
363 {
364 	u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
365 	    MPI2_IOCSTATUS_MASK;
366 	char *desc = NULL;
367 	u16 frame_sz;
368 	char *func_str = NULL;
369 
370 	/* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */
371 	if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
372 	    request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
373 	    request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
374 		return;
375 
376 	if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE)
377 		return;
378 
379 	switch (ioc_status) {
380 
381 /****************************************************************************
382 *  Common IOCStatus values for all replies
383 ****************************************************************************/
384 
385 	case MPI2_IOCSTATUS_INVALID_FUNCTION:
386 		desc = "invalid function";
387 		break;
388 	case MPI2_IOCSTATUS_BUSY:
389 		desc = "busy";
390 		break;
391 	case MPI2_IOCSTATUS_INVALID_SGL:
392 		desc = "invalid sgl";
393 		break;
394 	case MPI2_IOCSTATUS_INTERNAL_ERROR:
395 		desc = "internal error";
396 		break;
397 	case MPI2_IOCSTATUS_INVALID_VPID:
398 		desc = "invalid vpid";
399 		break;
400 	case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
401 		desc = "insufficient resources";
402 		break;
403 	case MPI2_IOCSTATUS_INSUFFICIENT_POWER:
404 		desc = "insufficient power";
405 		break;
406 	case MPI2_IOCSTATUS_INVALID_FIELD:
407 		desc = "invalid field";
408 		break;
409 	case MPI2_IOCSTATUS_INVALID_STATE:
410 		desc = "invalid state";
411 		break;
412 	case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
413 		desc = "op state not supported";
414 		break;
415 
416 /****************************************************************************
417 *  Config IOCStatus values
418 ****************************************************************************/
419 
420 	case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
421 		desc = "config invalid action";
422 		break;
423 	case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
424 		desc = "config invalid type";
425 		break;
426 	case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
427 		desc = "config invalid page";
428 		break;
429 	case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
430 		desc = "config invalid data";
431 		break;
432 	case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
433 		desc = "config no defaults";
434 		break;
435 	case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
436 		desc = "config cant commit";
437 		break;
438 
439 /****************************************************************************
440 *  SCSI IO Reply
441 ****************************************************************************/
442 
443 	case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
444 	case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
445 	case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
446 	case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
447 	case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
448 	case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
449 	case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
450 	case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
451 	case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
452 	case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
453 	case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
454 	case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
455 		break;
456 
457 /****************************************************************************
458 *  For use by SCSI Initiator and SCSI Target end-to-end data protection
459 ****************************************************************************/
460 
461 	case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
462 		desc = "eedp guard error";
463 		break;
464 	case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
465 		desc = "eedp ref tag error";
466 		break;
467 	case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
468 		desc = "eedp app tag error";
469 		break;
470 
471 /****************************************************************************
472 *  SCSI Target values
473 ****************************************************************************/
474 
475 	case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
476 		desc = "target invalid io index";
477 		break;
478 	case MPI2_IOCSTATUS_TARGET_ABORTED:
479 		desc = "target aborted";
480 		break;
481 	case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
482 		desc = "target no conn retryable";
483 		break;
484 	case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
485 		desc = "target no connection";
486 		break;
487 	case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
488 		desc = "target xfer count mismatch";
489 		break;
490 	case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
491 		desc = "target data offset error";
492 		break;
493 	case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
494 		desc = "target too much write data";
495 		break;
496 	case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
497 		desc = "target iu too short";
498 		break;
499 	case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
500 		desc = "target ack nak timeout";
501 		break;
502 	case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
503 		desc = "target nak received";
504 		break;
505 
506 /****************************************************************************
507 *  Serial Attached SCSI values
508 ****************************************************************************/
509 
510 	case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
511 		desc = "smp request failed";
512 		break;
513 	case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
514 		desc = "smp data overrun";
515 		break;
516 
517 /****************************************************************************
518 *  Diagnostic Buffer Post / Diagnostic Release values
519 ****************************************************************************/
520 
521 	case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
522 		desc = "diagnostic released";
523 		break;
524 	default:
525 		break;
526 	}
527 
528 	if (!desc)
529 		return;
530 
531 	switch (request_hdr->Function) {
532 	case MPI2_FUNCTION_CONFIG:
533 		frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
534 		func_str = "config_page";
535 		break;
536 	case MPI2_FUNCTION_SCSI_TASK_MGMT:
537 		frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
538 		func_str = "task_mgmt";
539 		break;
540 	case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
541 		frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
542 		func_str = "sas_iounit_ctl";
543 		break;
544 	case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
545 		frame_sz = sizeof(Mpi2SepRequest_t);
546 		func_str = "enclosure";
547 		break;
548 	case MPI2_FUNCTION_IOC_INIT:
549 		frame_sz = sizeof(Mpi2IOCInitRequest_t);
550 		func_str = "ioc_init";
551 		break;
552 	case MPI2_FUNCTION_PORT_ENABLE:
553 		frame_sz = sizeof(Mpi2PortEnableRequest_t);
554 		func_str = "port_enable";
555 		break;
556 	case MPI2_FUNCTION_SMP_PASSTHROUGH:
557 		frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
558 		func_str = "smp_passthru";
559 		break;
560 	default:
561 		frame_sz = 32;
562 		func_str = "unknown";
563 		break;
564 	}
565 
566 	pr_warn(MPT3SAS_FMT "ioc_status: %s(0x%04x), request(0x%p),(%s)\n",
567 		ioc->name, desc, ioc_status, request_hdr, func_str);
568 
569 	_debug_dump_mf(request_hdr, frame_sz/4);
570 }
571 
572 /**
573  * _base_display_event_data - verbose translation of firmware asyn events
574  * @ioc: per adapter object
575  * @mpi_reply: reply mf payload returned from firmware
576  *
577  * Return nothing.
578  */
579 static void
580 _base_display_event_data(struct MPT3SAS_ADAPTER *ioc,
581 	Mpi2EventNotificationReply_t *mpi_reply)
582 {
583 	char *desc = NULL;
584 	u16 event;
585 
586 	if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
587 		return;
588 
589 	event = le16_to_cpu(mpi_reply->Event);
590 
591 	switch (event) {
592 	case MPI2_EVENT_LOG_DATA:
593 		desc = "Log Data";
594 		break;
595 	case MPI2_EVENT_STATE_CHANGE:
596 		desc = "Status Change";
597 		break;
598 	case MPI2_EVENT_HARD_RESET_RECEIVED:
599 		desc = "Hard Reset Received";
600 		break;
601 	case MPI2_EVENT_EVENT_CHANGE:
602 		desc = "Event Change";
603 		break;
604 	case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
605 		desc = "Device Status Change";
606 		break;
607 	case MPI2_EVENT_IR_OPERATION_STATUS:
608 		if (!ioc->hide_ir_msg)
609 			desc = "IR Operation Status";
610 		break;
611 	case MPI2_EVENT_SAS_DISCOVERY:
612 	{
613 		Mpi2EventDataSasDiscovery_t *event_data =
614 		    (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
615 		pr_info(MPT3SAS_FMT "Discovery: (%s)", ioc->name,
616 		    (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ?
617 		    "start" : "stop");
618 		if (event_data->DiscoveryStatus)
619 			pr_info("discovery_status(0x%08x)",
620 			    le32_to_cpu(event_data->DiscoveryStatus));
621 			pr_info("\n");
622 		return;
623 	}
624 	case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
625 		desc = "SAS Broadcast Primitive";
626 		break;
627 	case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
628 		desc = "SAS Init Device Status Change";
629 		break;
630 	case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
631 		desc = "SAS Init Table Overflow";
632 		break;
633 	case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
634 		desc = "SAS Topology Change List";
635 		break;
636 	case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
637 		desc = "SAS Enclosure Device Status Change";
638 		break;
639 	case MPI2_EVENT_IR_VOLUME:
640 		if (!ioc->hide_ir_msg)
641 			desc = "IR Volume";
642 		break;
643 	case MPI2_EVENT_IR_PHYSICAL_DISK:
644 		if (!ioc->hide_ir_msg)
645 			desc = "IR Physical Disk";
646 		break;
647 	case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
648 		if (!ioc->hide_ir_msg)
649 			desc = "IR Configuration Change List";
650 		break;
651 	case MPI2_EVENT_LOG_ENTRY_ADDED:
652 		if (!ioc->hide_ir_msg)
653 			desc = "Log Entry Added";
654 		break;
655 	case MPI2_EVENT_TEMP_THRESHOLD:
656 		desc = "Temperature Threshold";
657 		break;
658 	case MPI2_EVENT_ACTIVE_CABLE_EXCEPTION:
659 		desc = "Active cable exception";
660 		break;
661 	}
662 
663 	if (!desc)
664 		return;
665 
666 	pr_info(MPT3SAS_FMT "%s\n", ioc->name, desc);
667 }
668 
669 /**
670  * _base_sas_log_info - verbose translation of firmware log info
671  * @ioc: per adapter object
672  * @log_info: log info
673  *
674  * Return nothing.
675  */
676 static void
677 _base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info)
678 {
679 	union loginfo_type {
680 		u32	loginfo;
681 		struct {
682 			u32	subcode:16;
683 			u32	code:8;
684 			u32	originator:4;
685 			u32	bus_type:4;
686 		} dw;
687 	};
688 	union loginfo_type sas_loginfo;
689 	char *originator_str = NULL;
690 
691 	sas_loginfo.loginfo = log_info;
692 	if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
693 		return;
694 
695 	/* each nexus loss loginfo */
696 	if (log_info == 0x31170000)
697 		return;
698 
699 	/* eat the loginfos associated with task aborts */
700 	if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info ==
701 	    0x31140000 || log_info == 0x31130000))
702 		return;
703 
704 	switch (sas_loginfo.dw.originator) {
705 	case 0:
706 		originator_str = "IOP";
707 		break;
708 	case 1:
709 		originator_str = "PL";
710 		break;
711 	case 2:
712 		if (!ioc->hide_ir_msg)
713 			originator_str = "IR";
714 		else
715 			originator_str = "WarpDrive";
716 		break;
717 	}
718 
719 	pr_warn(MPT3SAS_FMT
720 		"log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n",
721 		ioc->name, log_info,
722 	     originator_str, sas_loginfo.dw.code,
723 	     sas_loginfo.dw.subcode);
724 }
725 
726 /**
727  * _base_display_reply_info -
728  * @ioc: per adapter object
729  * @smid: system request message index
730  * @msix_index: MSIX table index supplied by the OS
731  * @reply: reply message frame(lower 32bit addr)
732  *
733  * Return nothing.
734  */
735 static void
736 _base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
737 	u32 reply)
738 {
739 	MPI2DefaultReply_t *mpi_reply;
740 	u16 ioc_status;
741 	u32 loginfo = 0;
742 
743 	mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
744 	if (unlikely(!mpi_reply)) {
745 		pr_err(MPT3SAS_FMT "mpi_reply not valid at %s:%d/%s()!\n",
746 		    ioc->name, __FILE__, __LINE__, __func__);
747 		return;
748 	}
749 	ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
750 
751 	if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
752 	    (ioc->logging_level & MPT_DEBUG_REPLY)) {
753 		_base_sas_ioc_info(ioc , mpi_reply,
754 		   mpt3sas_base_get_msg_frame(ioc, smid));
755 	}
756 
757 	if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
758 		loginfo = le32_to_cpu(mpi_reply->IOCLogInfo);
759 		_base_sas_log_info(ioc, loginfo);
760 	}
761 
762 	if (ioc_status || loginfo) {
763 		ioc_status &= MPI2_IOCSTATUS_MASK;
764 		mpt3sas_trigger_mpi(ioc, ioc_status, loginfo);
765 	}
766 }
767 
768 /**
769  * mpt3sas_base_done - base internal command completion routine
770  * @ioc: per adapter object
771  * @smid: system request message index
772  * @msix_index: MSIX table index supplied by the OS
773  * @reply: reply message frame(lower 32bit addr)
774  *
775  * Return 1 meaning mf should be freed from _base_interrupt
776  *        0 means the mf is freed from this function.
777  */
778 u8
779 mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
780 	u32 reply)
781 {
782 	MPI2DefaultReply_t *mpi_reply;
783 
784 	mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
785 	if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
786 		return mpt3sas_check_for_pending_internal_cmds(ioc, smid);
787 
788 	if (ioc->base_cmds.status == MPT3_CMD_NOT_USED)
789 		return 1;
790 
791 	ioc->base_cmds.status |= MPT3_CMD_COMPLETE;
792 	if (mpi_reply) {
793 		ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID;
794 		memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
795 	}
796 	ioc->base_cmds.status &= ~MPT3_CMD_PENDING;
797 
798 	complete(&ioc->base_cmds.done);
799 	return 1;
800 }
801 
802 /**
803  * _base_async_event - main callback handler for firmware asyn events
804  * @ioc: per adapter object
805  * @msix_index: MSIX table index supplied by the OS
806  * @reply: reply message frame(lower 32bit addr)
807  *
808  * Return 1 meaning mf should be freed from _base_interrupt
809  *        0 means the mf is freed from this function.
810  */
811 static u8
812 _base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
813 {
814 	Mpi2EventNotificationReply_t *mpi_reply;
815 	Mpi2EventAckRequest_t *ack_request;
816 	u16 smid;
817 	struct _event_ack_list *delayed_event_ack;
818 
819 	mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
820 	if (!mpi_reply)
821 		return 1;
822 	if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
823 		return 1;
824 
825 	_base_display_event_data(ioc, mpi_reply);
826 
827 	if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
828 		goto out;
829 	smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
830 	if (!smid) {
831 		delayed_event_ack = kzalloc(sizeof(*delayed_event_ack),
832 					GFP_ATOMIC);
833 		if (!delayed_event_ack)
834 			goto out;
835 		INIT_LIST_HEAD(&delayed_event_ack->list);
836 		delayed_event_ack->Event = mpi_reply->Event;
837 		delayed_event_ack->EventContext = mpi_reply->EventContext;
838 		list_add_tail(&delayed_event_ack->list,
839 				&ioc->delayed_event_ack_list);
840 		dewtprintk(ioc, pr_info(MPT3SAS_FMT
841 				"DELAYED: EVENT ACK: event (0x%04x)\n",
842 				ioc->name, le16_to_cpu(mpi_reply->Event)));
843 		goto out;
844 	}
845 
846 	ack_request = mpt3sas_base_get_msg_frame(ioc, smid);
847 	memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
848 	ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
849 	ack_request->Event = mpi_reply->Event;
850 	ack_request->EventContext = mpi_reply->EventContext;
851 	ack_request->VF_ID = 0;  /* TODO */
852 	ack_request->VP_ID = 0;
853 	mpt3sas_base_put_smid_default(ioc, smid);
854 
855  out:
856 
857 	/* scsih callback handler */
858 	mpt3sas_scsih_event_callback(ioc, msix_index, reply);
859 
860 	/* ctl callback handler */
861 	mpt3sas_ctl_event_callback(ioc, msix_index, reply);
862 
863 	return 1;
864 }
865 
866 /**
867  * _base_get_cb_idx - obtain the callback index
868  * @ioc: per adapter object
869  * @smid: system request message index
870  *
871  * Return callback index.
872  */
873 static u8
874 _base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid)
875 {
876 	int i;
877 	u8 cb_idx;
878 
879 	if (smid < ioc->hi_priority_smid) {
880 		i = smid - 1;
881 		cb_idx = ioc->scsi_lookup[i].cb_idx;
882 	} else if (smid < ioc->internal_smid) {
883 		i = smid - ioc->hi_priority_smid;
884 		cb_idx = ioc->hpr_lookup[i].cb_idx;
885 	} else if (smid <= ioc->hba_queue_depth) {
886 		i = smid - ioc->internal_smid;
887 		cb_idx = ioc->internal_lookup[i].cb_idx;
888 	} else
889 		cb_idx = 0xFF;
890 	return cb_idx;
891 }
892 
893 /**
894  * _base_mask_interrupts - disable interrupts
895  * @ioc: per adapter object
896  *
897  * Disabling ResetIRQ, Reply and Doorbell Interrupts
898  *
899  * Return nothing.
900  */
901 static void
902 _base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc)
903 {
904 	u32 him_register;
905 
906 	ioc->mask_interrupts = 1;
907 	him_register = readl(&ioc->chip->HostInterruptMask);
908 	him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
909 	writel(him_register, &ioc->chip->HostInterruptMask);
910 	readl(&ioc->chip->HostInterruptMask);
911 }
912 
913 /**
914  * _base_unmask_interrupts - enable interrupts
915  * @ioc: per adapter object
916  *
917  * Enabling only Reply Interrupts
918  *
919  * Return nothing.
920  */
921 static void
922 _base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc)
923 {
924 	u32 him_register;
925 
926 	him_register = readl(&ioc->chip->HostInterruptMask);
927 	him_register &= ~MPI2_HIM_RIM;
928 	writel(him_register, &ioc->chip->HostInterruptMask);
929 	ioc->mask_interrupts = 0;
930 }
931 
932 union reply_descriptor {
933 	u64 word;
934 	struct {
935 		u32 low;
936 		u32 high;
937 	} u;
938 };
939 
940 /**
941  * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
942  * @irq: irq number (not used)
943  * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
944  * @r: pt_regs pointer (not used)
945  *
946  * Return IRQ_HANDLE if processed, else IRQ_NONE.
947  */
948 static irqreturn_t
949 _base_interrupt(int irq, void *bus_id)
950 {
951 	struct adapter_reply_queue *reply_q = bus_id;
952 	union reply_descriptor rd;
953 	u32 completed_cmds;
954 	u8 request_desript_type;
955 	u16 smid;
956 	u8 cb_idx;
957 	u32 reply;
958 	u8 msix_index = reply_q->msix_index;
959 	struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
960 	Mpi2ReplyDescriptorsUnion_t *rpf;
961 	u8 rc;
962 
963 	if (ioc->mask_interrupts)
964 		return IRQ_NONE;
965 
966 	if (!atomic_add_unless(&reply_q->busy, 1, 1))
967 		return IRQ_NONE;
968 
969 	rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index];
970 	request_desript_type = rpf->Default.ReplyFlags
971 	     & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
972 	if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) {
973 		atomic_dec(&reply_q->busy);
974 		return IRQ_NONE;
975 	}
976 
977 	completed_cmds = 0;
978 	cb_idx = 0xFF;
979 	do {
980 		rd.word = le64_to_cpu(rpf->Words);
981 		if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
982 			goto out;
983 		reply = 0;
984 		smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
985 		if (request_desript_type ==
986 		    MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS ||
987 		    request_desript_type ==
988 		    MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) {
989 			cb_idx = _base_get_cb_idx(ioc, smid);
990 			if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
991 			    (likely(mpt_callbacks[cb_idx] != NULL))) {
992 				rc = mpt_callbacks[cb_idx](ioc, smid,
993 				    msix_index, 0);
994 				if (rc)
995 					mpt3sas_base_free_smid(ioc, smid);
996 			}
997 		} else if (request_desript_type ==
998 		    MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
999 			reply = le32_to_cpu(
1000 			    rpf->AddressReply.ReplyFrameAddress);
1001 			if (reply > ioc->reply_dma_max_address ||
1002 			    reply < ioc->reply_dma_min_address)
1003 				reply = 0;
1004 			if (smid) {
1005 				cb_idx = _base_get_cb_idx(ioc, smid);
1006 				if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
1007 				    (likely(mpt_callbacks[cb_idx] != NULL))) {
1008 					rc = mpt_callbacks[cb_idx](ioc, smid,
1009 					    msix_index, reply);
1010 					if (reply)
1011 						_base_display_reply_info(ioc,
1012 						    smid, msix_index, reply);
1013 					if (rc)
1014 						mpt3sas_base_free_smid(ioc,
1015 						    smid);
1016 				}
1017 			} else {
1018 				_base_async_event(ioc, msix_index, reply);
1019 			}
1020 
1021 			/* reply free queue handling */
1022 			if (reply) {
1023 				ioc->reply_free_host_index =
1024 				    (ioc->reply_free_host_index ==
1025 				    (ioc->reply_free_queue_depth - 1)) ?
1026 				    0 : ioc->reply_free_host_index + 1;
1027 				ioc->reply_free[ioc->reply_free_host_index] =
1028 				    cpu_to_le32(reply);
1029 				wmb();
1030 				writel(ioc->reply_free_host_index,
1031 				    &ioc->chip->ReplyFreeHostIndex);
1032 			}
1033 		}
1034 
1035 		rpf->Words = cpu_to_le64(ULLONG_MAX);
1036 		reply_q->reply_post_host_index =
1037 		    (reply_q->reply_post_host_index ==
1038 		    (ioc->reply_post_queue_depth - 1)) ? 0 :
1039 		    reply_q->reply_post_host_index + 1;
1040 		request_desript_type =
1041 		    reply_q->reply_post_free[reply_q->reply_post_host_index].
1042 		    Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1043 		completed_cmds++;
1044 		if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
1045 			goto out;
1046 		if (!reply_q->reply_post_host_index)
1047 			rpf = reply_q->reply_post_free;
1048 		else
1049 			rpf++;
1050 	} while (1);
1051 
1052  out:
1053 
1054 	if (!completed_cmds) {
1055 		atomic_dec(&reply_q->busy);
1056 		return IRQ_NONE;
1057 	}
1058 
1059 	wmb();
1060 	if (ioc->is_warpdrive) {
1061 		writel(reply_q->reply_post_host_index,
1062 		ioc->reply_post_host_index[msix_index]);
1063 		atomic_dec(&reply_q->busy);
1064 		return IRQ_HANDLED;
1065 	}
1066 
1067 	/* Update Reply Post Host Index.
1068 	 * For those HBA's which support combined reply queue feature
1069 	 * 1. Get the correct Supplemental Reply Post Host Index Register.
1070 	 *    i.e. (msix_index / 8)th entry from Supplemental Reply Post Host
1071 	 *    Index Register address bank i.e replyPostRegisterIndex[],
1072 	 * 2. Then update this register with new reply host index value
1073 	 *    in ReplyPostIndex field and the MSIxIndex field with
1074 	 *    msix_index value reduced to a value between 0 and 7,
1075 	 *    using a modulo 8 operation. Since each Supplemental Reply Post
1076 	 *    Host Index Register supports 8 MSI-X vectors.
1077 	 *
1078 	 * For other HBA's just update the Reply Post Host Index register with
1079 	 * new reply host index value in ReplyPostIndex Field and msix_index
1080 	 * value in MSIxIndex field.
1081 	 */
1082 	if (ioc->msix96_vector)
1083 		writel(reply_q->reply_post_host_index | ((msix_index  & 7) <<
1084 			MPI2_RPHI_MSIX_INDEX_SHIFT),
1085 			ioc->replyPostRegisterIndex[msix_index/8]);
1086 	else
1087 		writel(reply_q->reply_post_host_index | (msix_index <<
1088 			MPI2_RPHI_MSIX_INDEX_SHIFT),
1089 			&ioc->chip->ReplyPostHostIndex);
1090 	atomic_dec(&reply_q->busy);
1091 	return IRQ_HANDLED;
1092 }
1093 
1094 /**
1095  * _base_is_controller_msix_enabled - is controller support muli-reply queues
1096  * @ioc: per adapter object
1097  *
1098  */
1099 static inline int
1100 _base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc)
1101 {
1102 	return (ioc->facts.IOCCapabilities &
1103 	    MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable;
1104 }
1105 
1106 /**
1107  * mpt3sas_base_sync_reply_irqs - flush pending MSIX interrupts
1108  * @ioc: per adapter object
1109  * Context: non ISR conext
1110  *
1111  * Called when a Task Management request has completed.
1112  *
1113  * Return nothing.
1114  */
1115 void
1116 mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc)
1117 {
1118 	struct adapter_reply_queue *reply_q;
1119 
1120 	/* If MSIX capability is turned off
1121 	 * then multi-queues are not enabled
1122 	 */
1123 	if (!_base_is_controller_msix_enabled(ioc))
1124 		return;
1125 
1126 	list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1127 		if (ioc->shost_recovery || ioc->remove_host ||
1128 				ioc->pci_error_recovery)
1129 			return;
1130 		/* TMs are on msix_index == 0 */
1131 		if (reply_q->msix_index == 0)
1132 			continue;
1133 		synchronize_irq(reply_q->vector);
1134 	}
1135 }
1136 
1137 /**
1138  * mpt3sas_base_release_callback_handler - clear interrupt callback handler
1139  * @cb_idx: callback index
1140  *
1141  * Return nothing.
1142  */
1143 void
1144 mpt3sas_base_release_callback_handler(u8 cb_idx)
1145 {
1146 	mpt_callbacks[cb_idx] = NULL;
1147 }
1148 
1149 /**
1150  * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler
1151  * @cb_func: callback function
1152  *
1153  * Returns cb_func.
1154  */
1155 u8
1156 mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func)
1157 {
1158 	u8 cb_idx;
1159 
1160 	for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
1161 		if (mpt_callbacks[cb_idx] == NULL)
1162 			break;
1163 
1164 	mpt_callbacks[cb_idx] = cb_func;
1165 	return cb_idx;
1166 }
1167 
1168 /**
1169  * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler
1170  *
1171  * Return nothing.
1172  */
1173 void
1174 mpt3sas_base_initialize_callback_handler(void)
1175 {
1176 	u8 cb_idx;
1177 
1178 	for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
1179 		mpt3sas_base_release_callback_handler(cb_idx);
1180 }
1181 
1182 
1183 /**
1184  * _base_build_zero_len_sge - build zero length sg entry
1185  * @ioc: per adapter object
1186  * @paddr: virtual address for SGE
1187  *
1188  * Create a zero length scatter gather entry to insure the IOCs hardware has
1189  * something to use if the target device goes brain dead and tries
1190  * to send data even when none is asked for.
1191  *
1192  * Return nothing.
1193  */
1194 static void
1195 _base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1196 {
1197 	u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
1198 	    MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
1199 	    MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
1200 	    MPI2_SGE_FLAGS_SHIFT);
1201 	ioc->base_add_sg_single(paddr, flags_length, -1);
1202 }
1203 
1204 /**
1205  * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr.
1206  * @paddr: virtual address for SGE
1207  * @flags_length: SGE flags and data transfer length
1208  * @dma_addr: Physical address
1209  *
1210  * Return nothing.
1211  */
1212 static void
1213 _base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1214 {
1215 	Mpi2SGESimple32_t *sgel = paddr;
1216 
1217 	flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
1218 	    MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1219 	sgel->FlagsLength = cpu_to_le32(flags_length);
1220 	sgel->Address = cpu_to_le32(dma_addr);
1221 }
1222 
1223 
1224 /**
1225  * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr.
1226  * @paddr: virtual address for SGE
1227  * @flags_length: SGE flags and data transfer length
1228  * @dma_addr: Physical address
1229  *
1230  * Return nothing.
1231  */
1232 static void
1233 _base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1234 {
1235 	Mpi2SGESimple64_t *sgel = paddr;
1236 
1237 	flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
1238 	    MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1239 	sgel->FlagsLength = cpu_to_le32(flags_length);
1240 	sgel->Address = cpu_to_le64(dma_addr);
1241 }
1242 
1243 /**
1244  * _base_get_chain_buffer_tracker - obtain chain tracker
1245  * @ioc: per adapter object
1246  * @smid: smid associated to an IO request
1247  *
1248  * Returns chain tracker(from ioc->free_chain_list)
1249  */
1250 static struct chain_tracker *
1251 _base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1252 {
1253 	struct chain_tracker *chain_req;
1254 	unsigned long flags;
1255 
1256 	spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
1257 	if (list_empty(&ioc->free_chain_list)) {
1258 		spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1259 		dfailprintk(ioc, pr_warn(MPT3SAS_FMT
1260 			"chain buffers not available\n", ioc->name));
1261 		return NULL;
1262 	}
1263 	chain_req = list_entry(ioc->free_chain_list.next,
1264 	    struct chain_tracker, tracker_list);
1265 	list_del_init(&chain_req->tracker_list);
1266 	list_add_tail(&chain_req->tracker_list,
1267 	    &ioc->scsi_lookup[smid - 1].chain_list);
1268 	spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1269 	return chain_req;
1270 }
1271 
1272 
1273 /**
1274  * _base_build_sg - build generic sg
1275  * @ioc: per adapter object
1276  * @psge: virtual address for SGE
1277  * @data_out_dma: physical address for WRITES
1278  * @data_out_sz: data xfer size for WRITES
1279  * @data_in_dma: physical address for READS
1280  * @data_in_sz: data xfer size for READS
1281  *
1282  * Return nothing.
1283  */
1284 static void
1285 _base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge,
1286 	dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1287 	size_t data_in_sz)
1288 {
1289 	u32 sgl_flags;
1290 
1291 	if (!data_out_sz && !data_in_sz) {
1292 		_base_build_zero_len_sge(ioc, psge);
1293 		return;
1294 	}
1295 
1296 	if (data_out_sz && data_in_sz) {
1297 		/* WRITE sgel first */
1298 		sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1299 		    MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC);
1300 		sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1301 		ioc->base_add_sg_single(psge, sgl_flags |
1302 		    data_out_sz, data_out_dma);
1303 
1304 		/* incr sgel */
1305 		psge += ioc->sge_size;
1306 
1307 		/* READ sgel last */
1308 		sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1309 		    MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1310 		    MPI2_SGE_FLAGS_END_OF_LIST);
1311 		sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1312 		ioc->base_add_sg_single(psge, sgl_flags |
1313 		    data_in_sz, data_in_dma);
1314 	} else if (data_out_sz) /* WRITE */ {
1315 		sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1316 		    MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1317 		    MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC);
1318 		sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1319 		ioc->base_add_sg_single(psge, sgl_flags |
1320 		    data_out_sz, data_out_dma);
1321 	} else if (data_in_sz) /* READ */ {
1322 		sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1323 		    MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1324 		    MPI2_SGE_FLAGS_END_OF_LIST);
1325 		sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1326 		ioc->base_add_sg_single(psge, sgl_flags |
1327 		    data_in_sz, data_in_dma);
1328 	}
1329 }
1330 
1331 /* IEEE format sgls */
1332 
1333 /**
1334  * _base_add_sg_single_ieee - add sg element for IEEE format
1335  * @paddr: virtual address for SGE
1336  * @flags: SGE flags
1337  * @chain_offset: number of 128 byte elements from start of segment
1338  * @length: data transfer length
1339  * @dma_addr: Physical address
1340  *
1341  * Return nothing.
1342  */
1343 static void
1344 _base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length,
1345 	dma_addr_t dma_addr)
1346 {
1347 	Mpi25IeeeSgeChain64_t *sgel = paddr;
1348 
1349 	sgel->Flags = flags;
1350 	sgel->NextChainOffset = chain_offset;
1351 	sgel->Length = cpu_to_le32(length);
1352 	sgel->Address = cpu_to_le64(dma_addr);
1353 }
1354 
1355 /**
1356  * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format
1357  * @ioc: per adapter object
1358  * @paddr: virtual address for SGE
1359  *
1360  * Create a zero length scatter gather entry to insure the IOCs hardware has
1361  * something to use if the target device goes brain dead and tries
1362  * to send data even when none is asked for.
1363  *
1364  * Return nothing.
1365  */
1366 static void
1367 _base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1368 {
1369 	u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1370 		MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
1371 		MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
1372 
1373 	_base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1);
1374 }
1375 
1376 /**
1377  * _base_build_sg_scmd - main sg creation routine
1378  * @ioc: per adapter object
1379  * @scmd: scsi command
1380  * @smid: system request message index
1381  * Context: none.
1382  *
1383  * The main routine that builds scatter gather table from a given
1384  * scsi request sent via the .queuecommand main handler.
1385  *
1386  * Returns 0 success, anything else error
1387  */
1388 static int
1389 _base_build_sg_scmd(struct MPT3SAS_ADAPTER *ioc,
1390 		struct scsi_cmnd *scmd, u16 smid)
1391 {
1392 	Mpi2SCSIIORequest_t *mpi_request;
1393 	dma_addr_t chain_dma;
1394 	struct scatterlist *sg_scmd;
1395 	void *sg_local, *chain;
1396 	u32 chain_offset;
1397 	u32 chain_length;
1398 	u32 chain_flags;
1399 	int sges_left;
1400 	u32 sges_in_segment;
1401 	u32 sgl_flags;
1402 	u32 sgl_flags_last_element;
1403 	u32 sgl_flags_end_buffer;
1404 	struct chain_tracker *chain_req;
1405 
1406 	mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
1407 
1408 	/* init scatter gather flags */
1409 	sgl_flags = MPI2_SGE_FLAGS_SIMPLE_ELEMENT;
1410 	if (scmd->sc_data_direction == DMA_TO_DEVICE)
1411 		sgl_flags |= MPI2_SGE_FLAGS_HOST_TO_IOC;
1412 	sgl_flags_last_element = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT)
1413 	    << MPI2_SGE_FLAGS_SHIFT;
1414 	sgl_flags_end_buffer = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT |
1415 	    MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST)
1416 	    << MPI2_SGE_FLAGS_SHIFT;
1417 	sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1418 
1419 	sg_scmd = scsi_sglist(scmd);
1420 	sges_left = scsi_dma_map(scmd);
1421 	if (sges_left < 0) {
1422 		sdev_printk(KERN_ERR, scmd->device,
1423 		 "pci_map_sg failed: request for %d bytes!\n",
1424 		 scsi_bufflen(scmd));
1425 		return -ENOMEM;
1426 	}
1427 
1428 	sg_local = &mpi_request->SGL;
1429 	sges_in_segment = ioc->max_sges_in_main_message;
1430 	if (sges_left <= sges_in_segment)
1431 		goto fill_in_last_segment;
1432 
1433 	mpi_request->ChainOffset = (offsetof(Mpi2SCSIIORequest_t, SGL) +
1434 	    (sges_in_segment * ioc->sge_size))/4;
1435 
1436 	/* fill in main message segment when there is a chain following */
1437 	while (sges_in_segment) {
1438 		if (sges_in_segment == 1)
1439 			ioc->base_add_sg_single(sg_local,
1440 			    sgl_flags_last_element | sg_dma_len(sg_scmd),
1441 			    sg_dma_address(sg_scmd));
1442 		else
1443 			ioc->base_add_sg_single(sg_local, sgl_flags |
1444 			    sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1445 		sg_scmd = sg_next(sg_scmd);
1446 		sg_local += ioc->sge_size;
1447 		sges_left--;
1448 		sges_in_segment--;
1449 	}
1450 
1451 	/* initializing the chain flags and pointers */
1452 	chain_flags = MPI2_SGE_FLAGS_CHAIN_ELEMENT << MPI2_SGE_FLAGS_SHIFT;
1453 	chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1454 	if (!chain_req)
1455 		return -1;
1456 	chain = chain_req->chain_buffer;
1457 	chain_dma = chain_req->chain_buffer_dma;
1458 	do {
1459 		sges_in_segment = (sges_left <=
1460 		    ioc->max_sges_in_chain_message) ? sges_left :
1461 		    ioc->max_sges_in_chain_message;
1462 		chain_offset = (sges_left == sges_in_segment) ?
1463 		    0 : (sges_in_segment * ioc->sge_size)/4;
1464 		chain_length = sges_in_segment * ioc->sge_size;
1465 		if (chain_offset) {
1466 			chain_offset = chain_offset <<
1467 			    MPI2_SGE_CHAIN_OFFSET_SHIFT;
1468 			chain_length += ioc->sge_size;
1469 		}
1470 		ioc->base_add_sg_single(sg_local, chain_flags | chain_offset |
1471 		    chain_length, chain_dma);
1472 		sg_local = chain;
1473 		if (!chain_offset)
1474 			goto fill_in_last_segment;
1475 
1476 		/* fill in chain segments */
1477 		while (sges_in_segment) {
1478 			if (sges_in_segment == 1)
1479 				ioc->base_add_sg_single(sg_local,
1480 				    sgl_flags_last_element |
1481 				    sg_dma_len(sg_scmd),
1482 				    sg_dma_address(sg_scmd));
1483 			else
1484 				ioc->base_add_sg_single(sg_local, sgl_flags |
1485 				    sg_dma_len(sg_scmd),
1486 				    sg_dma_address(sg_scmd));
1487 			sg_scmd = sg_next(sg_scmd);
1488 			sg_local += ioc->sge_size;
1489 			sges_left--;
1490 			sges_in_segment--;
1491 		}
1492 
1493 		chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1494 		if (!chain_req)
1495 			return -1;
1496 		chain = chain_req->chain_buffer;
1497 		chain_dma = chain_req->chain_buffer_dma;
1498 	} while (1);
1499 
1500 
1501  fill_in_last_segment:
1502 
1503 	/* fill the last segment */
1504 	while (sges_left) {
1505 		if (sges_left == 1)
1506 			ioc->base_add_sg_single(sg_local, sgl_flags_end_buffer |
1507 			    sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1508 		else
1509 			ioc->base_add_sg_single(sg_local, sgl_flags |
1510 			    sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1511 		sg_scmd = sg_next(sg_scmd);
1512 		sg_local += ioc->sge_size;
1513 		sges_left--;
1514 	}
1515 
1516 	return 0;
1517 }
1518 
1519 /**
1520  * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format
1521  * @ioc: per adapter object
1522  * @scmd: scsi command
1523  * @smid: system request message index
1524  * Context: none.
1525  *
1526  * The main routine that builds scatter gather table from a given
1527  * scsi request sent via the .queuecommand main handler.
1528  *
1529  * Returns 0 success, anything else error
1530  */
1531 static int
1532 _base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc,
1533 	struct scsi_cmnd *scmd, u16 smid)
1534 {
1535 	Mpi2SCSIIORequest_t *mpi_request;
1536 	dma_addr_t chain_dma;
1537 	struct scatterlist *sg_scmd;
1538 	void *sg_local, *chain;
1539 	u32 chain_offset;
1540 	u32 chain_length;
1541 	int sges_left;
1542 	u32 sges_in_segment;
1543 	u8 simple_sgl_flags;
1544 	u8 simple_sgl_flags_last;
1545 	u8 chain_sgl_flags;
1546 	struct chain_tracker *chain_req;
1547 
1548 	mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
1549 
1550 	/* init scatter gather flags */
1551 	simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1552 	    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1553 	simple_sgl_flags_last = simple_sgl_flags |
1554 	    MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
1555 	chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
1556 	    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1557 
1558 	sg_scmd = scsi_sglist(scmd);
1559 	sges_left = scsi_dma_map(scmd);
1560 	if (sges_left < 0) {
1561 		sdev_printk(KERN_ERR, scmd->device,
1562 			"pci_map_sg failed: request for %d bytes!\n",
1563 			scsi_bufflen(scmd));
1564 		return -ENOMEM;
1565 	}
1566 
1567 	sg_local = &mpi_request->SGL;
1568 	sges_in_segment = (ioc->request_sz -
1569 	    offsetof(Mpi2SCSIIORequest_t, SGL))/ioc->sge_size_ieee;
1570 	if (sges_left <= sges_in_segment)
1571 		goto fill_in_last_segment;
1572 
1573 	mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) +
1574 	    (offsetof(Mpi2SCSIIORequest_t, SGL)/ioc->sge_size_ieee);
1575 
1576 	/* fill in main message segment when there is a chain following */
1577 	while (sges_in_segment > 1) {
1578 		_base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1579 		    sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1580 		sg_scmd = sg_next(sg_scmd);
1581 		sg_local += ioc->sge_size_ieee;
1582 		sges_left--;
1583 		sges_in_segment--;
1584 	}
1585 
1586 	/* initializing the pointers */
1587 	chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1588 	if (!chain_req)
1589 		return -1;
1590 	chain = chain_req->chain_buffer;
1591 	chain_dma = chain_req->chain_buffer_dma;
1592 	do {
1593 		sges_in_segment = (sges_left <=
1594 		    ioc->max_sges_in_chain_message) ? sges_left :
1595 		    ioc->max_sges_in_chain_message;
1596 		chain_offset = (sges_left == sges_in_segment) ?
1597 		    0 : sges_in_segment;
1598 		chain_length = sges_in_segment * ioc->sge_size_ieee;
1599 		if (chain_offset)
1600 			chain_length += ioc->sge_size_ieee;
1601 		_base_add_sg_single_ieee(sg_local, chain_sgl_flags,
1602 		    chain_offset, chain_length, chain_dma);
1603 
1604 		sg_local = chain;
1605 		if (!chain_offset)
1606 			goto fill_in_last_segment;
1607 
1608 		/* fill in chain segments */
1609 		while (sges_in_segment) {
1610 			_base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1611 			    sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1612 			sg_scmd = sg_next(sg_scmd);
1613 			sg_local += ioc->sge_size_ieee;
1614 			sges_left--;
1615 			sges_in_segment--;
1616 		}
1617 
1618 		chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1619 		if (!chain_req)
1620 			return -1;
1621 		chain = chain_req->chain_buffer;
1622 		chain_dma = chain_req->chain_buffer_dma;
1623 	} while (1);
1624 
1625 
1626  fill_in_last_segment:
1627 
1628 	/* fill the last segment */
1629 	while (sges_left > 0) {
1630 		if (sges_left == 1)
1631 			_base_add_sg_single_ieee(sg_local,
1632 			    simple_sgl_flags_last, 0, sg_dma_len(sg_scmd),
1633 			    sg_dma_address(sg_scmd));
1634 		else
1635 			_base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1636 			    sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1637 		sg_scmd = sg_next(sg_scmd);
1638 		sg_local += ioc->sge_size_ieee;
1639 		sges_left--;
1640 	}
1641 
1642 	return 0;
1643 }
1644 
1645 /**
1646  * _base_build_sg_ieee - build generic sg for IEEE format
1647  * @ioc: per adapter object
1648  * @psge: virtual address for SGE
1649  * @data_out_dma: physical address for WRITES
1650  * @data_out_sz: data xfer size for WRITES
1651  * @data_in_dma: physical address for READS
1652  * @data_in_sz: data xfer size for READS
1653  *
1654  * Return nothing.
1655  */
1656 static void
1657 _base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge,
1658 	dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1659 	size_t data_in_sz)
1660 {
1661 	u8 sgl_flags;
1662 
1663 	if (!data_out_sz && !data_in_sz) {
1664 		_base_build_zero_len_sge_ieee(ioc, psge);
1665 		return;
1666 	}
1667 
1668 	if (data_out_sz && data_in_sz) {
1669 		/* WRITE sgel first */
1670 		sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1671 		    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1672 		_base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
1673 		    data_out_dma);
1674 
1675 		/* incr sgel */
1676 		psge += ioc->sge_size_ieee;
1677 
1678 		/* READ sgel last */
1679 		sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
1680 		_base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
1681 		    data_in_dma);
1682 	} else if (data_out_sz) /* WRITE */ {
1683 		sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1684 		    MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
1685 		    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1686 		_base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
1687 		    data_out_dma);
1688 	} else if (data_in_sz) /* READ */ {
1689 		sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1690 		    MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
1691 		    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1692 		_base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
1693 		    data_in_dma);
1694 	}
1695 }
1696 
1697 #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
1698 
1699 /**
1700  * _base_config_dma_addressing - set dma addressing
1701  * @ioc: per adapter object
1702  * @pdev: PCI device struct
1703  *
1704  * Returns 0 for success, non-zero for failure.
1705  */
1706 static int
1707 _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
1708 {
1709 	struct sysinfo s;
1710 	u64 consistent_dma_mask;
1711 
1712 	if (ioc->dma_mask)
1713 		consistent_dma_mask = DMA_BIT_MASK(64);
1714 	else
1715 		consistent_dma_mask = DMA_BIT_MASK(32);
1716 
1717 	if (sizeof(dma_addr_t) > 4) {
1718 		const uint64_t required_mask =
1719 		    dma_get_required_mask(&pdev->dev);
1720 		if ((required_mask > DMA_BIT_MASK(32)) &&
1721 		    !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
1722 		    !pci_set_consistent_dma_mask(pdev, consistent_dma_mask)) {
1723 			ioc->base_add_sg_single = &_base_add_sg_single_64;
1724 			ioc->sge_size = sizeof(Mpi2SGESimple64_t);
1725 			ioc->dma_mask = 64;
1726 			goto out;
1727 		}
1728 	}
1729 
1730 	if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
1731 	    && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1732 		ioc->base_add_sg_single = &_base_add_sg_single_32;
1733 		ioc->sge_size = sizeof(Mpi2SGESimple32_t);
1734 		ioc->dma_mask = 32;
1735 	} else
1736 		return -ENODEV;
1737 
1738  out:
1739 	si_meminfo(&s);
1740 	pr_info(MPT3SAS_FMT
1741 		"%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
1742 		ioc->name, ioc->dma_mask, convert_to_kb(s.totalram));
1743 
1744 	return 0;
1745 }
1746 
1747 static int
1748 _base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc,
1749 				      struct pci_dev *pdev)
1750 {
1751 	if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
1752 		if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
1753 			return -ENODEV;
1754 	}
1755 	return 0;
1756 }
1757 
1758 /**
1759  * _base_check_enable_msix - checks MSIX capabable.
1760  * @ioc: per adapter object
1761  *
1762  * Check to see if card is capable of MSIX, and set number
1763  * of available msix vectors
1764  */
1765 static int
1766 _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)
1767 {
1768 	int base;
1769 	u16 message_control;
1770 
1771 	/* Check whether controller SAS2008 B0 controller,
1772 	 * if it is SAS2008 B0 controller use IO-APIC instead of MSIX
1773 	 */
1774 	if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 &&
1775 	    ioc->pdev->revision == SAS2_PCI_DEVICE_B0_REVISION) {
1776 		return -EINVAL;
1777 	}
1778 
1779 	base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
1780 	if (!base) {
1781 		dfailprintk(ioc, pr_info(MPT3SAS_FMT "msix not supported\n",
1782 			ioc->name));
1783 		return -EINVAL;
1784 	}
1785 
1786 	/* get msix vector count */
1787 	/* NUMA_IO not supported for older controllers */
1788 	if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 ||
1789 	    ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 ||
1790 	    ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 ||
1791 	    ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 ||
1792 	    ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 ||
1793 	    ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 ||
1794 	    ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2)
1795 		ioc->msix_vector_count = 1;
1796 	else {
1797 		pci_read_config_word(ioc->pdev, base + 2, &message_control);
1798 		ioc->msix_vector_count = (message_control & 0x3FF) + 1;
1799 	}
1800 	dinitprintk(ioc, pr_info(MPT3SAS_FMT
1801 		"msix is supported, vector_count(%d)\n",
1802 		ioc->name, ioc->msix_vector_count));
1803 	return 0;
1804 }
1805 
1806 /**
1807  * _base_free_irq - free irq
1808  * @ioc: per adapter object
1809  *
1810  * Freeing respective reply_queue from the list.
1811  */
1812 static void
1813 _base_free_irq(struct MPT3SAS_ADAPTER *ioc)
1814 {
1815 	struct adapter_reply_queue *reply_q, *next;
1816 
1817 	if (list_empty(&ioc->reply_queue_list))
1818 		return;
1819 
1820 	list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
1821 		list_del(&reply_q->list);
1822 		if (smp_affinity_enable) {
1823 			irq_set_affinity_hint(reply_q->vector, NULL);
1824 			free_cpumask_var(reply_q->affinity_hint);
1825 		}
1826 		free_irq(reply_q->vector, reply_q);
1827 		kfree(reply_q);
1828 	}
1829 }
1830 
1831 /**
1832  * _base_request_irq - request irq
1833  * @ioc: per adapter object
1834  * @index: msix index into vector table
1835  * @vector: irq vector
1836  *
1837  * Inserting respective reply_queue into the list.
1838  */
1839 static int
1840 _base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index, u32 vector)
1841 {
1842 	struct adapter_reply_queue *reply_q;
1843 	int r;
1844 
1845 	reply_q =  kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL);
1846 	if (!reply_q) {
1847 		pr_err(MPT3SAS_FMT "unable to allocate memory %d!\n",
1848 		    ioc->name, (int)sizeof(struct adapter_reply_queue));
1849 		return -ENOMEM;
1850 	}
1851 	reply_q->ioc = ioc;
1852 	reply_q->msix_index = index;
1853 	reply_q->vector = vector;
1854 
1855 	if (smp_affinity_enable) {
1856 		if (!zalloc_cpumask_var(&reply_q->affinity_hint, GFP_KERNEL)) {
1857 			kfree(reply_q);
1858 			return -ENOMEM;
1859 		}
1860 	}
1861 
1862 	atomic_set(&reply_q->busy, 0);
1863 	if (ioc->msix_enable)
1864 		snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d",
1865 		    ioc->driver_name, ioc->id, index);
1866 	else
1867 		snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d",
1868 		    ioc->driver_name, ioc->id);
1869 	r = request_irq(vector, _base_interrupt, IRQF_SHARED, reply_q->name,
1870 	    reply_q);
1871 	if (r) {
1872 		pr_err(MPT3SAS_FMT "unable to allocate interrupt %d!\n",
1873 		    reply_q->name, vector);
1874 		free_cpumask_var(reply_q->affinity_hint);
1875 		kfree(reply_q);
1876 		return -EBUSY;
1877 	}
1878 
1879 	INIT_LIST_HEAD(&reply_q->list);
1880 	list_add_tail(&reply_q->list, &ioc->reply_queue_list);
1881 	return 0;
1882 }
1883 
1884 /**
1885  * _base_assign_reply_queues - assigning msix index for each cpu
1886  * @ioc: per adapter object
1887  *
1888  * The enduser would need to set the affinity via /proc/irq/#/smp_affinity
1889  *
1890  * It would nice if we could call irq_set_affinity, however it is not
1891  * an exported symbol
1892  */
1893 static void
1894 _base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc)
1895 {
1896 	unsigned int cpu, nr_cpus, nr_msix, index = 0;
1897 	struct adapter_reply_queue *reply_q;
1898 
1899 	if (!_base_is_controller_msix_enabled(ioc))
1900 		return;
1901 
1902 	memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz);
1903 
1904 	nr_cpus = num_online_cpus();
1905 	nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count,
1906 					       ioc->facts.MaxMSIxVectors);
1907 	if (!nr_msix)
1908 		return;
1909 
1910 	cpu = cpumask_first(cpu_online_mask);
1911 
1912 	list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1913 
1914 		unsigned int i, group = nr_cpus / nr_msix;
1915 
1916 		if (cpu >= nr_cpus)
1917 			break;
1918 
1919 		if (index < nr_cpus % nr_msix)
1920 			group++;
1921 
1922 		for (i = 0 ; i < group ; i++) {
1923 			ioc->cpu_msix_table[cpu] = index;
1924 			if (smp_affinity_enable)
1925 				cpumask_or(reply_q->affinity_hint,
1926 				   reply_q->affinity_hint, get_cpu_mask(cpu));
1927 			cpu = cpumask_next(cpu, cpu_online_mask);
1928 		}
1929 		if (smp_affinity_enable)
1930 			if (irq_set_affinity_hint(reply_q->vector,
1931 					   reply_q->affinity_hint))
1932 				dinitprintk(ioc, pr_info(MPT3SAS_FMT
1933 				 "Err setting affinity hint to irq vector %d\n",
1934 				 ioc->name, reply_q->vector));
1935 		index++;
1936 	}
1937 }
1938 
1939 /**
1940  * _base_disable_msix - disables msix
1941  * @ioc: per adapter object
1942  *
1943  */
1944 static void
1945 _base_disable_msix(struct MPT3SAS_ADAPTER *ioc)
1946 {
1947 	if (!ioc->msix_enable)
1948 		return;
1949 	pci_disable_msix(ioc->pdev);
1950 	ioc->msix_enable = 0;
1951 }
1952 
1953 /**
1954  * _base_enable_msix - enables msix, failback to io_apic
1955  * @ioc: per adapter object
1956  *
1957  */
1958 static int
1959 _base_enable_msix(struct MPT3SAS_ADAPTER *ioc)
1960 {
1961 	struct msix_entry *entries, *a;
1962 	int r;
1963 	int i;
1964 	u8 try_msix = 0;
1965 
1966 	if (msix_disable == -1 || msix_disable == 0)
1967 		try_msix = 1;
1968 
1969 	if (!try_msix)
1970 		goto try_ioapic;
1971 
1972 	if (_base_check_enable_msix(ioc) != 0)
1973 		goto try_ioapic;
1974 
1975 	ioc->reply_queue_count = min_t(int, ioc->cpu_count,
1976 	    ioc->msix_vector_count);
1977 
1978 	printk(MPT3SAS_FMT "MSI-X vectors supported: %d, no of cores"
1979 	  ": %d, max_msix_vectors: %d\n", ioc->name, ioc->msix_vector_count,
1980 	  ioc->cpu_count, max_msix_vectors);
1981 
1982 	if (!ioc->rdpq_array_enable && max_msix_vectors == -1)
1983 		max_msix_vectors = 8;
1984 
1985 	if (max_msix_vectors > 0) {
1986 		ioc->reply_queue_count = min_t(int, max_msix_vectors,
1987 			ioc->reply_queue_count);
1988 		ioc->msix_vector_count = ioc->reply_queue_count;
1989 	} else if (max_msix_vectors == 0)
1990 		goto try_ioapic;
1991 
1992 	if (ioc->msix_vector_count < ioc->cpu_count)
1993 		smp_affinity_enable = 0;
1994 
1995 	entries = kcalloc(ioc->reply_queue_count, sizeof(struct msix_entry),
1996 	    GFP_KERNEL);
1997 	if (!entries) {
1998 		dfailprintk(ioc, pr_info(MPT3SAS_FMT
1999 			"kcalloc failed @ at %s:%d/%s() !!!\n",
2000 			ioc->name, __FILE__, __LINE__, __func__));
2001 		goto try_ioapic;
2002 	}
2003 
2004 	for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++)
2005 		a->entry = i;
2006 
2007 	r = pci_enable_msix_exact(ioc->pdev, entries, ioc->reply_queue_count);
2008 	if (r) {
2009 		dfailprintk(ioc, pr_info(MPT3SAS_FMT
2010 			"pci_enable_msix_exact failed (r=%d) !!!\n",
2011 			ioc->name, r));
2012 		kfree(entries);
2013 		goto try_ioapic;
2014 	}
2015 
2016 	ioc->msix_enable = 1;
2017 	for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++) {
2018 		r = _base_request_irq(ioc, i, a->vector);
2019 		if (r) {
2020 			_base_free_irq(ioc);
2021 			_base_disable_msix(ioc);
2022 			kfree(entries);
2023 			goto try_ioapic;
2024 		}
2025 	}
2026 
2027 	kfree(entries);
2028 	return 0;
2029 
2030 /* failback to io_apic interrupt routing */
2031  try_ioapic:
2032 
2033 	ioc->reply_queue_count = 1;
2034 	r = _base_request_irq(ioc, 0, ioc->pdev->irq);
2035 
2036 	return r;
2037 }
2038 
2039 /**
2040  * mpt3sas_base_unmap_resources - free controller resources
2041  * @ioc: per adapter object
2042  */
2043 void
2044 mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc)
2045 {
2046 	struct pci_dev *pdev = ioc->pdev;
2047 
2048 	dexitprintk(ioc, printk(MPT3SAS_FMT "%s\n",
2049 		ioc->name, __func__));
2050 
2051 	_base_free_irq(ioc);
2052 	_base_disable_msix(ioc);
2053 
2054 	if (ioc->msix96_vector) {
2055 		kfree(ioc->replyPostRegisterIndex);
2056 		ioc->replyPostRegisterIndex = NULL;
2057 	}
2058 
2059 	if (ioc->chip_phys) {
2060 		iounmap(ioc->chip);
2061 		ioc->chip_phys = 0;
2062 	}
2063 
2064 	if (pci_is_enabled(pdev)) {
2065 		pci_release_selected_regions(ioc->pdev, ioc->bars);
2066 		pci_disable_pcie_error_reporting(pdev);
2067 		pci_disable_device(pdev);
2068 	}
2069 }
2070 
2071 /**
2072  * mpt3sas_base_map_resources - map in controller resources (io/irq/memap)
2073  * @ioc: per adapter object
2074  *
2075  * Returns 0 for success, non-zero for failure.
2076  */
2077 int
2078 mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
2079 {
2080 	struct pci_dev *pdev = ioc->pdev;
2081 	u32 memap_sz;
2082 	u32 pio_sz;
2083 	int i, r = 0;
2084 	u64 pio_chip = 0;
2085 	u64 chip_phys = 0;
2086 	struct adapter_reply_queue *reply_q;
2087 
2088 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n",
2089 	    ioc->name, __func__));
2090 
2091 	ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
2092 	if (pci_enable_device_mem(pdev)) {
2093 		pr_warn(MPT3SAS_FMT "pci_enable_device_mem: failed\n",
2094 			ioc->name);
2095 		ioc->bars = 0;
2096 		return -ENODEV;
2097 	}
2098 
2099 
2100 	if (pci_request_selected_regions(pdev, ioc->bars,
2101 	    ioc->driver_name)) {
2102 		pr_warn(MPT3SAS_FMT "pci_request_selected_regions: failed\n",
2103 			ioc->name);
2104 		ioc->bars = 0;
2105 		r = -ENODEV;
2106 		goto out_fail;
2107 	}
2108 
2109 /* AER (Advanced Error Reporting) hooks */
2110 	pci_enable_pcie_error_reporting(pdev);
2111 
2112 	pci_set_master(pdev);
2113 
2114 
2115 	if (_base_config_dma_addressing(ioc, pdev) != 0) {
2116 		pr_warn(MPT3SAS_FMT "no suitable DMA mask for %s\n",
2117 		    ioc->name, pci_name(pdev));
2118 		r = -ENODEV;
2119 		goto out_fail;
2120 	}
2121 
2122 	for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) &&
2123 	     (!memap_sz || !pio_sz); i++) {
2124 		if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
2125 			if (pio_sz)
2126 				continue;
2127 			pio_chip = (u64)pci_resource_start(pdev, i);
2128 			pio_sz = pci_resource_len(pdev, i);
2129 		} else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
2130 			if (memap_sz)
2131 				continue;
2132 			ioc->chip_phys = pci_resource_start(pdev, i);
2133 			chip_phys = (u64)ioc->chip_phys;
2134 			memap_sz = pci_resource_len(pdev, i);
2135 			ioc->chip = ioremap(ioc->chip_phys, memap_sz);
2136 		}
2137 	}
2138 
2139 	if (ioc->chip == NULL) {
2140 		pr_err(MPT3SAS_FMT "unable to map adapter memory! "
2141 			" or resource not found\n", ioc->name);
2142 		r = -EINVAL;
2143 		goto out_fail;
2144 	}
2145 
2146 	_base_mask_interrupts(ioc);
2147 
2148 	r = _base_get_ioc_facts(ioc, CAN_SLEEP);
2149 	if (r)
2150 		goto out_fail;
2151 
2152 	if (!ioc->rdpq_array_enable_assigned) {
2153 		ioc->rdpq_array_enable = ioc->rdpq_array_capable;
2154 		ioc->rdpq_array_enable_assigned = 1;
2155 	}
2156 
2157 	r = _base_enable_msix(ioc);
2158 	if (r)
2159 		goto out_fail;
2160 
2161 	/* Use the Combined reply queue feature only for SAS3 C0 & higher
2162 	 * revision HBAs and also only when reply queue count is greater than 8
2163 	 */
2164 	if (ioc->msix96_vector && ioc->reply_queue_count > 8) {
2165 		/* Determine the Supplemental Reply Post Host Index Registers
2166 		 * Addresse. Supplemental Reply Post Host Index Registers
2167 		 * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and
2168 		 * each register is at offset bytes of
2169 		 * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one.
2170 		 */
2171 		ioc->replyPostRegisterIndex = kcalloc(
2172 		     MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT,
2173 		     sizeof(resource_size_t *), GFP_KERNEL);
2174 		if (!ioc->replyPostRegisterIndex) {
2175 			dfailprintk(ioc, printk(MPT3SAS_FMT
2176 			"allocation for reply Post Register Index failed!!!\n",
2177 								   ioc->name));
2178 			r = -ENOMEM;
2179 			goto out_fail;
2180 		}
2181 
2182 		for (i = 0; i < MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT; i++) {
2183 			ioc->replyPostRegisterIndex[i] = (resource_size_t *)
2184 			     ((u8 *)&ioc->chip->Doorbell +
2185 			     MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET +
2186 			     (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET));
2187 		}
2188 	} else
2189 		ioc->msix96_vector = 0;
2190 
2191 	list_for_each_entry(reply_q, &ioc->reply_queue_list, list)
2192 		pr_info(MPT3SAS_FMT "%s: IRQ %d\n",
2193 		    reply_q->name,  ((ioc->msix_enable) ? "PCI-MSI-X enabled" :
2194 		    "IO-APIC enabled"), reply_q->vector);
2195 
2196 	pr_info(MPT3SAS_FMT "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
2197 	    ioc->name, (unsigned long long)chip_phys, ioc->chip, memap_sz);
2198 	pr_info(MPT3SAS_FMT "ioport(0x%016llx), size(%d)\n",
2199 	    ioc->name, (unsigned long long)pio_chip, pio_sz);
2200 
2201 	/* Save PCI configuration state for recovery from PCI AER/EEH errors */
2202 	pci_save_state(pdev);
2203 	return 0;
2204 
2205  out_fail:
2206 	mpt3sas_base_unmap_resources(ioc);
2207 	return r;
2208 }
2209 
2210 /**
2211  * mpt3sas_base_get_msg_frame - obtain request mf pointer
2212  * @ioc: per adapter object
2213  * @smid: system request message index(smid zero is invalid)
2214  *
2215  * Returns virt pointer to message frame.
2216  */
2217 void *
2218 mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2219 {
2220 	return (void *)(ioc->request + (smid * ioc->request_sz));
2221 }
2222 
2223 /**
2224  * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr
2225  * @ioc: per adapter object
2226  * @smid: system request message index
2227  *
2228  * Returns virt pointer to sense buffer.
2229  */
2230 void *
2231 mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2232 {
2233 	return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
2234 }
2235 
2236 /**
2237  * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr
2238  * @ioc: per adapter object
2239  * @smid: system request message index
2240  *
2241  * Returns phys pointer to the low 32bit address of the sense buffer.
2242  */
2243 __le32
2244 mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2245 {
2246 	return cpu_to_le32(ioc->sense_dma + ((smid - 1) *
2247 	    SCSI_SENSE_BUFFERSIZE));
2248 }
2249 
2250 /**
2251  * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address
2252  * @ioc: per adapter object
2253  * @phys_addr: lower 32 physical addr of the reply
2254  *
2255  * Converts 32bit lower physical addr into a virt address.
2256  */
2257 void *
2258 mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr)
2259 {
2260 	if (!phys_addr)
2261 		return NULL;
2262 	return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
2263 }
2264 
2265 static inline u8
2266 _base_get_msix_index(struct MPT3SAS_ADAPTER *ioc)
2267 {
2268 	return ioc->cpu_msix_table[raw_smp_processor_id()];
2269 }
2270 
2271 /**
2272  * mpt3sas_base_get_smid - obtain a free smid from internal queue
2273  * @ioc: per adapter object
2274  * @cb_idx: callback index
2275  *
2276  * Returns smid (zero is invalid)
2277  */
2278 u16
2279 mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
2280 {
2281 	unsigned long flags;
2282 	struct request_tracker *request;
2283 	u16 smid;
2284 
2285 	spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2286 	if (list_empty(&ioc->internal_free_list)) {
2287 		spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2288 		pr_err(MPT3SAS_FMT "%s: smid not available\n",
2289 		    ioc->name, __func__);
2290 		return 0;
2291 	}
2292 
2293 	request = list_entry(ioc->internal_free_list.next,
2294 	    struct request_tracker, tracker_list);
2295 	request->cb_idx = cb_idx;
2296 	smid = request->smid;
2297 	list_del(&request->tracker_list);
2298 	spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2299 	return smid;
2300 }
2301 
2302 /**
2303  * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue
2304  * @ioc: per adapter object
2305  * @cb_idx: callback index
2306  * @scmd: pointer to scsi command object
2307  *
2308  * Returns smid (zero is invalid)
2309  */
2310 u16
2311 mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx,
2312 	struct scsi_cmnd *scmd)
2313 {
2314 	unsigned long flags;
2315 	struct scsiio_tracker *request;
2316 	u16 smid;
2317 
2318 	spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2319 	if (list_empty(&ioc->free_list)) {
2320 		spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2321 		pr_err(MPT3SAS_FMT "%s: smid not available\n",
2322 		    ioc->name, __func__);
2323 		return 0;
2324 	}
2325 
2326 	request = list_entry(ioc->free_list.next,
2327 	    struct scsiio_tracker, tracker_list);
2328 	request->scmd = scmd;
2329 	request->cb_idx = cb_idx;
2330 	smid = request->smid;
2331 	request->msix_io = _base_get_msix_index(ioc);
2332 	list_del(&request->tracker_list);
2333 	spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2334 	return smid;
2335 }
2336 
2337 /**
2338  * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue
2339  * @ioc: per adapter object
2340  * @cb_idx: callback index
2341  *
2342  * Returns smid (zero is invalid)
2343  */
2344 u16
2345 mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
2346 {
2347 	unsigned long flags;
2348 	struct request_tracker *request;
2349 	u16 smid;
2350 
2351 	spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2352 	if (list_empty(&ioc->hpr_free_list)) {
2353 		spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2354 		return 0;
2355 	}
2356 
2357 	request = list_entry(ioc->hpr_free_list.next,
2358 	    struct request_tracker, tracker_list);
2359 	request->cb_idx = cb_idx;
2360 	smid = request->smid;
2361 	list_del(&request->tracker_list);
2362 	spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2363 	return smid;
2364 }
2365 
2366 /**
2367  * mpt3sas_base_free_smid - put smid back on free_list
2368  * @ioc: per adapter object
2369  * @smid: system request message index
2370  *
2371  * Return nothing.
2372  */
2373 void
2374 mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2375 {
2376 	unsigned long flags;
2377 	int i;
2378 	struct chain_tracker *chain_req, *next;
2379 
2380 	spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2381 	if (smid < ioc->hi_priority_smid) {
2382 		/* scsiio queue */
2383 		i = smid - 1;
2384 		if (!list_empty(&ioc->scsi_lookup[i].chain_list)) {
2385 			list_for_each_entry_safe(chain_req, next,
2386 			    &ioc->scsi_lookup[i].chain_list, tracker_list) {
2387 				list_del_init(&chain_req->tracker_list);
2388 				list_add(&chain_req->tracker_list,
2389 				    &ioc->free_chain_list);
2390 			}
2391 		}
2392 		ioc->scsi_lookup[i].cb_idx = 0xFF;
2393 		ioc->scsi_lookup[i].scmd = NULL;
2394 		ioc->scsi_lookup[i].direct_io = 0;
2395 		list_add(&ioc->scsi_lookup[i].tracker_list, &ioc->free_list);
2396 		spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2397 
2398 		/*
2399 		 * See _wait_for_commands_to_complete() call with regards
2400 		 * to this code.
2401 		 */
2402 		if (ioc->shost_recovery && ioc->pending_io_count) {
2403 			if (ioc->pending_io_count == 1)
2404 				wake_up(&ioc->reset_wq);
2405 			ioc->pending_io_count--;
2406 		}
2407 		return;
2408 	} else if (smid < ioc->internal_smid) {
2409 		/* hi-priority */
2410 		i = smid - ioc->hi_priority_smid;
2411 		ioc->hpr_lookup[i].cb_idx = 0xFF;
2412 		list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list);
2413 	} else if (smid <= ioc->hba_queue_depth) {
2414 		/* internal queue */
2415 		i = smid - ioc->internal_smid;
2416 		ioc->internal_lookup[i].cb_idx = 0xFF;
2417 		list_add(&ioc->internal_lookup[i].tracker_list,
2418 		    &ioc->internal_free_list);
2419 	}
2420 	spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2421 }
2422 
2423 /**
2424  * _base_writeq - 64 bit write to MMIO
2425  * @ioc: per adapter object
2426  * @b: data payload
2427  * @addr: address in MMIO space
2428  * @writeq_lock: spin lock
2429  *
2430  * Glue for handling an atomic 64 bit word to MMIO. This special handling takes
2431  * care of 32 bit environment where its not quarenteed to send the entire word
2432  * in one transfer.
2433  */
2434 #if defined(writeq) && defined(CONFIG_64BIT)
2435 static inline void
2436 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
2437 {
2438 	writeq(cpu_to_le64(b), addr);
2439 }
2440 #else
2441 static inline void
2442 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
2443 {
2444 	unsigned long flags;
2445 	__u64 data_out = cpu_to_le64(b);
2446 
2447 	spin_lock_irqsave(writeq_lock, flags);
2448 	writel((u32)(data_out), addr);
2449 	writel((u32)(data_out >> 32), (addr + 4));
2450 	spin_unlock_irqrestore(writeq_lock, flags);
2451 }
2452 #endif
2453 
2454 /**
2455  * mpt3sas_base_put_smid_scsi_io - send SCSI_IO request to firmware
2456  * @ioc: per adapter object
2457  * @smid: system request message index
2458  * @handle: device handle
2459  *
2460  * Return nothing.
2461  */
2462 void
2463 mpt3sas_base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle)
2464 {
2465 	Mpi2RequestDescriptorUnion_t descriptor;
2466 	u64 *request = (u64 *)&descriptor;
2467 
2468 
2469 	descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
2470 	descriptor.SCSIIO.MSIxIndex =  _base_get_msix_index(ioc);
2471 	descriptor.SCSIIO.SMID = cpu_to_le16(smid);
2472 	descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
2473 	descriptor.SCSIIO.LMID = 0;
2474 	_base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2475 	    &ioc->scsi_lookup_lock);
2476 }
2477 
2478 /**
2479  * mpt3sas_base_put_smid_fast_path - send fast path request to firmware
2480  * @ioc: per adapter object
2481  * @smid: system request message index
2482  * @handle: device handle
2483  *
2484  * Return nothing.
2485  */
2486 void
2487 mpt3sas_base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid,
2488 	u16 handle)
2489 {
2490 	Mpi2RequestDescriptorUnion_t descriptor;
2491 	u64 *request = (u64 *)&descriptor;
2492 
2493 	descriptor.SCSIIO.RequestFlags =
2494 	    MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
2495 	descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
2496 	descriptor.SCSIIO.SMID = cpu_to_le16(smid);
2497 	descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
2498 	descriptor.SCSIIO.LMID = 0;
2499 	_base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2500 	    &ioc->scsi_lookup_lock);
2501 }
2502 
2503 /**
2504  * mpt3sas_base_put_smid_hi_priority - send Task Managment request to firmware
2505  * @ioc: per adapter object
2506  * @smid: system request message index
2507  * @msix_task: msix_task will be same as msix of IO incase of task abort else 0.
2508  * Return nothing.
2509  */
2510 void
2511 mpt3sas_base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid,
2512 	u16 msix_task)
2513 {
2514 	Mpi2RequestDescriptorUnion_t descriptor;
2515 	u64 *request = (u64 *)&descriptor;
2516 
2517 	descriptor.HighPriority.RequestFlags =
2518 	    MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
2519 	descriptor.HighPriority.MSIxIndex =  msix_task;
2520 	descriptor.HighPriority.SMID = cpu_to_le16(smid);
2521 	descriptor.HighPriority.LMID = 0;
2522 	descriptor.HighPriority.Reserved1 = 0;
2523 	_base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2524 	    &ioc->scsi_lookup_lock);
2525 }
2526 
2527 /**
2528  * mpt3sas_base_put_smid_default - Default, primarily used for config pages
2529  * @ioc: per adapter object
2530  * @smid: system request message index
2531  *
2532  * Return nothing.
2533  */
2534 void
2535 mpt3sas_base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2536 {
2537 	Mpi2RequestDescriptorUnion_t descriptor;
2538 	u64 *request = (u64 *)&descriptor;
2539 
2540 	descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
2541 	descriptor.Default.MSIxIndex =  _base_get_msix_index(ioc);
2542 	descriptor.Default.SMID = cpu_to_le16(smid);
2543 	descriptor.Default.LMID = 0;
2544 	descriptor.Default.DescriptorTypeDependent = 0;
2545 	_base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2546 	    &ioc->scsi_lookup_lock);
2547 }
2548 
2549 /**
2550  * _base_display_OEMs_branding - Display branding string
2551  * @ioc: per adapter object
2552  *
2553  * Return nothing.
2554  */
2555 static void
2556 _base_display_OEMs_branding(struct MPT3SAS_ADAPTER *ioc)
2557 {
2558 	if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL)
2559 		return;
2560 
2561 	switch (ioc->pdev->subsystem_vendor) {
2562 	case PCI_VENDOR_ID_INTEL:
2563 		switch (ioc->pdev->device) {
2564 		case MPI2_MFGPAGE_DEVID_SAS2008:
2565 			switch (ioc->pdev->subsystem_device) {
2566 			case MPT2SAS_INTEL_RMS2LL080_SSDID:
2567 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2568 				    MPT2SAS_INTEL_RMS2LL080_BRANDING);
2569 				break;
2570 			case MPT2SAS_INTEL_RMS2LL040_SSDID:
2571 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2572 				    MPT2SAS_INTEL_RMS2LL040_BRANDING);
2573 				break;
2574 			case MPT2SAS_INTEL_SSD910_SSDID:
2575 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2576 				    MPT2SAS_INTEL_SSD910_BRANDING);
2577 				break;
2578 			default:
2579 				pr_info(MPT3SAS_FMT
2580 				 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2581 				 ioc->name, ioc->pdev->subsystem_device);
2582 				break;
2583 			}
2584 		case MPI2_MFGPAGE_DEVID_SAS2308_2:
2585 			switch (ioc->pdev->subsystem_device) {
2586 			case MPT2SAS_INTEL_RS25GB008_SSDID:
2587 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2588 				    MPT2SAS_INTEL_RS25GB008_BRANDING);
2589 				break;
2590 			case MPT2SAS_INTEL_RMS25JB080_SSDID:
2591 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2592 				    MPT2SAS_INTEL_RMS25JB080_BRANDING);
2593 				break;
2594 			case MPT2SAS_INTEL_RMS25JB040_SSDID:
2595 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2596 				    MPT2SAS_INTEL_RMS25JB040_BRANDING);
2597 				break;
2598 			case MPT2SAS_INTEL_RMS25KB080_SSDID:
2599 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2600 				    MPT2SAS_INTEL_RMS25KB080_BRANDING);
2601 				break;
2602 			case MPT2SAS_INTEL_RMS25KB040_SSDID:
2603 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2604 				    MPT2SAS_INTEL_RMS25KB040_BRANDING);
2605 				break;
2606 			case MPT2SAS_INTEL_RMS25LB040_SSDID:
2607 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2608 				    MPT2SAS_INTEL_RMS25LB040_BRANDING);
2609 				break;
2610 			case MPT2SAS_INTEL_RMS25LB080_SSDID:
2611 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2612 				    MPT2SAS_INTEL_RMS25LB080_BRANDING);
2613 				break;
2614 			default:
2615 				pr_info(MPT3SAS_FMT
2616 				 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2617 				 ioc->name, ioc->pdev->subsystem_device);
2618 				break;
2619 			}
2620 		case MPI25_MFGPAGE_DEVID_SAS3008:
2621 			switch (ioc->pdev->subsystem_device) {
2622 			case MPT3SAS_INTEL_RMS3JC080_SSDID:
2623 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2624 					MPT3SAS_INTEL_RMS3JC080_BRANDING);
2625 				break;
2626 
2627 			case MPT3SAS_INTEL_RS3GC008_SSDID:
2628 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2629 					MPT3SAS_INTEL_RS3GC008_BRANDING);
2630 				break;
2631 			case MPT3SAS_INTEL_RS3FC044_SSDID:
2632 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2633 					MPT3SAS_INTEL_RS3FC044_BRANDING);
2634 				break;
2635 			case MPT3SAS_INTEL_RS3UC080_SSDID:
2636 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2637 					MPT3SAS_INTEL_RS3UC080_BRANDING);
2638 				break;
2639 			default:
2640 				pr_info(MPT3SAS_FMT
2641 				 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2642 				 ioc->name, ioc->pdev->subsystem_device);
2643 				break;
2644 			}
2645 			break;
2646 		default:
2647 			pr_info(MPT3SAS_FMT
2648 			 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2649 			 ioc->name, ioc->pdev->subsystem_device);
2650 			break;
2651 		}
2652 		break;
2653 	case PCI_VENDOR_ID_DELL:
2654 		switch (ioc->pdev->device) {
2655 		case MPI2_MFGPAGE_DEVID_SAS2008:
2656 			switch (ioc->pdev->subsystem_device) {
2657 			case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID:
2658 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2659 				 MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING);
2660 				break;
2661 			case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID:
2662 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2663 				 MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING);
2664 				break;
2665 			case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID:
2666 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2667 				 MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING);
2668 				break;
2669 			case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID:
2670 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2671 				 MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING);
2672 				break;
2673 			case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID:
2674 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2675 				 MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING);
2676 				break;
2677 			case MPT2SAS_DELL_PERC_H200_SSDID:
2678 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2679 				 MPT2SAS_DELL_PERC_H200_BRANDING);
2680 				break;
2681 			case MPT2SAS_DELL_6GBPS_SAS_SSDID:
2682 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2683 				 MPT2SAS_DELL_6GBPS_SAS_BRANDING);
2684 				break;
2685 			default:
2686 				pr_info(MPT3SAS_FMT
2687 				   "Dell 6Gbps HBA: Subsystem ID: 0x%X\n",
2688 				   ioc->name, ioc->pdev->subsystem_device);
2689 				break;
2690 			}
2691 			break;
2692 		case MPI25_MFGPAGE_DEVID_SAS3008:
2693 			switch (ioc->pdev->subsystem_device) {
2694 			case MPT3SAS_DELL_12G_HBA_SSDID:
2695 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2696 					MPT3SAS_DELL_12G_HBA_BRANDING);
2697 				break;
2698 			default:
2699 				pr_info(MPT3SAS_FMT
2700 				   "Dell 12Gbps HBA: Subsystem ID: 0x%X\n",
2701 				   ioc->name, ioc->pdev->subsystem_device);
2702 				break;
2703 			}
2704 			break;
2705 		default:
2706 			pr_info(MPT3SAS_FMT
2707 			   "Dell HBA: Subsystem ID: 0x%X\n", ioc->name,
2708 			   ioc->pdev->subsystem_device);
2709 			break;
2710 		}
2711 		break;
2712 	case PCI_VENDOR_ID_CISCO:
2713 		switch (ioc->pdev->device) {
2714 		case MPI25_MFGPAGE_DEVID_SAS3008:
2715 			switch (ioc->pdev->subsystem_device) {
2716 			case MPT3SAS_CISCO_12G_8E_HBA_SSDID:
2717 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2718 					MPT3SAS_CISCO_12G_8E_HBA_BRANDING);
2719 				break;
2720 			case MPT3SAS_CISCO_12G_8I_HBA_SSDID:
2721 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2722 					MPT3SAS_CISCO_12G_8I_HBA_BRANDING);
2723 				break;
2724 			case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
2725 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2726 					MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
2727 				break;
2728 			default:
2729 				pr_info(MPT3SAS_FMT
2730 				  "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
2731 				  ioc->name, ioc->pdev->subsystem_device);
2732 				break;
2733 			}
2734 			break;
2735 		case MPI25_MFGPAGE_DEVID_SAS3108_1:
2736 			switch (ioc->pdev->subsystem_device) {
2737 			case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
2738 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2739 				MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
2740 				break;
2741 			case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID:
2742 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2743 				MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING
2744 				);
2745 				break;
2746 			default:
2747 				pr_info(MPT3SAS_FMT
2748 				 "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
2749 				 ioc->name, ioc->pdev->subsystem_device);
2750 				break;
2751 			}
2752 			break;
2753 		default:
2754 			pr_info(MPT3SAS_FMT
2755 			   "Cisco SAS HBA: Subsystem ID: 0x%X\n",
2756 			   ioc->name, ioc->pdev->subsystem_device);
2757 			break;
2758 		}
2759 		break;
2760 	case MPT2SAS_HP_3PAR_SSVID:
2761 		switch (ioc->pdev->device) {
2762 		case MPI2_MFGPAGE_DEVID_SAS2004:
2763 			switch (ioc->pdev->subsystem_device) {
2764 			case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID:
2765 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2766 				    MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING);
2767 				break;
2768 			default:
2769 				pr_info(MPT3SAS_FMT
2770 				   "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
2771 				   ioc->name, ioc->pdev->subsystem_device);
2772 				break;
2773 			}
2774 		case MPI2_MFGPAGE_DEVID_SAS2308_2:
2775 			switch (ioc->pdev->subsystem_device) {
2776 			case MPT2SAS_HP_2_4_INTERNAL_SSDID:
2777 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2778 				    MPT2SAS_HP_2_4_INTERNAL_BRANDING);
2779 				break;
2780 			case MPT2SAS_HP_2_4_EXTERNAL_SSDID:
2781 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2782 				    MPT2SAS_HP_2_4_EXTERNAL_BRANDING);
2783 				break;
2784 			case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID:
2785 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2786 				 MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING);
2787 				break;
2788 			case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID:
2789 				pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2790 				    MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING);
2791 				break;
2792 			default:
2793 				pr_info(MPT3SAS_FMT
2794 				   "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
2795 				   ioc->name, ioc->pdev->subsystem_device);
2796 				break;
2797 			}
2798 		default:
2799 			pr_info(MPT3SAS_FMT
2800 			   "HP SAS HBA: Subsystem ID: 0x%X\n",
2801 			   ioc->name, ioc->pdev->subsystem_device);
2802 			break;
2803 		}
2804 	default:
2805 		break;
2806 	}
2807 }
2808 
2809 /**
2810  * _base_display_ioc_capabilities - Disply IOC's capabilities.
2811  * @ioc: per adapter object
2812  *
2813  * Return nothing.
2814  */
2815 static void
2816 _base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc)
2817 {
2818 	int i = 0;
2819 	char desc[16];
2820 	u32 iounit_pg1_flags;
2821 	u32 bios_version;
2822 
2823 	bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion);
2824 	strncpy(desc, ioc->manu_pg0.ChipName, 16);
2825 	pr_info(MPT3SAS_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "\
2826 	   "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
2827 	    ioc->name, desc,
2828 	   (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
2829 	   (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
2830 	   (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
2831 	   ioc->facts.FWVersion.Word & 0x000000FF,
2832 	   ioc->pdev->revision,
2833 	   (bios_version & 0xFF000000) >> 24,
2834 	   (bios_version & 0x00FF0000) >> 16,
2835 	   (bios_version & 0x0000FF00) >> 8,
2836 	    bios_version & 0x000000FF);
2837 
2838 	_base_display_OEMs_branding(ioc);
2839 
2840 	pr_info(MPT3SAS_FMT "Protocol=(", ioc->name);
2841 
2842 	if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
2843 		pr_info("Initiator");
2844 		i++;
2845 	}
2846 
2847 	if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
2848 		pr_info("%sTarget", i ? "," : "");
2849 		i++;
2850 	}
2851 
2852 	i = 0;
2853 	pr_info("), ");
2854 	pr_info("Capabilities=(");
2855 
2856 	if (!ioc->hide_ir_msg) {
2857 		if (ioc->facts.IOCCapabilities &
2858 		    MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
2859 			pr_info("Raid");
2860 			i++;
2861 		}
2862 	}
2863 
2864 	if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
2865 		pr_info("%sTLR", i ? "," : "");
2866 		i++;
2867 	}
2868 
2869 	if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
2870 		pr_info("%sMulticast", i ? "," : "");
2871 		i++;
2872 	}
2873 
2874 	if (ioc->facts.IOCCapabilities &
2875 	    MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
2876 		pr_info("%sBIDI Target", i ? "," : "");
2877 		i++;
2878 	}
2879 
2880 	if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
2881 		pr_info("%sEEDP", i ? "," : "");
2882 		i++;
2883 	}
2884 
2885 	if (ioc->facts.IOCCapabilities &
2886 	    MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
2887 		pr_info("%sSnapshot Buffer", i ? "," : "");
2888 		i++;
2889 	}
2890 
2891 	if (ioc->facts.IOCCapabilities &
2892 	    MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
2893 		pr_info("%sDiag Trace Buffer", i ? "," : "");
2894 		i++;
2895 	}
2896 
2897 	if (ioc->facts.IOCCapabilities &
2898 	    MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
2899 		pr_info("%sDiag Extended Buffer", i ? "," : "");
2900 		i++;
2901 	}
2902 
2903 	if (ioc->facts.IOCCapabilities &
2904 	    MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
2905 		pr_info("%sTask Set Full", i ? "," : "");
2906 		i++;
2907 	}
2908 
2909 	iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
2910 	if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
2911 		pr_info("%sNCQ", i ? "," : "");
2912 		i++;
2913 	}
2914 
2915 	pr_info(")\n");
2916 }
2917 
2918 /**
2919  * mpt3sas_base_update_missing_delay - change the missing delay timers
2920  * @ioc: per adapter object
2921  * @device_missing_delay: amount of time till device is reported missing
2922  * @io_missing_delay: interval IO is returned when there is a missing device
2923  *
2924  * Return nothing.
2925  *
2926  * Passed on the command line, this function will modify the device missing
2927  * delay, as well as the io missing delay. This should be called at driver
2928  * load time.
2929  */
2930 void
2931 mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc,
2932 	u16 device_missing_delay, u8 io_missing_delay)
2933 {
2934 	u16 dmd, dmd_new, dmd_orignal;
2935 	u8 io_missing_delay_original;
2936 	u16 sz;
2937 	Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL;
2938 	Mpi2ConfigReply_t mpi_reply;
2939 	u8 num_phys = 0;
2940 	u16 ioc_status;
2941 
2942 	mpt3sas_config_get_number_hba_phys(ioc, &num_phys);
2943 	if (!num_phys)
2944 		return;
2945 
2946 	sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys *
2947 	    sizeof(Mpi2SasIOUnit1PhyData_t));
2948 	sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL);
2949 	if (!sas_iounit_pg1) {
2950 		pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2951 		    ioc->name, __FILE__, __LINE__, __func__);
2952 		goto out;
2953 	}
2954 	if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
2955 	    sas_iounit_pg1, sz))) {
2956 		pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2957 		    ioc->name, __FILE__, __LINE__, __func__);
2958 		goto out;
2959 	}
2960 	ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
2961 	    MPI2_IOCSTATUS_MASK;
2962 	if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
2963 		pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2964 		    ioc->name, __FILE__, __LINE__, __func__);
2965 		goto out;
2966 	}
2967 
2968 	/* device missing delay */
2969 	dmd = sas_iounit_pg1->ReportDeviceMissingDelay;
2970 	if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
2971 		dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
2972 	else
2973 		dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
2974 	dmd_orignal = dmd;
2975 	if (device_missing_delay > 0x7F) {
2976 		dmd = (device_missing_delay > 0x7F0) ? 0x7F0 :
2977 		    device_missing_delay;
2978 		dmd = dmd / 16;
2979 		dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16;
2980 	} else
2981 		dmd = device_missing_delay;
2982 	sas_iounit_pg1->ReportDeviceMissingDelay = dmd;
2983 
2984 	/* io missing delay */
2985 	io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay;
2986 	sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay;
2987 
2988 	if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1,
2989 	    sz)) {
2990 		if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
2991 			dmd_new = (dmd &
2992 			    MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
2993 		else
2994 			dmd_new =
2995 		    dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
2996 		pr_info(MPT3SAS_FMT "device_missing_delay: old(%d), new(%d)\n",
2997 			ioc->name, dmd_orignal, dmd_new);
2998 		pr_info(MPT3SAS_FMT "ioc_missing_delay: old(%d), new(%d)\n",
2999 			ioc->name, io_missing_delay_original,
3000 		    io_missing_delay);
3001 		ioc->device_missing_delay = dmd_new;
3002 		ioc->io_missing_delay = io_missing_delay;
3003 	}
3004 
3005 out:
3006 	kfree(sas_iounit_pg1);
3007 }
3008 /**
3009  * _base_static_config_pages - static start of day config pages
3010  * @ioc: per adapter object
3011  *
3012  * Return nothing.
3013  */
3014 static void
3015 _base_static_config_pages(struct MPT3SAS_ADAPTER *ioc)
3016 {
3017 	Mpi2ConfigReply_t mpi_reply;
3018 	u32 iounit_pg1_flags;
3019 
3020 	mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0);
3021 	if (ioc->ir_firmware)
3022 		mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
3023 		    &ioc->manu_pg10);
3024 
3025 	/*
3026 	 * Ensure correct T10 PI operation if vendor left EEDPTagMode
3027 	 * flag unset in NVDATA.
3028 	 */
3029 	mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply, &ioc->manu_pg11);
3030 	if (ioc->manu_pg11.EEDPTagMode == 0) {
3031 		pr_err("%s: overriding NVDATA EEDPTagMode setting\n",
3032 		    ioc->name);
3033 		ioc->manu_pg11.EEDPTagMode &= ~0x3;
3034 		ioc->manu_pg11.EEDPTagMode |= 0x1;
3035 		mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply,
3036 		    &ioc->manu_pg11);
3037 	}
3038 
3039 	mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
3040 	mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
3041 	mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
3042 	mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0);
3043 	mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
3044 	mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8);
3045 	_base_display_ioc_capabilities(ioc);
3046 
3047 	/*
3048 	 * Enable task_set_full handling in iounit_pg1 when the
3049 	 * facts capabilities indicate that its supported.
3050 	 */
3051 	iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
3052 	if ((ioc->facts.IOCCapabilities &
3053 	    MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING))
3054 		iounit_pg1_flags &=
3055 		    ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
3056 	else
3057 		iounit_pg1_flags |=
3058 		    MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
3059 	ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags);
3060 	mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
3061 
3062 	if (ioc->iounit_pg8.NumSensors)
3063 		ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors;
3064 }
3065 
3066 /**
3067  * _base_release_memory_pools - release memory
3068  * @ioc: per adapter object
3069  *
3070  * Free memory allocated from _base_allocate_memory_pools.
3071  *
3072  * Return nothing.
3073  */
3074 static void
3075 _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
3076 {
3077 	int i = 0;
3078 	struct reply_post_struct *rps;
3079 
3080 	dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3081 	    __func__));
3082 
3083 	if (ioc->request) {
3084 		pci_free_consistent(ioc->pdev, ioc->request_dma_sz,
3085 		    ioc->request,  ioc->request_dma);
3086 		dexitprintk(ioc, pr_info(MPT3SAS_FMT
3087 			"request_pool(0x%p): free\n",
3088 			ioc->name, ioc->request));
3089 		ioc->request = NULL;
3090 	}
3091 
3092 	if (ioc->sense) {
3093 		pci_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
3094 		if (ioc->sense_dma_pool)
3095 			pci_pool_destroy(ioc->sense_dma_pool);
3096 		dexitprintk(ioc, pr_info(MPT3SAS_FMT
3097 			"sense_pool(0x%p): free\n",
3098 			ioc->name, ioc->sense));
3099 		ioc->sense = NULL;
3100 	}
3101 
3102 	if (ioc->reply) {
3103 		pci_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
3104 		if (ioc->reply_dma_pool)
3105 			pci_pool_destroy(ioc->reply_dma_pool);
3106 		dexitprintk(ioc, pr_info(MPT3SAS_FMT
3107 			"reply_pool(0x%p): free\n",
3108 			ioc->name, ioc->reply));
3109 		ioc->reply = NULL;
3110 	}
3111 
3112 	if (ioc->reply_free) {
3113 		pci_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
3114 		    ioc->reply_free_dma);
3115 		if (ioc->reply_free_dma_pool)
3116 			pci_pool_destroy(ioc->reply_free_dma_pool);
3117 		dexitprintk(ioc, pr_info(MPT3SAS_FMT
3118 			"reply_free_pool(0x%p): free\n",
3119 			ioc->name, ioc->reply_free));
3120 		ioc->reply_free = NULL;
3121 	}
3122 
3123 	if (ioc->reply_post) {
3124 		do {
3125 			rps = &ioc->reply_post[i];
3126 			if (rps->reply_post_free) {
3127 				pci_pool_free(
3128 				    ioc->reply_post_free_dma_pool,
3129 				    rps->reply_post_free,
3130 				    rps->reply_post_free_dma);
3131 				dexitprintk(ioc, pr_info(MPT3SAS_FMT
3132 				    "reply_post_free_pool(0x%p): free\n",
3133 				    ioc->name, rps->reply_post_free));
3134 				rps->reply_post_free = NULL;
3135 			}
3136 		} while (ioc->rdpq_array_enable &&
3137 			   (++i < ioc->reply_queue_count));
3138 
3139 		if (ioc->reply_post_free_dma_pool)
3140 			pci_pool_destroy(ioc->reply_post_free_dma_pool);
3141 		kfree(ioc->reply_post);
3142 	}
3143 
3144 	if (ioc->config_page) {
3145 		dexitprintk(ioc, pr_info(MPT3SAS_FMT
3146 		    "config_page(0x%p): free\n", ioc->name,
3147 		    ioc->config_page));
3148 		pci_free_consistent(ioc->pdev, ioc->config_page_sz,
3149 		    ioc->config_page, ioc->config_page_dma);
3150 	}
3151 
3152 	if (ioc->scsi_lookup) {
3153 		free_pages((ulong)ioc->scsi_lookup, ioc->scsi_lookup_pages);
3154 		ioc->scsi_lookup = NULL;
3155 	}
3156 	kfree(ioc->hpr_lookup);
3157 	kfree(ioc->internal_lookup);
3158 	if (ioc->chain_lookup) {
3159 		for (i = 0; i < ioc->chain_depth; i++) {
3160 			if (ioc->chain_lookup[i].chain_buffer)
3161 				pci_pool_free(ioc->chain_dma_pool,
3162 				    ioc->chain_lookup[i].chain_buffer,
3163 				    ioc->chain_lookup[i].chain_buffer_dma);
3164 		}
3165 		if (ioc->chain_dma_pool)
3166 			pci_pool_destroy(ioc->chain_dma_pool);
3167 		free_pages((ulong)ioc->chain_lookup, ioc->chain_pages);
3168 		ioc->chain_lookup = NULL;
3169 	}
3170 }
3171 
3172 /**
3173  * _base_allocate_memory_pools - allocate start of day memory pools
3174  * @ioc: per adapter object
3175  * @sleep_flag: CAN_SLEEP or NO_SLEEP
3176  *
3177  * Returns 0 success, anything else error
3178  */
3179 static int
3180 _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc,  int sleep_flag)
3181 {
3182 	struct mpt3sas_facts *facts;
3183 	u16 max_sge_elements;
3184 	u16 chains_needed_per_io;
3185 	u32 sz, total_sz, reply_post_free_sz;
3186 	u32 retry_sz;
3187 	u16 max_request_credit;
3188 	unsigned short sg_tablesize;
3189 	u16 sge_size;
3190 	int i;
3191 
3192 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3193 	    __func__));
3194 
3195 
3196 	retry_sz = 0;
3197 	facts = &ioc->facts;
3198 
3199 	/* command line tunables for max sgl entries */
3200 	if (max_sgl_entries != -1)
3201 		sg_tablesize = max_sgl_entries;
3202 	else {
3203 		if (ioc->hba_mpi_version_belonged == MPI2_VERSION)
3204 			sg_tablesize = MPT2SAS_SG_DEPTH;
3205 		else
3206 			sg_tablesize = MPT3SAS_SG_DEPTH;
3207 	}
3208 
3209 	if (sg_tablesize < MPT_MIN_PHYS_SEGMENTS)
3210 		sg_tablesize = MPT_MIN_PHYS_SEGMENTS;
3211 	else if (sg_tablesize > MPT_MAX_PHYS_SEGMENTS) {
3212 		sg_tablesize = min_t(unsigned short, sg_tablesize,
3213 				      SG_MAX_SEGMENTS);
3214 		pr_warn(MPT3SAS_FMT
3215 		 "sg_tablesize(%u) is bigger than kernel"
3216 		 " defined SG_CHUNK_SIZE(%u)\n", ioc->name,
3217 		 sg_tablesize, MPT_MAX_PHYS_SEGMENTS);
3218 	}
3219 	ioc->shost->sg_tablesize = sg_tablesize;
3220 
3221 	ioc->internal_depth = min_t(int, (facts->HighPriorityCredit + (5)),
3222 		(facts->RequestCredit / 4));
3223 	if (ioc->internal_depth < INTERNAL_CMDS_COUNT) {
3224 		if (facts->RequestCredit <= (INTERNAL_CMDS_COUNT +
3225 				INTERNAL_SCSIIO_CMDS_COUNT)) {
3226 			pr_err(MPT3SAS_FMT "IOC doesn't have enough Request \
3227 			    Credits, it has just %d number of credits\n",
3228 			    ioc->name, facts->RequestCredit);
3229 			return -ENOMEM;
3230 		}
3231 		ioc->internal_depth = 10;
3232 	}
3233 
3234 	ioc->hi_priority_depth = ioc->internal_depth - (5);
3235 	/* command line tunables  for max controller queue depth */
3236 	if (max_queue_depth != -1 && max_queue_depth != 0) {
3237 		max_request_credit = min_t(u16, max_queue_depth +
3238 			ioc->internal_depth, facts->RequestCredit);
3239 		if (max_request_credit > MAX_HBA_QUEUE_DEPTH)
3240 			max_request_credit =  MAX_HBA_QUEUE_DEPTH;
3241 	} else
3242 		max_request_credit = min_t(u16, facts->RequestCredit,
3243 		    MAX_HBA_QUEUE_DEPTH);
3244 
3245 	/* Firmware maintains additional facts->HighPriorityCredit number of
3246 	 * credits for HiPriprity Request messages, so hba queue depth will be
3247 	 * sum of max_request_credit and high priority queue depth.
3248 	 */
3249 	ioc->hba_queue_depth = max_request_credit + ioc->hi_priority_depth;
3250 
3251 	/* request frame size */
3252 	ioc->request_sz = facts->IOCRequestFrameSize * 4;
3253 
3254 	/* reply frame size */
3255 	ioc->reply_sz = facts->ReplyFrameSize * 4;
3256 
3257 	/* chain segment size */
3258 	if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
3259 		if (facts->IOCMaxChainSegmentSize)
3260 			ioc->chain_segment_sz =
3261 					facts->IOCMaxChainSegmentSize *
3262 					MAX_CHAIN_ELEMT_SZ;
3263 		else
3264 		/* set to 128 bytes size if IOCMaxChainSegmentSize is zero */
3265 			ioc->chain_segment_sz = DEFAULT_NUM_FWCHAIN_ELEMTS *
3266 						    MAX_CHAIN_ELEMT_SZ;
3267 	} else
3268 		ioc->chain_segment_sz = ioc->request_sz;
3269 
3270 	/* calculate the max scatter element size */
3271 	sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee);
3272 
3273  retry_allocation:
3274 	total_sz = 0;
3275 	/* calculate number of sg elements left over in the 1st frame */
3276 	max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) -
3277 	    sizeof(Mpi2SGEIOUnion_t)) + sge_size);
3278 	ioc->max_sges_in_main_message = max_sge_elements/sge_size;
3279 
3280 	/* now do the same for a chain buffer */
3281 	max_sge_elements = ioc->chain_segment_sz - sge_size;
3282 	ioc->max_sges_in_chain_message = max_sge_elements/sge_size;
3283 
3284 	/*
3285 	 *  MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE
3286 	 */
3287 	chains_needed_per_io = ((ioc->shost->sg_tablesize -
3288 	   ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message)
3289 	    + 1;
3290 	if (chains_needed_per_io > facts->MaxChainDepth) {
3291 		chains_needed_per_io = facts->MaxChainDepth;
3292 		ioc->shost->sg_tablesize = min_t(u16,
3293 		ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message
3294 		* chains_needed_per_io), ioc->shost->sg_tablesize);
3295 	}
3296 	ioc->chains_needed_per_io = chains_needed_per_io;
3297 
3298 	/* reply free queue sizing - taking into account for 64 FW events */
3299 	ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
3300 
3301 	/* calculate reply descriptor post queue depth */
3302 	ioc->reply_post_queue_depth = ioc->hba_queue_depth +
3303 				ioc->reply_free_queue_depth +  1 ;
3304 	/* align the reply post queue on the next 16 count boundary */
3305 	if (ioc->reply_post_queue_depth % 16)
3306 		ioc->reply_post_queue_depth += 16 -
3307 		(ioc->reply_post_queue_depth % 16);
3308 
3309 	if (ioc->reply_post_queue_depth >
3310 	    facts->MaxReplyDescriptorPostQueueDepth) {
3311 		ioc->reply_post_queue_depth =
3312 				facts->MaxReplyDescriptorPostQueueDepth -
3313 		    (facts->MaxReplyDescriptorPostQueueDepth % 16);
3314 		ioc->hba_queue_depth =
3315 				((ioc->reply_post_queue_depth - 64) / 2) - 1;
3316 		ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
3317 	}
3318 
3319 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "scatter gather: " \
3320 	    "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), "
3321 	    "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message,
3322 	    ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize,
3323 	    ioc->chains_needed_per_io));
3324 
3325 	/* reply post queue, 16 byte align */
3326 	reply_post_free_sz = ioc->reply_post_queue_depth *
3327 	    sizeof(Mpi2DefaultReplyDescriptor_t);
3328 
3329 	sz = reply_post_free_sz;
3330 	if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable)
3331 		sz *= ioc->reply_queue_count;
3332 
3333 	ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ?
3334 	    (ioc->reply_queue_count):1,
3335 	    sizeof(struct reply_post_struct), GFP_KERNEL);
3336 
3337 	if (!ioc->reply_post) {
3338 		pr_err(MPT3SAS_FMT "reply_post_free pool: kcalloc failed\n",
3339 			ioc->name);
3340 		goto out;
3341 	}
3342 	ioc->reply_post_free_dma_pool = pci_pool_create("reply_post_free pool",
3343 	    ioc->pdev, sz, 16, 0);
3344 	if (!ioc->reply_post_free_dma_pool) {
3345 		pr_err(MPT3SAS_FMT
3346 		 "reply_post_free pool: pci_pool_create failed\n",
3347 		 ioc->name);
3348 		goto out;
3349 	}
3350 	i = 0;
3351 	do {
3352 		ioc->reply_post[i].reply_post_free =
3353 		    pci_pool_alloc(ioc->reply_post_free_dma_pool,
3354 		    GFP_KERNEL,
3355 		    &ioc->reply_post[i].reply_post_free_dma);
3356 		if (!ioc->reply_post[i].reply_post_free) {
3357 			pr_err(MPT3SAS_FMT
3358 			"reply_post_free pool: pci_pool_alloc failed\n",
3359 			ioc->name);
3360 			goto out;
3361 		}
3362 		memset(ioc->reply_post[i].reply_post_free, 0, sz);
3363 		dinitprintk(ioc, pr_info(MPT3SAS_FMT
3364 		    "reply post free pool (0x%p): depth(%d),"
3365 		    "element_size(%d), pool_size(%d kB)\n", ioc->name,
3366 		    ioc->reply_post[i].reply_post_free,
3367 		    ioc->reply_post_queue_depth, 8, sz/1024));
3368 		dinitprintk(ioc, pr_info(MPT3SAS_FMT
3369 		    "reply_post_free_dma = (0x%llx)\n", ioc->name,
3370 		    (unsigned long long)
3371 		    ioc->reply_post[i].reply_post_free_dma));
3372 		total_sz += sz;
3373 	} while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count));
3374 
3375 	if (ioc->dma_mask == 64) {
3376 		if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) {
3377 			pr_warn(MPT3SAS_FMT
3378 			    "no suitable consistent DMA mask for %s\n",
3379 			    ioc->name, pci_name(ioc->pdev));
3380 			goto out;
3381 		}
3382 	}
3383 
3384 	ioc->scsiio_depth = ioc->hba_queue_depth -
3385 	    ioc->hi_priority_depth - ioc->internal_depth;
3386 
3387 	/* set the scsi host can_queue depth
3388 	 * with some internal commands that could be outstanding
3389 	 */
3390 	ioc->shost->can_queue = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT;
3391 	dinitprintk(ioc, pr_info(MPT3SAS_FMT
3392 		"scsi host: can_queue depth (%d)\n",
3393 		ioc->name, ioc->shost->can_queue));
3394 
3395 
3396 	/* contiguous pool for request and chains, 16 byte align, one extra "
3397 	 * "frame for smid=0
3398 	 */
3399 	ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth;
3400 	sz = ((ioc->scsiio_depth + 1) * ioc->request_sz);
3401 
3402 	/* hi-priority queue */
3403 	sz += (ioc->hi_priority_depth * ioc->request_sz);
3404 
3405 	/* internal queue */
3406 	sz += (ioc->internal_depth * ioc->request_sz);
3407 
3408 	ioc->request_dma_sz = sz;
3409 	ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma);
3410 	if (!ioc->request) {
3411 		pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
3412 		    "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
3413 		    "total(%d kB)\n", ioc->name, ioc->hba_queue_depth,
3414 		    ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
3415 		if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH)
3416 			goto out;
3417 		retry_sz = 64;
3418 		ioc->hba_queue_depth -= retry_sz;
3419 		_base_release_memory_pools(ioc);
3420 		goto retry_allocation;
3421 	}
3422 
3423 	if (retry_sz)
3424 		pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
3425 		    "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
3426 		    "total(%d kb)\n", ioc->name, ioc->hba_queue_depth,
3427 		    ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
3428 
3429 	/* hi-priority queue */
3430 	ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
3431 	    ioc->request_sz);
3432 	ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) *
3433 	    ioc->request_sz);
3434 
3435 	/* internal queue */
3436 	ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth *
3437 	    ioc->request_sz);
3438 	ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
3439 	    ioc->request_sz);
3440 
3441 	dinitprintk(ioc, pr_info(MPT3SAS_FMT
3442 		"request pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
3443 		ioc->name, ioc->request, ioc->hba_queue_depth, ioc->request_sz,
3444 	    (ioc->hba_queue_depth * ioc->request_sz)/1024));
3445 
3446 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "request pool: dma(0x%llx)\n",
3447 	    ioc->name, (unsigned long long) ioc->request_dma));
3448 	total_sz += sz;
3449 
3450 	sz = ioc->scsiio_depth * sizeof(struct scsiio_tracker);
3451 	ioc->scsi_lookup_pages = get_order(sz);
3452 	ioc->scsi_lookup = (struct scsiio_tracker *)__get_free_pages(
3453 	    GFP_KERNEL, ioc->scsi_lookup_pages);
3454 	if (!ioc->scsi_lookup) {
3455 		pr_err(MPT3SAS_FMT "scsi_lookup: get_free_pages failed, sz(%d)\n",
3456 			ioc->name, (int)sz);
3457 		goto out;
3458 	}
3459 
3460 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "scsiio(0x%p): depth(%d)\n",
3461 		ioc->name, ioc->request, ioc->scsiio_depth));
3462 
3463 	ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH);
3464 	sz = ioc->chain_depth * sizeof(struct chain_tracker);
3465 	ioc->chain_pages = get_order(sz);
3466 	ioc->chain_lookup = (struct chain_tracker *)__get_free_pages(
3467 	    GFP_KERNEL, ioc->chain_pages);
3468 	if (!ioc->chain_lookup) {
3469 		pr_err(MPT3SAS_FMT "chain_lookup: __get_free_pages failed\n",
3470 			ioc->name);
3471 		goto out;
3472 	}
3473 	ioc->chain_dma_pool = pci_pool_create("chain pool", ioc->pdev,
3474 	    ioc->chain_segment_sz, 16, 0);
3475 	if (!ioc->chain_dma_pool) {
3476 		pr_err(MPT3SAS_FMT "chain_dma_pool: pci_pool_create failed\n",
3477 			ioc->name);
3478 		goto out;
3479 	}
3480 	for (i = 0; i < ioc->chain_depth; i++) {
3481 		ioc->chain_lookup[i].chain_buffer = pci_pool_alloc(
3482 		    ioc->chain_dma_pool , GFP_KERNEL,
3483 		    &ioc->chain_lookup[i].chain_buffer_dma);
3484 		if (!ioc->chain_lookup[i].chain_buffer) {
3485 			ioc->chain_depth = i;
3486 			goto chain_done;
3487 		}
3488 		total_sz += ioc->chain_segment_sz;
3489 	}
3490  chain_done:
3491 	dinitprintk(ioc, pr_info(MPT3SAS_FMT
3492 		"chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n",
3493 		ioc->name, ioc->chain_depth, ioc->chain_segment_sz,
3494 		((ioc->chain_depth *  ioc->chain_segment_sz))/1024));
3495 
3496 	/* initialize hi-priority queue smid's */
3497 	ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
3498 	    sizeof(struct request_tracker), GFP_KERNEL);
3499 	if (!ioc->hpr_lookup) {
3500 		pr_err(MPT3SAS_FMT "hpr_lookup: kcalloc failed\n",
3501 		    ioc->name);
3502 		goto out;
3503 	}
3504 	ioc->hi_priority_smid = ioc->scsiio_depth + 1;
3505 	dinitprintk(ioc, pr_info(MPT3SAS_FMT
3506 		"hi_priority(0x%p): depth(%d), start smid(%d)\n",
3507 		ioc->name, ioc->hi_priority,
3508 	    ioc->hi_priority_depth, ioc->hi_priority_smid));
3509 
3510 	/* initialize internal queue smid's */
3511 	ioc->internal_lookup = kcalloc(ioc->internal_depth,
3512 	    sizeof(struct request_tracker), GFP_KERNEL);
3513 	if (!ioc->internal_lookup) {
3514 		pr_err(MPT3SAS_FMT "internal_lookup: kcalloc failed\n",
3515 		    ioc->name);
3516 		goto out;
3517 	}
3518 	ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
3519 	dinitprintk(ioc, pr_info(MPT3SAS_FMT
3520 		"internal(0x%p): depth(%d), start smid(%d)\n",
3521 		ioc->name, ioc->internal,
3522 	    ioc->internal_depth, ioc->internal_smid));
3523 
3524 	/* sense buffers, 4 byte align */
3525 	sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
3526 	ioc->sense_dma_pool = pci_pool_create("sense pool", ioc->pdev, sz, 4,
3527 	    0);
3528 	if (!ioc->sense_dma_pool) {
3529 		pr_err(MPT3SAS_FMT "sense pool: pci_pool_create failed\n",
3530 		    ioc->name);
3531 		goto out;
3532 	}
3533 	ioc->sense = pci_pool_alloc(ioc->sense_dma_pool , GFP_KERNEL,
3534 	    &ioc->sense_dma);
3535 	if (!ioc->sense) {
3536 		pr_err(MPT3SAS_FMT "sense pool: pci_pool_alloc failed\n",
3537 		    ioc->name);
3538 		goto out;
3539 	}
3540 	dinitprintk(ioc, pr_info(MPT3SAS_FMT
3541 	    "sense pool(0x%p): depth(%d), element_size(%d), pool_size"
3542 	    "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth,
3543 	    SCSI_SENSE_BUFFERSIZE, sz/1024));
3544 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "sense_dma(0x%llx)\n",
3545 	    ioc->name, (unsigned long long)ioc->sense_dma));
3546 	total_sz += sz;
3547 
3548 	/* reply pool, 4 byte align */
3549 	sz = ioc->reply_free_queue_depth * ioc->reply_sz;
3550 	ioc->reply_dma_pool = pci_pool_create("reply pool", ioc->pdev, sz, 4,
3551 	    0);
3552 	if (!ioc->reply_dma_pool) {
3553 		pr_err(MPT3SAS_FMT "reply pool: pci_pool_create failed\n",
3554 		    ioc->name);
3555 		goto out;
3556 	}
3557 	ioc->reply = pci_pool_alloc(ioc->reply_dma_pool , GFP_KERNEL,
3558 	    &ioc->reply_dma);
3559 	if (!ioc->reply) {
3560 		pr_err(MPT3SAS_FMT "reply pool: pci_pool_alloc failed\n",
3561 		    ioc->name);
3562 		goto out;
3563 	}
3564 	ioc->reply_dma_min_address = (u32)(ioc->reply_dma);
3565 	ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz;
3566 	dinitprintk(ioc, pr_info(MPT3SAS_FMT
3567 		"reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
3568 		ioc->name, ioc->reply,
3569 	    ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024));
3570 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_dma(0x%llx)\n",
3571 	    ioc->name, (unsigned long long)ioc->reply_dma));
3572 	total_sz += sz;
3573 
3574 	/* reply free queue, 16 byte align */
3575 	sz = ioc->reply_free_queue_depth * 4;
3576 	ioc->reply_free_dma_pool = pci_pool_create("reply_free pool",
3577 	    ioc->pdev, sz, 16, 0);
3578 	if (!ioc->reply_free_dma_pool) {
3579 		pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_create failed\n",
3580 			ioc->name);
3581 		goto out;
3582 	}
3583 	ioc->reply_free = pci_pool_alloc(ioc->reply_free_dma_pool , GFP_KERNEL,
3584 	    &ioc->reply_free_dma);
3585 	if (!ioc->reply_free) {
3586 		pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_alloc failed\n",
3587 			ioc->name);
3588 		goto out;
3589 	}
3590 	memset(ioc->reply_free, 0, sz);
3591 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_free pool(0x%p): " \
3592 	    "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name,
3593 	    ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024));
3594 	dinitprintk(ioc, pr_info(MPT3SAS_FMT
3595 		"reply_free_dma (0x%llx)\n",
3596 		ioc->name, (unsigned long long)ioc->reply_free_dma));
3597 	total_sz += sz;
3598 
3599 	ioc->config_page_sz = 512;
3600 	ioc->config_page = pci_alloc_consistent(ioc->pdev,
3601 	    ioc->config_page_sz, &ioc->config_page_dma);
3602 	if (!ioc->config_page) {
3603 		pr_err(MPT3SAS_FMT
3604 			"config page: pci_pool_alloc failed\n",
3605 			ioc->name);
3606 		goto out;
3607 	}
3608 	dinitprintk(ioc, pr_info(MPT3SAS_FMT
3609 		"config page(0x%p): size(%d)\n",
3610 		ioc->name, ioc->config_page, ioc->config_page_sz));
3611 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "config_page_dma(0x%llx)\n",
3612 		ioc->name, (unsigned long long)ioc->config_page_dma));
3613 	total_sz += ioc->config_page_sz;
3614 
3615 	pr_info(MPT3SAS_FMT "Allocated physical memory: size(%d kB)\n",
3616 	    ioc->name, total_sz/1024);
3617 	pr_info(MPT3SAS_FMT
3618 		"Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n",
3619 	    ioc->name, ioc->shost->can_queue, facts->RequestCredit);
3620 	pr_info(MPT3SAS_FMT "Scatter Gather Elements per IO(%d)\n",
3621 	    ioc->name, ioc->shost->sg_tablesize);
3622 	return 0;
3623 
3624  out:
3625 	return -ENOMEM;
3626 }
3627 
3628 /**
3629  * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter.
3630  * @ioc: Pointer to MPT_ADAPTER structure
3631  * @cooked: Request raw or cooked IOC state
3632  *
3633  * Returns all IOC Doorbell register bits if cooked==0, else just the
3634  * Doorbell bits in MPI_IOC_STATE_MASK.
3635  */
3636 u32
3637 mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked)
3638 {
3639 	u32 s, sc;
3640 
3641 	s = readl(&ioc->chip->Doorbell);
3642 	sc = s & MPI2_IOC_STATE_MASK;
3643 	return cooked ? sc : s;
3644 }
3645 
3646 /**
3647  * _base_wait_on_iocstate - waiting on a particular ioc state
3648  * @ioc_state: controller state { READY, OPERATIONAL, or RESET }
3649  * @timeout: timeout in second
3650  * @sleep_flag: CAN_SLEEP or NO_SLEEP
3651  *
3652  * Returns 0 for success, non-zero for failure.
3653  */
3654 static int
3655 _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout,
3656 	int sleep_flag)
3657 {
3658 	u32 count, cntdn;
3659 	u32 current_state;
3660 
3661 	count = 0;
3662 	cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3663 	do {
3664 		current_state = mpt3sas_base_get_iocstate(ioc, 1);
3665 		if (current_state == ioc_state)
3666 			return 0;
3667 		if (count && current_state == MPI2_IOC_STATE_FAULT)
3668 			break;
3669 		if (sleep_flag == CAN_SLEEP)
3670 			usleep_range(1000, 1500);
3671 		else
3672 			udelay(500);
3673 		count++;
3674 	} while (--cntdn);
3675 
3676 	return current_state;
3677 }
3678 
3679 /**
3680  * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
3681  * a write to the doorbell)
3682  * @ioc: per adapter object
3683  * @timeout: timeout in second
3684  * @sleep_flag: CAN_SLEEP or NO_SLEEP
3685  *
3686  * Returns 0 for success, non-zero for failure.
3687  *
3688  * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
3689  */
3690 static int
3691 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc, int sleep_flag);
3692 
3693 static int
3694 _base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout,
3695 	int sleep_flag)
3696 {
3697 	u32 cntdn, count;
3698 	u32 int_status;
3699 
3700 	count = 0;
3701 	cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3702 	do {
3703 		int_status = readl(&ioc->chip->HostInterruptStatus);
3704 		if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3705 			dhsprintk(ioc, pr_info(MPT3SAS_FMT
3706 				"%s: successful count(%d), timeout(%d)\n",
3707 				ioc->name, __func__, count, timeout));
3708 			return 0;
3709 		}
3710 		if (sleep_flag == CAN_SLEEP)
3711 			usleep_range(1000, 1500);
3712 		else
3713 			udelay(500);
3714 		count++;
3715 	} while (--cntdn);
3716 
3717 	pr_err(MPT3SAS_FMT
3718 		"%s: failed due to timeout count(%d), int_status(%x)!\n",
3719 		ioc->name, __func__, count, int_status);
3720 	return -EFAULT;
3721 }
3722 
3723 /**
3724  * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell.
3725  * @ioc: per adapter object
3726  * @timeout: timeout in second
3727  * @sleep_flag: CAN_SLEEP or NO_SLEEP
3728  *
3729  * Returns 0 for success, non-zero for failure.
3730  *
3731  * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to
3732  * doorbell.
3733  */
3734 static int
3735 _base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout,
3736 	int sleep_flag)
3737 {
3738 	u32 cntdn, count;
3739 	u32 int_status;
3740 	u32 doorbell;
3741 
3742 	count = 0;
3743 	cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3744 	do {
3745 		int_status = readl(&ioc->chip->HostInterruptStatus);
3746 		if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
3747 			dhsprintk(ioc, pr_info(MPT3SAS_FMT
3748 				"%s: successful count(%d), timeout(%d)\n",
3749 				ioc->name, __func__, count, timeout));
3750 			return 0;
3751 		} else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3752 			doorbell = readl(&ioc->chip->Doorbell);
3753 			if ((doorbell & MPI2_IOC_STATE_MASK) ==
3754 			    MPI2_IOC_STATE_FAULT) {
3755 				mpt3sas_base_fault_info(ioc , doorbell);
3756 				return -EFAULT;
3757 			}
3758 		} else if (int_status == 0xFFFFFFFF)
3759 			goto out;
3760 
3761 		if (sleep_flag == CAN_SLEEP)
3762 			usleep_range(1000, 1500);
3763 		else
3764 			udelay(500);
3765 		count++;
3766 	} while (--cntdn);
3767 
3768  out:
3769 	pr_err(MPT3SAS_FMT
3770 	 "%s: failed due to timeout count(%d), int_status(%x)!\n",
3771 	 ioc->name, __func__, count, int_status);
3772 	return -EFAULT;
3773 }
3774 
3775 /**
3776  * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use
3777  * @ioc: per adapter object
3778  * @timeout: timeout in second
3779  * @sleep_flag: CAN_SLEEP or NO_SLEEP
3780  *
3781  * Returns 0 for success, non-zero for failure.
3782  *
3783  */
3784 static int
3785 _base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout,
3786 	int sleep_flag)
3787 {
3788 	u32 cntdn, count;
3789 	u32 doorbell_reg;
3790 
3791 	count = 0;
3792 	cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3793 	do {
3794 		doorbell_reg = readl(&ioc->chip->Doorbell);
3795 		if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
3796 			dhsprintk(ioc, pr_info(MPT3SAS_FMT
3797 				"%s: successful count(%d), timeout(%d)\n",
3798 				ioc->name, __func__, count, timeout));
3799 			return 0;
3800 		}
3801 		if (sleep_flag == CAN_SLEEP)
3802 			usleep_range(1000, 1500);
3803 		else
3804 			udelay(500);
3805 		count++;
3806 	} while (--cntdn);
3807 
3808 	pr_err(MPT3SAS_FMT
3809 		"%s: failed due to timeout count(%d), doorbell_reg(%x)!\n",
3810 		ioc->name, __func__, count, doorbell_reg);
3811 	return -EFAULT;
3812 }
3813 
3814 /**
3815  * _base_send_ioc_reset - send doorbell reset
3816  * @ioc: per adapter object
3817  * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
3818  * @timeout: timeout in second
3819  * @sleep_flag: CAN_SLEEP or NO_SLEEP
3820  *
3821  * Returns 0 for success, non-zero for failure.
3822  */
3823 static int
3824 _base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout,
3825 	int sleep_flag)
3826 {
3827 	u32 ioc_state;
3828 	int r = 0;
3829 
3830 	if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
3831 		pr_err(MPT3SAS_FMT "%s: unknown reset_type\n",
3832 		    ioc->name, __func__);
3833 		return -EFAULT;
3834 	}
3835 
3836 	if (!(ioc->facts.IOCCapabilities &
3837 	   MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
3838 		return -EFAULT;
3839 
3840 	pr_info(MPT3SAS_FMT "sending message unit reset !!\n", ioc->name);
3841 
3842 	writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
3843 	    &ioc->chip->Doorbell);
3844 	if ((_base_wait_for_doorbell_ack(ioc, 15, sleep_flag))) {
3845 		r = -EFAULT;
3846 		goto out;
3847 	}
3848 	ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY,
3849 	    timeout, sleep_flag);
3850 	if (ioc_state) {
3851 		pr_err(MPT3SAS_FMT
3852 			"%s: failed going to ready state (ioc_state=0x%x)\n",
3853 			ioc->name, __func__, ioc_state);
3854 		r = -EFAULT;
3855 		goto out;
3856 	}
3857  out:
3858 	pr_info(MPT3SAS_FMT "message unit reset: %s\n",
3859 	    ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
3860 	return r;
3861 }
3862 
3863 /**
3864  * _base_handshake_req_reply_wait - send request thru doorbell interface
3865  * @ioc: per adapter object
3866  * @request_bytes: request length
3867  * @request: pointer having request payload
3868  * @reply_bytes: reply length
3869  * @reply: pointer to reply payload
3870  * @timeout: timeout in second
3871  * @sleep_flag: CAN_SLEEP or NO_SLEEP
3872  *
3873  * Returns 0 for success, non-zero for failure.
3874  */
3875 static int
3876 _base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes,
3877 	u32 *request, int reply_bytes, u16 *reply, int timeout, int sleep_flag)
3878 {
3879 	MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
3880 	int i;
3881 	u8 failed;
3882 	u16 dummy;
3883 	__le32 *mfp;
3884 
3885 	/* make sure doorbell is not in use */
3886 	if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
3887 		pr_err(MPT3SAS_FMT
3888 			"doorbell is in use (line=%d)\n",
3889 			ioc->name, __LINE__);
3890 		return -EFAULT;
3891 	}
3892 
3893 	/* clear pending doorbell interrupts from previous state changes */
3894 	if (readl(&ioc->chip->HostInterruptStatus) &
3895 	    MPI2_HIS_IOC2SYS_DB_STATUS)
3896 		writel(0, &ioc->chip->HostInterruptStatus);
3897 
3898 	/* send message to ioc */
3899 	writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
3900 	    ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)),
3901 	    &ioc->chip->Doorbell);
3902 
3903 	if ((_base_wait_for_doorbell_int(ioc, 5, NO_SLEEP))) {
3904 		pr_err(MPT3SAS_FMT
3905 			"doorbell handshake int failed (line=%d)\n",
3906 			ioc->name, __LINE__);
3907 		return -EFAULT;
3908 	}
3909 	writel(0, &ioc->chip->HostInterruptStatus);
3910 
3911 	if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag))) {
3912 		pr_err(MPT3SAS_FMT
3913 			"doorbell handshake ack failed (line=%d)\n",
3914 			ioc->name, __LINE__);
3915 		return -EFAULT;
3916 	}
3917 
3918 	/* send message 32-bits at a time */
3919 	for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) {
3920 		writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
3921 		if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag)))
3922 			failed = 1;
3923 	}
3924 
3925 	if (failed) {
3926 		pr_err(MPT3SAS_FMT
3927 			"doorbell handshake sending request failed (line=%d)\n",
3928 			ioc->name, __LINE__);
3929 		return -EFAULT;
3930 	}
3931 
3932 	/* now wait for the reply */
3933 	if ((_base_wait_for_doorbell_int(ioc, timeout, sleep_flag))) {
3934 		pr_err(MPT3SAS_FMT
3935 			"doorbell handshake int failed (line=%d)\n",
3936 			ioc->name, __LINE__);
3937 		return -EFAULT;
3938 	}
3939 
3940 	/* read the first two 16-bits, it gives the total length of the reply */
3941 	reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3942 	    & MPI2_DOORBELL_DATA_MASK);
3943 	writel(0, &ioc->chip->HostInterruptStatus);
3944 	if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
3945 		pr_err(MPT3SAS_FMT
3946 			"doorbell handshake int failed (line=%d)\n",
3947 			ioc->name, __LINE__);
3948 		return -EFAULT;
3949 	}
3950 	reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3951 	    & MPI2_DOORBELL_DATA_MASK);
3952 	writel(0, &ioc->chip->HostInterruptStatus);
3953 
3954 	for (i = 2; i < default_reply->MsgLength * 2; i++)  {
3955 		if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
3956 			pr_err(MPT3SAS_FMT
3957 				"doorbell handshake int failed (line=%d)\n",
3958 				ioc->name, __LINE__);
3959 			return -EFAULT;
3960 		}
3961 		if (i >=  reply_bytes/2) /* overflow case */
3962 			dummy = readl(&ioc->chip->Doorbell);
3963 		else
3964 			reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3965 			    & MPI2_DOORBELL_DATA_MASK);
3966 		writel(0, &ioc->chip->HostInterruptStatus);
3967 	}
3968 
3969 	_base_wait_for_doorbell_int(ioc, 5, sleep_flag);
3970 	if (_base_wait_for_doorbell_not_used(ioc, 5, sleep_flag) != 0) {
3971 		dhsprintk(ioc, pr_info(MPT3SAS_FMT
3972 			"doorbell is in use (line=%d)\n", ioc->name, __LINE__));
3973 	}
3974 	writel(0, &ioc->chip->HostInterruptStatus);
3975 
3976 	if (ioc->logging_level & MPT_DEBUG_INIT) {
3977 		mfp = (__le32 *)reply;
3978 		pr_info("\toffset:data\n");
3979 		for (i = 0; i < reply_bytes/4; i++)
3980 			pr_info("\t[0x%02x]:%08x\n", i*4,
3981 			    le32_to_cpu(mfp[i]));
3982 	}
3983 	return 0;
3984 }
3985 
3986 /**
3987  * mpt3sas_base_sas_iounit_control - send sas iounit control to FW
3988  * @ioc: per adapter object
3989  * @mpi_reply: the reply payload from FW
3990  * @mpi_request: the request payload sent to FW
3991  *
3992  * The SAS IO Unit Control Request message allows the host to perform low-level
3993  * operations, such as resets on the PHYs of the IO Unit, also allows the host
3994  * to obtain the IOC assigned device handles for a device if it has other
3995  * identifying information about the device, in addition allows the host to
3996  * remove IOC resources associated with the device.
3997  *
3998  * Returns 0 for success, non-zero for failure.
3999  */
4000 int
4001 mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc,
4002 	Mpi2SasIoUnitControlReply_t *mpi_reply,
4003 	Mpi2SasIoUnitControlRequest_t *mpi_request)
4004 {
4005 	u16 smid;
4006 	u32 ioc_state;
4007 	unsigned long timeleft;
4008 	bool issue_reset = false;
4009 	int rc;
4010 	void *request;
4011 	u16 wait_state_count;
4012 
4013 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4014 	    __func__));
4015 
4016 	mutex_lock(&ioc->base_cmds.mutex);
4017 
4018 	if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
4019 		pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
4020 		    ioc->name, __func__);
4021 		rc = -EAGAIN;
4022 		goto out;
4023 	}
4024 
4025 	wait_state_count = 0;
4026 	ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4027 	while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
4028 		if (wait_state_count++ == 10) {
4029 			pr_err(MPT3SAS_FMT
4030 			    "%s: failed due to ioc not operational\n",
4031 			    ioc->name, __func__);
4032 			rc = -EFAULT;
4033 			goto out;
4034 		}
4035 		ssleep(1);
4036 		ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4037 		pr_info(MPT3SAS_FMT
4038 			"%s: waiting for operational state(count=%d)\n",
4039 			ioc->name, __func__, wait_state_count);
4040 	}
4041 
4042 	smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4043 	if (!smid) {
4044 		pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4045 		    ioc->name, __func__);
4046 		rc = -EAGAIN;
4047 		goto out;
4048 	}
4049 
4050 	rc = 0;
4051 	ioc->base_cmds.status = MPT3_CMD_PENDING;
4052 	request = mpt3sas_base_get_msg_frame(ioc, smid);
4053 	ioc->base_cmds.smid = smid;
4054 	memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t));
4055 	if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
4056 	    mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
4057 		ioc->ioc_link_reset_in_progress = 1;
4058 	init_completion(&ioc->base_cmds.done);
4059 	mpt3sas_base_put_smid_default(ioc, smid);
4060 	timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
4061 	    msecs_to_jiffies(10000));
4062 	if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
4063 	    mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) &&
4064 	    ioc->ioc_link_reset_in_progress)
4065 		ioc->ioc_link_reset_in_progress = 0;
4066 	if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4067 		pr_err(MPT3SAS_FMT "%s: timeout\n",
4068 		    ioc->name, __func__);
4069 		_debug_dump_mf(mpi_request,
4070 		    sizeof(Mpi2SasIoUnitControlRequest_t)/4);
4071 		if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
4072 			issue_reset = true;
4073 		goto issue_host_reset;
4074 	}
4075 	if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
4076 		memcpy(mpi_reply, ioc->base_cmds.reply,
4077 		    sizeof(Mpi2SasIoUnitControlReply_t));
4078 	else
4079 		memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t));
4080 	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4081 	goto out;
4082 
4083  issue_host_reset:
4084 	if (issue_reset)
4085 		mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
4086 		    FORCE_BIG_HAMMER);
4087 	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4088 	rc = -EFAULT;
4089  out:
4090 	mutex_unlock(&ioc->base_cmds.mutex);
4091 	return rc;
4092 }
4093 
4094 /**
4095  * mpt3sas_base_scsi_enclosure_processor - sending request to sep device
4096  * @ioc: per adapter object
4097  * @mpi_reply: the reply payload from FW
4098  * @mpi_request: the request payload sent to FW
4099  *
4100  * The SCSI Enclosure Processor request message causes the IOC to
4101  * communicate with SES devices to control LED status signals.
4102  *
4103  * Returns 0 for success, non-zero for failure.
4104  */
4105 int
4106 mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc,
4107 	Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request)
4108 {
4109 	u16 smid;
4110 	u32 ioc_state;
4111 	unsigned long timeleft;
4112 	bool issue_reset = false;
4113 	int rc;
4114 	void *request;
4115 	u16 wait_state_count;
4116 
4117 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4118 	    __func__));
4119 
4120 	mutex_lock(&ioc->base_cmds.mutex);
4121 
4122 	if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
4123 		pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
4124 		    ioc->name, __func__);
4125 		rc = -EAGAIN;
4126 		goto out;
4127 	}
4128 
4129 	wait_state_count = 0;
4130 	ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4131 	while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
4132 		if (wait_state_count++ == 10) {
4133 			pr_err(MPT3SAS_FMT
4134 			    "%s: failed due to ioc not operational\n",
4135 			    ioc->name, __func__);
4136 			rc = -EFAULT;
4137 			goto out;
4138 		}
4139 		ssleep(1);
4140 		ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4141 		pr_info(MPT3SAS_FMT
4142 			"%s: waiting for operational state(count=%d)\n",
4143 			ioc->name,
4144 		    __func__, wait_state_count);
4145 	}
4146 
4147 	smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4148 	if (!smid) {
4149 		pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4150 		    ioc->name, __func__);
4151 		rc = -EAGAIN;
4152 		goto out;
4153 	}
4154 
4155 	rc = 0;
4156 	ioc->base_cmds.status = MPT3_CMD_PENDING;
4157 	request = mpt3sas_base_get_msg_frame(ioc, smid);
4158 	ioc->base_cmds.smid = smid;
4159 	memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
4160 	init_completion(&ioc->base_cmds.done);
4161 	mpt3sas_base_put_smid_default(ioc, smid);
4162 	timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
4163 	    msecs_to_jiffies(10000));
4164 	if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4165 		pr_err(MPT3SAS_FMT "%s: timeout\n",
4166 		    ioc->name, __func__);
4167 		_debug_dump_mf(mpi_request,
4168 		    sizeof(Mpi2SepRequest_t)/4);
4169 		if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
4170 			issue_reset = false;
4171 		goto issue_host_reset;
4172 	}
4173 	if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
4174 		memcpy(mpi_reply, ioc->base_cmds.reply,
4175 		    sizeof(Mpi2SepReply_t));
4176 	else
4177 		memset(mpi_reply, 0, sizeof(Mpi2SepReply_t));
4178 	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4179 	goto out;
4180 
4181  issue_host_reset:
4182 	if (issue_reset)
4183 		mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
4184 		    FORCE_BIG_HAMMER);
4185 	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4186 	rc = -EFAULT;
4187  out:
4188 	mutex_unlock(&ioc->base_cmds.mutex);
4189 	return rc;
4190 }
4191 
4192 /**
4193  * _base_get_port_facts - obtain port facts reply and save in ioc
4194  * @ioc: per adapter object
4195  * @sleep_flag: CAN_SLEEP or NO_SLEEP
4196  *
4197  * Returns 0 for success, non-zero for failure.
4198  */
4199 static int
4200 _base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port, int sleep_flag)
4201 {
4202 	Mpi2PortFactsRequest_t mpi_request;
4203 	Mpi2PortFactsReply_t mpi_reply;
4204 	struct mpt3sas_port_facts *pfacts;
4205 	int mpi_reply_sz, mpi_request_sz, r;
4206 
4207 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4208 	    __func__));
4209 
4210 	mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
4211 	mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
4212 	memset(&mpi_request, 0, mpi_request_sz);
4213 	mpi_request.Function = MPI2_FUNCTION_PORT_FACTS;
4214 	mpi_request.PortNumber = port;
4215 	r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
4216 	    (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
4217 
4218 	if (r != 0) {
4219 		pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
4220 		    ioc->name, __func__, r);
4221 		return r;
4222 	}
4223 
4224 	pfacts = &ioc->pfacts[port];
4225 	memset(pfacts, 0, sizeof(struct mpt3sas_port_facts));
4226 	pfacts->PortNumber = mpi_reply.PortNumber;
4227 	pfacts->VP_ID = mpi_reply.VP_ID;
4228 	pfacts->VF_ID = mpi_reply.VF_ID;
4229 	pfacts->MaxPostedCmdBuffers =
4230 	    le16_to_cpu(mpi_reply.MaxPostedCmdBuffers);
4231 
4232 	return 0;
4233 }
4234 
4235 /**
4236  * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL
4237  * @ioc: per adapter object
4238  * @timeout:
4239  * @sleep_flag: CAN_SLEEP or NO_SLEEP
4240  *
4241  * Returns 0 for success, non-zero for failure.
4242  */
4243 static int
4244 _base_wait_for_iocstate(struct MPT3SAS_ADAPTER *ioc, int timeout,
4245 	int sleep_flag)
4246 {
4247 	u32 ioc_state;
4248 	int rc;
4249 
4250 	dinitprintk(ioc, printk(MPT3SAS_FMT "%s\n", ioc->name,
4251 	    __func__));
4252 
4253 	if (ioc->pci_error_recovery) {
4254 		dfailprintk(ioc, printk(MPT3SAS_FMT
4255 		    "%s: host in pci error recovery\n", ioc->name, __func__));
4256 		return -EFAULT;
4257 	}
4258 
4259 	ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4260 	dhsprintk(ioc, printk(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
4261 	    ioc->name, __func__, ioc_state));
4262 
4263 	if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) ||
4264 	    (ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
4265 		return 0;
4266 
4267 	if (ioc_state & MPI2_DOORBELL_USED) {
4268 		dhsprintk(ioc, printk(MPT3SAS_FMT
4269 		    "unexpected doorbell active!\n", ioc->name));
4270 		goto issue_diag_reset;
4271 	}
4272 
4273 	if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
4274 		mpt3sas_base_fault_info(ioc, ioc_state &
4275 		    MPI2_DOORBELL_DATA_MASK);
4276 		goto issue_diag_reset;
4277 	}
4278 
4279 	ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY,
4280 	    timeout, sleep_flag);
4281 	if (ioc_state) {
4282 		dfailprintk(ioc, printk(MPT3SAS_FMT
4283 		    "%s: failed going to ready state (ioc_state=0x%x)\n",
4284 		    ioc->name, __func__, ioc_state));
4285 		return -EFAULT;
4286 	}
4287 
4288  issue_diag_reset:
4289 	rc = _base_diag_reset(ioc, sleep_flag);
4290 	return rc;
4291 }
4292 
4293 /**
4294  * _base_get_ioc_facts - obtain ioc facts reply and save in ioc
4295  * @ioc: per adapter object
4296  * @sleep_flag: CAN_SLEEP or NO_SLEEP
4297  *
4298  * Returns 0 for success, non-zero for failure.
4299  */
4300 static int
4301 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4302 {
4303 	Mpi2IOCFactsRequest_t mpi_request;
4304 	Mpi2IOCFactsReply_t mpi_reply;
4305 	struct mpt3sas_facts *facts;
4306 	int mpi_reply_sz, mpi_request_sz, r;
4307 
4308 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4309 	    __func__));
4310 
4311 	r = _base_wait_for_iocstate(ioc, 10, sleep_flag);
4312 	if (r) {
4313 		dfailprintk(ioc, printk(MPT3SAS_FMT
4314 		    "%s: failed getting to correct state\n",
4315 		    ioc->name, __func__));
4316 		return r;
4317 	}
4318 	mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
4319 	mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t);
4320 	memset(&mpi_request, 0, mpi_request_sz);
4321 	mpi_request.Function = MPI2_FUNCTION_IOC_FACTS;
4322 	r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
4323 	    (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
4324 
4325 	if (r != 0) {
4326 		pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
4327 		    ioc->name, __func__, r);
4328 		return r;
4329 	}
4330 
4331 	facts = &ioc->facts;
4332 	memset(facts, 0, sizeof(struct mpt3sas_facts));
4333 	facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion);
4334 	facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion);
4335 	facts->VP_ID = mpi_reply.VP_ID;
4336 	facts->VF_ID = mpi_reply.VF_ID;
4337 	facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions);
4338 	facts->MaxChainDepth = mpi_reply.MaxChainDepth;
4339 	facts->WhoInit = mpi_reply.WhoInit;
4340 	facts->NumberOfPorts = mpi_reply.NumberOfPorts;
4341 	facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors;
4342 	facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);
4343 	facts->MaxReplyDescriptorPostQueueDepth =
4344 	    le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);
4345 	facts->ProductID = le16_to_cpu(mpi_reply.ProductID);
4346 	facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities);
4347 	if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID))
4348 		ioc->ir_firmware = 1;
4349 	if ((facts->IOCCapabilities &
4350 	      MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE))
4351 		ioc->rdpq_array_capable = 1;
4352 	facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
4353 	facts->IOCRequestFrameSize =
4354 	    le16_to_cpu(mpi_reply.IOCRequestFrameSize);
4355 	if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
4356 		facts->IOCMaxChainSegmentSize =
4357 			le16_to_cpu(mpi_reply.IOCMaxChainSegmentSize);
4358 	}
4359 	facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators);
4360 	facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets);
4361 	ioc->shost->max_id = -1;
4362 	facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders);
4363 	facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures);
4364 	facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags);
4365 	facts->HighPriorityCredit =
4366 	    le16_to_cpu(mpi_reply.HighPriorityCredit);
4367 	facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
4368 	facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
4369 
4370 	dinitprintk(ioc, pr_info(MPT3SAS_FMT
4371 		"hba queue depth(%d), max chains per io(%d)\n",
4372 		ioc->name, facts->RequestCredit,
4373 	    facts->MaxChainDepth));
4374 	dinitprintk(ioc, pr_info(MPT3SAS_FMT
4375 		"request frame size(%d), reply frame size(%d)\n", ioc->name,
4376 	    facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4));
4377 	return 0;
4378 }
4379 
4380 /**
4381  * _base_send_ioc_init - send ioc_init to firmware
4382  * @ioc: per adapter object
4383  * @sleep_flag: CAN_SLEEP or NO_SLEEP
4384  *
4385  * Returns 0 for success, non-zero for failure.
4386  */
4387 static int
4388 _base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4389 {
4390 	Mpi2IOCInitRequest_t mpi_request;
4391 	Mpi2IOCInitReply_t mpi_reply;
4392 	int i, r = 0;
4393 	ktime_t current_time;
4394 	u16 ioc_status;
4395 	u32 reply_post_free_array_sz = 0;
4396 	Mpi2IOCInitRDPQArrayEntry *reply_post_free_array = NULL;
4397 	dma_addr_t reply_post_free_array_dma;
4398 
4399 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4400 	    __func__));
4401 
4402 	memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
4403 	mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
4404 	mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
4405 	mpi_request.VF_ID = 0; /* TODO */
4406 	mpi_request.VP_ID = 0;
4407 	mpi_request.MsgVersion = cpu_to_le16(ioc->hba_mpi_version_belonged);
4408 	mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
4409 
4410 	if (_base_is_controller_msix_enabled(ioc))
4411 		mpi_request.HostMSIxVectors = ioc->reply_queue_count;
4412 	mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4);
4413 	mpi_request.ReplyDescriptorPostQueueDepth =
4414 	    cpu_to_le16(ioc->reply_post_queue_depth);
4415 	mpi_request.ReplyFreeQueueDepth =
4416 	    cpu_to_le16(ioc->reply_free_queue_depth);
4417 
4418 	mpi_request.SenseBufferAddressHigh =
4419 	    cpu_to_le32((u64)ioc->sense_dma >> 32);
4420 	mpi_request.SystemReplyAddressHigh =
4421 	    cpu_to_le32((u64)ioc->reply_dma >> 32);
4422 	mpi_request.SystemRequestFrameBaseAddress =
4423 	    cpu_to_le64((u64)ioc->request_dma);
4424 	mpi_request.ReplyFreeQueueAddress =
4425 	    cpu_to_le64((u64)ioc->reply_free_dma);
4426 
4427 	if (ioc->rdpq_array_enable) {
4428 		reply_post_free_array_sz = ioc->reply_queue_count *
4429 		    sizeof(Mpi2IOCInitRDPQArrayEntry);
4430 		reply_post_free_array = pci_alloc_consistent(ioc->pdev,
4431 			reply_post_free_array_sz, &reply_post_free_array_dma);
4432 		if (!reply_post_free_array) {
4433 			pr_err(MPT3SAS_FMT
4434 			"reply_post_free_array: pci_alloc_consistent failed\n",
4435 			ioc->name);
4436 			r = -ENOMEM;
4437 			goto out;
4438 		}
4439 		memset(reply_post_free_array, 0, reply_post_free_array_sz);
4440 		for (i = 0; i < ioc->reply_queue_count; i++)
4441 			reply_post_free_array[i].RDPQBaseAddress =
4442 			    cpu_to_le64(
4443 				(u64)ioc->reply_post[i].reply_post_free_dma);
4444 		mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE;
4445 		mpi_request.ReplyDescriptorPostQueueAddress =
4446 		    cpu_to_le64((u64)reply_post_free_array_dma);
4447 	} else {
4448 		mpi_request.ReplyDescriptorPostQueueAddress =
4449 		    cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma);
4450 	}
4451 
4452 	/* This time stamp specifies number of milliseconds
4453 	 * since epoch ~ midnight January 1, 1970.
4454 	 */
4455 	current_time = ktime_get_real();
4456 	mpi_request.TimeStamp = cpu_to_le64(ktime_to_ms(current_time));
4457 
4458 	if (ioc->logging_level & MPT_DEBUG_INIT) {
4459 		__le32 *mfp;
4460 		int i;
4461 
4462 		mfp = (__le32 *)&mpi_request;
4463 		pr_info("\toffset:data\n");
4464 		for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
4465 			pr_info("\t[0x%02x]:%08x\n", i*4,
4466 			    le32_to_cpu(mfp[i]));
4467 	}
4468 
4469 	r = _base_handshake_req_reply_wait(ioc,
4470 	    sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request,
4471 	    sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10,
4472 	    sleep_flag);
4473 
4474 	if (r != 0) {
4475 		pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
4476 		    ioc->name, __func__, r);
4477 		goto out;
4478 	}
4479 
4480 	ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
4481 	if (ioc_status != MPI2_IOCSTATUS_SUCCESS ||
4482 	    mpi_reply.IOCLogInfo) {
4483 		pr_err(MPT3SAS_FMT "%s: failed\n", ioc->name, __func__);
4484 		r = -EIO;
4485 	}
4486 
4487 out:
4488 	if (reply_post_free_array)
4489 		pci_free_consistent(ioc->pdev, reply_post_free_array_sz,
4490 				    reply_post_free_array,
4491 				    reply_post_free_array_dma);
4492 	return r;
4493 }
4494 
4495 /**
4496  * mpt3sas_port_enable_done - command completion routine for port enable
4497  * @ioc: per adapter object
4498  * @smid: system request message index
4499  * @msix_index: MSIX table index supplied by the OS
4500  * @reply: reply message frame(lower 32bit addr)
4501  *
4502  * Return 1 meaning mf should be freed from _base_interrupt
4503  *        0 means the mf is freed from this function.
4504  */
4505 u8
4506 mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
4507 	u32 reply)
4508 {
4509 	MPI2DefaultReply_t *mpi_reply;
4510 	u16 ioc_status;
4511 
4512 	if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED)
4513 		return 1;
4514 
4515 	mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
4516 	if (!mpi_reply)
4517 		return 1;
4518 
4519 	if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE)
4520 		return 1;
4521 
4522 	ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING;
4523 	ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE;
4524 	ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID;
4525 	memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
4526 	ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
4527 	if (ioc_status != MPI2_IOCSTATUS_SUCCESS)
4528 		ioc->port_enable_failed = 1;
4529 
4530 	if (ioc->is_driver_loading) {
4531 		if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
4532 			mpt3sas_port_enable_complete(ioc);
4533 			return 1;
4534 		} else {
4535 			ioc->start_scan_failed = ioc_status;
4536 			ioc->start_scan = 0;
4537 			return 1;
4538 		}
4539 	}
4540 	complete(&ioc->port_enable_cmds.done);
4541 	return 1;
4542 }
4543 
4544 /**
4545  * _base_send_port_enable - send port_enable(discovery stuff) to firmware
4546  * @ioc: per adapter object
4547  * @sleep_flag: CAN_SLEEP or NO_SLEEP
4548  *
4549  * Returns 0 for success, non-zero for failure.
4550  */
4551 static int
4552 _base_send_port_enable(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4553 {
4554 	Mpi2PortEnableRequest_t *mpi_request;
4555 	Mpi2PortEnableReply_t *mpi_reply;
4556 	unsigned long timeleft;
4557 	int r = 0;
4558 	u16 smid;
4559 	u16 ioc_status;
4560 
4561 	pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
4562 
4563 	if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
4564 		pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4565 		    ioc->name, __func__);
4566 		return -EAGAIN;
4567 	}
4568 
4569 	smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
4570 	if (!smid) {
4571 		pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4572 		    ioc->name, __func__);
4573 		return -EAGAIN;
4574 	}
4575 
4576 	ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
4577 	mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4578 	ioc->port_enable_cmds.smid = smid;
4579 	memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
4580 	mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
4581 
4582 	init_completion(&ioc->port_enable_cmds.done);
4583 	mpt3sas_base_put_smid_default(ioc, smid);
4584 	timeleft = wait_for_completion_timeout(&ioc->port_enable_cmds.done,
4585 	    300*HZ);
4586 	if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) {
4587 		pr_err(MPT3SAS_FMT "%s: timeout\n",
4588 		    ioc->name, __func__);
4589 		_debug_dump_mf(mpi_request,
4590 		    sizeof(Mpi2PortEnableRequest_t)/4);
4591 		if (ioc->port_enable_cmds.status & MPT3_CMD_RESET)
4592 			r = -EFAULT;
4593 		else
4594 			r = -ETIME;
4595 		goto out;
4596 	}
4597 
4598 	mpi_reply = ioc->port_enable_cmds.reply;
4599 	ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
4600 	if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
4601 		pr_err(MPT3SAS_FMT "%s: failed with (ioc_status=0x%08x)\n",
4602 		    ioc->name, __func__, ioc_status);
4603 		r = -EFAULT;
4604 		goto out;
4605 	}
4606 
4607  out:
4608 	ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
4609 	pr_info(MPT3SAS_FMT "port enable: %s\n", ioc->name, ((r == 0) ?
4610 	    "SUCCESS" : "FAILED"));
4611 	return r;
4612 }
4613 
4614 /**
4615  * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply)
4616  * @ioc: per adapter object
4617  *
4618  * Returns 0 for success, non-zero for failure.
4619  */
4620 int
4621 mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc)
4622 {
4623 	Mpi2PortEnableRequest_t *mpi_request;
4624 	u16 smid;
4625 
4626 	pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
4627 
4628 	if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
4629 		pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4630 		    ioc->name, __func__);
4631 		return -EAGAIN;
4632 	}
4633 
4634 	smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
4635 	if (!smid) {
4636 		pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4637 		    ioc->name, __func__);
4638 		return -EAGAIN;
4639 	}
4640 
4641 	ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
4642 	mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4643 	ioc->port_enable_cmds.smid = smid;
4644 	memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
4645 	mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
4646 
4647 	mpt3sas_base_put_smid_default(ioc, smid);
4648 	return 0;
4649 }
4650 
4651 /**
4652  * _base_determine_wait_on_discovery - desposition
4653  * @ioc: per adapter object
4654  *
4655  * Decide whether to wait on discovery to complete. Used to either
4656  * locate boot device, or report volumes ahead of physical devices.
4657  *
4658  * Returns 1 for wait, 0 for don't wait
4659  */
4660 static int
4661 _base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc)
4662 {
4663 	/* We wait for discovery to complete if IR firmware is loaded.
4664 	 * The sas topology events arrive before PD events, so we need time to
4665 	 * turn on the bit in ioc->pd_handles to indicate PD
4666 	 * Also, it maybe required to report Volumes ahead of physical
4667 	 * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set.
4668 	 */
4669 	if (ioc->ir_firmware)
4670 		return 1;
4671 
4672 	/* if no Bios, then we don't need to wait */
4673 	if (!ioc->bios_pg3.BiosVersion)
4674 		return 0;
4675 
4676 	/* Bios is present, then we drop down here.
4677 	 *
4678 	 * If there any entries in the Bios Page 2, then we wait
4679 	 * for discovery to complete.
4680 	 */
4681 
4682 	/* Current Boot Device */
4683 	if ((ioc->bios_pg2.CurrentBootDeviceForm &
4684 	    MPI2_BIOSPAGE2_FORM_MASK) ==
4685 	    MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
4686 	/* Request Boot Device */
4687 	   (ioc->bios_pg2.ReqBootDeviceForm &
4688 	    MPI2_BIOSPAGE2_FORM_MASK) ==
4689 	    MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
4690 	/* Alternate Request Boot Device */
4691 	   (ioc->bios_pg2.ReqAltBootDeviceForm &
4692 	    MPI2_BIOSPAGE2_FORM_MASK) ==
4693 	    MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED)
4694 		return 0;
4695 
4696 	return 1;
4697 }
4698 
4699 /**
4700  * _base_unmask_events - turn on notification for this event
4701  * @ioc: per adapter object
4702  * @event: firmware event
4703  *
4704  * The mask is stored in ioc->event_masks.
4705  */
4706 static void
4707 _base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event)
4708 {
4709 	u32 desired_event;
4710 
4711 	if (event >= 128)
4712 		return;
4713 
4714 	desired_event = (1 << (event % 32));
4715 
4716 	if (event < 32)
4717 		ioc->event_masks[0] &= ~desired_event;
4718 	else if (event < 64)
4719 		ioc->event_masks[1] &= ~desired_event;
4720 	else if (event < 96)
4721 		ioc->event_masks[2] &= ~desired_event;
4722 	else if (event < 128)
4723 		ioc->event_masks[3] &= ~desired_event;
4724 }
4725 
4726 /**
4727  * _base_event_notification - send event notification
4728  * @ioc: per adapter object
4729  * @sleep_flag: CAN_SLEEP or NO_SLEEP
4730  *
4731  * Returns 0 for success, non-zero for failure.
4732  */
4733 static int
4734 _base_event_notification(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4735 {
4736 	Mpi2EventNotificationRequest_t *mpi_request;
4737 	unsigned long timeleft;
4738 	u16 smid;
4739 	int r = 0;
4740 	int i;
4741 
4742 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4743 	    __func__));
4744 
4745 	if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
4746 		pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4747 		    ioc->name, __func__);
4748 		return -EAGAIN;
4749 	}
4750 
4751 	smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4752 	if (!smid) {
4753 		pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4754 		    ioc->name, __func__);
4755 		return -EAGAIN;
4756 	}
4757 	ioc->base_cmds.status = MPT3_CMD_PENDING;
4758 	mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4759 	ioc->base_cmds.smid = smid;
4760 	memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t));
4761 	mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
4762 	mpi_request->VF_ID = 0; /* TODO */
4763 	mpi_request->VP_ID = 0;
4764 	for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4765 		mpi_request->EventMasks[i] =
4766 		    cpu_to_le32(ioc->event_masks[i]);
4767 	init_completion(&ioc->base_cmds.done);
4768 	mpt3sas_base_put_smid_default(ioc, smid);
4769 	timeleft = wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
4770 	if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4771 		pr_err(MPT3SAS_FMT "%s: timeout\n",
4772 		    ioc->name, __func__);
4773 		_debug_dump_mf(mpi_request,
4774 		    sizeof(Mpi2EventNotificationRequest_t)/4);
4775 		if (ioc->base_cmds.status & MPT3_CMD_RESET)
4776 			r = -EFAULT;
4777 		else
4778 			r = -ETIME;
4779 	} else
4780 		dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s: complete\n",
4781 		    ioc->name, __func__));
4782 	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4783 	return r;
4784 }
4785 
4786 /**
4787  * mpt3sas_base_validate_event_type - validating event types
4788  * @ioc: per adapter object
4789  * @event: firmware event
4790  *
4791  * This will turn on firmware event notification when application
4792  * ask for that event. We don't mask events that are already enabled.
4793  */
4794 void
4795 mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type)
4796 {
4797 	int i, j;
4798 	u32 event_mask, desired_event;
4799 	u8 send_update_to_fw;
4800 
4801 	for (i = 0, send_update_to_fw = 0; i <
4802 	    MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) {
4803 		event_mask = ~event_type[i];
4804 		desired_event = 1;
4805 		for (j = 0; j < 32; j++) {
4806 			if (!(event_mask & desired_event) &&
4807 			    (ioc->event_masks[i] & desired_event)) {
4808 				ioc->event_masks[i] &= ~desired_event;
4809 				send_update_to_fw = 1;
4810 			}
4811 			desired_event = (desired_event << 1);
4812 		}
4813 	}
4814 
4815 	if (!send_update_to_fw)
4816 		return;
4817 
4818 	mutex_lock(&ioc->base_cmds.mutex);
4819 	_base_event_notification(ioc, CAN_SLEEP);
4820 	mutex_unlock(&ioc->base_cmds.mutex);
4821 }
4822 
4823 /**
4824  * _base_diag_reset - the "big hammer" start of day reset
4825  * @ioc: per adapter object
4826  * @sleep_flag: CAN_SLEEP or NO_SLEEP
4827  *
4828  * Returns 0 for success, non-zero for failure.
4829  */
4830 static int
4831 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4832 {
4833 	u32 host_diagnostic;
4834 	u32 ioc_state;
4835 	u32 count;
4836 	u32 hcb_size;
4837 
4838 	pr_info(MPT3SAS_FMT "sending diag reset !!\n", ioc->name);
4839 
4840 	drsprintk(ioc, pr_info(MPT3SAS_FMT "clear interrupts\n",
4841 	    ioc->name));
4842 
4843 	count = 0;
4844 	do {
4845 		/* Write magic sequence to WriteSequence register
4846 		 * Loop until in diagnostic mode
4847 		 */
4848 		drsprintk(ioc, pr_info(MPT3SAS_FMT
4849 			"write magic sequence\n", ioc->name));
4850 		writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
4851 		writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
4852 		writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
4853 		writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
4854 		writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
4855 		writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
4856 		writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
4857 
4858 		/* wait 100 msec */
4859 		if (sleep_flag == CAN_SLEEP)
4860 			msleep(100);
4861 		else
4862 			mdelay(100);
4863 
4864 		if (count++ > 20)
4865 			goto out;
4866 
4867 		host_diagnostic = readl(&ioc->chip->HostDiagnostic);
4868 		drsprintk(ioc, pr_info(MPT3SAS_FMT
4869 			"wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
4870 		    ioc->name, count, host_diagnostic));
4871 
4872 	} while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
4873 
4874 	hcb_size = readl(&ioc->chip->HCBSize);
4875 
4876 	drsprintk(ioc, pr_info(MPT3SAS_FMT "diag reset: issued\n",
4877 	    ioc->name));
4878 	writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
4879 	     &ioc->chip->HostDiagnostic);
4880 
4881 	/*This delay allows the chip PCIe hardware time to finish reset tasks*/
4882 	if (sleep_flag == CAN_SLEEP)
4883 		msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
4884 	else
4885 		mdelay(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
4886 
4887 	/* Approximately 300 second max wait */
4888 	for (count = 0; count < (300000000 /
4889 		MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
4890 
4891 		host_diagnostic = readl(&ioc->chip->HostDiagnostic);
4892 
4893 		if (host_diagnostic == 0xFFFFFFFF)
4894 			goto out;
4895 		if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
4896 			break;
4897 
4898 		/* Wait to pass the second read delay window */
4899 		if (sleep_flag == CAN_SLEEP)
4900 			msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC
4901 								/ 1000);
4902 		else
4903 			mdelay(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC
4904 								/ 1000);
4905 	}
4906 
4907 	if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
4908 
4909 		drsprintk(ioc, pr_info(MPT3SAS_FMT
4910 		"restart the adapter assuming the HCB Address points to good F/W\n",
4911 		    ioc->name));
4912 		host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
4913 		host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
4914 		writel(host_diagnostic, &ioc->chip->HostDiagnostic);
4915 
4916 		drsprintk(ioc, pr_info(MPT3SAS_FMT
4917 		    "re-enable the HCDW\n", ioc->name));
4918 		writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
4919 		    &ioc->chip->HCBSize);
4920 	}
4921 
4922 	drsprintk(ioc, pr_info(MPT3SAS_FMT "restart the adapter\n",
4923 	    ioc->name));
4924 	writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
4925 	    &ioc->chip->HostDiagnostic);
4926 
4927 	drsprintk(ioc, pr_info(MPT3SAS_FMT
4928 		"disable writes to the diagnostic register\n", ioc->name));
4929 	writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
4930 
4931 	drsprintk(ioc, pr_info(MPT3SAS_FMT
4932 		"Wait for FW to go to the READY state\n", ioc->name));
4933 	ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20,
4934 	    sleep_flag);
4935 	if (ioc_state) {
4936 		pr_err(MPT3SAS_FMT
4937 			"%s: failed going to ready state (ioc_state=0x%x)\n",
4938 			ioc->name, __func__, ioc_state);
4939 		goto out;
4940 	}
4941 
4942 	pr_info(MPT3SAS_FMT "diag reset: SUCCESS\n", ioc->name);
4943 	return 0;
4944 
4945  out:
4946 	pr_err(MPT3SAS_FMT "diag reset: FAILED\n", ioc->name);
4947 	return -EFAULT;
4948 }
4949 
4950 /**
4951  * _base_make_ioc_ready - put controller in READY state
4952  * @ioc: per adapter object
4953  * @sleep_flag: CAN_SLEEP or NO_SLEEP
4954  * @type: FORCE_BIG_HAMMER or SOFT_RESET
4955  *
4956  * Returns 0 for success, non-zero for failure.
4957  */
4958 static int
4959 _base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, int sleep_flag,
4960 	enum reset_type type)
4961 {
4962 	u32 ioc_state;
4963 	int rc;
4964 	int count;
4965 
4966 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4967 	    __func__));
4968 
4969 	if (ioc->pci_error_recovery)
4970 		return 0;
4971 
4972 	ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4973 	dhsprintk(ioc, pr_info(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
4974 	    ioc->name, __func__, ioc_state));
4975 
4976 	/* if in RESET state, it should move to READY state shortly */
4977 	count = 0;
4978 	if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
4979 		while ((ioc_state & MPI2_IOC_STATE_MASK) !=
4980 		    MPI2_IOC_STATE_READY) {
4981 			if (count++ == 10) {
4982 				pr_err(MPT3SAS_FMT
4983 					"%s: failed going to ready state (ioc_state=0x%x)\n",
4984 				    ioc->name, __func__, ioc_state);
4985 				return -EFAULT;
4986 			}
4987 			if (sleep_flag == CAN_SLEEP)
4988 				ssleep(1);
4989 			else
4990 				mdelay(1000);
4991 			ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4992 		}
4993 	}
4994 
4995 	if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY)
4996 		return 0;
4997 
4998 	if (ioc_state & MPI2_DOORBELL_USED) {
4999 		dhsprintk(ioc, pr_info(MPT3SAS_FMT
5000 			"unexpected doorbell active!\n",
5001 			ioc->name));
5002 		goto issue_diag_reset;
5003 	}
5004 
5005 	if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
5006 		mpt3sas_base_fault_info(ioc, ioc_state &
5007 		    MPI2_DOORBELL_DATA_MASK);
5008 		goto issue_diag_reset;
5009 	}
5010 
5011 	if (type == FORCE_BIG_HAMMER)
5012 		goto issue_diag_reset;
5013 
5014 	if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
5015 		if (!(_base_send_ioc_reset(ioc,
5016 		    MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15, CAN_SLEEP))) {
5017 			return 0;
5018 	}
5019 
5020  issue_diag_reset:
5021 	rc = _base_diag_reset(ioc, CAN_SLEEP);
5022 	return rc;
5023 }
5024 
5025 /**
5026  * _base_make_ioc_operational - put controller in OPERATIONAL state
5027  * @ioc: per adapter object
5028  * @sleep_flag: CAN_SLEEP or NO_SLEEP
5029  *
5030  * Returns 0 for success, non-zero for failure.
5031  */
5032 static int
5033 _base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
5034 {
5035 	int r, i, index;
5036 	unsigned long	flags;
5037 	u32 reply_address;
5038 	u16 smid;
5039 	struct _tr_list *delayed_tr, *delayed_tr_next;
5040 	struct _sc_list *delayed_sc, *delayed_sc_next;
5041 	struct _event_ack_list *delayed_event_ack, *delayed_event_ack_next;
5042 	u8 hide_flag;
5043 	struct adapter_reply_queue *reply_q;
5044 	Mpi2ReplyDescriptorsUnion_t *reply_post_free_contig;
5045 
5046 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5047 	    __func__));
5048 
5049 	/* clean the delayed target reset list */
5050 	list_for_each_entry_safe(delayed_tr, delayed_tr_next,
5051 	    &ioc->delayed_tr_list, list) {
5052 		list_del(&delayed_tr->list);
5053 		kfree(delayed_tr);
5054 	}
5055 
5056 
5057 	list_for_each_entry_safe(delayed_tr, delayed_tr_next,
5058 	    &ioc->delayed_tr_volume_list, list) {
5059 		list_del(&delayed_tr->list);
5060 		kfree(delayed_tr);
5061 	}
5062 
5063 	list_for_each_entry_safe(delayed_sc, delayed_sc_next,
5064 	    &ioc->delayed_sc_list, list) {
5065 		list_del(&delayed_sc->list);
5066 		kfree(delayed_sc);
5067 	}
5068 
5069 	list_for_each_entry_safe(delayed_event_ack, delayed_event_ack_next,
5070 	    &ioc->delayed_event_ack_list, list) {
5071 		list_del(&delayed_event_ack->list);
5072 		kfree(delayed_event_ack);
5073 	}
5074 
5075 	/* initialize the scsi lookup free list */
5076 	spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
5077 	INIT_LIST_HEAD(&ioc->free_list);
5078 	smid = 1;
5079 	for (i = 0; i < ioc->scsiio_depth; i++, smid++) {
5080 		INIT_LIST_HEAD(&ioc->scsi_lookup[i].chain_list);
5081 		ioc->scsi_lookup[i].cb_idx = 0xFF;
5082 		ioc->scsi_lookup[i].smid = smid;
5083 		ioc->scsi_lookup[i].scmd = NULL;
5084 		ioc->scsi_lookup[i].direct_io = 0;
5085 		list_add_tail(&ioc->scsi_lookup[i].tracker_list,
5086 		    &ioc->free_list);
5087 	}
5088 
5089 	/* hi-priority queue */
5090 	INIT_LIST_HEAD(&ioc->hpr_free_list);
5091 	smid = ioc->hi_priority_smid;
5092 	for (i = 0; i < ioc->hi_priority_depth; i++, smid++) {
5093 		ioc->hpr_lookup[i].cb_idx = 0xFF;
5094 		ioc->hpr_lookup[i].smid = smid;
5095 		list_add_tail(&ioc->hpr_lookup[i].tracker_list,
5096 		    &ioc->hpr_free_list);
5097 	}
5098 
5099 	/* internal queue */
5100 	INIT_LIST_HEAD(&ioc->internal_free_list);
5101 	smid = ioc->internal_smid;
5102 	for (i = 0; i < ioc->internal_depth; i++, smid++) {
5103 		ioc->internal_lookup[i].cb_idx = 0xFF;
5104 		ioc->internal_lookup[i].smid = smid;
5105 		list_add_tail(&ioc->internal_lookup[i].tracker_list,
5106 		    &ioc->internal_free_list);
5107 	}
5108 
5109 	/* chain pool */
5110 	INIT_LIST_HEAD(&ioc->free_chain_list);
5111 	for (i = 0; i < ioc->chain_depth; i++)
5112 		list_add_tail(&ioc->chain_lookup[i].tracker_list,
5113 		    &ioc->free_chain_list);
5114 
5115 	spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
5116 
5117 	/* initialize Reply Free Queue */
5118 	for (i = 0, reply_address = (u32)ioc->reply_dma ;
5119 	    i < ioc->reply_free_queue_depth ; i++, reply_address +=
5120 	    ioc->reply_sz)
5121 		ioc->reply_free[i] = cpu_to_le32(reply_address);
5122 
5123 	/* initialize reply queues */
5124 	if (ioc->is_driver_loading)
5125 		_base_assign_reply_queues(ioc);
5126 
5127 	/* initialize Reply Post Free Queue */
5128 	index = 0;
5129 	reply_post_free_contig = ioc->reply_post[0].reply_post_free;
5130 	list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
5131 		/*
5132 		 * If RDPQ is enabled, switch to the next allocation.
5133 		 * Otherwise advance within the contiguous region.
5134 		 */
5135 		if (ioc->rdpq_array_enable) {
5136 			reply_q->reply_post_free =
5137 				ioc->reply_post[index++].reply_post_free;
5138 		} else {
5139 			reply_q->reply_post_free = reply_post_free_contig;
5140 			reply_post_free_contig += ioc->reply_post_queue_depth;
5141 		}
5142 
5143 		reply_q->reply_post_host_index = 0;
5144 		for (i = 0; i < ioc->reply_post_queue_depth; i++)
5145 			reply_q->reply_post_free[i].Words =
5146 			    cpu_to_le64(ULLONG_MAX);
5147 		if (!_base_is_controller_msix_enabled(ioc))
5148 			goto skip_init_reply_post_free_queue;
5149 	}
5150  skip_init_reply_post_free_queue:
5151 
5152 	r = _base_send_ioc_init(ioc, sleep_flag);
5153 	if (r)
5154 		return r;
5155 
5156 	/* initialize reply free host index */
5157 	ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
5158 	writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
5159 
5160 	/* initialize reply post host index */
5161 	list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
5162 		if (ioc->msix96_vector)
5163 			writel((reply_q->msix_index & 7)<<
5164 			   MPI2_RPHI_MSIX_INDEX_SHIFT,
5165 			   ioc->replyPostRegisterIndex[reply_q->msix_index/8]);
5166 		else
5167 			writel(reply_q->msix_index <<
5168 				MPI2_RPHI_MSIX_INDEX_SHIFT,
5169 				&ioc->chip->ReplyPostHostIndex);
5170 
5171 		if (!_base_is_controller_msix_enabled(ioc))
5172 			goto skip_init_reply_post_host_index;
5173 	}
5174 
5175  skip_init_reply_post_host_index:
5176 
5177 	_base_unmask_interrupts(ioc);
5178 	r = _base_event_notification(ioc, sleep_flag);
5179 	if (r)
5180 		return r;
5181 
5182 	if (sleep_flag == CAN_SLEEP)
5183 		_base_static_config_pages(ioc);
5184 
5185 
5186 	if (ioc->is_driver_loading) {
5187 
5188 		if (ioc->is_warpdrive && ioc->manu_pg10.OEMIdentifier
5189 		    == 0x80) {
5190 			hide_flag = (u8) (
5191 			    le32_to_cpu(ioc->manu_pg10.OEMSpecificFlags0) &
5192 			    MFG_PAGE10_HIDE_SSDS_MASK);
5193 			if (hide_flag != MFG_PAGE10_HIDE_SSDS_MASK)
5194 				ioc->mfg_pg10_hide_flag = hide_flag;
5195 		}
5196 
5197 		ioc->wait_for_discovery_to_complete =
5198 		    _base_determine_wait_on_discovery(ioc);
5199 
5200 		return r; /* scan_start and scan_finished support */
5201 	}
5202 
5203 	r = _base_send_port_enable(ioc, sleep_flag);
5204 	if (r)
5205 		return r;
5206 
5207 	return r;
5208 }
5209 
5210 /**
5211  * mpt3sas_base_free_resources - free resources controller resources
5212  * @ioc: per adapter object
5213  *
5214  * Return nothing.
5215  */
5216 void
5217 mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc)
5218 {
5219 	dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5220 	    __func__));
5221 
5222 	/* synchronizing freeing resource with pci_access_mutex lock */
5223 	mutex_lock(&ioc->pci_access_mutex);
5224 	if (ioc->chip_phys && ioc->chip) {
5225 		_base_mask_interrupts(ioc);
5226 		ioc->shost_recovery = 1;
5227 		_base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
5228 		ioc->shost_recovery = 0;
5229 	}
5230 
5231 	mpt3sas_base_unmap_resources(ioc);
5232 	mutex_unlock(&ioc->pci_access_mutex);
5233 	return;
5234 }
5235 
5236 /**
5237  * mpt3sas_base_attach - attach controller instance
5238  * @ioc: per adapter object
5239  *
5240  * Returns 0 for success, non-zero for failure.
5241  */
5242 int
5243 mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
5244 {
5245 	int r, i;
5246 	int cpu_id, last_cpu_id = 0;
5247 
5248 	dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5249 	    __func__));
5250 
5251 	/* setup cpu_msix_table */
5252 	ioc->cpu_count = num_online_cpus();
5253 	for_each_online_cpu(cpu_id)
5254 		last_cpu_id = cpu_id;
5255 	ioc->cpu_msix_table_sz = last_cpu_id + 1;
5256 	ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL);
5257 	ioc->reply_queue_count = 1;
5258 	if (!ioc->cpu_msix_table) {
5259 		dfailprintk(ioc, pr_info(MPT3SAS_FMT
5260 			"allocation for cpu_msix_table failed!!!\n",
5261 			ioc->name));
5262 		r = -ENOMEM;
5263 		goto out_free_resources;
5264 	}
5265 
5266 	if (ioc->is_warpdrive) {
5267 		ioc->reply_post_host_index = kcalloc(ioc->cpu_msix_table_sz,
5268 		    sizeof(resource_size_t *), GFP_KERNEL);
5269 		if (!ioc->reply_post_host_index) {
5270 			dfailprintk(ioc, pr_info(MPT3SAS_FMT "allocation "
5271 				"for cpu_msix_table failed!!!\n", ioc->name));
5272 			r = -ENOMEM;
5273 			goto out_free_resources;
5274 		}
5275 	}
5276 
5277 	ioc->rdpq_array_enable_assigned = 0;
5278 	ioc->dma_mask = 0;
5279 	r = mpt3sas_base_map_resources(ioc);
5280 	if (r)
5281 		goto out_free_resources;
5282 
5283 	if (ioc->is_warpdrive) {
5284 		ioc->reply_post_host_index[0] = (resource_size_t __iomem *)
5285 		    &ioc->chip->ReplyPostHostIndex;
5286 
5287 		for (i = 1; i < ioc->cpu_msix_table_sz; i++)
5288 			ioc->reply_post_host_index[i] =
5289 			(resource_size_t __iomem *)
5290 			((u8 __iomem *)&ioc->chip->Doorbell + (0x4000 + ((i - 1)
5291 			* 4)));
5292 	}
5293 
5294 	pci_set_drvdata(ioc->pdev, ioc->shost);
5295 	r = _base_get_ioc_facts(ioc, CAN_SLEEP);
5296 	if (r)
5297 		goto out_free_resources;
5298 
5299 	switch (ioc->hba_mpi_version_belonged) {
5300 	case MPI2_VERSION:
5301 		ioc->build_sg_scmd = &_base_build_sg_scmd;
5302 		ioc->build_sg = &_base_build_sg;
5303 		ioc->build_zero_len_sge = &_base_build_zero_len_sge;
5304 		break;
5305 	case MPI25_VERSION:
5306 	case MPI26_VERSION:
5307 		/*
5308 		 * In SAS3.0,
5309 		 * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and
5310 		 * Target Status - all require the IEEE formated scatter gather
5311 		 * elements.
5312 		 */
5313 		ioc->build_sg_scmd = &_base_build_sg_scmd_ieee;
5314 		ioc->build_sg = &_base_build_sg_ieee;
5315 		ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee;
5316 		ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t);
5317 		break;
5318 	}
5319 
5320 	/*
5321 	 * These function pointers for other requests that don't
5322 	 * the require IEEE scatter gather elements.
5323 	 *
5324 	 * For example Configuration Pages and SAS IOUNIT Control don't.
5325 	 */
5326 	ioc->build_sg_mpi = &_base_build_sg;
5327 	ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge;
5328 
5329 	r = _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
5330 	if (r)
5331 		goto out_free_resources;
5332 
5333 	ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts,
5334 	    sizeof(struct mpt3sas_port_facts), GFP_KERNEL);
5335 	if (!ioc->pfacts) {
5336 		r = -ENOMEM;
5337 		goto out_free_resources;
5338 	}
5339 
5340 	for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
5341 		r = _base_get_port_facts(ioc, i, CAN_SLEEP);
5342 		if (r)
5343 			goto out_free_resources;
5344 	}
5345 
5346 	r = _base_allocate_memory_pools(ioc, CAN_SLEEP);
5347 	if (r)
5348 		goto out_free_resources;
5349 
5350 	init_waitqueue_head(&ioc->reset_wq);
5351 
5352 	/* allocate memory pd handle bitmask list */
5353 	ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
5354 	if (ioc->facts.MaxDevHandle % 8)
5355 		ioc->pd_handles_sz++;
5356 	ioc->pd_handles = kzalloc(ioc->pd_handles_sz,
5357 	    GFP_KERNEL);
5358 	if (!ioc->pd_handles) {
5359 		r = -ENOMEM;
5360 		goto out_free_resources;
5361 	}
5362 	ioc->blocking_handles = kzalloc(ioc->pd_handles_sz,
5363 	    GFP_KERNEL);
5364 	if (!ioc->blocking_handles) {
5365 		r = -ENOMEM;
5366 		goto out_free_resources;
5367 	}
5368 
5369 	ioc->fwfault_debug = mpt3sas_fwfault_debug;
5370 
5371 	/* base internal command bits */
5372 	mutex_init(&ioc->base_cmds.mutex);
5373 	ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5374 	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
5375 
5376 	/* port_enable command bits */
5377 	ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5378 	ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
5379 
5380 	/* transport internal command bits */
5381 	ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5382 	ioc->transport_cmds.status = MPT3_CMD_NOT_USED;
5383 	mutex_init(&ioc->transport_cmds.mutex);
5384 
5385 	/* scsih internal command bits */
5386 	ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5387 	ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
5388 	mutex_init(&ioc->scsih_cmds.mutex);
5389 
5390 	/* task management internal command bits */
5391 	ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5392 	ioc->tm_cmds.status = MPT3_CMD_NOT_USED;
5393 	mutex_init(&ioc->tm_cmds.mutex);
5394 
5395 	/* config page internal command bits */
5396 	ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5397 	ioc->config_cmds.status = MPT3_CMD_NOT_USED;
5398 	mutex_init(&ioc->config_cmds.mutex);
5399 
5400 	/* ctl module internal command bits */
5401 	ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5402 	ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
5403 	ioc->ctl_cmds.status = MPT3_CMD_NOT_USED;
5404 	mutex_init(&ioc->ctl_cmds.mutex);
5405 
5406 	if (!ioc->base_cmds.reply || !ioc->transport_cmds.reply ||
5407 	    !ioc->scsih_cmds.reply || !ioc->tm_cmds.reply ||
5408 	    !ioc->config_cmds.reply || !ioc->ctl_cmds.reply ||
5409 	    !ioc->ctl_cmds.sense) {
5410 		r = -ENOMEM;
5411 		goto out_free_resources;
5412 	}
5413 
5414 	for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
5415 		ioc->event_masks[i] = -1;
5416 
5417 	/* here we enable the events we care about */
5418 	_base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY);
5419 	_base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE);
5420 	_base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
5421 	_base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE);
5422 	_base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE);
5423 	_base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST);
5424 	_base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME);
5425 	_base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK);
5426 	_base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS);
5427 	_base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED);
5428 	_base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD);
5429 	if (ioc->hba_mpi_version_belonged == MPI26_VERSION)
5430 		_base_unmask_events(ioc, MPI2_EVENT_ACTIVE_CABLE_EXCEPTION);
5431 
5432 	r = _base_make_ioc_operational(ioc, CAN_SLEEP);
5433 	if (r)
5434 		goto out_free_resources;
5435 
5436 	ioc->non_operational_loop = 0;
5437 	return 0;
5438 
5439  out_free_resources:
5440 
5441 	ioc->remove_host = 1;
5442 
5443 	mpt3sas_base_free_resources(ioc);
5444 	_base_release_memory_pools(ioc);
5445 	pci_set_drvdata(ioc->pdev, NULL);
5446 	kfree(ioc->cpu_msix_table);
5447 	if (ioc->is_warpdrive)
5448 		kfree(ioc->reply_post_host_index);
5449 	kfree(ioc->pd_handles);
5450 	kfree(ioc->blocking_handles);
5451 	kfree(ioc->tm_cmds.reply);
5452 	kfree(ioc->transport_cmds.reply);
5453 	kfree(ioc->scsih_cmds.reply);
5454 	kfree(ioc->config_cmds.reply);
5455 	kfree(ioc->base_cmds.reply);
5456 	kfree(ioc->port_enable_cmds.reply);
5457 	kfree(ioc->ctl_cmds.reply);
5458 	kfree(ioc->ctl_cmds.sense);
5459 	kfree(ioc->pfacts);
5460 	ioc->ctl_cmds.reply = NULL;
5461 	ioc->base_cmds.reply = NULL;
5462 	ioc->tm_cmds.reply = NULL;
5463 	ioc->scsih_cmds.reply = NULL;
5464 	ioc->transport_cmds.reply = NULL;
5465 	ioc->config_cmds.reply = NULL;
5466 	ioc->pfacts = NULL;
5467 	return r;
5468 }
5469 
5470 
5471 /**
5472  * mpt3sas_base_detach - remove controller instance
5473  * @ioc: per adapter object
5474  *
5475  * Return nothing.
5476  */
5477 void
5478 mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc)
5479 {
5480 	dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5481 	    __func__));
5482 
5483 	mpt3sas_base_stop_watchdog(ioc);
5484 	mpt3sas_base_free_resources(ioc);
5485 	_base_release_memory_pools(ioc);
5486 	pci_set_drvdata(ioc->pdev, NULL);
5487 	kfree(ioc->cpu_msix_table);
5488 	if (ioc->is_warpdrive)
5489 		kfree(ioc->reply_post_host_index);
5490 	kfree(ioc->pd_handles);
5491 	kfree(ioc->blocking_handles);
5492 	kfree(ioc->pfacts);
5493 	kfree(ioc->ctl_cmds.reply);
5494 	kfree(ioc->ctl_cmds.sense);
5495 	kfree(ioc->base_cmds.reply);
5496 	kfree(ioc->port_enable_cmds.reply);
5497 	kfree(ioc->tm_cmds.reply);
5498 	kfree(ioc->transport_cmds.reply);
5499 	kfree(ioc->scsih_cmds.reply);
5500 	kfree(ioc->config_cmds.reply);
5501 }
5502 
5503 /**
5504  * _base_reset_handler - reset callback handler (for base)
5505  * @ioc: per adapter object
5506  * @reset_phase: phase
5507  *
5508  * The handler for doing any required cleanup or initialization.
5509  *
5510  * The reset phase can be MPT3_IOC_PRE_RESET, MPT3_IOC_AFTER_RESET,
5511  * MPT3_IOC_DONE_RESET
5512  *
5513  * Return nothing.
5514  */
5515 static void
5516 _base_reset_handler(struct MPT3SAS_ADAPTER *ioc, int reset_phase)
5517 {
5518 	mpt3sas_scsih_reset_handler(ioc, reset_phase);
5519 	mpt3sas_ctl_reset_handler(ioc, reset_phase);
5520 	switch (reset_phase) {
5521 	case MPT3_IOC_PRE_RESET:
5522 		dtmprintk(ioc, pr_info(MPT3SAS_FMT
5523 		"%s: MPT3_IOC_PRE_RESET\n", ioc->name, __func__));
5524 		break;
5525 	case MPT3_IOC_AFTER_RESET:
5526 		dtmprintk(ioc, pr_info(MPT3SAS_FMT
5527 		"%s: MPT3_IOC_AFTER_RESET\n", ioc->name, __func__));
5528 		if (ioc->transport_cmds.status & MPT3_CMD_PENDING) {
5529 			ioc->transport_cmds.status |= MPT3_CMD_RESET;
5530 			mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid);
5531 			complete(&ioc->transport_cmds.done);
5532 		}
5533 		if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
5534 			ioc->base_cmds.status |= MPT3_CMD_RESET;
5535 			mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid);
5536 			complete(&ioc->base_cmds.done);
5537 		}
5538 		if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
5539 			ioc->port_enable_failed = 1;
5540 			ioc->port_enable_cmds.status |= MPT3_CMD_RESET;
5541 			mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid);
5542 			if (ioc->is_driver_loading) {
5543 				ioc->start_scan_failed =
5544 				    MPI2_IOCSTATUS_INTERNAL_ERROR;
5545 				ioc->start_scan = 0;
5546 				ioc->port_enable_cmds.status =
5547 				    MPT3_CMD_NOT_USED;
5548 			} else
5549 				complete(&ioc->port_enable_cmds.done);
5550 		}
5551 		if (ioc->config_cmds.status & MPT3_CMD_PENDING) {
5552 			ioc->config_cmds.status |= MPT3_CMD_RESET;
5553 			mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid);
5554 			ioc->config_cmds.smid = USHRT_MAX;
5555 			complete(&ioc->config_cmds.done);
5556 		}
5557 		break;
5558 	case MPT3_IOC_DONE_RESET:
5559 		dtmprintk(ioc, pr_info(MPT3SAS_FMT
5560 			"%s: MPT3_IOC_DONE_RESET\n", ioc->name, __func__));
5561 		break;
5562 	}
5563 }
5564 
5565 /**
5566  * _wait_for_commands_to_complete - reset controller
5567  * @ioc: Pointer to MPT_ADAPTER structure
5568  * @sleep_flag: CAN_SLEEP or NO_SLEEP
5569  *
5570  * This function waiting(3s) for all pending commands to complete
5571  * prior to putting controller in reset.
5572  */
5573 static void
5574 _wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
5575 {
5576 	u32 ioc_state;
5577 	unsigned long flags;
5578 	u16 i;
5579 
5580 	ioc->pending_io_count = 0;
5581 	if (sleep_flag != CAN_SLEEP)
5582 		return;
5583 
5584 	ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
5585 	if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL)
5586 		return;
5587 
5588 	/* pending command count */
5589 	spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
5590 	for (i = 0; i < ioc->scsiio_depth; i++)
5591 		if (ioc->scsi_lookup[i].cb_idx != 0xFF)
5592 			ioc->pending_io_count++;
5593 	spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
5594 
5595 	if (!ioc->pending_io_count)
5596 		return;
5597 
5598 	/* wait for pending commands to complete */
5599 	wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ);
5600 }
5601 
5602 /**
5603  * mpt3sas_base_hard_reset_handler - reset controller
5604  * @ioc: Pointer to MPT_ADAPTER structure
5605  * @sleep_flag: CAN_SLEEP or NO_SLEEP
5606  * @type: FORCE_BIG_HAMMER or SOFT_RESET
5607  *
5608  * Returns 0 for success, non-zero for failure.
5609  */
5610 int
5611 mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc, int sleep_flag,
5612 	enum reset_type type)
5613 {
5614 	int r;
5615 	unsigned long flags;
5616 	u32 ioc_state;
5617 	u8 is_fault = 0, is_trigger = 0;
5618 
5619 	dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: enter\n", ioc->name,
5620 	    __func__));
5621 
5622 	if (ioc->pci_error_recovery) {
5623 		pr_err(MPT3SAS_FMT "%s: pci error recovery reset\n",
5624 		    ioc->name, __func__);
5625 		r = 0;
5626 		goto out_unlocked;
5627 	}
5628 
5629 	if (mpt3sas_fwfault_debug)
5630 		mpt3sas_halt_firmware(ioc);
5631 
5632 	/* TODO - What we really should be doing is pulling
5633 	 * out all the code associated with NO_SLEEP; its never used.
5634 	 * That is legacy code from mpt fusion driver, ported over.
5635 	 * I will leave this BUG_ON here for now till its been resolved.
5636 	 */
5637 	BUG_ON(sleep_flag == NO_SLEEP);
5638 
5639 	/* wait for an active reset in progress to complete */
5640 	if (!mutex_trylock(&ioc->reset_in_progress_mutex)) {
5641 		do {
5642 			ssleep(1);
5643 		} while (ioc->shost_recovery == 1);
5644 		dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
5645 		    __func__));
5646 		return ioc->ioc_reset_in_progress_status;
5647 	}
5648 
5649 	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
5650 	ioc->shost_recovery = 1;
5651 	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
5652 
5653 	if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
5654 	    MPT3_DIAG_BUFFER_IS_REGISTERED) &&
5655 	    (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
5656 	    MPT3_DIAG_BUFFER_IS_RELEASED))) {
5657 		is_trigger = 1;
5658 		ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
5659 		if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
5660 			is_fault = 1;
5661 	}
5662 	_base_reset_handler(ioc, MPT3_IOC_PRE_RESET);
5663 	_wait_for_commands_to_complete(ioc, sleep_flag);
5664 	_base_mask_interrupts(ioc);
5665 	r = _base_make_ioc_ready(ioc, sleep_flag, type);
5666 	if (r)
5667 		goto out;
5668 	_base_reset_handler(ioc, MPT3_IOC_AFTER_RESET);
5669 
5670 	/* If this hard reset is called while port enable is active, then
5671 	 * there is no reason to call make_ioc_operational
5672 	 */
5673 	if (ioc->is_driver_loading && ioc->port_enable_failed) {
5674 		ioc->remove_host = 1;
5675 		r = -EFAULT;
5676 		goto out;
5677 	}
5678 	r = _base_get_ioc_facts(ioc, CAN_SLEEP);
5679 	if (r)
5680 		goto out;
5681 
5682 	if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable)
5683 		panic("%s: Issue occurred with flashing controller firmware."
5684 		      "Please reboot the system and ensure that the correct"
5685 		      " firmware version is running\n", ioc->name);
5686 
5687 	r = _base_make_ioc_operational(ioc, sleep_flag);
5688 	if (!r)
5689 		_base_reset_handler(ioc, MPT3_IOC_DONE_RESET);
5690 
5691  out:
5692 	dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: %s\n",
5693 	    ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED")));
5694 
5695 	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
5696 	ioc->ioc_reset_in_progress_status = r;
5697 	ioc->shost_recovery = 0;
5698 	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
5699 	ioc->ioc_reset_count++;
5700 	mutex_unlock(&ioc->reset_in_progress_mutex);
5701 
5702  out_unlocked:
5703 	if ((r == 0) && is_trigger) {
5704 		if (is_fault)
5705 			mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT);
5706 		else
5707 			mpt3sas_trigger_master(ioc,
5708 			    MASTER_TRIGGER_ADAPTER_RESET);
5709 	}
5710 	dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
5711 	    __func__));
5712 	return r;
5713 }
5714