1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright 2000-2015 Avago Technologies. All rights reserved. 4 * 5 * 6 * Name: mpi2_cnfg.h 7 * Title: MPI Configuration messages and pages 8 * Creation Date: November 10, 2006 9 * 10 * mpi2_cnfg.h Version: 02.00.40 11 * 12 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 13 * prefix are for use only on MPI v2.5 products, and must not be used 14 * with MPI v2.0 products. Unless otherwise noted, names beginning with 15 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 16 * 17 * Version History 18 * --------------- 19 * 20 * Date Version Description 21 * -------- -------- ------------------------------------------------------ 22 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 23 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags. 24 * Added Manufacturing Page 11. 25 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE 26 * define. 27 * 06-26-07 02.00.02 Adding generic structure for product-specific 28 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS. 29 * Rework of BIOS Page 2 configuration page. 30 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the 31 * forms. 32 * Added configuration pages IOC Page 8 and Driver 33 * Persistent Mapping Page 0. 34 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated 35 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1, 36 * RAID Physical Disk Pages 0 and 1, RAID Configuration 37 * Page 0). 38 * Added new value for AccessStatus field of SAS Device 39 * Page 0 (_SATA_NEEDS_INITIALIZATION). 40 * 10-31-07 02.00.04 Added missing SEPDevHandle field to 41 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 42 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for 43 * NVDATA. 44 * Modified IOC Page 7 to use masks and added field for 45 * SASBroadcastPrimitiveMasks. 46 * Added MPI2_CONFIG_PAGE_BIOS_4. 47 * Added MPI2_CONFIG_PAGE_LOG_0. 48 * 02-29-08 02.00.06 Modified various names to make them 32-character unique. 49 * Added SAS Device IDs. 50 * Updated Integrated RAID configuration pages including 51 * Manufacturing Page 4, IOC Page 6, and RAID Configuration 52 * Page 0. 53 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA. 54 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION. 55 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING. 56 * Added missing MaxNumRoutedSasAddresses field to 57 * MPI2_CONFIG_PAGE_EXPANDER_0. 58 * Added SAS Port Page 0. 59 * Modified structure layout for 60 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0. 61 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use 62 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array. 63 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF 64 * to 0x000000FF. 65 * Added two new values for the Physical Disk Coercion Size 66 * bits in the Flags field of Manufacturing Page 4. 67 * Added product-specific Manufacturing pages 16 to 31. 68 * Modified Flags bits for controlling write cache on SATA 69 * drives in IO Unit Page 1. 70 * Added new bit to AdditionalControlFlags of SAS IO Unit 71 * Page 1 to control Invalid Topology Correction. 72 * Added additional defines for RAID Volume Page 0 73 * VolumeStatusFlags field. 74 * Modified meaning of RAID Volume Page 0 VolumeSettings 75 * define for auto-configure of hot-swap drives. 76 * Added SupportedPhysDisks field to RAID Volume Page 1 and 77 * added related defines. 78 * Added PhysDiskAttributes field (and related defines) to 79 * RAID Physical Disk Page 0. 80 * Added MPI2_SAS_PHYINFO_PHY_VACANT define. 81 * Added three new DiscoveryStatus bits for SAS IO Unit 82 * Page 0 and SAS Expander Page 0. 83 * Removed multiplexing information from SAS IO Unit pages. 84 * Added BootDeviceWaitTime field to SAS IO Unit Page 4. 85 * Removed Zone Address Resolved bit from PhyInfo and from 86 * Expander Page 0 Flags field. 87 * Added two new AccessStatus values to SAS Device Page 0 88 * for indicating routing problems. Added 3 reserved words 89 * to this page. 90 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3. 91 * Inserted missing reserved field into structure for IOC 92 * Page 6. 93 * Added more pending task bits to RAID Volume Page 0 94 * VolumeStatusFlags defines. 95 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define. 96 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0 97 * and SAS Expander Page 0 to flag a downstream initiator 98 * when in simplified routing mode. 99 * Removed SATA Init Failure defines for DiscoveryStatus 100 * fields of SAS IO Unit Page 0 and SAS Expander Page 0. 101 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define. 102 * Added PortGroups, DmaGroup, and ControlGroup fields to 103 * SAS Device Page 0. 104 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO 105 * Unit Page 6. 106 * Added expander reduced functionality data to SAS 107 * Expander Page 0. 108 * Added SAS PHY Page 2 and SAS PHY Page 3. 109 * 07-30-09 02.00.12 Added IO Unit Page 7. 110 * Added new device ids. 111 * Added SAS IO Unit Page 5. 112 * Added partial and slumber power management capable flags 113 * to SAS Device Page 0 Flags field. 114 * Added PhyInfo defines for power condition. 115 * Added Ethernet configuration pages. 116 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY. 117 * Added SAS PHY Page 4 structure and defines. 118 * 02-10-10 02.00.14 Modified the comments for the configuration page 119 * structures that contain an array of data. The host 120 * should use the "count" field in the page data (e.g. the 121 * NumPhys field) to determine the number of valid elements 122 * in the array. 123 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines. 124 * Added PowerManagementCapabilities to IO Unit Page 7. 125 * Added PortWidthModGroup field to 126 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS. 127 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines. 128 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines. 129 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines. 130 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT 131 * define. 132 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define. 133 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define. 134 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing) 135 * defines. 136 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to 137 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for 138 * the Pinout field. 139 * Added BoardTemperature and BoardTemperatureUnits fields 140 * to MPI2_CONFIG_PAGE_IO_UNIT_7. 141 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define 142 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure. 143 * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST. 144 * Added IO Unit Page 8, IO Unit Page 9, 145 * and IO Unit Page 10. 146 * Added SASNotifyPrimitiveMasks field to 147 * MPI2_CONFIG_PAGE_IOC_7. 148 * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec). 149 * 05-25-11 02.00.20 Cleaned up a few comments. 150 * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities 151 * for PCIe link as obsolete. 152 * Added SpinupFlags field containing a Disable Spin-up bit 153 * to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO 154 * Unit Page 4. 155 * 11-18-11 02.00.22 Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT. 156 * Added UEFIVersion field to BIOS Page 1 and defined new 157 * BiosOptions bits. 158 * Incorporating additions for MPI v2.5. 159 * 11-27-12 02.00.23 Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER. 160 * Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID. 161 * 12-20-12 02.00.24 Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as 162 * obsolete for MPI v2.5 and later. 163 * Added some defines for 12G SAS speeds. 164 * 04-09-13 02.00.25 Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK. 165 * Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to 166 * match the specification. 167 * 08-19-13 02.00.26 Added reserved words to MPI2_CONFIG_PAGE_IO_UNIT_7 for 168 * future use. 169 * 12-05-13 02.00.27 Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for 170 * MPI2_CONFIG_PAGE_MAN_7. 171 * Added EnclosureLevel and ConnectorName fields to 172 * MPI2_CONFIG_PAGE_SAS_DEV_0. 173 * Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for 174 * MPI2_CONFIG_PAGE_SAS_DEV_0. 175 * Added EnclosureLevel field to 176 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 177 * Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for 178 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 179 * 01-08-14 02.00.28 Added more defines for the BiosOptions field of 180 * MPI2_CONFIG_PAGE_BIOS_1. 181 * 06-13-14 02.00.29 Added SSUTimeout field to MPI2_CONFIG_PAGE_BIOS_1, and 182 * more defines for the BiosOptions field. 183 * 11-18-14 02.00.30 Updated copyright information. 184 * Added MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG. 185 * Added AdapterOrderAux fields to BIOS Page 3. 186 * 03-16-15 02.00.31 Updated for MPI v2.6. 187 * Added Flags field to IO Unit Page 7. 188 * Added new SAS Phy Event codes 189 * 05-25-15 02.00.33 Added more defines for the BiosOptions field of 190 * MPI2_CONFIG_PAGE_BIOS_1. 191 * 08-25-15 02.00.34 Bumped Header Version. 192 * 12-18-15 02.00.35 Added SATADeviceWaitTime to SAS IO Unit Page 4. 193 * 01-21-16 02.00.36 Added/modified MPI2_MFGPAGE_DEVID_SAS defines. 194 * Added Link field to PCIe Link Pages 195 * Added EnclosureLevel and ConnectorName to PCIe 196 * Device Page 0. 197 * Added define for PCIE IoUnit page 1 max rate shift. 198 * Added comment for reserved ExtPageTypes. 199 * Added SAS 4 22.5 gbs speed support. 200 * Added PCIe 4 16.0 GT/sec speec support. 201 * Removed AHCI support. 202 * Removed SOP support. 203 * Added NegotiatedLinkRate and NegotiatedPortWidth to 204 * PCIe device page 0. 205 * 04-10-16 02.00.37 Fixed MPI2_MFGPAGE_DEVID_SAS3616/3708 defines 206 * 07-01-16 02.00.38 Added Manufacturing page 7 Connector types. 207 * Changed declaration of ConnectorName in PCIe DevicePage0 208 * to match SAS DevicePage 0. 209 * Added SATADeviceWaitTime to IO Unit Page 11. 210 * Added MPI26_MFGPAGE_DEVID_SAS4008 211 * Added x16 PCIe width to IO Unit Page 7 212 * Added LINKFLAGS to control SRIS in PCIe IO Unit page 1 213 * phy data. 214 * Added InitStatus to PCIe IO Unit Page 1 header. 215 * 09-01-16 02.00.39 Added MPI26_CONFIG_PAGE_ENCLOSURE_0 and related defines. 216 * Added MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE and 217 * MPI26_ENCLOS_PGAD_FORM_HANDLE page address formats. 218 * 02-02-17 02.00.40 Added MPI2_MANPAGE7_SLOT_UNKNOWN. 219 * Added ChassisSlot field to SAS Enclosure Page 0. 220 * Added ChassisSlot Valid bit (bit 5) to the Flags field 221 * in SAS Enclosure Page 0. 222 * -------------------------------------------------------------------------- 223 */ 224 225 #ifndef MPI2_CNFG_H 226 #define MPI2_CNFG_H 227 228 /***************************************************************************** 229 * Configuration Page Header and defines 230 *****************************************************************************/ 231 232 /*Config Page Header */ 233 typedef struct _MPI2_CONFIG_PAGE_HEADER { 234 U8 PageVersion; /*0x00 */ 235 U8 PageLength; /*0x01 */ 236 U8 PageNumber; /*0x02 */ 237 U8 PageType; /*0x03 */ 238 } MPI2_CONFIG_PAGE_HEADER, *PTR_MPI2_CONFIG_PAGE_HEADER, 239 Mpi2ConfigPageHeader_t, *pMpi2ConfigPageHeader_t; 240 241 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION { 242 MPI2_CONFIG_PAGE_HEADER Struct; 243 U8 Bytes[4]; 244 U16 Word16[2]; 245 U32 Word32; 246 } MPI2_CONFIG_PAGE_HEADER_UNION, *PTR_MPI2_CONFIG_PAGE_HEADER_UNION, 247 Mpi2ConfigPageHeaderUnion, *pMpi2ConfigPageHeaderUnion; 248 249 /*Extended Config Page Header */ 250 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER { 251 U8 PageVersion; /*0x00 */ 252 U8 Reserved1; /*0x01 */ 253 U8 PageNumber; /*0x02 */ 254 U8 PageType; /*0x03 */ 255 U16 ExtPageLength; /*0x04 */ 256 U8 ExtPageType; /*0x06 */ 257 U8 Reserved2; /*0x07 */ 258 } MPI2_CONFIG_EXTENDED_PAGE_HEADER, 259 *PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER, 260 Mpi2ConfigExtendedPageHeader_t, 261 *pMpi2ConfigExtendedPageHeader_t; 262 263 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION { 264 MPI2_CONFIG_PAGE_HEADER Struct; 265 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext; 266 U8 Bytes[8]; 267 U16 Word16[4]; 268 U32 Word32[2]; 269 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 270 *PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 271 Mpi2ConfigPageExtendedHeaderUnion, 272 *pMpi2ConfigPageExtendedHeaderUnion; 273 274 275 /*PageType field values */ 276 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 277 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 278 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 279 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0) 280 281 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00) 282 #define MPI2_CONFIG_PAGETYPE_IOC (0x01) 283 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02) 284 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 285 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09) 286 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 287 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F) 288 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F) 289 290 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF) 291 292 293 /*ExtPageType field values */ 294 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 295 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 296 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 297 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 298 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14) 299 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 300 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 301 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 302 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 303 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19) 304 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A) 305 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_IO_UNIT (0x1B) 306 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_SWITCH (0x1C) 307 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_DEVICE (0x1D) 308 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_LINK (0x1E) 309 310 311 /***************************************************************************** 312 * PageAddress defines 313 *****************************************************************************/ 314 315 /*RAID Volume PageAddress format */ 316 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000) 317 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 318 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000) 319 320 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF) 321 322 323 /*RAID Physical Disk PageAddress format */ 324 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000) 325 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000) 326 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000) 327 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000) 328 329 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 330 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF) 331 332 333 /*SAS Expander PageAddress format */ 334 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 335 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 336 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000) 337 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000) 338 339 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) 340 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) 341 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 342 343 344 /*SAS Device PageAddress format */ 345 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 346 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 347 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000) 348 349 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 350 351 352 /*SAS PHY PageAddress format */ 353 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 354 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 355 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000) 356 357 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 358 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 359 360 361 /*SAS Port PageAddress format */ 362 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000) 363 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 364 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 365 366 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF) 367 368 369 /*SAS Enclosure PageAddress format */ 370 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 371 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 372 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 373 374 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 375 376 /*Enclosure PageAddress format */ 377 #define MPI26_ENCLOS_PGAD_FORM_MASK (0xF0000000) 378 #define MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 379 #define MPI26_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 380 381 #define MPI26_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 382 383 /*RAID Configuration PageAddress format */ 384 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000) 385 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000) 386 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000) 387 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000) 388 389 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF) 390 391 392 /*Driver Persistent Mapping PageAddress format */ 393 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000) 394 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000) 395 396 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000) 397 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16) 398 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF) 399 400 401 /*Ethernet PageAddress format */ 402 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000) 403 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000) 404 405 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF) 406 407 408 /*PCIe Switch PageAddress format */ 409 #define MPI26_PCIE_SWITCH_PGAD_FORM_MASK (0xF0000000) 410 #define MPI26_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 411 #define MPI26_PCIE_SWITCH_PGAD_FORM_HNDL_PORTNUM (0x10000000) 412 #define MPI26_PCIE_SWITCH_EXPAND_PGAD_FORM_HNDL (0x20000000) 413 414 #define MPI26_PCIE_SWITCH_PGAD_HANDLE_MASK (0x0000FFFF) 415 #define MPI26_PCIE_SWITCH_PGAD_PORTNUM_MASK (0x00FF0000) 416 #define MPI26_PCIE_SWITCH_PGAD_PORTNUM_SHIFT (16) 417 418 419 /*PCIe Device PageAddress format */ 420 #define MPI26_PCIE_DEVICE_PGAD_FORM_MASK (0xF0000000) 421 #define MPI26_PCIE_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 422 #define MPI26_PCIE_DEVICE_PGAD_FORM_HANDLE (0x20000000) 423 424 #define MPI26_PCIE_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 425 426 /*PCIe Link PageAddress format */ 427 #define MPI26_PCIE_LINK_PGAD_FORM_MASK (0xF0000000) 428 #define MPI26_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK (0x00000000) 429 #define MPI26_PCIE_LINK_PGAD_FORM_LINK_NUM (0x10000000) 430 431 #define MPI26_PCIE_DEVICE_PGAD_LINKNUM_MASK (0x000000FF) 432 433 434 435 /**************************************************************************** 436 * Configuration messages 437 ****************************************************************************/ 438 439 /*Configuration Request Message */ 440 typedef struct _MPI2_CONFIG_REQUEST { 441 U8 Action; /*0x00 */ 442 U8 SGLFlags; /*0x01 */ 443 U8 ChainOffset; /*0x02 */ 444 U8 Function; /*0x03 */ 445 U16 ExtPageLength; /*0x04 */ 446 U8 ExtPageType; /*0x06 */ 447 U8 MsgFlags; /*0x07 */ 448 U8 VP_ID; /*0x08 */ 449 U8 VF_ID; /*0x09 */ 450 U16 Reserved1; /*0x0A */ 451 U8 Reserved2; /*0x0C */ 452 U8 ProxyVF_ID; /*0x0D */ 453 U16 Reserved4; /*0x0E */ 454 U32 Reserved3; /*0x10 */ 455 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */ 456 U32 PageAddress; /*0x18 */ 457 MPI2_SGE_IO_UNION PageBufferSGE; /*0x1C */ 458 } MPI2_CONFIG_REQUEST, *PTR_MPI2_CONFIG_REQUEST, 459 Mpi2ConfigRequest_t, *pMpi2ConfigRequest_t; 460 461 /*values for the Action field */ 462 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00) 463 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 464 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 465 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03) 466 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 467 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 468 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 469 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07) 470 471 /*use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */ 472 473 474 /*Config Reply Message */ 475 typedef struct _MPI2_CONFIG_REPLY { 476 U8 Action; /*0x00 */ 477 U8 SGLFlags; /*0x01 */ 478 U8 MsgLength; /*0x02 */ 479 U8 Function; /*0x03 */ 480 U16 ExtPageLength; /*0x04 */ 481 U8 ExtPageType; /*0x06 */ 482 U8 MsgFlags; /*0x07 */ 483 U8 VP_ID; /*0x08 */ 484 U8 VF_ID; /*0x09 */ 485 U16 Reserved1; /*0x0A */ 486 U16 Reserved2; /*0x0C */ 487 U16 IOCStatus; /*0x0E */ 488 U32 IOCLogInfo; /*0x10 */ 489 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */ 490 } MPI2_CONFIG_REPLY, *PTR_MPI2_CONFIG_REPLY, 491 Mpi2ConfigReply_t, *pMpi2ConfigReply_t; 492 493 494 495 /***************************************************************************** 496 * 497 * C o n f i g u r a t i o n P a g e s 498 * 499 *****************************************************************************/ 500 501 /**************************************************************************** 502 * Manufacturing Config pages 503 ****************************************************************************/ 504 505 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000) 506 507 /*MPI v2.0 SAS products */ 508 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070) 509 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072) 510 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074) 511 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076) 512 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077) 513 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064) 514 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065) 515 516 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E) 517 518 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080) 519 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081) 520 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082) 521 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083) 522 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084) 523 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085) 524 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086) 525 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087) 526 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E) 527 528 /*MPI v2.5 SAS products */ 529 #define MPI25_MFGPAGE_DEVID_SAS3004 (0x0096) 530 #define MPI25_MFGPAGE_DEVID_SAS3008 (0x0097) 531 #define MPI25_MFGPAGE_DEVID_SAS3108_1 (0x0090) 532 #define MPI25_MFGPAGE_DEVID_SAS3108_2 (0x0091) 533 #define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094) 534 #define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095) 535 536 /* MPI v2.6 SAS Products */ 537 #define MPI26_MFGPAGE_DEVID_SAS3216 (0x00C9) 538 #define MPI26_MFGPAGE_DEVID_SAS3224 (0x00C4) 539 #define MPI26_MFGPAGE_DEVID_SAS3316_1 (0x00C5) 540 #define MPI26_MFGPAGE_DEVID_SAS3316_2 (0x00C6) 541 #define MPI26_MFGPAGE_DEVID_SAS3316_3 (0x00C7) 542 #define MPI26_MFGPAGE_DEVID_SAS3316_4 (0x00C8) 543 #define MPI26_MFGPAGE_DEVID_SAS3324_1 (0x00C0) 544 #define MPI26_MFGPAGE_DEVID_SAS3324_2 (0x00C1) 545 #define MPI26_MFGPAGE_DEVID_SAS3324_3 (0x00C2) 546 #define MPI26_MFGPAGE_DEVID_SAS3324_4 (0x00C3) 547 548 #define MPI26_MFGPAGE_DEVID_SAS3516 (0x00AA) 549 #define MPI26_MFGPAGE_DEVID_SAS3516_1 (0x00AB) 550 #define MPI26_MFGPAGE_DEVID_SAS3416 (0x00AC) 551 #define MPI26_MFGPAGE_DEVID_SAS3508 (0x00AD) 552 #define MPI26_MFGPAGE_DEVID_SAS3508_1 (0x00AE) 553 #define MPI26_MFGPAGE_DEVID_SAS3408 (0x00AF) 554 #define MPI26_MFGPAGE_DEVID_SAS3716 (0x00D0) 555 #define MPI26_MFGPAGE_DEVID_SAS3616 (0x00D1) 556 #define MPI26_MFGPAGE_DEVID_SAS3708 (0x00D2) 557 558 #define MPI26_MFGPAGE_DEVID_SAS4008 (0x00A1) 559 560 561 /*Manufacturing Page 0 */ 562 563 typedef struct _MPI2_CONFIG_PAGE_MAN_0 { 564 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 565 U8 ChipName[16]; /*0x04 */ 566 U8 ChipRevision[8]; /*0x14 */ 567 U8 BoardName[16]; /*0x1C */ 568 U8 BoardAssembly[16]; /*0x2C */ 569 U8 BoardTracerNumber[16]; /*0x3C */ 570 } MPI2_CONFIG_PAGE_MAN_0, 571 *PTR_MPI2_CONFIG_PAGE_MAN_0, 572 Mpi2ManufacturingPage0_t, 573 *pMpi2ManufacturingPage0_t; 574 575 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00) 576 577 578 /*Manufacturing Page 1 */ 579 580 typedef struct _MPI2_CONFIG_PAGE_MAN_1 { 581 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 582 U8 VPD[256]; /*0x04 */ 583 } MPI2_CONFIG_PAGE_MAN_1, 584 *PTR_MPI2_CONFIG_PAGE_MAN_1, 585 Mpi2ManufacturingPage1_t, 586 *pMpi2ManufacturingPage1_t; 587 588 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00) 589 590 591 typedef struct _MPI2_CHIP_REVISION_ID { 592 U16 DeviceID; /*0x00 */ 593 U8 PCIRevisionID; /*0x02 */ 594 U8 Reserved; /*0x03 */ 595 } MPI2_CHIP_REVISION_ID, *PTR_MPI2_CHIP_REVISION_ID, 596 Mpi2ChipRevisionId_t, *pMpi2ChipRevisionId_t; 597 598 599 /*Manufacturing Page 2 */ 600 601 /* 602 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 603 *one and check Header.PageLength at runtime. 604 */ 605 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS 606 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 607 #endif 608 609 typedef struct _MPI2_CONFIG_PAGE_MAN_2 { 610 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 611 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */ 612 U32 613 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/*0x08 */ 614 } MPI2_CONFIG_PAGE_MAN_2, 615 *PTR_MPI2_CONFIG_PAGE_MAN_2, 616 Mpi2ManufacturingPage2_t, 617 *pMpi2ManufacturingPage2_t; 618 619 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00) 620 621 622 /*Manufacturing Page 3 */ 623 624 /* 625 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 626 *one and check Header.PageLength at runtime. 627 */ 628 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS 629 #define MPI2_MAN_PAGE_3_INFO_WORDS (1) 630 #endif 631 632 typedef struct _MPI2_CONFIG_PAGE_MAN_3 { 633 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 634 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */ 635 U32 636 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/*0x08 */ 637 } MPI2_CONFIG_PAGE_MAN_3, 638 *PTR_MPI2_CONFIG_PAGE_MAN_3, 639 Mpi2ManufacturingPage3_t, 640 *pMpi2ManufacturingPage3_t; 641 642 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00) 643 644 645 /*Manufacturing Page 4 */ 646 647 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS { 648 U8 PowerSaveFlags; /*0x00 */ 649 U8 InternalOperationsSleepTime; /*0x01 */ 650 U8 InternalOperationsRunTime; /*0x02 */ 651 U8 HostIdleTime; /*0x03 */ 652 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 653 *PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 654 Mpi2ManPage4PwrSaveSettings_t, 655 *pMpi2ManPage4PwrSaveSettings_t; 656 657 /*defines for the PowerSaveFlags field */ 658 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03) 659 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00) 660 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01) 661 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02) 662 663 typedef struct _MPI2_CONFIG_PAGE_MAN_4 { 664 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 665 U32 Reserved1; /*0x04 */ 666 U32 Flags; /*0x08 */ 667 U8 InquirySize; /*0x0C */ 668 U8 Reserved2; /*0x0D */ 669 U16 Reserved3; /*0x0E */ 670 U8 InquiryData[56]; /*0x10 */ 671 U32 RAID0VolumeSettings; /*0x48 */ 672 U32 RAID1EVolumeSettings; /*0x4C */ 673 U32 RAID1VolumeSettings; /*0x50 */ 674 U32 RAID10VolumeSettings; /*0x54 */ 675 U32 Reserved4; /*0x58 */ 676 U32 Reserved5; /*0x5C */ 677 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /*0x60 */ 678 U8 MaxOCEDisks; /*0x64 */ 679 U8 ResyncRate; /*0x65 */ 680 U16 DataScrubDuration; /*0x66 */ 681 U8 MaxHotSpares; /*0x68 */ 682 U8 MaxPhysDisksPerVol; /*0x69 */ 683 U8 MaxPhysDisks; /*0x6A */ 684 U8 MaxVolumes; /*0x6B */ 685 } MPI2_CONFIG_PAGE_MAN_4, 686 *PTR_MPI2_CONFIG_PAGE_MAN_4, 687 Mpi2ManufacturingPage4_t, 688 *pMpi2ManufacturingPage4_t; 689 690 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A) 691 692 /*Manufacturing Page 4 Flags field */ 693 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000) 694 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000) 695 696 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000) 697 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000) 698 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000) 699 700 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00) 701 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000) 702 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400) 703 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800) 704 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00) 705 706 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300) 707 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000) 708 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100) 709 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200) 710 711 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080) 712 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040) 713 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020) 714 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010) 715 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008) 716 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004) 717 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002) 718 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001) 719 720 721 /*Manufacturing Page 5 */ 722 723 /* 724 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 725 *one and check the value returned for NumPhys at runtime. 726 */ 727 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES 728 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1) 729 #endif 730 731 typedef struct _MPI2_MANUFACTURING5_ENTRY { 732 U64 WWID; /*0x00 */ 733 U64 DeviceName; /*0x08 */ 734 } MPI2_MANUFACTURING5_ENTRY, 735 *PTR_MPI2_MANUFACTURING5_ENTRY, 736 Mpi2Manufacturing5Entry_t, 737 *pMpi2Manufacturing5Entry_t; 738 739 typedef struct _MPI2_CONFIG_PAGE_MAN_5 { 740 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 741 U8 NumPhys; /*0x04 */ 742 U8 Reserved1; /*0x05 */ 743 U16 Reserved2; /*0x06 */ 744 U32 Reserved3; /*0x08 */ 745 U32 Reserved4; /*0x0C */ 746 MPI2_MANUFACTURING5_ENTRY 747 Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/*0x08 */ 748 } MPI2_CONFIG_PAGE_MAN_5, 749 *PTR_MPI2_CONFIG_PAGE_MAN_5, 750 Mpi2ManufacturingPage5_t, 751 *pMpi2ManufacturingPage5_t; 752 753 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03) 754 755 756 /*Manufacturing Page 6 */ 757 758 typedef struct _MPI2_CONFIG_PAGE_MAN_6 { 759 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 760 U32 ProductSpecificInfo;/*0x04 */ 761 } MPI2_CONFIG_PAGE_MAN_6, 762 *PTR_MPI2_CONFIG_PAGE_MAN_6, 763 Mpi2ManufacturingPage6_t, 764 *pMpi2ManufacturingPage6_t; 765 766 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00) 767 768 769 /*Manufacturing Page 7 */ 770 771 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO { 772 U32 Pinout; /*0x00 */ 773 U8 Connector[16]; /*0x04 */ 774 U8 Location; /*0x14 */ 775 U8 ReceptacleID; /*0x15 */ 776 U16 Slot; /*0x16 */ 777 U32 Reserved2; /*0x18 */ 778 } MPI2_MANPAGE7_CONNECTOR_INFO, 779 *PTR_MPI2_MANPAGE7_CONNECTOR_INFO, 780 Mpi2ManPage7ConnectorInfo_t, 781 *pMpi2ManPage7ConnectorInfo_t; 782 783 /*defines for the Pinout field */ 784 #define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00) 785 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8) 786 787 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF) 788 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00) 789 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01) 790 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02) 791 #define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03) 792 #define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04) 793 #define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05) 794 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06) 795 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07) 796 #define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08) 797 #define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09) 798 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A) 799 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B) 800 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C) 801 #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D) 802 #define MPI2_MANPAGE7_PINOUT_SFF_8088_A (0x0E) 803 #define MPI2_MANPAGE7_PINOUT_SFF_8643_16i (0x0F) 804 #define MPI2_MANPAGE7_PINOUT_SFF_8654_4i (0x10) 805 #define MPI2_MANPAGE7_PINOUT_SFF_8654_8i (0x11) 806 #define MPI2_MANPAGE7_PINOUT_SFF_8611_4i (0x12) 807 #define MPI2_MANPAGE7_PINOUT_SFF_8611_8i (0x13) 808 809 /*defines for the Location field */ 810 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01) 811 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02) 812 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04) 813 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08) 814 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10) 815 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 816 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 817 818 /*defines for the Slot field */ 819 #define MPI2_MANPAGE7_SLOT_UNKNOWN (0xFFFF) 820 821 /* 822 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 823 *one and check the value returned for NumPhys at runtime. 824 */ 825 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX 826 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1) 827 #endif 828 829 typedef struct _MPI2_CONFIG_PAGE_MAN_7 { 830 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 831 U32 Reserved1; /*0x04 */ 832 U32 Reserved2; /*0x08 */ 833 U32 Flags; /*0x0C */ 834 U8 EnclosureName[16]; /*0x10 */ 835 U8 NumPhys; /*0x20 */ 836 U8 Reserved3; /*0x21 */ 837 U16 Reserved4; /*0x22 */ 838 MPI2_MANPAGE7_CONNECTOR_INFO 839 ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /*0x24 */ 840 } MPI2_CONFIG_PAGE_MAN_7, 841 *PTR_MPI2_CONFIG_PAGE_MAN_7, 842 Mpi2ManufacturingPage7_t, 843 *pMpi2ManufacturingPage7_t; 844 845 #define MPI2_MANUFACTURING7_PAGEVERSION (0x01) 846 847 /*defines for the Flags field */ 848 #define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL (0x00000008) 849 #define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER (0x00000002) 850 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 851 852 853 /* 854 *Generic structure to use for product-specific manufacturing pages 855 *(currently Manufacturing Page 8 through Manufacturing Page 31). 856 */ 857 858 typedef struct _MPI2_CONFIG_PAGE_MAN_PS { 859 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 860 U32 ProductSpecificInfo;/*0x04 */ 861 } MPI2_CONFIG_PAGE_MAN_PS, 862 *PTR_MPI2_CONFIG_PAGE_MAN_PS, 863 Mpi2ManufacturingPagePS_t, 864 *pMpi2ManufacturingPagePS_t; 865 866 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00) 867 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00) 868 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00) 869 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00) 870 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00) 871 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00) 872 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00) 873 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00) 874 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00) 875 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00) 876 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00) 877 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00) 878 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00) 879 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00) 880 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00) 881 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00) 882 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00) 883 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00) 884 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00) 885 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00) 886 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00) 887 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00) 888 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00) 889 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00) 890 891 892 /**************************************************************************** 893 * IO Unit Config Pages 894 ****************************************************************************/ 895 896 /*IO Unit Page 0 */ 897 898 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 { 899 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 900 U64 UniqueValue; /*0x04 */ 901 MPI2_VERSION_UNION NvdataVersionDefault; /*0x08 */ 902 MPI2_VERSION_UNION NvdataVersionPersistent; /*0x0A */ 903 } MPI2_CONFIG_PAGE_IO_UNIT_0, 904 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_0, 905 Mpi2IOUnitPage0_t, *pMpi2IOUnitPage0_t; 906 907 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02) 908 909 910 /*IO Unit Page 1 */ 911 912 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 { 913 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 914 U32 Flags; /*0x04 */ 915 } MPI2_CONFIG_PAGE_IO_UNIT_1, 916 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_1, 917 Mpi2IOUnitPage1_t, *pMpi2IOUnitPage1_t; 918 919 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04) 920 921 /*IO Unit Page 1 Flags defines */ 922 #define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK (0x00004000) 923 #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000) 924 #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000) 925 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800) 926 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600) 927 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9) 928 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000) 929 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200) 930 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400) 931 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 932 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040) 933 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020) 934 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 935 936 937 /*IO Unit Page 3 */ 938 939 /* 940 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 941 *one and check the value returned for GPIOCount at runtime. 942 */ 943 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX 944 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 945 #endif 946 947 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 { 948 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 949 U8 GPIOCount; /*0x04 */ 950 U8 Reserved1; /*0x05 */ 951 U16 Reserved2; /*0x06 */ 952 U16 953 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/*0x08 */ 954 } MPI2_CONFIG_PAGE_IO_UNIT_3, 955 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_3, 956 Mpi2IOUnitPage3_t, *pMpi2IOUnitPage3_t; 957 958 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01) 959 960 /*defines for IO Unit Page 3 GPIOVal field */ 961 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC) 962 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 963 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000) 964 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001) 965 966 967 /*IO Unit Page 5 */ 968 969 /* 970 *Upper layer code (drivers, utilities, etc.) should leave this define set to 971 *one and check the value returned for NumDmaEngines at runtime. 972 */ 973 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES 974 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1) 975 #endif 976 977 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 { 978 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 979 U64 980 RaidAcceleratorBufferBaseAddress; /*0x04 */ 981 U64 982 RaidAcceleratorBufferSize; /*0x0C */ 983 U64 984 RaidAcceleratorControlBaseAddress; /*0x14 */ 985 U8 RAControlSize; /*0x1C */ 986 U8 NumDmaEngines; /*0x1D */ 987 U8 RAMinControlSize; /*0x1E */ 988 U8 RAMaxControlSize; /*0x1F */ 989 U32 Reserved1; /*0x20 */ 990 U32 Reserved2; /*0x24 */ 991 U32 Reserved3; /*0x28 */ 992 U32 993 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /*0x2C */ 994 } MPI2_CONFIG_PAGE_IO_UNIT_5, 995 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_5, 996 Mpi2IOUnitPage5_t, *pMpi2IOUnitPage5_t; 997 998 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00) 999 1000 /*defines for IO Unit Page 5 DmaEngineCapabilities field */ 1001 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFFFF0000) 1002 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16) 1003 1004 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008) 1005 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004) 1006 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002) 1007 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001) 1008 1009 1010 /*IO Unit Page 6 */ 1011 1012 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 { 1013 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1014 U16 Flags; /*0x04 */ 1015 U8 RAHostControlSize; /*0x06 */ 1016 U8 Reserved0; /*0x07 */ 1017 U64 1018 RaidAcceleratorHostControlBaseAddress; /*0x08 */ 1019 U32 Reserved1; /*0x10 */ 1020 U32 Reserved2; /*0x14 */ 1021 U32 Reserved3; /*0x18 */ 1022 } MPI2_CONFIG_PAGE_IO_UNIT_6, 1023 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_6, 1024 Mpi2IOUnitPage6_t, *pMpi2IOUnitPage6_t; 1025 1026 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00) 1027 1028 /*defines for IO Unit Page 6 Flags field */ 1029 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001) 1030 1031 1032 /*IO Unit Page 7 */ 1033 1034 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 { 1035 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1036 U8 CurrentPowerMode; /*0x04 */ 1037 U8 PreviousPowerMode; /*0x05 */ 1038 U8 PCIeWidth; /*0x06 */ 1039 U8 PCIeSpeed; /*0x07 */ 1040 U32 ProcessorState; /*0x08 */ 1041 U32 1042 PowerManagementCapabilities; /*0x0C */ 1043 U16 IOCTemperature; /*0x10 */ 1044 U8 1045 IOCTemperatureUnits; /*0x12 */ 1046 U8 IOCSpeed; /*0x13 */ 1047 U16 BoardTemperature; /*0x14 */ 1048 U8 1049 BoardTemperatureUnits; /*0x16 */ 1050 U8 Reserved3; /*0x17 */ 1051 U32 BoardPowerRequirement; /*0x18 */ 1052 U32 PCISlotPowerAllocation; /*0x1C */ 1053 /* reserved prior to MPI v2.6 */ 1054 U8 Flags; /* 0x20 */ 1055 U8 Reserved6; /* 0x21 */ 1056 U16 Reserved7; /* 0x22 */ 1057 U32 Reserved8; /* 0x24 */ 1058 } MPI2_CONFIG_PAGE_IO_UNIT_7, 1059 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_7, 1060 Mpi2IOUnitPage7_t, *pMpi2IOUnitPage7_t; 1061 1062 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x05) 1063 1064 /*defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */ 1065 #define MPI25_IOUNITPAGE7_PM_INIT_MASK (0xC0) 1066 #define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE (0x00) 1067 #define MPI25_IOUNITPAGE7_PM_INIT_HOST (0x40) 1068 #define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT (0x80) 1069 #define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA (0xC0) 1070 1071 #define MPI25_IOUNITPAGE7_PM_MODE_MASK (0x07) 1072 #define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE (0x00) 1073 #define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN (0x01) 1074 #define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER (0x04) 1075 #define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER (0x05) 1076 #define MPI25_IOUNITPAGE7_PM_MODE_STANDBY (0x06) 1077 1078 1079 /*defines for IO Unit Page 7 PCIeWidth field */ 1080 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01) 1081 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02) 1082 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04) 1083 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08) 1084 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X16 (0x10) 1085 1086 /*defines for IO Unit Page 7 PCIeSpeed field */ 1087 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00) 1088 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01) 1089 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02) 1090 #define MPI2_IOUNITPAGE7_PCIE_SPEED_16_0_GBPS (0x03) 1091 1092 /*defines for IO Unit Page 7 ProcessorState field */ 1093 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F) 1094 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0) 1095 1096 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00) 1097 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01) 1098 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02) 1099 1100 /*defines for IO Unit Page 7 PowerManagementCapabilities field */ 1101 #define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE (0x00400000) 1102 #define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE (0x00200000) 1103 #define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE (0x00100000) 1104 #define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE (0x00040000) 1105 #define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE (0x00020000) 1106 #define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE (0x00010000) 1107 #define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE (0x00004000) 1108 #define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE (0x00002000) 1109 #define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE (0x00001000) 1110 #define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED (0x00000400) 1111 #define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED (0x00000200) 1112 #define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED (0x00000100) 1113 #define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED (0x00000040) 1114 #define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED (0x00000020) 1115 #define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED (0x00000010) 1116 #define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE (0x00000008) 1117 #define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE (0x00000004) 1118 #define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE (0x00000002) 1119 #define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE (0x00000001) 1120 1121 /*obsolete names for the PowerManagementCapabilities bits (above) */ 1122 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400) 1123 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200) 1124 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100) 1125 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /*obsolete */ 1126 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /*obsolete */ 1127 1128 1129 /*defines for IO Unit Page 7 IOCTemperatureUnits field */ 1130 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00) 1131 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01) 1132 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02) 1133 1134 /*defines for IO Unit Page 7 IOCSpeed field */ 1135 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01) 1136 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02) 1137 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04) 1138 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08) 1139 1140 /*defines for IO Unit Page 7 BoardTemperatureUnits field */ 1141 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00) 1142 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01) 1143 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02) 1144 1145 /* defines for IO Unit Page 7 Flags field */ 1146 #define MPI2_IOUNITPAGE7_FLAG_CABLE_POWER_EXC (0x01) 1147 1148 /*IO Unit Page 8 */ 1149 1150 #define MPI2_IOUNIT8_NUM_THRESHOLDS (4) 1151 1152 typedef struct _MPI2_IOUNIT8_SENSOR { 1153 U16 Flags; /*0x00 */ 1154 U16 Reserved1; /*0x02 */ 1155 U16 1156 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /*0x04 */ 1157 U32 Reserved2; /*0x0C */ 1158 U32 Reserved3; /*0x10 */ 1159 U32 Reserved4; /*0x14 */ 1160 } MPI2_IOUNIT8_SENSOR, *PTR_MPI2_IOUNIT8_SENSOR, 1161 Mpi2IOUnit8Sensor_t, *pMpi2IOUnit8Sensor_t; 1162 1163 /*defines for IO Unit Page 8 Sensor Flags field */ 1164 #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008) 1165 #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004) 1166 #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002) 1167 #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001) 1168 1169 /* 1170 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1171 *one and check the value returned for NumSensors at runtime. 1172 */ 1173 #ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES 1174 #define MPI2_IOUNITPAGE8_SENSOR_ENTRIES (1) 1175 #endif 1176 1177 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 { 1178 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1179 U32 Reserved1; /*0x04 */ 1180 U32 Reserved2; /*0x08 */ 1181 U8 NumSensors; /*0x0C */ 1182 U8 PollingInterval; /*0x0D */ 1183 U16 Reserved3; /*0x0E */ 1184 MPI2_IOUNIT8_SENSOR 1185 Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/*0x10 */ 1186 } MPI2_CONFIG_PAGE_IO_UNIT_8, 1187 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_8, 1188 Mpi2IOUnitPage8_t, *pMpi2IOUnitPage8_t; 1189 1190 #define MPI2_IOUNITPAGE8_PAGEVERSION (0x00) 1191 1192 1193 /*IO Unit Page 9 */ 1194 1195 typedef struct _MPI2_IOUNIT9_SENSOR { 1196 U16 CurrentTemperature; /*0x00 */ 1197 U16 Reserved1; /*0x02 */ 1198 U8 Flags; /*0x04 */ 1199 U8 Reserved2; /*0x05 */ 1200 U16 Reserved3; /*0x06 */ 1201 U32 Reserved4; /*0x08 */ 1202 U32 Reserved5; /*0x0C */ 1203 } MPI2_IOUNIT9_SENSOR, *PTR_MPI2_IOUNIT9_SENSOR, 1204 Mpi2IOUnit9Sensor_t, *pMpi2IOUnit9Sensor_t; 1205 1206 /*defines for IO Unit Page 9 Sensor Flags field */ 1207 #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01) 1208 1209 /* 1210 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1211 *one and check the value returned for NumSensors at runtime. 1212 */ 1213 #ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES 1214 #define MPI2_IOUNITPAGE9_SENSOR_ENTRIES (1) 1215 #endif 1216 1217 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 { 1218 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1219 U32 Reserved1; /*0x04 */ 1220 U32 Reserved2; /*0x08 */ 1221 U8 NumSensors; /*0x0C */ 1222 U8 Reserved4; /*0x0D */ 1223 U16 Reserved3; /*0x0E */ 1224 MPI2_IOUNIT9_SENSOR 1225 Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/*0x10 */ 1226 } MPI2_CONFIG_PAGE_IO_UNIT_9, 1227 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_9, 1228 Mpi2IOUnitPage9_t, *pMpi2IOUnitPage9_t; 1229 1230 #define MPI2_IOUNITPAGE9_PAGEVERSION (0x00) 1231 1232 1233 /*IO Unit Page 10 */ 1234 1235 typedef struct _MPI2_IOUNIT10_FUNCTION { 1236 U8 CreditPercent; /*0x00 */ 1237 U8 Reserved1; /*0x01 */ 1238 U16 Reserved2; /*0x02 */ 1239 } MPI2_IOUNIT10_FUNCTION, 1240 *PTR_MPI2_IOUNIT10_FUNCTION, 1241 Mpi2IOUnit10Function_t, 1242 *pMpi2IOUnit10Function_t; 1243 1244 /* 1245 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1246 *one and check the value returned for NumFunctions at runtime. 1247 */ 1248 #ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES 1249 #define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES (1) 1250 #endif 1251 1252 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 { 1253 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1254 U8 NumFunctions; /*0x04 */ 1255 U8 Reserved1; /*0x05 */ 1256 U16 Reserved2; /*0x06 */ 1257 U32 Reserved3; /*0x08 */ 1258 U32 Reserved4; /*0x0C */ 1259 MPI2_IOUNIT10_FUNCTION 1260 Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];/*0x10 */ 1261 } MPI2_CONFIG_PAGE_IO_UNIT_10, 1262 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_10, 1263 Mpi2IOUnitPage10_t, *pMpi2IOUnitPage10_t; 1264 1265 #define MPI2_IOUNITPAGE10_PAGEVERSION (0x01) 1266 1267 1268 /* IO Unit Page 11 (for MPI v2.6 and later) */ 1269 1270 typedef struct _MPI26_IOUNIT11_SPINUP_GROUP { 1271 U8 MaxTargetSpinup; /* 0x00 */ 1272 U8 SpinupDelay; /* 0x01 */ 1273 U8 SpinupFlags; /* 0x02 */ 1274 U8 Reserved1; /* 0x03 */ 1275 } MPI26_IOUNIT11_SPINUP_GROUP, 1276 *PTR_MPI26_IOUNIT11_SPINUP_GROUP, 1277 Mpi26IOUnit11SpinupGroup_t, 1278 *pMpi26IOUnit11SpinupGroup_t; 1279 1280 /* defines for IO Unit Page 11 SpinupFlags */ 1281 #define MPI26_IOUNITPAGE11_SPINUP_DISABLE_FLAG (0x01) 1282 1283 1284 /* 1285 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1286 * four and check the value returned for NumPhys at runtime. 1287 */ 1288 #ifndef MPI26_IOUNITPAGE11_PHY_MAX 1289 #define MPI26_IOUNITPAGE11_PHY_MAX (4) 1290 #endif 1291 1292 typedef struct _MPI26_CONFIG_PAGE_IO_UNIT_11 { 1293 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1294 U32 Reserved1; /*0x04 */ 1295 MPI26_IOUNIT11_SPINUP_GROUP SpinupGroupParameters[4]; /*0x08 */ 1296 U32 Reserved2; /*0x18 */ 1297 U32 Reserved3; /*0x1C */ 1298 U32 Reserved4; /*0x20 */ 1299 U8 BootDeviceWaitTime; /*0x24 */ 1300 U8 Reserved5; /*0x25 */ 1301 U16 Reserved6; /*0x26 */ 1302 U8 NumPhys; /*0x28 */ 1303 U8 PEInitialSpinupDelay; /*0x29 */ 1304 U8 PEReplyDelay; /*0x2A */ 1305 U8 Flags; /*0x2B */ 1306 U8 PHY[MPI26_IOUNITPAGE11_PHY_MAX];/*0x2C */ 1307 } MPI26_CONFIG_PAGE_IO_UNIT_11, 1308 *PTR_MPI26_CONFIG_PAGE_IO_UNIT_11, 1309 Mpi26IOUnitPage11_t, 1310 *pMpi26IOUnitPage11_t; 1311 1312 #define MPI26_IOUNITPAGE11_PAGEVERSION (0x00) 1313 1314 /* defines for Flags field */ 1315 #define MPI26_IOUNITPAGE11_FLAGS_AUTO_PORTENABLE (0x01) 1316 1317 /* defines for PHY field */ 1318 #define MPI26_IOUNITPAGE11_PHY_SPINUP_GROUP_MASK (0x03) 1319 1320 1321 1322 1323 1324 1325 /**************************************************************************** 1326 * IOC Config Pages 1327 ****************************************************************************/ 1328 1329 /*IOC Page 0 */ 1330 1331 typedef struct _MPI2_CONFIG_PAGE_IOC_0 { 1332 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1333 U32 Reserved1; /*0x04 */ 1334 U32 Reserved2; /*0x08 */ 1335 U16 VendorID; /*0x0C */ 1336 U16 DeviceID; /*0x0E */ 1337 U8 RevisionID; /*0x10 */ 1338 U8 Reserved3; /*0x11 */ 1339 U16 Reserved4; /*0x12 */ 1340 U32 ClassCode; /*0x14 */ 1341 U16 SubsystemVendorID; /*0x18 */ 1342 U16 SubsystemID; /*0x1A */ 1343 } MPI2_CONFIG_PAGE_IOC_0, 1344 *PTR_MPI2_CONFIG_PAGE_IOC_0, 1345 Mpi2IOCPage0_t, *pMpi2IOCPage0_t; 1346 1347 #define MPI2_IOCPAGE0_PAGEVERSION (0x02) 1348 1349 1350 /*IOC Page 1 */ 1351 1352 typedef struct _MPI2_CONFIG_PAGE_IOC_1 { 1353 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1354 U32 Flags; /*0x04 */ 1355 U32 CoalescingTimeout; /*0x08 */ 1356 U8 CoalescingDepth; /*0x0C */ 1357 U8 PCISlotNum; /*0x0D */ 1358 U8 PCIBusNum; /*0x0E */ 1359 U8 PCIDomainSegment; /*0x0F */ 1360 U32 Reserved1; /*0x10 */ 1361 U32 Reserved2; /*0x14 */ 1362 } MPI2_CONFIG_PAGE_IOC_1, 1363 *PTR_MPI2_CONFIG_PAGE_IOC_1, 1364 Mpi2IOCPage1_t, *pMpi2IOCPage1_t; 1365 1366 #define MPI2_IOCPAGE1_PAGEVERSION (0x05) 1367 1368 /*defines for IOC Page 1 Flags field */ 1369 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001) 1370 1371 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 1372 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF) 1373 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF) 1374 1375 /*IOC Page 6 */ 1376 1377 typedef struct _MPI2_CONFIG_PAGE_IOC_6 { 1378 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1379 U32 1380 CapabilitiesFlags; /*0x04 */ 1381 U8 MaxDrivesRAID0; /*0x08 */ 1382 U8 MaxDrivesRAID1; /*0x09 */ 1383 U8 1384 MaxDrivesRAID1E; /*0x0A */ 1385 U8 1386 MaxDrivesRAID10; /*0x0B */ 1387 U8 MinDrivesRAID0; /*0x0C */ 1388 U8 MinDrivesRAID1; /*0x0D */ 1389 U8 1390 MinDrivesRAID1E; /*0x0E */ 1391 U8 1392 MinDrivesRAID10; /*0x0F */ 1393 U32 Reserved1; /*0x10 */ 1394 U8 1395 MaxGlobalHotSpares; /*0x14 */ 1396 U8 MaxPhysDisks; /*0x15 */ 1397 U8 MaxVolumes; /*0x16 */ 1398 U8 MaxConfigs; /*0x17 */ 1399 U8 MaxOCEDisks; /*0x18 */ 1400 U8 Reserved2; /*0x19 */ 1401 U16 Reserved3; /*0x1A */ 1402 U32 1403 SupportedStripeSizeMapRAID0; /*0x1C */ 1404 U32 1405 SupportedStripeSizeMapRAID1E; /*0x20 */ 1406 U32 1407 SupportedStripeSizeMapRAID10; /*0x24 */ 1408 U32 Reserved4; /*0x28 */ 1409 U32 Reserved5; /*0x2C */ 1410 U16 1411 DefaultMetadataSize; /*0x30 */ 1412 U16 Reserved6; /*0x32 */ 1413 U16 1414 MaxBadBlockTableEntries; /*0x34 */ 1415 U16 Reserved7; /*0x36 */ 1416 U32 1417 IRNvsramVersion; /*0x38 */ 1418 } MPI2_CONFIG_PAGE_IOC_6, 1419 *PTR_MPI2_CONFIG_PAGE_IOC_6, 1420 Mpi2IOCPage6_t, *pMpi2IOCPage6_t; 1421 1422 #define MPI2_IOCPAGE6_PAGEVERSION (0x05) 1423 1424 /*defines for IOC Page 6 CapabilitiesFlags */ 1425 #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT (0x00000020) 1426 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010) 1427 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008) 1428 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004) 1429 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002) 1430 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 1431 1432 1433 /*IOC Page 7 */ 1434 1435 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4) 1436 1437 typedef struct _MPI2_CONFIG_PAGE_IOC_7 { 1438 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1439 U32 Reserved1; /*0x04 */ 1440 U32 1441 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/*0x08 */ 1442 U16 SASBroadcastPrimitiveMasks; /*0x18 */ 1443 U16 SASNotifyPrimitiveMasks; /*0x1A */ 1444 U32 Reserved3; /*0x1C */ 1445 } MPI2_CONFIG_PAGE_IOC_7, 1446 *PTR_MPI2_CONFIG_PAGE_IOC_7, 1447 Mpi2IOCPage7_t, *pMpi2IOCPage7_t; 1448 1449 #define MPI2_IOCPAGE7_PAGEVERSION (0x02) 1450 1451 1452 /*IOC Page 8 */ 1453 1454 typedef struct _MPI2_CONFIG_PAGE_IOC_8 { 1455 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1456 U8 NumDevsPerEnclosure; /*0x04 */ 1457 U8 Reserved1; /*0x05 */ 1458 U16 Reserved2; /*0x06 */ 1459 U16 MaxPersistentEntries; /*0x08 */ 1460 U16 MaxNumPhysicalMappedIDs; /*0x0A */ 1461 U16 Flags; /*0x0C */ 1462 U16 Reserved3; /*0x0E */ 1463 U16 IRVolumeMappingFlags; /*0x10 */ 1464 U16 Reserved4; /*0x12 */ 1465 U32 Reserved5; /*0x14 */ 1466 } MPI2_CONFIG_PAGE_IOC_8, 1467 *PTR_MPI2_CONFIG_PAGE_IOC_8, 1468 Mpi2IOCPage8_t, *pMpi2IOCPage8_t; 1469 1470 #define MPI2_IOCPAGE8_PAGEVERSION (0x00) 1471 1472 /*defines for IOC Page 8 Flags field */ 1473 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020) 1474 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010) 1475 1476 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E) 1477 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000) 1478 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002) 1479 1480 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001) 1481 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000) 1482 1483 /*defines for IOC Page 8 IRVolumeMappingFlags */ 1484 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003) 1485 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000) 1486 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001) 1487 1488 1489 /**************************************************************************** 1490 * BIOS Config Pages 1491 ****************************************************************************/ 1492 1493 /*BIOS Page 1 */ 1494 1495 typedef struct _MPI2_CONFIG_PAGE_BIOS_1 { 1496 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1497 U32 BiosOptions; /*0x04 */ 1498 U32 IOCSettings; /*0x08 */ 1499 U8 SSUTimeout; /*0x0C */ 1500 U8 Reserved1; /*0x0D */ 1501 U16 Reserved2; /*0x0E */ 1502 U32 DeviceSettings; /*0x10 */ 1503 U16 NumberOfDevices; /*0x14 */ 1504 U16 UEFIVersion; /*0x16 */ 1505 U16 IOTimeoutBlockDevicesNonRM; /*0x18 */ 1506 U16 IOTimeoutSequential; /*0x1A */ 1507 U16 IOTimeoutOther; /*0x1C */ 1508 U16 IOTimeoutBlockDevicesRM; /*0x1E */ 1509 } MPI2_CONFIG_PAGE_BIOS_1, 1510 *PTR_MPI2_CONFIG_PAGE_BIOS_1, 1511 Mpi2BiosPage1_t, *pMpi2BiosPage1_t; 1512 1513 #define MPI2_BIOSPAGE1_PAGEVERSION (0x07) 1514 1515 /*values for BIOS Page 1 BiosOptions field */ 1516 #define MPI2_BIOSPAGE1_OPTIONS_BOOT_LIST_ADD_ALT_BOOT_DEVICE (0x00008000) 1517 #define MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG (0x00004000) 1518 1519 #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800) 1520 #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800) 1521 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL (0x00000000) 1522 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE (0x00000800) 1523 #define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID (0x00001000) 1524 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PSENS (0x00001800) 1525 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ESPHY (0x00002000) 1526 1527 #define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS (0x00000400) 1528 1529 #define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD (0x00000300) 1530 #define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD (0x00000000) 1531 #define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD (0x00000100) 1532 #define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD (0x00000200) 1533 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD (0x00000300) 1534 1535 #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0) 1536 #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000) 1537 1538 #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006) 1539 #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000) 1540 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002) 1541 #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004) 1542 1543 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1544 1545 /*values for BIOS Page 1 IOCSettings field */ 1546 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1547 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1548 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1549 1550 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1551 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1552 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1553 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1554 1555 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1556 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1557 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1558 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1559 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1560 1561 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1562 1563 /*values for BIOS Page 1 DeviceSettings field */ 1564 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 1565 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1566 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1567 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1568 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1569 1570 /*defines for BIOS Page 1 UEFIVersion field */ 1571 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK (0xFF00) 1572 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT (8) 1573 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK (0x00FF) 1574 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT (0) 1575 1576 1577 1578 /*BIOS Page 2 */ 1579 1580 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER { 1581 U32 Reserved1; /*0x00 */ 1582 U32 Reserved2; /*0x04 */ 1583 U32 Reserved3; /*0x08 */ 1584 U32 Reserved4; /*0x0C */ 1585 U32 Reserved5; /*0x10 */ 1586 U32 Reserved6; /*0x14 */ 1587 } MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1588 *PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1589 Mpi2BootDeviceAdapterOrder_t, 1590 *pMpi2BootDeviceAdapterOrder_t; 1591 1592 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID { 1593 U64 SASAddress; /*0x00 */ 1594 U8 LUN[8]; /*0x08 */ 1595 U32 Reserved1; /*0x10 */ 1596 U32 Reserved2; /*0x14 */ 1597 } MPI2_BOOT_DEVICE_SAS_WWID, 1598 *PTR_MPI2_BOOT_DEVICE_SAS_WWID, 1599 Mpi2BootDeviceSasWwid_t, 1600 *pMpi2BootDeviceSasWwid_t; 1601 1602 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT { 1603 U64 EnclosureLogicalID; /*0x00 */ 1604 U32 Reserved1; /*0x08 */ 1605 U32 Reserved2; /*0x0C */ 1606 U16 SlotNumber; /*0x10 */ 1607 U16 Reserved3; /*0x12 */ 1608 U32 Reserved4; /*0x14 */ 1609 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1610 *PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1611 Mpi2BootDeviceEnclosureSlot_t, 1612 *pMpi2BootDeviceEnclosureSlot_t; 1613 1614 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME { 1615 U64 DeviceName; /*0x00 */ 1616 U8 LUN[8]; /*0x08 */ 1617 U32 Reserved1; /*0x10 */ 1618 U32 Reserved2; /*0x14 */ 1619 } MPI2_BOOT_DEVICE_DEVICE_NAME, 1620 *PTR_MPI2_BOOT_DEVICE_DEVICE_NAME, 1621 Mpi2BootDeviceDeviceName_t, 1622 *pMpi2BootDeviceDeviceName_t; 1623 1624 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE { 1625 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1626 MPI2_BOOT_DEVICE_SAS_WWID SasWwid; 1627 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1628 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName; 1629 } MPI2_BIOSPAGE2_BOOT_DEVICE, 1630 *PTR_MPI2_BIOSPAGE2_BOOT_DEVICE, 1631 Mpi2BiosPage2BootDevice_t, 1632 *pMpi2BiosPage2BootDevice_t; 1633 1634 typedef struct _MPI2_CONFIG_PAGE_BIOS_2 { 1635 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1636 U32 Reserved1; /*0x04 */ 1637 U32 Reserved2; /*0x08 */ 1638 U32 Reserved3; /*0x0C */ 1639 U32 Reserved4; /*0x10 */ 1640 U32 Reserved5; /*0x14 */ 1641 U32 Reserved6; /*0x18 */ 1642 U8 ReqBootDeviceForm; /*0x1C */ 1643 U8 Reserved7; /*0x1D */ 1644 U16 Reserved8; /*0x1E */ 1645 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /*0x20 */ 1646 U8 ReqAltBootDeviceForm; /*0x38 */ 1647 U8 Reserved9; /*0x39 */ 1648 U16 Reserved10; /*0x3A */ 1649 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /*0x3C */ 1650 U8 CurrentBootDeviceForm; /*0x58 */ 1651 U8 Reserved11; /*0x59 */ 1652 U16 Reserved12; /*0x5A */ 1653 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /*0x58 */ 1654 } MPI2_CONFIG_PAGE_BIOS_2, *PTR_MPI2_CONFIG_PAGE_BIOS_2, 1655 Mpi2BiosPage2_t, *pMpi2BiosPage2_t; 1656 1657 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04) 1658 1659 /*values for BIOS Page 2 BootDeviceForm fields */ 1660 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F) 1661 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00) 1662 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05) 1663 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1664 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07) 1665 1666 1667 /*BIOS Page 3 */ 1668 1669 #define MPI2_BIOSPAGE3_NUM_ADAPTER (4) 1670 1671 typedef struct _MPI2_ADAPTER_INFO { 1672 U8 PciBusNumber; /*0x00 */ 1673 U8 PciDeviceAndFunctionNumber; /*0x01 */ 1674 U16 AdapterFlags; /*0x02 */ 1675 } MPI2_ADAPTER_INFO, *PTR_MPI2_ADAPTER_INFO, 1676 Mpi2AdapterInfo_t, *pMpi2AdapterInfo_t; 1677 1678 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 1679 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 1680 1681 typedef struct _MPI2_ADAPTER_ORDER_AUX { 1682 U64 WWID; /* 0x00 */ 1683 U32 Reserved1; /* 0x08 */ 1684 U32 Reserved2; /* 0x0C */ 1685 } MPI2_ADAPTER_ORDER_AUX, *PTR_MPI2_ADAPTER_ORDER_AUX, 1686 Mpi2AdapterOrderAux_t, *pMpi2AdapterOrderAux_t; 1687 1688 1689 typedef struct _MPI2_CONFIG_PAGE_BIOS_3 { 1690 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1691 U32 GlobalFlags; /*0x04 */ 1692 U32 BiosVersion; /*0x08 */ 1693 MPI2_ADAPTER_INFO AdapterOrder[MPI2_BIOSPAGE3_NUM_ADAPTER]; 1694 U32 Reserved1; /*0x1C */ 1695 MPI2_ADAPTER_ORDER_AUX AdapterOrderAux[MPI2_BIOSPAGE3_NUM_ADAPTER]; 1696 } MPI2_CONFIG_PAGE_BIOS_3, 1697 *PTR_MPI2_CONFIG_PAGE_BIOS_3, 1698 Mpi2BiosPage3_t, *pMpi2BiosPage3_t; 1699 1700 #define MPI2_BIOSPAGE3_PAGEVERSION (0x01) 1701 1702 /*values for BIOS Page 3 GlobalFlags */ 1703 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) 1704 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004) 1705 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010) 1706 1707 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 1708 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 1709 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020) 1710 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 1711 1712 1713 /*BIOS Page 4 */ 1714 1715 /* 1716 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1717 *one and check the value returned for NumPhys at runtime. 1718 */ 1719 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES 1720 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1) 1721 #endif 1722 1723 typedef struct _MPI2_BIOS4_ENTRY { 1724 U64 ReassignmentWWID; /*0x00 */ 1725 U64 ReassignmentDeviceName; /*0x08 */ 1726 } MPI2_BIOS4_ENTRY, *PTR_MPI2_BIOS4_ENTRY, 1727 Mpi2MBios4Entry_t, *pMpi2Bios4Entry_t; 1728 1729 typedef struct _MPI2_CONFIG_PAGE_BIOS_4 { 1730 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1731 U8 NumPhys; /*0x04 */ 1732 U8 Reserved1; /*0x05 */ 1733 U16 Reserved2; /*0x06 */ 1734 MPI2_BIOS4_ENTRY 1735 Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /*0x08 */ 1736 } MPI2_CONFIG_PAGE_BIOS_4, *PTR_MPI2_CONFIG_PAGE_BIOS_4, 1737 Mpi2BiosPage4_t, *pMpi2BiosPage4_t; 1738 1739 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01) 1740 1741 1742 /**************************************************************************** 1743 * RAID Volume Config Pages 1744 ****************************************************************************/ 1745 1746 /*RAID Volume Page 0 */ 1747 1748 typedef struct _MPI2_RAIDVOL0_PHYS_DISK { 1749 U8 RAIDSetNum; /*0x00 */ 1750 U8 PhysDiskMap; /*0x01 */ 1751 U8 PhysDiskNum; /*0x02 */ 1752 U8 Reserved; /*0x03 */ 1753 } MPI2_RAIDVOL0_PHYS_DISK, *PTR_MPI2_RAIDVOL0_PHYS_DISK, 1754 Mpi2RaidVol0PhysDisk_t, *pMpi2RaidVol0PhysDisk_t; 1755 1756 /*defines for the PhysDiskMap field */ 1757 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1758 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1759 1760 typedef struct _MPI2_RAIDVOL0_SETTINGS { 1761 U16 Settings; /*0x00 */ 1762 U8 HotSparePool; /*0x01 */ 1763 U8 Reserved; /*0x02 */ 1764 } MPI2_RAIDVOL0_SETTINGS, *PTR_MPI2_RAIDVOL0_SETTINGS, 1765 Mpi2RaidVol0Settings_t, 1766 *pMpi2RaidVol0Settings_t; 1767 1768 /*RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1769 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01) 1770 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02) 1771 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04) 1772 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08) 1773 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10) 1774 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20) 1775 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40) 1776 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80) 1777 1778 /*RAID Volume Page 0 VolumeSettings defines */ 1779 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008) 1780 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004) 1781 1782 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003) 1783 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000) 1784 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001) 1785 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002) 1786 1787 /* 1788 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1789 *one and check the value returned for NumPhysDisks at runtime. 1790 */ 1791 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX 1792 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 1793 #endif 1794 1795 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 { 1796 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1797 U16 DevHandle; /*0x04 */ 1798 U8 VolumeState; /*0x06 */ 1799 U8 VolumeType; /*0x07 */ 1800 U32 VolumeStatusFlags; /*0x08 */ 1801 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /*0x0C */ 1802 U64 MaxLBA; /*0x10 */ 1803 U32 StripeSize; /*0x18 */ 1804 U16 BlockSize; /*0x1C */ 1805 U16 Reserved1; /*0x1E */ 1806 U8 SupportedPhysDisks;/*0x20 */ 1807 U8 ResyncRate; /*0x21 */ 1808 U16 DataScrubDuration; /*0x22 */ 1809 U8 NumPhysDisks; /*0x24 */ 1810 U8 Reserved2; /*0x25 */ 1811 U8 Reserved3; /*0x26 */ 1812 U8 InactiveStatus; /*0x27 */ 1813 MPI2_RAIDVOL0_PHYS_DISK 1814 PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /*0x28 */ 1815 } MPI2_CONFIG_PAGE_RAID_VOL_0, 1816 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_0, 1817 Mpi2RaidVolPage0_t, *pMpi2RaidVolPage0_t; 1818 1819 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A) 1820 1821 /*values for RAID VolumeState */ 1822 #define MPI2_RAID_VOL_STATE_MISSING (0x00) 1823 #define MPI2_RAID_VOL_STATE_FAILED (0x01) 1824 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02) 1825 #define MPI2_RAID_VOL_STATE_ONLINE (0x03) 1826 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04) 1827 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05) 1828 1829 /*values for RAID VolumeType */ 1830 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00) 1831 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01) 1832 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02) 1833 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05) 1834 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF) 1835 1836 /*values for RAID Volume Page 0 VolumeStatusFlags field */ 1837 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000) 1838 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000) 1839 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000) 1840 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000) 1841 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000) 1842 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000) 1843 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000) 1844 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000) 1845 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000) 1846 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000) 1847 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080) 1848 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040) 1849 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020) 1850 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000) 1851 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010) 1852 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008) 1853 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004) 1854 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002) 1855 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001) 1856 1857 /*values for RAID Volume Page 0 SupportedPhysDisks field */ 1858 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08) 1859 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04) 1860 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02) 1861 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01) 1862 1863 /*values for RAID Volume Page 0 InactiveStatus field */ 1864 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 1865 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 1866 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 1867 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 1868 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 1869 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 1870 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 1871 1872 1873 /*RAID Volume Page 1 */ 1874 1875 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 { 1876 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1877 U16 DevHandle; /*0x04 */ 1878 U16 Reserved0; /*0x06 */ 1879 U8 GUID[24]; /*0x08 */ 1880 U8 Name[16]; /*0x20 */ 1881 U64 WWID; /*0x30 */ 1882 U32 Reserved1; /*0x38 */ 1883 U32 Reserved2; /*0x3C */ 1884 } MPI2_CONFIG_PAGE_RAID_VOL_1, 1885 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_1, 1886 Mpi2RaidVolPage1_t, *pMpi2RaidVolPage1_t; 1887 1888 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03) 1889 1890 1891 /**************************************************************************** 1892 * RAID Physical Disk Config Pages 1893 ****************************************************************************/ 1894 1895 /*RAID Physical Disk Page 0 */ 1896 1897 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS { 1898 U16 Reserved1; /*0x00 */ 1899 U8 HotSparePool; /*0x02 */ 1900 U8 Reserved2; /*0x03 */ 1901 } MPI2_RAIDPHYSDISK0_SETTINGS, 1902 *PTR_MPI2_RAIDPHYSDISK0_SETTINGS, 1903 Mpi2RaidPhysDisk0Settings_t, 1904 *pMpi2RaidPhysDisk0Settings_t; 1905 1906 /*use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */ 1907 1908 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA { 1909 U8 VendorID[8]; /*0x00 */ 1910 U8 ProductID[16]; /*0x08 */ 1911 U8 ProductRevLevel[4]; /*0x18 */ 1912 U8 SerialNum[32]; /*0x1C */ 1913 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1914 *PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1915 Mpi2RaidPhysDisk0InquiryData_t, 1916 *pMpi2RaidPhysDisk0InquiryData_t; 1917 1918 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 { 1919 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1920 U16 DevHandle; /*0x04 */ 1921 U8 Reserved1; /*0x06 */ 1922 U8 PhysDiskNum; /*0x07 */ 1923 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /*0x08 */ 1924 U32 Reserved2; /*0x0C */ 1925 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /*0x10 */ 1926 U32 Reserved3; /*0x4C */ 1927 U8 PhysDiskState; /*0x50 */ 1928 U8 OfflineReason; /*0x51 */ 1929 U8 IncompatibleReason; /*0x52 */ 1930 U8 PhysDiskAttributes; /*0x53 */ 1931 U32 PhysDiskStatusFlags;/*0x54 */ 1932 U64 DeviceMaxLBA; /*0x58 */ 1933 U64 HostMaxLBA; /*0x60 */ 1934 U64 CoercedMaxLBA; /*0x68 */ 1935 U16 BlockSize; /*0x70 */ 1936 U16 Reserved5; /*0x72 */ 1937 U32 Reserved6; /*0x74 */ 1938 } MPI2_CONFIG_PAGE_RD_PDISK_0, 1939 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_0, 1940 Mpi2RaidPhysDiskPage0_t, 1941 *pMpi2RaidPhysDiskPage0_t; 1942 1943 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05) 1944 1945 /*PhysDiskState defines */ 1946 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00) 1947 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01) 1948 #define MPI2_RAID_PD_STATE_OFFLINE (0x02) 1949 #define MPI2_RAID_PD_STATE_ONLINE (0x03) 1950 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04) 1951 #define MPI2_RAID_PD_STATE_DEGRADED (0x05) 1952 #define MPI2_RAID_PD_STATE_REBUILDING (0x06) 1953 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07) 1954 1955 /*OfflineReason defines */ 1956 #define MPI2_PHYSDISK0_ONLINE (0x00) 1957 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01) 1958 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03) 1959 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04) 1960 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05) 1961 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06) 1962 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF) 1963 1964 /*IncompatibleReason defines */ 1965 #define MPI2_PHYSDISK0_COMPATIBLE (0x00) 1966 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01) 1967 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02) 1968 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03) 1969 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04) 1970 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05) 1971 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06) 1972 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF) 1973 1974 /*PhysDiskAttributes defines */ 1975 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C) 1976 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08) 1977 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04) 1978 1979 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03) 1980 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02) 1981 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01) 1982 1983 /*PhysDiskStatusFlags defines */ 1984 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040) 1985 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020) 1986 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010) 1987 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000) 1988 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008) 1989 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004) 1990 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002) 1991 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001) 1992 1993 1994 /*RAID Physical Disk Page 1 */ 1995 1996 /* 1997 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1998 *one and check the value returned for NumPhysDiskPaths at runtime. 1999 */ 2000 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX 2001 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1) 2002 #endif 2003 2004 typedef struct _MPI2_RAIDPHYSDISK1_PATH { 2005 U16 DevHandle; /*0x00 */ 2006 U16 Reserved1; /*0x02 */ 2007 U64 WWID; /*0x04 */ 2008 U64 OwnerWWID; /*0x0C */ 2009 U8 OwnerIdentifier; /*0x14 */ 2010 U8 Reserved2; /*0x15 */ 2011 U16 Flags; /*0x16 */ 2012 } MPI2_RAIDPHYSDISK1_PATH, *PTR_MPI2_RAIDPHYSDISK1_PATH, 2013 Mpi2RaidPhysDisk1Path_t, 2014 *pMpi2RaidPhysDisk1Path_t; 2015 2016 /*RAID Physical Disk Page 1 Physical Disk Path Flags field defines */ 2017 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004) 2018 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 2019 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 2020 2021 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 { 2022 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 2023 U8 NumPhysDiskPaths; /*0x04 */ 2024 U8 PhysDiskNum; /*0x05 */ 2025 U16 Reserved1; /*0x06 */ 2026 U32 Reserved2; /*0x08 */ 2027 MPI2_RAIDPHYSDISK1_PATH 2028 PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/*0x0C */ 2029 } MPI2_CONFIG_PAGE_RD_PDISK_1, 2030 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_1, 2031 Mpi2RaidPhysDiskPage1_t, 2032 *pMpi2RaidPhysDiskPage1_t; 2033 2034 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02) 2035 2036 2037 /**************************************************************************** 2038 * values for fields used by several types of SAS Config Pages 2039 ****************************************************************************/ 2040 2041 /*values for NegotiatedLinkRates fields */ 2042 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0) 2043 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4) 2044 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 2045 /*link rates used for Negotiated Physical and Logical Link Rate */ 2046 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 2047 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 2048 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 2049 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 2050 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 2051 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 2052 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 2053 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08) 2054 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09) 2055 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A) 2056 #define MPI25_SAS_NEG_LINK_RATE_12_0 (0x0B) 2057 #define MPI26_SAS_NEG_LINK_RATE_22_5 (0x0C) 2058 2059 2060 /*values for AttachedPhyInfo fields */ 2061 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 2062 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 2063 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 2064 2065 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F) 2066 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 2067 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 2068 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 2069 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 2070 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 2071 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 2072 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 2073 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 2074 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 2075 2076 2077 /*values for PhyInfo fields */ 2078 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000) 2079 2080 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 2081 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27) 2082 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000) 2083 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000) 2084 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000) 2085 2086 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000) 2087 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000) 2088 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000) 2089 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 2090 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000) 2091 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 2092 2093 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000) 2094 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 2095 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 2096 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 2097 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 2098 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 2099 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 2100 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 2101 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 2102 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 2103 2104 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000) 2105 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 2106 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 2107 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 2108 2109 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 2110 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 2111 2112 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 2113 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000) 2114 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 2115 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020) 2116 2117 2118 /*values for SAS ProgrammedLinkRate fields */ 2119 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0) 2120 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 2121 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80) 2122 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90) 2123 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0) 2124 #define MPI25_SAS_PRATE_MAX_RATE_12_0 (0xB0) 2125 #define MPI26_SAS_PRATE_MAX_RATE_22_5 (0xC0) 2126 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F) 2127 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 2128 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08) 2129 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09) 2130 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A) 2131 #define MPI25_SAS_PRATE_MIN_RATE_12_0 (0x0B) 2132 #define MPI26_SAS_PRATE_MIN_RATE_22_5 (0x0C) 2133 2134 2135 /*values for SAS HwLinkRate fields */ 2136 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0) 2137 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80) 2138 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90) 2139 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0) 2140 #define MPI25_SAS_HWRATE_MAX_RATE_12_0 (0xB0) 2141 #define MPI26_SAS_HWRATE_MAX_RATE_22_5 (0xC0) 2142 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F) 2143 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08) 2144 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09) 2145 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A) 2146 #define MPI25_SAS_HWRATE_MIN_RATE_12_0 (0x0B) 2147 #define MPI26_SAS_HWRATE_MIN_RATE_22_5 (0x0C) 2148 2149 2150 2151 /**************************************************************************** 2152 * SAS IO Unit Config Pages 2153 ****************************************************************************/ 2154 2155 /*SAS IO Unit Page 0 */ 2156 2157 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA { 2158 U8 Port; /*0x00 */ 2159 U8 PortFlags; /*0x01 */ 2160 U8 PhyFlags; /*0x02 */ 2161 U8 NegotiatedLinkRate; /*0x03 */ 2162 U32 ControllerPhyDeviceInfo;/*0x04 */ 2163 U16 AttachedDevHandle; /*0x08 */ 2164 U16 ControllerDevHandle; /*0x0A */ 2165 U32 DiscoveryStatus; /*0x0C */ 2166 U32 Reserved; /*0x10 */ 2167 } MPI2_SAS_IO_UNIT0_PHY_DATA, 2168 *PTR_MPI2_SAS_IO_UNIT0_PHY_DATA, 2169 Mpi2SasIOUnit0PhyData_t, 2170 *pMpi2SasIOUnit0PhyData_t; 2171 2172 /* 2173 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2174 *one and check the value returned for NumPhys at runtime. 2175 */ 2176 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX 2177 #define MPI2_SAS_IOUNIT0_PHY_MAX (1) 2178 #endif 2179 2180 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 { 2181 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2182 U32 Reserved1;/*0x08 */ 2183 U8 NumPhys; /*0x0C */ 2184 U8 Reserved2;/*0x0D */ 2185 U16 Reserved3;/*0x0E */ 2186 MPI2_SAS_IO_UNIT0_PHY_DATA 2187 PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /*0x10 */ 2188 } MPI2_CONFIG_PAGE_SASIOUNIT_0, 2189 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0, 2190 Mpi2SasIOUnitPage0_t, *pMpi2SasIOUnitPage0_t; 2191 2192 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05) 2193 2194 /*values for SAS IO Unit Page 0 PortFlags */ 2195 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08) 2196 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) 2197 2198 /*values for SAS IO Unit Page 0 PhyFlags */ 2199 #define MPI2_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2200 #define MPI2_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2201 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) 2202 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 2203 2204 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2205 2206 /*see mpi2_sas.h for values for 2207 *SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 2208 2209 /*values for SAS IO Unit Page 0 DiscoveryStatus */ 2210 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2211 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2212 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000) 2213 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2214 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2215 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2216 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2217 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 2218 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2219 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 2220 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400) 2221 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 2222 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 2223 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 2224 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 2225 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2226 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010) 2227 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 2228 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2229 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001) 2230 2231 2232 /*SAS IO Unit Page 1 */ 2233 2234 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA { 2235 U8 Port; /*0x00 */ 2236 U8 PortFlags; /*0x01 */ 2237 U8 PhyFlags; /*0x02 */ 2238 U8 MaxMinLinkRate; /*0x03 */ 2239 U32 ControllerPhyDeviceInfo; /*0x04 */ 2240 U16 MaxTargetPortConnectTime; /*0x08 */ 2241 U16 Reserved1; /*0x0A */ 2242 } MPI2_SAS_IO_UNIT1_PHY_DATA, 2243 *PTR_MPI2_SAS_IO_UNIT1_PHY_DATA, 2244 Mpi2SasIOUnit1PhyData_t, 2245 *pMpi2SasIOUnit1PhyData_t; 2246 2247 /* 2248 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2249 *one and check the value returned for NumPhys at runtime. 2250 */ 2251 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX 2252 #define MPI2_SAS_IOUNIT1_PHY_MAX (1) 2253 #endif 2254 2255 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 { 2256 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2257 U16 2258 ControlFlags; /*0x08 */ 2259 U16 2260 SASNarrowMaxQueueDepth; /*0x0A */ 2261 U16 2262 AdditionalControlFlags; /*0x0C */ 2263 U16 2264 SASWideMaxQueueDepth; /*0x0E */ 2265 U8 2266 NumPhys; /*0x10 */ 2267 U8 2268 SATAMaxQDepth; /*0x11 */ 2269 U8 2270 ReportDeviceMissingDelay; /*0x12 */ 2271 U8 2272 IODeviceMissingDelay; /*0x13 */ 2273 MPI2_SAS_IO_UNIT1_PHY_DATA 2274 PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /*0x14 */ 2275 } MPI2_CONFIG_PAGE_SASIOUNIT_1, 2276 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1, 2277 Mpi2SasIOUnitPage1_t, *pMpi2SasIOUnitPage1_t; 2278 2279 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09) 2280 2281 /*values for SAS IO Unit Page 1 ControlFlags */ 2282 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 2283 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 2284 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) 2285 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 2286 2287 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 2288 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 2289 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0) 2290 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1) 2291 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2) 2292 2293 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 2294 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 2295 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 2296 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 2297 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 2298 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 2299 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 2300 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) 2301 2302 /*values for SAS IO Unit Page 1 AdditionalControlFlags */ 2303 #define MPI2_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100) 2304 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 2305 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 2306 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 2307 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 2308 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 2309 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 2310 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 2311 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 2312 2313 /*defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 2314 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 2315 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 2316 2317 /*values for SAS IO Unit Page 1 PortFlags */ 2318 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2319 2320 /*values for SAS IO Unit Page 1 PhyFlags */ 2321 #define MPI2_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2322 #define MPI2_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2323 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) 2324 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 2325 2326 /*values for SAS IO Unit Page 1 MaxMinLinkRate */ 2327 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) 2328 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) 2329 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) 2330 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) 2331 #define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0) 2332 #define MPI26_SASIOUNIT1_MAX_RATE_22_5 (0xC0) 2333 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) 2334 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) 2335 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) 2336 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) 2337 #define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B) 2338 #define MPI26_SASIOUNIT1_MIN_RATE_22_5 (0x0C) 2339 2340 /*see mpi2_sas.h for values for 2341 *SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 2342 2343 2344 /*SAS IO Unit Page 4 (for MPI v2.5 and earlier) */ 2345 2346 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP { 2347 U8 MaxTargetSpinup; /*0x00 */ 2348 U8 SpinupDelay; /*0x01 */ 2349 U8 SpinupFlags; /*0x02 */ 2350 U8 Reserved1; /*0x03 */ 2351 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, 2352 *PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP, 2353 Mpi2SasIOUnit4SpinupGroup_t, 2354 *pMpi2SasIOUnit4SpinupGroup_t; 2355 /*defines for SAS IO Unit Page 4 SpinupFlags */ 2356 #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01) 2357 2358 2359 /* 2360 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2361 *one and check the value returned for NumPhys at runtime. 2362 */ 2363 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX 2364 #define MPI2_SAS_IOUNIT4_PHY_MAX (4) 2365 #endif 2366 2367 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 { 2368 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header;/*0x00 */ 2369 MPI2_SAS_IOUNIT4_SPINUP_GROUP 2370 SpinupGroupParameters[4]; /*0x08 */ 2371 U32 2372 Reserved1; /*0x18 */ 2373 U32 2374 Reserved2; /*0x1C */ 2375 U32 2376 Reserved3; /*0x20 */ 2377 U8 2378 BootDeviceWaitTime; /*0x24 */ 2379 U8 2380 SATADeviceWaitTime; /*0x25 */ 2381 U16 2382 Reserved5; /*0x26 */ 2383 U8 2384 NumPhys; /*0x28 */ 2385 U8 2386 PEInitialSpinupDelay; /*0x29 */ 2387 U8 2388 PEReplyDelay; /*0x2A */ 2389 U8 2390 Flags; /*0x2B */ 2391 U8 2392 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /*0x2C */ 2393 } MPI2_CONFIG_PAGE_SASIOUNIT_4, 2394 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4, 2395 Mpi2SasIOUnitPage4_t, *pMpi2SasIOUnitPage4_t; 2396 2397 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02) 2398 2399 /*defines for Flags field */ 2400 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01) 2401 2402 /*defines for PHY field */ 2403 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03) 2404 2405 2406 /*SAS IO Unit Page 5 */ 2407 2408 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS { 2409 U8 ControlFlags; /*0x00 */ 2410 U8 PortWidthModGroup; /*0x01 */ 2411 U16 InactivityTimerExponent; /*0x02 */ 2412 U8 SATAPartialTimeout; /*0x04 */ 2413 U8 Reserved2; /*0x05 */ 2414 U8 SATASlumberTimeout; /*0x06 */ 2415 U8 Reserved3; /*0x07 */ 2416 U8 SASPartialTimeout; /*0x08 */ 2417 U8 Reserved4; /*0x09 */ 2418 U8 SASSlumberTimeout; /*0x0A */ 2419 U8 Reserved5; /*0x0B */ 2420 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2421 *PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2422 Mpi2SasIOUnit5PhyPmSettings_t, 2423 *pMpi2SasIOUnit5PhyPmSettings_t; 2424 2425 /*defines for ControlFlags field */ 2426 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08) 2427 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04) 2428 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02) 2429 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01) 2430 2431 /*defines for PortWidthModeGroup field */ 2432 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF) 2433 2434 /*defines for InactivityTimerExponent field */ 2435 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000) 2436 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12) 2437 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700) 2438 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8) 2439 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070) 2440 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4) 2441 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007) 2442 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0) 2443 2444 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7) 2445 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6) 2446 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5) 2447 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4) 2448 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3) 2449 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2) 2450 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1) 2451 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0) 2452 2453 /* 2454 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2455 *one and check the value returned for NumPhys at runtime. 2456 */ 2457 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX 2458 #define MPI2_SAS_IOUNIT5_PHY_MAX (1) 2459 #endif 2460 2461 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 { 2462 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2463 U8 NumPhys; /*0x08 */ 2464 U8 Reserved1;/*0x09 */ 2465 U16 Reserved2;/*0x0A */ 2466 U32 Reserved3;/*0x0C */ 2467 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS 2468 SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX];/*0x10 */ 2469 } MPI2_CONFIG_PAGE_SASIOUNIT_5, 2470 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5, 2471 Mpi2SasIOUnitPage5_t, *pMpi2SasIOUnitPage5_t; 2472 2473 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01) 2474 2475 2476 /*SAS IO Unit Page 6 */ 2477 2478 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS { 2479 U8 CurrentStatus; /*0x00 */ 2480 U8 CurrentModulation; /*0x01 */ 2481 U8 CurrentUtilization; /*0x02 */ 2482 U8 Reserved1; /*0x03 */ 2483 U32 Reserved2; /*0x04 */ 2484 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2485 *PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2486 Mpi2SasIOUnit6PortWidthModGroupStatus_t, 2487 *pMpi2SasIOUnit6PortWidthModGroupStatus_t; 2488 2489 /*defines for CurrentStatus field */ 2490 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00) 2491 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01) 2492 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02) 2493 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03) 2494 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04) 2495 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05) 2496 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06) 2497 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07) 2498 2499 /*defines for CurrentModulation field */ 2500 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00) 2501 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01) 2502 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02) 2503 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03) 2504 2505 /* 2506 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2507 *one and check the value returned for NumGroups at runtime. 2508 */ 2509 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX 2510 #define MPI2_SAS_IOUNIT6_GROUP_MAX (1) 2511 #endif 2512 2513 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 { 2514 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2515 U32 Reserved1; /*0x08 */ 2516 U32 Reserved2; /*0x0C */ 2517 U8 NumGroups; /*0x10 */ 2518 U8 Reserved3; /*0x11 */ 2519 U16 Reserved4; /*0x12 */ 2520 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 2521 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /*0x14 */ 2522 } MPI2_CONFIG_PAGE_SASIOUNIT_6, 2523 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6, 2524 Mpi2SasIOUnitPage6_t, *pMpi2SasIOUnitPage6_t; 2525 2526 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00) 2527 2528 2529 /*SAS IO Unit Page 7 */ 2530 2531 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS { 2532 U8 Flags; /*0x00 */ 2533 U8 Reserved1; /*0x01 */ 2534 U16 Reserved2; /*0x02 */ 2535 U8 Threshold75Pct; /*0x04 */ 2536 U8 Threshold50Pct; /*0x05 */ 2537 U8 Threshold25Pct; /*0x06 */ 2538 U8 Reserved3; /*0x07 */ 2539 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2540 *PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2541 Mpi2SasIOUnit7PortWidthModGroupSettings_t, 2542 *pMpi2SasIOUnit7PortWidthModGroupSettings_t; 2543 2544 /*defines for Flags field */ 2545 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01) 2546 2547 2548 /* 2549 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2550 *one and check the value returned for NumGroups at runtime. 2551 */ 2552 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX 2553 #define MPI2_SAS_IOUNIT7_GROUP_MAX (1) 2554 #endif 2555 2556 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 { 2557 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2558 U8 SamplingInterval; /*0x08 */ 2559 U8 WindowLength; /*0x09 */ 2560 U16 Reserved1; /*0x0A */ 2561 U32 Reserved2; /*0x0C */ 2562 U32 Reserved3; /*0x10 */ 2563 U8 NumGroups; /*0x14 */ 2564 U8 Reserved4; /*0x15 */ 2565 U16 Reserved5; /*0x16 */ 2566 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2567 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX];/*0x18 */ 2568 } MPI2_CONFIG_PAGE_SASIOUNIT_7, 2569 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7, 2570 Mpi2SasIOUnitPage7_t, *pMpi2SasIOUnitPage7_t; 2571 2572 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00) 2573 2574 2575 /*SAS IO Unit Page 8 */ 2576 2577 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 { 2578 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2579 Header; /*0x00 */ 2580 U32 2581 Reserved1; /*0x08 */ 2582 U32 2583 PowerManagementCapabilities; /*0x0C */ 2584 U8 2585 TxRxSleepStatus; /*0x10 */ 2586 U8 2587 Reserved2; /*0x11 */ 2588 U16 2589 Reserved3; /*0x12 */ 2590 } MPI2_CONFIG_PAGE_SASIOUNIT_8, 2591 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8, 2592 Mpi2SasIOUnitPage8_t, *pMpi2SasIOUnitPage8_t; 2593 2594 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00) 2595 2596 /*defines for PowerManagementCapabilities field */ 2597 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000) 2598 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800) 2599 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400) 2600 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200) 2601 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100) 2602 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010) 2603 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008) 2604 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004) 2605 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002) 2606 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001) 2607 2608 /*defines for TxRxSleepStatus field */ 2609 #define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED (0x00) 2610 #define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED (0x01) 2611 #define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE (0x02) 2612 #define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN (0x03) 2613 2614 2615 2616 /*SAS IO Unit Page 16 */ 2617 2618 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 { 2619 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2620 Header; /*0x00 */ 2621 U64 2622 TimeStamp; /*0x08 */ 2623 U32 2624 Reserved1; /*0x10 */ 2625 U32 2626 Reserved2; /*0x14 */ 2627 U32 2628 FastPathPendedRequests; /*0x18 */ 2629 U32 2630 FastPathUnPendedRequests; /*0x1C */ 2631 U32 2632 FastPathHostRequestStarts; /*0x20 */ 2633 U32 2634 FastPathFirmwareRequestStarts; /*0x24 */ 2635 U32 2636 FastPathHostCompletions; /*0x28 */ 2637 U32 2638 FastPathFirmwareCompletions; /*0x2C */ 2639 U32 2640 NonFastPathRequestStarts; /*0x30 */ 2641 U32 2642 NonFastPathHostCompletions; /*0x30 */ 2643 } MPI2_CONFIG_PAGE_SASIOUNIT16, 2644 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT16, 2645 Mpi2SasIOUnitPage16_t, *pMpi2SasIOUnitPage16_t; 2646 2647 #define MPI2_SASIOUNITPAGE16_PAGEVERSION (0x00) 2648 2649 2650 /**************************************************************************** 2651 * SAS Expander Config Pages 2652 ****************************************************************************/ 2653 2654 /*SAS Expander Page 0 */ 2655 2656 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 { 2657 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2658 Header; /*0x00 */ 2659 U8 2660 PhysicalPort; /*0x08 */ 2661 U8 2662 ReportGenLength; /*0x09 */ 2663 U16 2664 EnclosureHandle; /*0x0A */ 2665 U64 2666 SASAddress; /*0x0C */ 2667 U32 2668 DiscoveryStatus; /*0x14 */ 2669 U16 2670 DevHandle; /*0x18 */ 2671 U16 2672 ParentDevHandle; /*0x1A */ 2673 U16 2674 ExpanderChangeCount; /*0x1C */ 2675 U16 2676 ExpanderRouteIndexes; /*0x1E */ 2677 U8 2678 NumPhys; /*0x20 */ 2679 U8 2680 SASLevel; /*0x21 */ 2681 U16 2682 Flags; /*0x22 */ 2683 U16 2684 STPBusInactivityTimeLimit; /*0x24 */ 2685 U16 2686 STPMaxConnectTimeLimit; /*0x26 */ 2687 U16 2688 STP_SMP_NexusLossTime; /*0x28 */ 2689 U16 2690 MaxNumRoutedSasAddresses; /*0x2A */ 2691 U64 2692 ActiveZoneManagerSASAddress;/*0x2C */ 2693 U16 2694 ZoneLockInactivityLimit; /*0x34 */ 2695 U16 2696 Reserved1; /*0x36 */ 2697 U8 2698 TimeToReducedFunc; /*0x38 */ 2699 U8 2700 InitialTimeToReducedFunc; /*0x39 */ 2701 U8 2702 MaxReducedFuncTime; /*0x3A */ 2703 U8 2704 Reserved2; /*0x3B */ 2705 } MPI2_CONFIG_PAGE_EXPANDER_0, 2706 *PTR_MPI2_CONFIG_PAGE_EXPANDER_0, 2707 Mpi2ExpanderPage0_t, *pMpi2ExpanderPage0_t; 2708 2709 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06) 2710 2711 /*values for SAS Expander Page 0 DiscoveryStatus field */ 2712 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2713 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2714 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000) 2715 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2716 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2717 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2718 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2719 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000) 2720 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2721 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2722 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2723 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2724 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2725 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2726 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2727 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2728 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2729 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2730 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2731 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2732 2733 /*values for SAS Expander Page 0 Flags field */ 2734 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 2735 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 2736 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 2737 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 2738 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 2739 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 2740 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 2741 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 2742 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 2743 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 2744 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 2745 2746 2747 /*SAS Expander Page 1 */ 2748 2749 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 { 2750 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2751 Header; /*0x00 */ 2752 U8 2753 PhysicalPort; /*0x08 */ 2754 U8 2755 Reserved1; /*0x09 */ 2756 U16 2757 Reserved2; /*0x0A */ 2758 U8 2759 NumPhys; /*0x0C */ 2760 U8 2761 Phy; /*0x0D */ 2762 U16 2763 NumTableEntriesProgrammed; /*0x0E */ 2764 U8 2765 ProgrammedLinkRate; /*0x10 */ 2766 U8 2767 HwLinkRate; /*0x11 */ 2768 U16 2769 AttachedDevHandle; /*0x12 */ 2770 U32 2771 PhyInfo; /*0x14 */ 2772 U32 2773 AttachedDeviceInfo; /*0x18 */ 2774 U16 2775 ExpanderDevHandle; /*0x1C */ 2776 U8 2777 ChangeCount; /*0x1E */ 2778 U8 2779 NegotiatedLinkRate; /*0x1F */ 2780 U8 2781 PhyIdentifier; /*0x20 */ 2782 U8 2783 AttachedPhyIdentifier; /*0x21 */ 2784 U8 2785 Reserved3; /*0x22 */ 2786 U8 2787 DiscoveryInfo; /*0x23 */ 2788 U32 2789 AttachedPhyInfo; /*0x24 */ 2790 U8 2791 ZoneGroup; /*0x28 */ 2792 U8 2793 SelfConfigStatus; /*0x29 */ 2794 U16 2795 Reserved4; /*0x2A */ 2796 } MPI2_CONFIG_PAGE_EXPANDER_1, 2797 *PTR_MPI2_CONFIG_PAGE_EXPANDER_1, 2798 Mpi2ExpanderPage1_t, *pMpi2ExpanderPage1_t; 2799 2800 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02) 2801 2802 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2803 2804 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2805 2806 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2807 2808 /*see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines 2809 *used for the AttachedDeviceInfo field */ 2810 2811 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2812 2813 /*values for SAS Expander Page 1 DiscoveryInfo field */ 2814 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2815 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2816 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2817 2818 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2819 2820 2821 /**************************************************************************** 2822 * SAS Device Config Pages 2823 ****************************************************************************/ 2824 2825 /*SAS Device Page 0 */ 2826 2827 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 { 2828 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2829 Header; /*0x00 */ 2830 U16 2831 Slot; /*0x08 */ 2832 U16 2833 EnclosureHandle; /*0x0A */ 2834 U64 2835 SASAddress; /*0x0C */ 2836 U16 2837 ParentDevHandle; /*0x14 */ 2838 U8 2839 PhyNum; /*0x16 */ 2840 U8 2841 AccessStatus; /*0x17 */ 2842 U16 2843 DevHandle; /*0x18 */ 2844 U8 2845 AttachedPhyIdentifier; /*0x1A */ 2846 U8 2847 ZoneGroup; /*0x1B */ 2848 U32 2849 DeviceInfo; /*0x1C */ 2850 U16 2851 Flags; /*0x20 */ 2852 U8 2853 PhysicalPort; /*0x22 */ 2854 U8 2855 MaxPortConnections; /*0x23 */ 2856 U64 2857 DeviceName; /*0x24 */ 2858 U8 2859 PortGroups; /*0x2C */ 2860 U8 2861 DmaGroup; /*0x2D */ 2862 U8 2863 ControlGroup; /*0x2E */ 2864 U8 2865 EnclosureLevel; /*0x2F */ 2866 U32 2867 ConnectorName[4]; /*0x30 */ 2868 U32 2869 Reserved3; /*0x34 */ 2870 } MPI2_CONFIG_PAGE_SAS_DEV_0, 2871 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_0, 2872 Mpi2SasDevicePage0_t, 2873 *pMpi2SasDevicePage0_t; 2874 2875 #define MPI2_SASDEVICE0_PAGEVERSION (0x09) 2876 2877 /*values for SAS Device Page 0 AccessStatus field */ 2878 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2879 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2880 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2881 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2882 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2883 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05) 2884 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06) 2885 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07) 2886 /*specific values for SATA Init failures */ 2887 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2888 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2889 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2890 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2891 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2892 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2893 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2894 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2895 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2896 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2897 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2898 2899 /*see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2900 2901 /*values for SAS Device Page 0 Flags field */ 2902 #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000) 2903 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH (0x4000) 2904 #define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE (0x2000) 2905 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000) 2906 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800) 2907 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2908 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2909 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2910 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2911 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2912 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2913 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2914 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2915 #define MPI2_SAS_DEVICE0_FLAGS_PERSIST_CAPABLE (0x0004) 2916 #define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID (0x0002) 2917 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2918 2919 2920 /*SAS Device Page 1 */ 2921 2922 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 { 2923 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2924 Header; /*0x00 */ 2925 U32 2926 Reserved1; /*0x08 */ 2927 U64 2928 SASAddress; /*0x0C */ 2929 U32 2930 Reserved2; /*0x14 */ 2931 U16 2932 DevHandle; /*0x18 */ 2933 U16 2934 Reserved3; /*0x1A */ 2935 U8 2936 InitialRegDeviceFIS[20];/*0x1C */ 2937 } MPI2_CONFIG_PAGE_SAS_DEV_1, 2938 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_1, 2939 Mpi2SasDevicePage1_t, 2940 *pMpi2SasDevicePage1_t; 2941 2942 #define MPI2_SASDEVICE1_PAGEVERSION (0x01) 2943 2944 2945 /**************************************************************************** 2946 * SAS PHY Config Pages 2947 ****************************************************************************/ 2948 2949 /*SAS PHY Page 0 */ 2950 2951 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 { 2952 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2953 Header; /*0x00 */ 2954 U16 2955 OwnerDevHandle; /*0x08 */ 2956 U16 2957 Reserved1; /*0x0A */ 2958 U16 2959 AttachedDevHandle; /*0x0C */ 2960 U8 2961 AttachedPhyIdentifier; /*0x0E */ 2962 U8 2963 Reserved2; /*0x0F */ 2964 U32 2965 AttachedPhyInfo; /*0x10 */ 2966 U8 2967 ProgrammedLinkRate; /*0x14 */ 2968 U8 2969 HwLinkRate; /*0x15 */ 2970 U8 2971 ChangeCount; /*0x16 */ 2972 U8 2973 Flags; /*0x17 */ 2974 U32 2975 PhyInfo; /*0x18 */ 2976 U8 2977 NegotiatedLinkRate; /*0x1C */ 2978 U8 2979 Reserved3; /*0x1D */ 2980 U16 2981 Reserved4; /*0x1E */ 2982 } MPI2_CONFIG_PAGE_SAS_PHY_0, 2983 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_0, 2984 Mpi2SasPhyPage0_t, *pMpi2SasPhyPage0_t; 2985 2986 #define MPI2_SASPHY0_PAGEVERSION (0x03) 2987 2988 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2989 2990 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2991 2992 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2993 2994 /*values for SAS PHY Page 0 Flags field */ 2995 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 2996 2997 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2998 2999 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3000 3001 3002 /*SAS PHY Page 1 */ 3003 3004 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 { 3005 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3006 Header; /*0x00 */ 3007 U32 3008 Reserved1; /*0x08 */ 3009 U32 3010 InvalidDwordCount; /*0x0C */ 3011 U32 3012 RunningDisparityErrorCount; /*0x10 */ 3013 U32 3014 LossDwordSynchCount; /*0x14 */ 3015 U32 3016 PhyResetProblemCount; /*0x18 */ 3017 } MPI2_CONFIG_PAGE_SAS_PHY_1, 3018 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_1, 3019 Mpi2SasPhyPage1_t, *pMpi2SasPhyPage1_t; 3020 3021 #define MPI2_SASPHY1_PAGEVERSION (0x01) 3022 3023 3024 /*SAS PHY Page 2 */ 3025 3026 typedef struct _MPI2_SASPHY2_PHY_EVENT { 3027 U8 PhyEventCode; /*0x00 */ 3028 U8 Reserved1; /*0x01 */ 3029 U16 Reserved2; /*0x02 */ 3030 U32 PhyEventInfo; /*0x04 */ 3031 } MPI2_SASPHY2_PHY_EVENT, *PTR_MPI2_SASPHY2_PHY_EVENT, 3032 Mpi2SasPhy2PhyEvent_t, *pMpi2SasPhy2PhyEvent_t; 3033 3034 /*use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */ 3035 3036 3037 /* 3038 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3039 *one and check the value returned for NumPhyEvents at runtime. 3040 */ 3041 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX 3042 #define MPI2_SASPHY2_PHY_EVENT_MAX (1) 3043 #endif 3044 3045 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 { 3046 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3047 Header; /*0x00 */ 3048 U32 3049 Reserved1; /*0x08 */ 3050 U8 3051 NumPhyEvents; /*0x0C */ 3052 U8 3053 Reserved2; /*0x0D */ 3054 U16 3055 Reserved3; /*0x0E */ 3056 MPI2_SASPHY2_PHY_EVENT 3057 PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /*0x10 */ 3058 } MPI2_CONFIG_PAGE_SAS_PHY_2, 3059 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_2, 3060 Mpi2SasPhyPage2_t, 3061 *pMpi2SasPhyPage2_t; 3062 3063 #define MPI2_SASPHY2_PAGEVERSION (0x00) 3064 3065 3066 /*SAS PHY Page 3 */ 3067 3068 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG { 3069 U8 PhyEventCode; /*0x00 */ 3070 U8 Reserved1; /*0x01 */ 3071 U16 Reserved2; /*0x02 */ 3072 U8 CounterType; /*0x04 */ 3073 U8 ThresholdWindow; /*0x05 */ 3074 U8 TimeUnits; /*0x06 */ 3075 U8 Reserved3; /*0x07 */ 3076 U32 EventThreshold; /*0x08 */ 3077 U16 ThresholdFlags; /*0x0C */ 3078 U16 Reserved4; /*0x0E */ 3079 } MPI2_SASPHY3_PHY_EVENT_CONFIG, 3080 *PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG, 3081 Mpi2SasPhy3PhyEventConfig_t, 3082 *pMpi2SasPhy3PhyEventConfig_t; 3083 3084 /*values for PhyEventCode field */ 3085 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 3086 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 3087 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 3088 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 3089 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 3090 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 3091 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 3092 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 3093 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 3094 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 3095 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 3096 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 3097 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 3098 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 3099 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 3100 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 3101 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 3102 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A) 3103 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B) 3104 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C) 3105 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D) 3106 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E) 3107 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 3108 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 3109 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 3110 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 3111 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 3112 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 3113 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 3114 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 3115 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 3116 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 3117 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 3118 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 3119 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) 3120 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) 3121 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2) 3122 3123 /*Following codes are product specific and in MPI v2.6 and later */ 3124 #define MPI2_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xD3) 3125 #define MPI2_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xD4) 3126 #define MPI2_SASPHY3_EVENT_CODE_LCCONN_TIME (0xD5) 3127 #define MPI2_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xD6) 3128 #define MPI2_SASPHY3_EVENT_CODE_SATA_TX_START (0xD7) 3129 #define MPI2_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xD8) 3130 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xD9) 3131 #define MPI2_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xDA) 3132 #define MPI2_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xDB) 3133 #define MPI2_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xDC) 3134 3135 3136 /*values for the CounterType field */ 3137 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 3138 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 3139 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 3140 3141 /*values for the TimeUnits field */ 3142 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 3143 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 3144 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 3145 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 3146 3147 /*values for the ThresholdFlags field */ 3148 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002) 3149 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 3150 3151 /* 3152 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3153 *one and check the value returned for NumPhyEvents at runtime. 3154 */ 3155 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX 3156 #define MPI2_SASPHY3_PHY_EVENT_MAX (1) 3157 #endif 3158 3159 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 { 3160 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3161 Header; /*0x00 */ 3162 U32 3163 Reserved1; /*0x08 */ 3164 U8 3165 NumPhyEvents; /*0x0C */ 3166 U8 3167 Reserved2; /*0x0D */ 3168 U16 3169 Reserved3; /*0x0E */ 3170 MPI2_SASPHY3_PHY_EVENT_CONFIG 3171 PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /*0x10 */ 3172 } MPI2_CONFIG_PAGE_SAS_PHY_3, 3173 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_3, 3174 Mpi2SasPhyPage3_t, *pMpi2SasPhyPage3_t; 3175 3176 #define MPI2_SASPHY3_PAGEVERSION (0x00) 3177 3178 3179 /*SAS PHY Page 4 */ 3180 3181 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 { 3182 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3183 Header; /*0x00 */ 3184 U16 3185 Reserved1; /*0x08 */ 3186 U8 3187 Reserved2; /*0x0A */ 3188 U8 3189 Flags; /*0x0B */ 3190 U8 3191 InitialFrame[28]; /*0x0C */ 3192 } MPI2_CONFIG_PAGE_SAS_PHY_4, 3193 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_4, 3194 Mpi2SasPhyPage4_t, *pMpi2SasPhyPage4_t; 3195 3196 #define MPI2_SASPHY4_PAGEVERSION (0x00) 3197 3198 /*values for the Flags field */ 3199 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02) 3200 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01) 3201 3202 3203 3204 3205 /**************************************************************************** 3206 * SAS Port Config Pages 3207 ****************************************************************************/ 3208 3209 /*SAS Port Page 0 */ 3210 3211 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 { 3212 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3213 Header; /*0x00 */ 3214 U8 3215 PortNumber; /*0x08 */ 3216 U8 3217 PhysicalPort; /*0x09 */ 3218 U8 3219 PortWidth; /*0x0A */ 3220 U8 3221 PhysicalPortWidth; /*0x0B */ 3222 U8 3223 ZoneGroup; /*0x0C */ 3224 U8 3225 Reserved1; /*0x0D */ 3226 U16 3227 Reserved2; /*0x0E */ 3228 U64 3229 SASAddress; /*0x10 */ 3230 U32 3231 DeviceInfo; /*0x18 */ 3232 U32 3233 Reserved3; /*0x1C */ 3234 U32 3235 Reserved4; /*0x20 */ 3236 } MPI2_CONFIG_PAGE_SAS_PORT_0, 3237 *PTR_MPI2_CONFIG_PAGE_SAS_PORT_0, 3238 Mpi2SasPortPage0_t, *pMpi2SasPortPage0_t; 3239 3240 #define MPI2_SASPORT0_PAGEVERSION (0x00) 3241 3242 /*see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */ 3243 3244 3245 /**************************************************************************** 3246 * SAS Enclosure Config Pages 3247 ****************************************************************************/ 3248 3249 /*SAS Enclosure Page 0 */ 3250 3251 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 { 3252 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3253 U32 Reserved1; /*0x08 */ 3254 U64 EnclosureLogicalID; /*0x0C */ 3255 U16 Flags; /*0x14 */ 3256 U16 EnclosureHandle; /*0x16 */ 3257 U16 NumSlots; /*0x18 */ 3258 U16 StartSlot; /*0x1A */ 3259 U8 ChassisSlot; /*0x1C */ 3260 U8 EnclosureLeve; /*0x1D */ 3261 U16 SEPDevHandle; /*0x1E */ 3262 U32 Reserved3; /*0x20 */ 3263 U32 Reserved4; /*0x24 */ 3264 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3265 *PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3266 Mpi2SasEnclosurePage0_t, *pMpi2SasEnclosurePage0_t, 3267 MPI26_CONFIG_PAGE_ENCLOSURE_0, 3268 *PTR_MPI26_CONFIG_PAGE_ENCLOSURE_0, 3269 Mpi26EnclosurePage0_t, *pMpi26EnclosurePage0_t; 3270 3271 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x04) 3272 3273 /*values for SAS Enclosure Page 0 Flags field */ 3274 #define MPI2_SAS_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020) 3275 #define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010) 3276 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 3277 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3278 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3279 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3280 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3281 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3282 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3283 3284 #define MPI26_ENCLOSURE0_PAGEVERSION (0x04) 3285 3286 /*Values for Enclosure Page 0 Flags field */ 3287 #define MPI26_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020) 3288 #define MPI26_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010) 3289 #define MPI26_ENCLS0_FLAGS_MNG_MASK (0x000F) 3290 #define MPI26_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3291 #define MPI26_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3292 #define MPI26_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3293 #define MPI26_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3294 #define MPI26_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3295 #define MPI26_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3296 3297 /**************************************************************************** 3298 * Log Config Page 3299 ****************************************************************************/ 3300 3301 /*Log Page 0 */ 3302 3303 /* 3304 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3305 *one and check the value returned for NumLogEntries at runtime. 3306 */ 3307 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES 3308 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1) 3309 #endif 3310 3311 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C) 3312 3313 typedef struct _MPI2_LOG_0_ENTRY { 3314 U64 TimeStamp; /*0x00 */ 3315 U32 Reserved1; /*0x08 */ 3316 U16 LogSequence; /*0x0C */ 3317 U16 LogEntryQualifier; /*0x0E */ 3318 U8 VP_ID; /*0x10 */ 3319 U8 VF_ID; /*0x11 */ 3320 U16 Reserved2; /*0x12 */ 3321 U8 3322 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/*0x14 */ 3323 } MPI2_LOG_0_ENTRY, *PTR_MPI2_LOG_0_ENTRY, 3324 Mpi2Log0Entry_t, *pMpi2Log0Entry_t; 3325 3326 /*values for Log Page 0 LogEntry LogEntryQualifier field */ 3327 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 3328 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 3329 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002) 3330 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000) 3331 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF) 3332 3333 typedef struct _MPI2_CONFIG_PAGE_LOG_0 { 3334 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3335 U32 Reserved1; /*0x08 */ 3336 U32 Reserved2; /*0x0C */ 3337 U16 NumLogEntries;/*0x10 */ 3338 U16 Reserved3; /*0x12 */ 3339 MPI2_LOG_0_ENTRY 3340 LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /*0x14 */ 3341 } MPI2_CONFIG_PAGE_LOG_0, *PTR_MPI2_CONFIG_PAGE_LOG_0, 3342 Mpi2LogPage0_t, *pMpi2LogPage0_t; 3343 3344 #define MPI2_LOG_0_PAGEVERSION (0x02) 3345 3346 3347 /**************************************************************************** 3348 * RAID Config Page 3349 ****************************************************************************/ 3350 3351 /*RAID Page 0 */ 3352 3353 /* 3354 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3355 *one and check the value returned for NumElements at runtime. 3356 */ 3357 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS 3358 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1) 3359 #endif 3360 3361 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT { 3362 U16 ElementFlags; /*0x00 */ 3363 U16 VolDevHandle; /*0x02 */ 3364 U8 HotSparePool; /*0x04 */ 3365 U8 PhysDiskNum; /*0x05 */ 3366 U16 PhysDiskDevHandle; /*0x06 */ 3367 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3368 *PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3369 Mpi2RaidConfig0ConfigElement_t, 3370 *pMpi2RaidConfig0ConfigElement_t; 3371 3372 /*values for the ElementFlags field */ 3373 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F) 3374 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000) 3375 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001) 3376 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002) 3377 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003) 3378 3379 3380 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 { 3381 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3382 U8 NumHotSpares; /*0x08 */ 3383 U8 NumPhysDisks; /*0x09 */ 3384 U8 NumVolumes; /*0x0A */ 3385 U8 ConfigNum; /*0x0B */ 3386 U32 Flags; /*0x0C */ 3387 U8 ConfigGUID[24]; /*0x10 */ 3388 U32 Reserved1; /*0x28 */ 3389 U8 NumElements; /*0x2C */ 3390 U8 Reserved2; /*0x2D */ 3391 U16 Reserved3; /*0x2E */ 3392 MPI2_RAIDCONFIG0_CONFIG_ELEMENT 3393 ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /*0x30 */ 3394 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3395 *PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3396 Mpi2RaidConfigurationPage0_t, 3397 *pMpi2RaidConfigurationPage0_t; 3398 3399 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00) 3400 3401 /*values for RAID Configuration Page 0 Flags field */ 3402 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001) 3403 3404 3405 /**************************************************************************** 3406 * Driver Persistent Mapping Config Pages 3407 ****************************************************************************/ 3408 3409 /*Driver Persistent Mapping Page 0 */ 3410 3411 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY { 3412 U64 PhysicalIdentifier; /*0x00 */ 3413 U16 MappingInformation; /*0x08 */ 3414 U16 DeviceIndex; /*0x0A */ 3415 U32 PhysicalBitsMapping; /*0x0C */ 3416 U32 Reserved1; /*0x10 */ 3417 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3418 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3419 Mpi2DriverMap0Entry_t, *pMpi2DriverMap0Entry_t; 3420 3421 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 { 3422 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3423 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /*0x08 */ 3424 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3425 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3426 Mpi2DriverMappingPage0_t, *pMpi2DriverMappingPage0_t; 3427 3428 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00) 3429 3430 /*values for Driver Persistent Mapping Page 0 MappingInformation field */ 3431 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0) 3432 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4) 3433 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F) 3434 3435 3436 /**************************************************************************** 3437 * Ethernet Config Pages 3438 ****************************************************************************/ 3439 3440 /*Ethernet Page 0 */ 3441 3442 /*IP address (union of IPv4 and IPv6) */ 3443 typedef union _MPI2_ETHERNET_IP_ADDR { 3444 U32 IPv4Addr; 3445 U32 IPv6Addr[4]; 3446 } MPI2_ETHERNET_IP_ADDR, *PTR_MPI2_ETHERNET_IP_ADDR, 3447 Mpi2EthernetIpAddr_t, *pMpi2EthernetIpAddr_t; 3448 3449 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32) 3450 3451 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 { 3452 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3453 U8 NumInterfaces; /*0x08 */ 3454 U8 Reserved0; /*0x09 */ 3455 U16 Reserved1; /*0x0A */ 3456 U32 Status; /*0x0C */ 3457 U8 MediaState; /*0x10 */ 3458 U8 Reserved2; /*0x11 */ 3459 U16 Reserved3; /*0x12 */ 3460 U8 MacAddress[6]; /*0x14 */ 3461 U8 Reserved4; /*0x1A */ 3462 U8 Reserved5; /*0x1B */ 3463 MPI2_ETHERNET_IP_ADDR IpAddress; /*0x1C */ 3464 MPI2_ETHERNET_IP_ADDR SubnetMask; /*0x2C */ 3465 MPI2_ETHERNET_IP_ADDR GatewayIpAddress;/*0x3C */ 3466 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /*0x4C */ 3467 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /*0x5C */ 3468 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /*0x6C */ 3469 U8 3470 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */ 3471 } MPI2_CONFIG_PAGE_ETHERNET_0, 3472 *PTR_MPI2_CONFIG_PAGE_ETHERNET_0, 3473 Mpi2EthernetPage0_t, *pMpi2EthernetPage0_t; 3474 3475 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00) 3476 3477 /*values for Ethernet Page 0 Status field */ 3478 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000) 3479 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000) 3480 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000) 3481 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100) 3482 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080) 3483 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040) 3484 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020) 3485 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010) 3486 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008) 3487 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004) 3488 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002) 3489 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001) 3490 3491 /*values for Ethernet Page 0 MediaState field */ 3492 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80) 3493 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00) 3494 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80) 3495 3496 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07) 3497 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00) 3498 #define MPI2_ETHPG0_MS_10MBIT (0x01) 3499 #define MPI2_ETHPG0_MS_100MBIT (0x02) 3500 #define MPI2_ETHPG0_MS_1GBIT (0x03) 3501 3502 3503 /*Ethernet Page 1 */ 3504 3505 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 { 3506 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3507 Header; /*0x00 */ 3508 U32 3509 Reserved0; /*0x08 */ 3510 U32 3511 Flags; /*0x0C */ 3512 U8 3513 MediaState; /*0x10 */ 3514 U8 3515 Reserved1; /*0x11 */ 3516 U16 3517 Reserved2; /*0x12 */ 3518 U8 3519 MacAddress[6]; /*0x14 */ 3520 U8 3521 Reserved3; /*0x1A */ 3522 U8 3523 Reserved4; /*0x1B */ 3524 MPI2_ETHERNET_IP_ADDR 3525 StaticIpAddress; /*0x1C */ 3526 MPI2_ETHERNET_IP_ADDR 3527 StaticSubnetMask; /*0x2C */ 3528 MPI2_ETHERNET_IP_ADDR 3529 StaticGatewayIpAddress; /*0x3C */ 3530 MPI2_ETHERNET_IP_ADDR 3531 StaticDNS1IpAddress; /*0x4C */ 3532 MPI2_ETHERNET_IP_ADDR 3533 StaticDNS2IpAddress; /*0x5C */ 3534 U32 3535 Reserved5; /*0x6C */ 3536 U32 3537 Reserved6; /*0x70 */ 3538 U32 3539 Reserved7; /*0x74 */ 3540 U32 3541 Reserved8; /*0x78 */ 3542 U8 3543 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */ 3544 } MPI2_CONFIG_PAGE_ETHERNET_1, 3545 *PTR_MPI2_CONFIG_PAGE_ETHERNET_1, 3546 Mpi2EthernetPage1_t, *pMpi2EthernetPage1_t; 3547 3548 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00) 3549 3550 /*values for Ethernet Page 1 Flags field */ 3551 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100) 3552 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080) 3553 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040) 3554 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020) 3555 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010) 3556 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008) 3557 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004) 3558 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002) 3559 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001) 3560 3561 /*values for Ethernet Page 1 MediaState field */ 3562 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80) 3563 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00) 3564 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80) 3565 3566 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07) 3567 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00) 3568 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01) 3569 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02) 3570 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03) 3571 3572 3573 /**************************************************************************** 3574 * Extended Manufacturing Config Pages 3575 ****************************************************************************/ 3576 3577 /* 3578 *Generic structure to use for product-specific extended manufacturing pages 3579 *(currently Extended Manufacturing Page 40 through Extended Manufacturing 3580 *Page 60). 3581 */ 3582 3583 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS { 3584 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3585 Header; /*0x00 */ 3586 U32 3587 ProductSpecificInfo; /*0x08 */ 3588 } MPI2_CONFIG_PAGE_EXT_MAN_PS, 3589 *PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS, 3590 Mpi2ExtManufacturingPagePS_t, 3591 *pMpi2ExtManufacturingPagePS_t; 3592 3593 /*PageVersion should be provided by product-specific code */ 3594 3595 3596 3597 /**************************************************************************** 3598 * values for fields used by several types of PCIe Config Pages 3599 ****************************************************************************/ 3600 3601 /*values for NegotiatedLinkRates fields */ 3602 #define MPI26_PCIE_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 3603 /*link rates used for Negotiated Physical Link Rate */ 3604 #define MPI26_PCIE_NEG_LINK_RATE_UNKNOWN (0x00) 3605 #define MPI26_PCIE_NEG_LINK_RATE_PHY_DISABLED (0x01) 3606 #define MPI26_PCIE_NEG_LINK_RATE_2_5 (0x02) 3607 #define MPI26_PCIE_NEG_LINK_RATE_5_0 (0x03) 3608 #define MPI26_PCIE_NEG_LINK_RATE_8_0 (0x04) 3609 #define MPI26_PCIE_NEG_LINK_RATE_16_0 (0x05) 3610 3611 3612 /**************************************************************************** 3613 * PCIe IO Unit Config Pages (MPI v2.6 and later) 3614 ****************************************************************************/ 3615 3616 /*PCIe IO Unit Page 0 */ 3617 3618 typedef struct _MPI26_PCIE_IO_UNIT0_PHY_DATA { 3619 U8 Link; /*0x00 */ 3620 U8 LinkFlags; /*0x01 */ 3621 U8 PhyFlags; /*0x02 */ 3622 U8 NegotiatedLinkRate; /*0x03 */ 3623 U32 ControllerPhyDeviceInfo;/*0x04 */ 3624 U16 AttachedDevHandle; /*0x08 */ 3625 U16 ControllerDevHandle; /*0x0A */ 3626 U32 EnumerationStatus; /*0x0C */ 3627 U32 Reserved1; /*0x10 */ 3628 } MPI26_PCIE_IO_UNIT0_PHY_DATA, 3629 *PTR_MPI26_PCIE_IO_UNIT0_PHY_DATA, 3630 Mpi26PCIeIOUnit0PhyData_t, *pMpi26PCIeIOUnit0PhyData_t; 3631 3632 /* 3633 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3634 *one and check the value returned for NumPhys at runtime. 3635 */ 3636 #ifndef MPI26_PCIE_IOUNIT0_PHY_MAX 3637 #define MPI26_PCIE_IOUNIT0_PHY_MAX (1) 3638 #endif 3639 3640 typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_0 { 3641 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3642 U32 Reserved1; /*0x08 */ 3643 U8 NumPhys; /*0x0C */ 3644 U8 InitStatus; /*0x0D */ 3645 U16 Reserved3; /*0x0E */ 3646 MPI26_PCIE_IO_UNIT0_PHY_DATA 3647 PhyData[MPI26_PCIE_IOUNIT0_PHY_MAX]; /*0x10 */ 3648 } MPI26_CONFIG_PAGE_PIOUNIT_0, 3649 *PTR_MPI26_CONFIG_PAGE_PIOUNIT_0, 3650 Mpi26PCIeIOUnitPage0_t, *pMpi26PCIeIOUnitPage0_t; 3651 3652 #define MPI26_PCIEIOUNITPAGE0_PAGEVERSION (0x00) 3653 3654 /*values for PCIe IO Unit Page 0 LinkFlags */ 3655 #define MPI26_PCIEIOUNIT0_LINKFLAGS_ENUMERATION_IN_PROGRESS (0x08) 3656 3657 /*values for PCIe IO Unit Page 0 PhyFlags */ 3658 #define MPI26_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 3659 3660 /*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3661 3662 /*see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo 3663 *values 3664 */ 3665 3666 /*values for PCIe IO Unit Page 0 EnumerationStatus */ 3667 #define MPI26_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED (0x40000000) 3668 #define MPI26_PCIEIOUNIT0_ES_MAX_DEVICES_EXCEEDED (0x20000000) 3669 3670 3671 /*PCIe IO Unit Page 1 */ 3672 3673 typedef struct _MPI26_PCIE_IO_UNIT1_PHY_DATA { 3674 U8 Link; /*0x00 */ 3675 U8 LinkFlags; /*0x01 */ 3676 U8 PhyFlags; /*0x02 */ 3677 U8 MaxMinLinkRate; /*0x03 */ 3678 U32 ControllerPhyDeviceInfo; /*0x04 */ 3679 U32 Reserved1; /*0x08 */ 3680 } MPI26_PCIE_IO_UNIT1_PHY_DATA, 3681 *PTR_MPI26_PCIE_IO_UNIT1_PHY_DATA, 3682 Mpi26PCIeIOUnit1PhyData_t, *pMpi26PCIeIOUnit1PhyData_t; 3683 3684 /*values for LinkFlags */ 3685 #define MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SRIS (0x00) 3686 #define MPI26_PCIEIOUNIT1_LINKFLAGS_EN_SRIS (0x01) 3687 3688 /* 3689 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3690 *one and check the value returned for NumPhys at runtime. 3691 */ 3692 #ifndef MPI26_PCIE_IOUNIT1_PHY_MAX 3693 #define MPI26_PCIE_IOUNIT1_PHY_MAX (1) 3694 #endif 3695 3696 typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_1 { 3697 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3698 U16 ControlFlags; /*0x08 */ 3699 U16 Reserved; /*0x0A */ 3700 U16 AdditionalControlFlags; /*0x0C */ 3701 U16 NVMeMaxQueueDepth; /*0x0E */ 3702 U8 NumPhys; /*0x10 */ 3703 U8 Reserved1; /*0x11 */ 3704 U16 Reserved2; /*0x12 */ 3705 MPI26_PCIE_IO_UNIT1_PHY_DATA 3706 PhyData[MPI26_PCIE_IOUNIT1_PHY_MAX];/*0x14 */ 3707 } MPI26_CONFIG_PAGE_PIOUNIT_1, 3708 *PTR_MPI26_CONFIG_PAGE_PIOUNIT_1, 3709 Mpi26PCIeIOUnitPage1_t, *pMpi26PCIeIOUnitPage1_t; 3710 3711 #define MPI26_PCIEIOUNITPAGE1_PAGEVERSION (0x00) 3712 3713 /*values for PCIe IO Unit Page 1 PhyFlags */ 3714 #define MPI26_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 3715 #define MPI26_PCIEIOUNIT1_PHYFLAGS_ENDPOINT_ONLY (0x01) 3716 3717 /*values for PCIe IO Unit Page 1 MaxMinLinkRate */ 3718 #define MPI26_PCIEIOUNIT1_MAX_RATE_MASK (0xF0) 3719 #define MPI26_PCIEIOUNIT1_MAX_RATE_SHIFT (4) 3720 #define MPI26_PCIEIOUNIT1_MAX_RATE_2_5 (0x20) 3721 #define MPI26_PCIEIOUNIT1_MAX_RATE_5_0 (0x30) 3722 #define MPI26_PCIEIOUNIT1_MAX_RATE_8_0 (0x40) 3723 #define MPI26_PCIEIOUNIT1_MAX_RATE_16_0 (0x50) 3724 3725 /*see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo 3726 *values 3727 */ 3728 3729 3730 /**************************************************************************** 3731 * PCIe Switch Config Pages (MPI v2.6 and later) 3732 ****************************************************************************/ 3733 3734 /*PCIe Switch Page 0 */ 3735 3736 typedef struct _MPI26_CONFIG_PAGE_PSWITCH_0 { 3737 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3738 U8 PhysicalPort; /*0x08 */ 3739 U8 Reserved1; /*0x09 */ 3740 U16 Reserved2; /*0x0A */ 3741 U16 DevHandle; /*0x0C */ 3742 U16 ParentDevHandle; /*0x0E */ 3743 U8 NumPorts; /*0x10 */ 3744 U8 PCIeLevel; /*0x11 */ 3745 U16 Reserved3; /*0x12 */ 3746 U32 Reserved4; /*0x14 */ 3747 U32 Reserved5; /*0x18 */ 3748 U32 Reserved6; /*0x1C */ 3749 } MPI26_CONFIG_PAGE_PSWITCH_0, *PTR_MPI26_CONFIG_PAGE_PSWITCH_0, 3750 Mpi26PCIeSwitchPage0_t, *pMpi26PCIeSwitchPage0_t; 3751 3752 #define MPI26_PCIESWITCH0_PAGEVERSION (0x00) 3753 3754 3755 /*PCIe Switch Page 1 */ 3756 3757 typedef struct _MPI26_CONFIG_PAGE_PSWITCH_1 { 3758 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3759 U8 PhysicalPort; /*0x08 */ 3760 U8 Reserved1; /*0x09 */ 3761 U16 Reserved2; /*0x0A */ 3762 U8 NumPorts; /*0x0C */ 3763 U8 PortNum; /*0x0D */ 3764 U16 AttachedDevHandle; /*0x0E */ 3765 U16 SwitchDevHandle; /*0x10 */ 3766 U8 NegotiatedPortWidth; /*0x12 */ 3767 U8 NegotiatedLinkRate; /*0x13 */ 3768 U32 Reserved4; /*0x14 */ 3769 U32 Reserved5; /*0x18 */ 3770 } MPI26_CONFIG_PAGE_PSWITCH_1, *PTR_MPI26_CONFIG_PAGE_PSWITCH_1, 3771 Mpi26PCIeSwitchPage1_t, *pMpi26PCIeSwitchPage1_t; 3772 3773 #define MPI26_PCIESWITCH1_PAGEVERSION (0x00) 3774 3775 /*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3776 3777 3778 /**************************************************************************** 3779 * PCIe Device Config Pages (MPI v2.6 and later) 3780 ****************************************************************************/ 3781 3782 /*PCIe Device Page 0 */ 3783 3784 typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_0 { 3785 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3786 U16 Slot; /*0x08 */ 3787 U16 EnclosureHandle; /*0x0A */ 3788 U64 WWID; /*0x0C */ 3789 U16 ParentDevHandle; /*0x14 */ 3790 U8 PortNum; /*0x16 */ 3791 U8 AccessStatus; /*0x17 */ 3792 U16 DevHandle; /*0x18 */ 3793 U8 PhysicalPort; /*0x1A */ 3794 U8 Reserved1; /*0x1B */ 3795 U32 DeviceInfo; /*0x1C */ 3796 U32 Flags; /*0x20 */ 3797 U8 SupportedLinkRates; /*0x24 */ 3798 U8 MaxPortWidth; /*0x25 */ 3799 U8 NegotiatedPortWidth; /*0x26 */ 3800 U8 NegotiatedLinkRate; /*0x27 */ 3801 U8 EnclosureLevel; /*0x28 */ 3802 U8 Reserved2; /*0x29 */ 3803 U16 Reserved3; /*0x2A */ 3804 U8 ConnectorName[4]; /*0x2C */ 3805 U32 Reserved4; /*0x30 */ 3806 U32 Reserved5; /*0x34 */ 3807 } MPI26_CONFIG_PAGE_PCIEDEV_0, *PTR_MPI26_CONFIG_PAGE_PCIEDEV_0, 3808 Mpi26PCIeDevicePage0_t, *pMpi26PCIeDevicePage0_t; 3809 3810 #define MPI26_PCIEDEVICE0_PAGEVERSION (0x01) 3811 3812 /*values for PCIe Device Page 0 AccessStatus field */ 3813 #define MPI26_PCIEDEV0_ASTATUS_NO_ERRORS (0x00) 3814 #define MPI26_PCIEDEV0_ASTATUS_NEEDS_INITIALIZATION (0x04) 3815 #define MPI26_PCIEDEV0_ASTATUS_CAPABILITY_FAILED (0x02) 3816 #define MPI26_PCIEDEV0_ASTATUS_DEVICE_BLOCKED (0x07) 3817 #define MPI26_PCIEDEV0_ASTATUS_MEMORY_SPACE_ACCESS_FAILED (0x08) 3818 #define MPI26_PCIEDEV0_ASTATUS_UNSUPPORTED_DEVICE (0x09) 3819 #define MPI26_PCIEDEV0_ASTATUS_MSIX_REQUIRED (0x0A) 3820 #define MPI26_PCIEDEV0_ASTATUS_UNKNOWN (0x10) 3821 3822 #define MPI26_PCIEDEV0_ASTATUS_NVME_READY_TIMEOUT (0x30) 3823 #define MPI26_PCIEDEV0_ASTATUS_NVME_DEVCFG_UNSUPPORTED (0x31) 3824 #define MPI26_PCIEDEV0_ASTATUS_NVME_IDENTIFY_FAILED (0x32) 3825 #define MPI26_PCIEDEV0_ASTATUS_NVME_QCONFIG_FAILED (0x33) 3826 #define MPI26_PCIEDEV0_ASTATUS_NVME_QCREATION_FAILED (0x34) 3827 #define MPI26_PCIEDEV0_ASTATUS_NVME_EVENTCFG_FAILED (0x35) 3828 #define MPI26_PCIEDEV0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED (0x36) 3829 #define MPI26_PCIEDEV0_ASTATUS_NVME_IDLE_TIMEOUT (0x37) 3830 #define MPI26_PCIEDEV0_ASTATUS_NVME_FAILURE_STATUS (0x38) 3831 3832 #define MPI26_PCIEDEV0_ASTATUS_INIT_FAIL_MAX (0x3F) 3833 3834 /*see mpi2_pci.h for the MPI26_PCIE_DEVINFO_ defines used for the DeviceInfo 3835 *field 3836 */ 3837 3838 /*values for PCIe Device Page 0 Flags field */ 3839 #define MPI26_PCIEDEV0_FLAGS_UNAUTHORIZED_DEVICE (0x8000) 3840 #define MPI26_PCIEDEV0_FLAGS_ENABLED_FAST_PATH (0x4000) 3841 #define MPI26_PCIEDEV0_FLAGS_FAST_PATH_CAPABLE (0x2000) 3842 #define MPI26_PCIEDEV0_FLAGS_ASYNCHRONOUS_NOTIFICATION (0x0400) 3843 #define MPI26_PCIEDEV0_FLAGS_ATA_SW_PRESERVATION (0x0200) 3844 #define MPI26_PCIEDEV0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 3845 #define MPI26_PCIEDEV0_FLAGS_ATA_48BIT_LBA_SUPPORTED (0x0080) 3846 #define MPI26_PCIEDEV0_FLAGS_ATA_SMART_SUPPORTED (0x0040) 3847 #define MPI26_PCIEDEV0_FLAGS_ATA_NCQ_SUPPORTED (0x0020) 3848 #define MPI26_PCIEDEV0_FLAGS_ATA_FUA_SUPPORTED (0x0010) 3849 #define MPI26_PCIEDEV0_FLAGS_ENCL_LEVEL_VALID (0x0002) 3850 #define MPI26_PCIEDEV0_FLAGS_DEVICE_PRESENT (0x0001) 3851 3852 /* values for PCIe Device Page 0 SupportedLinkRates field */ 3853 #define MPI26_PCIEDEV0_LINK_RATE_16_0_SUPPORTED (0x08) 3854 #define MPI26_PCIEDEV0_LINK_RATE_8_0_SUPPORTED (0x04) 3855 #define MPI26_PCIEDEV0_LINK_RATE_5_0_SUPPORTED (0x02) 3856 #define MPI26_PCIEDEV0_LINK_RATE_2_5_SUPPORTED (0x01) 3857 3858 /*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3859 3860 3861 /*PCIe Device Page 2 */ 3862 3863 typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_2 { 3864 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3865 U16 DevHandle; /*0x08 */ 3866 U16 Reserved1; /*0x0A */ 3867 U32 MaximumDataTransferSize;/*0x0C */ 3868 U32 Capabilities; /*0x10 */ 3869 U32 Reserved2; /*0x14 */ 3870 } MPI26_CONFIG_PAGE_PCIEDEV_2, *PTR_MPI26_CONFIG_PAGE_PCIEDEV_2, 3871 Mpi26PCIeDevicePage2_t, *pMpi26PCIeDevicePage2_t; 3872 3873 #define MPI26_PCIEDEVICE2_PAGEVERSION (0x00) 3874 3875 /*defines for PCIe Device Page 2 Capabilities field */ 3876 #define MPI26_PCIEDEV2_CAP_SGL_FORMAT (0x00000004) 3877 #define MPI26_PCIEDEV2_CAP_BIT_BUCKET_SUPPORT (0x00000002) 3878 #define MPI26_PCIEDEV2_CAP_SGL_SUPPORT (0x00000001) 3879 3880 3881 /**************************************************************************** 3882 * PCIe Link Config Pages (MPI v2.6 and later) 3883 ****************************************************************************/ 3884 3885 /*PCIe Link Page 1 */ 3886 3887 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_1 { 3888 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3889 U8 Link; /*0x08 */ 3890 U8 Reserved1; /*0x09 */ 3891 U16 Reserved2; /*0x0A */ 3892 U32 CorrectableErrorCount; /*0x0C */ 3893 U16 NonFatalErrorCount; /*0x10 */ 3894 U16 Reserved3; /*0x12 */ 3895 U16 FatalErrorCount; /*0x14 */ 3896 U16 Reserved4; /*0x16 */ 3897 } MPI26_CONFIG_PAGE_PCIELINK_1, *PTR_MPI26_CONFIG_PAGE_PCIELINK_1, 3898 Mpi26PcieLinkPage1_t, *pMpi26PcieLinkPage1_t; 3899 3900 #define MPI26_PCIELINK1_PAGEVERSION (0x00) 3901 3902 /*PCIe Link Page 2 */ 3903 3904 typedef struct _MPI26_PCIELINK2_LINK_EVENT { 3905 U8 LinkEventCode; /*0x00 */ 3906 U8 Reserved1; /*0x01 */ 3907 U16 Reserved2; /*0x02 */ 3908 U32 LinkEventInfo; /*0x04 */ 3909 } MPI26_PCIELINK2_LINK_EVENT, *PTR_MPI26_PCIELINK2_LINK_EVENT, 3910 Mpi26PcieLink2LinkEvent_t, *pMpi26PcieLink2LinkEvent_t; 3911 3912 /*use MPI26_PCIELINK3_EVTCODE_ for the LinkEventCode field */ 3913 3914 3915 /* 3916 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3917 *one and check the value returned for NumLinkEvents at runtime. 3918 */ 3919 #ifndef MPI26_PCIELINK2_LINK_EVENT_MAX 3920 #define MPI26_PCIELINK2_LINK_EVENT_MAX (1) 3921 #endif 3922 3923 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_2 { 3924 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3925 U8 Link; /*0x08 */ 3926 U8 Reserved1; /*0x09 */ 3927 U16 Reserved2; /*0x0A */ 3928 U8 NumLinkEvents; /*0x0C */ 3929 U8 Reserved3; /*0x0D */ 3930 U16 Reserved4; /*0x0E */ 3931 MPI26_PCIELINK2_LINK_EVENT 3932 LinkEvent[MPI26_PCIELINK2_LINK_EVENT_MAX]; /*0x10 */ 3933 } MPI26_CONFIG_PAGE_PCIELINK_2, *PTR_MPI26_CONFIG_PAGE_PCIELINK_2, 3934 Mpi26PcieLinkPage2_t, *pMpi26PcieLinkPage2_t; 3935 3936 #define MPI26_PCIELINK2_PAGEVERSION (0x00) 3937 3938 /*PCIe Link Page 3 */ 3939 3940 typedef struct _MPI26_PCIELINK3_LINK_EVENT_CONFIG { 3941 U8 LinkEventCode; /*0x00 */ 3942 U8 Reserved1; /*0x01 */ 3943 U16 Reserved2; /*0x02 */ 3944 U8 CounterType; /*0x04 */ 3945 U8 ThresholdWindow; /*0x05 */ 3946 U8 TimeUnits; /*0x06 */ 3947 U8 Reserved3; /*0x07 */ 3948 U32 EventThreshold; /*0x08 */ 3949 U16 ThresholdFlags; /*0x0C */ 3950 U16 Reserved4; /*0x0E */ 3951 } MPI26_PCIELINK3_LINK_EVENT_CONFIG, *PTR_MPI26_PCIELINK3_LINK_EVENT_CONFIG, 3952 Mpi26PcieLink3LinkEventConfig_t, *pMpi26PcieLink3LinkEventConfig_t; 3953 3954 /*values for LinkEventCode field */ 3955 #define MPI26_PCIELINK3_EVTCODE_NO_EVENT (0x00) 3956 #define MPI26_PCIELINK3_EVTCODE_CORRECTABLE_ERROR_RECEIVED (0x01) 3957 #define MPI26_PCIELINK3_EVTCODE_NON_FATAL_ERROR_RECEIVED (0x02) 3958 #define MPI26_PCIELINK3_EVTCODE_FATAL_ERROR_RECEIVED (0x03) 3959 #define MPI26_PCIELINK3_EVTCODE_DATA_LINK_ERROR_DETECTED (0x04) 3960 #define MPI26_PCIELINK3_EVTCODE_TRANSACTION_LAYER_ERROR_DETECTED (0x05) 3961 #define MPI26_PCIELINK3_EVTCODE_TLP_ECRC_ERROR_DETECTED (0x06) 3962 #define MPI26_PCIELINK3_EVTCODE_POISONED_TLP (0x07) 3963 #define MPI26_PCIELINK3_EVTCODE_RECEIVED_NAK_DLLP (0x08) 3964 #define MPI26_PCIELINK3_EVTCODE_SENT_NAK_DLLP (0x09) 3965 #define MPI26_PCIELINK3_EVTCODE_LTSSM_RECOVERY_STATE (0x0A) 3966 #define MPI26_PCIELINK3_EVTCODE_LTSSM_RXL0S_STATE (0x0B) 3967 #define MPI26_PCIELINK3_EVTCODE_LTSSM_TXL0S_STATE (0x0C) 3968 #define MPI26_PCIELINK3_EVTCODE_LTSSM_L1_STATE (0x0D) 3969 #define MPI26_PCIELINK3_EVTCODE_LTSSM_DISABLED_STATE (0x0E) 3970 #define MPI26_PCIELINK3_EVTCODE_LTSSM_HOT_RESET_STATE (0x0F) 3971 #define MPI26_PCIELINK3_EVTCODE_SYSTEM_ERROR (0x10) 3972 #define MPI26_PCIELINK3_EVTCODE_DECODE_ERROR (0x11) 3973 #define MPI26_PCIELINK3_EVTCODE_DISPARITY_ERROR (0x12) 3974 3975 /*values for the CounterType field */ 3976 #define MPI26_PCIELINK3_COUNTER_TYPE_WRAPPING (0x00) 3977 #define MPI26_PCIELINK3_COUNTER_TYPE_SATURATING (0x01) 3978 #define MPI26_PCIELINK3_COUNTER_TYPE_PEAK_VALUE (0x02) 3979 3980 /*values for the TimeUnits field */ 3981 #define MPI26_PCIELINK3_TM_UNITS_10_MICROSECONDS (0x00) 3982 #define MPI26_PCIELINK3_TM_UNITS_100_MICROSECONDS (0x01) 3983 #define MPI26_PCIELINK3_TM_UNITS_1_MILLISECOND (0x02) 3984 #define MPI26_PCIELINK3_TM_UNITS_10_MILLISECONDS (0x03) 3985 3986 /*values for the ThresholdFlags field */ 3987 #define MPI26_PCIELINK3_TFLAGS_EVENT_NOTIFY (0x0001) 3988 3989 /* 3990 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3991 *one and check the value returned for NumLinkEvents at runtime. 3992 */ 3993 #ifndef MPI26_PCIELINK3_LINK_EVENT_MAX 3994 #define MPI26_PCIELINK3_LINK_EVENT_MAX (1) 3995 #endif 3996 3997 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_3 { 3998 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3999 U8 Link; /*0x08 */ 4000 U8 Reserved1; /*0x09 */ 4001 U16 Reserved2; /*0x0A */ 4002 U8 NumLinkEvents; /*0x0C */ 4003 U8 Reserved3; /*0x0D */ 4004 U16 Reserved4; /*0x0E */ 4005 MPI26_PCIELINK3_LINK_EVENT_CONFIG 4006 LinkEventConfig[MPI26_PCIELINK3_LINK_EVENT_MAX]; /*0x10 */ 4007 } MPI26_CONFIG_PAGE_PCIELINK_3, *PTR_MPI26_CONFIG_PAGE_PCIELINK_3, 4008 Mpi26PcieLinkPage3_t, *pMpi26PcieLinkPage3_t; 4009 4010 #define MPI26_PCIELINK3_PAGEVERSION (0x00) 4011 4012 4013 #endif 4014