1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright 2000-2020 Broadcom Inc. All rights reserved. 4 * 5 * 6 * Name: mpi2_cnfg.h 7 * Title: MPI Configuration messages and pages 8 * Creation Date: November 10, 2006 9 * 10 * mpi2_cnfg.h Version: 02.00.46 11 * 12 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 13 * prefix are for use only on MPI v2.5 products, and must not be used 14 * with MPI v2.0 products. Unless otherwise noted, names beginning with 15 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 16 * 17 * Version History 18 * --------------- 19 * 20 * Date Version Description 21 * -------- -------- ------------------------------------------------------ 22 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 23 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags. 24 * Added Manufacturing Page 11. 25 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE 26 * define. 27 * 06-26-07 02.00.02 Adding generic structure for product-specific 28 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS. 29 * Rework of BIOS Page 2 configuration page. 30 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the 31 * forms. 32 * Added configuration pages IOC Page 8 and Driver 33 * Persistent Mapping Page 0. 34 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated 35 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1, 36 * RAID Physical Disk Pages 0 and 1, RAID Configuration 37 * Page 0). 38 * Added new value for AccessStatus field of SAS Device 39 * Page 0 (_SATA_NEEDS_INITIALIZATION). 40 * 10-31-07 02.00.04 Added missing SEPDevHandle field to 41 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 42 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for 43 * NVDATA. 44 * Modified IOC Page 7 to use masks and added field for 45 * SASBroadcastPrimitiveMasks. 46 * Added MPI2_CONFIG_PAGE_BIOS_4. 47 * Added MPI2_CONFIG_PAGE_LOG_0. 48 * 02-29-08 02.00.06 Modified various names to make them 32-character unique. 49 * Added SAS Device IDs. 50 * Updated Integrated RAID configuration pages including 51 * Manufacturing Page 4, IOC Page 6, and RAID Configuration 52 * Page 0. 53 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA. 54 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION. 55 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING. 56 * Added missing MaxNumRoutedSasAddresses field to 57 * MPI2_CONFIG_PAGE_EXPANDER_0. 58 * Added SAS Port Page 0. 59 * Modified structure layout for 60 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0. 61 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use 62 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array. 63 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF 64 * to 0x000000FF. 65 * Added two new values for the Physical Disk Coercion Size 66 * bits in the Flags field of Manufacturing Page 4. 67 * Added product-specific Manufacturing pages 16 to 31. 68 * Modified Flags bits for controlling write cache on SATA 69 * drives in IO Unit Page 1. 70 * Added new bit to AdditionalControlFlags of SAS IO Unit 71 * Page 1 to control Invalid Topology Correction. 72 * Added additional defines for RAID Volume Page 0 73 * VolumeStatusFlags field. 74 * Modified meaning of RAID Volume Page 0 VolumeSettings 75 * define for auto-configure of hot-swap drives. 76 * Added SupportedPhysDisks field to RAID Volume Page 1 and 77 * added related defines. 78 * Added PhysDiskAttributes field (and related defines) to 79 * RAID Physical Disk Page 0. 80 * Added MPI2_SAS_PHYINFO_PHY_VACANT define. 81 * Added three new DiscoveryStatus bits for SAS IO Unit 82 * Page 0 and SAS Expander Page 0. 83 * Removed multiplexing information from SAS IO Unit pages. 84 * Added BootDeviceWaitTime field to SAS IO Unit Page 4. 85 * Removed Zone Address Resolved bit from PhyInfo and from 86 * Expander Page 0 Flags field. 87 * Added two new AccessStatus values to SAS Device Page 0 88 * for indicating routing problems. Added 3 reserved words 89 * to this page. 90 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3. 91 * Inserted missing reserved field into structure for IOC 92 * Page 6. 93 * Added more pending task bits to RAID Volume Page 0 94 * VolumeStatusFlags defines. 95 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define. 96 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0 97 * and SAS Expander Page 0 to flag a downstream initiator 98 * when in simplified routing mode. 99 * Removed SATA Init Failure defines for DiscoveryStatus 100 * fields of SAS IO Unit Page 0 and SAS Expander Page 0. 101 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define. 102 * Added PortGroups, DmaGroup, and ControlGroup fields to 103 * SAS Device Page 0. 104 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO 105 * Unit Page 6. 106 * Added expander reduced functionality data to SAS 107 * Expander Page 0. 108 * Added SAS PHY Page 2 and SAS PHY Page 3. 109 * 07-30-09 02.00.12 Added IO Unit Page 7. 110 * Added new device ids. 111 * Added SAS IO Unit Page 5. 112 * Added partial and slumber power management capable flags 113 * to SAS Device Page 0 Flags field. 114 * Added PhyInfo defines for power condition. 115 * Added Ethernet configuration pages. 116 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY. 117 * Added SAS PHY Page 4 structure and defines. 118 * 02-10-10 02.00.14 Modified the comments for the configuration page 119 * structures that contain an array of data. The host 120 * should use the "count" field in the page data (e.g. the 121 * NumPhys field) to determine the number of valid elements 122 * in the array. 123 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines. 124 * Added PowerManagementCapabilities to IO Unit Page 7. 125 * Added PortWidthModGroup field to 126 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS. 127 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines. 128 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines. 129 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines. 130 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT 131 * define. 132 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define. 133 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define. 134 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing) 135 * defines. 136 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to 137 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for 138 * the Pinout field. 139 * Added BoardTemperature and BoardTemperatureUnits fields 140 * to MPI2_CONFIG_PAGE_IO_UNIT_7. 141 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define 142 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure. 143 * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST. 144 * Added IO Unit Page 8, IO Unit Page 9, 145 * and IO Unit Page 10. 146 * Added SASNotifyPrimitiveMasks field to 147 * MPI2_CONFIG_PAGE_IOC_7. 148 * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec). 149 * 05-25-11 02.00.20 Cleaned up a few comments. 150 * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities 151 * for PCIe link as obsolete. 152 * Added SpinupFlags field containing a Disable Spin-up bit 153 * to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO 154 * Unit Page 4. 155 * 11-18-11 02.00.22 Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT. 156 * Added UEFIVersion field to BIOS Page 1 and defined new 157 * BiosOptions bits. 158 * Incorporating additions for MPI v2.5. 159 * 11-27-12 02.00.23 Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER. 160 * Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID. 161 * 12-20-12 02.00.24 Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as 162 * obsolete for MPI v2.5 and later. 163 * Added some defines for 12G SAS speeds. 164 * 04-09-13 02.00.25 Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK. 165 * Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to 166 * match the specification. 167 * 08-19-13 02.00.26 Added reserved words to MPI2_CONFIG_PAGE_IO_UNIT_7 for 168 * future use. 169 * 12-05-13 02.00.27 Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for 170 * MPI2_CONFIG_PAGE_MAN_7. 171 * Added EnclosureLevel and ConnectorName fields to 172 * MPI2_CONFIG_PAGE_SAS_DEV_0. 173 * Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for 174 * MPI2_CONFIG_PAGE_SAS_DEV_0. 175 * Added EnclosureLevel field to 176 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 177 * Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for 178 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 179 * 01-08-14 02.00.28 Added more defines for the BiosOptions field of 180 * MPI2_CONFIG_PAGE_BIOS_1. 181 * 06-13-14 02.00.29 Added SSUTimeout field to MPI2_CONFIG_PAGE_BIOS_1, and 182 * more defines for the BiosOptions field. 183 * 11-18-14 02.00.30 Updated copyright information. 184 * Added MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG. 185 * Added AdapterOrderAux fields to BIOS Page 3. 186 * 03-16-15 02.00.31 Updated for MPI v2.6. 187 * Added Flags field to IO Unit Page 7. 188 * Added new SAS Phy Event codes 189 * 05-25-15 02.00.33 Added more defines for the BiosOptions field of 190 * MPI2_CONFIG_PAGE_BIOS_1. 191 * 08-25-15 02.00.34 Bumped Header Version. 192 * 12-18-15 02.00.35 Added SATADeviceWaitTime to SAS IO Unit Page 4. 193 * 01-21-16 02.00.36 Added/modified MPI2_MFGPAGE_DEVID_SAS defines. 194 * Added Link field to PCIe Link Pages 195 * Added EnclosureLevel and ConnectorName to PCIe 196 * Device Page 0. 197 * Added define for PCIE IoUnit page 1 max rate shift. 198 * Added comment for reserved ExtPageTypes. 199 * Added SAS 4 22.5 gbs speed support. 200 * Added PCIe 4 16.0 GT/sec speec support. 201 * Removed AHCI support. 202 * Removed SOP support. 203 * Added NegotiatedLinkRate and NegotiatedPortWidth to 204 * PCIe device page 0. 205 * 04-10-16 02.00.37 Fixed MPI2_MFGPAGE_DEVID_SAS3616/3708 defines 206 * 07-01-16 02.00.38 Added Manufacturing page 7 Connector types. 207 * Changed declaration of ConnectorName in PCIe DevicePage0 208 * to match SAS DevicePage 0. 209 * Added SATADeviceWaitTime to IO Unit Page 11. 210 * Added MPI26_MFGPAGE_DEVID_SAS4008 211 * Added x16 PCIe width to IO Unit Page 7 212 * Added LINKFLAGS to control SRIS in PCIe IO Unit page 1 213 * phy data. 214 * Added InitStatus to PCIe IO Unit Page 1 header. 215 * 09-01-16 02.00.39 Added MPI26_CONFIG_PAGE_ENCLOSURE_0 and related defines. 216 * Added MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE and 217 * MPI26_ENCLOS_PGAD_FORM_HANDLE page address formats. 218 * 02-02-17 02.00.40 Added MPI2_MANPAGE7_SLOT_UNKNOWN. 219 * Added ChassisSlot field to SAS Enclosure Page 0. 220 * Added ChassisSlot Valid bit (bit 5) to the Flags field 221 * in SAS Enclosure Page 0. 222 * 06-13-17 02.00.41 Added MPI26_MFGPAGE_DEVID_SAS3816 and 223 * MPI26_MFGPAGE_DEVID_SAS3916 defines. 224 * Removed MPI26_MFGPAGE_DEVID_SAS4008 define. 225 * Added MPI26_PCIEIOUNIT1_LINKFLAGS_SRNS_EN define. 226 * Renamed PI26_PCIEIOUNIT1_LINKFLAGS_EN_SRIS to 227 * PI26_PCIEIOUNIT1_LINKFLAGS_SRIS_EN. 228 * Renamed MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SRIS to 229 * MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SEPARATE_REFCLK. 230 * 09-29-17 02.00.42 Added ControllerResetTO field to PCIe Device Page 2. 231 * Added NOIOB field to PCIe Device Page 2. 232 * Added MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN to 233 * the Capabilities field of PCIe Device Page 2. 234 * 07-22-18 02.00.43 Added defines for SAS3916 and SAS3816. 235 * Added WRiteCache defines to IO Unit Page 1. 236 * Added MaxEnclosureLevel to BIOS Page 1. 237 * Added OEMRD to SAS Enclosure Page 1. 238 * Added DMDReportPCIe to PCIe IO Unit Page 1. 239 * Added Flags field and flags for Retimers to 240 * PCIe Switch Page 1. 241 * 08-02-18 02.00.44 Added Slotx2, Slotx4 to ManPage 7. 242 * 08-15-18 02.00.45 Added ProductSpecific field at end of IOC Page 1 243 * 08-28-18 02.00.46 Added NVMs Write Cache flag to IOUnitPage1 244 * Added DMDReport Delay Time defines to 245 * PCIeIOUnitPage1 246 * -------------------------------------------------------------------------- 247 */ 248 249 #ifndef MPI2_CNFG_H 250 #define MPI2_CNFG_H 251 252 /***************************************************************************** 253 * Configuration Page Header and defines 254 *****************************************************************************/ 255 256 /*Config Page Header */ 257 typedef struct _MPI2_CONFIG_PAGE_HEADER { 258 U8 PageVersion; /*0x00 */ 259 U8 PageLength; /*0x01 */ 260 U8 PageNumber; /*0x02 */ 261 U8 PageType; /*0x03 */ 262 } MPI2_CONFIG_PAGE_HEADER, *PTR_MPI2_CONFIG_PAGE_HEADER, 263 Mpi2ConfigPageHeader_t, *pMpi2ConfigPageHeader_t; 264 265 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION { 266 MPI2_CONFIG_PAGE_HEADER Struct; 267 U8 Bytes[4]; 268 U16 Word16[2]; 269 U32 Word32; 270 } MPI2_CONFIG_PAGE_HEADER_UNION, *PTR_MPI2_CONFIG_PAGE_HEADER_UNION, 271 Mpi2ConfigPageHeaderUnion, *pMpi2ConfigPageHeaderUnion; 272 273 /*Extended Config Page Header */ 274 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER { 275 U8 PageVersion; /*0x00 */ 276 U8 Reserved1; /*0x01 */ 277 U8 PageNumber; /*0x02 */ 278 U8 PageType; /*0x03 */ 279 U16 ExtPageLength; /*0x04 */ 280 U8 ExtPageType; /*0x06 */ 281 U8 Reserved2; /*0x07 */ 282 } MPI2_CONFIG_EXTENDED_PAGE_HEADER, 283 *PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER, 284 Mpi2ConfigExtendedPageHeader_t, 285 *pMpi2ConfigExtendedPageHeader_t; 286 287 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION { 288 MPI2_CONFIG_PAGE_HEADER Struct; 289 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext; 290 U8 Bytes[8]; 291 U16 Word16[4]; 292 U32 Word32[2]; 293 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 294 *PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 295 Mpi2ConfigPageExtendedHeaderUnion, 296 *pMpi2ConfigPageExtendedHeaderUnion; 297 298 299 /*PageType field values */ 300 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 301 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 302 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 303 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0) 304 305 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00) 306 #define MPI2_CONFIG_PAGETYPE_IOC (0x01) 307 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02) 308 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 309 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09) 310 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 311 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F) 312 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F) 313 314 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF) 315 316 317 /*ExtPageType field values */ 318 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 319 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 320 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 321 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 322 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14) 323 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 324 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 325 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 326 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 327 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19) 328 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A) 329 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_IO_UNIT (0x1B) 330 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_SWITCH (0x1C) 331 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_DEVICE (0x1D) 332 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_LINK (0x1E) 333 334 335 /***************************************************************************** 336 * PageAddress defines 337 *****************************************************************************/ 338 339 /*RAID Volume PageAddress format */ 340 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000) 341 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 342 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000) 343 344 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF) 345 346 347 /*RAID Physical Disk PageAddress format */ 348 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000) 349 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000) 350 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000) 351 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000) 352 353 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 354 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF) 355 356 357 /*SAS Expander PageAddress format */ 358 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 359 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 360 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000) 361 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000) 362 363 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) 364 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) 365 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 366 367 368 /*SAS Device PageAddress format */ 369 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 370 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 371 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000) 372 373 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 374 375 376 /*SAS PHY PageAddress format */ 377 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 378 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 379 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000) 380 381 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 382 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 383 384 385 /*SAS Port PageAddress format */ 386 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000) 387 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 388 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 389 390 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF) 391 392 393 /*SAS Enclosure PageAddress format */ 394 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 395 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 396 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 397 398 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 399 400 /*Enclosure PageAddress format */ 401 #define MPI26_ENCLOS_PGAD_FORM_MASK (0xF0000000) 402 #define MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 403 #define MPI26_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 404 405 #define MPI26_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 406 407 /*RAID Configuration PageAddress format */ 408 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000) 409 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000) 410 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000) 411 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000) 412 413 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF) 414 415 416 /*Driver Persistent Mapping PageAddress format */ 417 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000) 418 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000) 419 420 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000) 421 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16) 422 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF) 423 424 425 /*Ethernet PageAddress format */ 426 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000) 427 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000) 428 429 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF) 430 431 432 /*PCIe Switch PageAddress format */ 433 #define MPI26_PCIE_SWITCH_PGAD_FORM_MASK (0xF0000000) 434 #define MPI26_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 435 #define MPI26_PCIE_SWITCH_PGAD_FORM_HNDL_PORTNUM (0x10000000) 436 #define MPI26_PCIE_SWITCH_EXPAND_PGAD_FORM_HNDL (0x20000000) 437 438 #define MPI26_PCIE_SWITCH_PGAD_HANDLE_MASK (0x0000FFFF) 439 #define MPI26_PCIE_SWITCH_PGAD_PORTNUM_MASK (0x00FF0000) 440 #define MPI26_PCIE_SWITCH_PGAD_PORTNUM_SHIFT (16) 441 442 443 /*PCIe Device PageAddress format */ 444 #define MPI26_PCIE_DEVICE_PGAD_FORM_MASK (0xF0000000) 445 #define MPI26_PCIE_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 446 #define MPI26_PCIE_DEVICE_PGAD_FORM_HANDLE (0x20000000) 447 448 #define MPI26_PCIE_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 449 450 /*PCIe Link PageAddress format */ 451 #define MPI26_PCIE_LINK_PGAD_FORM_MASK (0xF0000000) 452 #define MPI26_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK (0x00000000) 453 #define MPI26_PCIE_LINK_PGAD_FORM_LINK_NUM (0x10000000) 454 455 #define MPI26_PCIE_DEVICE_PGAD_LINKNUM_MASK (0x000000FF) 456 457 458 459 /**************************************************************************** 460 * Configuration messages 461 ****************************************************************************/ 462 463 /*Configuration Request Message */ 464 typedef struct _MPI2_CONFIG_REQUEST { 465 U8 Action; /*0x00 */ 466 U8 SGLFlags; /*0x01 */ 467 U8 ChainOffset; /*0x02 */ 468 U8 Function; /*0x03 */ 469 U16 ExtPageLength; /*0x04 */ 470 U8 ExtPageType; /*0x06 */ 471 U8 MsgFlags; /*0x07 */ 472 U8 VP_ID; /*0x08 */ 473 U8 VF_ID; /*0x09 */ 474 U16 Reserved1; /*0x0A */ 475 U8 Reserved2; /*0x0C */ 476 U8 ProxyVF_ID; /*0x0D */ 477 U16 Reserved4; /*0x0E */ 478 U32 Reserved3; /*0x10 */ 479 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */ 480 U32 PageAddress; /*0x18 */ 481 MPI2_SGE_IO_UNION PageBufferSGE; /*0x1C */ 482 } MPI2_CONFIG_REQUEST, *PTR_MPI2_CONFIG_REQUEST, 483 Mpi2ConfigRequest_t, *pMpi2ConfigRequest_t; 484 485 /*values for the Action field */ 486 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00) 487 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 488 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 489 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03) 490 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 491 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 492 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 493 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07) 494 495 /*use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */ 496 497 498 /*Config Reply Message */ 499 typedef struct _MPI2_CONFIG_REPLY { 500 U8 Action; /*0x00 */ 501 U8 SGLFlags; /*0x01 */ 502 U8 MsgLength; /*0x02 */ 503 U8 Function; /*0x03 */ 504 U16 ExtPageLength; /*0x04 */ 505 U8 ExtPageType; /*0x06 */ 506 U8 MsgFlags; /*0x07 */ 507 U8 VP_ID; /*0x08 */ 508 U8 VF_ID; /*0x09 */ 509 U16 Reserved1; /*0x0A */ 510 U16 Reserved2; /*0x0C */ 511 U16 IOCStatus; /*0x0E */ 512 U32 IOCLogInfo; /*0x10 */ 513 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */ 514 } MPI2_CONFIG_REPLY, *PTR_MPI2_CONFIG_REPLY, 515 Mpi2ConfigReply_t, *pMpi2ConfigReply_t; 516 517 518 519 /***************************************************************************** 520 * 521 * C o n f i g u r a t i o n P a g e s 522 * 523 *****************************************************************************/ 524 525 /**************************************************************************** 526 * Manufacturing Config pages 527 ****************************************************************************/ 528 529 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000) 530 531 /*MPI v2.0 SAS products */ 532 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070) 533 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072) 534 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074) 535 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076) 536 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077) 537 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064) 538 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065) 539 540 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E) 541 542 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080) 543 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081) 544 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082) 545 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083) 546 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084) 547 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085) 548 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086) 549 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087) 550 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E) 551 #define MPI2_MFGPAGE_DEVID_SAS2308_MPI_EP (0x02B0) 552 553 /*MPI v2.5 SAS products */ 554 #define MPI25_MFGPAGE_DEVID_SAS3004 (0x0096) 555 #define MPI25_MFGPAGE_DEVID_SAS3008 (0x0097) 556 #define MPI25_MFGPAGE_DEVID_SAS3108_1 (0x0090) 557 #define MPI25_MFGPAGE_DEVID_SAS3108_2 (0x0091) 558 #define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094) 559 #define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095) 560 561 /* MPI v2.6 SAS Products */ 562 #define MPI26_MFGPAGE_DEVID_SAS3216 (0x00C9) 563 #define MPI26_MFGPAGE_DEVID_SAS3224 (0x00C4) 564 #define MPI26_MFGPAGE_DEVID_SAS3316_1 (0x00C5) 565 #define MPI26_MFGPAGE_DEVID_SAS3316_2 (0x00C6) 566 #define MPI26_MFGPAGE_DEVID_SAS3316_3 (0x00C7) 567 #define MPI26_MFGPAGE_DEVID_SAS3316_4 (0x00C8) 568 #define MPI26_MFGPAGE_DEVID_SAS3324_1 (0x00C0) 569 #define MPI26_MFGPAGE_DEVID_SAS3324_2 (0x00C1) 570 #define MPI26_MFGPAGE_DEVID_SAS3324_3 (0x00C2) 571 #define MPI26_MFGPAGE_DEVID_SAS3324_4 (0x00C3) 572 573 #define MPI26_MFGPAGE_DEVID_SAS3516 (0x00AA) 574 #define MPI26_MFGPAGE_DEVID_SAS3516_1 (0x00AB) 575 #define MPI26_MFGPAGE_DEVID_SAS3416 (0x00AC) 576 #define MPI26_MFGPAGE_DEVID_SAS3508 (0x00AD) 577 #define MPI26_MFGPAGE_DEVID_SAS3508_1 (0x00AE) 578 #define MPI26_MFGPAGE_DEVID_SAS3408 (0x00AF) 579 #define MPI26_MFGPAGE_DEVID_SAS3716 (0x00D0) 580 #define MPI26_MFGPAGE_DEVID_SAS3616 (0x00D1) 581 #define MPI26_MFGPAGE_DEVID_SAS3708 (0x00D2) 582 583 #define MPI26_MFGPAGE_DEVID_SEC_MASK_3916 (0x0003) 584 #define MPI26_MFGPAGE_DEVID_INVALID0_3916 (0x00E0) 585 #define MPI26_MFGPAGE_DEVID_CFG_SEC_3916 (0x00E1) 586 #define MPI26_MFGPAGE_DEVID_HARD_SEC_3916 (0x00E2) 587 #define MPI26_MFGPAGE_DEVID_INVALID1_3916 (0x00E3) 588 589 #define MPI26_MFGPAGE_DEVID_SEC_MASK_3816 (0x0003) 590 #define MPI26_MFGPAGE_DEVID_INVALID0_3816 (0x00E4) 591 #define MPI26_MFGPAGE_DEVID_CFG_SEC_3816 (0x00E5) 592 #define MPI26_MFGPAGE_DEVID_HARD_SEC_3816 (0x00E6) 593 #define MPI26_MFGPAGE_DEVID_INVALID1_3816 (0x00E7) 594 595 596 /*Manufacturing Page 0 */ 597 598 typedef struct _MPI2_CONFIG_PAGE_MAN_0 { 599 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 600 U8 ChipName[16]; /*0x04 */ 601 U8 ChipRevision[8]; /*0x14 */ 602 U8 BoardName[16]; /*0x1C */ 603 U8 BoardAssembly[16]; /*0x2C */ 604 U8 BoardTracerNumber[16]; /*0x3C */ 605 } MPI2_CONFIG_PAGE_MAN_0, 606 *PTR_MPI2_CONFIG_PAGE_MAN_0, 607 Mpi2ManufacturingPage0_t, 608 *pMpi2ManufacturingPage0_t; 609 610 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00) 611 612 613 /*Manufacturing Page 1 */ 614 615 typedef struct _MPI2_CONFIG_PAGE_MAN_1 { 616 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 617 U8 VPD[256]; /*0x04 */ 618 } MPI2_CONFIG_PAGE_MAN_1, 619 *PTR_MPI2_CONFIG_PAGE_MAN_1, 620 Mpi2ManufacturingPage1_t, 621 *pMpi2ManufacturingPage1_t; 622 623 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00) 624 625 626 typedef struct _MPI2_CHIP_REVISION_ID { 627 U16 DeviceID; /*0x00 */ 628 U8 PCIRevisionID; /*0x02 */ 629 U8 Reserved; /*0x03 */ 630 } MPI2_CHIP_REVISION_ID, *PTR_MPI2_CHIP_REVISION_ID, 631 Mpi2ChipRevisionId_t, *pMpi2ChipRevisionId_t; 632 633 634 /*Manufacturing Page 2 */ 635 636 /* 637 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 638 *one and check Header.PageLength at runtime. 639 */ 640 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS 641 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 642 #endif 643 644 typedef struct _MPI2_CONFIG_PAGE_MAN_2 { 645 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 646 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */ 647 U32 648 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/*0x08 */ 649 } MPI2_CONFIG_PAGE_MAN_2, 650 *PTR_MPI2_CONFIG_PAGE_MAN_2, 651 Mpi2ManufacturingPage2_t, 652 *pMpi2ManufacturingPage2_t; 653 654 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00) 655 656 657 /*Manufacturing Page 3 */ 658 659 /* 660 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 661 *one and check Header.PageLength at runtime. 662 */ 663 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS 664 #define MPI2_MAN_PAGE_3_INFO_WORDS (1) 665 #endif 666 667 typedef struct _MPI2_CONFIG_PAGE_MAN_3 { 668 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 669 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */ 670 U32 671 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/*0x08 */ 672 } MPI2_CONFIG_PAGE_MAN_3, 673 *PTR_MPI2_CONFIG_PAGE_MAN_3, 674 Mpi2ManufacturingPage3_t, 675 *pMpi2ManufacturingPage3_t; 676 677 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00) 678 679 680 /*Manufacturing Page 4 */ 681 682 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS { 683 U8 PowerSaveFlags; /*0x00 */ 684 U8 InternalOperationsSleepTime; /*0x01 */ 685 U8 InternalOperationsRunTime; /*0x02 */ 686 U8 HostIdleTime; /*0x03 */ 687 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 688 *PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 689 Mpi2ManPage4PwrSaveSettings_t, 690 *pMpi2ManPage4PwrSaveSettings_t; 691 692 /*defines for the PowerSaveFlags field */ 693 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03) 694 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00) 695 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01) 696 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02) 697 698 typedef struct _MPI2_CONFIG_PAGE_MAN_4 { 699 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 700 U32 Reserved1; /*0x04 */ 701 U32 Flags; /*0x08 */ 702 U8 InquirySize; /*0x0C */ 703 U8 Reserved2; /*0x0D */ 704 U16 Reserved3; /*0x0E */ 705 U8 InquiryData[56]; /*0x10 */ 706 U32 RAID0VolumeSettings; /*0x48 */ 707 U32 RAID1EVolumeSettings; /*0x4C */ 708 U32 RAID1VolumeSettings; /*0x50 */ 709 U32 RAID10VolumeSettings; /*0x54 */ 710 U32 Reserved4; /*0x58 */ 711 U32 Reserved5; /*0x5C */ 712 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /*0x60 */ 713 U8 MaxOCEDisks; /*0x64 */ 714 U8 ResyncRate; /*0x65 */ 715 U16 DataScrubDuration; /*0x66 */ 716 U8 MaxHotSpares; /*0x68 */ 717 U8 MaxPhysDisksPerVol; /*0x69 */ 718 U8 MaxPhysDisks; /*0x6A */ 719 U8 MaxVolumes; /*0x6B */ 720 } MPI2_CONFIG_PAGE_MAN_4, 721 *PTR_MPI2_CONFIG_PAGE_MAN_4, 722 Mpi2ManufacturingPage4_t, 723 *pMpi2ManufacturingPage4_t; 724 725 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A) 726 727 /*Manufacturing Page 4 Flags field */ 728 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000) 729 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000) 730 731 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000) 732 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000) 733 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000) 734 735 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00) 736 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000) 737 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400) 738 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800) 739 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00) 740 741 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300) 742 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000) 743 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100) 744 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200) 745 746 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080) 747 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040) 748 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020) 749 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010) 750 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008) 751 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004) 752 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002) 753 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001) 754 755 756 /*Manufacturing Page 5 */ 757 758 /* 759 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 760 *one and check the value returned for NumPhys at runtime. 761 */ 762 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES 763 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1) 764 #endif 765 766 typedef struct _MPI2_MANUFACTURING5_ENTRY { 767 U64 WWID; /*0x00 */ 768 U64 DeviceName; /*0x08 */ 769 } MPI2_MANUFACTURING5_ENTRY, 770 *PTR_MPI2_MANUFACTURING5_ENTRY, 771 Mpi2Manufacturing5Entry_t, 772 *pMpi2Manufacturing5Entry_t; 773 774 typedef struct _MPI2_CONFIG_PAGE_MAN_5 { 775 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 776 U8 NumPhys; /*0x04 */ 777 U8 Reserved1; /*0x05 */ 778 U16 Reserved2; /*0x06 */ 779 U32 Reserved3; /*0x08 */ 780 U32 Reserved4; /*0x0C */ 781 MPI2_MANUFACTURING5_ENTRY 782 Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/*0x08 */ 783 } MPI2_CONFIG_PAGE_MAN_5, 784 *PTR_MPI2_CONFIG_PAGE_MAN_5, 785 Mpi2ManufacturingPage5_t, 786 *pMpi2ManufacturingPage5_t; 787 788 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03) 789 790 791 /*Manufacturing Page 6 */ 792 793 typedef struct _MPI2_CONFIG_PAGE_MAN_6 { 794 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 795 U32 ProductSpecificInfo;/*0x04 */ 796 } MPI2_CONFIG_PAGE_MAN_6, 797 *PTR_MPI2_CONFIG_PAGE_MAN_6, 798 Mpi2ManufacturingPage6_t, 799 *pMpi2ManufacturingPage6_t; 800 801 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00) 802 803 804 /*Manufacturing Page 7 */ 805 806 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO { 807 U32 Pinout; /*0x00 */ 808 U8 Connector[16]; /*0x04 */ 809 U8 Location; /*0x14 */ 810 U8 ReceptacleID; /*0x15 */ 811 U16 Slot; /*0x16 */ 812 U32 Reserved2; /*0x18 */ 813 } MPI2_MANPAGE7_CONNECTOR_INFO, 814 *PTR_MPI2_MANPAGE7_CONNECTOR_INFO, 815 Mpi2ManPage7ConnectorInfo_t, 816 *pMpi2ManPage7ConnectorInfo_t; 817 818 /*defines for the Pinout field */ 819 #define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00) 820 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8) 821 822 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF) 823 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00) 824 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01) 825 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02) 826 #define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03) 827 #define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04) 828 #define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05) 829 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06) 830 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07) 831 #define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08) 832 #define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09) 833 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A) 834 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B) 835 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C) 836 #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D) 837 #define MPI2_MANPAGE7_PINOUT_SFF_8088_A (0x0E) 838 #define MPI2_MANPAGE7_PINOUT_SFF_8643_16i (0x0F) 839 #define MPI2_MANPAGE7_PINOUT_SFF_8654_4i (0x10) 840 #define MPI2_MANPAGE7_PINOUT_SFF_8654_8i (0x11) 841 #define MPI2_MANPAGE7_PINOUT_SFF_8611_4i (0x12) 842 #define MPI2_MANPAGE7_PINOUT_SFF_8611_8i (0x13) 843 844 /*defines for the Location field */ 845 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01) 846 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02) 847 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04) 848 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08) 849 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10) 850 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 851 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 852 853 /*defines for the Slot field */ 854 #define MPI2_MANPAGE7_SLOT_UNKNOWN (0xFFFF) 855 856 /* 857 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 858 *one and check the value returned for NumPhys at runtime. 859 */ 860 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX 861 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1) 862 #endif 863 864 typedef struct _MPI2_CONFIG_PAGE_MAN_7 { 865 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 866 U32 Reserved1; /*0x04 */ 867 U32 Reserved2; /*0x08 */ 868 U32 Flags; /*0x0C */ 869 U8 EnclosureName[16]; /*0x10 */ 870 U8 NumPhys; /*0x20 */ 871 U8 Reserved3; /*0x21 */ 872 U16 Reserved4; /*0x22 */ 873 MPI2_MANPAGE7_CONNECTOR_INFO 874 ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /*0x24 */ 875 } MPI2_CONFIG_PAGE_MAN_7, 876 *PTR_MPI2_CONFIG_PAGE_MAN_7, 877 Mpi2ManufacturingPage7_t, 878 *pMpi2ManufacturingPage7_t; 879 880 #define MPI2_MANUFACTURING7_PAGEVERSION (0x01) 881 882 /*defines for the Flags field */ 883 #define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL (0x00000008) 884 #define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER (0x00000002) 885 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 886 887 888 /* 889 *Generic structure to use for product-specific manufacturing pages 890 *(currently Manufacturing Page 8 through Manufacturing Page 31). 891 */ 892 893 typedef struct _MPI2_CONFIG_PAGE_MAN_PS { 894 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 895 U32 ProductSpecificInfo;/*0x04 */ 896 } MPI2_CONFIG_PAGE_MAN_PS, 897 *PTR_MPI2_CONFIG_PAGE_MAN_PS, 898 Mpi2ManufacturingPagePS_t, 899 *pMpi2ManufacturingPagePS_t; 900 901 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00) 902 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00) 903 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00) 904 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00) 905 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00) 906 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00) 907 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00) 908 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00) 909 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00) 910 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00) 911 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00) 912 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00) 913 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00) 914 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00) 915 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00) 916 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00) 917 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00) 918 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00) 919 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00) 920 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00) 921 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00) 922 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00) 923 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00) 924 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00) 925 926 927 /**************************************************************************** 928 * IO Unit Config Pages 929 ****************************************************************************/ 930 931 /*IO Unit Page 0 */ 932 933 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 { 934 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 935 U64 UniqueValue; /*0x04 */ 936 MPI2_VERSION_UNION NvdataVersionDefault; /*0x08 */ 937 MPI2_VERSION_UNION NvdataVersionPersistent; /*0x0A */ 938 } MPI2_CONFIG_PAGE_IO_UNIT_0, 939 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_0, 940 Mpi2IOUnitPage0_t, *pMpi2IOUnitPage0_t; 941 942 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02) 943 944 945 /*IO Unit Page 1 */ 946 947 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 { 948 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 949 U32 Flags; /*0x04 */ 950 } MPI2_CONFIG_PAGE_IO_UNIT_1, 951 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_1, 952 Mpi2IOUnitPage1_t, *pMpi2IOUnitPage1_t; 953 954 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04) 955 956 /* IO Unit Page 1 Flags defines */ 957 #define MPI26_IOUNITPAGE1_NVME_WRCACHE_MASK (0x00030000) 958 #define MPI26_IOUNITPAGE1_NVME_WRCACHE_ENABLE (0x00000000) 959 #define MPI26_IOUNITPAGE1_NVME_WRCACHE_DISABLE (0x00010000) 960 #define MPI26_IOUNITPAGE1_NVME_WRCACHE_NO_CHANGE (0x00020000) 961 #define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK (0x00004000) 962 #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000) 963 #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000) 964 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800) 965 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600) 966 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9) 967 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000) 968 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200) 969 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400) 970 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 971 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040) 972 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020) 973 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 974 975 976 /*IO Unit Page 3 */ 977 978 /* 979 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 980 *one and check the value returned for GPIOCount at runtime. 981 */ 982 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX 983 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 984 #endif 985 986 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 { 987 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 988 U8 GPIOCount; /*0x04 */ 989 U8 Reserved1; /*0x05 */ 990 U16 Reserved2; /*0x06 */ 991 U16 992 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/*0x08 */ 993 } MPI2_CONFIG_PAGE_IO_UNIT_3, 994 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_3, 995 Mpi2IOUnitPage3_t, *pMpi2IOUnitPage3_t; 996 997 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01) 998 999 /*defines for IO Unit Page 3 GPIOVal field */ 1000 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC) 1001 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 1002 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000) 1003 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001) 1004 1005 1006 /*IO Unit Page 5 */ 1007 1008 /* 1009 *Upper layer code (drivers, utilities, etc.) should leave this define set to 1010 *one and check the value returned for NumDmaEngines at runtime. 1011 */ 1012 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES 1013 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1) 1014 #endif 1015 1016 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 { 1017 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1018 U64 1019 RaidAcceleratorBufferBaseAddress; /*0x04 */ 1020 U64 1021 RaidAcceleratorBufferSize; /*0x0C */ 1022 U64 1023 RaidAcceleratorControlBaseAddress; /*0x14 */ 1024 U8 RAControlSize; /*0x1C */ 1025 U8 NumDmaEngines; /*0x1D */ 1026 U8 RAMinControlSize; /*0x1E */ 1027 U8 RAMaxControlSize; /*0x1F */ 1028 U32 Reserved1; /*0x20 */ 1029 U32 Reserved2; /*0x24 */ 1030 U32 Reserved3; /*0x28 */ 1031 U32 1032 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /*0x2C */ 1033 } MPI2_CONFIG_PAGE_IO_UNIT_5, 1034 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_5, 1035 Mpi2IOUnitPage5_t, *pMpi2IOUnitPage5_t; 1036 1037 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00) 1038 1039 /*defines for IO Unit Page 5 DmaEngineCapabilities field */ 1040 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFFFF0000) 1041 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16) 1042 1043 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008) 1044 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004) 1045 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002) 1046 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001) 1047 1048 1049 /*IO Unit Page 6 */ 1050 1051 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 { 1052 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1053 U16 Flags; /*0x04 */ 1054 U8 RAHostControlSize; /*0x06 */ 1055 U8 Reserved0; /*0x07 */ 1056 U64 1057 RaidAcceleratorHostControlBaseAddress; /*0x08 */ 1058 U32 Reserved1; /*0x10 */ 1059 U32 Reserved2; /*0x14 */ 1060 U32 Reserved3; /*0x18 */ 1061 } MPI2_CONFIG_PAGE_IO_UNIT_6, 1062 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_6, 1063 Mpi2IOUnitPage6_t, *pMpi2IOUnitPage6_t; 1064 1065 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00) 1066 1067 /*defines for IO Unit Page 6 Flags field */ 1068 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001) 1069 1070 1071 /*IO Unit Page 7 */ 1072 1073 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 { 1074 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1075 U8 CurrentPowerMode; /*0x04 */ 1076 U8 PreviousPowerMode; /*0x05 */ 1077 U8 PCIeWidth; /*0x06 */ 1078 U8 PCIeSpeed; /*0x07 */ 1079 U32 ProcessorState; /*0x08 */ 1080 U32 1081 PowerManagementCapabilities; /*0x0C */ 1082 U16 IOCTemperature; /*0x10 */ 1083 U8 1084 IOCTemperatureUnits; /*0x12 */ 1085 U8 IOCSpeed; /*0x13 */ 1086 U16 BoardTemperature; /*0x14 */ 1087 U8 1088 BoardTemperatureUnits; /*0x16 */ 1089 U8 Reserved3; /*0x17 */ 1090 U32 BoardPowerRequirement; /*0x18 */ 1091 U32 PCISlotPowerAllocation; /*0x1C */ 1092 /* reserved prior to MPI v2.6 */ 1093 U8 Flags; /* 0x20 */ 1094 U8 Reserved6; /* 0x21 */ 1095 U16 Reserved7; /* 0x22 */ 1096 U32 Reserved8; /* 0x24 */ 1097 } MPI2_CONFIG_PAGE_IO_UNIT_7, 1098 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_7, 1099 Mpi2IOUnitPage7_t, *pMpi2IOUnitPage7_t; 1100 1101 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x05) 1102 1103 /*defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */ 1104 #define MPI25_IOUNITPAGE7_PM_INIT_MASK (0xC0) 1105 #define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE (0x00) 1106 #define MPI25_IOUNITPAGE7_PM_INIT_HOST (0x40) 1107 #define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT (0x80) 1108 #define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA (0xC0) 1109 1110 #define MPI25_IOUNITPAGE7_PM_MODE_MASK (0x07) 1111 #define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE (0x00) 1112 #define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN (0x01) 1113 #define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER (0x04) 1114 #define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER (0x05) 1115 #define MPI25_IOUNITPAGE7_PM_MODE_STANDBY (0x06) 1116 1117 1118 /*defines for IO Unit Page 7 PCIeWidth field */ 1119 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01) 1120 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02) 1121 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04) 1122 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08) 1123 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X16 (0x10) 1124 1125 /*defines for IO Unit Page 7 PCIeSpeed field */ 1126 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00) 1127 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01) 1128 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02) 1129 #define MPI2_IOUNITPAGE7_PCIE_SPEED_16_0_GBPS (0x03) 1130 1131 /*defines for IO Unit Page 7 ProcessorState field */ 1132 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F) 1133 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0) 1134 1135 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00) 1136 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01) 1137 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02) 1138 1139 /*defines for IO Unit Page 7 PowerManagementCapabilities field */ 1140 #define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE (0x00400000) 1141 #define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE (0x00200000) 1142 #define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE (0x00100000) 1143 #define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE (0x00040000) 1144 #define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE (0x00020000) 1145 #define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE (0x00010000) 1146 #define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE (0x00004000) 1147 #define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE (0x00002000) 1148 #define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE (0x00001000) 1149 #define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED (0x00000400) 1150 #define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED (0x00000200) 1151 #define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED (0x00000100) 1152 #define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED (0x00000040) 1153 #define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED (0x00000020) 1154 #define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED (0x00000010) 1155 #define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE (0x00000008) 1156 #define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE (0x00000004) 1157 #define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE (0x00000002) 1158 #define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE (0x00000001) 1159 1160 /*obsolete names for the PowerManagementCapabilities bits (above) */ 1161 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400) 1162 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200) 1163 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100) 1164 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /*obsolete */ 1165 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /*obsolete */ 1166 1167 1168 /*defines for IO Unit Page 7 IOCTemperatureUnits field */ 1169 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00) 1170 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01) 1171 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02) 1172 1173 /*defines for IO Unit Page 7 IOCSpeed field */ 1174 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01) 1175 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02) 1176 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04) 1177 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08) 1178 1179 /*defines for IO Unit Page 7 BoardTemperatureUnits field */ 1180 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00) 1181 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01) 1182 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02) 1183 1184 /* defines for IO Unit Page 7 Flags field */ 1185 #define MPI2_IOUNITPAGE7_FLAG_CABLE_POWER_EXC (0x01) 1186 1187 /*IO Unit Page 8 */ 1188 1189 #define MPI2_IOUNIT8_NUM_THRESHOLDS (4) 1190 1191 typedef struct _MPI2_IOUNIT8_SENSOR { 1192 U16 Flags; /*0x00 */ 1193 U16 Reserved1; /*0x02 */ 1194 U16 1195 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /*0x04 */ 1196 U32 Reserved2; /*0x0C */ 1197 U32 Reserved3; /*0x10 */ 1198 U32 Reserved4; /*0x14 */ 1199 } MPI2_IOUNIT8_SENSOR, *PTR_MPI2_IOUNIT8_SENSOR, 1200 Mpi2IOUnit8Sensor_t, *pMpi2IOUnit8Sensor_t; 1201 1202 /*defines for IO Unit Page 8 Sensor Flags field */ 1203 #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008) 1204 #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004) 1205 #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002) 1206 #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001) 1207 1208 /* 1209 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1210 *one and check the value returned for NumSensors at runtime. 1211 */ 1212 #ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES 1213 #define MPI2_IOUNITPAGE8_SENSOR_ENTRIES (1) 1214 #endif 1215 1216 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 { 1217 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1218 U32 Reserved1; /*0x04 */ 1219 U32 Reserved2; /*0x08 */ 1220 U8 NumSensors; /*0x0C */ 1221 U8 PollingInterval; /*0x0D */ 1222 U16 Reserved3; /*0x0E */ 1223 MPI2_IOUNIT8_SENSOR 1224 Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/*0x10 */ 1225 } MPI2_CONFIG_PAGE_IO_UNIT_8, 1226 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_8, 1227 Mpi2IOUnitPage8_t, *pMpi2IOUnitPage8_t; 1228 1229 #define MPI2_IOUNITPAGE8_PAGEVERSION (0x00) 1230 1231 1232 /*IO Unit Page 9 */ 1233 1234 typedef struct _MPI2_IOUNIT9_SENSOR { 1235 U16 CurrentTemperature; /*0x00 */ 1236 U16 Reserved1; /*0x02 */ 1237 U8 Flags; /*0x04 */ 1238 U8 Reserved2; /*0x05 */ 1239 U16 Reserved3; /*0x06 */ 1240 U32 Reserved4; /*0x08 */ 1241 U32 Reserved5; /*0x0C */ 1242 } MPI2_IOUNIT9_SENSOR, *PTR_MPI2_IOUNIT9_SENSOR, 1243 Mpi2IOUnit9Sensor_t, *pMpi2IOUnit9Sensor_t; 1244 1245 /*defines for IO Unit Page 9 Sensor Flags field */ 1246 #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01) 1247 1248 /* 1249 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1250 *one and check the value returned for NumSensors at runtime. 1251 */ 1252 #ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES 1253 #define MPI2_IOUNITPAGE9_SENSOR_ENTRIES (1) 1254 #endif 1255 1256 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 { 1257 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1258 U32 Reserved1; /*0x04 */ 1259 U32 Reserved2; /*0x08 */ 1260 U8 NumSensors; /*0x0C */ 1261 U8 Reserved4; /*0x0D */ 1262 U16 Reserved3; /*0x0E */ 1263 MPI2_IOUNIT9_SENSOR 1264 Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/*0x10 */ 1265 } MPI2_CONFIG_PAGE_IO_UNIT_9, 1266 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_9, 1267 Mpi2IOUnitPage9_t, *pMpi2IOUnitPage9_t; 1268 1269 #define MPI2_IOUNITPAGE9_PAGEVERSION (0x00) 1270 1271 1272 /*IO Unit Page 10 */ 1273 1274 typedef struct _MPI2_IOUNIT10_FUNCTION { 1275 U8 CreditPercent; /*0x00 */ 1276 U8 Reserved1; /*0x01 */ 1277 U16 Reserved2; /*0x02 */ 1278 } MPI2_IOUNIT10_FUNCTION, 1279 *PTR_MPI2_IOUNIT10_FUNCTION, 1280 Mpi2IOUnit10Function_t, 1281 *pMpi2IOUnit10Function_t; 1282 1283 /* 1284 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1285 *one and check the value returned for NumFunctions at runtime. 1286 */ 1287 #ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES 1288 #define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES (1) 1289 #endif 1290 1291 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 { 1292 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1293 U8 NumFunctions; /*0x04 */ 1294 U8 Reserved1; /*0x05 */ 1295 U16 Reserved2; /*0x06 */ 1296 U32 Reserved3; /*0x08 */ 1297 U32 Reserved4; /*0x0C */ 1298 MPI2_IOUNIT10_FUNCTION 1299 Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];/*0x10 */ 1300 } MPI2_CONFIG_PAGE_IO_UNIT_10, 1301 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_10, 1302 Mpi2IOUnitPage10_t, *pMpi2IOUnitPage10_t; 1303 1304 #define MPI2_IOUNITPAGE10_PAGEVERSION (0x01) 1305 1306 1307 /* IO Unit Page 11 (for MPI v2.6 and later) */ 1308 1309 typedef struct _MPI26_IOUNIT11_SPINUP_GROUP { 1310 U8 MaxTargetSpinup; /* 0x00 */ 1311 U8 SpinupDelay; /* 0x01 */ 1312 U8 SpinupFlags; /* 0x02 */ 1313 U8 Reserved1; /* 0x03 */ 1314 } MPI26_IOUNIT11_SPINUP_GROUP, 1315 *PTR_MPI26_IOUNIT11_SPINUP_GROUP, 1316 Mpi26IOUnit11SpinupGroup_t, 1317 *pMpi26IOUnit11SpinupGroup_t; 1318 1319 /* defines for IO Unit Page 11 SpinupFlags */ 1320 #define MPI26_IOUNITPAGE11_SPINUP_DISABLE_FLAG (0x01) 1321 1322 1323 /* 1324 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1325 * four and check the value returned for NumPhys at runtime. 1326 */ 1327 #ifndef MPI26_IOUNITPAGE11_PHY_MAX 1328 #define MPI26_IOUNITPAGE11_PHY_MAX (4) 1329 #endif 1330 1331 typedef struct _MPI26_CONFIG_PAGE_IO_UNIT_11 { 1332 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1333 U32 Reserved1; /*0x04 */ 1334 MPI26_IOUNIT11_SPINUP_GROUP SpinupGroupParameters[4]; /*0x08 */ 1335 U32 Reserved2; /*0x18 */ 1336 U32 Reserved3; /*0x1C */ 1337 U32 Reserved4; /*0x20 */ 1338 U8 BootDeviceWaitTime; /*0x24 */ 1339 U8 Reserved5; /*0x25 */ 1340 U16 Reserved6; /*0x26 */ 1341 U8 NumPhys; /*0x28 */ 1342 U8 PEInitialSpinupDelay; /*0x29 */ 1343 U8 PEReplyDelay; /*0x2A */ 1344 U8 Flags; /*0x2B */ 1345 U8 PHY[MPI26_IOUNITPAGE11_PHY_MAX];/*0x2C */ 1346 } MPI26_CONFIG_PAGE_IO_UNIT_11, 1347 *PTR_MPI26_CONFIG_PAGE_IO_UNIT_11, 1348 Mpi26IOUnitPage11_t, 1349 *pMpi26IOUnitPage11_t; 1350 1351 #define MPI26_IOUNITPAGE11_PAGEVERSION (0x00) 1352 1353 /* defines for Flags field */ 1354 #define MPI26_IOUNITPAGE11_FLAGS_AUTO_PORTENABLE (0x01) 1355 1356 /* defines for PHY field */ 1357 #define MPI26_IOUNITPAGE11_PHY_SPINUP_GROUP_MASK (0x03) 1358 1359 1360 1361 1362 1363 1364 /**************************************************************************** 1365 * IOC Config Pages 1366 ****************************************************************************/ 1367 1368 /*IOC Page 0 */ 1369 1370 typedef struct _MPI2_CONFIG_PAGE_IOC_0 { 1371 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1372 U32 Reserved1; /*0x04 */ 1373 U32 Reserved2; /*0x08 */ 1374 U16 VendorID; /*0x0C */ 1375 U16 DeviceID; /*0x0E */ 1376 U8 RevisionID; /*0x10 */ 1377 U8 Reserved3; /*0x11 */ 1378 U16 Reserved4; /*0x12 */ 1379 U32 ClassCode; /*0x14 */ 1380 U16 SubsystemVendorID; /*0x18 */ 1381 U16 SubsystemID; /*0x1A */ 1382 } MPI2_CONFIG_PAGE_IOC_0, 1383 *PTR_MPI2_CONFIG_PAGE_IOC_0, 1384 Mpi2IOCPage0_t, *pMpi2IOCPage0_t; 1385 1386 #define MPI2_IOCPAGE0_PAGEVERSION (0x02) 1387 1388 1389 /*IOC Page 1 */ 1390 1391 typedef struct _MPI2_CONFIG_PAGE_IOC_1 { 1392 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1393 U32 Flags; /*0x04 */ 1394 U32 CoalescingTimeout; /*0x08 */ 1395 U8 CoalescingDepth; /*0x0C */ 1396 U8 PCISlotNum; /*0x0D */ 1397 U8 PCIBusNum; /*0x0E */ 1398 U8 PCIDomainSegment; /*0x0F */ 1399 U32 Reserved1; /*0x10 */ 1400 U32 Reserved2; /*0x14 */ 1401 } MPI2_CONFIG_PAGE_IOC_1, 1402 *PTR_MPI2_CONFIG_PAGE_IOC_1, 1403 Mpi2IOCPage1_t, *pMpi2IOCPage1_t; 1404 1405 #define MPI2_IOCPAGE1_PAGEVERSION (0x05) 1406 1407 /*defines for IOC Page 1 Flags field */ 1408 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001) 1409 1410 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 1411 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF) 1412 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF) 1413 1414 /*IOC Page 6 */ 1415 1416 typedef struct _MPI2_CONFIG_PAGE_IOC_6 { 1417 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1418 U32 1419 CapabilitiesFlags; /*0x04 */ 1420 U8 MaxDrivesRAID0; /*0x08 */ 1421 U8 MaxDrivesRAID1; /*0x09 */ 1422 U8 1423 MaxDrivesRAID1E; /*0x0A */ 1424 U8 1425 MaxDrivesRAID10; /*0x0B */ 1426 U8 MinDrivesRAID0; /*0x0C */ 1427 U8 MinDrivesRAID1; /*0x0D */ 1428 U8 1429 MinDrivesRAID1E; /*0x0E */ 1430 U8 1431 MinDrivesRAID10; /*0x0F */ 1432 U32 Reserved1; /*0x10 */ 1433 U8 1434 MaxGlobalHotSpares; /*0x14 */ 1435 U8 MaxPhysDisks; /*0x15 */ 1436 U8 MaxVolumes; /*0x16 */ 1437 U8 MaxConfigs; /*0x17 */ 1438 U8 MaxOCEDisks; /*0x18 */ 1439 U8 Reserved2; /*0x19 */ 1440 U16 Reserved3; /*0x1A */ 1441 U32 1442 SupportedStripeSizeMapRAID0; /*0x1C */ 1443 U32 1444 SupportedStripeSizeMapRAID1E; /*0x20 */ 1445 U32 1446 SupportedStripeSizeMapRAID10; /*0x24 */ 1447 U32 Reserved4; /*0x28 */ 1448 U32 Reserved5; /*0x2C */ 1449 U16 1450 DefaultMetadataSize; /*0x30 */ 1451 U16 Reserved6; /*0x32 */ 1452 U16 1453 MaxBadBlockTableEntries; /*0x34 */ 1454 U16 Reserved7; /*0x36 */ 1455 U32 1456 IRNvsramVersion; /*0x38 */ 1457 } MPI2_CONFIG_PAGE_IOC_6, 1458 *PTR_MPI2_CONFIG_PAGE_IOC_6, 1459 Mpi2IOCPage6_t, *pMpi2IOCPage6_t; 1460 1461 #define MPI2_IOCPAGE6_PAGEVERSION (0x05) 1462 1463 /*defines for IOC Page 6 CapabilitiesFlags */ 1464 #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT (0x00000020) 1465 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010) 1466 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008) 1467 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004) 1468 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002) 1469 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 1470 1471 1472 /*IOC Page 7 */ 1473 1474 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4) 1475 1476 typedef struct _MPI2_CONFIG_PAGE_IOC_7 { 1477 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1478 U32 Reserved1; /*0x04 */ 1479 U32 1480 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/*0x08 */ 1481 U16 SASBroadcastPrimitiveMasks; /*0x18 */ 1482 U16 SASNotifyPrimitiveMasks; /*0x1A */ 1483 U32 Reserved3; /*0x1C */ 1484 } MPI2_CONFIG_PAGE_IOC_7, 1485 *PTR_MPI2_CONFIG_PAGE_IOC_7, 1486 Mpi2IOCPage7_t, *pMpi2IOCPage7_t; 1487 1488 #define MPI2_IOCPAGE7_PAGEVERSION (0x02) 1489 1490 1491 /*IOC Page 8 */ 1492 1493 typedef struct _MPI2_CONFIG_PAGE_IOC_8 { 1494 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1495 U8 NumDevsPerEnclosure; /*0x04 */ 1496 U8 Reserved1; /*0x05 */ 1497 U16 Reserved2; /*0x06 */ 1498 U16 MaxPersistentEntries; /*0x08 */ 1499 U16 MaxNumPhysicalMappedIDs; /*0x0A */ 1500 U16 Flags; /*0x0C */ 1501 U16 Reserved3; /*0x0E */ 1502 U16 IRVolumeMappingFlags; /*0x10 */ 1503 U16 Reserved4; /*0x12 */ 1504 U32 Reserved5; /*0x14 */ 1505 } MPI2_CONFIG_PAGE_IOC_8, 1506 *PTR_MPI2_CONFIG_PAGE_IOC_8, 1507 Mpi2IOCPage8_t, *pMpi2IOCPage8_t; 1508 1509 #define MPI2_IOCPAGE8_PAGEVERSION (0x00) 1510 1511 /*defines for IOC Page 8 Flags field */ 1512 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020) 1513 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010) 1514 1515 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E) 1516 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000) 1517 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002) 1518 1519 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001) 1520 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000) 1521 1522 /*defines for IOC Page 8 IRVolumeMappingFlags */ 1523 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003) 1524 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000) 1525 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001) 1526 1527 1528 /**************************************************************************** 1529 * BIOS Config Pages 1530 ****************************************************************************/ 1531 1532 /*BIOS Page 1 */ 1533 1534 typedef struct _MPI2_CONFIG_PAGE_BIOS_1 { 1535 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1536 U32 BiosOptions; /*0x04 */ 1537 U32 IOCSettings; /*0x08 */ 1538 U8 SSUTimeout; /*0x0C */ 1539 U8 MaxEnclosureLevel; /*0x0D */ 1540 U16 Reserved2; /*0x0E */ 1541 U32 DeviceSettings; /*0x10 */ 1542 U16 NumberOfDevices; /*0x14 */ 1543 U16 UEFIVersion; /*0x16 */ 1544 U16 IOTimeoutBlockDevicesNonRM; /*0x18 */ 1545 U16 IOTimeoutSequential; /*0x1A */ 1546 U16 IOTimeoutOther; /*0x1C */ 1547 U16 IOTimeoutBlockDevicesRM; /*0x1E */ 1548 } MPI2_CONFIG_PAGE_BIOS_1, 1549 *PTR_MPI2_CONFIG_PAGE_BIOS_1, 1550 Mpi2BiosPage1_t, *pMpi2BiosPage1_t; 1551 1552 #define MPI2_BIOSPAGE1_PAGEVERSION (0x07) 1553 1554 /*values for BIOS Page 1 BiosOptions field */ 1555 #define MPI2_BIOSPAGE1_OPTIONS_BOOT_LIST_ADD_ALT_BOOT_DEVICE (0x00008000) 1556 #define MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG (0x00004000) 1557 1558 #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800) 1559 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL (0x00000000) 1560 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE (0x00000800) 1561 #define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID (0x00001000) 1562 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PSENS (0x00001800) 1563 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ESPHY (0x00002000) 1564 1565 #define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS (0x00000400) 1566 1567 #define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD (0x00000300) 1568 #define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD (0x00000000) 1569 #define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD (0x00000100) 1570 #define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD (0x00000200) 1571 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD (0x00000300) 1572 1573 #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0) 1574 #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000) 1575 1576 #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006) 1577 #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000) 1578 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002) 1579 #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004) 1580 1581 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1582 1583 /*values for BIOS Page 1 IOCSettings field */ 1584 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1585 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1586 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1587 1588 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1589 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1590 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1591 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1592 1593 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1594 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1595 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1596 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1597 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1598 1599 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1600 1601 /*values for BIOS Page 1 DeviceSettings field */ 1602 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 1603 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1604 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1605 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1606 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1607 1608 /*defines for BIOS Page 1 UEFIVersion field */ 1609 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK (0xFF00) 1610 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT (8) 1611 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK (0x00FF) 1612 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT (0) 1613 1614 1615 1616 /*BIOS Page 2 */ 1617 1618 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER { 1619 U32 Reserved1; /*0x00 */ 1620 U32 Reserved2; /*0x04 */ 1621 U32 Reserved3; /*0x08 */ 1622 U32 Reserved4; /*0x0C */ 1623 U32 Reserved5; /*0x10 */ 1624 U32 Reserved6; /*0x14 */ 1625 } MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1626 *PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1627 Mpi2BootDeviceAdapterOrder_t, 1628 *pMpi2BootDeviceAdapterOrder_t; 1629 1630 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID { 1631 U64 SASAddress; /*0x00 */ 1632 U8 LUN[8]; /*0x08 */ 1633 U32 Reserved1; /*0x10 */ 1634 U32 Reserved2; /*0x14 */ 1635 } MPI2_BOOT_DEVICE_SAS_WWID, 1636 *PTR_MPI2_BOOT_DEVICE_SAS_WWID, 1637 Mpi2BootDeviceSasWwid_t, 1638 *pMpi2BootDeviceSasWwid_t; 1639 1640 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT { 1641 U64 EnclosureLogicalID; /*0x00 */ 1642 U32 Reserved1; /*0x08 */ 1643 U32 Reserved2; /*0x0C */ 1644 U16 SlotNumber; /*0x10 */ 1645 U16 Reserved3; /*0x12 */ 1646 U32 Reserved4; /*0x14 */ 1647 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1648 *PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1649 Mpi2BootDeviceEnclosureSlot_t, 1650 *pMpi2BootDeviceEnclosureSlot_t; 1651 1652 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME { 1653 U64 DeviceName; /*0x00 */ 1654 U8 LUN[8]; /*0x08 */ 1655 U32 Reserved1; /*0x10 */ 1656 U32 Reserved2; /*0x14 */ 1657 } MPI2_BOOT_DEVICE_DEVICE_NAME, 1658 *PTR_MPI2_BOOT_DEVICE_DEVICE_NAME, 1659 Mpi2BootDeviceDeviceName_t, 1660 *pMpi2BootDeviceDeviceName_t; 1661 1662 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE { 1663 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1664 MPI2_BOOT_DEVICE_SAS_WWID SasWwid; 1665 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1666 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName; 1667 } MPI2_BIOSPAGE2_BOOT_DEVICE, 1668 *PTR_MPI2_BIOSPAGE2_BOOT_DEVICE, 1669 Mpi2BiosPage2BootDevice_t, 1670 *pMpi2BiosPage2BootDevice_t; 1671 1672 typedef struct _MPI2_CONFIG_PAGE_BIOS_2 { 1673 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1674 U32 Reserved1; /*0x04 */ 1675 U32 Reserved2; /*0x08 */ 1676 U32 Reserved3; /*0x0C */ 1677 U32 Reserved4; /*0x10 */ 1678 U32 Reserved5; /*0x14 */ 1679 U32 Reserved6; /*0x18 */ 1680 U8 ReqBootDeviceForm; /*0x1C */ 1681 U8 Reserved7; /*0x1D */ 1682 U16 Reserved8; /*0x1E */ 1683 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /*0x20 */ 1684 U8 ReqAltBootDeviceForm; /*0x38 */ 1685 U8 Reserved9; /*0x39 */ 1686 U16 Reserved10; /*0x3A */ 1687 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /*0x3C */ 1688 U8 CurrentBootDeviceForm; /*0x58 */ 1689 U8 Reserved11; /*0x59 */ 1690 U16 Reserved12; /*0x5A */ 1691 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /*0x58 */ 1692 } MPI2_CONFIG_PAGE_BIOS_2, *PTR_MPI2_CONFIG_PAGE_BIOS_2, 1693 Mpi2BiosPage2_t, *pMpi2BiosPage2_t; 1694 1695 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04) 1696 1697 /*values for BIOS Page 2 BootDeviceForm fields */ 1698 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F) 1699 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00) 1700 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05) 1701 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1702 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07) 1703 1704 1705 /*BIOS Page 3 */ 1706 1707 #define MPI2_BIOSPAGE3_NUM_ADAPTER (4) 1708 1709 typedef struct _MPI2_ADAPTER_INFO { 1710 U8 PciBusNumber; /*0x00 */ 1711 U8 PciDeviceAndFunctionNumber; /*0x01 */ 1712 U16 AdapterFlags; /*0x02 */ 1713 } MPI2_ADAPTER_INFO, *PTR_MPI2_ADAPTER_INFO, 1714 Mpi2AdapterInfo_t, *pMpi2AdapterInfo_t; 1715 1716 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 1717 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 1718 1719 typedef struct _MPI2_ADAPTER_ORDER_AUX { 1720 U64 WWID; /* 0x00 */ 1721 U32 Reserved1; /* 0x08 */ 1722 U32 Reserved2; /* 0x0C */ 1723 } MPI2_ADAPTER_ORDER_AUX, *PTR_MPI2_ADAPTER_ORDER_AUX, 1724 Mpi2AdapterOrderAux_t, *pMpi2AdapterOrderAux_t; 1725 1726 1727 typedef struct _MPI2_CONFIG_PAGE_BIOS_3 { 1728 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1729 U32 GlobalFlags; /*0x04 */ 1730 U32 BiosVersion; /*0x08 */ 1731 MPI2_ADAPTER_INFO AdapterOrder[MPI2_BIOSPAGE3_NUM_ADAPTER]; 1732 U32 Reserved1; /*0x1C */ 1733 MPI2_ADAPTER_ORDER_AUX AdapterOrderAux[MPI2_BIOSPAGE3_NUM_ADAPTER]; 1734 } MPI2_CONFIG_PAGE_BIOS_3, 1735 *PTR_MPI2_CONFIG_PAGE_BIOS_3, 1736 Mpi2BiosPage3_t, *pMpi2BiosPage3_t; 1737 1738 #define MPI2_BIOSPAGE3_PAGEVERSION (0x01) 1739 1740 /*values for BIOS Page 3 GlobalFlags */ 1741 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) 1742 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004) 1743 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010) 1744 1745 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 1746 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 1747 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020) 1748 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 1749 1750 1751 /*BIOS Page 4 */ 1752 1753 /* 1754 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1755 *one and check the value returned for NumPhys at runtime. 1756 */ 1757 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES 1758 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1) 1759 #endif 1760 1761 typedef struct _MPI2_BIOS4_ENTRY { 1762 U64 ReassignmentWWID; /*0x00 */ 1763 U64 ReassignmentDeviceName; /*0x08 */ 1764 } MPI2_BIOS4_ENTRY, *PTR_MPI2_BIOS4_ENTRY, 1765 Mpi2MBios4Entry_t, *pMpi2Bios4Entry_t; 1766 1767 typedef struct _MPI2_CONFIG_PAGE_BIOS_4 { 1768 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1769 U8 NumPhys; /*0x04 */ 1770 U8 Reserved1; /*0x05 */ 1771 U16 Reserved2; /*0x06 */ 1772 MPI2_BIOS4_ENTRY 1773 Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /*0x08 */ 1774 } MPI2_CONFIG_PAGE_BIOS_4, *PTR_MPI2_CONFIG_PAGE_BIOS_4, 1775 Mpi2BiosPage4_t, *pMpi2BiosPage4_t; 1776 1777 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01) 1778 1779 1780 /**************************************************************************** 1781 * RAID Volume Config Pages 1782 ****************************************************************************/ 1783 1784 /*RAID Volume Page 0 */ 1785 1786 typedef struct _MPI2_RAIDVOL0_PHYS_DISK { 1787 U8 RAIDSetNum; /*0x00 */ 1788 U8 PhysDiskMap; /*0x01 */ 1789 U8 PhysDiskNum; /*0x02 */ 1790 U8 Reserved; /*0x03 */ 1791 } MPI2_RAIDVOL0_PHYS_DISK, *PTR_MPI2_RAIDVOL0_PHYS_DISK, 1792 Mpi2RaidVol0PhysDisk_t, *pMpi2RaidVol0PhysDisk_t; 1793 1794 /*defines for the PhysDiskMap field */ 1795 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1796 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1797 1798 typedef struct _MPI2_RAIDVOL0_SETTINGS { 1799 U16 Settings; /*0x00 */ 1800 U8 HotSparePool; /*0x01 */ 1801 U8 Reserved; /*0x02 */ 1802 } MPI2_RAIDVOL0_SETTINGS, *PTR_MPI2_RAIDVOL0_SETTINGS, 1803 Mpi2RaidVol0Settings_t, 1804 *pMpi2RaidVol0Settings_t; 1805 1806 /*RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1807 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01) 1808 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02) 1809 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04) 1810 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08) 1811 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10) 1812 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20) 1813 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40) 1814 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80) 1815 1816 /*RAID Volume Page 0 VolumeSettings defines */ 1817 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008) 1818 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004) 1819 1820 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003) 1821 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000) 1822 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001) 1823 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002) 1824 1825 /* 1826 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1827 *one and check the value returned for NumPhysDisks at runtime. 1828 */ 1829 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX 1830 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 1831 #endif 1832 1833 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 { 1834 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1835 U16 DevHandle; /*0x04 */ 1836 U8 VolumeState; /*0x06 */ 1837 U8 VolumeType; /*0x07 */ 1838 U32 VolumeStatusFlags; /*0x08 */ 1839 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /*0x0C */ 1840 U64 MaxLBA; /*0x10 */ 1841 U32 StripeSize; /*0x18 */ 1842 U16 BlockSize; /*0x1C */ 1843 U16 Reserved1; /*0x1E */ 1844 U8 SupportedPhysDisks;/*0x20 */ 1845 U8 ResyncRate; /*0x21 */ 1846 U16 DataScrubDuration; /*0x22 */ 1847 U8 NumPhysDisks; /*0x24 */ 1848 U8 Reserved2; /*0x25 */ 1849 U8 Reserved3; /*0x26 */ 1850 U8 InactiveStatus; /*0x27 */ 1851 MPI2_RAIDVOL0_PHYS_DISK 1852 PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /*0x28 */ 1853 } MPI2_CONFIG_PAGE_RAID_VOL_0, 1854 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_0, 1855 Mpi2RaidVolPage0_t, *pMpi2RaidVolPage0_t; 1856 1857 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A) 1858 1859 /*values for RAID VolumeState */ 1860 #define MPI2_RAID_VOL_STATE_MISSING (0x00) 1861 #define MPI2_RAID_VOL_STATE_FAILED (0x01) 1862 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02) 1863 #define MPI2_RAID_VOL_STATE_ONLINE (0x03) 1864 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04) 1865 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05) 1866 1867 /*values for RAID VolumeType */ 1868 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00) 1869 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01) 1870 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02) 1871 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05) 1872 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF) 1873 1874 /*values for RAID Volume Page 0 VolumeStatusFlags field */ 1875 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000) 1876 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000) 1877 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000) 1878 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000) 1879 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000) 1880 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000) 1881 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000) 1882 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000) 1883 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000) 1884 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000) 1885 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080) 1886 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040) 1887 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020) 1888 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000) 1889 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010) 1890 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008) 1891 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004) 1892 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002) 1893 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001) 1894 1895 /*values for RAID Volume Page 0 SupportedPhysDisks field */ 1896 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08) 1897 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04) 1898 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02) 1899 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01) 1900 1901 /*values for RAID Volume Page 0 InactiveStatus field */ 1902 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 1903 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 1904 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 1905 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 1906 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 1907 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 1908 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 1909 1910 1911 /*RAID Volume Page 1 */ 1912 1913 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 { 1914 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1915 U16 DevHandle; /*0x04 */ 1916 U16 Reserved0; /*0x06 */ 1917 U8 GUID[24]; /*0x08 */ 1918 U8 Name[16]; /*0x20 */ 1919 U64 WWID; /*0x30 */ 1920 U32 Reserved1; /*0x38 */ 1921 U32 Reserved2; /*0x3C */ 1922 } MPI2_CONFIG_PAGE_RAID_VOL_1, 1923 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_1, 1924 Mpi2RaidVolPage1_t, *pMpi2RaidVolPage1_t; 1925 1926 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03) 1927 1928 1929 /**************************************************************************** 1930 * RAID Physical Disk Config Pages 1931 ****************************************************************************/ 1932 1933 /*RAID Physical Disk Page 0 */ 1934 1935 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS { 1936 U16 Reserved1; /*0x00 */ 1937 U8 HotSparePool; /*0x02 */ 1938 U8 Reserved2; /*0x03 */ 1939 } MPI2_RAIDPHYSDISK0_SETTINGS, 1940 *PTR_MPI2_RAIDPHYSDISK0_SETTINGS, 1941 Mpi2RaidPhysDisk0Settings_t, 1942 *pMpi2RaidPhysDisk0Settings_t; 1943 1944 /*use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */ 1945 1946 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA { 1947 U8 VendorID[8]; /*0x00 */ 1948 U8 ProductID[16]; /*0x08 */ 1949 U8 ProductRevLevel[4]; /*0x18 */ 1950 U8 SerialNum[32]; /*0x1C */ 1951 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1952 *PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1953 Mpi2RaidPhysDisk0InquiryData_t, 1954 *pMpi2RaidPhysDisk0InquiryData_t; 1955 1956 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 { 1957 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1958 U16 DevHandle; /*0x04 */ 1959 U8 Reserved1; /*0x06 */ 1960 U8 PhysDiskNum; /*0x07 */ 1961 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /*0x08 */ 1962 U32 Reserved2; /*0x0C */ 1963 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /*0x10 */ 1964 U32 Reserved3; /*0x4C */ 1965 U8 PhysDiskState; /*0x50 */ 1966 U8 OfflineReason; /*0x51 */ 1967 U8 IncompatibleReason; /*0x52 */ 1968 U8 PhysDiskAttributes; /*0x53 */ 1969 U32 PhysDiskStatusFlags;/*0x54 */ 1970 U64 DeviceMaxLBA; /*0x58 */ 1971 U64 HostMaxLBA; /*0x60 */ 1972 U64 CoercedMaxLBA; /*0x68 */ 1973 U16 BlockSize; /*0x70 */ 1974 U16 Reserved5; /*0x72 */ 1975 U32 Reserved6; /*0x74 */ 1976 } MPI2_CONFIG_PAGE_RD_PDISK_0, 1977 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_0, 1978 Mpi2RaidPhysDiskPage0_t, 1979 *pMpi2RaidPhysDiskPage0_t; 1980 1981 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05) 1982 1983 /*PhysDiskState defines */ 1984 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00) 1985 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01) 1986 #define MPI2_RAID_PD_STATE_OFFLINE (0x02) 1987 #define MPI2_RAID_PD_STATE_ONLINE (0x03) 1988 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04) 1989 #define MPI2_RAID_PD_STATE_DEGRADED (0x05) 1990 #define MPI2_RAID_PD_STATE_REBUILDING (0x06) 1991 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07) 1992 1993 /*OfflineReason defines */ 1994 #define MPI2_PHYSDISK0_ONLINE (0x00) 1995 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01) 1996 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03) 1997 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04) 1998 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05) 1999 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06) 2000 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF) 2001 2002 /*IncompatibleReason defines */ 2003 #define MPI2_PHYSDISK0_COMPATIBLE (0x00) 2004 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01) 2005 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02) 2006 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03) 2007 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04) 2008 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05) 2009 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06) 2010 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF) 2011 2012 /*PhysDiskAttributes defines */ 2013 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C) 2014 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08) 2015 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04) 2016 2017 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03) 2018 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02) 2019 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01) 2020 2021 /*PhysDiskStatusFlags defines */ 2022 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040) 2023 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020) 2024 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010) 2025 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000) 2026 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008) 2027 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004) 2028 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002) 2029 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001) 2030 2031 2032 /*RAID Physical Disk Page 1 */ 2033 2034 /* 2035 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2036 *one and check the value returned for NumPhysDiskPaths at runtime. 2037 */ 2038 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX 2039 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1) 2040 #endif 2041 2042 typedef struct _MPI2_RAIDPHYSDISK1_PATH { 2043 U16 DevHandle; /*0x00 */ 2044 U16 Reserved1; /*0x02 */ 2045 U64 WWID; /*0x04 */ 2046 U64 OwnerWWID; /*0x0C */ 2047 U8 OwnerIdentifier; /*0x14 */ 2048 U8 Reserved2; /*0x15 */ 2049 U16 Flags; /*0x16 */ 2050 } MPI2_RAIDPHYSDISK1_PATH, *PTR_MPI2_RAIDPHYSDISK1_PATH, 2051 Mpi2RaidPhysDisk1Path_t, 2052 *pMpi2RaidPhysDisk1Path_t; 2053 2054 /*RAID Physical Disk Page 1 Physical Disk Path Flags field defines */ 2055 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004) 2056 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 2057 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 2058 2059 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 { 2060 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 2061 U8 NumPhysDiskPaths; /*0x04 */ 2062 U8 PhysDiskNum; /*0x05 */ 2063 U16 Reserved1; /*0x06 */ 2064 U32 Reserved2; /*0x08 */ 2065 MPI2_RAIDPHYSDISK1_PATH 2066 PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/*0x0C */ 2067 } MPI2_CONFIG_PAGE_RD_PDISK_1, 2068 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_1, 2069 Mpi2RaidPhysDiskPage1_t, 2070 *pMpi2RaidPhysDiskPage1_t; 2071 2072 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02) 2073 2074 2075 /**************************************************************************** 2076 * values for fields used by several types of SAS Config Pages 2077 ****************************************************************************/ 2078 2079 /*values for NegotiatedLinkRates fields */ 2080 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0) 2081 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4) 2082 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 2083 /*link rates used for Negotiated Physical and Logical Link Rate */ 2084 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 2085 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 2086 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 2087 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 2088 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 2089 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 2090 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 2091 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08) 2092 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09) 2093 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A) 2094 #define MPI25_SAS_NEG_LINK_RATE_12_0 (0x0B) 2095 #define MPI26_SAS_NEG_LINK_RATE_22_5 (0x0C) 2096 2097 2098 /*values for AttachedPhyInfo fields */ 2099 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 2100 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 2101 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 2102 2103 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F) 2104 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 2105 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 2106 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 2107 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 2108 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 2109 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 2110 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 2111 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 2112 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 2113 2114 2115 /*values for PhyInfo fields */ 2116 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000) 2117 2118 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 2119 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27) 2120 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000) 2121 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000) 2122 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000) 2123 2124 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000) 2125 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000) 2126 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000) 2127 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 2128 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000) 2129 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 2130 2131 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000) 2132 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 2133 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 2134 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 2135 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 2136 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 2137 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 2138 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 2139 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 2140 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 2141 2142 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000) 2143 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 2144 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 2145 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 2146 2147 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 2148 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 2149 2150 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 2151 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000) 2152 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 2153 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020) 2154 2155 2156 /*values for SAS ProgrammedLinkRate fields */ 2157 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0) 2158 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 2159 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80) 2160 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90) 2161 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0) 2162 #define MPI25_SAS_PRATE_MAX_RATE_12_0 (0xB0) 2163 #define MPI26_SAS_PRATE_MAX_RATE_22_5 (0xC0) 2164 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F) 2165 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 2166 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08) 2167 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09) 2168 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A) 2169 #define MPI25_SAS_PRATE_MIN_RATE_12_0 (0x0B) 2170 #define MPI26_SAS_PRATE_MIN_RATE_22_5 (0x0C) 2171 2172 2173 /*values for SAS HwLinkRate fields */ 2174 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0) 2175 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80) 2176 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90) 2177 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0) 2178 #define MPI25_SAS_HWRATE_MAX_RATE_12_0 (0xB0) 2179 #define MPI26_SAS_HWRATE_MAX_RATE_22_5 (0xC0) 2180 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F) 2181 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08) 2182 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09) 2183 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A) 2184 #define MPI25_SAS_HWRATE_MIN_RATE_12_0 (0x0B) 2185 #define MPI26_SAS_HWRATE_MIN_RATE_22_5 (0x0C) 2186 2187 2188 2189 /**************************************************************************** 2190 * SAS IO Unit Config Pages 2191 ****************************************************************************/ 2192 2193 /*SAS IO Unit Page 0 */ 2194 2195 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA { 2196 U8 Port; /*0x00 */ 2197 U8 PortFlags; /*0x01 */ 2198 U8 PhyFlags; /*0x02 */ 2199 U8 NegotiatedLinkRate; /*0x03 */ 2200 U32 ControllerPhyDeviceInfo;/*0x04 */ 2201 U16 AttachedDevHandle; /*0x08 */ 2202 U16 ControllerDevHandle; /*0x0A */ 2203 U32 DiscoveryStatus; /*0x0C */ 2204 U32 Reserved; /*0x10 */ 2205 } MPI2_SAS_IO_UNIT0_PHY_DATA, 2206 *PTR_MPI2_SAS_IO_UNIT0_PHY_DATA, 2207 Mpi2SasIOUnit0PhyData_t, 2208 *pMpi2SasIOUnit0PhyData_t; 2209 2210 /* 2211 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2212 *one and check the value returned for NumPhys at runtime. 2213 */ 2214 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX 2215 #define MPI2_SAS_IOUNIT0_PHY_MAX (1) 2216 #endif 2217 2218 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 { 2219 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2220 U32 Reserved1;/*0x08 */ 2221 U8 NumPhys; /*0x0C */ 2222 U8 Reserved2;/*0x0D */ 2223 U16 Reserved3;/*0x0E */ 2224 MPI2_SAS_IO_UNIT0_PHY_DATA 2225 PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /*0x10 */ 2226 } MPI2_CONFIG_PAGE_SASIOUNIT_0, 2227 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0, 2228 Mpi2SasIOUnitPage0_t, *pMpi2SasIOUnitPage0_t; 2229 2230 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05) 2231 2232 /*values for SAS IO Unit Page 0 PortFlags */ 2233 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08) 2234 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) 2235 2236 /*values for SAS IO Unit Page 0 PhyFlags */ 2237 #define MPI2_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2238 #define MPI2_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2239 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) 2240 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 2241 2242 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2243 2244 /*see mpi2_sas.h for values for 2245 *SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 2246 2247 /*values for SAS IO Unit Page 0 DiscoveryStatus */ 2248 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2249 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2250 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000) 2251 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2252 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2253 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2254 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2255 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 2256 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2257 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 2258 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400) 2259 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 2260 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 2261 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 2262 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 2263 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2264 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010) 2265 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 2266 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2267 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001) 2268 2269 2270 /*SAS IO Unit Page 1 */ 2271 2272 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA { 2273 U8 Port; /*0x00 */ 2274 U8 PortFlags; /*0x01 */ 2275 U8 PhyFlags; /*0x02 */ 2276 U8 MaxMinLinkRate; /*0x03 */ 2277 U32 ControllerPhyDeviceInfo; /*0x04 */ 2278 U16 MaxTargetPortConnectTime; /*0x08 */ 2279 U16 Reserved1; /*0x0A */ 2280 } MPI2_SAS_IO_UNIT1_PHY_DATA, 2281 *PTR_MPI2_SAS_IO_UNIT1_PHY_DATA, 2282 Mpi2SasIOUnit1PhyData_t, 2283 *pMpi2SasIOUnit1PhyData_t; 2284 2285 /* 2286 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2287 *one and check the value returned for NumPhys at runtime. 2288 */ 2289 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX 2290 #define MPI2_SAS_IOUNIT1_PHY_MAX (1) 2291 #endif 2292 2293 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 { 2294 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2295 U16 2296 ControlFlags; /*0x08 */ 2297 U16 2298 SASNarrowMaxQueueDepth; /*0x0A */ 2299 U16 2300 AdditionalControlFlags; /*0x0C */ 2301 U16 2302 SASWideMaxQueueDepth; /*0x0E */ 2303 U8 2304 NumPhys; /*0x10 */ 2305 U8 2306 SATAMaxQDepth; /*0x11 */ 2307 U8 2308 ReportDeviceMissingDelay; /*0x12 */ 2309 U8 2310 IODeviceMissingDelay; /*0x13 */ 2311 MPI2_SAS_IO_UNIT1_PHY_DATA 2312 PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /*0x14 */ 2313 } MPI2_CONFIG_PAGE_SASIOUNIT_1, 2314 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1, 2315 Mpi2SasIOUnitPage1_t, *pMpi2SasIOUnitPage1_t; 2316 2317 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09) 2318 2319 /*values for SAS IO Unit Page 1 ControlFlags */ 2320 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 2321 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 2322 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) 2323 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 2324 2325 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 2326 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 2327 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0) 2328 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1) 2329 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2) 2330 2331 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 2332 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 2333 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 2334 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 2335 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 2336 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 2337 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 2338 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) 2339 2340 /*values for SAS IO Unit Page 1 AdditionalControlFlags */ 2341 #define MPI2_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100) 2342 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 2343 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 2344 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 2345 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 2346 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 2347 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 2348 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 2349 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 2350 2351 /*defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 2352 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 2353 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 2354 2355 /*values for SAS IO Unit Page 1 PortFlags */ 2356 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2357 2358 /*values for SAS IO Unit Page 1 PhyFlags */ 2359 #define MPI2_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2360 #define MPI2_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2361 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) 2362 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 2363 2364 /*values for SAS IO Unit Page 1 MaxMinLinkRate */ 2365 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) 2366 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) 2367 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) 2368 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) 2369 #define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0) 2370 #define MPI26_SASIOUNIT1_MAX_RATE_22_5 (0xC0) 2371 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) 2372 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) 2373 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) 2374 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) 2375 #define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B) 2376 #define MPI26_SASIOUNIT1_MIN_RATE_22_5 (0x0C) 2377 2378 /*see mpi2_sas.h for values for 2379 *SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 2380 2381 2382 /*SAS IO Unit Page 4 (for MPI v2.5 and earlier) */ 2383 2384 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP { 2385 U8 MaxTargetSpinup; /*0x00 */ 2386 U8 SpinupDelay; /*0x01 */ 2387 U8 SpinupFlags; /*0x02 */ 2388 U8 Reserved1; /*0x03 */ 2389 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, 2390 *PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP, 2391 Mpi2SasIOUnit4SpinupGroup_t, 2392 *pMpi2SasIOUnit4SpinupGroup_t; 2393 /*defines for SAS IO Unit Page 4 SpinupFlags */ 2394 #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01) 2395 2396 2397 /* 2398 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2399 *one and check the value returned for NumPhys at runtime. 2400 */ 2401 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX 2402 #define MPI2_SAS_IOUNIT4_PHY_MAX (4) 2403 #endif 2404 2405 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 { 2406 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header;/*0x00 */ 2407 MPI2_SAS_IOUNIT4_SPINUP_GROUP 2408 SpinupGroupParameters[4]; /*0x08 */ 2409 U32 2410 Reserved1; /*0x18 */ 2411 U32 2412 Reserved2; /*0x1C */ 2413 U32 2414 Reserved3; /*0x20 */ 2415 U8 2416 BootDeviceWaitTime; /*0x24 */ 2417 U8 2418 SATADeviceWaitTime; /*0x25 */ 2419 U16 2420 Reserved5; /*0x26 */ 2421 U8 2422 NumPhys; /*0x28 */ 2423 U8 2424 PEInitialSpinupDelay; /*0x29 */ 2425 U8 2426 PEReplyDelay; /*0x2A */ 2427 U8 2428 Flags; /*0x2B */ 2429 U8 2430 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /*0x2C */ 2431 } MPI2_CONFIG_PAGE_SASIOUNIT_4, 2432 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4, 2433 Mpi2SasIOUnitPage4_t, *pMpi2SasIOUnitPage4_t; 2434 2435 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02) 2436 2437 /*defines for Flags field */ 2438 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01) 2439 2440 /*defines for PHY field */ 2441 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03) 2442 2443 2444 /*SAS IO Unit Page 5 */ 2445 2446 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS { 2447 U8 ControlFlags; /*0x00 */ 2448 U8 PortWidthModGroup; /*0x01 */ 2449 U16 InactivityTimerExponent; /*0x02 */ 2450 U8 SATAPartialTimeout; /*0x04 */ 2451 U8 Reserved2; /*0x05 */ 2452 U8 SATASlumberTimeout; /*0x06 */ 2453 U8 Reserved3; /*0x07 */ 2454 U8 SASPartialTimeout; /*0x08 */ 2455 U8 Reserved4; /*0x09 */ 2456 U8 SASSlumberTimeout; /*0x0A */ 2457 U8 Reserved5; /*0x0B */ 2458 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2459 *PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2460 Mpi2SasIOUnit5PhyPmSettings_t, 2461 *pMpi2SasIOUnit5PhyPmSettings_t; 2462 2463 /*defines for ControlFlags field */ 2464 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08) 2465 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04) 2466 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02) 2467 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01) 2468 2469 /*defines for PortWidthModeGroup field */ 2470 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF) 2471 2472 /*defines for InactivityTimerExponent field */ 2473 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000) 2474 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12) 2475 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700) 2476 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8) 2477 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070) 2478 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4) 2479 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007) 2480 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0) 2481 2482 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7) 2483 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6) 2484 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5) 2485 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4) 2486 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3) 2487 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2) 2488 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1) 2489 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0) 2490 2491 /* 2492 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2493 *one and check the value returned for NumPhys at runtime. 2494 */ 2495 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX 2496 #define MPI2_SAS_IOUNIT5_PHY_MAX (1) 2497 #endif 2498 2499 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 { 2500 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2501 U8 NumPhys; /*0x08 */ 2502 U8 Reserved1;/*0x09 */ 2503 U16 Reserved2;/*0x0A */ 2504 U32 Reserved3;/*0x0C */ 2505 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS 2506 SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX];/*0x10 */ 2507 } MPI2_CONFIG_PAGE_SASIOUNIT_5, 2508 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5, 2509 Mpi2SasIOUnitPage5_t, *pMpi2SasIOUnitPage5_t; 2510 2511 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01) 2512 2513 2514 /*SAS IO Unit Page 6 */ 2515 2516 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS { 2517 U8 CurrentStatus; /*0x00 */ 2518 U8 CurrentModulation; /*0x01 */ 2519 U8 CurrentUtilization; /*0x02 */ 2520 U8 Reserved1; /*0x03 */ 2521 U32 Reserved2; /*0x04 */ 2522 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2523 *PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2524 Mpi2SasIOUnit6PortWidthModGroupStatus_t, 2525 *pMpi2SasIOUnit6PortWidthModGroupStatus_t; 2526 2527 /*defines for CurrentStatus field */ 2528 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00) 2529 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01) 2530 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02) 2531 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03) 2532 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04) 2533 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05) 2534 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06) 2535 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07) 2536 2537 /*defines for CurrentModulation field */ 2538 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00) 2539 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01) 2540 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02) 2541 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03) 2542 2543 /* 2544 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2545 *one and check the value returned for NumGroups at runtime. 2546 */ 2547 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX 2548 #define MPI2_SAS_IOUNIT6_GROUP_MAX (1) 2549 #endif 2550 2551 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 { 2552 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2553 U32 Reserved1; /*0x08 */ 2554 U32 Reserved2; /*0x0C */ 2555 U8 NumGroups; /*0x10 */ 2556 U8 Reserved3; /*0x11 */ 2557 U16 Reserved4; /*0x12 */ 2558 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 2559 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /*0x14 */ 2560 } MPI2_CONFIG_PAGE_SASIOUNIT_6, 2561 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6, 2562 Mpi2SasIOUnitPage6_t, *pMpi2SasIOUnitPage6_t; 2563 2564 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00) 2565 2566 2567 /*SAS IO Unit Page 7 */ 2568 2569 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS { 2570 U8 Flags; /*0x00 */ 2571 U8 Reserved1; /*0x01 */ 2572 U16 Reserved2; /*0x02 */ 2573 U8 Threshold75Pct; /*0x04 */ 2574 U8 Threshold50Pct; /*0x05 */ 2575 U8 Threshold25Pct; /*0x06 */ 2576 U8 Reserved3; /*0x07 */ 2577 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2578 *PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2579 Mpi2SasIOUnit7PortWidthModGroupSettings_t, 2580 *pMpi2SasIOUnit7PortWidthModGroupSettings_t; 2581 2582 /*defines for Flags field */ 2583 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01) 2584 2585 2586 /* 2587 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2588 *one and check the value returned for NumGroups at runtime. 2589 */ 2590 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX 2591 #define MPI2_SAS_IOUNIT7_GROUP_MAX (1) 2592 #endif 2593 2594 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 { 2595 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2596 U8 SamplingInterval; /*0x08 */ 2597 U8 WindowLength; /*0x09 */ 2598 U16 Reserved1; /*0x0A */ 2599 U32 Reserved2; /*0x0C */ 2600 U32 Reserved3; /*0x10 */ 2601 U8 NumGroups; /*0x14 */ 2602 U8 Reserved4; /*0x15 */ 2603 U16 Reserved5; /*0x16 */ 2604 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2605 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX];/*0x18 */ 2606 } MPI2_CONFIG_PAGE_SASIOUNIT_7, 2607 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7, 2608 Mpi2SasIOUnitPage7_t, *pMpi2SasIOUnitPage7_t; 2609 2610 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00) 2611 2612 2613 /*SAS IO Unit Page 8 */ 2614 2615 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 { 2616 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2617 Header; /*0x00 */ 2618 U32 2619 Reserved1; /*0x08 */ 2620 U32 2621 PowerManagementCapabilities; /*0x0C */ 2622 U8 2623 TxRxSleepStatus; /*0x10 */ 2624 U8 2625 Reserved2; /*0x11 */ 2626 U16 2627 Reserved3; /*0x12 */ 2628 } MPI2_CONFIG_PAGE_SASIOUNIT_8, 2629 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8, 2630 Mpi2SasIOUnitPage8_t, *pMpi2SasIOUnitPage8_t; 2631 2632 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00) 2633 2634 /*defines for PowerManagementCapabilities field */ 2635 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000) 2636 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800) 2637 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400) 2638 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200) 2639 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100) 2640 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010) 2641 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008) 2642 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004) 2643 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002) 2644 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001) 2645 2646 /*defines for TxRxSleepStatus field */ 2647 #define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED (0x00) 2648 #define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED (0x01) 2649 #define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE (0x02) 2650 #define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN (0x03) 2651 2652 2653 2654 /*SAS IO Unit Page 16 */ 2655 2656 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 { 2657 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2658 Header; /*0x00 */ 2659 U64 2660 TimeStamp; /*0x08 */ 2661 U32 2662 Reserved1; /*0x10 */ 2663 U32 2664 Reserved2; /*0x14 */ 2665 U32 2666 FastPathPendedRequests; /*0x18 */ 2667 U32 2668 FastPathUnPendedRequests; /*0x1C */ 2669 U32 2670 FastPathHostRequestStarts; /*0x20 */ 2671 U32 2672 FastPathFirmwareRequestStarts; /*0x24 */ 2673 U32 2674 FastPathHostCompletions; /*0x28 */ 2675 U32 2676 FastPathFirmwareCompletions; /*0x2C */ 2677 U32 2678 NonFastPathRequestStarts; /*0x30 */ 2679 U32 2680 NonFastPathHostCompletions; /*0x30 */ 2681 } MPI2_CONFIG_PAGE_SASIOUNIT16, 2682 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT16, 2683 Mpi2SasIOUnitPage16_t, *pMpi2SasIOUnitPage16_t; 2684 2685 #define MPI2_SASIOUNITPAGE16_PAGEVERSION (0x00) 2686 2687 2688 /**************************************************************************** 2689 * SAS Expander Config Pages 2690 ****************************************************************************/ 2691 2692 /*SAS Expander Page 0 */ 2693 2694 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 { 2695 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2696 Header; /*0x00 */ 2697 U8 2698 PhysicalPort; /*0x08 */ 2699 U8 2700 ReportGenLength; /*0x09 */ 2701 U16 2702 EnclosureHandle; /*0x0A */ 2703 U64 2704 SASAddress; /*0x0C */ 2705 U32 2706 DiscoveryStatus; /*0x14 */ 2707 U16 2708 DevHandle; /*0x18 */ 2709 U16 2710 ParentDevHandle; /*0x1A */ 2711 U16 2712 ExpanderChangeCount; /*0x1C */ 2713 U16 2714 ExpanderRouteIndexes; /*0x1E */ 2715 U8 2716 NumPhys; /*0x20 */ 2717 U8 2718 SASLevel; /*0x21 */ 2719 U16 2720 Flags; /*0x22 */ 2721 U16 2722 STPBusInactivityTimeLimit; /*0x24 */ 2723 U16 2724 STPMaxConnectTimeLimit; /*0x26 */ 2725 U16 2726 STP_SMP_NexusLossTime; /*0x28 */ 2727 U16 2728 MaxNumRoutedSasAddresses; /*0x2A */ 2729 U64 2730 ActiveZoneManagerSASAddress;/*0x2C */ 2731 U16 2732 ZoneLockInactivityLimit; /*0x34 */ 2733 U16 2734 Reserved1; /*0x36 */ 2735 U8 2736 TimeToReducedFunc; /*0x38 */ 2737 U8 2738 InitialTimeToReducedFunc; /*0x39 */ 2739 U8 2740 MaxReducedFuncTime; /*0x3A */ 2741 U8 2742 Reserved2; /*0x3B */ 2743 } MPI2_CONFIG_PAGE_EXPANDER_0, 2744 *PTR_MPI2_CONFIG_PAGE_EXPANDER_0, 2745 Mpi2ExpanderPage0_t, *pMpi2ExpanderPage0_t; 2746 2747 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06) 2748 2749 /*values for SAS Expander Page 0 DiscoveryStatus field */ 2750 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2751 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2752 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000) 2753 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2754 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2755 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2756 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2757 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000) 2758 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2759 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2760 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2761 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2762 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2763 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2764 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2765 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2766 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2767 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2768 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2769 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2770 2771 /*values for SAS Expander Page 0 Flags field */ 2772 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 2773 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 2774 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 2775 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 2776 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 2777 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 2778 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 2779 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 2780 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 2781 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 2782 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 2783 2784 2785 /*SAS Expander Page 1 */ 2786 2787 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 { 2788 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2789 Header; /*0x00 */ 2790 U8 2791 PhysicalPort; /*0x08 */ 2792 U8 2793 Reserved1; /*0x09 */ 2794 U16 2795 Reserved2; /*0x0A */ 2796 U8 2797 NumPhys; /*0x0C */ 2798 U8 2799 Phy; /*0x0D */ 2800 U16 2801 NumTableEntriesProgrammed; /*0x0E */ 2802 U8 2803 ProgrammedLinkRate; /*0x10 */ 2804 U8 2805 HwLinkRate; /*0x11 */ 2806 U16 2807 AttachedDevHandle; /*0x12 */ 2808 U32 2809 PhyInfo; /*0x14 */ 2810 U32 2811 AttachedDeviceInfo; /*0x18 */ 2812 U16 2813 ExpanderDevHandle; /*0x1C */ 2814 U8 2815 ChangeCount; /*0x1E */ 2816 U8 2817 NegotiatedLinkRate; /*0x1F */ 2818 U8 2819 PhyIdentifier; /*0x20 */ 2820 U8 2821 AttachedPhyIdentifier; /*0x21 */ 2822 U8 2823 Reserved3; /*0x22 */ 2824 U8 2825 DiscoveryInfo; /*0x23 */ 2826 U32 2827 AttachedPhyInfo; /*0x24 */ 2828 U8 2829 ZoneGroup; /*0x28 */ 2830 U8 2831 SelfConfigStatus; /*0x29 */ 2832 U16 2833 Reserved4; /*0x2A */ 2834 } MPI2_CONFIG_PAGE_EXPANDER_1, 2835 *PTR_MPI2_CONFIG_PAGE_EXPANDER_1, 2836 Mpi2ExpanderPage1_t, *pMpi2ExpanderPage1_t; 2837 2838 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02) 2839 2840 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2841 2842 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2843 2844 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2845 2846 /*see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines 2847 *used for the AttachedDeviceInfo field */ 2848 2849 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2850 2851 /*values for SAS Expander Page 1 DiscoveryInfo field */ 2852 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2853 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2854 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2855 2856 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2857 2858 2859 /**************************************************************************** 2860 * SAS Device Config Pages 2861 ****************************************************************************/ 2862 2863 /*SAS Device Page 0 */ 2864 2865 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 { 2866 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2867 Header; /*0x00 */ 2868 U16 2869 Slot; /*0x08 */ 2870 U16 2871 EnclosureHandle; /*0x0A */ 2872 U64 2873 SASAddress; /*0x0C */ 2874 U16 2875 ParentDevHandle; /*0x14 */ 2876 U8 2877 PhyNum; /*0x16 */ 2878 U8 2879 AccessStatus; /*0x17 */ 2880 U16 2881 DevHandle; /*0x18 */ 2882 U8 2883 AttachedPhyIdentifier; /*0x1A */ 2884 U8 2885 ZoneGroup; /*0x1B */ 2886 U32 2887 DeviceInfo; /*0x1C */ 2888 U16 2889 Flags; /*0x20 */ 2890 U8 2891 PhysicalPort; /*0x22 */ 2892 U8 2893 MaxPortConnections; /*0x23 */ 2894 U64 2895 DeviceName; /*0x24 */ 2896 U8 2897 PortGroups; /*0x2C */ 2898 U8 2899 DmaGroup; /*0x2D */ 2900 U8 2901 ControlGroup; /*0x2E */ 2902 U8 2903 EnclosureLevel; /*0x2F */ 2904 U32 2905 ConnectorName[4]; /*0x30 */ 2906 U32 2907 Reserved3; /*0x34 */ 2908 } MPI2_CONFIG_PAGE_SAS_DEV_0, 2909 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_0, 2910 Mpi2SasDevicePage0_t, 2911 *pMpi2SasDevicePage0_t; 2912 2913 #define MPI2_SASDEVICE0_PAGEVERSION (0x09) 2914 2915 /*values for SAS Device Page 0 AccessStatus field */ 2916 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2917 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2918 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2919 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2920 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2921 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05) 2922 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06) 2923 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07) 2924 /*specific values for SATA Init failures */ 2925 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2926 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2927 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2928 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2929 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2930 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2931 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2932 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2933 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2934 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2935 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2936 2937 /*see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2938 2939 /*values for SAS Device Page 0 Flags field */ 2940 #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000) 2941 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH (0x4000) 2942 #define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE (0x2000) 2943 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000) 2944 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800) 2945 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2946 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2947 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2948 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2949 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2950 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2951 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2952 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2953 #define MPI2_SAS_DEVICE0_FLAGS_PERSIST_CAPABLE (0x0004) 2954 #define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID (0x0002) 2955 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2956 2957 2958 /*SAS Device Page 1 */ 2959 2960 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 { 2961 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2962 Header; /*0x00 */ 2963 U32 2964 Reserved1; /*0x08 */ 2965 U64 2966 SASAddress; /*0x0C */ 2967 U32 2968 Reserved2; /*0x14 */ 2969 U16 2970 DevHandle; /*0x18 */ 2971 U16 2972 Reserved3; /*0x1A */ 2973 U8 2974 InitialRegDeviceFIS[20];/*0x1C */ 2975 } MPI2_CONFIG_PAGE_SAS_DEV_1, 2976 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_1, 2977 Mpi2SasDevicePage1_t, 2978 *pMpi2SasDevicePage1_t; 2979 2980 #define MPI2_SASDEVICE1_PAGEVERSION (0x01) 2981 2982 2983 /**************************************************************************** 2984 * SAS PHY Config Pages 2985 ****************************************************************************/ 2986 2987 /*SAS PHY Page 0 */ 2988 2989 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 { 2990 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2991 Header; /*0x00 */ 2992 U16 2993 OwnerDevHandle; /*0x08 */ 2994 U16 2995 Reserved1; /*0x0A */ 2996 U16 2997 AttachedDevHandle; /*0x0C */ 2998 U8 2999 AttachedPhyIdentifier; /*0x0E */ 3000 U8 3001 Reserved2; /*0x0F */ 3002 U32 3003 AttachedPhyInfo; /*0x10 */ 3004 U8 3005 ProgrammedLinkRate; /*0x14 */ 3006 U8 3007 HwLinkRate; /*0x15 */ 3008 U8 3009 ChangeCount; /*0x16 */ 3010 U8 3011 Flags; /*0x17 */ 3012 U32 3013 PhyInfo; /*0x18 */ 3014 U8 3015 NegotiatedLinkRate; /*0x1C */ 3016 U8 3017 Reserved3; /*0x1D */ 3018 U16 3019 Reserved4; /*0x1E */ 3020 } MPI2_CONFIG_PAGE_SAS_PHY_0, 3021 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_0, 3022 Mpi2SasPhyPage0_t, *pMpi2SasPhyPage0_t; 3023 3024 #define MPI2_SASPHY0_PAGEVERSION (0x03) 3025 3026 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 3027 3028 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 3029 3030 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 3031 3032 /*values for SAS PHY Page 0 Flags field */ 3033 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 3034 3035 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 3036 3037 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3038 3039 3040 /*SAS PHY Page 1 */ 3041 3042 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 { 3043 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3044 Header; /*0x00 */ 3045 U32 3046 Reserved1; /*0x08 */ 3047 U32 3048 InvalidDwordCount; /*0x0C */ 3049 U32 3050 RunningDisparityErrorCount; /*0x10 */ 3051 U32 3052 LossDwordSynchCount; /*0x14 */ 3053 U32 3054 PhyResetProblemCount; /*0x18 */ 3055 } MPI2_CONFIG_PAGE_SAS_PHY_1, 3056 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_1, 3057 Mpi2SasPhyPage1_t, *pMpi2SasPhyPage1_t; 3058 3059 #define MPI2_SASPHY1_PAGEVERSION (0x01) 3060 3061 3062 /*SAS PHY Page 2 */ 3063 3064 typedef struct _MPI2_SASPHY2_PHY_EVENT { 3065 U8 PhyEventCode; /*0x00 */ 3066 U8 Reserved1; /*0x01 */ 3067 U16 Reserved2; /*0x02 */ 3068 U32 PhyEventInfo; /*0x04 */ 3069 } MPI2_SASPHY2_PHY_EVENT, *PTR_MPI2_SASPHY2_PHY_EVENT, 3070 Mpi2SasPhy2PhyEvent_t, *pMpi2SasPhy2PhyEvent_t; 3071 3072 /*use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */ 3073 3074 3075 /* 3076 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3077 *one and check the value returned for NumPhyEvents at runtime. 3078 */ 3079 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX 3080 #define MPI2_SASPHY2_PHY_EVENT_MAX (1) 3081 #endif 3082 3083 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 { 3084 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3085 Header; /*0x00 */ 3086 U32 3087 Reserved1; /*0x08 */ 3088 U8 3089 NumPhyEvents; /*0x0C */ 3090 U8 3091 Reserved2; /*0x0D */ 3092 U16 3093 Reserved3; /*0x0E */ 3094 MPI2_SASPHY2_PHY_EVENT 3095 PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /*0x10 */ 3096 } MPI2_CONFIG_PAGE_SAS_PHY_2, 3097 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_2, 3098 Mpi2SasPhyPage2_t, 3099 *pMpi2SasPhyPage2_t; 3100 3101 #define MPI2_SASPHY2_PAGEVERSION (0x00) 3102 3103 3104 /*SAS PHY Page 3 */ 3105 3106 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG { 3107 U8 PhyEventCode; /*0x00 */ 3108 U8 Reserved1; /*0x01 */ 3109 U16 Reserved2; /*0x02 */ 3110 U8 CounterType; /*0x04 */ 3111 U8 ThresholdWindow; /*0x05 */ 3112 U8 TimeUnits; /*0x06 */ 3113 U8 Reserved3; /*0x07 */ 3114 U32 EventThreshold; /*0x08 */ 3115 U16 ThresholdFlags; /*0x0C */ 3116 U16 Reserved4; /*0x0E */ 3117 } MPI2_SASPHY3_PHY_EVENT_CONFIG, 3118 *PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG, 3119 Mpi2SasPhy3PhyEventConfig_t, 3120 *pMpi2SasPhy3PhyEventConfig_t; 3121 3122 /*values for PhyEventCode field */ 3123 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 3124 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 3125 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 3126 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 3127 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 3128 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 3129 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 3130 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 3131 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 3132 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 3133 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 3134 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 3135 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 3136 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 3137 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 3138 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 3139 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 3140 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A) 3141 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B) 3142 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C) 3143 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D) 3144 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E) 3145 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 3146 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 3147 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 3148 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 3149 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 3150 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 3151 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 3152 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 3153 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 3154 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 3155 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 3156 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 3157 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) 3158 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) 3159 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2) 3160 3161 /*Following codes are product specific and in MPI v2.6 and later */ 3162 #define MPI2_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xD3) 3163 #define MPI2_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xD4) 3164 #define MPI2_SASPHY3_EVENT_CODE_LCCONN_TIME (0xD5) 3165 #define MPI2_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xD6) 3166 #define MPI2_SASPHY3_EVENT_CODE_SATA_TX_START (0xD7) 3167 #define MPI2_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xD8) 3168 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xD9) 3169 #define MPI2_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xDA) 3170 #define MPI2_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xDB) 3171 #define MPI2_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xDC) 3172 3173 3174 /*values for the CounterType field */ 3175 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 3176 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 3177 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 3178 3179 /*values for the TimeUnits field */ 3180 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 3181 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 3182 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 3183 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 3184 3185 /*values for the ThresholdFlags field */ 3186 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002) 3187 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 3188 3189 /* 3190 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3191 *one and check the value returned for NumPhyEvents at runtime. 3192 */ 3193 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX 3194 #define MPI2_SASPHY3_PHY_EVENT_MAX (1) 3195 #endif 3196 3197 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 { 3198 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3199 Header; /*0x00 */ 3200 U32 3201 Reserved1; /*0x08 */ 3202 U8 3203 NumPhyEvents; /*0x0C */ 3204 U8 3205 Reserved2; /*0x0D */ 3206 U16 3207 Reserved3; /*0x0E */ 3208 MPI2_SASPHY3_PHY_EVENT_CONFIG 3209 PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /*0x10 */ 3210 } MPI2_CONFIG_PAGE_SAS_PHY_3, 3211 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_3, 3212 Mpi2SasPhyPage3_t, *pMpi2SasPhyPage3_t; 3213 3214 #define MPI2_SASPHY3_PAGEVERSION (0x00) 3215 3216 3217 /*SAS PHY Page 4 */ 3218 3219 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 { 3220 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3221 Header; /*0x00 */ 3222 U16 3223 Reserved1; /*0x08 */ 3224 U8 3225 Reserved2; /*0x0A */ 3226 U8 3227 Flags; /*0x0B */ 3228 U8 3229 InitialFrame[28]; /*0x0C */ 3230 } MPI2_CONFIG_PAGE_SAS_PHY_4, 3231 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_4, 3232 Mpi2SasPhyPage4_t, *pMpi2SasPhyPage4_t; 3233 3234 #define MPI2_SASPHY4_PAGEVERSION (0x00) 3235 3236 /*values for the Flags field */ 3237 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02) 3238 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01) 3239 3240 3241 3242 3243 /**************************************************************************** 3244 * SAS Port Config Pages 3245 ****************************************************************************/ 3246 3247 /*SAS Port Page 0 */ 3248 3249 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 { 3250 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3251 Header; /*0x00 */ 3252 U8 3253 PortNumber; /*0x08 */ 3254 U8 3255 PhysicalPort; /*0x09 */ 3256 U8 3257 PortWidth; /*0x0A */ 3258 U8 3259 PhysicalPortWidth; /*0x0B */ 3260 U8 3261 ZoneGroup; /*0x0C */ 3262 U8 3263 Reserved1; /*0x0D */ 3264 U16 3265 Reserved2; /*0x0E */ 3266 U64 3267 SASAddress; /*0x10 */ 3268 U32 3269 DeviceInfo; /*0x18 */ 3270 U32 3271 Reserved3; /*0x1C */ 3272 U32 3273 Reserved4; /*0x20 */ 3274 } MPI2_CONFIG_PAGE_SAS_PORT_0, 3275 *PTR_MPI2_CONFIG_PAGE_SAS_PORT_0, 3276 Mpi2SasPortPage0_t, *pMpi2SasPortPage0_t; 3277 3278 #define MPI2_SASPORT0_PAGEVERSION (0x00) 3279 3280 /*see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */ 3281 3282 3283 /**************************************************************************** 3284 * SAS Enclosure Config Pages 3285 ****************************************************************************/ 3286 3287 /*SAS Enclosure Page 0 */ 3288 3289 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 { 3290 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3291 U32 Reserved1; /*0x08 */ 3292 U64 EnclosureLogicalID; /*0x0C */ 3293 U16 Flags; /*0x14 */ 3294 U16 EnclosureHandle; /*0x16 */ 3295 U16 NumSlots; /*0x18 */ 3296 U16 StartSlot; /*0x1A */ 3297 U8 ChassisSlot; /*0x1C */ 3298 U8 EnclosureLevel; /*0x1D */ 3299 U16 SEPDevHandle; /*0x1E */ 3300 U8 OEMRD; /*0x20 */ 3301 U8 Reserved1a; /*0x21 */ 3302 U16 Reserved2; /*0x22 */ 3303 U32 Reserved3; /*0x24 */ 3304 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3305 *PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3306 Mpi2SasEnclosurePage0_t, *pMpi2SasEnclosurePage0_t, 3307 MPI26_CONFIG_PAGE_ENCLOSURE_0, 3308 *PTR_MPI26_CONFIG_PAGE_ENCLOSURE_0, 3309 Mpi26EnclosurePage0_t, *pMpi26EnclosurePage0_t; 3310 3311 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x04) 3312 3313 /*values for SAS Enclosure Page 0 Flags field */ 3314 #define MPI26_SAS_ENCLS0_FLAGS_OEMRD_VALID (0x0080) 3315 #define MPI26_SAS_ENCLS0_FLAGS_OEMRD_COLLECTING (0x0040) 3316 #define MPI2_SAS_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020) 3317 #define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010) 3318 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 3319 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3320 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3321 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3322 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3323 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3324 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3325 3326 #define MPI26_ENCLOSURE0_PAGEVERSION (0x04) 3327 3328 /*Values for Enclosure Page 0 Flags field */ 3329 #define MPI26_ENCLS0_FLAGS_OEMRD_VALID (0x0080) 3330 #define MPI26_ENCLS0_FLAGS_OEMRD_COLLECTING (0x0040) 3331 #define MPI26_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020) 3332 #define MPI26_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010) 3333 #define MPI26_ENCLS0_FLAGS_MNG_MASK (0x000F) 3334 #define MPI26_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3335 #define MPI26_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3336 #define MPI26_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3337 #define MPI26_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3338 #define MPI26_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3339 #define MPI26_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3340 3341 /**************************************************************************** 3342 * Log Config Page 3343 ****************************************************************************/ 3344 3345 /*Log Page 0 */ 3346 3347 /* 3348 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3349 *one and check the value returned for NumLogEntries at runtime. 3350 */ 3351 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES 3352 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1) 3353 #endif 3354 3355 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C) 3356 3357 typedef struct _MPI2_LOG_0_ENTRY { 3358 U64 TimeStamp; /*0x00 */ 3359 U32 Reserved1; /*0x08 */ 3360 U16 LogSequence; /*0x0C */ 3361 U16 LogEntryQualifier; /*0x0E */ 3362 U8 VP_ID; /*0x10 */ 3363 U8 VF_ID; /*0x11 */ 3364 U16 Reserved2; /*0x12 */ 3365 U8 3366 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/*0x14 */ 3367 } MPI2_LOG_0_ENTRY, *PTR_MPI2_LOG_0_ENTRY, 3368 Mpi2Log0Entry_t, *pMpi2Log0Entry_t; 3369 3370 /*values for Log Page 0 LogEntry LogEntryQualifier field */ 3371 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 3372 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 3373 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002) 3374 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000) 3375 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF) 3376 3377 typedef struct _MPI2_CONFIG_PAGE_LOG_0 { 3378 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3379 U32 Reserved1; /*0x08 */ 3380 U32 Reserved2; /*0x0C */ 3381 U16 NumLogEntries;/*0x10 */ 3382 U16 Reserved3; /*0x12 */ 3383 MPI2_LOG_0_ENTRY 3384 LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /*0x14 */ 3385 } MPI2_CONFIG_PAGE_LOG_0, *PTR_MPI2_CONFIG_PAGE_LOG_0, 3386 Mpi2LogPage0_t, *pMpi2LogPage0_t; 3387 3388 #define MPI2_LOG_0_PAGEVERSION (0x02) 3389 3390 3391 /**************************************************************************** 3392 * RAID Config Page 3393 ****************************************************************************/ 3394 3395 /*RAID Page 0 */ 3396 3397 /* 3398 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3399 *one and check the value returned for NumElements at runtime. 3400 */ 3401 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS 3402 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1) 3403 #endif 3404 3405 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT { 3406 U16 ElementFlags; /*0x00 */ 3407 U16 VolDevHandle; /*0x02 */ 3408 U8 HotSparePool; /*0x04 */ 3409 U8 PhysDiskNum; /*0x05 */ 3410 U16 PhysDiskDevHandle; /*0x06 */ 3411 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3412 *PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3413 Mpi2RaidConfig0ConfigElement_t, 3414 *pMpi2RaidConfig0ConfigElement_t; 3415 3416 /*values for the ElementFlags field */ 3417 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F) 3418 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000) 3419 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001) 3420 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002) 3421 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003) 3422 3423 3424 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 { 3425 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3426 U8 NumHotSpares; /*0x08 */ 3427 U8 NumPhysDisks; /*0x09 */ 3428 U8 NumVolumes; /*0x0A */ 3429 U8 ConfigNum; /*0x0B */ 3430 U32 Flags; /*0x0C */ 3431 U8 ConfigGUID[24]; /*0x10 */ 3432 U32 Reserved1; /*0x28 */ 3433 U8 NumElements; /*0x2C */ 3434 U8 Reserved2; /*0x2D */ 3435 U16 Reserved3; /*0x2E */ 3436 MPI2_RAIDCONFIG0_CONFIG_ELEMENT 3437 ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /*0x30 */ 3438 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3439 *PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3440 Mpi2RaidConfigurationPage0_t, 3441 *pMpi2RaidConfigurationPage0_t; 3442 3443 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00) 3444 3445 /*values for RAID Configuration Page 0 Flags field */ 3446 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001) 3447 3448 3449 /**************************************************************************** 3450 * Driver Persistent Mapping Config Pages 3451 ****************************************************************************/ 3452 3453 /*Driver Persistent Mapping Page 0 */ 3454 3455 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY { 3456 U64 PhysicalIdentifier; /*0x00 */ 3457 U16 MappingInformation; /*0x08 */ 3458 U16 DeviceIndex; /*0x0A */ 3459 U32 PhysicalBitsMapping; /*0x0C */ 3460 U32 Reserved1; /*0x10 */ 3461 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3462 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3463 Mpi2DriverMap0Entry_t, *pMpi2DriverMap0Entry_t; 3464 3465 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 { 3466 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3467 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /*0x08 */ 3468 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3469 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3470 Mpi2DriverMappingPage0_t, *pMpi2DriverMappingPage0_t; 3471 3472 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00) 3473 3474 /*values for Driver Persistent Mapping Page 0 MappingInformation field */ 3475 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0) 3476 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4) 3477 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F) 3478 3479 3480 /**************************************************************************** 3481 * Ethernet Config Pages 3482 ****************************************************************************/ 3483 3484 /*Ethernet Page 0 */ 3485 3486 /*IP address (union of IPv4 and IPv6) */ 3487 typedef union _MPI2_ETHERNET_IP_ADDR { 3488 U32 IPv4Addr; 3489 U32 IPv6Addr[4]; 3490 } MPI2_ETHERNET_IP_ADDR, *PTR_MPI2_ETHERNET_IP_ADDR, 3491 Mpi2EthernetIpAddr_t, *pMpi2EthernetIpAddr_t; 3492 3493 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32) 3494 3495 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 { 3496 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3497 U8 NumInterfaces; /*0x08 */ 3498 U8 Reserved0; /*0x09 */ 3499 U16 Reserved1; /*0x0A */ 3500 U32 Status; /*0x0C */ 3501 U8 MediaState; /*0x10 */ 3502 U8 Reserved2; /*0x11 */ 3503 U16 Reserved3; /*0x12 */ 3504 U8 MacAddress[6]; /*0x14 */ 3505 U8 Reserved4; /*0x1A */ 3506 U8 Reserved5; /*0x1B */ 3507 MPI2_ETHERNET_IP_ADDR IpAddress; /*0x1C */ 3508 MPI2_ETHERNET_IP_ADDR SubnetMask; /*0x2C */ 3509 MPI2_ETHERNET_IP_ADDR GatewayIpAddress;/*0x3C */ 3510 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /*0x4C */ 3511 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /*0x5C */ 3512 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /*0x6C */ 3513 U8 3514 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */ 3515 } MPI2_CONFIG_PAGE_ETHERNET_0, 3516 *PTR_MPI2_CONFIG_PAGE_ETHERNET_0, 3517 Mpi2EthernetPage0_t, *pMpi2EthernetPage0_t; 3518 3519 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00) 3520 3521 /*values for Ethernet Page 0 Status field */ 3522 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000) 3523 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000) 3524 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000) 3525 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100) 3526 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080) 3527 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040) 3528 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020) 3529 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010) 3530 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008) 3531 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004) 3532 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002) 3533 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001) 3534 3535 /*values for Ethernet Page 0 MediaState field */ 3536 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80) 3537 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00) 3538 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80) 3539 3540 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07) 3541 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00) 3542 #define MPI2_ETHPG0_MS_10MBIT (0x01) 3543 #define MPI2_ETHPG0_MS_100MBIT (0x02) 3544 #define MPI2_ETHPG0_MS_1GBIT (0x03) 3545 3546 3547 /*Ethernet Page 1 */ 3548 3549 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 { 3550 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3551 Header; /*0x00 */ 3552 U32 3553 Reserved0; /*0x08 */ 3554 U32 3555 Flags; /*0x0C */ 3556 U8 3557 MediaState; /*0x10 */ 3558 U8 3559 Reserved1; /*0x11 */ 3560 U16 3561 Reserved2; /*0x12 */ 3562 U8 3563 MacAddress[6]; /*0x14 */ 3564 U8 3565 Reserved3; /*0x1A */ 3566 U8 3567 Reserved4; /*0x1B */ 3568 MPI2_ETHERNET_IP_ADDR 3569 StaticIpAddress; /*0x1C */ 3570 MPI2_ETHERNET_IP_ADDR 3571 StaticSubnetMask; /*0x2C */ 3572 MPI2_ETHERNET_IP_ADDR 3573 StaticGatewayIpAddress; /*0x3C */ 3574 MPI2_ETHERNET_IP_ADDR 3575 StaticDNS1IpAddress; /*0x4C */ 3576 MPI2_ETHERNET_IP_ADDR 3577 StaticDNS2IpAddress; /*0x5C */ 3578 U32 3579 Reserved5; /*0x6C */ 3580 U32 3581 Reserved6; /*0x70 */ 3582 U32 3583 Reserved7; /*0x74 */ 3584 U32 3585 Reserved8; /*0x78 */ 3586 U8 3587 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */ 3588 } MPI2_CONFIG_PAGE_ETHERNET_1, 3589 *PTR_MPI2_CONFIG_PAGE_ETHERNET_1, 3590 Mpi2EthernetPage1_t, *pMpi2EthernetPage1_t; 3591 3592 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00) 3593 3594 /*values for Ethernet Page 1 Flags field */ 3595 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100) 3596 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080) 3597 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040) 3598 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020) 3599 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010) 3600 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008) 3601 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004) 3602 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002) 3603 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001) 3604 3605 /*values for Ethernet Page 1 MediaState field */ 3606 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80) 3607 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00) 3608 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80) 3609 3610 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07) 3611 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00) 3612 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01) 3613 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02) 3614 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03) 3615 3616 3617 /**************************************************************************** 3618 * Extended Manufacturing Config Pages 3619 ****************************************************************************/ 3620 3621 /* 3622 *Generic structure to use for product-specific extended manufacturing pages 3623 *(currently Extended Manufacturing Page 40 through Extended Manufacturing 3624 *Page 60). 3625 */ 3626 3627 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS { 3628 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3629 Header; /*0x00 */ 3630 U32 3631 ProductSpecificInfo; /*0x08 */ 3632 } MPI2_CONFIG_PAGE_EXT_MAN_PS, 3633 *PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS, 3634 Mpi2ExtManufacturingPagePS_t, 3635 *pMpi2ExtManufacturingPagePS_t; 3636 3637 /*PageVersion should be provided by product-specific code */ 3638 3639 3640 3641 /**************************************************************************** 3642 * values for fields used by several types of PCIe Config Pages 3643 ****************************************************************************/ 3644 3645 /*values for NegotiatedLinkRates fields */ 3646 #define MPI26_PCIE_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 3647 /*link rates used for Negotiated Physical Link Rate */ 3648 #define MPI26_PCIE_NEG_LINK_RATE_UNKNOWN (0x00) 3649 #define MPI26_PCIE_NEG_LINK_RATE_PHY_DISABLED (0x01) 3650 #define MPI26_PCIE_NEG_LINK_RATE_2_5 (0x02) 3651 #define MPI26_PCIE_NEG_LINK_RATE_5_0 (0x03) 3652 #define MPI26_PCIE_NEG_LINK_RATE_8_0 (0x04) 3653 #define MPI26_PCIE_NEG_LINK_RATE_16_0 (0x05) 3654 3655 3656 /**************************************************************************** 3657 * PCIe IO Unit Config Pages (MPI v2.6 and later) 3658 ****************************************************************************/ 3659 3660 /*PCIe IO Unit Page 0 */ 3661 3662 typedef struct _MPI26_PCIE_IO_UNIT0_PHY_DATA { 3663 U8 Link; /*0x00 */ 3664 U8 LinkFlags; /*0x01 */ 3665 U8 PhyFlags; /*0x02 */ 3666 U8 NegotiatedLinkRate; /*0x03 */ 3667 U32 ControllerPhyDeviceInfo;/*0x04 */ 3668 U16 AttachedDevHandle; /*0x08 */ 3669 U16 ControllerDevHandle; /*0x0A */ 3670 U32 EnumerationStatus; /*0x0C */ 3671 U32 Reserved1; /*0x10 */ 3672 } MPI26_PCIE_IO_UNIT0_PHY_DATA, 3673 *PTR_MPI26_PCIE_IO_UNIT0_PHY_DATA, 3674 Mpi26PCIeIOUnit0PhyData_t, *pMpi26PCIeIOUnit0PhyData_t; 3675 3676 /* 3677 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3678 *one and check the value returned for NumPhys at runtime. 3679 */ 3680 #ifndef MPI26_PCIE_IOUNIT0_PHY_MAX 3681 #define MPI26_PCIE_IOUNIT0_PHY_MAX (1) 3682 #endif 3683 3684 typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_0 { 3685 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3686 U32 Reserved1; /*0x08 */ 3687 U8 NumPhys; /*0x0C */ 3688 U8 InitStatus; /*0x0D */ 3689 U16 Reserved3; /*0x0E */ 3690 MPI26_PCIE_IO_UNIT0_PHY_DATA 3691 PhyData[MPI26_PCIE_IOUNIT0_PHY_MAX]; /*0x10 */ 3692 } MPI26_CONFIG_PAGE_PIOUNIT_0, 3693 *PTR_MPI26_CONFIG_PAGE_PIOUNIT_0, 3694 Mpi26PCIeIOUnitPage0_t, *pMpi26PCIeIOUnitPage0_t; 3695 3696 #define MPI26_PCIEIOUNITPAGE0_PAGEVERSION (0x00) 3697 3698 /*values for PCIe IO Unit Page 0 LinkFlags */ 3699 #define MPI26_PCIEIOUNIT0_LINKFLAGS_ENUMERATION_IN_PROGRESS (0x08) 3700 3701 /*values for PCIe IO Unit Page 0 PhyFlags */ 3702 #define MPI26_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 3703 3704 /*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3705 3706 /*see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo 3707 *values 3708 */ 3709 3710 /*values for PCIe IO Unit Page 0 EnumerationStatus */ 3711 #define MPI26_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED (0x40000000) 3712 #define MPI26_PCIEIOUNIT0_ES_MAX_DEVICES_EXCEEDED (0x20000000) 3713 3714 3715 /*PCIe IO Unit Page 1 */ 3716 3717 typedef struct _MPI26_PCIE_IO_UNIT1_PHY_DATA { 3718 U8 Link; /*0x00 */ 3719 U8 LinkFlags; /*0x01 */ 3720 U8 PhyFlags; /*0x02 */ 3721 U8 MaxMinLinkRate; /*0x03 */ 3722 U32 ControllerPhyDeviceInfo; /*0x04 */ 3723 U32 Reserved1; /*0x08 */ 3724 } MPI26_PCIE_IO_UNIT1_PHY_DATA, 3725 *PTR_MPI26_PCIE_IO_UNIT1_PHY_DATA, 3726 Mpi26PCIeIOUnit1PhyData_t, *pMpi26PCIeIOUnit1PhyData_t; 3727 3728 /*values for LinkFlags */ 3729 #define MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SEPARATE_REFCLK (0x00) 3730 #define MPI26_PCIEIOUNIT1_LINKFLAGS_SRIS_EN (0x01) 3731 #define MPI26_PCIEIOUNIT1_LINKFLAGS_SRNS_EN (0x02) 3732 3733 /* 3734 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3735 *one and check the value returned for NumPhys at runtime. 3736 */ 3737 #ifndef MPI26_PCIE_IOUNIT1_PHY_MAX 3738 #define MPI26_PCIE_IOUNIT1_PHY_MAX (1) 3739 #endif 3740 3741 typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_1 { 3742 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3743 U16 ControlFlags; /*0x08 */ 3744 U16 Reserved; /*0x0A */ 3745 U16 AdditionalControlFlags; /*0x0C */ 3746 U16 NVMeMaxQueueDepth; /*0x0E */ 3747 U8 NumPhys; /*0x10 */ 3748 U8 DMDReportPCIe; /*0x11 */ 3749 U16 Reserved2; /*0x12 */ 3750 MPI26_PCIE_IO_UNIT1_PHY_DATA 3751 PhyData[MPI26_PCIE_IOUNIT1_PHY_MAX];/*0x14 */ 3752 } MPI26_CONFIG_PAGE_PIOUNIT_1, 3753 *PTR_MPI26_CONFIG_PAGE_PIOUNIT_1, 3754 Mpi26PCIeIOUnitPage1_t, *pMpi26PCIeIOUnitPage1_t; 3755 3756 #define MPI26_PCIEIOUNITPAGE1_PAGEVERSION (0x00) 3757 3758 /*values for PCIe IO Unit Page 1 PhyFlags */ 3759 #define MPI26_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 3760 #define MPI26_PCIEIOUNIT1_PHYFLAGS_ENDPOINT_ONLY (0x01) 3761 3762 /*values for PCIe IO Unit Page 1 MaxMinLinkRate */ 3763 #define MPI26_PCIEIOUNIT1_MAX_RATE_MASK (0xF0) 3764 #define MPI26_PCIEIOUNIT1_MAX_RATE_SHIFT (4) 3765 #define MPI26_PCIEIOUNIT1_MAX_RATE_2_5 (0x20) 3766 #define MPI26_PCIEIOUNIT1_MAX_RATE_5_0 (0x30) 3767 #define MPI26_PCIEIOUNIT1_MAX_RATE_8_0 (0x40) 3768 #define MPI26_PCIEIOUNIT1_MAX_RATE_16_0 (0x50) 3769 3770 /*values for PCIe IO Unit Page 1 DMDReportPCIe */ 3771 #define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_MASK (0x80) 3772 #define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_1_SEC (0x00) 3773 #define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_16_SEC (0x80) 3774 #define MPI26_PCIEIOUNIT1_DMDRPT_DELAY_TIME_MASK (0x7F) 3775 3776 /*see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo 3777 *values 3778 */ 3779 3780 3781 /**************************************************************************** 3782 * PCIe Switch Config Pages (MPI v2.6 and later) 3783 ****************************************************************************/ 3784 3785 /*PCIe Switch Page 0 */ 3786 3787 typedef struct _MPI26_CONFIG_PAGE_PSWITCH_0 { 3788 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3789 U8 PhysicalPort; /*0x08 */ 3790 U8 Reserved1; /*0x09 */ 3791 U16 Reserved2; /*0x0A */ 3792 U16 DevHandle; /*0x0C */ 3793 U16 ParentDevHandle; /*0x0E */ 3794 U8 NumPorts; /*0x10 */ 3795 U8 PCIeLevel; /*0x11 */ 3796 U16 Reserved3; /*0x12 */ 3797 U32 Reserved4; /*0x14 */ 3798 U32 Reserved5; /*0x18 */ 3799 U32 Reserved6; /*0x1C */ 3800 } MPI26_CONFIG_PAGE_PSWITCH_0, *PTR_MPI26_CONFIG_PAGE_PSWITCH_0, 3801 Mpi26PCIeSwitchPage0_t, *pMpi26PCIeSwitchPage0_t; 3802 3803 #define MPI26_PCIESWITCH0_PAGEVERSION (0x00) 3804 3805 3806 /*PCIe Switch Page 1 */ 3807 3808 typedef struct _MPI26_CONFIG_PAGE_PSWITCH_1 { 3809 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3810 U8 PhysicalPort; /*0x08 */ 3811 U8 Reserved1; /*0x09 */ 3812 U16 Reserved2; /*0x0A */ 3813 U8 NumPorts; /*0x0C */ 3814 U8 PortNum; /*0x0D */ 3815 U16 AttachedDevHandle; /*0x0E */ 3816 U16 SwitchDevHandle; /*0x10 */ 3817 U8 NegotiatedPortWidth; /*0x12 */ 3818 U8 NegotiatedLinkRate; /*0x13 */ 3819 U32 Reserved4; /*0x14 */ 3820 U32 Reserved5; /*0x18 */ 3821 } MPI26_CONFIG_PAGE_PSWITCH_1, *PTR_MPI26_CONFIG_PAGE_PSWITCH_1, 3822 Mpi26PCIeSwitchPage1_t, *pMpi26PCIeSwitchPage1_t; 3823 3824 #define MPI26_PCIESWITCH1_PAGEVERSION (0x00) 3825 3826 /*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3827 3828 /* defines for the Flags field */ 3829 #define MPI26_PCIESWITCH1_2_RETIMER_PRESENCE (0x0002) 3830 #define MPI26_PCIESWITCH1_RETIMER_PRESENCE (0x0001) 3831 3832 /**************************************************************************** 3833 * PCIe Device Config Pages (MPI v2.6 and later) 3834 ****************************************************************************/ 3835 3836 /*PCIe Device Page 0 */ 3837 3838 typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_0 { 3839 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3840 U16 Slot; /*0x08 */ 3841 U16 EnclosureHandle; /*0x0A */ 3842 U64 WWID; /*0x0C */ 3843 U16 ParentDevHandle; /*0x14 */ 3844 U8 PortNum; /*0x16 */ 3845 U8 AccessStatus; /*0x17 */ 3846 U16 DevHandle; /*0x18 */ 3847 U8 PhysicalPort; /*0x1A */ 3848 U8 Reserved1; /*0x1B */ 3849 U32 DeviceInfo; /*0x1C */ 3850 U32 Flags; /*0x20 */ 3851 U8 SupportedLinkRates; /*0x24 */ 3852 U8 MaxPortWidth; /*0x25 */ 3853 U8 NegotiatedPortWidth; /*0x26 */ 3854 U8 NegotiatedLinkRate; /*0x27 */ 3855 U8 EnclosureLevel; /*0x28 */ 3856 U8 Reserved2; /*0x29 */ 3857 U16 Reserved3; /*0x2A */ 3858 U8 ConnectorName[4]; /*0x2C */ 3859 U32 Reserved4; /*0x30 */ 3860 U32 Reserved5; /*0x34 */ 3861 } MPI26_CONFIG_PAGE_PCIEDEV_0, *PTR_MPI26_CONFIG_PAGE_PCIEDEV_0, 3862 Mpi26PCIeDevicePage0_t, *pMpi26PCIeDevicePage0_t; 3863 3864 #define MPI26_PCIEDEVICE0_PAGEVERSION (0x01) 3865 3866 /*values for PCIe Device Page 0 AccessStatus field */ 3867 #define MPI26_PCIEDEV0_ASTATUS_NO_ERRORS (0x00) 3868 #define MPI26_PCIEDEV0_ASTATUS_NEEDS_INITIALIZATION (0x04) 3869 #define MPI26_PCIEDEV0_ASTATUS_CAPABILITY_FAILED (0x02) 3870 #define MPI26_PCIEDEV0_ASTATUS_DEVICE_BLOCKED (0x07) 3871 #define MPI26_PCIEDEV0_ASTATUS_MEMORY_SPACE_ACCESS_FAILED (0x08) 3872 #define MPI26_PCIEDEV0_ASTATUS_UNSUPPORTED_DEVICE (0x09) 3873 #define MPI26_PCIEDEV0_ASTATUS_MSIX_REQUIRED (0x0A) 3874 #define MPI26_PCIEDEV0_ASTATUS_UNKNOWN (0x10) 3875 3876 #define MPI26_PCIEDEV0_ASTATUS_NVME_READY_TIMEOUT (0x30) 3877 #define MPI26_PCIEDEV0_ASTATUS_NVME_DEVCFG_UNSUPPORTED (0x31) 3878 #define MPI26_PCIEDEV0_ASTATUS_NVME_IDENTIFY_FAILED (0x32) 3879 #define MPI26_PCIEDEV0_ASTATUS_NVME_QCONFIG_FAILED (0x33) 3880 #define MPI26_PCIEDEV0_ASTATUS_NVME_QCREATION_FAILED (0x34) 3881 #define MPI26_PCIEDEV0_ASTATUS_NVME_EVENTCFG_FAILED (0x35) 3882 #define MPI26_PCIEDEV0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED (0x36) 3883 #define MPI26_PCIEDEV0_ASTATUS_NVME_IDLE_TIMEOUT (0x37) 3884 #define MPI26_PCIEDEV0_ASTATUS_NVME_FAILURE_STATUS (0x38) 3885 3886 #define MPI26_PCIEDEV0_ASTATUS_INIT_FAIL_MAX (0x3F) 3887 3888 /*see mpi2_pci.h for the MPI26_PCIE_DEVINFO_ defines used for the DeviceInfo 3889 *field 3890 */ 3891 3892 /*values for PCIe Device Page 0 Flags field*/ 3893 #define MPI26_PCIEDEV0_FLAGS_2_RETIMER_PRESENCE (0x00020000) 3894 #define MPI26_PCIEDEV0_FLAGS_RETIMER_PRESENCE (0x00010000) 3895 #define MPI26_PCIEDEV0_FLAGS_UNAUTHORIZED_DEVICE (0x00008000) 3896 #define MPI26_PCIEDEV0_FLAGS_ENABLED_FAST_PATH (0x00004000) 3897 #define MPI26_PCIEDEV0_FLAGS_FAST_PATH_CAPABLE (0x00002000) 3898 #define MPI26_PCIEDEV0_FLAGS_ASYNCHRONOUS_NOTIFICATION (0x00000400) 3899 #define MPI26_PCIEDEV0_FLAGS_ATA_SW_PRESERVATION (0x00000200) 3900 #define MPI26_PCIEDEV0_FLAGS_UNSUPPORTED_DEVICE (0x00000100) 3901 #define MPI26_PCIEDEV0_FLAGS_ATA_48BIT_LBA_SUPPORTED (0x00000080) 3902 #define MPI26_PCIEDEV0_FLAGS_ATA_SMART_SUPPORTED (0x00000040) 3903 #define MPI26_PCIEDEV0_FLAGS_ATA_NCQ_SUPPORTED (0x00000020) 3904 #define MPI26_PCIEDEV0_FLAGS_ATA_FUA_SUPPORTED (0x00000010) 3905 #define MPI26_PCIEDEV0_FLAGS_ENCL_LEVEL_VALID (0x00000002) 3906 #define MPI26_PCIEDEV0_FLAGS_DEVICE_PRESENT (0x00000001) 3907 3908 /* values for PCIe Device Page 0 SupportedLinkRates field */ 3909 #define MPI26_PCIEDEV0_LINK_RATE_16_0_SUPPORTED (0x08) 3910 #define MPI26_PCIEDEV0_LINK_RATE_8_0_SUPPORTED (0x04) 3911 #define MPI26_PCIEDEV0_LINK_RATE_5_0_SUPPORTED (0x02) 3912 #define MPI26_PCIEDEV0_LINK_RATE_2_5_SUPPORTED (0x01) 3913 3914 /*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3915 3916 3917 /*PCIe Device Page 2 */ 3918 3919 typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_2 { 3920 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3921 U16 DevHandle; /*0x08 */ 3922 U8 ControllerResetTO; /* 0x0A */ 3923 U8 Reserved1; /* 0x0B */ 3924 U32 MaximumDataTransferSize; /*0x0C */ 3925 U32 Capabilities; /*0x10 */ 3926 U16 NOIOB; /* 0x14 */ 3927 U16 Reserved2; /* 0x16 */ 3928 } MPI26_CONFIG_PAGE_PCIEDEV_2, *PTR_MPI26_CONFIG_PAGE_PCIEDEV_2, 3929 Mpi26PCIeDevicePage2_t, *pMpi26PCIeDevicePage2_t; 3930 3931 #define MPI26_PCIEDEVICE2_PAGEVERSION (0x01) 3932 3933 /*defines for PCIe Device Page 2 Capabilities field */ 3934 #define MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN (0x00000008) 3935 #define MPI26_PCIEDEV2_CAP_SGL_FORMAT (0x00000004) 3936 #define MPI26_PCIEDEV2_CAP_BIT_BUCKET_SUPPORT (0x00000002) 3937 #define MPI26_PCIEDEV2_CAP_SGL_SUPPORT (0x00000001) 3938 3939 /* Defines for the NOIOB field */ 3940 #define MPI26_PCIEDEV2_NOIOB_UNSUPPORTED (0x0000) 3941 3942 /**************************************************************************** 3943 * PCIe Link Config Pages (MPI v2.6 and later) 3944 ****************************************************************************/ 3945 3946 /*PCIe Link Page 1 */ 3947 3948 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_1 { 3949 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3950 U8 Link; /*0x08 */ 3951 U8 Reserved1; /*0x09 */ 3952 U16 Reserved2; /*0x0A */ 3953 U32 CorrectableErrorCount; /*0x0C */ 3954 U16 NonFatalErrorCount; /*0x10 */ 3955 U16 Reserved3; /*0x12 */ 3956 U16 FatalErrorCount; /*0x14 */ 3957 U16 Reserved4; /*0x16 */ 3958 } MPI26_CONFIG_PAGE_PCIELINK_1, *PTR_MPI26_CONFIG_PAGE_PCIELINK_1, 3959 Mpi26PcieLinkPage1_t, *pMpi26PcieLinkPage1_t; 3960 3961 #define MPI26_PCIELINK1_PAGEVERSION (0x00) 3962 3963 /*PCIe Link Page 2 */ 3964 3965 typedef struct _MPI26_PCIELINK2_LINK_EVENT { 3966 U8 LinkEventCode; /*0x00 */ 3967 U8 Reserved1; /*0x01 */ 3968 U16 Reserved2; /*0x02 */ 3969 U32 LinkEventInfo; /*0x04 */ 3970 } MPI26_PCIELINK2_LINK_EVENT, *PTR_MPI26_PCIELINK2_LINK_EVENT, 3971 Mpi26PcieLink2LinkEvent_t, *pMpi26PcieLink2LinkEvent_t; 3972 3973 /*use MPI26_PCIELINK3_EVTCODE_ for the LinkEventCode field */ 3974 3975 3976 /* 3977 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3978 *one and check the value returned for NumLinkEvents at runtime. 3979 */ 3980 #ifndef MPI26_PCIELINK2_LINK_EVENT_MAX 3981 #define MPI26_PCIELINK2_LINK_EVENT_MAX (1) 3982 #endif 3983 3984 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_2 { 3985 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3986 U8 Link; /*0x08 */ 3987 U8 Reserved1; /*0x09 */ 3988 U16 Reserved2; /*0x0A */ 3989 U8 NumLinkEvents; /*0x0C */ 3990 U8 Reserved3; /*0x0D */ 3991 U16 Reserved4; /*0x0E */ 3992 MPI26_PCIELINK2_LINK_EVENT 3993 LinkEvent[MPI26_PCIELINK2_LINK_EVENT_MAX]; /*0x10 */ 3994 } MPI26_CONFIG_PAGE_PCIELINK_2, *PTR_MPI26_CONFIG_PAGE_PCIELINK_2, 3995 Mpi26PcieLinkPage2_t, *pMpi26PcieLinkPage2_t; 3996 3997 #define MPI26_PCIELINK2_PAGEVERSION (0x00) 3998 3999 /*PCIe Link Page 3 */ 4000 4001 typedef struct _MPI26_PCIELINK3_LINK_EVENT_CONFIG { 4002 U8 LinkEventCode; /*0x00 */ 4003 U8 Reserved1; /*0x01 */ 4004 U16 Reserved2; /*0x02 */ 4005 U8 CounterType; /*0x04 */ 4006 U8 ThresholdWindow; /*0x05 */ 4007 U8 TimeUnits; /*0x06 */ 4008 U8 Reserved3; /*0x07 */ 4009 U32 EventThreshold; /*0x08 */ 4010 U16 ThresholdFlags; /*0x0C */ 4011 U16 Reserved4; /*0x0E */ 4012 } MPI26_PCIELINK3_LINK_EVENT_CONFIG, *PTR_MPI26_PCIELINK3_LINK_EVENT_CONFIG, 4013 Mpi26PcieLink3LinkEventConfig_t, *pMpi26PcieLink3LinkEventConfig_t; 4014 4015 /*values for LinkEventCode field */ 4016 #define MPI26_PCIELINK3_EVTCODE_NO_EVENT (0x00) 4017 #define MPI26_PCIELINK3_EVTCODE_CORRECTABLE_ERROR_RECEIVED (0x01) 4018 #define MPI26_PCIELINK3_EVTCODE_NON_FATAL_ERROR_RECEIVED (0x02) 4019 #define MPI26_PCIELINK3_EVTCODE_FATAL_ERROR_RECEIVED (0x03) 4020 #define MPI26_PCIELINK3_EVTCODE_DATA_LINK_ERROR_DETECTED (0x04) 4021 #define MPI26_PCIELINK3_EVTCODE_TRANSACTION_LAYER_ERROR_DETECTED (0x05) 4022 #define MPI26_PCIELINK3_EVTCODE_TLP_ECRC_ERROR_DETECTED (0x06) 4023 #define MPI26_PCIELINK3_EVTCODE_POISONED_TLP (0x07) 4024 #define MPI26_PCIELINK3_EVTCODE_RECEIVED_NAK_DLLP (0x08) 4025 #define MPI26_PCIELINK3_EVTCODE_SENT_NAK_DLLP (0x09) 4026 #define MPI26_PCIELINK3_EVTCODE_LTSSM_RECOVERY_STATE (0x0A) 4027 #define MPI26_PCIELINK3_EVTCODE_LTSSM_RXL0S_STATE (0x0B) 4028 #define MPI26_PCIELINK3_EVTCODE_LTSSM_TXL0S_STATE (0x0C) 4029 #define MPI26_PCIELINK3_EVTCODE_LTSSM_L1_STATE (0x0D) 4030 #define MPI26_PCIELINK3_EVTCODE_LTSSM_DISABLED_STATE (0x0E) 4031 #define MPI26_PCIELINK3_EVTCODE_LTSSM_HOT_RESET_STATE (0x0F) 4032 #define MPI26_PCIELINK3_EVTCODE_SYSTEM_ERROR (0x10) 4033 #define MPI26_PCIELINK3_EVTCODE_DECODE_ERROR (0x11) 4034 #define MPI26_PCIELINK3_EVTCODE_DISPARITY_ERROR (0x12) 4035 4036 /*values for the CounterType field */ 4037 #define MPI26_PCIELINK3_COUNTER_TYPE_WRAPPING (0x00) 4038 #define MPI26_PCIELINK3_COUNTER_TYPE_SATURATING (0x01) 4039 #define MPI26_PCIELINK3_COUNTER_TYPE_PEAK_VALUE (0x02) 4040 4041 /*values for the TimeUnits field */ 4042 #define MPI26_PCIELINK3_TM_UNITS_10_MICROSECONDS (0x00) 4043 #define MPI26_PCIELINK3_TM_UNITS_100_MICROSECONDS (0x01) 4044 #define MPI26_PCIELINK3_TM_UNITS_1_MILLISECOND (0x02) 4045 #define MPI26_PCIELINK3_TM_UNITS_10_MILLISECONDS (0x03) 4046 4047 /*values for the ThresholdFlags field */ 4048 #define MPI26_PCIELINK3_TFLAGS_EVENT_NOTIFY (0x0001) 4049 4050 /* 4051 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 4052 *one and check the value returned for NumLinkEvents at runtime. 4053 */ 4054 #ifndef MPI26_PCIELINK3_LINK_EVENT_MAX 4055 #define MPI26_PCIELINK3_LINK_EVENT_MAX (1) 4056 #endif 4057 4058 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_3 { 4059 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 4060 U8 Link; /*0x08 */ 4061 U8 Reserved1; /*0x09 */ 4062 U16 Reserved2; /*0x0A */ 4063 U8 NumLinkEvents; /*0x0C */ 4064 U8 Reserved3; /*0x0D */ 4065 U16 Reserved4; /*0x0E */ 4066 MPI26_PCIELINK3_LINK_EVENT_CONFIG 4067 LinkEventConfig[MPI26_PCIELINK3_LINK_EVENT_MAX]; /*0x10 */ 4068 } MPI26_CONFIG_PAGE_PCIELINK_3, *PTR_MPI26_CONFIG_PAGE_PCIELINK_3, 4069 Mpi26PcieLinkPage3_t, *pMpi26PcieLinkPage3_t; 4070 4071 #define MPI26_PCIELINK3_PAGEVERSION (0x00) 4072 4073 4074 #endif 4075