1 /* 2 * Copyright 2000-2015 Avago Technologies. All rights reserved. 3 * 4 * 5 * Name: mpi2_cnfg.h 6 * Title: MPI Configuration messages and pages 7 * Creation Date: November 10, 2006 8 * 9 * mpi2_cnfg.h Version: 02.00.35 10 * 11 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 12 * prefix are for use only on MPI v2.5 products, and must not be used 13 * with MPI v2.0 products. Unless otherwise noted, names beginning with 14 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 15 * 16 * Version History 17 * --------------- 18 * 19 * Date Version Description 20 * -------- -------- ------------------------------------------------------ 21 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 22 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags. 23 * Added Manufacturing Page 11. 24 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE 25 * define. 26 * 06-26-07 02.00.02 Adding generic structure for product-specific 27 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS. 28 * Rework of BIOS Page 2 configuration page. 29 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the 30 * forms. 31 * Added configuration pages IOC Page 8 and Driver 32 * Persistent Mapping Page 0. 33 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated 34 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1, 35 * RAID Physical Disk Pages 0 and 1, RAID Configuration 36 * Page 0). 37 * Added new value for AccessStatus field of SAS Device 38 * Page 0 (_SATA_NEEDS_INITIALIZATION). 39 * 10-31-07 02.00.04 Added missing SEPDevHandle field to 40 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 41 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for 42 * NVDATA. 43 * Modified IOC Page 7 to use masks and added field for 44 * SASBroadcastPrimitiveMasks. 45 * Added MPI2_CONFIG_PAGE_BIOS_4. 46 * Added MPI2_CONFIG_PAGE_LOG_0. 47 * 02-29-08 02.00.06 Modified various names to make them 32-character unique. 48 * Added SAS Device IDs. 49 * Updated Integrated RAID configuration pages including 50 * Manufacturing Page 4, IOC Page 6, and RAID Configuration 51 * Page 0. 52 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA. 53 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION. 54 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING. 55 * Added missing MaxNumRoutedSasAddresses field to 56 * MPI2_CONFIG_PAGE_EXPANDER_0. 57 * Added SAS Port Page 0. 58 * Modified structure layout for 59 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0. 60 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use 61 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array. 62 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF 63 * to 0x000000FF. 64 * Added two new values for the Physical Disk Coercion Size 65 * bits in the Flags field of Manufacturing Page 4. 66 * Added product-specific Manufacturing pages 16 to 31. 67 * Modified Flags bits for controlling write cache on SATA 68 * drives in IO Unit Page 1. 69 * Added new bit to AdditionalControlFlags of SAS IO Unit 70 * Page 1 to control Invalid Topology Correction. 71 * Added additional defines for RAID Volume Page 0 72 * VolumeStatusFlags field. 73 * Modified meaning of RAID Volume Page 0 VolumeSettings 74 * define for auto-configure of hot-swap drives. 75 * Added SupportedPhysDisks field to RAID Volume Page 1 and 76 * added related defines. 77 * Added PhysDiskAttributes field (and related defines) to 78 * RAID Physical Disk Page 0. 79 * Added MPI2_SAS_PHYINFO_PHY_VACANT define. 80 * Added three new DiscoveryStatus bits for SAS IO Unit 81 * Page 0 and SAS Expander Page 0. 82 * Removed multiplexing information from SAS IO Unit pages. 83 * Added BootDeviceWaitTime field to SAS IO Unit Page 4. 84 * Removed Zone Address Resolved bit from PhyInfo and from 85 * Expander Page 0 Flags field. 86 * Added two new AccessStatus values to SAS Device Page 0 87 * for indicating routing problems. Added 3 reserved words 88 * to this page. 89 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3. 90 * Inserted missing reserved field into structure for IOC 91 * Page 6. 92 * Added more pending task bits to RAID Volume Page 0 93 * VolumeStatusFlags defines. 94 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define. 95 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0 96 * and SAS Expander Page 0 to flag a downstream initiator 97 * when in simplified routing mode. 98 * Removed SATA Init Failure defines for DiscoveryStatus 99 * fields of SAS IO Unit Page 0 and SAS Expander Page 0. 100 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define. 101 * Added PortGroups, DmaGroup, and ControlGroup fields to 102 * SAS Device Page 0. 103 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO 104 * Unit Page 6. 105 * Added expander reduced functionality data to SAS 106 * Expander Page 0. 107 * Added SAS PHY Page 2 and SAS PHY Page 3. 108 * 07-30-09 02.00.12 Added IO Unit Page 7. 109 * Added new device ids. 110 * Added SAS IO Unit Page 5. 111 * Added partial and slumber power management capable flags 112 * to SAS Device Page 0 Flags field. 113 * Added PhyInfo defines for power condition. 114 * Added Ethernet configuration pages. 115 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY. 116 * Added SAS PHY Page 4 structure and defines. 117 * 02-10-10 02.00.14 Modified the comments for the configuration page 118 * structures that contain an array of data. The host 119 * should use the "count" field in the page data (e.g. the 120 * NumPhys field) to determine the number of valid elements 121 * in the array. 122 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines. 123 * Added PowerManagementCapabilities to IO Unit Page 7. 124 * Added PortWidthModGroup field to 125 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS. 126 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines. 127 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines. 128 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines. 129 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT 130 * define. 131 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define. 132 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define. 133 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing) 134 * defines. 135 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to 136 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for 137 * the Pinout field. 138 * Added BoardTemperature and BoardTemperatureUnits fields 139 * to MPI2_CONFIG_PAGE_IO_UNIT_7. 140 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define 141 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure. 142 * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST. 143 * Added IO Unit Page 8, IO Unit Page 9, 144 * and IO Unit Page 10. 145 * Added SASNotifyPrimitiveMasks field to 146 * MPI2_CONFIG_PAGE_IOC_7. 147 * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec). 148 * 05-25-11 02.00.20 Cleaned up a few comments. 149 * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities 150 * for PCIe link as obsolete. 151 * Added SpinupFlags field containing a Disable Spin-up bit 152 * to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO 153 * Unit Page 4. 154 * 11-18-11 02.00.22 Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT. 155 * Added UEFIVersion field to BIOS Page 1 and defined new 156 * BiosOptions bits. 157 * Incorporating additions for MPI v2.5. 158 * 11-27-12 02.00.23 Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER. 159 * Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID. 160 * 12-20-12 02.00.24 Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as 161 * obsolete for MPI v2.5 and later. 162 * Added some defines for 12G SAS speeds. 163 * 04-09-13 02.00.25 Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK. 164 * Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to 165 * match the specification. 166 * 08-19-13 02.00.26 Added reserved words to MPI2_CONFIG_PAGE_IO_UNIT_7 for 167 * future use. 168 * 12-05-13 02.00.27 Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for 169 * MPI2_CONFIG_PAGE_MAN_7. 170 * Added EnclosureLevel and ConnectorName fields to 171 * MPI2_CONFIG_PAGE_SAS_DEV_0. 172 * Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for 173 * MPI2_CONFIG_PAGE_SAS_DEV_0. 174 * Added EnclosureLevel field to 175 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 176 * Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for 177 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 178 * 01-08-14 02.00.28 Added more defines for the BiosOptions field of 179 * MPI2_CONFIG_PAGE_BIOS_1. 180 * 06-13-14 02.00.29 Added SSUTimeout field to MPI2_CONFIG_PAGE_BIOS_1, and 181 * more defines for the BiosOptions field. 182 * 11-18-14 02.00.30 Updated copyright information. 183 * Added MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG. 184 * Added AdapterOrderAux fields to BIOS Page 3. 185 * 03-16-15 02.00.31 Updated for MPI v2.6. 186 * Added Flags field to IO Unit Page 7. 187 * Added new SAS Phy Event codes 188 * 05-25-15 02.00.33 Added more defines for the BiosOptions field of 189 * MPI2_CONFIG_PAGE_BIOS_1. 190 * 08-25-15 02.00.34 Bumped Header Version. 191 * 12-18-15 02.00.35 Added SATADeviceWaitTime to SAS IO Unit Page 4. 192 * -------------------------------------------------------------------------- 193 */ 194 195 #ifndef MPI2_CNFG_H 196 #define MPI2_CNFG_H 197 198 /***************************************************************************** 199 * Configuration Page Header and defines 200 *****************************************************************************/ 201 202 /*Config Page Header */ 203 typedef struct _MPI2_CONFIG_PAGE_HEADER { 204 U8 PageVersion; /*0x00 */ 205 U8 PageLength; /*0x01 */ 206 U8 PageNumber; /*0x02 */ 207 U8 PageType; /*0x03 */ 208 } MPI2_CONFIG_PAGE_HEADER, *PTR_MPI2_CONFIG_PAGE_HEADER, 209 Mpi2ConfigPageHeader_t, *pMpi2ConfigPageHeader_t; 210 211 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION { 212 MPI2_CONFIG_PAGE_HEADER Struct; 213 U8 Bytes[4]; 214 U16 Word16[2]; 215 U32 Word32; 216 } MPI2_CONFIG_PAGE_HEADER_UNION, *PTR_MPI2_CONFIG_PAGE_HEADER_UNION, 217 Mpi2ConfigPageHeaderUnion, *pMpi2ConfigPageHeaderUnion; 218 219 /*Extended Config Page Header */ 220 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER { 221 U8 PageVersion; /*0x00 */ 222 U8 Reserved1; /*0x01 */ 223 U8 PageNumber; /*0x02 */ 224 U8 PageType; /*0x03 */ 225 U16 ExtPageLength; /*0x04 */ 226 U8 ExtPageType; /*0x06 */ 227 U8 Reserved2; /*0x07 */ 228 } MPI2_CONFIG_EXTENDED_PAGE_HEADER, 229 *PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER, 230 Mpi2ConfigExtendedPageHeader_t, 231 *pMpi2ConfigExtendedPageHeader_t; 232 233 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION { 234 MPI2_CONFIG_PAGE_HEADER Struct; 235 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext; 236 U8 Bytes[8]; 237 U16 Word16[4]; 238 U32 Word32[2]; 239 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 240 *PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 241 Mpi2ConfigPageExtendedHeaderUnion, 242 *pMpi2ConfigPageExtendedHeaderUnion; 243 244 245 /*PageType field values */ 246 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 247 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 248 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 249 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0) 250 251 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00) 252 #define MPI2_CONFIG_PAGETYPE_IOC (0x01) 253 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02) 254 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 255 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09) 256 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 257 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F) 258 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F) 259 260 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF) 261 262 263 /*ExtPageType field values */ 264 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 265 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 266 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 267 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 268 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14) 269 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 270 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 271 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 272 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 273 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19) 274 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A) 275 276 277 /***************************************************************************** 278 * PageAddress defines 279 *****************************************************************************/ 280 281 /*RAID Volume PageAddress format */ 282 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000) 283 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 284 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000) 285 286 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF) 287 288 289 /*RAID Physical Disk PageAddress format */ 290 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000) 291 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000) 292 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000) 293 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000) 294 295 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 296 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF) 297 298 299 /*SAS Expander PageAddress format */ 300 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 301 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 302 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000) 303 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000) 304 305 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) 306 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) 307 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 308 309 310 /*SAS Device PageAddress format */ 311 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 312 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 313 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000) 314 315 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 316 317 318 /*SAS PHY PageAddress format */ 319 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 320 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 321 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000) 322 323 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 324 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 325 326 327 /*SAS Port PageAddress format */ 328 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000) 329 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 330 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 331 332 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF) 333 334 335 /*SAS Enclosure PageAddress format */ 336 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 337 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 338 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 339 340 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 341 342 343 /*RAID Configuration PageAddress format */ 344 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000) 345 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000) 346 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000) 347 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000) 348 349 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF) 350 351 352 /*Driver Persistent Mapping PageAddress format */ 353 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000) 354 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000) 355 356 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000) 357 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16) 358 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF) 359 360 361 /*Ethernet PageAddress format */ 362 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000) 363 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000) 364 365 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF) 366 367 368 /**************************************************************************** 369 * Configuration messages 370 ****************************************************************************/ 371 372 /*Configuration Request Message */ 373 typedef struct _MPI2_CONFIG_REQUEST { 374 U8 Action; /*0x00 */ 375 U8 SGLFlags; /*0x01 */ 376 U8 ChainOffset; /*0x02 */ 377 U8 Function; /*0x03 */ 378 U16 ExtPageLength; /*0x04 */ 379 U8 ExtPageType; /*0x06 */ 380 U8 MsgFlags; /*0x07 */ 381 U8 VP_ID; /*0x08 */ 382 U8 VF_ID; /*0x09 */ 383 U16 Reserved1; /*0x0A */ 384 U8 Reserved2; /*0x0C */ 385 U8 ProxyVF_ID; /*0x0D */ 386 U16 Reserved4; /*0x0E */ 387 U32 Reserved3; /*0x10 */ 388 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */ 389 U32 PageAddress; /*0x18 */ 390 MPI2_SGE_IO_UNION PageBufferSGE; /*0x1C */ 391 } MPI2_CONFIG_REQUEST, *PTR_MPI2_CONFIG_REQUEST, 392 Mpi2ConfigRequest_t, *pMpi2ConfigRequest_t; 393 394 /*values for the Action field */ 395 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00) 396 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 397 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 398 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03) 399 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 400 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 401 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 402 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07) 403 404 /*use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */ 405 406 407 /*Config Reply Message */ 408 typedef struct _MPI2_CONFIG_REPLY { 409 U8 Action; /*0x00 */ 410 U8 SGLFlags; /*0x01 */ 411 U8 MsgLength; /*0x02 */ 412 U8 Function; /*0x03 */ 413 U16 ExtPageLength; /*0x04 */ 414 U8 ExtPageType; /*0x06 */ 415 U8 MsgFlags; /*0x07 */ 416 U8 VP_ID; /*0x08 */ 417 U8 VF_ID; /*0x09 */ 418 U16 Reserved1; /*0x0A */ 419 U16 Reserved2; /*0x0C */ 420 U16 IOCStatus; /*0x0E */ 421 U32 IOCLogInfo; /*0x10 */ 422 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */ 423 } MPI2_CONFIG_REPLY, *PTR_MPI2_CONFIG_REPLY, 424 Mpi2ConfigReply_t, *pMpi2ConfigReply_t; 425 426 427 428 /***************************************************************************** 429 * 430 * C o n f i g u r a t i o n P a g e s 431 * 432 *****************************************************************************/ 433 434 /**************************************************************************** 435 * Manufacturing Config pages 436 ****************************************************************************/ 437 438 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000) 439 440 /*MPI v2.0 SAS products */ 441 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070) 442 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072) 443 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074) 444 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076) 445 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077) 446 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064) 447 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065) 448 449 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E) 450 451 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080) 452 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081) 453 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082) 454 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083) 455 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084) 456 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085) 457 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086) 458 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087) 459 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E) 460 461 /*MPI v2.5 SAS products */ 462 #define MPI25_MFGPAGE_DEVID_SAS3004 (0x0096) 463 #define MPI25_MFGPAGE_DEVID_SAS3008 (0x0097) 464 #define MPI25_MFGPAGE_DEVID_SAS3108_1 (0x0090) 465 #define MPI25_MFGPAGE_DEVID_SAS3108_2 (0x0091) 466 #define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094) 467 #define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095) 468 469 /* MPI v2.6 SAS Products */ 470 #define MPI26_MFGPAGE_DEVID_SAS3216 (0x00C9) 471 #define MPI26_MFGPAGE_DEVID_SAS3224 (0x00C4) 472 #define MPI26_MFGPAGE_DEVID_SAS3316_1 (0x00C5) 473 #define MPI26_MFGPAGE_DEVID_SAS3316_2 (0x00C6) 474 #define MPI26_MFGPAGE_DEVID_SAS3316_3 (0x00C7) 475 #define MPI26_MFGPAGE_DEVID_SAS3316_4 (0x00C8) 476 #define MPI26_MFGPAGE_DEVID_SAS3324_1 (0x00C0) 477 #define MPI26_MFGPAGE_DEVID_SAS3324_2 (0x00C1) 478 #define MPI26_MFGPAGE_DEVID_SAS3324_3 (0x00C2) 479 #define MPI26_MFGPAGE_DEVID_SAS3324_4 (0x00C3) 480 481 #define MPI26_MFGPAGE_DEVID_SAS3516 (0x00AA) 482 #define MPI26_MFGPAGE_DEVID_SAS3516_1 (0x00AB) 483 #define MPI26_MFGPAGE_DEVID_SAS3416 (0x00AC) 484 #define MPI26_MFGPAGE_DEVID_SAS3508 (0x00AD) 485 #define MPI26_MFGPAGE_DEVID_SAS3508_1 (0x00AE) 486 #define MPI26_MFGPAGE_DEVID_SAS3408 (0x00AF) 487 488 /*Manufacturing Page 0 */ 489 490 typedef struct _MPI2_CONFIG_PAGE_MAN_0 { 491 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 492 U8 ChipName[16]; /*0x04 */ 493 U8 ChipRevision[8]; /*0x14 */ 494 U8 BoardName[16]; /*0x1C */ 495 U8 BoardAssembly[16]; /*0x2C */ 496 U8 BoardTracerNumber[16]; /*0x3C */ 497 } MPI2_CONFIG_PAGE_MAN_0, 498 *PTR_MPI2_CONFIG_PAGE_MAN_0, 499 Mpi2ManufacturingPage0_t, 500 *pMpi2ManufacturingPage0_t; 501 502 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00) 503 504 505 /*Manufacturing Page 1 */ 506 507 typedef struct _MPI2_CONFIG_PAGE_MAN_1 { 508 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 509 U8 VPD[256]; /*0x04 */ 510 } MPI2_CONFIG_PAGE_MAN_1, 511 *PTR_MPI2_CONFIG_PAGE_MAN_1, 512 Mpi2ManufacturingPage1_t, 513 *pMpi2ManufacturingPage1_t; 514 515 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00) 516 517 518 typedef struct _MPI2_CHIP_REVISION_ID { 519 U16 DeviceID; /*0x00 */ 520 U8 PCIRevisionID; /*0x02 */ 521 U8 Reserved; /*0x03 */ 522 } MPI2_CHIP_REVISION_ID, *PTR_MPI2_CHIP_REVISION_ID, 523 Mpi2ChipRevisionId_t, *pMpi2ChipRevisionId_t; 524 525 526 /*Manufacturing Page 2 */ 527 528 /* 529 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 530 *one and check Header.PageLength at runtime. 531 */ 532 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS 533 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 534 #endif 535 536 typedef struct _MPI2_CONFIG_PAGE_MAN_2 { 537 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 538 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */ 539 U32 540 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/*0x08 */ 541 } MPI2_CONFIG_PAGE_MAN_2, 542 *PTR_MPI2_CONFIG_PAGE_MAN_2, 543 Mpi2ManufacturingPage2_t, 544 *pMpi2ManufacturingPage2_t; 545 546 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00) 547 548 549 /*Manufacturing Page 3 */ 550 551 /* 552 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 553 *one and check Header.PageLength at runtime. 554 */ 555 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS 556 #define MPI2_MAN_PAGE_3_INFO_WORDS (1) 557 #endif 558 559 typedef struct _MPI2_CONFIG_PAGE_MAN_3 { 560 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 561 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */ 562 U32 563 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/*0x08 */ 564 } MPI2_CONFIG_PAGE_MAN_3, 565 *PTR_MPI2_CONFIG_PAGE_MAN_3, 566 Mpi2ManufacturingPage3_t, 567 *pMpi2ManufacturingPage3_t; 568 569 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00) 570 571 572 /*Manufacturing Page 4 */ 573 574 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS { 575 U8 PowerSaveFlags; /*0x00 */ 576 U8 InternalOperationsSleepTime; /*0x01 */ 577 U8 InternalOperationsRunTime; /*0x02 */ 578 U8 HostIdleTime; /*0x03 */ 579 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 580 *PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 581 Mpi2ManPage4PwrSaveSettings_t, 582 *pMpi2ManPage4PwrSaveSettings_t; 583 584 /*defines for the PowerSaveFlags field */ 585 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03) 586 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00) 587 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01) 588 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02) 589 590 typedef struct _MPI2_CONFIG_PAGE_MAN_4 { 591 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 592 U32 Reserved1; /*0x04 */ 593 U32 Flags; /*0x08 */ 594 U8 InquirySize; /*0x0C */ 595 U8 Reserved2; /*0x0D */ 596 U16 Reserved3; /*0x0E */ 597 U8 InquiryData[56]; /*0x10 */ 598 U32 RAID0VolumeSettings; /*0x48 */ 599 U32 RAID1EVolumeSettings; /*0x4C */ 600 U32 RAID1VolumeSettings; /*0x50 */ 601 U32 RAID10VolumeSettings; /*0x54 */ 602 U32 Reserved4; /*0x58 */ 603 U32 Reserved5; /*0x5C */ 604 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /*0x60 */ 605 U8 MaxOCEDisks; /*0x64 */ 606 U8 ResyncRate; /*0x65 */ 607 U16 DataScrubDuration; /*0x66 */ 608 U8 MaxHotSpares; /*0x68 */ 609 U8 MaxPhysDisksPerVol; /*0x69 */ 610 U8 MaxPhysDisks; /*0x6A */ 611 U8 MaxVolumes; /*0x6B */ 612 } MPI2_CONFIG_PAGE_MAN_4, 613 *PTR_MPI2_CONFIG_PAGE_MAN_4, 614 Mpi2ManufacturingPage4_t, 615 *pMpi2ManufacturingPage4_t; 616 617 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A) 618 619 /*Manufacturing Page 4 Flags field */ 620 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000) 621 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000) 622 623 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000) 624 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000) 625 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000) 626 627 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00) 628 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000) 629 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400) 630 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800) 631 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00) 632 633 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300) 634 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000) 635 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100) 636 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200) 637 638 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080) 639 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040) 640 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020) 641 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010) 642 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008) 643 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004) 644 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002) 645 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001) 646 647 648 /*Manufacturing Page 5 */ 649 650 /* 651 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 652 *one and check the value returned for NumPhys at runtime. 653 */ 654 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES 655 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1) 656 #endif 657 658 typedef struct _MPI2_MANUFACTURING5_ENTRY { 659 U64 WWID; /*0x00 */ 660 U64 DeviceName; /*0x08 */ 661 } MPI2_MANUFACTURING5_ENTRY, 662 *PTR_MPI2_MANUFACTURING5_ENTRY, 663 Mpi2Manufacturing5Entry_t, 664 *pMpi2Manufacturing5Entry_t; 665 666 typedef struct _MPI2_CONFIG_PAGE_MAN_5 { 667 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 668 U8 NumPhys; /*0x04 */ 669 U8 Reserved1; /*0x05 */ 670 U16 Reserved2; /*0x06 */ 671 U32 Reserved3; /*0x08 */ 672 U32 Reserved4; /*0x0C */ 673 MPI2_MANUFACTURING5_ENTRY 674 Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/*0x08 */ 675 } MPI2_CONFIG_PAGE_MAN_5, 676 *PTR_MPI2_CONFIG_PAGE_MAN_5, 677 Mpi2ManufacturingPage5_t, 678 *pMpi2ManufacturingPage5_t; 679 680 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03) 681 682 683 /*Manufacturing Page 6 */ 684 685 typedef struct _MPI2_CONFIG_PAGE_MAN_6 { 686 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 687 U32 ProductSpecificInfo;/*0x04 */ 688 } MPI2_CONFIG_PAGE_MAN_6, 689 *PTR_MPI2_CONFIG_PAGE_MAN_6, 690 Mpi2ManufacturingPage6_t, 691 *pMpi2ManufacturingPage6_t; 692 693 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00) 694 695 696 /*Manufacturing Page 7 */ 697 698 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO { 699 U32 Pinout; /*0x00 */ 700 U8 Connector[16]; /*0x04 */ 701 U8 Location; /*0x14 */ 702 U8 ReceptacleID; /*0x15 */ 703 U16 Slot; /*0x16 */ 704 U32 Reserved2; /*0x18 */ 705 } MPI2_MANPAGE7_CONNECTOR_INFO, 706 *PTR_MPI2_MANPAGE7_CONNECTOR_INFO, 707 Mpi2ManPage7ConnectorInfo_t, 708 *pMpi2ManPage7ConnectorInfo_t; 709 710 /*defines for the Pinout field */ 711 #define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00) 712 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8) 713 714 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF) 715 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00) 716 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01) 717 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02) 718 #define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03) 719 #define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04) 720 #define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05) 721 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06) 722 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07) 723 #define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08) 724 #define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09) 725 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A) 726 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B) 727 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C) 728 #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D) 729 730 /*defines for the Location field */ 731 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01) 732 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02) 733 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04) 734 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08) 735 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10) 736 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 737 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 738 739 /* 740 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 741 *one and check the value returned for NumPhys at runtime. 742 */ 743 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX 744 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1) 745 #endif 746 747 typedef struct _MPI2_CONFIG_PAGE_MAN_7 { 748 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 749 U32 Reserved1; /*0x04 */ 750 U32 Reserved2; /*0x08 */ 751 U32 Flags; /*0x0C */ 752 U8 EnclosureName[16]; /*0x10 */ 753 U8 NumPhys; /*0x20 */ 754 U8 Reserved3; /*0x21 */ 755 U16 Reserved4; /*0x22 */ 756 MPI2_MANPAGE7_CONNECTOR_INFO 757 ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /*0x24 */ 758 } MPI2_CONFIG_PAGE_MAN_7, 759 *PTR_MPI2_CONFIG_PAGE_MAN_7, 760 Mpi2ManufacturingPage7_t, 761 *pMpi2ManufacturingPage7_t; 762 763 #define MPI2_MANUFACTURING7_PAGEVERSION (0x01) 764 765 /*defines for the Flags field */ 766 #define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL (0x00000008) 767 #define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER (0x00000002) 768 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 769 770 771 /* 772 *Generic structure to use for product-specific manufacturing pages 773 *(currently Manufacturing Page 8 through Manufacturing Page 31). 774 */ 775 776 typedef struct _MPI2_CONFIG_PAGE_MAN_PS { 777 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 778 U32 ProductSpecificInfo;/*0x04 */ 779 } MPI2_CONFIG_PAGE_MAN_PS, 780 *PTR_MPI2_CONFIG_PAGE_MAN_PS, 781 Mpi2ManufacturingPagePS_t, 782 *pMpi2ManufacturingPagePS_t; 783 784 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00) 785 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00) 786 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00) 787 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00) 788 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00) 789 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00) 790 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00) 791 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00) 792 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00) 793 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00) 794 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00) 795 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00) 796 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00) 797 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00) 798 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00) 799 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00) 800 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00) 801 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00) 802 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00) 803 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00) 804 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00) 805 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00) 806 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00) 807 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00) 808 809 810 /**************************************************************************** 811 * IO Unit Config Pages 812 ****************************************************************************/ 813 814 /*IO Unit Page 0 */ 815 816 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 { 817 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 818 U64 UniqueValue; /*0x04 */ 819 MPI2_VERSION_UNION NvdataVersionDefault; /*0x08 */ 820 MPI2_VERSION_UNION NvdataVersionPersistent; /*0x0A */ 821 } MPI2_CONFIG_PAGE_IO_UNIT_0, 822 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_0, 823 Mpi2IOUnitPage0_t, *pMpi2IOUnitPage0_t; 824 825 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02) 826 827 828 /*IO Unit Page 1 */ 829 830 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 { 831 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 832 U32 Flags; /*0x04 */ 833 } MPI2_CONFIG_PAGE_IO_UNIT_1, 834 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_1, 835 Mpi2IOUnitPage1_t, *pMpi2IOUnitPage1_t; 836 837 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04) 838 839 /*IO Unit Page 1 Flags defines */ 840 #define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK (0x00004000) 841 #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000) 842 #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000) 843 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800) 844 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600) 845 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9) 846 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000) 847 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200) 848 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400) 849 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 850 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040) 851 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020) 852 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 853 854 855 /*IO Unit Page 3 */ 856 857 /* 858 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 859 *one and check the value returned for GPIOCount at runtime. 860 */ 861 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX 862 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 863 #endif 864 865 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 { 866 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 867 U8 GPIOCount; /*0x04 */ 868 U8 Reserved1; /*0x05 */ 869 U16 Reserved2; /*0x06 */ 870 U16 871 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/*0x08 */ 872 } MPI2_CONFIG_PAGE_IO_UNIT_3, 873 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_3, 874 Mpi2IOUnitPage3_t, *pMpi2IOUnitPage3_t; 875 876 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01) 877 878 /*defines for IO Unit Page 3 GPIOVal field */ 879 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC) 880 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 881 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000) 882 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001) 883 884 885 /*IO Unit Page 5 */ 886 887 /* 888 *Upper layer code (drivers, utilities, etc.) should leave this define set to 889 *one and check the value returned for NumDmaEngines at runtime. 890 */ 891 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES 892 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1) 893 #endif 894 895 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 { 896 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 897 U64 898 RaidAcceleratorBufferBaseAddress; /*0x04 */ 899 U64 900 RaidAcceleratorBufferSize; /*0x0C */ 901 U64 902 RaidAcceleratorControlBaseAddress; /*0x14 */ 903 U8 RAControlSize; /*0x1C */ 904 U8 NumDmaEngines; /*0x1D */ 905 U8 RAMinControlSize; /*0x1E */ 906 U8 RAMaxControlSize; /*0x1F */ 907 U32 Reserved1; /*0x20 */ 908 U32 Reserved2; /*0x24 */ 909 U32 Reserved3; /*0x28 */ 910 U32 911 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /*0x2C */ 912 } MPI2_CONFIG_PAGE_IO_UNIT_5, 913 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_5, 914 Mpi2IOUnitPage5_t, *pMpi2IOUnitPage5_t; 915 916 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00) 917 918 /*defines for IO Unit Page 5 DmaEngineCapabilities field */ 919 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFFFF0000) 920 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16) 921 922 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008) 923 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004) 924 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002) 925 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001) 926 927 928 /*IO Unit Page 6 */ 929 930 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 { 931 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 932 U16 Flags; /*0x04 */ 933 U8 RAHostControlSize; /*0x06 */ 934 U8 Reserved0; /*0x07 */ 935 U64 936 RaidAcceleratorHostControlBaseAddress; /*0x08 */ 937 U32 Reserved1; /*0x10 */ 938 U32 Reserved2; /*0x14 */ 939 U32 Reserved3; /*0x18 */ 940 } MPI2_CONFIG_PAGE_IO_UNIT_6, 941 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_6, 942 Mpi2IOUnitPage6_t, *pMpi2IOUnitPage6_t; 943 944 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00) 945 946 /*defines for IO Unit Page 6 Flags field */ 947 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001) 948 949 950 /*IO Unit Page 7 */ 951 952 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 { 953 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 954 U8 CurrentPowerMode; /*0x04 */ 955 U8 PreviousPowerMode; /*0x05 */ 956 U8 PCIeWidth; /*0x06 */ 957 U8 PCIeSpeed; /*0x07 */ 958 U32 ProcessorState; /*0x08 */ 959 U32 960 PowerManagementCapabilities; /*0x0C */ 961 U16 IOCTemperature; /*0x10 */ 962 U8 963 IOCTemperatureUnits; /*0x12 */ 964 U8 IOCSpeed; /*0x13 */ 965 U16 BoardTemperature; /*0x14 */ 966 U8 967 BoardTemperatureUnits; /*0x16 */ 968 U8 Reserved3; /*0x17 */ 969 U32 BoardPowerRequirement; /*0x18 */ 970 U32 PCISlotPowerAllocation; /*0x1C */ 971 /* reserved prior to MPI v2.6 */ 972 U8 Flags; /* 0x20 */ 973 U8 Reserved6; /* 0x21 */ 974 U16 Reserved7; /* 0x22 */ 975 U32 Reserved8; /* 0x24 */ 976 } MPI2_CONFIG_PAGE_IO_UNIT_7, 977 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_7, 978 Mpi2IOUnitPage7_t, *pMpi2IOUnitPage7_t; 979 980 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x05) 981 982 /*defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */ 983 #define MPI25_IOUNITPAGE7_PM_INIT_MASK (0xC0) 984 #define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE (0x00) 985 #define MPI25_IOUNITPAGE7_PM_INIT_HOST (0x40) 986 #define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT (0x80) 987 #define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA (0xC0) 988 989 #define MPI25_IOUNITPAGE7_PM_MODE_MASK (0x07) 990 #define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE (0x00) 991 #define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN (0x01) 992 #define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER (0x04) 993 #define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER (0x05) 994 #define MPI25_IOUNITPAGE7_PM_MODE_STANDBY (0x06) 995 996 997 /*defines for IO Unit Page 7 PCIeWidth field */ 998 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01) 999 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02) 1000 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04) 1001 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08) 1002 1003 /*defines for IO Unit Page 7 PCIeSpeed field */ 1004 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00) 1005 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01) 1006 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02) 1007 1008 /*defines for IO Unit Page 7 ProcessorState field */ 1009 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F) 1010 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0) 1011 1012 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00) 1013 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01) 1014 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02) 1015 1016 /*defines for IO Unit Page 7 PowerManagementCapabilities field */ 1017 #define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE (0x00400000) 1018 #define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE (0x00200000) 1019 #define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE (0x00100000) 1020 #define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE (0x00040000) 1021 #define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE (0x00020000) 1022 #define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE (0x00010000) 1023 #define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE (0x00004000) 1024 #define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE (0x00002000) 1025 #define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE (0x00001000) 1026 #define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED (0x00000400) 1027 #define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED (0x00000200) 1028 #define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED (0x00000100) 1029 #define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED (0x00000040) 1030 #define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED (0x00000020) 1031 #define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED (0x00000010) 1032 #define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE (0x00000008) 1033 #define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE (0x00000004) 1034 #define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE (0x00000002) 1035 #define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE (0x00000001) 1036 1037 /*obsolete names for the PowerManagementCapabilities bits (above) */ 1038 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400) 1039 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200) 1040 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100) 1041 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /*obsolete */ 1042 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /*obsolete */ 1043 1044 1045 /*defines for IO Unit Page 7 IOCTemperatureUnits field */ 1046 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00) 1047 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01) 1048 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02) 1049 1050 /*defines for IO Unit Page 7 IOCSpeed field */ 1051 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01) 1052 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02) 1053 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04) 1054 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08) 1055 1056 /*defines for IO Unit Page 7 BoardTemperatureUnits field */ 1057 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00) 1058 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01) 1059 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02) 1060 1061 /* defines for IO Unit Page 7 Flags field */ 1062 #define MPI2_IOUNITPAGE7_FLAG_CABLE_POWER_EXC (0x01) 1063 1064 /*IO Unit Page 8 */ 1065 1066 #define MPI2_IOUNIT8_NUM_THRESHOLDS (4) 1067 1068 typedef struct _MPI2_IOUNIT8_SENSOR { 1069 U16 Flags; /*0x00 */ 1070 U16 Reserved1; /*0x02 */ 1071 U16 1072 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /*0x04 */ 1073 U32 Reserved2; /*0x0C */ 1074 U32 Reserved3; /*0x10 */ 1075 U32 Reserved4; /*0x14 */ 1076 } MPI2_IOUNIT8_SENSOR, *PTR_MPI2_IOUNIT8_SENSOR, 1077 Mpi2IOUnit8Sensor_t, *pMpi2IOUnit8Sensor_t; 1078 1079 /*defines for IO Unit Page 8 Sensor Flags field */ 1080 #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008) 1081 #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004) 1082 #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002) 1083 #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001) 1084 1085 /* 1086 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1087 *one and check the value returned for NumSensors at runtime. 1088 */ 1089 #ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES 1090 #define MPI2_IOUNITPAGE8_SENSOR_ENTRIES (1) 1091 #endif 1092 1093 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 { 1094 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1095 U32 Reserved1; /*0x04 */ 1096 U32 Reserved2; /*0x08 */ 1097 U8 NumSensors; /*0x0C */ 1098 U8 PollingInterval; /*0x0D */ 1099 U16 Reserved3; /*0x0E */ 1100 MPI2_IOUNIT8_SENSOR 1101 Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/*0x10 */ 1102 } MPI2_CONFIG_PAGE_IO_UNIT_8, 1103 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_8, 1104 Mpi2IOUnitPage8_t, *pMpi2IOUnitPage8_t; 1105 1106 #define MPI2_IOUNITPAGE8_PAGEVERSION (0x00) 1107 1108 1109 /*IO Unit Page 9 */ 1110 1111 typedef struct _MPI2_IOUNIT9_SENSOR { 1112 U16 CurrentTemperature; /*0x00 */ 1113 U16 Reserved1; /*0x02 */ 1114 U8 Flags; /*0x04 */ 1115 U8 Reserved2; /*0x05 */ 1116 U16 Reserved3; /*0x06 */ 1117 U32 Reserved4; /*0x08 */ 1118 U32 Reserved5; /*0x0C */ 1119 } MPI2_IOUNIT9_SENSOR, *PTR_MPI2_IOUNIT9_SENSOR, 1120 Mpi2IOUnit9Sensor_t, *pMpi2IOUnit9Sensor_t; 1121 1122 /*defines for IO Unit Page 9 Sensor Flags field */ 1123 #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01) 1124 1125 /* 1126 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1127 *one and check the value returned for NumSensors at runtime. 1128 */ 1129 #ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES 1130 #define MPI2_IOUNITPAGE9_SENSOR_ENTRIES (1) 1131 #endif 1132 1133 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 { 1134 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1135 U32 Reserved1; /*0x04 */ 1136 U32 Reserved2; /*0x08 */ 1137 U8 NumSensors; /*0x0C */ 1138 U8 Reserved4; /*0x0D */ 1139 U16 Reserved3; /*0x0E */ 1140 MPI2_IOUNIT9_SENSOR 1141 Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/*0x10 */ 1142 } MPI2_CONFIG_PAGE_IO_UNIT_9, 1143 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_9, 1144 Mpi2IOUnitPage9_t, *pMpi2IOUnitPage9_t; 1145 1146 #define MPI2_IOUNITPAGE9_PAGEVERSION (0x00) 1147 1148 1149 /*IO Unit Page 10 */ 1150 1151 typedef struct _MPI2_IOUNIT10_FUNCTION { 1152 U8 CreditPercent; /*0x00 */ 1153 U8 Reserved1; /*0x01 */ 1154 U16 Reserved2; /*0x02 */ 1155 } MPI2_IOUNIT10_FUNCTION, 1156 *PTR_MPI2_IOUNIT10_FUNCTION, 1157 Mpi2IOUnit10Function_t, 1158 *pMpi2IOUnit10Function_t; 1159 1160 /* 1161 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1162 *one and check the value returned for NumFunctions at runtime. 1163 */ 1164 #ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES 1165 #define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES (1) 1166 #endif 1167 1168 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 { 1169 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1170 U8 NumFunctions; /*0x04 */ 1171 U8 Reserved1; /*0x05 */ 1172 U16 Reserved2; /*0x06 */ 1173 U32 Reserved3; /*0x08 */ 1174 U32 Reserved4; /*0x0C */ 1175 MPI2_IOUNIT10_FUNCTION 1176 Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];/*0x10 */ 1177 } MPI2_CONFIG_PAGE_IO_UNIT_10, 1178 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_10, 1179 Mpi2IOUnitPage10_t, *pMpi2IOUnitPage10_t; 1180 1181 #define MPI2_IOUNITPAGE10_PAGEVERSION (0x01) 1182 1183 1184 /* IO Unit Page 11 (for MPI v2.6 and later) */ 1185 1186 typedef struct _MPI26_IOUNIT11_SPINUP_GROUP { 1187 U8 MaxTargetSpinup; /* 0x00 */ 1188 U8 SpinupDelay; /* 0x01 */ 1189 U8 SpinupFlags; /* 0x02 */ 1190 U8 Reserved1; /* 0x03 */ 1191 } MPI26_IOUNIT11_SPINUP_GROUP, 1192 *PTR_MPI26_IOUNIT11_SPINUP_GROUP, 1193 Mpi26IOUnit11SpinupGroup_t, 1194 *pMpi26IOUnit11SpinupGroup_t; 1195 1196 /* defines for IO Unit Page 11 SpinupFlags */ 1197 #define MPI26_IOUNITPAGE11_SPINUP_DISABLE_FLAG (0x01) 1198 1199 1200 /* 1201 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1202 * four and check the value returned for NumPhys at runtime. 1203 */ 1204 #ifndef MPI26_IOUNITPAGE11_PHY_MAX 1205 #define MPI26_IOUNITPAGE11_PHY_MAX (4) 1206 #endif 1207 1208 typedef struct _MPI26_CONFIG_PAGE_IO_UNIT_11 { 1209 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1210 U32 Reserved1; /*0x04 */ 1211 MPI26_IOUNIT11_SPINUP_GROUP SpinupGroupParameters[4]; /*0x08 */ 1212 U32 Reserved2; /*0x18 */ 1213 U32 Reserved3; /*0x1C */ 1214 U32 Reserved4; /*0x20 */ 1215 U8 BootDeviceWaitTime; /*0x24 */ 1216 U8 Reserved5; /*0x25 */ 1217 U16 Reserved6; /*0x26 */ 1218 U8 NumPhys; /*0x28 */ 1219 U8 PEInitialSpinupDelay; /*0x29 */ 1220 U8 PEReplyDelay; /*0x2A */ 1221 U8 Flags; /*0x2B */ 1222 U8 PHY[MPI26_IOUNITPAGE11_PHY_MAX];/*0x2C */ 1223 } MPI26_CONFIG_PAGE_IO_UNIT_11, 1224 *PTR_MPI26_CONFIG_PAGE_IO_UNIT_11, 1225 Mpi26IOUnitPage11_t, 1226 *pMpi26IOUnitPage11_t; 1227 1228 #define MPI26_IOUNITPAGE11_PAGEVERSION (0x00) 1229 1230 /* defines for Flags field */ 1231 #define MPI26_IOUNITPAGE11_FLAGS_AUTO_PORTENABLE (0x01) 1232 1233 /* defines for PHY field */ 1234 #define MPI26_IOUNITPAGE11_PHY_SPINUP_GROUP_MASK (0x03) 1235 1236 1237 1238 1239 1240 1241 /**************************************************************************** 1242 * IOC Config Pages 1243 ****************************************************************************/ 1244 1245 /*IOC Page 0 */ 1246 1247 typedef struct _MPI2_CONFIG_PAGE_IOC_0 { 1248 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1249 U32 Reserved1; /*0x04 */ 1250 U32 Reserved2; /*0x08 */ 1251 U16 VendorID; /*0x0C */ 1252 U16 DeviceID; /*0x0E */ 1253 U8 RevisionID; /*0x10 */ 1254 U8 Reserved3; /*0x11 */ 1255 U16 Reserved4; /*0x12 */ 1256 U32 ClassCode; /*0x14 */ 1257 U16 SubsystemVendorID; /*0x18 */ 1258 U16 SubsystemID; /*0x1A */ 1259 } MPI2_CONFIG_PAGE_IOC_0, 1260 *PTR_MPI2_CONFIG_PAGE_IOC_0, 1261 Mpi2IOCPage0_t, *pMpi2IOCPage0_t; 1262 1263 #define MPI2_IOCPAGE0_PAGEVERSION (0x02) 1264 1265 1266 /*IOC Page 1 */ 1267 1268 typedef struct _MPI2_CONFIG_PAGE_IOC_1 { 1269 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1270 U32 Flags; /*0x04 */ 1271 U32 CoalescingTimeout; /*0x08 */ 1272 U8 CoalescingDepth; /*0x0C */ 1273 U8 PCISlotNum; /*0x0D */ 1274 U8 PCIBusNum; /*0x0E */ 1275 U8 PCIDomainSegment; /*0x0F */ 1276 U32 Reserved1; /*0x10 */ 1277 U32 Reserved2; /*0x14 */ 1278 } MPI2_CONFIG_PAGE_IOC_1, 1279 *PTR_MPI2_CONFIG_PAGE_IOC_1, 1280 Mpi2IOCPage1_t, *pMpi2IOCPage1_t; 1281 1282 #define MPI2_IOCPAGE1_PAGEVERSION (0x05) 1283 1284 /*defines for IOC Page 1 Flags field */ 1285 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001) 1286 1287 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 1288 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF) 1289 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF) 1290 1291 /*IOC Page 6 */ 1292 1293 typedef struct _MPI2_CONFIG_PAGE_IOC_6 { 1294 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1295 U32 1296 CapabilitiesFlags; /*0x04 */ 1297 U8 MaxDrivesRAID0; /*0x08 */ 1298 U8 MaxDrivesRAID1; /*0x09 */ 1299 U8 1300 MaxDrivesRAID1E; /*0x0A */ 1301 U8 1302 MaxDrivesRAID10; /*0x0B */ 1303 U8 MinDrivesRAID0; /*0x0C */ 1304 U8 MinDrivesRAID1; /*0x0D */ 1305 U8 1306 MinDrivesRAID1E; /*0x0E */ 1307 U8 1308 MinDrivesRAID10; /*0x0F */ 1309 U32 Reserved1; /*0x10 */ 1310 U8 1311 MaxGlobalHotSpares; /*0x14 */ 1312 U8 MaxPhysDisks; /*0x15 */ 1313 U8 MaxVolumes; /*0x16 */ 1314 U8 MaxConfigs; /*0x17 */ 1315 U8 MaxOCEDisks; /*0x18 */ 1316 U8 Reserved2; /*0x19 */ 1317 U16 Reserved3; /*0x1A */ 1318 U32 1319 SupportedStripeSizeMapRAID0; /*0x1C */ 1320 U32 1321 SupportedStripeSizeMapRAID1E; /*0x20 */ 1322 U32 1323 SupportedStripeSizeMapRAID10; /*0x24 */ 1324 U32 Reserved4; /*0x28 */ 1325 U32 Reserved5; /*0x2C */ 1326 U16 1327 DefaultMetadataSize; /*0x30 */ 1328 U16 Reserved6; /*0x32 */ 1329 U16 1330 MaxBadBlockTableEntries; /*0x34 */ 1331 U16 Reserved7; /*0x36 */ 1332 U32 1333 IRNvsramVersion; /*0x38 */ 1334 } MPI2_CONFIG_PAGE_IOC_6, 1335 *PTR_MPI2_CONFIG_PAGE_IOC_6, 1336 Mpi2IOCPage6_t, *pMpi2IOCPage6_t; 1337 1338 #define MPI2_IOCPAGE6_PAGEVERSION (0x05) 1339 1340 /*defines for IOC Page 6 CapabilitiesFlags */ 1341 #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT (0x00000020) 1342 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010) 1343 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008) 1344 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004) 1345 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002) 1346 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 1347 1348 1349 /*IOC Page 7 */ 1350 1351 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4) 1352 1353 typedef struct _MPI2_CONFIG_PAGE_IOC_7 { 1354 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1355 U32 Reserved1; /*0x04 */ 1356 U32 1357 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/*0x08 */ 1358 U16 SASBroadcastPrimitiveMasks; /*0x18 */ 1359 U16 SASNotifyPrimitiveMasks; /*0x1A */ 1360 U32 Reserved3; /*0x1C */ 1361 } MPI2_CONFIG_PAGE_IOC_7, 1362 *PTR_MPI2_CONFIG_PAGE_IOC_7, 1363 Mpi2IOCPage7_t, *pMpi2IOCPage7_t; 1364 1365 #define MPI2_IOCPAGE7_PAGEVERSION (0x02) 1366 1367 1368 /*IOC Page 8 */ 1369 1370 typedef struct _MPI2_CONFIG_PAGE_IOC_8 { 1371 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1372 U8 NumDevsPerEnclosure; /*0x04 */ 1373 U8 Reserved1; /*0x05 */ 1374 U16 Reserved2; /*0x06 */ 1375 U16 MaxPersistentEntries; /*0x08 */ 1376 U16 MaxNumPhysicalMappedIDs; /*0x0A */ 1377 U16 Flags; /*0x0C */ 1378 U16 Reserved3; /*0x0E */ 1379 U16 IRVolumeMappingFlags; /*0x10 */ 1380 U16 Reserved4; /*0x12 */ 1381 U32 Reserved5; /*0x14 */ 1382 } MPI2_CONFIG_PAGE_IOC_8, 1383 *PTR_MPI2_CONFIG_PAGE_IOC_8, 1384 Mpi2IOCPage8_t, *pMpi2IOCPage8_t; 1385 1386 #define MPI2_IOCPAGE8_PAGEVERSION (0x00) 1387 1388 /*defines for IOC Page 8 Flags field */ 1389 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020) 1390 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010) 1391 1392 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E) 1393 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000) 1394 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002) 1395 1396 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001) 1397 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000) 1398 1399 /*defines for IOC Page 8 IRVolumeMappingFlags */ 1400 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003) 1401 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000) 1402 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001) 1403 1404 1405 /**************************************************************************** 1406 * BIOS Config Pages 1407 ****************************************************************************/ 1408 1409 /*BIOS Page 1 */ 1410 1411 typedef struct _MPI2_CONFIG_PAGE_BIOS_1 { 1412 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1413 U32 BiosOptions; /*0x04 */ 1414 U32 IOCSettings; /*0x08 */ 1415 U8 SSUTimeout; /*0x0C */ 1416 U8 Reserved1; /*0x0D */ 1417 U16 Reserved2; /*0x0E */ 1418 U32 DeviceSettings; /*0x10 */ 1419 U16 NumberOfDevices; /*0x14 */ 1420 U16 UEFIVersion; /*0x16 */ 1421 U16 IOTimeoutBlockDevicesNonRM; /*0x18 */ 1422 U16 IOTimeoutSequential; /*0x1A */ 1423 U16 IOTimeoutOther; /*0x1C */ 1424 U16 IOTimeoutBlockDevicesRM; /*0x1E */ 1425 } MPI2_CONFIG_PAGE_BIOS_1, 1426 *PTR_MPI2_CONFIG_PAGE_BIOS_1, 1427 Mpi2BiosPage1_t, *pMpi2BiosPage1_t; 1428 1429 #define MPI2_BIOSPAGE1_PAGEVERSION (0x07) 1430 1431 /*values for BIOS Page 1 BiosOptions field */ 1432 #define MPI2_BIOSPAGE1_OPTIONS_BOOT_LIST_ADD_ALT_BOOT_DEVICE (0x00008000) 1433 #define MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG (0x00004000) 1434 1435 #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800) 1436 #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800) 1437 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL (0x00000000) 1438 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE (0x00000800) 1439 #define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID (0x00001000) 1440 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PSENS (0x00001800) 1441 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ESPHY (0x00002000) 1442 1443 #define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS (0x00000400) 1444 1445 #define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD (0x00000300) 1446 #define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD (0x00000000) 1447 #define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD (0x00000100) 1448 #define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD (0x00000200) 1449 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD (0x00000300) 1450 1451 #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0) 1452 #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000) 1453 1454 #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006) 1455 #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000) 1456 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002) 1457 #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004) 1458 1459 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1460 1461 /*values for BIOS Page 1 IOCSettings field */ 1462 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1463 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1464 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1465 1466 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1467 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1468 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1469 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1470 1471 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1472 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1473 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1474 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1475 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1476 1477 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1478 1479 /*values for BIOS Page 1 DeviceSettings field */ 1480 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 1481 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1482 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1483 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1484 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1485 1486 /*defines for BIOS Page 1 UEFIVersion field */ 1487 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK (0xFF00) 1488 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT (8) 1489 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK (0x00FF) 1490 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT (0) 1491 1492 1493 1494 /*BIOS Page 2 */ 1495 1496 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER { 1497 U32 Reserved1; /*0x00 */ 1498 U32 Reserved2; /*0x04 */ 1499 U32 Reserved3; /*0x08 */ 1500 U32 Reserved4; /*0x0C */ 1501 U32 Reserved5; /*0x10 */ 1502 U32 Reserved6; /*0x14 */ 1503 } MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1504 *PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1505 Mpi2BootDeviceAdapterOrder_t, 1506 *pMpi2BootDeviceAdapterOrder_t; 1507 1508 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID { 1509 U64 SASAddress; /*0x00 */ 1510 U8 LUN[8]; /*0x08 */ 1511 U32 Reserved1; /*0x10 */ 1512 U32 Reserved2; /*0x14 */ 1513 } MPI2_BOOT_DEVICE_SAS_WWID, 1514 *PTR_MPI2_BOOT_DEVICE_SAS_WWID, 1515 Mpi2BootDeviceSasWwid_t, 1516 *pMpi2BootDeviceSasWwid_t; 1517 1518 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT { 1519 U64 EnclosureLogicalID; /*0x00 */ 1520 U32 Reserved1; /*0x08 */ 1521 U32 Reserved2; /*0x0C */ 1522 U16 SlotNumber; /*0x10 */ 1523 U16 Reserved3; /*0x12 */ 1524 U32 Reserved4; /*0x14 */ 1525 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1526 *PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1527 Mpi2BootDeviceEnclosureSlot_t, 1528 *pMpi2BootDeviceEnclosureSlot_t; 1529 1530 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME { 1531 U64 DeviceName; /*0x00 */ 1532 U8 LUN[8]; /*0x08 */ 1533 U32 Reserved1; /*0x10 */ 1534 U32 Reserved2; /*0x14 */ 1535 } MPI2_BOOT_DEVICE_DEVICE_NAME, 1536 *PTR_MPI2_BOOT_DEVICE_DEVICE_NAME, 1537 Mpi2BootDeviceDeviceName_t, 1538 *pMpi2BootDeviceDeviceName_t; 1539 1540 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE { 1541 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1542 MPI2_BOOT_DEVICE_SAS_WWID SasWwid; 1543 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1544 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName; 1545 } MPI2_BIOSPAGE2_BOOT_DEVICE, 1546 *PTR_MPI2_BIOSPAGE2_BOOT_DEVICE, 1547 Mpi2BiosPage2BootDevice_t, 1548 *pMpi2BiosPage2BootDevice_t; 1549 1550 typedef struct _MPI2_CONFIG_PAGE_BIOS_2 { 1551 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1552 U32 Reserved1; /*0x04 */ 1553 U32 Reserved2; /*0x08 */ 1554 U32 Reserved3; /*0x0C */ 1555 U32 Reserved4; /*0x10 */ 1556 U32 Reserved5; /*0x14 */ 1557 U32 Reserved6; /*0x18 */ 1558 U8 ReqBootDeviceForm; /*0x1C */ 1559 U8 Reserved7; /*0x1D */ 1560 U16 Reserved8; /*0x1E */ 1561 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /*0x20 */ 1562 U8 ReqAltBootDeviceForm; /*0x38 */ 1563 U8 Reserved9; /*0x39 */ 1564 U16 Reserved10; /*0x3A */ 1565 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /*0x3C */ 1566 U8 CurrentBootDeviceForm; /*0x58 */ 1567 U8 Reserved11; /*0x59 */ 1568 U16 Reserved12; /*0x5A */ 1569 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /*0x58 */ 1570 } MPI2_CONFIG_PAGE_BIOS_2, *PTR_MPI2_CONFIG_PAGE_BIOS_2, 1571 Mpi2BiosPage2_t, *pMpi2BiosPage2_t; 1572 1573 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04) 1574 1575 /*values for BIOS Page 2 BootDeviceForm fields */ 1576 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F) 1577 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00) 1578 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05) 1579 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1580 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07) 1581 1582 1583 /*BIOS Page 3 */ 1584 1585 #define MPI2_BIOSPAGE3_NUM_ADAPTER (4) 1586 1587 typedef struct _MPI2_ADAPTER_INFO { 1588 U8 PciBusNumber; /*0x00 */ 1589 U8 PciDeviceAndFunctionNumber; /*0x01 */ 1590 U16 AdapterFlags; /*0x02 */ 1591 } MPI2_ADAPTER_INFO, *PTR_MPI2_ADAPTER_INFO, 1592 Mpi2AdapterInfo_t, *pMpi2AdapterInfo_t; 1593 1594 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 1595 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 1596 1597 typedef struct _MPI2_ADAPTER_ORDER_AUX { 1598 U64 WWID; /* 0x00 */ 1599 U32 Reserved1; /* 0x08 */ 1600 U32 Reserved2; /* 0x0C */ 1601 } MPI2_ADAPTER_ORDER_AUX, *PTR_MPI2_ADAPTER_ORDER_AUX, 1602 Mpi2AdapterOrderAux_t, *pMpi2AdapterOrderAux_t; 1603 1604 1605 typedef struct _MPI2_CONFIG_PAGE_BIOS_3 { 1606 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1607 U32 GlobalFlags; /*0x04 */ 1608 U32 BiosVersion; /*0x08 */ 1609 MPI2_ADAPTER_INFO AdapterOrder[MPI2_BIOSPAGE3_NUM_ADAPTER]; 1610 U32 Reserved1; /*0x1C */ 1611 MPI2_ADAPTER_ORDER_AUX AdapterOrderAux[MPI2_BIOSPAGE3_NUM_ADAPTER]; 1612 } MPI2_CONFIG_PAGE_BIOS_3, 1613 *PTR_MPI2_CONFIG_PAGE_BIOS_3, 1614 Mpi2BiosPage3_t, *pMpi2BiosPage3_t; 1615 1616 #define MPI2_BIOSPAGE3_PAGEVERSION (0x01) 1617 1618 /*values for BIOS Page 3 GlobalFlags */ 1619 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) 1620 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004) 1621 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010) 1622 1623 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 1624 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 1625 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020) 1626 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 1627 1628 1629 /*BIOS Page 4 */ 1630 1631 /* 1632 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1633 *one and check the value returned for NumPhys at runtime. 1634 */ 1635 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES 1636 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1) 1637 #endif 1638 1639 typedef struct _MPI2_BIOS4_ENTRY { 1640 U64 ReassignmentWWID; /*0x00 */ 1641 U64 ReassignmentDeviceName; /*0x08 */ 1642 } MPI2_BIOS4_ENTRY, *PTR_MPI2_BIOS4_ENTRY, 1643 Mpi2MBios4Entry_t, *pMpi2Bios4Entry_t; 1644 1645 typedef struct _MPI2_CONFIG_PAGE_BIOS_4 { 1646 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1647 U8 NumPhys; /*0x04 */ 1648 U8 Reserved1; /*0x05 */ 1649 U16 Reserved2; /*0x06 */ 1650 MPI2_BIOS4_ENTRY 1651 Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /*0x08 */ 1652 } MPI2_CONFIG_PAGE_BIOS_4, *PTR_MPI2_CONFIG_PAGE_BIOS_4, 1653 Mpi2BiosPage4_t, *pMpi2BiosPage4_t; 1654 1655 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01) 1656 1657 1658 /**************************************************************************** 1659 * RAID Volume Config Pages 1660 ****************************************************************************/ 1661 1662 /*RAID Volume Page 0 */ 1663 1664 typedef struct _MPI2_RAIDVOL0_PHYS_DISK { 1665 U8 RAIDSetNum; /*0x00 */ 1666 U8 PhysDiskMap; /*0x01 */ 1667 U8 PhysDiskNum; /*0x02 */ 1668 U8 Reserved; /*0x03 */ 1669 } MPI2_RAIDVOL0_PHYS_DISK, *PTR_MPI2_RAIDVOL0_PHYS_DISK, 1670 Mpi2RaidVol0PhysDisk_t, *pMpi2RaidVol0PhysDisk_t; 1671 1672 /*defines for the PhysDiskMap field */ 1673 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1674 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1675 1676 typedef struct _MPI2_RAIDVOL0_SETTINGS { 1677 U16 Settings; /*0x00 */ 1678 U8 HotSparePool; /*0x01 */ 1679 U8 Reserved; /*0x02 */ 1680 } MPI2_RAIDVOL0_SETTINGS, *PTR_MPI2_RAIDVOL0_SETTINGS, 1681 Mpi2RaidVol0Settings_t, 1682 *pMpi2RaidVol0Settings_t; 1683 1684 /*RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1685 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01) 1686 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02) 1687 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04) 1688 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08) 1689 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10) 1690 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20) 1691 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40) 1692 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80) 1693 1694 /*RAID Volume Page 0 VolumeSettings defines */ 1695 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008) 1696 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004) 1697 1698 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003) 1699 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000) 1700 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001) 1701 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002) 1702 1703 /* 1704 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1705 *one and check the value returned for NumPhysDisks at runtime. 1706 */ 1707 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX 1708 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 1709 #endif 1710 1711 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 { 1712 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1713 U16 DevHandle; /*0x04 */ 1714 U8 VolumeState; /*0x06 */ 1715 U8 VolumeType; /*0x07 */ 1716 U32 VolumeStatusFlags; /*0x08 */ 1717 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /*0x0C */ 1718 U64 MaxLBA; /*0x10 */ 1719 U32 StripeSize; /*0x18 */ 1720 U16 BlockSize; /*0x1C */ 1721 U16 Reserved1; /*0x1E */ 1722 U8 SupportedPhysDisks;/*0x20 */ 1723 U8 ResyncRate; /*0x21 */ 1724 U16 DataScrubDuration; /*0x22 */ 1725 U8 NumPhysDisks; /*0x24 */ 1726 U8 Reserved2; /*0x25 */ 1727 U8 Reserved3; /*0x26 */ 1728 U8 InactiveStatus; /*0x27 */ 1729 MPI2_RAIDVOL0_PHYS_DISK 1730 PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /*0x28 */ 1731 } MPI2_CONFIG_PAGE_RAID_VOL_0, 1732 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_0, 1733 Mpi2RaidVolPage0_t, *pMpi2RaidVolPage0_t; 1734 1735 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A) 1736 1737 /*values for RAID VolumeState */ 1738 #define MPI2_RAID_VOL_STATE_MISSING (0x00) 1739 #define MPI2_RAID_VOL_STATE_FAILED (0x01) 1740 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02) 1741 #define MPI2_RAID_VOL_STATE_ONLINE (0x03) 1742 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04) 1743 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05) 1744 1745 /*values for RAID VolumeType */ 1746 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00) 1747 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01) 1748 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02) 1749 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05) 1750 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF) 1751 1752 /*values for RAID Volume Page 0 VolumeStatusFlags field */ 1753 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000) 1754 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000) 1755 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000) 1756 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000) 1757 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000) 1758 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000) 1759 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000) 1760 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000) 1761 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000) 1762 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000) 1763 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080) 1764 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040) 1765 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020) 1766 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000) 1767 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010) 1768 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008) 1769 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004) 1770 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002) 1771 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001) 1772 1773 /*values for RAID Volume Page 0 SupportedPhysDisks field */ 1774 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08) 1775 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04) 1776 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02) 1777 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01) 1778 1779 /*values for RAID Volume Page 0 InactiveStatus field */ 1780 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 1781 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 1782 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 1783 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 1784 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 1785 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 1786 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 1787 1788 1789 /*RAID Volume Page 1 */ 1790 1791 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 { 1792 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1793 U16 DevHandle; /*0x04 */ 1794 U16 Reserved0; /*0x06 */ 1795 U8 GUID[24]; /*0x08 */ 1796 U8 Name[16]; /*0x20 */ 1797 U64 WWID; /*0x30 */ 1798 U32 Reserved1; /*0x38 */ 1799 U32 Reserved2; /*0x3C */ 1800 } MPI2_CONFIG_PAGE_RAID_VOL_1, 1801 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_1, 1802 Mpi2RaidVolPage1_t, *pMpi2RaidVolPage1_t; 1803 1804 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03) 1805 1806 1807 /**************************************************************************** 1808 * RAID Physical Disk Config Pages 1809 ****************************************************************************/ 1810 1811 /*RAID Physical Disk Page 0 */ 1812 1813 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS { 1814 U16 Reserved1; /*0x00 */ 1815 U8 HotSparePool; /*0x02 */ 1816 U8 Reserved2; /*0x03 */ 1817 } MPI2_RAIDPHYSDISK0_SETTINGS, 1818 *PTR_MPI2_RAIDPHYSDISK0_SETTINGS, 1819 Mpi2RaidPhysDisk0Settings_t, 1820 *pMpi2RaidPhysDisk0Settings_t; 1821 1822 /*use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */ 1823 1824 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA { 1825 U8 VendorID[8]; /*0x00 */ 1826 U8 ProductID[16]; /*0x08 */ 1827 U8 ProductRevLevel[4]; /*0x18 */ 1828 U8 SerialNum[32]; /*0x1C */ 1829 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1830 *PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1831 Mpi2RaidPhysDisk0InquiryData_t, 1832 *pMpi2RaidPhysDisk0InquiryData_t; 1833 1834 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 { 1835 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1836 U16 DevHandle; /*0x04 */ 1837 U8 Reserved1; /*0x06 */ 1838 U8 PhysDiskNum; /*0x07 */ 1839 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /*0x08 */ 1840 U32 Reserved2; /*0x0C */ 1841 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /*0x10 */ 1842 U32 Reserved3; /*0x4C */ 1843 U8 PhysDiskState; /*0x50 */ 1844 U8 OfflineReason; /*0x51 */ 1845 U8 IncompatibleReason; /*0x52 */ 1846 U8 PhysDiskAttributes; /*0x53 */ 1847 U32 PhysDiskStatusFlags;/*0x54 */ 1848 U64 DeviceMaxLBA; /*0x58 */ 1849 U64 HostMaxLBA; /*0x60 */ 1850 U64 CoercedMaxLBA; /*0x68 */ 1851 U16 BlockSize; /*0x70 */ 1852 U16 Reserved5; /*0x72 */ 1853 U32 Reserved6; /*0x74 */ 1854 } MPI2_CONFIG_PAGE_RD_PDISK_0, 1855 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_0, 1856 Mpi2RaidPhysDiskPage0_t, 1857 *pMpi2RaidPhysDiskPage0_t; 1858 1859 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05) 1860 1861 /*PhysDiskState defines */ 1862 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00) 1863 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01) 1864 #define MPI2_RAID_PD_STATE_OFFLINE (0x02) 1865 #define MPI2_RAID_PD_STATE_ONLINE (0x03) 1866 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04) 1867 #define MPI2_RAID_PD_STATE_DEGRADED (0x05) 1868 #define MPI2_RAID_PD_STATE_REBUILDING (0x06) 1869 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07) 1870 1871 /*OfflineReason defines */ 1872 #define MPI2_PHYSDISK0_ONLINE (0x00) 1873 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01) 1874 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03) 1875 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04) 1876 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05) 1877 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06) 1878 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF) 1879 1880 /*IncompatibleReason defines */ 1881 #define MPI2_PHYSDISK0_COMPATIBLE (0x00) 1882 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01) 1883 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02) 1884 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03) 1885 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04) 1886 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05) 1887 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06) 1888 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF) 1889 1890 /*PhysDiskAttributes defines */ 1891 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C) 1892 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08) 1893 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04) 1894 1895 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03) 1896 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02) 1897 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01) 1898 1899 /*PhysDiskStatusFlags defines */ 1900 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040) 1901 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020) 1902 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010) 1903 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000) 1904 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008) 1905 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004) 1906 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002) 1907 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001) 1908 1909 1910 /*RAID Physical Disk Page 1 */ 1911 1912 /* 1913 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1914 *one and check the value returned for NumPhysDiskPaths at runtime. 1915 */ 1916 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX 1917 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1) 1918 #endif 1919 1920 typedef struct _MPI2_RAIDPHYSDISK1_PATH { 1921 U16 DevHandle; /*0x00 */ 1922 U16 Reserved1; /*0x02 */ 1923 U64 WWID; /*0x04 */ 1924 U64 OwnerWWID; /*0x0C */ 1925 U8 OwnerIdentifier; /*0x14 */ 1926 U8 Reserved2; /*0x15 */ 1927 U16 Flags; /*0x16 */ 1928 } MPI2_RAIDPHYSDISK1_PATH, *PTR_MPI2_RAIDPHYSDISK1_PATH, 1929 Mpi2RaidPhysDisk1Path_t, 1930 *pMpi2RaidPhysDisk1Path_t; 1931 1932 /*RAID Physical Disk Page 1 Physical Disk Path Flags field defines */ 1933 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004) 1934 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 1935 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 1936 1937 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 { 1938 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1939 U8 NumPhysDiskPaths; /*0x04 */ 1940 U8 PhysDiskNum; /*0x05 */ 1941 U16 Reserved1; /*0x06 */ 1942 U32 Reserved2; /*0x08 */ 1943 MPI2_RAIDPHYSDISK1_PATH 1944 PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/*0x0C */ 1945 } MPI2_CONFIG_PAGE_RD_PDISK_1, 1946 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_1, 1947 Mpi2RaidPhysDiskPage1_t, 1948 *pMpi2RaidPhysDiskPage1_t; 1949 1950 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02) 1951 1952 1953 /**************************************************************************** 1954 * values for fields used by several types of SAS Config Pages 1955 ****************************************************************************/ 1956 1957 /*values for NegotiatedLinkRates fields */ 1958 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0) 1959 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4) 1960 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 1961 /*link rates used for Negotiated Physical and Logical Link Rate */ 1962 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 1963 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 1964 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 1965 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 1966 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 1967 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 1968 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 1969 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08) 1970 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09) 1971 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A) 1972 #define MPI25_SAS_NEG_LINK_RATE_12_0 (0x0B) 1973 1974 1975 /*values for AttachedPhyInfo fields */ 1976 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 1977 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 1978 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 1979 1980 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F) 1981 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 1982 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 1983 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 1984 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 1985 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 1986 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 1987 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 1988 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 1989 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 1990 1991 1992 /*values for PhyInfo fields */ 1993 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000) 1994 1995 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 1996 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27) 1997 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000) 1998 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000) 1999 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000) 2000 2001 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000) 2002 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000) 2003 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000) 2004 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 2005 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000) 2006 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 2007 2008 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000) 2009 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 2010 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 2011 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 2012 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 2013 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 2014 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 2015 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 2016 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 2017 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 2018 2019 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000) 2020 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 2021 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 2022 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 2023 2024 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 2025 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 2026 2027 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 2028 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000) 2029 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 2030 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020) 2031 2032 2033 /*values for SAS ProgrammedLinkRate fields */ 2034 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0) 2035 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 2036 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80) 2037 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90) 2038 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0) 2039 #define MPI25_SAS_PRATE_MAX_RATE_12_0 (0xB0) 2040 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F) 2041 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 2042 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08) 2043 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09) 2044 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A) 2045 #define MPI25_SAS_PRATE_MIN_RATE_12_0 (0x0B) 2046 2047 2048 /*values for SAS HwLinkRate fields */ 2049 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0) 2050 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80) 2051 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90) 2052 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0) 2053 #define MPI25_SAS_HWRATE_MAX_RATE_12_0 (0xB0) 2054 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F) 2055 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08) 2056 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09) 2057 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A) 2058 #define MPI25_SAS_HWRATE_MIN_RATE_12_0 (0x0B) 2059 2060 2061 2062 /**************************************************************************** 2063 * SAS IO Unit Config Pages 2064 ****************************************************************************/ 2065 2066 /*SAS IO Unit Page 0 */ 2067 2068 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA { 2069 U8 Port; /*0x00 */ 2070 U8 PortFlags; /*0x01 */ 2071 U8 PhyFlags; /*0x02 */ 2072 U8 NegotiatedLinkRate; /*0x03 */ 2073 U32 ControllerPhyDeviceInfo;/*0x04 */ 2074 U16 AttachedDevHandle; /*0x08 */ 2075 U16 ControllerDevHandle; /*0x0A */ 2076 U32 DiscoveryStatus; /*0x0C */ 2077 U32 Reserved; /*0x10 */ 2078 } MPI2_SAS_IO_UNIT0_PHY_DATA, 2079 *PTR_MPI2_SAS_IO_UNIT0_PHY_DATA, 2080 Mpi2SasIOUnit0PhyData_t, 2081 *pMpi2SasIOUnit0PhyData_t; 2082 2083 /* 2084 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2085 *one and check the value returned for NumPhys at runtime. 2086 */ 2087 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX 2088 #define MPI2_SAS_IOUNIT0_PHY_MAX (1) 2089 #endif 2090 2091 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 { 2092 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2093 U32 Reserved1;/*0x08 */ 2094 U8 NumPhys; /*0x0C */ 2095 U8 Reserved2;/*0x0D */ 2096 U16 Reserved3;/*0x0E */ 2097 MPI2_SAS_IO_UNIT0_PHY_DATA 2098 PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /*0x10 */ 2099 } MPI2_CONFIG_PAGE_SASIOUNIT_0, 2100 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0, 2101 Mpi2SasIOUnitPage0_t, *pMpi2SasIOUnitPage0_t; 2102 2103 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05) 2104 2105 /*values for SAS IO Unit Page 0 PortFlags */ 2106 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08) 2107 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) 2108 2109 /*values for SAS IO Unit Page 0 PhyFlags */ 2110 #define MPI2_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2111 #define MPI2_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2112 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) 2113 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 2114 2115 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2116 2117 /*see mpi2_sas.h for values for 2118 *SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 2119 2120 /*values for SAS IO Unit Page 0 DiscoveryStatus */ 2121 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2122 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2123 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000) 2124 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2125 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2126 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2127 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2128 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 2129 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2130 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 2131 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400) 2132 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 2133 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 2134 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 2135 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 2136 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2137 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010) 2138 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 2139 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2140 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001) 2141 2142 2143 /*SAS IO Unit Page 1 */ 2144 2145 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA { 2146 U8 Port; /*0x00 */ 2147 U8 PortFlags; /*0x01 */ 2148 U8 PhyFlags; /*0x02 */ 2149 U8 MaxMinLinkRate; /*0x03 */ 2150 U32 ControllerPhyDeviceInfo; /*0x04 */ 2151 U16 MaxTargetPortConnectTime; /*0x08 */ 2152 U16 Reserved1; /*0x0A */ 2153 } MPI2_SAS_IO_UNIT1_PHY_DATA, 2154 *PTR_MPI2_SAS_IO_UNIT1_PHY_DATA, 2155 Mpi2SasIOUnit1PhyData_t, 2156 *pMpi2SasIOUnit1PhyData_t; 2157 2158 /* 2159 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2160 *one and check the value returned for NumPhys at runtime. 2161 */ 2162 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX 2163 #define MPI2_SAS_IOUNIT1_PHY_MAX (1) 2164 #endif 2165 2166 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 { 2167 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2168 U16 2169 ControlFlags; /*0x08 */ 2170 U16 2171 SASNarrowMaxQueueDepth; /*0x0A */ 2172 U16 2173 AdditionalControlFlags; /*0x0C */ 2174 U16 2175 SASWideMaxQueueDepth; /*0x0E */ 2176 U8 2177 NumPhys; /*0x10 */ 2178 U8 2179 SATAMaxQDepth; /*0x11 */ 2180 U8 2181 ReportDeviceMissingDelay; /*0x12 */ 2182 U8 2183 IODeviceMissingDelay; /*0x13 */ 2184 MPI2_SAS_IO_UNIT1_PHY_DATA 2185 PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /*0x14 */ 2186 } MPI2_CONFIG_PAGE_SASIOUNIT_1, 2187 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1, 2188 Mpi2SasIOUnitPage1_t, *pMpi2SasIOUnitPage1_t; 2189 2190 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09) 2191 2192 /*values for SAS IO Unit Page 1 ControlFlags */ 2193 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 2194 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 2195 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) 2196 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 2197 2198 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 2199 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 2200 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0) 2201 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1) 2202 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2) 2203 2204 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 2205 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 2206 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 2207 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 2208 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 2209 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 2210 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 2211 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) 2212 2213 /*values for SAS IO Unit Page 1 AdditionalControlFlags */ 2214 #define MPI2_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100) 2215 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 2216 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 2217 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 2218 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 2219 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 2220 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 2221 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 2222 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 2223 2224 /*defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 2225 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 2226 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 2227 2228 /*values for SAS IO Unit Page 1 PortFlags */ 2229 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2230 2231 /*values for SAS IO Unit Page 1 PhyFlags */ 2232 #define MPI2_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2233 #define MPI2_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2234 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) 2235 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 2236 2237 /*values for SAS IO Unit Page 1 MaxMinLinkRate */ 2238 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) 2239 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) 2240 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) 2241 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) 2242 #define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0) 2243 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) 2244 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) 2245 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) 2246 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) 2247 #define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B) 2248 2249 /*see mpi2_sas.h for values for 2250 *SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 2251 2252 2253 /*SAS IO Unit Page 4 (for MPI v2.5 and earlier) */ 2254 2255 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP { 2256 U8 MaxTargetSpinup; /*0x00 */ 2257 U8 SpinupDelay; /*0x01 */ 2258 U8 SpinupFlags; /*0x02 */ 2259 U8 Reserved1; /*0x03 */ 2260 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, 2261 *PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP, 2262 Mpi2SasIOUnit4SpinupGroup_t, 2263 *pMpi2SasIOUnit4SpinupGroup_t; 2264 /*defines for SAS IO Unit Page 4 SpinupFlags */ 2265 #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01) 2266 2267 2268 /* 2269 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2270 *one and check the value returned for NumPhys at runtime. 2271 */ 2272 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX 2273 #define MPI2_SAS_IOUNIT4_PHY_MAX (4) 2274 #endif 2275 2276 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 { 2277 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header;/*0x00 */ 2278 MPI2_SAS_IOUNIT4_SPINUP_GROUP 2279 SpinupGroupParameters[4]; /*0x08 */ 2280 U32 2281 Reserved1; /*0x18 */ 2282 U32 2283 Reserved2; /*0x1C */ 2284 U32 2285 Reserved3; /*0x20 */ 2286 U8 2287 BootDeviceWaitTime; /*0x24 */ 2288 U8 2289 SATADeviceWaitTime; /*0x25 */ 2290 U16 2291 Reserved5; /*0x26 */ 2292 U8 2293 NumPhys; /*0x28 */ 2294 U8 2295 PEInitialSpinupDelay; /*0x29 */ 2296 U8 2297 PEReplyDelay; /*0x2A */ 2298 U8 2299 Flags; /*0x2B */ 2300 U8 2301 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /*0x2C */ 2302 } MPI2_CONFIG_PAGE_SASIOUNIT_4, 2303 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4, 2304 Mpi2SasIOUnitPage4_t, *pMpi2SasIOUnitPage4_t; 2305 2306 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02) 2307 2308 /*defines for Flags field */ 2309 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01) 2310 2311 /*defines for PHY field */ 2312 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03) 2313 2314 2315 /*SAS IO Unit Page 5 */ 2316 2317 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS { 2318 U8 ControlFlags; /*0x00 */ 2319 U8 PortWidthModGroup; /*0x01 */ 2320 U16 InactivityTimerExponent; /*0x02 */ 2321 U8 SATAPartialTimeout; /*0x04 */ 2322 U8 Reserved2; /*0x05 */ 2323 U8 SATASlumberTimeout; /*0x06 */ 2324 U8 Reserved3; /*0x07 */ 2325 U8 SASPartialTimeout; /*0x08 */ 2326 U8 Reserved4; /*0x09 */ 2327 U8 SASSlumberTimeout; /*0x0A */ 2328 U8 Reserved5; /*0x0B */ 2329 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2330 *PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2331 Mpi2SasIOUnit5PhyPmSettings_t, 2332 *pMpi2SasIOUnit5PhyPmSettings_t; 2333 2334 /*defines for ControlFlags field */ 2335 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08) 2336 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04) 2337 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02) 2338 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01) 2339 2340 /*defines for PortWidthModeGroup field */ 2341 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF) 2342 2343 /*defines for InactivityTimerExponent field */ 2344 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000) 2345 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12) 2346 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700) 2347 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8) 2348 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070) 2349 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4) 2350 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007) 2351 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0) 2352 2353 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7) 2354 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6) 2355 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5) 2356 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4) 2357 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3) 2358 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2) 2359 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1) 2360 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0) 2361 2362 /* 2363 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2364 *one and check the value returned for NumPhys at runtime. 2365 */ 2366 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX 2367 #define MPI2_SAS_IOUNIT5_PHY_MAX (1) 2368 #endif 2369 2370 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 { 2371 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2372 U8 NumPhys; /*0x08 */ 2373 U8 Reserved1;/*0x09 */ 2374 U16 Reserved2;/*0x0A */ 2375 U32 Reserved3;/*0x0C */ 2376 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS 2377 SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX];/*0x10 */ 2378 } MPI2_CONFIG_PAGE_SASIOUNIT_5, 2379 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5, 2380 Mpi2SasIOUnitPage5_t, *pMpi2SasIOUnitPage5_t; 2381 2382 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01) 2383 2384 2385 /*SAS IO Unit Page 6 */ 2386 2387 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS { 2388 U8 CurrentStatus; /*0x00 */ 2389 U8 CurrentModulation; /*0x01 */ 2390 U8 CurrentUtilization; /*0x02 */ 2391 U8 Reserved1; /*0x03 */ 2392 U32 Reserved2; /*0x04 */ 2393 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2394 *PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2395 Mpi2SasIOUnit6PortWidthModGroupStatus_t, 2396 *pMpi2SasIOUnit6PortWidthModGroupStatus_t; 2397 2398 /*defines for CurrentStatus field */ 2399 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00) 2400 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01) 2401 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02) 2402 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03) 2403 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04) 2404 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05) 2405 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06) 2406 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07) 2407 2408 /*defines for CurrentModulation field */ 2409 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00) 2410 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01) 2411 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02) 2412 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03) 2413 2414 /* 2415 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2416 *one and check the value returned for NumGroups at runtime. 2417 */ 2418 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX 2419 #define MPI2_SAS_IOUNIT6_GROUP_MAX (1) 2420 #endif 2421 2422 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 { 2423 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2424 U32 Reserved1; /*0x08 */ 2425 U32 Reserved2; /*0x0C */ 2426 U8 NumGroups; /*0x10 */ 2427 U8 Reserved3; /*0x11 */ 2428 U16 Reserved4; /*0x12 */ 2429 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 2430 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /*0x14 */ 2431 } MPI2_CONFIG_PAGE_SASIOUNIT_6, 2432 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6, 2433 Mpi2SasIOUnitPage6_t, *pMpi2SasIOUnitPage6_t; 2434 2435 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00) 2436 2437 2438 /*SAS IO Unit Page 7 */ 2439 2440 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS { 2441 U8 Flags; /*0x00 */ 2442 U8 Reserved1; /*0x01 */ 2443 U16 Reserved2; /*0x02 */ 2444 U8 Threshold75Pct; /*0x04 */ 2445 U8 Threshold50Pct; /*0x05 */ 2446 U8 Threshold25Pct; /*0x06 */ 2447 U8 Reserved3; /*0x07 */ 2448 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2449 *PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2450 Mpi2SasIOUnit7PortWidthModGroupSettings_t, 2451 *pMpi2SasIOUnit7PortWidthModGroupSettings_t; 2452 2453 /*defines for Flags field */ 2454 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01) 2455 2456 2457 /* 2458 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2459 *one and check the value returned for NumGroups at runtime. 2460 */ 2461 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX 2462 #define MPI2_SAS_IOUNIT7_GROUP_MAX (1) 2463 #endif 2464 2465 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 { 2466 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2467 U8 SamplingInterval; /*0x08 */ 2468 U8 WindowLength; /*0x09 */ 2469 U16 Reserved1; /*0x0A */ 2470 U32 Reserved2; /*0x0C */ 2471 U32 Reserved3; /*0x10 */ 2472 U8 NumGroups; /*0x14 */ 2473 U8 Reserved4; /*0x15 */ 2474 U16 Reserved5; /*0x16 */ 2475 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2476 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX];/*0x18 */ 2477 } MPI2_CONFIG_PAGE_SASIOUNIT_7, 2478 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7, 2479 Mpi2SasIOUnitPage7_t, *pMpi2SasIOUnitPage7_t; 2480 2481 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00) 2482 2483 2484 /*SAS IO Unit Page 8 */ 2485 2486 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 { 2487 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2488 Header; /*0x00 */ 2489 U32 2490 Reserved1; /*0x08 */ 2491 U32 2492 PowerManagementCapabilities; /*0x0C */ 2493 U8 2494 TxRxSleepStatus; /*0x10 */ 2495 U8 2496 Reserved2; /*0x11 */ 2497 U16 2498 Reserved3; /*0x12 */ 2499 } MPI2_CONFIG_PAGE_SASIOUNIT_8, 2500 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8, 2501 Mpi2SasIOUnitPage8_t, *pMpi2SasIOUnitPage8_t; 2502 2503 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00) 2504 2505 /*defines for PowerManagementCapabilities field */ 2506 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000) 2507 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800) 2508 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400) 2509 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200) 2510 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100) 2511 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010) 2512 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008) 2513 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004) 2514 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002) 2515 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001) 2516 2517 /*defines for TxRxSleepStatus field */ 2518 #define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED (0x00) 2519 #define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED (0x01) 2520 #define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE (0x02) 2521 #define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN (0x03) 2522 2523 2524 2525 /*SAS IO Unit Page 16 */ 2526 2527 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 { 2528 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2529 Header; /*0x00 */ 2530 U64 2531 TimeStamp; /*0x08 */ 2532 U32 2533 Reserved1; /*0x10 */ 2534 U32 2535 Reserved2; /*0x14 */ 2536 U32 2537 FastPathPendedRequests; /*0x18 */ 2538 U32 2539 FastPathUnPendedRequests; /*0x1C */ 2540 U32 2541 FastPathHostRequestStarts; /*0x20 */ 2542 U32 2543 FastPathFirmwareRequestStarts; /*0x24 */ 2544 U32 2545 FastPathHostCompletions; /*0x28 */ 2546 U32 2547 FastPathFirmwareCompletions; /*0x2C */ 2548 U32 2549 NonFastPathRequestStarts; /*0x30 */ 2550 U32 2551 NonFastPathHostCompletions; /*0x30 */ 2552 } MPI2_CONFIG_PAGE_SASIOUNIT16, 2553 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT16, 2554 Mpi2SasIOUnitPage16_t, *pMpi2SasIOUnitPage16_t; 2555 2556 #define MPI2_SASIOUNITPAGE16_PAGEVERSION (0x00) 2557 2558 2559 /**************************************************************************** 2560 * SAS Expander Config Pages 2561 ****************************************************************************/ 2562 2563 /*SAS Expander Page 0 */ 2564 2565 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 { 2566 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2567 Header; /*0x00 */ 2568 U8 2569 PhysicalPort; /*0x08 */ 2570 U8 2571 ReportGenLength; /*0x09 */ 2572 U16 2573 EnclosureHandle; /*0x0A */ 2574 U64 2575 SASAddress; /*0x0C */ 2576 U32 2577 DiscoveryStatus; /*0x14 */ 2578 U16 2579 DevHandle; /*0x18 */ 2580 U16 2581 ParentDevHandle; /*0x1A */ 2582 U16 2583 ExpanderChangeCount; /*0x1C */ 2584 U16 2585 ExpanderRouteIndexes; /*0x1E */ 2586 U8 2587 NumPhys; /*0x20 */ 2588 U8 2589 SASLevel; /*0x21 */ 2590 U16 2591 Flags; /*0x22 */ 2592 U16 2593 STPBusInactivityTimeLimit; /*0x24 */ 2594 U16 2595 STPMaxConnectTimeLimit; /*0x26 */ 2596 U16 2597 STP_SMP_NexusLossTime; /*0x28 */ 2598 U16 2599 MaxNumRoutedSasAddresses; /*0x2A */ 2600 U64 2601 ActiveZoneManagerSASAddress;/*0x2C */ 2602 U16 2603 ZoneLockInactivityLimit; /*0x34 */ 2604 U16 2605 Reserved1; /*0x36 */ 2606 U8 2607 TimeToReducedFunc; /*0x38 */ 2608 U8 2609 InitialTimeToReducedFunc; /*0x39 */ 2610 U8 2611 MaxReducedFuncTime; /*0x3A */ 2612 U8 2613 Reserved2; /*0x3B */ 2614 } MPI2_CONFIG_PAGE_EXPANDER_0, 2615 *PTR_MPI2_CONFIG_PAGE_EXPANDER_0, 2616 Mpi2ExpanderPage0_t, *pMpi2ExpanderPage0_t; 2617 2618 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06) 2619 2620 /*values for SAS Expander Page 0 DiscoveryStatus field */ 2621 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2622 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2623 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000) 2624 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2625 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2626 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2627 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2628 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000) 2629 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2630 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2631 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2632 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2633 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2634 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2635 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2636 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2637 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2638 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2639 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2640 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2641 2642 /*values for SAS Expander Page 0 Flags field */ 2643 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 2644 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 2645 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 2646 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 2647 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 2648 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 2649 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 2650 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 2651 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 2652 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 2653 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 2654 2655 2656 /*SAS Expander Page 1 */ 2657 2658 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 { 2659 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2660 Header; /*0x00 */ 2661 U8 2662 PhysicalPort; /*0x08 */ 2663 U8 2664 Reserved1; /*0x09 */ 2665 U16 2666 Reserved2; /*0x0A */ 2667 U8 2668 NumPhys; /*0x0C */ 2669 U8 2670 Phy; /*0x0D */ 2671 U16 2672 NumTableEntriesProgrammed; /*0x0E */ 2673 U8 2674 ProgrammedLinkRate; /*0x10 */ 2675 U8 2676 HwLinkRate; /*0x11 */ 2677 U16 2678 AttachedDevHandle; /*0x12 */ 2679 U32 2680 PhyInfo; /*0x14 */ 2681 U32 2682 AttachedDeviceInfo; /*0x18 */ 2683 U16 2684 ExpanderDevHandle; /*0x1C */ 2685 U8 2686 ChangeCount; /*0x1E */ 2687 U8 2688 NegotiatedLinkRate; /*0x1F */ 2689 U8 2690 PhyIdentifier; /*0x20 */ 2691 U8 2692 AttachedPhyIdentifier; /*0x21 */ 2693 U8 2694 Reserved3; /*0x22 */ 2695 U8 2696 DiscoveryInfo; /*0x23 */ 2697 U32 2698 AttachedPhyInfo; /*0x24 */ 2699 U8 2700 ZoneGroup; /*0x28 */ 2701 U8 2702 SelfConfigStatus; /*0x29 */ 2703 U16 2704 Reserved4; /*0x2A */ 2705 } MPI2_CONFIG_PAGE_EXPANDER_1, 2706 *PTR_MPI2_CONFIG_PAGE_EXPANDER_1, 2707 Mpi2ExpanderPage1_t, *pMpi2ExpanderPage1_t; 2708 2709 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02) 2710 2711 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2712 2713 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2714 2715 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2716 2717 /*see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines 2718 *used for the AttachedDeviceInfo field */ 2719 2720 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2721 2722 /*values for SAS Expander Page 1 DiscoveryInfo field */ 2723 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2724 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2725 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2726 2727 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2728 2729 2730 /**************************************************************************** 2731 * SAS Device Config Pages 2732 ****************************************************************************/ 2733 2734 /*SAS Device Page 0 */ 2735 2736 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 { 2737 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2738 Header; /*0x00 */ 2739 U16 2740 Slot; /*0x08 */ 2741 U16 2742 EnclosureHandle; /*0x0A */ 2743 U64 2744 SASAddress; /*0x0C */ 2745 U16 2746 ParentDevHandle; /*0x14 */ 2747 U8 2748 PhyNum; /*0x16 */ 2749 U8 2750 AccessStatus; /*0x17 */ 2751 U16 2752 DevHandle; /*0x18 */ 2753 U8 2754 AttachedPhyIdentifier; /*0x1A */ 2755 U8 2756 ZoneGroup; /*0x1B */ 2757 U32 2758 DeviceInfo; /*0x1C */ 2759 U16 2760 Flags; /*0x20 */ 2761 U8 2762 PhysicalPort; /*0x22 */ 2763 U8 2764 MaxPortConnections; /*0x23 */ 2765 U64 2766 DeviceName; /*0x24 */ 2767 U8 2768 PortGroups; /*0x2C */ 2769 U8 2770 DmaGroup; /*0x2D */ 2771 U8 2772 ControlGroup; /*0x2E */ 2773 U8 2774 EnclosureLevel; /*0x2F */ 2775 U32 2776 ConnectorName[4]; /*0x30 */ 2777 U32 2778 Reserved3; /*0x34 */ 2779 } MPI2_CONFIG_PAGE_SAS_DEV_0, 2780 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_0, 2781 Mpi2SasDevicePage0_t, 2782 *pMpi2SasDevicePage0_t; 2783 2784 #define MPI2_SASDEVICE0_PAGEVERSION (0x09) 2785 2786 /*values for SAS Device Page 0 AccessStatus field */ 2787 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2788 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2789 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2790 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2791 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2792 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05) 2793 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06) 2794 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07) 2795 /*specific values for SATA Init failures */ 2796 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2797 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2798 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2799 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2800 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2801 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2802 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2803 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2804 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2805 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2806 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2807 2808 /*see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2809 2810 /*values for SAS Device Page 0 Flags field */ 2811 #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000) 2812 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH (0x4000) 2813 #define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE (0x2000) 2814 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000) 2815 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800) 2816 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2817 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2818 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2819 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2820 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2821 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2822 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2823 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2824 #define MPI2_SAS_DEVICE0_FLAGS_PERSIST_CAPABLE (0x0004) 2825 #define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID (0x0002) 2826 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2827 2828 2829 /*SAS Device Page 1 */ 2830 2831 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 { 2832 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2833 Header; /*0x00 */ 2834 U32 2835 Reserved1; /*0x08 */ 2836 U64 2837 SASAddress; /*0x0C */ 2838 U32 2839 Reserved2; /*0x14 */ 2840 U16 2841 DevHandle; /*0x18 */ 2842 U16 2843 Reserved3; /*0x1A */ 2844 U8 2845 InitialRegDeviceFIS[20];/*0x1C */ 2846 } MPI2_CONFIG_PAGE_SAS_DEV_1, 2847 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_1, 2848 Mpi2SasDevicePage1_t, 2849 *pMpi2SasDevicePage1_t; 2850 2851 #define MPI2_SASDEVICE1_PAGEVERSION (0x01) 2852 2853 2854 /**************************************************************************** 2855 * SAS PHY Config Pages 2856 ****************************************************************************/ 2857 2858 /*SAS PHY Page 0 */ 2859 2860 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 { 2861 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2862 Header; /*0x00 */ 2863 U16 2864 OwnerDevHandle; /*0x08 */ 2865 U16 2866 Reserved1; /*0x0A */ 2867 U16 2868 AttachedDevHandle; /*0x0C */ 2869 U8 2870 AttachedPhyIdentifier; /*0x0E */ 2871 U8 2872 Reserved2; /*0x0F */ 2873 U32 2874 AttachedPhyInfo; /*0x10 */ 2875 U8 2876 ProgrammedLinkRate; /*0x14 */ 2877 U8 2878 HwLinkRate; /*0x15 */ 2879 U8 2880 ChangeCount; /*0x16 */ 2881 U8 2882 Flags; /*0x17 */ 2883 U32 2884 PhyInfo; /*0x18 */ 2885 U8 2886 NegotiatedLinkRate; /*0x1C */ 2887 U8 2888 Reserved3; /*0x1D */ 2889 U16 2890 Reserved4; /*0x1E */ 2891 } MPI2_CONFIG_PAGE_SAS_PHY_0, 2892 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_0, 2893 Mpi2SasPhyPage0_t, *pMpi2SasPhyPage0_t; 2894 2895 #define MPI2_SASPHY0_PAGEVERSION (0x03) 2896 2897 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2898 2899 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2900 2901 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2902 2903 /*values for SAS PHY Page 0 Flags field */ 2904 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 2905 2906 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2907 2908 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2909 2910 2911 /*SAS PHY Page 1 */ 2912 2913 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 { 2914 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2915 Header; /*0x00 */ 2916 U32 2917 Reserved1; /*0x08 */ 2918 U32 2919 InvalidDwordCount; /*0x0C */ 2920 U32 2921 RunningDisparityErrorCount; /*0x10 */ 2922 U32 2923 LossDwordSynchCount; /*0x14 */ 2924 U32 2925 PhyResetProblemCount; /*0x18 */ 2926 } MPI2_CONFIG_PAGE_SAS_PHY_1, 2927 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_1, 2928 Mpi2SasPhyPage1_t, *pMpi2SasPhyPage1_t; 2929 2930 #define MPI2_SASPHY1_PAGEVERSION (0x01) 2931 2932 2933 /*SAS PHY Page 2 */ 2934 2935 typedef struct _MPI2_SASPHY2_PHY_EVENT { 2936 U8 PhyEventCode; /*0x00 */ 2937 U8 Reserved1; /*0x01 */ 2938 U16 Reserved2; /*0x02 */ 2939 U32 PhyEventInfo; /*0x04 */ 2940 } MPI2_SASPHY2_PHY_EVENT, *PTR_MPI2_SASPHY2_PHY_EVENT, 2941 Mpi2SasPhy2PhyEvent_t, *pMpi2SasPhy2PhyEvent_t; 2942 2943 /*use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */ 2944 2945 2946 /* 2947 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2948 *one and check the value returned for NumPhyEvents at runtime. 2949 */ 2950 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX 2951 #define MPI2_SASPHY2_PHY_EVENT_MAX (1) 2952 #endif 2953 2954 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 { 2955 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2956 Header; /*0x00 */ 2957 U32 2958 Reserved1; /*0x08 */ 2959 U8 2960 NumPhyEvents; /*0x0C */ 2961 U8 2962 Reserved2; /*0x0D */ 2963 U16 2964 Reserved3; /*0x0E */ 2965 MPI2_SASPHY2_PHY_EVENT 2966 PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /*0x10 */ 2967 } MPI2_CONFIG_PAGE_SAS_PHY_2, 2968 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_2, 2969 Mpi2SasPhyPage2_t, 2970 *pMpi2SasPhyPage2_t; 2971 2972 #define MPI2_SASPHY2_PAGEVERSION (0x00) 2973 2974 2975 /*SAS PHY Page 3 */ 2976 2977 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG { 2978 U8 PhyEventCode; /*0x00 */ 2979 U8 Reserved1; /*0x01 */ 2980 U16 Reserved2; /*0x02 */ 2981 U8 CounterType; /*0x04 */ 2982 U8 ThresholdWindow; /*0x05 */ 2983 U8 TimeUnits; /*0x06 */ 2984 U8 Reserved3; /*0x07 */ 2985 U32 EventThreshold; /*0x08 */ 2986 U16 ThresholdFlags; /*0x0C */ 2987 U16 Reserved4; /*0x0E */ 2988 } MPI2_SASPHY3_PHY_EVENT_CONFIG, 2989 *PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG, 2990 Mpi2SasPhy3PhyEventConfig_t, 2991 *pMpi2SasPhy3PhyEventConfig_t; 2992 2993 /*values for PhyEventCode field */ 2994 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 2995 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 2996 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 2997 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 2998 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 2999 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 3000 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 3001 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 3002 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 3003 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 3004 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 3005 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 3006 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 3007 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 3008 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 3009 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 3010 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 3011 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A) 3012 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B) 3013 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C) 3014 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D) 3015 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E) 3016 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 3017 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 3018 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 3019 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 3020 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 3021 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 3022 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 3023 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 3024 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 3025 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 3026 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 3027 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 3028 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) 3029 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) 3030 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2) 3031 3032 /*Following codes are product specific and in MPI v2.6 and later */ 3033 #define MPI2_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xD3) 3034 #define MPI2_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xD4) 3035 #define MPI2_SASPHY3_EVENT_CODE_LCCONN_TIME (0xD5) 3036 #define MPI2_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xD6) 3037 #define MPI2_SASPHY3_EVENT_CODE_SATA_TX_START (0xD7) 3038 #define MPI2_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xD8) 3039 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xD9) 3040 #define MPI2_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xDA) 3041 #define MPI2_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xDB) 3042 #define MPI2_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xDC) 3043 3044 3045 /*values for the CounterType field */ 3046 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 3047 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 3048 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 3049 3050 /*values for the TimeUnits field */ 3051 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 3052 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 3053 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 3054 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 3055 3056 /*values for the ThresholdFlags field */ 3057 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002) 3058 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 3059 3060 /* 3061 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3062 *one and check the value returned for NumPhyEvents at runtime. 3063 */ 3064 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX 3065 #define MPI2_SASPHY3_PHY_EVENT_MAX (1) 3066 #endif 3067 3068 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 { 3069 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3070 Header; /*0x00 */ 3071 U32 3072 Reserved1; /*0x08 */ 3073 U8 3074 NumPhyEvents; /*0x0C */ 3075 U8 3076 Reserved2; /*0x0D */ 3077 U16 3078 Reserved3; /*0x0E */ 3079 MPI2_SASPHY3_PHY_EVENT_CONFIG 3080 PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /*0x10 */ 3081 } MPI2_CONFIG_PAGE_SAS_PHY_3, 3082 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_3, 3083 Mpi2SasPhyPage3_t, *pMpi2SasPhyPage3_t; 3084 3085 #define MPI2_SASPHY3_PAGEVERSION (0x00) 3086 3087 3088 /*SAS PHY Page 4 */ 3089 3090 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 { 3091 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3092 Header; /*0x00 */ 3093 U16 3094 Reserved1; /*0x08 */ 3095 U8 3096 Reserved2; /*0x0A */ 3097 U8 3098 Flags; /*0x0B */ 3099 U8 3100 InitialFrame[28]; /*0x0C */ 3101 } MPI2_CONFIG_PAGE_SAS_PHY_4, 3102 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_4, 3103 Mpi2SasPhyPage4_t, *pMpi2SasPhyPage4_t; 3104 3105 #define MPI2_SASPHY4_PAGEVERSION (0x00) 3106 3107 /*values for the Flags field */ 3108 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02) 3109 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01) 3110 3111 3112 3113 3114 /**************************************************************************** 3115 * SAS Port Config Pages 3116 ****************************************************************************/ 3117 3118 /*SAS Port Page 0 */ 3119 3120 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 { 3121 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3122 Header; /*0x00 */ 3123 U8 3124 PortNumber; /*0x08 */ 3125 U8 3126 PhysicalPort; /*0x09 */ 3127 U8 3128 PortWidth; /*0x0A */ 3129 U8 3130 PhysicalPortWidth; /*0x0B */ 3131 U8 3132 ZoneGroup; /*0x0C */ 3133 U8 3134 Reserved1; /*0x0D */ 3135 U16 3136 Reserved2; /*0x0E */ 3137 U64 3138 SASAddress; /*0x10 */ 3139 U32 3140 DeviceInfo; /*0x18 */ 3141 U32 3142 Reserved3; /*0x1C */ 3143 U32 3144 Reserved4; /*0x20 */ 3145 } MPI2_CONFIG_PAGE_SAS_PORT_0, 3146 *PTR_MPI2_CONFIG_PAGE_SAS_PORT_0, 3147 Mpi2SasPortPage0_t, *pMpi2SasPortPage0_t; 3148 3149 #define MPI2_SASPORT0_PAGEVERSION (0x00) 3150 3151 /*see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */ 3152 3153 3154 /**************************************************************************** 3155 * SAS Enclosure Config Pages 3156 ****************************************************************************/ 3157 3158 /*SAS Enclosure Page 0 */ 3159 3160 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 { 3161 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3162 Header; /*0x00 */ 3163 U32 3164 Reserved1; /*0x08 */ 3165 U64 3166 EnclosureLogicalID; /*0x0C */ 3167 U16 3168 Flags; /*0x14 */ 3169 U16 3170 EnclosureHandle; /*0x16 */ 3171 U16 3172 NumSlots; /*0x18 */ 3173 U16 3174 StartSlot; /*0x1A */ 3175 U8 3176 Reserved2; /*0x1C */ 3177 U8 3178 EnclosureLevel; /*0x1D */ 3179 U16 3180 SEPDevHandle; /*0x1E */ 3181 U32 3182 Reserved3; /*0x20 */ 3183 U32 3184 Reserved4; /*0x24 */ 3185 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3186 *PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3187 Mpi2SasEnclosurePage0_t, *pMpi2SasEnclosurePage0_t; 3188 3189 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x04) 3190 3191 /*values for SAS Enclosure Page 0 Flags field */ 3192 #define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010) 3193 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 3194 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3195 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3196 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3197 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3198 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3199 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3200 3201 3202 /**************************************************************************** 3203 * Log Config Page 3204 ****************************************************************************/ 3205 3206 /*Log Page 0 */ 3207 3208 /* 3209 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3210 *one and check the value returned for NumLogEntries at runtime. 3211 */ 3212 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES 3213 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1) 3214 #endif 3215 3216 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C) 3217 3218 typedef struct _MPI2_LOG_0_ENTRY { 3219 U64 TimeStamp; /*0x00 */ 3220 U32 Reserved1; /*0x08 */ 3221 U16 LogSequence; /*0x0C */ 3222 U16 LogEntryQualifier; /*0x0E */ 3223 U8 VP_ID; /*0x10 */ 3224 U8 VF_ID; /*0x11 */ 3225 U16 Reserved2; /*0x12 */ 3226 U8 3227 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/*0x14 */ 3228 } MPI2_LOG_0_ENTRY, *PTR_MPI2_LOG_0_ENTRY, 3229 Mpi2Log0Entry_t, *pMpi2Log0Entry_t; 3230 3231 /*values for Log Page 0 LogEntry LogEntryQualifier field */ 3232 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 3233 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 3234 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002) 3235 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000) 3236 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF) 3237 3238 typedef struct _MPI2_CONFIG_PAGE_LOG_0 { 3239 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3240 U32 Reserved1; /*0x08 */ 3241 U32 Reserved2; /*0x0C */ 3242 U16 NumLogEntries;/*0x10 */ 3243 U16 Reserved3; /*0x12 */ 3244 MPI2_LOG_0_ENTRY 3245 LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /*0x14 */ 3246 } MPI2_CONFIG_PAGE_LOG_0, *PTR_MPI2_CONFIG_PAGE_LOG_0, 3247 Mpi2LogPage0_t, *pMpi2LogPage0_t; 3248 3249 #define MPI2_LOG_0_PAGEVERSION (0x02) 3250 3251 3252 /**************************************************************************** 3253 * RAID Config Page 3254 ****************************************************************************/ 3255 3256 /*RAID Page 0 */ 3257 3258 /* 3259 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3260 *one and check the value returned for NumElements at runtime. 3261 */ 3262 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS 3263 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1) 3264 #endif 3265 3266 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT { 3267 U16 ElementFlags; /*0x00 */ 3268 U16 VolDevHandle; /*0x02 */ 3269 U8 HotSparePool; /*0x04 */ 3270 U8 PhysDiskNum; /*0x05 */ 3271 U16 PhysDiskDevHandle; /*0x06 */ 3272 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3273 *PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3274 Mpi2RaidConfig0ConfigElement_t, 3275 *pMpi2RaidConfig0ConfigElement_t; 3276 3277 /*values for the ElementFlags field */ 3278 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F) 3279 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000) 3280 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001) 3281 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002) 3282 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003) 3283 3284 3285 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 { 3286 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3287 U8 NumHotSpares; /*0x08 */ 3288 U8 NumPhysDisks; /*0x09 */ 3289 U8 NumVolumes; /*0x0A */ 3290 U8 ConfigNum; /*0x0B */ 3291 U32 Flags; /*0x0C */ 3292 U8 ConfigGUID[24]; /*0x10 */ 3293 U32 Reserved1; /*0x28 */ 3294 U8 NumElements; /*0x2C */ 3295 U8 Reserved2; /*0x2D */ 3296 U16 Reserved3; /*0x2E */ 3297 MPI2_RAIDCONFIG0_CONFIG_ELEMENT 3298 ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /*0x30 */ 3299 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3300 *PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3301 Mpi2RaidConfigurationPage0_t, 3302 *pMpi2RaidConfigurationPage0_t; 3303 3304 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00) 3305 3306 /*values for RAID Configuration Page 0 Flags field */ 3307 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001) 3308 3309 3310 /**************************************************************************** 3311 * Driver Persistent Mapping Config Pages 3312 ****************************************************************************/ 3313 3314 /*Driver Persistent Mapping Page 0 */ 3315 3316 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY { 3317 U64 PhysicalIdentifier; /*0x00 */ 3318 U16 MappingInformation; /*0x08 */ 3319 U16 DeviceIndex; /*0x0A */ 3320 U32 PhysicalBitsMapping; /*0x0C */ 3321 U32 Reserved1; /*0x10 */ 3322 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3323 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3324 Mpi2DriverMap0Entry_t, *pMpi2DriverMap0Entry_t; 3325 3326 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 { 3327 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3328 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /*0x08 */ 3329 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3330 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3331 Mpi2DriverMappingPage0_t, *pMpi2DriverMappingPage0_t; 3332 3333 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00) 3334 3335 /*values for Driver Persistent Mapping Page 0 MappingInformation field */ 3336 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0) 3337 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4) 3338 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F) 3339 3340 3341 /**************************************************************************** 3342 * Ethernet Config Pages 3343 ****************************************************************************/ 3344 3345 /*Ethernet Page 0 */ 3346 3347 /*IP address (union of IPv4 and IPv6) */ 3348 typedef union _MPI2_ETHERNET_IP_ADDR { 3349 U32 IPv4Addr; 3350 U32 IPv6Addr[4]; 3351 } MPI2_ETHERNET_IP_ADDR, *PTR_MPI2_ETHERNET_IP_ADDR, 3352 Mpi2EthernetIpAddr_t, *pMpi2EthernetIpAddr_t; 3353 3354 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32) 3355 3356 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 { 3357 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3358 U8 NumInterfaces; /*0x08 */ 3359 U8 Reserved0; /*0x09 */ 3360 U16 Reserved1; /*0x0A */ 3361 U32 Status; /*0x0C */ 3362 U8 MediaState; /*0x10 */ 3363 U8 Reserved2; /*0x11 */ 3364 U16 Reserved3; /*0x12 */ 3365 U8 MacAddress[6]; /*0x14 */ 3366 U8 Reserved4; /*0x1A */ 3367 U8 Reserved5; /*0x1B */ 3368 MPI2_ETHERNET_IP_ADDR IpAddress; /*0x1C */ 3369 MPI2_ETHERNET_IP_ADDR SubnetMask; /*0x2C */ 3370 MPI2_ETHERNET_IP_ADDR GatewayIpAddress;/*0x3C */ 3371 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /*0x4C */ 3372 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /*0x5C */ 3373 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /*0x6C */ 3374 U8 3375 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */ 3376 } MPI2_CONFIG_PAGE_ETHERNET_0, 3377 *PTR_MPI2_CONFIG_PAGE_ETHERNET_0, 3378 Mpi2EthernetPage0_t, *pMpi2EthernetPage0_t; 3379 3380 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00) 3381 3382 /*values for Ethernet Page 0 Status field */ 3383 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000) 3384 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000) 3385 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000) 3386 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100) 3387 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080) 3388 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040) 3389 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020) 3390 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010) 3391 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008) 3392 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004) 3393 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002) 3394 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001) 3395 3396 /*values for Ethernet Page 0 MediaState field */ 3397 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80) 3398 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00) 3399 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80) 3400 3401 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07) 3402 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00) 3403 #define MPI2_ETHPG0_MS_10MBIT (0x01) 3404 #define MPI2_ETHPG0_MS_100MBIT (0x02) 3405 #define MPI2_ETHPG0_MS_1GBIT (0x03) 3406 3407 3408 /*Ethernet Page 1 */ 3409 3410 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 { 3411 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3412 Header; /*0x00 */ 3413 U32 3414 Reserved0; /*0x08 */ 3415 U32 3416 Flags; /*0x0C */ 3417 U8 3418 MediaState; /*0x10 */ 3419 U8 3420 Reserved1; /*0x11 */ 3421 U16 3422 Reserved2; /*0x12 */ 3423 U8 3424 MacAddress[6]; /*0x14 */ 3425 U8 3426 Reserved3; /*0x1A */ 3427 U8 3428 Reserved4; /*0x1B */ 3429 MPI2_ETHERNET_IP_ADDR 3430 StaticIpAddress; /*0x1C */ 3431 MPI2_ETHERNET_IP_ADDR 3432 StaticSubnetMask; /*0x2C */ 3433 MPI2_ETHERNET_IP_ADDR 3434 StaticGatewayIpAddress; /*0x3C */ 3435 MPI2_ETHERNET_IP_ADDR 3436 StaticDNS1IpAddress; /*0x4C */ 3437 MPI2_ETHERNET_IP_ADDR 3438 StaticDNS2IpAddress; /*0x5C */ 3439 U32 3440 Reserved5; /*0x6C */ 3441 U32 3442 Reserved6; /*0x70 */ 3443 U32 3444 Reserved7; /*0x74 */ 3445 U32 3446 Reserved8; /*0x78 */ 3447 U8 3448 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */ 3449 } MPI2_CONFIG_PAGE_ETHERNET_1, 3450 *PTR_MPI2_CONFIG_PAGE_ETHERNET_1, 3451 Mpi2EthernetPage1_t, *pMpi2EthernetPage1_t; 3452 3453 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00) 3454 3455 /*values for Ethernet Page 1 Flags field */ 3456 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100) 3457 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080) 3458 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040) 3459 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020) 3460 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010) 3461 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008) 3462 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004) 3463 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002) 3464 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001) 3465 3466 /*values for Ethernet Page 1 MediaState field */ 3467 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80) 3468 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00) 3469 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80) 3470 3471 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07) 3472 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00) 3473 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01) 3474 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02) 3475 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03) 3476 3477 3478 /**************************************************************************** 3479 * Extended Manufacturing Config Pages 3480 ****************************************************************************/ 3481 3482 /* 3483 *Generic structure to use for product-specific extended manufacturing pages 3484 *(currently Extended Manufacturing Page 40 through Extended Manufacturing 3485 *Page 60). 3486 */ 3487 3488 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS { 3489 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3490 Header; /*0x00 */ 3491 U32 3492 ProductSpecificInfo; /*0x08 */ 3493 } MPI2_CONFIG_PAGE_EXT_MAN_PS, 3494 *PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS, 3495 Mpi2ExtManufacturingPagePS_t, 3496 *pMpi2ExtManufacturingPagePS_t; 3497 3498 /*PageVersion should be provided by product-specific code */ 3499 3500 #endif 3501