1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright 2000-2015 Avago Technologies. All rights reserved. 4 * 5 * 6 * Name: mpi2_cnfg.h 7 * Title: MPI Configuration messages and pages 8 * Creation Date: November 10, 2006 9 * 10 * mpi2_cnfg.h Version: 02.00.42 11 * 12 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 13 * prefix are for use only on MPI v2.5 products, and must not be used 14 * with MPI v2.0 products. Unless otherwise noted, names beginning with 15 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 16 * 17 * Version History 18 * --------------- 19 * 20 * Date Version Description 21 * -------- -------- ------------------------------------------------------ 22 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 23 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags. 24 * Added Manufacturing Page 11. 25 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE 26 * define. 27 * 06-26-07 02.00.02 Adding generic structure for product-specific 28 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS. 29 * Rework of BIOS Page 2 configuration page. 30 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the 31 * forms. 32 * Added configuration pages IOC Page 8 and Driver 33 * Persistent Mapping Page 0. 34 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated 35 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1, 36 * RAID Physical Disk Pages 0 and 1, RAID Configuration 37 * Page 0). 38 * Added new value for AccessStatus field of SAS Device 39 * Page 0 (_SATA_NEEDS_INITIALIZATION). 40 * 10-31-07 02.00.04 Added missing SEPDevHandle field to 41 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 42 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for 43 * NVDATA. 44 * Modified IOC Page 7 to use masks and added field for 45 * SASBroadcastPrimitiveMasks. 46 * Added MPI2_CONFIG_PAGE_BIOS_4. 47 * Added MPI2_CONFIG_PAGE_LOG_0. 48 * 02-29-08 02.00.06 Modified various names to make them 32-character unique. 49 * Added SAS Device IDs. 50 * Updated Integrated RAID configuration pages including 51 * Manufacturing Page 4, IOC Page 6, and RAID Configuration 52 * Page 0. 53 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA. 54 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION. 55 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING. 56 * Added missing MaxNumRoutedSasAddresses field to 57 * MPI2_CONFIG_PAGE_EXPANDER_0. 58 * Added SAS Port Page 0. 59 * Modified structure layout for 60 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0. 61 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use 62 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array. 63 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF 64 * to 0x000000FF. 65 * Added two new values for the Physical Disk Coercion Size 66 * bits in the Flags field of Manufacturing Page 4. 67 * Added product-specific Manufacturing pages 16 to 31. 68 * Modified Flags bits for controlling write cache on SATA 69 * drives in IO Unit Page 1. 70 * Added new bit to AdditionalControlFlags of SAS IO Unit 71 * Page 1 to control Invalid Topology Correction. 72 * Added additional defines for RAID Volume Page 0 73 * VolumeStatusFlags field. 74 * Modified meaning of RAID Volume Page 0 VolumeSettings 75 * define for auto-configure of hot-swap drives. 76 * Added SupportedPhysDisks field to RAID Volume Page 1 and 77 * added related defines. 78 * Added PhysDiskAttributes field (and related defines) to 79 * RAID Physical Disk Page 0. 80 * Added MPI2_SAS_PHYINFO_PHY_VACANT define. 81 * Added three new DiscoveryStatus bits for SAS IO Unit 82 * Page 0 and SAS Expander Page 0. 83 * Removed multiplexing information from SAS IO Unit pages. 84 * Added BootDeviceWaitTime field to SAS IO Unit Page 4. 85 * Removed Zone Address Resolved bit from PhyInfo and from 86 * Expander Page 0 Flags field. 87 * Added two new AccessStatus values to SAS Device Page 0 88 * for indicating routing problems. Added 3 reserved words 89 * to this page. 90 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3. 91 * Inserted missing reserved field into structure for IOC 92 * Page 6. 93 * Added more pending task bits to RAID Volume Page 0 94 * VolumeStatusFlags defines. 95 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define. 96 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0 97 * and SAS Expander Page 0 to flag a downstream initiator 98 * when in simplified routing mode. 99 * Removed SATA Init Failure defines for DiscoveryStatus 100 * fields of SAS IO Unit Page 0 and SAS Expander Page 0. 101 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define. 102 * Added PortGroups, DmaGroup, and ControlGroup fields to 103 * SAS Device Page 0. 104 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO 105 * Unit Page 6. 106 * Added expander reduced functionality data to SAS 107 * Expander Page 0. 108 * Added SAS PHY Page 2 and SAS PHY Page 3. 109 * 07-30-09 02.00.12 Added IO Unit Page 7. 110 * Added new device ids. 111 * Added SAS IO Unit Page 5. 112 * Added partial and slumber power management capable flags 113 * to SAS Device Page 0 Flags field. 114 * Added PhyInfo defines for power condition. 115 * Added Ethernet configuration pages. 116 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY. 117 * Added SAS PHY Page 4 structure and defines. 118 * 02-10-10 02.00.14 Modified the comments for the configuration page 119 * structures that contain an array of data. The host 120 * should use the "count" field in the page data (e.g. the 121 * NumPhys field) to determine the number of valid elements 122 * in the array. 123 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines. 124 * Added PowerManagementCapabilities to IO Unit Page 7. 125 * Added PortWidthModGroup field to 126 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS. 127 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines. 128 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines. 129 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines. 130 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT 131 * define. 132 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define. 133 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define. 134 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing) 135 * defines. 136 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to 137 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for 138 * the Pinout field. 139 * Added BoardTemperature and BoardTemperatureUnits fields 140 * to MPI2_CONFIG_PAGE_IO_UNIT_7. 141 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define 142 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure. 143 * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST. 144 * Added IO Unit Page 8, IO Unit Page 9, 145 * and IO Unit Page 10. 146 * Added SASNotifyPrimitiveMasks field to 147 * MPI2_CONFIG_PAGE_IOC_7. 148 * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec). 149 * 05-25-11 02.00.20 Cleaned up a few comments. 150 * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities 151 * for PCIe link as obsolete. 152 * Added SpinupFlags field containing a Disable Spin-up bit 153 * to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO 154 * Unit Page 4. 155 * 11-18-11 02.00.22 Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT. 156 * Added UEFIVersion field to BIOS Page 1 and defined new 157 * BiosOptions bits. 158 * Incorporating additions for MPI v2.5. 159 * 11-27-12 02.00.23 Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER. 160 * Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID. 161 * 12-20-12 02.00.24 Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as 162 * obsolete for MPI v2.5 and later. 163 * Added some defines for 12G SAS speeds. 164 * 04-09-13 02.00.25 Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK. 165 * Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to 166 * match the specification. 167 * 08-19-13 02.00.26 Added reserved words to MPI2_CONFIG_PAGE_IO_UNIT_7 for 168 * future use. 169 * 12-05-13 02.00.27 Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for 170 * MPI2_CONFIG_PAGE_MAN_7. 171 * Added EnclosureLevel and ConnectorName fields to 172 * MPI2_CONFIG_PAGE_SAS_DEV_0. 173 * Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for 174 * MPI2_CONFIG_PAGE_SAS_DEV_0. 175 * Added EnclosureLevel field to 176 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 177 * Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for 178 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 179 * 01-08-14 02.00.28 Added more defines for the BiosOptions field of 180 * MPI2_CONFIG_PAGE_BIOS_1. 181 * 06-13-14 02.00.29 Added SSUTimeout field to MPI2_CONFIG_PAGE_BIOS_1, and 182 * more defines for the BiosOptions field. 183 * 11-18-14 02.00.30 Updated copyright information. 184 * Added MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG. 185 * Added AdapterOrderAux fields to BIOS Page 3. 186 * 03-16-15 02.00.31 Updated for MPI v2.6. 187 * Added Flags field to IO Unit Page 7. 188 * Added new SAS Phy Event codes 189 * 05-25-15 02.00.33 Added more defines for the BiosOptions field of 190 * MPI2_CONFIG_PAGE_BIOS_1. 191 * 08-25-15 02.00.34 Bumped Header Version. 192 * 12-18-15 02.00.35 Added SATADeviceWaitTime to SAS IO Unit Page 4. 193 * 01-21-16 02.00.36 Added/modified MPI2_MFGPAGE_DEVID_SAS defines. 194 * Added Link field to PCIe Link Pages 195 * Added EnclosureLevel and ConnectorName to PCIe 196 * Device Page 0. 197 * Added define for PCIE IoUnit page 1 max rate shift. 198 * Added comment for reserved ExtPageTypes. 199 * Added SAS 4 22.5 gbs speed support. 200 * Added PCIe 4 16.0 GT/sec speec support. 201 * Removed AHCI support. 202 * Removed SOP support. 203 * Added NegotiatedLinkRate and NegotiatedPortWidth to 204 * PCIe device page 0. 205 * 04-10-16 02.00.37 Fixed MPI2_MFGPAGE_DEVID_SAS3616/3708 defines 206 * 07-01-16 02.00.38 Added Manufacturing page 7 Connector types. 207 * Changed declaration of ConnectorName in PCIe DevicePage0 208 * to match SAS DevicePage 0. 209 * Added SATADeviceWaitTime to IO Unit Page 11. 210 * Added MPI26_MFGPAGE_DEVID_SAS4008 211 * Added x16 PCIe width to IO Unit Page 7 212 * Added LINKFLAGS to control SRIS in PCIe IO Unit page 1 213 * phy data. 214 * Added InitStatus to PCIe IO Unit Page 1 header. 215 * 09-01-16 02.00.39 Added MPI26_CONFIG_PAGE_ENCLOSURE_0 and related defines. 216 * Added MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE and 217 * MPI26_ENCLOS_PGAD_FORM_HANDLE page address formats. 218 * 02-02-17 02.00.40 Added MPI2_MANPAGE7_SLOT_UNKNOWN. 219 * Added ChassisSlot field to SAS Enclosure Page 0. 220 * Added ChassisSlot Valid bit (bit 5) to the Flags field 221 * in SAS Enclosure Page 0. 222 * 06-13-17 02.00.41 Added MPI26_MFGPAGE_DEVID_SAS3816 and 223 * MPI26_MFGPAGE_DEVID_SAS3916 defines. 224 * Removed MPI26_MFGPAGE_DEVID_SAS4008 define. 225 * Added MPI26_PCIEIOUNIT1_LINKFLAGS_SRNS_EN define. 226 * Renamed PI26_PCIEIOUNIT1_LINKFLAGS_EN_SRIS to 227 * PI26_PCIEIOUNIT1_LINKFLAGS_SRIS_EN. 228 * Renamed MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SRIS to 229 * MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SEPARATE_REFCLK. 230 * 09-29-17 02.00.42 Added ControllerResetTO field to PCIe Device Page 2. 231 * Added NOIOB field to PCIe Device Page 2. 232 * Added MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN to 233 * the Capabilities field of PCIe Device Page 2. 234 * -------------------------------------------------------------------------- 235 */ 236 237 #ifndef MPI2_CNFG_H 238 #define MPI2_CNFG_H 239 240 /***************************************************************************** 241 * Configuration Page Header and defines 242 *****************************************************************************/ 243 244 /*Config Page Header */ 245 typedef struct _MPI2_CONFIG_PAGE_HEADER { 246 U8 PageVersion; /*0x00 */ 247 U8 PageLength; /*0x01 */ 248 U8 PageNumber; /*0x02 */ 249 U8 PageType; /*0x03 */ 250 } MPI2_CONFIG_PAGE_HEADER, *PTR_MPI2_CONFIG_PAGE_HEADER, 251 Mpi2ConfigPageHeader_t, *pMpi2ConfigPageHeader_t; 252 253 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION { 254 MPI2_CONFIG_PAGE_HEADER Struct; 255 U8 Bytes[4]; 256 U16 Word16[2]; 257 U32 Word32; 258 } MPI2_CONFIG_PAGE_HEADER_UNION, *PTR_MPI2_CONFIG_PAGE_HEADER_UNION, 259 Mpi2ConfigPageHeaderUnion, *pMpi2ConfigPageHeaderUnion; 260 261 /*Extended Config Page Header */ 262 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER { 263 U8 PageVersion; /*0x00 */ 264 U8 Reserved1; /*0x01 */ 265 U8 PageNumber; /*0x02 */ 266 U8 PageType; /*0x03 */ 267 U16 ExtPageLength; /*0x04 */ 268 U8 ExtPageType; /*0x06 */ 269 U8 Reserved2; /*0x07 */ 270 } MPI2_CONFIG_EXTENDED_PAGE_HEADER, 271 *PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER, 272 Mpi2ConfigExtendedPageHeader_t, 273 *pMpi2ConfigExtendedPageHeader_t; 274 275 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION { 276 MPI2_CONFIG_PAGE_HEADER Struct; 277 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext; 278 U8 Bytes[8]; 279 U16 Word16[4]; 280 U32 Word32[2]; 281 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 282 *PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 283 Mpi2ConfigPageExtendedHeaderUnion, 284 *pMpi2ConfigPageExtendedHeaderUnion; 285 286 287 /*PageType field values */ 288 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 289 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 290 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 291 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0) 292 293 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00) 294 #define MPI2_CONFIG_PAGETYPE_IOC (0x01) 295 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02) 296 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 297 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09) 298 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 299 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F) 300 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F) 301 302 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF) 303 304 305 /*ExtPageType field values */ 306 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 307 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 308 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 309 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 310 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14) 311 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 312 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 313 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 314 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 315 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19) 316 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A) 317 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_IO_UNIT (0x1B) 318 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_SWITCH (0x1C) 319 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_DEVICE (0x1D) 320 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_LINK (0x1E) 321 322 323 /***************************************************************************** 324 * PageAddress defines 325 *****************************************************************************/ 326 327 /*RAID Volume PageAddress format */ 328 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000) 329 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 330 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000) 331 332 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF) 333 334 335 /*RAID Physical Disk PageAddress format */ 336 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000) 337 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000) 338 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000) 339 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000) 340 341 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 342 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF) 343 344 345 /*SAS Expander PageAddress format */ 346 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 347 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 348 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000) 349 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000) 350 351 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) 352 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) 353 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 354 355 356 /*SAS Device PageAddress format */ 357 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 358 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 359 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000) 360 361 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 362 363 364 /*SAS PHY PageAddress format */ 365 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 366 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 367 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000) 368 369 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 370 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 371 372 373 /*SAS Port PageAddress format */ 374 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000) 375 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 376 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 377 378 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF) 379 380 381 /*SAS Enclosure PageAddress format */ 382 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 383 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 384 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 385 386 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 387 388 /*Enclosure PageAddress format */ 389 #define MPI26_ENCLOS_PGAD_FORM_MASK (0xF0000000) 390 #define MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 391 #define MPI26_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 392 393 #define MPI26_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 394 395 /*RAID Configuration PageAddress format */ 396 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000) 397 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000) 398 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000) 399 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000) 400 401 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF) 402 403 404 /*Driver Persistent Mapping PageAddress format */ 405 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000) 406 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000) 407 408 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000) 409 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16) 410 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF) 411 412 413 /*Ethernet PageAddress format */ 414 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000) 415 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000) 416 417 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF) 418 419 420 /*PCIe Switch PageAddress format */ 421 #define MPI26_PCIE_SWITCH_PGAD_FORM_MASK (0xF0000000) 422 #define MPI26_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 423 #define MPI26_PCIE_SWITCH_PGAD_FORM_HNDL_PORTNUM (0x10000000) 424 #define MPI26_PCIE_SWITCH_EXPAND_PGAD_FORM_HNDL (0x20000000) 425 426 #define MPI26_PCIE_SWITCH_PGAD_HANDLE_MASK (0x0000FFFF) 427 #define MPI26_PCIE_SWITCH_PGAD_PORTNUM_MASK (0x00FF0000) 428 #define MPI26_PCIE_SWITCH_PGAD_PORTNUM_SHIFT (16) 429 430 431 /*PCIe Device PageAddress format */ 432 #define MPI26_PCIE_DEVICE_PGAD_FORM_MASK (0xF0000000) 433 #define MPI26_PCIE_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 434 #define MPI26_PCIE_DEVICE_PGAD_FORM_HANDLE (0x20000000) 435 436 #define MPI26_PCIE_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 437 438 /*PCIe Link PageAddress format */ 439 #define MPI26_PCIE_LINK_PGAD_FORM_MASK (0xF0000000) 440 #define MPI26_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK (0x00000000) 441 #define MPI26_PCIE_LINK_PGAD_FORM_LINK_NUM (0x10000000) 442 443 #define MPI26_PCIE_DEVICE_PGAD_LINKNUM_MASK (0x000000FF) 444 445 446 447 /**************************************************************************** 448 * Configuration messages 449 ****************************************************************************/ 450 451 /*Configuration Request Message */ 452 typedef struct _MPI2_CONFIG_REQUEST { 453 U8 Action; /*0x00 */ 454 U8 SGLFlags; /*0x01 */ 455 U8 ChainOffset; /*0x02 */ 456 U8 Function; /*0x03 */ 457 U16 ExtPageLength; /*0x04 */ 458 U8 ExtPageType; /*0x06 */ 459 U8 MsgFlags; /*0x07 */ 460 U8 VP_ID; /*0x08 */ 461 U8 VF_ID; /*0x09 */ 462 U16 Reserved1; /*0x0A */ 463 U8 Reserved2; /*0x0C */ 464 U8 ProxyVF_ID; /*0x0D */ 465 U16 Reserved4; /*0x0E */ 466 U32 Reserved3; /*0x10 */ 467 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */ 468 U32 PageAddress; /*0x18 */ 469 MPI2_SGE_IO_UNION PageBufferSGE; /*0x1C */ 470 } MPI2_CONFIG_REQUEST, *PTR_MPI2_CONFIG_REQUEST, 471 Mpi2ConfigRequest_t, *pMpi2ConfigRequest_t; 472 473 /*values for the Action field */ 474 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00) 475 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 476 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 477 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03) 478 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 479 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 480 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 481 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07) 482 483 /*use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */ 484 485 486 /*Config Reply Message */ 487 typedef struct _MPI2_CONFIG_REPLY { 488 U8 Action; /*0x00 */ 489 U8 SGLFlags; /*0x01 */ 490 U8 MsgLength; /*0x02 */ 491 U8 Function; /*0x03 */ 492 U16 ExtPageLength; /*0x04 */ 493 U8 ExtPageType; /*0x06 */ 494 U8 MsgFlags; /*0x07 */ 495 U8 VP_ID; /*0x08 */ 496 U8 VF_ID; /*0x09 */ 497 U16 Reserved1; /*0x0A */ 498 U16 Reserved2; /*0x0C */ 499 U16 IOCStatus; /*0x0E */ 500 U32 IOCLogInfo; /*0x10 */ 501 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */ 502 } MPI2_CONFIG_REPLY, *PTR_MPI2_CONFIG_REPLY, 503 Mpi2ConfigReply_t, *pMpi2ConfigReply_t; 504 505 506 507 /***************************************************************************** 508 * 509 * C o n f i g u r a t i o n P a g e s 510 * 511 *****************************************************************************/ 512 513 /**************************************************************************** 514 * Manufacturing Config pages 515 ****************************************************************************/ 516 517 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000) 518 519 /*MPI v2.0 SAS products */ 520 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070) 521 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072) 522 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074) 523 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076) 524 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077) 525 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064) 526 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065) 527 528 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E) 529 530 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080) 531 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081) 532 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082) 533 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083) 534 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084) 535 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085) 536 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086) 537 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087) 538 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E) 539 #define MPI2_MFGPAGE_DEVID_SAS2308_MPI_EP (0x02B0) 540 541 /*MPI v2.5 SAS products */ 542 #define MPI25_MFGPAGE_DEVID_SAS3004 (0x0096) 543 #define MPI25_MFGPAGE_DEVID_SAS3008 (0x0097) 544 #define MPI25_MFGPAGE_DEVID_SAS3108_1 (0x0090) 545 #define MPI25_MFGPAGE_DEVID_SAS3108_2 (0x0091) 546 #define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094) 547 #define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095) 548 549 /* MPI v2.6 SAS Products */ 550 #define MPI26_MFGPAGE_DEVID_SAS3216 (0x00C9) 551 #define MPI26_MFGPAGE_DEVID_SAS3224 (0x00C4) 552 #define MPI26_MFGPAGE_DEVID_SAS3316_1 (0x00C5) 553 #define MPI26_MFGPAGE_DEVID_SAS3316_2 (0x00C6) 554 #define MPI26_MFGPAGE_DEVID_SAS3316_3 (0x00C7) 555 #define MPI26_MFGPAGE_DEVID_SAS3316_4 (0x00C8) 556 #define MPI26_MFGPAGE_DEVID_SAS3324_1 (0x00C0) 557 #define MPI26_MFGPAGE_DEVID_SAS3324_2 (0x00C1) 558 #define MPI26_MFGPAGE_DEVID_SAS3324_3 (0x00C2) 559 #define MPI26_MFGPAGE_DEVID_SAS3324_4 (0x00C3) 560 561 #define MPI26_MFGPAGE_DEVID_SAS3516 (0x00AA) 562 #define MPI26_MFGPAGE_DEVID_SAS3516_1 (0x00AB) 563 #define MPI26_MFGPAGE_DEVID_SAS3416 (0x00AC) 564 #define MPI26_MFGPAGE_DEVID_SAS3508 (0x00AD) 565 #define MPI26_MFGPAGE_DEVID_SAS3508_1 (0x00AE) 566 #define MPI26_MFGPAGE_DEVID_SAS3408 (0x00AF) 567 #define MPI26_MFGPAGE_DEVID_SAS3716 (0x00D0) 568 #define MPI26_MFGPAGE_DEVID_SAS3616 (0x00D1) 569 #define MPI26_MFGPAGE_DEVID_SAS3708 (0x00D2) 570 571 #define MPI26_MFGPAGE_DEVID_SAS3816 (0x00A1) 572 #define MPI26_MFGPAGE_DEVID_SAS3916 (0x00A0) 573 574 575 /*Manufacturing Page 0 */ 576 577 typedef struct _MPI2_CONFIG_PAGE_MAN_0 { 578 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 579 U8 ChipName[16]; /*0x04 */ 580 U8 ChipRevision[8]; /*0x14 */ 581 U8 BoardName[16]; /*0x1C */ 582 U8 BoardAssembly[16]; /*0x2C */ 583 U8 BoardTracerNumber[16]; /*0x3C */ 584 } MPI2_CONFIG_PAGE_MAN_0, 585 *PTR_MPI2_CONFIG_PAGE_MAN_0, 586 Mpi2ManufacturingPage0_t, 587 *pMpi2ManufacturingPage0_t; 588 589 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00) 590 591 592 /*Manufacturing Page 1 */ 593 594 typedef struct _MPI2_CONFIG_PAGE_MAN_1 { 595 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 596 U8 VPD[256]; /*0x04 */ 597 } MPI2_CONFIG_PAGE_MAN_1, 598 *PTR_MPI2_CONFIG_PAGE_MAN_1, 599 Mpi2ManufacturingPage1_t, 600 *pMpi2ManufacturingPage1_t; 601 602 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00) 603 604 605 typedef struct _MPI2_CHIP_REVISION_ID { 606 U16 DeviceID; /*0x00 */ 607 U8 PCIRevisionID; /*0x02 */ 608 U8 Reserved; /*0x03 */ 609 } MPI2_CHIP_REVISION_ID, *PTR_MPI2_CHIP_REVISION_ID, 610 Mpi2ChipRevisionId_t, *pMpi2ChipRevisionId_t; 611 612 613 /*Manufacturing Page 2 */ 614 615 /* 616 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 617 *one and check Header.PageLength at runtime. 618 */ 619 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS 620 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 621 #endif 622 623 typedef struct _MPI2_CONFIG_PAGE_MAN_2 { 624 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 625 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */ 626 U32 627 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/*0x08 */ 628 } MPI2_CONFIG_PAGE_MAN_2, 629 *PTR_MPI2_CONFIG_PAGE_MAN_2, 630 Mpi2ManufacturingPage2_t, 631 *pMpi2ManufacturingPage2_t; 632 633 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00) 634 635 636 /*Manufacturing Page 3 */ 637 638 /* 639 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 640 *one and check Header.PageLength at runtime. 641 */ 642 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS 643 #define MPI2_MAN_PAGE_3_INFO_WORDS (1) 644 #endif 645 646 typedef struct _MPI2_CONFIG_PAGE_MAN_3 { 647 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 648 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */ 649 U32 650 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/*0x08 */ 651 } MPI2_CONFIG_PAGE_MAN_3, 652 *PTR_MPI2_CONFIG_PAGE_MAN_3, 653 Mpi2ManufacturingPage3_t, 654 *pMpi2ManufacturingPage3_t; 655 656 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00) 657 658 659 /*Manufacturing Page 4 */ 660 661 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS { 662 U8 PowerSaveFlags; /*0x00 */ 663 U8 InternalOperationsSleepTime; /*0x01 */ 664 U8 InternalOperationsRunTime; /*0x02 */ 665 U8 HostIdleTime; /*0x03 */ 666 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 667 *PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 668 Mpi2ManPage4PwrSaveSettings_t, 669 *pMpi2ManPage4PwrSaveSettings_t; 670 671 /*defines for the PowerSaveFlags field */ 672 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03) 673 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00) 674 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01) 675 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02) 676 677 typedef struct _MPI2_CONFIG_PAGE_MAN_4 { 678 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 679 U32 Reserved1; /*0x04 */ 680 U32 Flags; /*0x08 */ 681 U8 InquirySize; /*0x0C */ 682 U8 Reserved2; /*0x0D */ 683 U16 Reserved3; /*0x0E */ 684 U8 InquiryData[56]; /*0x10 */ 685 U32 RAID0VolumeSettings; /*0x48 */ 686 U32 RAID1EVolumeSettings; /*0x4C */ 687 U32 RAID1VolumeSettings; /*0x50 */ 688 U32 RAID10VolumeSettings; /*0x54 */ 689 U32 Reserved4; /*0x58 */ 690 U32 Reserved5; /*0x5C */ 691 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /*0x60 */ 692 U8 MaxOCEDisks; /*0x64 */ 693 U8 ResyncRate; /*0x65 */ 694 U16 DataScrubDuration; /*0x66 */ 695 U8 MaxHotSpares; /*0x68 */ 696 U8 MaxPhysDisksPerVol; /*0x69 */ 697 U8 MaxPhysDisks; /*0x6A */ 698 U8 MaxVolumes; /*0x6B */ 699 } MPI2_CONFIG_PAGE_MAN_4, 700 *PTR_MPI2_CONFIG_PAGE_MAN_4, 701 Mpi2ManufacturingPage4_t, 702 *pMpi2ManufacturingPage4_t; 703 704 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A) 705 706 /*Manufacturing Page 4 Flags field */ 707 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000) 708 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000) 709 710 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000) 711 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000) 712 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000) 713 714 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00) 715 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000) 716 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400) 717 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800) 718 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00) 719 720 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300) 721 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000) 722 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100) 723 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200) 724 725 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080) 726 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040) 727 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020) 728 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010) 729 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008) 730 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004) 731 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002) 732 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001) 733 734 735 /*Manufacturing Page 5 */ 736 737 /* 738 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 739 *one and check the value returned for NumPhys at runtime. 740 */ 741 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES 742 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1) 743 #endif 744 745 typedef struct _MPI2_MANUFACTURING5_ENTRY { 746 U64 WWID; /*0x00 */ 747 U64 DeviceName; /*0x08 */ 748 } MPI2_MANUFACTURING5_ENTRY, 749 *PTR_MPI2_MANUFACTURING5_ENTRY, 750 Mpi2Manufacturing5Entry_t, 751 *pMpi2Manufacturing5Entry_t; 752 753 typedef struct _MPI2_CONFIG_PAGE_MAN_5 { 754 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 755 U8 NumPhys; /*0x04 */ 756 U8 Reserved1; /*0x05 */ 757 U16 Reserved2; /*0x06 */ 758 U32 Reserved3; /*0x08 */ 759 U32 Reserved4; /*0x0C */ 760 MPI2_MANUFACTURING5_ENTRY 761 Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/*0x08 */ 762 } MPI2_CONFIG_PAGE_MAN_5, 763 *PTR_MPI2_CONFIG_PAGE_MAN_5, 764 Mpi2ManufacturingPage5_t, 765 *pMpi2ManufacturingPage5_t; 766 767 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03) 768 769 770 /*Manufacturing Page 6 */ 771 772 typedef struct _MPI2_CONFIG_PAGE_MAN_6 { 773 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 774 U32 ProductSpecificInfo;/*0x04 */ 775 } MPI2_CONFIG_PAGE_MAN_6, 776 *PTR_MPI2_CONFIG_PAGE_MAN_6, 777 Mpi2ManufacturingPage6_t, 778 *pMpi2ManufacturingPage6_t; 779 780 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00) 781 782 783 /*Manufacturing Page 7 */ 784 785 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO { 786 U32 Pinout; /*0x00 */ 787 U8 Connector[16]; /*0x04 */ 788 U8 Location; /*0x14 */ 789 U8 ReceptacleID; /*0x15 */ 790 U16 Slot; /*0x16 */ 791 U32 Reserved2; /*0x18 */ 792 } MPI2_MANPAGE7_CONNECTOR_INFO, 793 *PTR_MPI2_MANPAGE7_CONNECTOR_INFO, 794 Mpi2ManPage7ConnectorInfo_t, 795 *pMpi2ManPage7ConnectorInfo_t; 796 797 /*defines for the Pinout field */ 798 #define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00) 799 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8) 800 801 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF) 802 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00) 803 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01) 804 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02) 805 #define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03) 806 #define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04) 807 #define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05) 808 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06) 809 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07) 810 #define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08) 811 #define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09) 812 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A) 813 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B) 814 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C) 815 #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D) 816 #define MPI2_MANPAGE7_PINOUT_SFF_8088_A (0x0E) 817 #define MPI2_MANPAGE7_PINOUT_SFF_8643_16i (0x0F) 818 #define MPI2_MANPAGE7_PINOUT_SFF_8654_4i (0x10) 819 #define MPI2_MANPAGE7_PINOUT_SFF_8654_8i (0x11) 820 #define MPI2_MANPAGE7_PINOUT_SFF_8611_4i (0x12) 821 #define MPI2_MANPAGE7_PINOUT_SFF_8611_8i (0x13) 822 823 /*defines for the Location field */ 824 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01) 825 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02) 826 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04) 827 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08) 828 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10) 829 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 830 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 831 832 /*defines for the Slot field */ 833 #define MPI2_MANPAGE7_SLOT_UNKNOWN (0xFFFF) 834 835 /* 836 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 837 *one and check the value returned for NumPhys at runtime. 838 */ 839 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX 840 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1) 841 #endif 842 843 typedef struct _MPI2_CONFIG_PAGE_MAN_7 { 844 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 845 U32 Reserved1; /*0x04 */ 846 U32 Reserved2; /*0x08 */ 847 U32 Flags; /*0x0C */ 848 U8 EnclosureName[16]; /*0x10 */ 849 U8 NumPhys; /*0x20 */ 850 U8 Reserved3; /*0x21 */ 851 U16 Reserved4; /*0x22 */ 852 MPI2_MANPAGE7_CONNECTOR_INFO 853 ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /*0x24 */ 854 } MPI2_CONFIG_PAGE_MAN_7, 855 *PTR_MPI2_CONFIG_PAGE_MAN_7, 856 Mpi2ManufacturingPage7_t, 857 *pMpi2ManufacturingPage7_t; 858 859 #define MPI2_MANUFACTURING7_PAGEVERSION (0x01) 860 861 /*defines for the Flags field */ 862 #define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL (0x00000008) 863 #define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER (0x00000002) 864 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 865 866 867 /* 868 *Generic structure to use for product-specific manufacturing pages 869 *(currently Manufacturing Page 8 through Manufacturing Page 31). 870 */ 871 872 typedef struct _MPI2_CONFIG_PAGE_MAN_PS { 873 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 874 U32 ProductSpecificInfo;/*0x04 */ 875 } MPI2_CONFIG_PAGE_MAN_PS, 876 *PTR_MPI2_CONFIG_PAGE_MAN_PS, 877 Mpi2ManufacturingPagePS_t, 878 *pMpi2ManufacturingPagePS_t; 879 880 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00) 881 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00) 882 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00) 883 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00) 884 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00) 885 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00) 886 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00) 887 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00) 888 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00) 889 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00) 890 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00) 891 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00) 892 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00) 893 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00) 894 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00) 895 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00) 896 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00) 897 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00) 898 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00) 899 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00) 900 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00) 901 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00) 902 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00) 903 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00) 904 905 906 /**************************************************************************** 907 * IO Unit Config Pages 908 ****************************************************************************/ 909 910 /*IO Unit Page 0 */ 911 912 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 { 913 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 914 U64 UniqueValue; /*0x04 */ 915 MPI2_VERSION_UNION NvdataVersionDefault; /*0x08 */ 916 MPI2_VERSION_UNION NvdataVersionPersistent; /*0x0A */ 917 } MPI2_CONFIG_PAGE_IO_UNIT_0, 918 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_0, 919 Mpi2IOUnitPage0_t, *pMpi2IOUnitPage0_t; 920 921 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02) 922 923 924 /*IO Unit Page 1 */ 925 926 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 { 927 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 928 U32 Flags; /*0x04 */ 929 } MPI2_CONFIG_PAGE_IO_UNIT_1, 930 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_1, 931 Mpi2IOUnitPage1_t, *pMpi2IOUnitPage1_t; 932 933 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04) 934 935 /*IO Unit Page 1 Flags defines */ 936 #define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK (0x00004000) 937 #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000) 938 #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000) 939 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800) 940 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600) 941 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9) 942 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000) 943 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200) 944 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400) 945 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 946 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040) 947 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020) 948 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 949 950 951 /*IO Unit Page 3 */ 952 953 /* 954 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 955 *one and check the value returned for GPIOCount at runtime. 956 */ 957 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX 958 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 959 #endif 960 961 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 { 962 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 963 U8 GPIOCount; /*0x04 */ 964 U8 Reserved1; /*0x05 */ 965 U16 Reserved2; /*0x06 */ 966 U16 967 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/*0x08 */ 968 } MPI2_CONFIG_PAGE_IO_UNIT_3, 969 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_3, 970 Mpi2IOUnitPage3_t, *pMpi2IOUnitPage3_t; 971 972 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01) 973 974 /*defines for IO Unit Page 3 GPIOVal field */ 975 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC) 976 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 977 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000) 978 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001) 979 980 981 /*IO Unit Page 5 */ 982 983 /* 984 *Upper layer code (drivers, utilities, etc.) should leave this define set to 985 *one and check the value returned for NumDmaEngines at runtime. 986 */ 987 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES 988 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1) 989 #endif 990 991 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 { 992 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 993 U64 994 RaidAcceleratorBufferBaseAddress; /*0x04 */ 995 U64 996 RaidAcceleratorBufferSize; /*0x0C */ 997 U64 998 RaidAcceleratorControlBaseAddress; /*0x14 */ 999 U8 RAControlSize; /*0x1C */ 1000 U8 NumDmaEngines; /*0x1D */ 1001 U8 RAMinControlSize; /*0x1E */ 1002 U8 RAMaxControlSize; /*0x1F */ 1003 U32 Reserved1; /*0x20 */ 1004 U32 Reserved2; /*0x24 */ 1005 U32 Reserved3; /*0x28 */ 1006 U32 1007 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /*0x2C */ 1008 } MPI2_CONFIG_PAGE_IO_UNIT_5, 1009 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_5, 1010 Mpi2IOUnitPage5_t, *pMpi2IOUnitPage5_t; 1011 1012 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00) 1013 1014 /*defines for IO Unit Page 5 DmaEngineCapabilities field */ 1015 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFFFF0000) 1016 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16) 1017 1018 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008) 1019 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004) 1020 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002) 1021 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001) 1022 1023 1024 /*IO Unit Page 6 */ 1025 1026 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 { 1027 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1028 U16 Flags; /*0x04 */ 1029 U8 RAHostControlSize; /*0x06 */ 1030 U8 Reserved0; /*0x07 */ 1031 U64 1032 RaidAcceleratorHostControlBaseAddress; /*0x08 */ 1033 U32 Reserved1; /*0x10 */ 1034 U32 Reserved2; /*0x14 */ 1035 U32 Reserved3; /*0x18 */ 1036 } MPI2_CONFIG_PAGE_IO_UNIT_6, 1037 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_6, 1038 Mpi2IOUnitPage6_t, *pMpi2IOUnitPage6_t; 1039 1040 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00) 1041 1042 /*defines for IO Unit Page 6 Flags field */ 1043 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001) 1044 1045 1046 /*IO Unit Page 7 */ 1047 1048 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 { 1049 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1050 U8 CurrentPowerMode; /*0x04 */ 1051 U8 PreviousPowerMode; /*0x05 */ 1052 U8 PCIeWidth; /*0x06 */ 1053 U8 PCIeSpeed; /*0x07 */ 1054 U32 ProcessorState; /*0x08 */ 1055 U32 1056 PowerManagementCapabilities; /*0x0C */ 1057 U16 IOCTemperature; /*0x10 */ 1058 U8 1059 IOCTemperatureUnits; /*0x12 */ 1060 U8 IOCSpeed; /*0x13 */ 1061 U16 BoardTemperature; /*0x14 */ 1062 U8 1063 BoardTemperatureUnits; /*0x16 */ 1064 U8 Reserved3; /*0x17 */ 1065 U32 BoardPowerRequirement; /*0x18 */ 1066 U32 PCISlotPowerAllocation; /*0x1C */ 1067 /* reserved prior to MPI v2.6 */ 1068 U8 Flags; /* 0x20 */ 1069 U8 Reserved6; /* 0x21 */ 1070 U16 Reserved7; /* 0x22 */ 1071 U32 Reserved8; /* 0x24 */ 1072 } MPI2_CONFIG_PAGE_IO_UNIT_7, 1073 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_7, 1074 Mpi2IOUnitPage7_t, *pMpi2IOUnitPage7_t; 1075 1076 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x05) 1077 1078 /*defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */ 1079 #define MPI25_IOUNITPAGE7_PM_INIT_MASK (0xC0) 1080 #define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE (0x00) 1081 #define MPI25_IOUNITPAGE7_PM_INIT_HOST (0x40) 1082 #define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT (0x80) 1083 #define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA (0xC0) 1084 1085 #define MPI25_IOUNITPAGE7_PM_MODE_MASK (0x07) 1086 #define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE (0x00) 1087 #define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN (0x01) 1088 #define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER (0x04) 1089 #define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER (0x05) 1090 #define MPI25_IOUNITPAGE7_PM_MODE_STANDBY (0x06) 1091 1092 1093 /*defines for IO Unit Page 7 PCIeWidth field */ 1094 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01) 1095 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02) 1096 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04) 1097 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08) 1098 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X16 (0x10) 1099 1100 /*defines for IO Unit Page 7 PCIeSpeed field */ 1101 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00) 1102 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01) 1103 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02) 1104 #define MPI2_IOUNITPAGE7_PCIE_SPEED_16_0_GBPS (0x03) 1105 1106 /*defines for IO Unit Page 7 ProcessorState field */ 1107 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F) 1108 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0) 1109 1110 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00) 1111 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01) 1112 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02) 1113 1114 /*defines for IO Unit Page 7 PowerManagementCapabilities field */ 1115 #define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE (0x00400000) 1116 #define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE (0x00200000) 1117 #define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE (0x00100000) 1118 #define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE (0x00040000) 1119 #define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE (0x00020000) 1120 #define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE (0x00010000) 1121 #define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE (0x00004000) 1122 #define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE (0x00002000) 1123 #define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE (0x00001000) 1124 #define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED (0x00000400) 1125 #define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED (0x00000200) 1126 #define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED (0x00000100) 1127 #define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED (0x00000040) 1128 #define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED (0x00000020) 1129 #define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED (0x00000010) 1130 #define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE (0x00000008) 1131 #define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE (0x00000004) 1132 #define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE (0x00000002) 1133 #define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE (0x00000001) 1134 1135 /*obsolete names for the PowerManagementCapabilities bits (above) */ 1136 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400) 1137 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200) 1138 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100) 1139 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /*obsolete */ 1140 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /*obsolete */ 1141 1142 1143 /*defines for IO Unit Page 7 IOCTemperatureUnits field */ 1144 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00) 1145 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01) 1146 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02) 1147 1148 /*defines for IO Unit Page 7 IOCSpeed field */ 1149 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01) 1150 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02) 1151 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04) 1152 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08) 1153 1154 /*defines for IO Unit Page 7 BoardTemperatureUnits field */ 1155 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00) 1156 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01) 1157 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02) 1158 1159 /* defines for IO Unit Page 7 Flags field */ 1160 #define MPI2_IOUNITPAGE7_FLAG_CABLE_POWER_EXC (0x01) 1161 1162 /*IO Unit Page 8 */ 1163 1164 #define MPI2_IOUNIT8_NUM_THRESHOLDS (4) 1165 1166 typedef struct _MPI2_IOUNIT8_SENSOR { 1167 U16 Flags; /*0x00 */ 1168 U16 Reserved1; /*0x02 */ 1169 U16 1170 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /*0x04 */ 1171 U32 Reserved2; /*0x0C */ 1172 U32 Reserved3; /*0x10 */ 1173 U32 Reserved4; /*0x14 */ 1174 } MPI2_IOUNIT8_SENSOR, *PTR_MPI2_IOUNIT8_SENSOR, 1175 Mpi2IOUnit8Sensor_t, *pMpi2IOUnit8Sensor_t; 1176 1177 /*defines for IO Unit Page 8 Sensor Flags field */ 1178 #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008) 1179 #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004) 1180 #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002) 1181 #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001) 1182 1183 /* 1184 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1185 *one and check the value returned for NumSensors at runtime. 1186 */ 1187 #ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES 1188 #define MPI2_IOUNITPAGE8_SENSOR_ENTRIES (1) 1189 #endif 1190 1191 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 { 1192 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1193 U32 Reserved1; /*0x04 */ 1194 U32 Reserved2; /*0x08 */ 1195 U8 NumSensors; /*0x0C */ 1196 U8 PollingInterval; /*0x0D */ 1197 U16 Reserved3; /*0x0E */ 1198 MPI2_IOUNIT8_SENSOR 1199 Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/*0x10 */ 1200 } MPI2_CONFIG_PAGE_IO_UNIT_8, 1201 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_8, 1202 Mpi2IOUnitPage8_t, *pMpi2IOUnitPage8_t; 1203 1204 #define MPI2_IOUNITPAGE8_PAGEVERSION (0x00) 1205 1206 1207 /*IO Unit Page 9 */ 1208 1209 typedef struct _MPI2_IOUNIT9_SENSOR { 1210 U16 CurrentTemperature; /*0x00 */ 1211 U16 Reserved1; /*0x02 */ 1212 U8 Flags; /*0x04 */ 1213 U8 Reserved2; /*0x05 */ 1214 U16 Reserved3; /*0x06 */ 1215 U32 Reserved4; /*0x08 */ 1216 U32 Reserved5; /*0x0C */ 1217 } MPI2_IOUNIT9_SENSOR, *PTR_MPI2_IOUNIT9_SENSOR, 1218 Mpi2IOUnit9Sensor_t, *pMpi2IOUnit9Sensor_t; 1219 1220 /*defines for IO Unit Page 9 Sensor Flags field */ 1221 #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01) 1222 1223 /* 1224 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1225 *one and check the value returned for NumSensors at runtime. 1226 */ 1227 #ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES 1228 #define MPI2_IOUNITPAGE9_SENSOR_ENTRIES (1) 1229 #endif 1230 1231 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 { 1232 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1233 U32 Reserved1; /*0x04 */ 1234 U32 Reserved2; /*0x08 */ 1235 U8 NumSensors; /*0x0C */ 1236 U8 Reserved4; /*0x0D */ 1237 U16 Reserved3; /*0x0E */ 1238 MPI2_IOUNIT9_SENSOR 1239 Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/*0x10 */ 1240 } MPI2_CONFIG_PAGE_IO_UNIT_9, 1241 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_9, 1242 Mpi2IOUnitPage9_t, *pMpi2IOUnitPage9_t; 1243 1244 #define MPI2_IOUNITPAGE9_PAGEVERSION (0x00) 1245 1246 1247 /*IO Unit Page 10 */ 1248 1249 typedef struct _MPI2_IOUNIT10_FUNCTION { 1250 U8 CreditPercent; /*0x00 */ 1251 U8 Reserved1; /*0x01 */ 1252 U16 Reserved2; /*0x02 */ 1253 } MPI2_IOUNIT10_FUNCTION, 1254 *PTR_MPI2_IOUNIT10_FUNCTION, 1255 Mpi2IOUnit10Function_t, 1256 *pMpi2IOUnit10Function_t; 1257 1258 /* 1259 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1260 *one and check the value returned for NumFunctions at runtime. 1261 */ 1262 #ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES 1263 #define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES (1) 1264 #endif 1265 1266 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 { 1267 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1268 U8 NumFunctions; /*0x04 */ 1269 U8 Reserved1; /*0x05 */ 1270 U16 Reserved2; /*0x06 */ 1271 U32 Reserved3; /*0x08 */ 1272 U32 Reserved4; /*0x0C */ 1273 MPI2_IOUNIT10_FUNCTION 1274 Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];/*0x10 */ 1275 } MPI2_CONFIG_PAGE_IO_UNIT_10, 1276 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_10, 1277 Mpi2IOUnitPage10_t, *pMpi2IOUnitPage10_t; 1278 1279 #define MPI2_IOUNITPAGE10_PAGEVERSION (0x01) 1280 1281 1282 /* IO Unit Page 11 (for MPI v2.6 and later) */ 1283 1284 typedef struct _MPI26_IOUNIT11_SPINUP_GROUP { 1285 U8 MaxTargetSpinup; /* 0x00 */ 1286 U8 SpinupDelay; /* 0x01 */ 1287 U8 SpinupFlags; /* 0x02 */ 1288 U8 Reserved1; /* 0x03 */ 1289 } MPI26_IOUNIT11_SPINUP_GROUP, 1290 *PTR_MPI26_IOUNIT11_SPINUP_GROUP, 1291 Mpi26IOUnit11SpinupGroup_t, 1292 *pMpi26IOUnit11SpinupGroup_t; 1293 1294 /* defines for IO Unit Page 11 SpinupFlags */ 1295 #define MPI26_IOUNITPAGE11_SPINUP_DISABLE_FLAG (0x01) 1296 1297 1298 /* 1299 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1300 * four and check the value returned for NumPhys at runtime. 1301 */ 1302 #ifndef MPI26_IOUNITPAGE11_PHY_MAX 1303 #define MPI26_IOUNITPAGE11_PHY_MAX (4) 1304 #endif 1305 1306 typedef struct _MPI26_CONFIG_PAGE_IO_UNIT_11 { 1307 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1308 U32 Reserved1; /*0x04 */ 1309 MPI26_IOUNIT11_SPINUP_GROUP SpinupGroupParameters[4]; /*0x08 */ 1310 U32 Reserved2; /*0x18 */ 1311 U32 Reserved3; /*0x1C */ 1312 U32 Reserved4; /*0x20 */ 1313 U8 BootDeviceWaitTime; /*0x24 */ 1314 U8 Reserved5; /*0x25 */ 1315 U16 Reserved6; /*0x26 */ 1316 U8 NumPhys; /*0x28 */ 1317 U8 PEInitialSpinupDelay; /*0x29 */ 1318 U8 PEReplyDelay; /*0x2A */ 1319 U8 Flags; /*0x2B */ 1320 U8 PHY[MPI26_IOUNITPAGE11_PHY_MAX];/*0x2C */ 1321 } MPI26_CONFIG_PAGE_IO_UNIT_11, 1322 *PTR_MPI26_CONFIG_PAGE_IO_UNIT_11, 1323 Mpi26IOUnitPage11_t, 1324 *pMpi26IOUnitPage11_t; 1325 1326 #define MPI26_IOUNITPAGE11_PAGEVERSION (0x00) 1327 1328 /* defines for Flags field */ 1329 #define MPI26_IOUNITPAGE11_FLAGS_AUTO_PORTENABLE (0x01) 1330 1331 /* defines for PHY field */ 1332 #define MPI26_IOUNITPAGE11_PHY_SPINUP_GROUP_MASK (0x03) 1333 1334 1335 1336 1337 1338 1339 /**************************************************************************** 1340 * IOC Config Pages 1341 ****************************************************************************/ 1342 1343 /*IOC Page 0 */ 1344 1345 typedef struct _MPI2_CONFIG_PAGE_IOC_0 { 1346 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1347 U32 Reserved1; /*0x04 */ 1348 U32 Reserved2; /*0x08 */ 1349 U16 VendorID; /*0x0C */ 1350 U16 DeviceID; /*0x0E */ 1351 U8 RevisionID; /*0x10 */ 1352 U8 Reserved3; /*0x11 */ 1353 U16 Reserved4; /*0x12 */ 1354 U32 ClassCode; /*0x14 */ 1355 U16 SubsystemVendorID; /*0x18 */ 1356 U16 SubsystemID; /*0x1A */ 1357 } MPI2_CONFIG_PAGE_IOC_0, 1358 *PTR_MPI2_CONFIG_PAGE_IOC_0, 1359 Mpi2IOCPage0_t, *pMpi2IOCPage0_t; 1360 1361 #define MPI2_IOCPAGE0_PAGEVERSION (0x02) 1362 1363 1364 /*IOC Page 1 */ 1365 1366 typedef struct _MPI2_CONFIG_PAGE_IOC_1 { 1367 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1368 U32 Flags; /*0x04 */ 1369 U32 CoalescingTimeout; /*0x08 */ 1370 U8 CoalescingDepth; /*0x0C */ 1371 U8 PCISlotNum; /*0x0D */ 1372 U8 PCIBusNum; /*0x0E */ 1373 U8 PCIDomainSegment; /*0x0F */ 1374 U32 Reserved1; /*0x10 */ 1375 U32 Reserved2; /*0x14 */ 1376 } MPI2_CONFIG_PAGE_IOC_1, 1377 *PTR_MPI2_CONFIG_PAGE_IOC_1, 1378 Mpi2IOCPage1_t, *pMpi2IOCPage1_t; 1379 1380 #define MPI2_IOCPAGE1_PAGEVERSION (0x05) 1381 1382 /*defines for IOC Page 1 Flags field */ 1383 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001) 1384 1385 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 1386 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF) 1387 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF) 1388 1389 /*IOC Page 6 */ 1390 1391 typedef struct _MPI2_CONFIG_PAGE_IOC_6 { 1392 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1393 U32 1394 CapabilitiesFlags; /*0x04 */ 1395 U8 MaxDrivesRAID0; /*0x08 */ 1396 U8 MaxDrivesRAID1; /*0x09 */ 1397 U8 1398 MaxDrivesRAID1E; /*0x0A */ 1399 U8 1400 MaxDrivesRAID10; /*0x0B */ 1401 U8 MinDrivesRAID0; /*0x0C */ 1402 U8 MinDrivesRAID1; /*0x0D */ 1403 U8 1404 MinDrivesRAID1E; /*0x0E */ 1405 U8 1406 MinDrivesRAID10; /*0x0F */ 1407 U32 Reserved1; /*0x10 */ 1408 U8 1409 MaxGlobalHotSpares; /*0x14 */ 1410 U8 MaxPhysDisks; /*0x15 */ 1411 U8 MaxVolumes; /*0x16 */ 1412 U8 MaxConfigs; /*0x17 */ 1413 U8 MaxOCEDisks; /*0x18 */ 1414 U8 Reserved2; /*0x19 */ 1415 U16 Reserved3; /*0x1A */ 1416 U32 1417 SupportedStripeSizeMapRAID0; /*0x1C */ 1418 U32 1419 SupportedStripeSizeMapRAID1E; /*0x20 */ 1420 U32 1421 SupportedStripeSizeMapRAID10; /*0x24 */ 1422 U32 Reserved4; /*0x28 */ 1423 U32 Reserved5; /*0x2C */ 1424 U16 1425 DefaultMetadataSize; /*0x30 */ 1426 U16 Reserved6; /*0x32 */ 1427 U16 1428 MaxBadBlockTableEntries; /*0x34 */ 1429 U16 Reserved7; /*0x36 */ 1430 U32 1431 IRNvsramVersion; /*0x38 */ 1432 } MPI2_CONFIG_PAGE_IOC_6, 1433 *PTR_MPI2_CONFIG_PAGE_IOC_6, 1434 Mpi2IOCPage6_t, *pMpi2IOCPage6_t; 1435 1436 #define MPI2_IOCPAGE6_PAGEVERSION (0x05) 1437 1438 /*defines for IOC Page 6 CapabilitiesFlags */ 1439 #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT (0x00000020) 1440 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010) 1441 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008) 1442 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004) 1443 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002) 1444 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 1445 1446 1447 /*IOC Page 7 */ 1448 1449 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4) 1450 1451 typedef struct _MPI2_CONFIG_PAGE_IOC_7 { 1452 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1453 U32 Reserved1; /*0x04 */ 1454 U32 1455 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/*0x08 */ 1456 U16 SASBroadcastPrimitiveMasks; /*0x18 */ 1457 U16 SASNotifyPrimitiveMasks; /*0x1A */ 1458 U32 Reserved3; /*0x1C */ 1459 } MPI2_CONFIG_PAGE_IOC_7, 1460 *PTR_MPI2_CONFIG_PAGE_IOC_7, 1461 Mpi2IOCPage7_t, *pMpi2IOCPage7_t; 1462 1463 #define MPI2_IOCPAGE7_PAGEVERSION (0x02) 1464 1465 1466 /*IOC Page 8 */ 1467 1468 typedef struct _MPI2_CONFIG_PAGE_IOC_8 { 1469 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1470 U8 NumDevsPerEnclosure; /*0x04 */ 1471 U8 Reserved1; /*0x05 */ 1472 U16 Reserved2; /*0x06 */ 1473 U16 MaxPersistentEntries; /*0x08 */ 1474 U16 MaxNumPhysicalMappedIDs; /*0x0A */ 1475 U16 Flags; /*0x0C */ 1476 U16 Reserved3; /*0x0E */ 1477 U16 IRVolumeMappingFlags; /*0x10 */ 1478 U16 Reserved4; /*0x12 */ 1479 U32 Reserved5; /*0x14 */ 1480 } MPI2_CONFIG_PAGE_IOC_8, 1481 *PTR_MPI2_CONFIG_PAGE_IOC_8, 1482 Mpi2IOCPage8_t, *pMpi2IOCPage8_t; 1483 1484 #define MPI2_IOCPAGE8_PAGEVERSION (0x00) 1485 1486 /*defines for IOC Page 8 Flags field */ 1487 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020) 1488 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010) 1489 1490 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E) 1491 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000) 1492 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002) 1493 1494 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001) 1495 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000) 1496 1497 /*defines for IOC Page 8 IRVolumeMappingFlags */ 1498 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003) 1499 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000) 1500 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001) 1501 1502 1503 /**************************************************************************** 1504 * BIOS Config Pages 1505 ****************************************************************************/ 1506 1507 /*BIOS Page 1 */ 1508 1509 typedef struct _MPI2_CONFIG_PAGE_BIOS_1 { 1510 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1511 U32 BiosOptions; /*0x04 */ 1512 U32 IOCSettings; /*0x08 */ 1513 U8 SSUTimeout; /*0x0C */ 1514 U8 Reserved1; /*0x0D */ 1515 U16 Reserved2; /*0x0E */ 1516 U32 DeviceSettings; /*0x10 */ 1517 U16 NumberOfDevices; /*0x14 */ 1518 U16 UEFIVersion; /*0x16 */ 1519 U16 IOTimeoutBlockDevicesNonRM; /*0x18 */ 1520 U16 IOTimeoutSequential; /*0x1A */ 1521 U16 IOTimeoutOther; /*0x1C */ 1522 U16 IOTimeoutBlockDevicesRM; /*0x1E */ 1523 } MPI2_CONFIG_PAGE_BIOS_1, 1524 *PTR_MPI2_CONFIG_PAGE_BIOS_1, 1525 Mpi2BiosPage1_t, *pMpi2BiosPage1_t; 1526 1527 #define MPI2_BIOSPAGE1_PAGEVERSION (0x07) 1528 1529 /*values for BIOS Page 1 BiosOptions field */ 1530 #define MPI2_BIOSPAGE1_OPTIONS_BOOT_LIST_ADD_ALT_BOOT_DEVICE (0x00008000) 1531 #define MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG (0x00004000) 1532 1533 #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800) 1534 #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800) 1535 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL (0x00000000) 1536 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE (0x00000800) 1537 #define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID (0x00001000) 1538 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PSENS (0x00001800) 1539 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ESPHY (0x00002000) 1540 1541 #define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS (0x00000400) 1542 1543 #define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD (0x00000300) 1544 #define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD (0x00000000) 1545 #define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD (0x00000100) 1546 #define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD (0x00000200) 1547 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD (0x00000300) 1548 1549 #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0) 1550 #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000) 1551 1552 #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006) 1553 #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000) 1554 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002) 1555 #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004) 1556 1557 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1558 1559 /*values for BIOS Page 1 IOCSettings field */ 1560 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1561 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1562 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1563 1564 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1565 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1566 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1567 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1568 1569 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1570 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1571 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1572 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1573 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1574 1575 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1576 1577 /*values for BIOS Page 1 DeviceSettings field */ 1578 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 1579 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1580 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1581 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1582 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1583 1584 /*defines for BIOS Page 1 UEFIVersion field */ 1585 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK (0xFF00) 1586 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT (8) 1587 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK (0x00FF) 1588 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT (0) 1589 1590 1591 1592 /*BIOS Page 2 */ 1593 1594 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER { 1595 U32 Reserved1; /*0x00 */ 1596 U32 Reserved2; /*0x04 */ 1597 U32 Reserved3; /*0x08 */ 1598 U32 Reserved4; /*0x0C */ 1599 U32 Reserved5; /*0x10 */ 1600 U32 Reserved6; /*0x14 */ 1601 } MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1602 *PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1603 Mpi2BootDeviceAdapterOrder_t, 1604 *pMpi2BootDeviceAdapterOrder_t; 1605 1606 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID { 1607 U64 SASAddress; /*0x00 */ 1608 U8 LUN[8]; /*0x08 */ 1609 U32 Reserved1; /*0x10 */ 1610 U32 Reserved2; /*0x14 */ 1611 } MPI2_BOOT_DEVICE_SAS_WWID, 1612 *PTR_MPI2_BOOT_DEVICE_SAS_WWID, 1613 Mpi2BootDeviceSasWwid_t, 1614 *pMpi2BootDeviceSasWwid_t; 1615 1616 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT { 1617 U64 EnclosureLogicalID; /*0x00 */ 1618 U32 Reserved1; /*0x08 */ 1619 U32 Reserved2; /*0x0C */ 1620 U16 SlotNumber; /*0x10 */ 1621 U16 Reserved3; /*0x12 */ 1622 U32 Reserved4; /*0x14 */ 1623 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1624 *PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1625 Mpi2BootDeviceEnclosureSlot_t, 1626 *pMpi2BootDeviceEnclosureSlot_t; 1627 1628 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME { 1629 U64 DeviceName; /*0x00 */ 1630 U8 LUN[8]; /*0x08 */ 1631 U32 Reserved1; /*0x10 */ 1632 U32 Reserved2; /*0x14 */ 1633 } MPI2_BOOT_DEVICE_DEVICE_NAME, 1634 *PTR_MPI2_BOOT_DEVICE_DEVICE_NAME, 1635 Mpi2BootDeviceDeviceName_t, 1636 *pMpi2BootDeviceDeviceName_t; 1637 1638 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE { 1639 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1640 MPI2_BOOT_DEVICE_SAS_WWID SasWwid; 1641 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1642 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName; 1643 } MPI2_BIOSPAGE2_BOOT_DEVICE, 1644 *PTR_MPI2_BIOSPAGE2_BOOT_DEVICE, 1645 Mpi2BiosPage2BootDevice_t, 1646 *pMpi2BiosPage2BootDevice_t; 1647 1648 typedef struct _MPI2_CONFIG_PAGE_BIOS_2 { 1649 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1650 U32 Reserved1; /*0x04 */ 1651 U32 Reserved2; /*0x08 */ 1652 U32 Reserved3; /*0x0C */ 1653 U32 Reserved4; /*0x10 */ 1654 U32 Reserved5; /*0x14 */ 1655 U32 Reserved6; /*0x18 */ 1656 U8 ReqBootDeviceForm; /*0x1C */ 1657 U8 Reserved7; /*0x1D */ 1658 U16 Reserved8; /*0x1E */ 1659 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /*0x20 */ 1660 U8 ReqAltBootDeviceForm; /*0x38 */ 1661 U8 Reserved9; /*0x39 */ 1662 U16 Reserved10; /*0x3A */ 1663 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /*0x3C */ 1664 U8 CurrentBootDeviceForm; /*0x58 */ 1665 U8 Reserved11; /*0x59 */ 1666 U16 Reserved12; /*0x5A */ 1667 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /*0x58 */ 1668 } MPI2_CONFIG_PAGE_BIOS_2, *PTR_MPI2_CONFIG_PAGE_BIOS_2, 1669 Mpi2BiosPage2_t, *pMpi2BiosPage2_t; 1670 1671 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04) 1672 1673 /*values for BIOS Page 2 BootDeviceForm fields */ 1674 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F) 1675 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00) 1676 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05) 1677 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1678 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07) 1679 1680 1681 /*BIOS Page 3 */ 1682 1683 #define MPI2_BIOSPAGE3_NUM_ADAPTER (4) 1684 1685 typedef struct _MPI2_ADAPTER_INFO { 1686 U8 PciBusNumber; /*0x00 */ 1687 U8 PciDeviceAndFunctionNumber; /*0x01 */ 1688 U16 AdapterFlags; /*0x02 */ 1689 } MPI2_ADAPTER_INFO, *PTR_MPI2_ADAPTER_INFO, 1690 Mpi2AdapterInfo_t, *pMpi2AdapterInfo_t; 1691 1692 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 1693 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 1694 1695 typedef struct _MPI2_ADAPTER_ORDER_AUX { 1696 U64 WWID; /* 0x00 */ 1697 U32 Reserved1; /* 0x08 */ 1698 U32 Reserved2; /* 0x0C */ 1699 } MPI2_ADAPTER_ORDER_AUX, *PTR_MPI2_ADAPTER_ORDER_AUX, 1700 Mpi2AdapterOrderAux_t, *pMpi2AdapterOrderAux_t; 1701 1702 1703 typedef struct _MPI2_CONFIG_PAGE_BIOS_3 { 1704 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1705 U32 GlobalFlags; /*0x04 */ 1706 U32 BiosVersion; /*0x08 */ 1707 MPI2_ADAPTER_INFO AdapterOrder[MPI2_BIOSPAGE3_NUM_ADAPTER]; 1708 U32 Reserved1; /*0x1C */ 1709 MPI2_ADAPTER_ORDER_AUX AdapterOrderAux[MPI2_BIOSPAGE3_NUM_ADAPTER]; 1710 } MPI2_CONFIG_PAGE_BIOS_3, 1711 *PTR_MPI2_CONFIG_PAGE_BIOS_3, 1712 Mpi2BiosPage3_t, *pMpi2BiosPage3_t; 1713 1714 #define MPI2_BIOSPAGE3_PAGEVERSION (0x01) 1715 1716 /*values for BIOS Page 3 GlobalFlags */ 1717 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) 1718 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004) 1719 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010) 1720 1721 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 1722 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 1723 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020) 1724 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 1725 1726 1727 /*BIOS Page 4 */ 1728 1729 /* 1730 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1731 *one and check the value returned for NumPhys at runtime. 1732 */ 1733 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES 1734 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1) 1735 #endif 1736 1737 typedef struct _MPI2_BIOS4_ENTRY { 1738 U64 ReassignmentWWID; /*0x00 */ 1739 U64 ReassignmentDeviceName; /*0x08 */ 1740 } MPI2_BIOS4_ENTRY, *PTR_MPI2_BIOS4_ENTRY, 1741 Mpi2MBios4Entry_t, *pMpi2Bios4Entry_t; 1742 1743 typedef struct _MPI2_CONFIG_PAGE_BIOS_4 { 1744 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1745 U8 NumPhys; /*0x04 */ 1746 U8 Reserved1; /*0x05 */ 1747 U16 Reserved2; /*0x06 */ 1748 MPI2_BIOS4_ENTRY 1749 Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /*0x08 */ 1750 } MPI2_CONFIG_PAGE_BIOS_4, *PTR_MPI2_CONFIG_PAGE_BIOS_4, 1751 Mpi2BiosPage4_t, *pMpi2BiosPage4_t; 1752 1753 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01) 1754 1755 1756 /**************************************************************************** 1757 * RAID Volume Config Pages 1758 ****************************************************************************/ 1759 1760 /*RAID Volume Page 0 */ 1761 1762 typedef struct _MPI2_RAIDVOL0_PHYS_DISK { 1763 U8 RAIDSetNum; /*0x00 */ 1764 U8 PhysDiskMap; /*0x01 */ 1765 U8 PhysDiskNum; /*0x02 */ 1766 U8 Reserved; /*0x03 */ 1767 } MPI2_RAIDVOL0_PHYS_DISK, *PTR_MPI2_RAIDVOL0_PHYS_DISK, 1768 Mpi2RaidVol0PhysDisk_t, *pMpi2RaidVol0PhysDisk_t; 1769 1770 /*defines for the PhysDiskMap field */ 1771 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1772 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1773 1774 typedef struct _MPI2_RAIDVOL0_SETTINGS { 1775 U16 Settings; /*0x00 */ 1776 U8 HotSparePool; /*0x01 */ 1777 U8 Reserved; /*0x02 */ 1778 } MPI2_RAIDVOL0_SETTINGS, *PTR_MPI2_RAIDVOL0_SETTINGS, 1779 Mpi2RaidVol0Settings_t, 1780 *pMpi2RaidVol0Settings_t; 1781 1782 /*RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1783 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01) 1784 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02) 1785 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04) 1786 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08) 1787 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10) 1788 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20) 1789 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40) 1790 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80) 1791 1792 /*RAID Volume Page 0 VolumeSettings defines */ 1793 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008) 1794 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004) 1795 1796 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003) 1797 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000) 1798 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001) 1799 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002) 1800 1801 /* 1802 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1803 *one and check the value returned for NumPhysDisks at runtime. 1804 */ 1805 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX 1806 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 1807 #endif 1808 1809 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 { 1810 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1811 U16 DevHandle; /*0x04 */ 1812 U8 VolumeState; /*0x06 */ 1813 U8 VolumeType; /*0x07 */ 1814 U32 VolumeStatusFlags; /*0x08 */ 1815 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /*0x0C */ 1816 U64 MaxLBA; /*0x10 */ 1817 U32 StripeSize; /*0x18 */ 1818 U16 BlockSize; /*0x1C */ 1819 U16 Reserved1; /*0x1E */ 1820 U8 SupportedPhysDisks;/*0x20 */ 1821 U8 ResyncRate; /*0x21 */ 1822 U16 DataScrubDuration; /*0x22 */ 1823 U8 NumPhysDisks; /*0x24 */ 1824 U8 Reserved2; /*0x25 */ 1825 U8 Reserved3; /*0x26 */ 1826 U8 InactiveStatus; /*0x27 */ 1827 MPI2_RAIDVOL0_PHYS_DISK 1828 PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /*0x28 */ 1829 } MPI2_CONFIG_PAGE_RAID_VOL_0, 1830 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_0, 1831 Mpi2RaidVolPage0_t, *pMpi2RaidVolPage0_t; 1832 1833 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A) 1834 1835 /*values for RAID VolumeState */ 1836 #define MPI2_RAID_VOL_STATE_MISSING (0x00) 1837 #define MPI2_RAID_VOL_STATE_FAILED (0x01) 1838 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02) 1839 #define MPI2_RAID_VOL_STATE_ONLINE (0x03) 1840 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04) 1841 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05) 1842 1843 /*values for RAID VolumeType */ 1844 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00) 1845 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01) 1846 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02) 1847 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05) 1848 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF) 1849 1850 /*values for RAID Volume Page 0 VolumeStatusFlags field */ 1851 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000) 1852 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000) 1853 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000) 1854 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000) 1855 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000) 1856 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000) 1857 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000) 1858 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000) 1859 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000) 1860 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000) 1861 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080) 1862 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040) 1863 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020) 1864 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000) 1865 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010) 1866 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008) 1867 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004) 1868 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002) 1869 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001) 1870 1871 /*values for RAID Volume Page 0 SupportedPhysDisks field */ 1872 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08) 1873 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04) 1874 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02) 1875 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01) 1876 1877 /*values for RAID Volume Page 0 InactiveStatus field */ 1878 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 1879 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 1880 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 1881 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 1882 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 1883 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 1884 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 1885 1886 1887 /*RAID Volume Page 1 */ 1888 1889 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 { 1890 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1891 U16 DevHandle; /*0x04 */ 1892 U16 Reserved0; /*0x06 */ 1893 U8 GUID[24]; /*0x08 */ 1894 U8 Name[16]; /*0x20 */ 1895 U64 WWID; /*0x30 */ 1896 U32 Reserved1; /*0x38 */ 1897 U32 Reserved2; /*0x3C */ 1898 } MPI2_CONFIG_PAGE_RAID_VOL_1, 1899 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_1, 1900 Mpi2RaidVolPage1_t, *pMpi2RaidVolPage1_t; 1901 1902 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03) 1903 1904 1905 /**************************************************************************** 1906 * RAID Physical Disk Config Pages 1907 ****************************************************************************/ 1908 1909 /*RAID Physical Disk Page 0 */ 1910 1911 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS { 1912 U16 Reserved1; /*0x00 */ 1913 U8 HotSparePool; /*0x02 */ 1914 U8 Reserved2; /*0x03 */ 1915 } MPI2_RAIDPHYSDISK0_SETTINGS, 1916 *PTR_MPI2_RAIDPHYSDISK0_SETTINGS, 1917 Mpi2RaidPhysDisk0Settings_t, 1918 *pMpi2RaidPhysDisk0Settings_t; 1919 1920 /*use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */ 1921 1922 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA { 1923 U8 VendorID[8]; /*0x00 */ 1924 U8 ProductID[16]; /*0x08 */ 1925 U8 ProductRevLevel[4]; /*0x18 */ 1926 U8 SerialNum[32]; /*0x1C */ 1927 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1928 *PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1929 Mpi2RaidPhysDisk0InquiryData_t, 1930 *pMpi2RaidPhysDisk0InquiryData_t; 1931 1932 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 { 1933 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1934 U16 DevHandle; /*0x04 */ 1935 U8 Reserved1; /*0x06 */ 1936 U8 PhysDiskNum; /*0x07 */ 1937 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /*0x08 */ 1938 U32 Reserved2; /*0x0C */ 1939 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /*0x10 */ 1940 U32 Reserved3; /*0x4C */ 1941 U8 PhysDiskState; /*0x50 */ 1942 U8 OfflineReason; /*0x51 */ 1943 U8 IncompatibleReason; /*0x52 */ 1944 U8 PhysDiskAttributes; /*0x53 */ 1945 U32 PhysDiskStatusFlags;/*0x54 */ 1946 U64 DeviceMaxLBA; /*0x58 */ 1947 U64 HostMaxLBA; /*0x60 */ 1948 U64 CoercedMaxLBA; /*0x68 */ 1949 U16 BlockSize; /*0x70 */ 1950 U16 Reserved5; /*0x72 */ 1951 U32 Reserved6; /*0x74 */ 1952 } MPI2_CONFIG_PAGE_RD_PDISK_0, 1953 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_0, 1954 Mpi2RaidPhysDiskPage0_t, 1955 *pMpi2RaidPhysDiskPage0_t; 1956 1957 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05) 1958 1959 /*PhysDiskState defines */ 1960 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00) 1961 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01) 1962 #define MPI2_RAID_PD_STATE_OFFLINE (0x02) 1963 #define MPI2_RAID_PD_STATE_ONLINE (0x03) 1964 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04) 1965 #define MPI2_RAID_PD_STATE_DEGRADED (0x05) 1966 #define MPI2_RAID_PD_STATE_REBUILDING (0x06) 1967 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07) 1968 1969 /*OfflineReason defines */ 1970 #define MPI2_PHYSDISK0_ONLINE (0x00) 1971 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01) 1972 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03) 1973 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04) 1974 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05) 1975 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06) 1976 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF) 1977 1978 /*IncompatibleReason defines */ 1979 #define MPI2_PHYSDISK0_COMPATIBLE (0x00) 1980 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01) 1981 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02) 1982 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03) 1983 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04) 1984 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05) 1985 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06) 1986 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF) 1987 1988 /*PhysDiskAttributes defines */ 1989 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C) 1990 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08) 1991 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04) 1992 1993 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03) 1994 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02) 1995 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01) 1996 1997 /*PhysDiskStatusFlags defines */ 1998 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040) 1999 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020) 2000 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010) 2001 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000) 2002 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008) 2003 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004) 2004 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002) 2005 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001) 2006 2007 2008 /*RAID Physical Disk Page 1 */ 2009 2010 /* 2011 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2012 *one and check the value returned for NumPhysDiskPaths at runtime. 2013 */ 2014 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX 2015 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1) 2016 #endif 2017 2018 typedef struct _MPI2_RAIDPHYSDISK1_PATH { 2019 U16 DevHandle; /*0x00 */ 2020 U16 Reserved1; /*0x02 */ 2021 U64 WWID; /*0x04 */ 2022 U64 OwnerWWID; /*0x0C */ 2023 U8 OwnerIdentifier; /*0x14 */ 2024 U8 Reserved2; /*0x15 */ 2025 U16 Flags; /*0x16 */ 2026 } MPI2_RAIDPHYSDISK1_PATH, *PTR_MPI2_RAIDPHYSDISK1_PATH, 2027 Mpi2RaidPhysDisk1Path_t, 2028 *pMpi2RaidPhysDisk1Path_t; 2029 2030 /*RAID Physical Disk Page 1 Physical Disk Path Flags field defines */ 2031 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004) 2032 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 2033 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 2034 2035 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 { 2036 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 2037 U8 NumPhysDiskPaths; /*0x04 */ 2038 U8 PhysDiskNum; /*0x05 */ 2039 U16 Reserved1; /*0x06 */ 2040 U32 Reserved2; /*0x08 */ 2041 MPI2_RAIDPHYSDISK1_PATH 2042 PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/*0x0C */ 2043 } MPI2_CONFIG_PAGE_RD_PDISK_1, 2044 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_1, 2045 Mpi2RaidPhysDiskPage1_t, 2046 *pMpi2RaidPhysDiskPage1_t; 2047 2048 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02) 2049 2050 2051 /**************************************************************************** 2052 * values for fields used by several types of SAS Config Pages 2053 ****************************************************************************/ 2054 2055 /*values for NegotiatedLinkRates fields */ 2056 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0) 2057 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4) 2058 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 2059 /*link rates used for Negotiated Physical and Logical Link Rate */ 2060 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 2061 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 2062 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 2063 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 2064 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 2065 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 2066 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 2067 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08) 2068 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09) 2069 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A) 2070 #define MPI25_SAS_NEG_LINK_RATE_12_0 (0x0B) 2071 #define MPI26_SAS_NEG_LINK_RATE_22_5 (0x0C) 2072 2073 2074 /*values for AttachedPhyInfo fields */ 2075 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 2076 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 2077 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 2078 2079 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F) 2080 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 2081 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 2082 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 2083 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 2084 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 2085 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 2086 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 2087 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 2088 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 2089 2090 2091 /*values for PhyInfo fields */ 2092 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000) 2093 2094 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 2095 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27) 2096 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000) 2097 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000) 2098 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000) 2099 2100 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000) 2101 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000) 2102 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000) 2103 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 2104 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000) 2105 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 2106 2107 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000) 2108 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 2109 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 2110 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 2111 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 2112 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 2113 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 2114 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 2115 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 2116 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 2117 2118 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000) 2119 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 2120 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 2121 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 2122 2123 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 2124 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 2125 2126 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 2127 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000) 2128 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 2129 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020) 2130 2131 2132 /*values for SAS ProgrammedLinkRate fields */ 2133 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0) 2134 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 2135 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80) 2136 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90) 2137 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0) 2138 #define MPI25_SAS_PRATE_MAX_RATE_12_0 (0xB0) 2139 #define MPI26_SAS_PRATE_MAX_RATE_22_5 (0xC0) 2140 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F) 2141 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 2142 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08) 2143 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09) 2144 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A) 2145 #define MPI25_SAS_PRATE_MIN_RATE_12_0 (0x0B) 2146 #define MPI26_SAS_PRATE_MIN_RATE_22_5 (0x0C) 2147 2148 2149 /*values for SAS HwLinkRate fields */ 2150 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0) 2151 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80) 2152 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90) 2153 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0) 2154 #define MPI25_SAS_HWRATE_MAX_RATE_12_0 (0xB0) 2155 #define MPI26_SAS_HWRATE_MAX_RATE_22_5 (0xC0) 2156 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F) 2157 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08) 2158 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09) 2159 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A) 2160 #define MPI25_SAS_HWRATE_MIN_RATE_12_0 (0x0B) 2161 #define MPI26_SAS_HWRATE_MIN_RATE_22_5 (0x0C) 2162 2163 2164 2165 /**************************************************************************** 2166 * SAS IO Unit Config Pages 2167 ****************************************************************************/ 2168 2169 /*SAS IO Unit Page 0 */ 2170 2171 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA { 2172 U8 Port; /*0x00 */ 2173 U8 PortFlags; /*0x01 */ 2174 U8 PhyFlags; /*0x02 */ 2175 U8 NegotiatedLinkRate; /*0x03 */ 2176 U32 ControllerPhyDeviceInfo;/*0x04 */ 2177 U16 AttachedDevHandle; /*0x08 */ 2178 U16 ControllerDevHandle; /*0x0A */ 2179 U32 DiscoveryStatus; /*0x0C */ 2180 U32 Reserved; /*0x10 */ 2181 } MPI2_SAS_IO_UNIT0_PHY_DATA, 2182 *PTR_MPI2_SAS_IO_UNIT0_PHY_DATA, 2183 Mpi2SasIOUnit0PhyData_t, 2184 *pMpi2SasIOUnit0PhyData_t; 2185 2186 /* 2187 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2188 *one and check the value returned for NumPhys at runtime. 2189 */ 2190 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX 2191 #define MPI2_SAS_IOUNIT0_PHY_MAX (1) 2192 #endif 2193 2194 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 { 2195 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2196 U32 Reserved1;/*0x08 */ 2197 U8 NumPhys; /*0x0C */ 2198 U8 Reserved2;/*0x0D */ 2199 U16 Reserved3;/*0x0E */ 2200 MPI2_SAS_IO_UNIT0_PHY_DATA 2201 PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /*0x10 */ 2202 } MPI2_CONFIG_PAGE_SASIOUNIT_0, 2203 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0, 2204 Mpi2SasIOUnitPage0_t, *pMpi2SasIOUnitPage0_t; 2205 2206 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05) 2207 2208 /*values for SAS IO Unit Page 0 PortFlags */ 2209 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08) 2210 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) 2211 2212 /*values for SAS IO Unit Page 0 PhyFlags */ 2213 #define MPI2_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2214 #define MPI2_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2215 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) 2216 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 2217 2218 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2219 2220 /*see mpi2_sas.h for values for 2221 *SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 2222 2223 /*values for SAS IO Unit Page 0 DiscoveryStatus */ 2224 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2225 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2226 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000) 2227 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2228 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2229 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2230 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2231 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 2232 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2233 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 2234 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400) 2235 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 2236 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 2237 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 2238 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 2239 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2240 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010) 2241 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 2242 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2243 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001) 2244 2245 2246 /*SAS IO Unit Page 1 */ 2247 2248 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA { 2249 U8 Port; /*0x00 */ 2250 U8 PortFlags; /*0x01 */ 2251 U8 PhyFlags; /*0x02 */ 2252 U8 MaxMinLinkRate; /*0x03 */ 2253 U32 ControllerPhyDeviceInfo; /*0x04 */ 2254 U16 MaxTargetPortConnectTime; /*0x08 */ 2255 U16 Reserved1; /*0x0A */ 2256 } MPI2_SAS_IO_UNIT1_PHY_DATA, 2257 *PTR_MPI2_SAS_IO_UNIT1_PHY_DATA, 2258 Mpi2SasIOUnit1PhyData_t, 2259 *pMpi2SasIOUnit1PhyData_t; 2260 2261 /* 2262 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2263 *one and check the value returned for NumPhys at runtime. 2264 */ 2265 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX 2266 #define MPI2_SAS_IOUNIT1_PHY_MAX (1) 2267 #endif 2268 2269 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 { 2270 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2271 U16 2272 ControlFlags; /*0x08 */ 2273 U16 2274 SASNarrowMaxQueueDepth; /*0x0A */ 2275 U16 2276 AdditionalControlFlags; /*0x0C */ 2277 U16 2278 SASWideMaxQueueDepth; /*0x0E */ 2279 U8 2280 NumPhys; /*0x10 */ 2281 U8 2282 SATAMaxQDepth; /*0x11 */ 2283 U8 2284 ReportDeviceMissingDelay; /*0x12 */ 2285 U8 2286 IODeviceMissingDelay; /*0x13 */ 2287 MPI2_SAS_IO_UNIT1_PHY_DATA 2288 PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /*0x14 */ 2289 } MPI2_CONFIG_PAGE_SASIOUNIT_1, 2290 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1, 2291 Mpi2SasIOUnitPage1_t, *pMpi2SasIOUnitPage1_t; 2292 2293 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09) 2294 2295 /*values for SAS IO Unit Page 1 ControlFlags */ 2296 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 2297 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 2298 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) 2299 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 2300 2301 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 2302 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 2303 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0) 2304 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1) 2305 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2) 2306 2307 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 2308 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 2309 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 2310 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 2311 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 2312 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 2313 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 2314 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) 2315 2316 /*values for SAS IO Unit Page 1 AdditionalControlFlags */ 2317 #define MPI2_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100) 2318 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 2319 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 2320 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 2321 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 2322 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 2323 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 2324 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 2325 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 2326 2327 /*defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 2328 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 2329 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 2330 2331 /*values for SAS IO Unit Page 1 PortFlags */ 2332 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2333 2334 /*values for SAS IO Unit Page 1 PhyFlags */ 2335 #define MPI2_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2336 #define MPI2_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2337 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) 2338 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 2339 2340 /*values for SAS IO Unit Page 1 MaxMinLinkRate */ 2341 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) 2342 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) 2343 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) 2344 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) 2345 #define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0) 2346 #define MPI26_SASIOUNIT1_MAX_RATE_22_5 (0xC0) 2347 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) 2348 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) 2349 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) 2350 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) 2351 #define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B) 2352 #define MPI26_SASIOUNIT1_MIN_RATE_22_5 (0x0C) 2353 2354 /*see mpi2_sas.h for values for 2355 *SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 2356 2357 2358 /*SAS IO Unit Page 4 (for MPI v2.5 and earlier) */ 2359 2360 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP { 2361 U8 MaxTargetSpinup; /*0x00 */ 2362 U8 SpinupDelay; /*0x01 */ 2363 U8 SpinupFlags; /*0x02 */ 2364 U8 Reserved1; /*0x03 */ 2365 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, 2366 *PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP, 2367 Mpi2SasIOUnit4SpinupGroup_t, 2368 *pMpi2SasIOUnit4SpinupGroup_t; 2369 /*defines for SAS IO Unit Page 4 SpinupFlags */ 2370 #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01) 2371 2372 2373 /* 2374 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2375 *one and check the value returned for NumPhys at runtime. 2376 */ 2377 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX 2378 #define MPI2_SAS_IOUNIT4_PHY_MAX (4) 2379 #endif 2380 2381 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 { 2382 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header;/*0x00 */ 2383 MPI2_SAS_IOUNIT4_SPINUP_GROUP 2384 SpinupGroupParameters[4]; /*0x08 */ 2385 U32 2386 Reserved1; /*0x18 */ 2387 U32 2388 Reserved2; /*0x1C */ 2389 U32 2390 Reserved3; /*0x20 */ 2391 U8 2392 BootDeviceWaitTime; /*0x24 */ 2393 U8 2394 SATADeviceWaitTime; /*0x25 */ 2395 U16 2396 Reserved5; /*0x26 */ 2397 U8 2398 NumPhys; /*0x28 */ 2399 U8 2400 PEInitialSpinupDelay; /*0x29 */ 2401 U8 2402 PEReplyDelay; /*0x2A */ 2403 U8 2404 Flags; /*0x2B */ 2405 U8 2406 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /*0x2C */ 2407 } MPI2_CONFIG_PAGE_SASIOUNIT_4, 2408 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4, 2409 Mpi2SasIOUnitPage4_t, *pMpi2SasIOUnitPage4_t; 2410 2411 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02) 2412 2413 /*defines for Flags field */ 2414 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01) 2415 2416 /*defines for PHY field */ 2417 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03) 2418 2419 2420 /*SAS IO Unit Page 5 */ 2421 2422 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS { 2423 U8 ControlFlags; /*0x00 */ 2424 U8 PortWidthModGroup; /*0x01 */ 2425 U16 InactivityTimerExponent; /*0x02 */ 2426 U8 SATAPartialTimeout; /*0x04 */ 2427 U8 Reserved2; /*0x05 */ 2428 U8 SATASlumberTimeout; /*0x06 */ 2429 U8 Reserved3; /*0x07 */ 2430 U8 SASPartialTimeout; /*0x08 */ 2431 U8 Reserved4; /*0x09 */ 2432 U8 SASSlumberTimeout; /*0x0A */ 2433 U8 Reserved5; /*0x0B */ 2434 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2435 *PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2436 Mpi2SasIOUnit5PhyPmSettings_t, 2437 *pMpi2SasIOUnit5PhyPmSettings_t; 2438 2439 /*defines for ControlFlags field */ 2440 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08) 2441 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04) 2442 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02) 2443 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01) 2444 2445 /*defines for PortWidthModeGroup field */ 2446 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF) 2447 2448 /*defines for InactivityTimerExponent field */ 2449 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000) 2450 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12) 2451 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700) 2452 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8) 2453 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070) 2454 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4) 2455 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007) 2456 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0) 2457 2458 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7) 2459 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6) 2460 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5) 2461 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4) 2462 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3) 2463 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2) 2464 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1) 2465 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0) 2466 2467 /* 2468 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2469 *one and check the value returned for NumPhys at runtime. 2470 */ 2471 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX 2472 #define MPI2_SAS_IOUNIT5_PHY_MAX (1) 2473 #endif 2474 2475 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 { 2476 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2477 U8 NumPhys; /*0x08 */ 2478 U8 Reserved1;/*0x09 */ 2479 U16 Reserved2;/*0x0A */ 2480 U32 Reserved3;/*0x0C */ 2481 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS 2482 SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX];/*0x10 */ 2483 } MPI2_CONFIG_PAGE_SASIOUNIT_5, 2484 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5, 2485 Mpi2SasIOUnitPage5_t, *pMpi2SasIOUnitPage5_t; 2486 2487 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01) 2488 2489 2490 /*SAS IO Unit Page 6 */ 2491 2492 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS { 2493 U8 CurrentStatus; /*0x00 */ 2494 U8 CurrentModulation; /*0x01 */ 2495 U8 CurrentUtilization; /*0x02 */ 2496 U8 Reserved1; /*0x03 */ 2497 U32 Reserved2; /*0x04 */ 2498 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2499 *PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2500 Mpi2SasIOUnit6PortWidthModGroupStatus_t, 2501 *pMpi2SasIOUnit6PortWidthModGroupStatus_t; 2502 2503 /*defines for CurrentStatus field */ 2504 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00) 2505 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01) 2506 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02) 2507 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03) 2508 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04) 2509 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05) 2510 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06) 2511 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07) 2512 2513 /*defines for CurrentModulation field */ 2514 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00) 2515 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01) 2516 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02) 2517 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03) 2518 2519 /* 2520 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2521 *one and check the value returned for NumGroups at runtime. 2522 */ 2523 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX 2524 #define MPI2_SAS_IOUNIT6_GROUP_MAX (1) 2525 #endif 2526 2527 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 { 2528 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2529 U32 Reserved1; /*0x08 */ 2530 U32 Reserved2; /*0x0C */ 2531 U8 NumGroups; /*0x10 */ 2532 U8 Reserved3; /*0x11 */ 2533 U16 Reserved4; /*0x12 */ 2534 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 2535 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /*0x14 */ 2536 } MPI2_CONFIG_PAGE_SASIOUNIT_6, 2537 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6, 2538 Mpi2SasIOUnitPage6_t, *pMpi2SasIOUnitPage6_t; 2539 2540 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00) 2541 2542 2543 /*SAS IO Unit Page 7 */ 2544 2545 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS { 2546 U8 Flags; /*0x00 */ 2547 U8 Reserved1; /*0x01 */ 2548 U16 Reserved2; /*0x02 */ 2549 U8 Threshold75Pct; /*0x04 */ 2550 U8 Threshold50Pct; /*0x05 */ 2551 U8 Threshold25Pct; /*0x06 */ 2552 U8 Reserved3; /*0x07 */ 2553 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2554 *PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2555 Mpi2SasIOUnit7PortWidthModGroupSettings_t, 2556 *pMpi2SasIOUnit7PortWidthModGroupSettings_t; 2557 2558 /*defines for Flags field */ 2559 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01) 2560 2561 2562 /* 2563 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2564 *one and check the value returned for NumGroups at runtime. 2565 */ 2566 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX 2567 #define MPI2_SAS_IOUNIT7_GROUP_MAX (1) 2568 #endif 2569 2570 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 { 2571 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2572 U8 SamplingInterval; /*0x08 */ 2573 U8 WindowLength; /*0x09 */ 2574 U16 Reserved1; /*0x0A */ 2575 U32 Reserved2; /*0x0C */ 2576 U32 Reserved3; /*0x10 */ 2577 U8 NumGroups; /*0x14 */ 2578 U8 Reserved4; /*0x15 */ 2579 U16 Reserved5; /*0x16 */ 2580 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2581 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX];/*0x18 */ 2582 } MPI2_CONFIG_PAGE_SASIOUNIT_7, 2583 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7, 2584 Mpi2SasIOUnitPage7_t, *pMpi2SasIOUnitPage7_t; 2585 2586 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00) 2587 2588 2589 /*SAS IO Unit Page 8 */ 2590 2591 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 { 2592 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2593 Header; /*0x00 */ 2594 U32 2595 Reserved1; /*0x08 */ 2596 U32 2597 PowerManagementCapabilities; /*0x0C */ 2598 U8 2599 TxRxSleepStatus; /*0x10 */ 2600 U8 2601 Reserved2; /*0x11 */ 2602 U16 2603 Reserved3; /*0x12 */ 2604 } MPI2_CONFIG_PAGE_SASIOUNIT_8, 2605 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8, 2606 Mpi2SasIOUnitPage8_t, *pMpi2SasIOUnitPage8_t; 2607 2608 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00) 2609 2610 /*defines for PowerManagementCapabilities field */ 2611 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000) 2612 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800) 2613 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400) 2614 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200) 2615 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100) 2616 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010) 2617 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008) 2618 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004) 2619 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002) 2620 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001) 2621 2622 /*defines for TxRxSleepStatus field */ 2623 #define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED (0x00) 2624 #define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED (0x01) 2625 #define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE (0x02) 2626 #define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN (0x03) 2627 2628 2629 2630 /*SAS IO Unit Page 16 */ 2631 2632 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 { 2633 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2634 Header; /*0x00 */ 2635 U64 2636 TimeStamp; /*0x08 */ 2637 U32 2638 Reserved1; /*0x10 */ 2639 U32 2640 Reserved2; /*0x14 */ 2641 U32 2642 FastPathPendedRequests; /*0x18 */ 2643 U32 2644 FastPathUnPendedRequests; /*0x1C */ 2645 U32 2646 FastPathHostRequestStarts; /*0x20 */ 2647 U32 2648 FastPathFirmwareRequestStarts; /*0x24 */ 2649 U32 2650 FastPathHostCompletions; /*0x28 */ 2651 U32 2652 FastPathFirmwareCompletions; /*0x2C */ 2653 U32 2654 NonFastPathRequestStarts; /*0x30 */ 2655 U32 2656 NonFastPathHostCompletions; /*0x30 */ 2657 } MPI2_CONFIG_PAGE_SASIOUNIT16, 2658 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT16, 2659 Mpi2SasIOUnitPage16_t, *pMpi2SasIOUnitPage16_t; 2660 2661 #define MPI2_SASIOUNITPAGE16_PAGEVERSION (0x00) 2662 2663 2664 /**************************************************************************** 2665 * SAS Expander Config Pages 2666 ****************************************************************************/ 2667 2668 /*SAS Expander Page 0 */ 2669 2670 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 { 2671 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2672 Header; /*0x00 */ 2673 U8 2674 PhysicalPort; /*0x08 */ 2675 U8 2676 ReportGenLength; /*0x09 */ 2677 U16 2678 EnclosureHandle; /*0x0A */ 2679 U64 2680 SASAddress; /*0x0C */ 2681 U32 2682 DiscoveryStatus; /*0x14 */ 2683 U16 2684 DevHandle; /*0x18 */ 2685 U16 2686 ParentDevHandle; /*0x1A */ 2687 U16 2688 ExpanderChangeCount; /*0x1C */ 2689 U16 2690 ExpanderRouteIndexes; /*0x1E */ 2691 U8 2692 NumPhys; /*0x20 */ 2693 U8 2694 SASLevel; /*0x21 */ 2695 U16 2696 Flags; /*0x22 */ 2697 U16 2698 STPBusInactivityTimeLimit; /*0x24 */ 2699 U16 2700 STPMaxConnectTimeLimit; /*0x26 */ 2701 U16 2702 STP_SMP_NexusLossTime; /*0x28 */ 2703 U16 2704 MaxNumRoutedSasAddresses; /*0x2A */ 2705 U64 2706 ActiveZoneManagerSASAddress;/*0x2C */ 2707 U16 2708 ZoneLockInactivityLimit; /*0x34 */ 2709 U16 2710 Reserved1; /*0x36 */ 2711 U8 2712 TimeToReducedFunc; /*0x38 */ 2713 U8 2714 InitialTimeToReducedFunc; /*0x39 */ 2715 U8 2716 MaxReducedFuncTime; /*0x3A */ 2717 U8 2718 Reserved2; /*0x3B */ 2719 } MPI2_CONFIG_PAGE_EXPANDER_0, 2720 *PTR_MPI2_CONFIG_PAGE_EXPANDER_0, 2721 Mpi2ExpanderPage0_t, *pMpi2ExpanderPage0_t; 2722 2723 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06) 2724 2725 /*values for SAS Expander Page 0 DiscoveryStatus field */ 2726 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2727 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2728 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000) 2729 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2730 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2731 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2732 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2733 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000) 2734 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2735 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2736 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2737 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2738 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2739 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2740 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2741 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2742 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2743 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2744 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2745 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2746 2747 /*values for SAS Expander Page 0 Flags field */ 2748 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 2749 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 2750 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 2751 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 2752 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 2753 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 2754 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 2755 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 2756 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 2757 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 2758 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 2759 2760 2761 /*SAS Expander Page 1 */ 2762 2763 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 { 2764 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2765 Header; /*0x00 */ 2766 U8 2767 PhysicalPort; /*0x08 */ 2768 U8 2769 Reserved1; /*0x09 */ 2770 U16 2771 Reserved2; /*0x0A */ 2772 U8 2773 NumPhys; /*0x0C */ 2774 U8 2775 Phy; /*0x0D */ 2776 U16 2777 NumTableEntriesProgrammed; /*0x0E */ 2778 U8 2779 ProgrammedLinkRate; /*0x10 */ 2780 U8 2781 HwLinkRate; /*0x11 */ 2782 U16 2783 AttachedDevHandle; /*0x12 */ 2784 U32 2785 PhyInfo; /*0x14 */ 2786 U32 2787 AttachedDeviceInfo; /*0x18 */ 2788 U16 2789 ExpanderDevHandle; /*0x1C */ 2790 U8 2791 ChangeCount; /*0x1E */ 2792 U8 2793 NegotiatedLinkRate; /*0x1F */ 2794 U8 2795 PhyIdentifier; /*0x20 */ 2796 U8 2797 AttachedPhyIdentifier; /*0x21 */ 2798 U8 2799 Reserved3; /*0x22 */ 2800 U8 2801 DiscoveryInfo; /*0x23 */ 2802 U32 2803 AttachedPhyInfo; /*0x24 */ 2804 U8 2805 ZoneGroup; /*0x28 */ 2806 U8 2807 SelfConfigStatus; /*0x29 */ 2808 U16 2809 Reserved4; /*0x2A */ 2810 } MPI2_CONFIG_PAGE_EXPANDER_1, 2811 *PTR_MPI2_CONFIG_PAGE_EXPANDER_1, 2812 Mpi2ExpanderPage1_t, *pMpi2ExpanderPage1_t; 2813 2814 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02) 2815 2816 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2817 2818 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2819 2820 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2821 2822 /*see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines 2823 *used for the AttachedDeviceInfo field */ 2824 2825 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2826 2827 /*values for SAS Expander Page 1 DiscoveryInfo field */ 2828 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2829 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2830 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2831 2832 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2833 2834 2835 /**************************************************************************** 2836 * SAS Device Config Pages 2837 ****************************************************************************/ 2838 2839 /*SAS Device Page 0 */ 2840 2841 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 { 2842 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2843 Header; /*0x00 */ 2844 U16 2845 Slot; /*0x08 */ 2846 U16 2847 EnclosureHandle; /*0x0A */ 2848 U64 2849 SASAddress; /*0x0C */ 2850 U16 2851 ParentDevHandle; /*0x14 */ 2852 U8 2853 PhyNum; /*0x16 */ 2854 U8 2855 AccessStatus; /*0x17 */ 2856 U16 2857 DevHandle; /*0x18 */ 2858 U8 2859 AttachedPhyIdentifier; /*0x1A */ 2860 U8 2861 ZoneGroup; /*0x1B */ 2862 U32 2863 DeviceInfo; /*0x1C */ 2864 U16 2865 Flags; /*0x20 */ 2866 U8 2867 PhysicalPort; /*0x22 */ 2868 U8 2869 MaxPortConnections; /*0x23 */ 2870 U64 2871 DeviceName; /*0x24 */ 2872 U8 2873 PortGroups; /*0x2C */ 2874 U8 2875 DmaGroup; /*0x2D */ 2876 U8 2877 ControlGroup; /*0x2E */ 2878 U8 2879 EnclosureLevel; /*0x2F */ 2880 U32 2881 ConnectorName[4]; /*0x30 */ 2882 U32 2883 Reserved3; /*0x34 */ 2884 } MPI2_CONFIG_PAGE_SAS_DEV_0, 2885 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_0, 2886 Mpi2SasDevicePage0_t, 2887 *pMpi2SasDevicePage0_t; 2888 2889 #define MPI2_SASDEVICE0_PAGEVERSION (0x09) 2890 2891 /*values for SAS Device Page 0 AccessStatus field */ 2892 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2893 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2894 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2895 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2896 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2897 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05) 2898 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06) 2899 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07) 2900 /*specific values for SATA Init failures */ 2901 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2902 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2903 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2904 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2905 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2906 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2907 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2908 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2909 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2910 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2911 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2912 2913 /*see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2914 2915 /*values for SAS Device Page 0 Flags field */ 2916 #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000) 2917 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH (0x4000) 2918 #define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE (0x2000) 2919 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000) 2920 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800) 2921 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2922 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2923 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2924 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2925 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2926 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2927 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2928 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2929 #define MPI2_SAS_DEVICE0_FLAGS_PERSIST_CAPABLE (0x0004) 2930 #define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID (0x0002) 2931 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2932 2933 2934 /*SAS Device Page 1 */ 2935 2936 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 { 2937 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2938 Header; /*0x00 */ 2939 U32 2940 Reserved1; /*0x08 */ 2941 U64 2942 SASAddress; /*0x0C */ 2943 U32 2944 Reserved2; /*0x14 */ 2945 U16 2946 DevHandle; /*0x18 */ 2947 U16 2948 Reserved3; /*0x1A */ 2949 U8 2950 InitialRegDeviceFIS[20];/*0x1C */ 2951 } MPI2_CONFIG_PAGE_SAS_DEV_1, 2952 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_1, 2953 Mpi2SasDevicePage1_t, 2954 *pMpi2SasDevicePage1_t; 2955 2956 #define MPI2_SASDEVICE1_PAGEVERSION (0x01) 2957 2958 2959 /**************************************************************************** 2960 * SAS PHY Config Pages 2961 ****************************************************************************/ 2962 2963 /*SAS PHY Page 0 */ 2964 2965 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 { 2966 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2967 Header; /*0x00 */ 2968 U16 2969 OwnerDevHandle; /*0x08 */ 2970 U16 2971 Reserved1; /*0x0A */ 2972 U16 2973 AttachedDevHandle; /*0x0C */ 2974 U8 2975 AttachedPhyIdentifier; /*0x0E */ 2976 U8 2977 Reserved2; /*0x0F */ 2978 U32 2979 AttachedPhyInfo; /*0x10 */ 2980 U8 2981 ProgrammedLinkRate; /*0x14 */ 2982 U8 2983 HwLinkRate; /*0x15 */ 2984 U8 2985 ChangeCount; /*0x16 */ 2986 U8 2987 Flags; /*0x17 */ 2988 U32 2989 PhyInfo; /*0x18 */ 2990 U8 2991 NegotiatedLinkRate; /*0x1C */ 2992 U8 2993 Reserved3; /*0x1D */ 2994 U16 2995 Reserved4; /*0x1E */ 2996 } MPI2_CONFIG_PAGE_SAS_PHY_0, 2997 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_0, 2998 Mpi2SasPhyPage0_t, *pMpi2SasPhyPage0_t; 2999 3000 #define MPI2_SASPHY0_PAGEVERSION (0x03) 3001 3002 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 3003 3004 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 3005 3006 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 3007 3008 /*values for SAS PHY Page 0 Flags field */ 3009 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 3010 3011 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 3012 3013 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3014 3015 3016 /*SAS PHY Page 1 */ 3017 3018 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 { 3019 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3020 Header; /*0x00 */ 3021 U32 3022 Reserved1; /*0x08 */ 3023 U32 3024 InvalidDwordCount; /*0x0C */ 3025 U32 3026 RunningDisparityErrorCount; /*0x10 */ 3027 U32 3028 LossDwordSynchCount; /*0x14 */ 3029 U32 3030 PhyResetProblemCount; /*0x18 */ 3031 } MPI2_CONFIG_PAGE_SAS_PHY_1, 3032 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_1, 3033 Mpi2SasPhyPage1_t, *pMpi2SasPhyPage1_t; 3034 3035 #define MPI2_SASPHY1_PAGEVERSION (0x01) 3036 3037 3038 /*SAS PHY Page 2 */ 3039 3040 typedef struct _MPI2_SASPHY2_PHY_EVENT { 3041 U8 PhyEventCode; /*0x00 */ 3042 U8 Reserved1; /*0x01 */ 3043 U16 Reserved2; /*0x02 */ 3044 U32 PhyEventInfo; /*0x04 */ 3045 } MPI2_SASPHY2_PHY_EVENT, *PTR_MPI2_SASPHY2_PHY_EVENT, 3046 Mpi2SasPhy2PhyEvent_t, *pMpi2SasPhy2PhyEvent_t; 3047 3048 /*use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */ 3049 3050 3051 /* 3052 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3053 *one and check the value returned for NumPhyEvents at runtime. 3054 */ 3055 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX 3056 #define MPI2_SASPHY2_PHY_EVENT_MAX (1) 3057 #endif 3058 3059 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 { 3060 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3061 Header; /*0x00 */ 3062 U32 3063 Reserved1; /*0x08 */ 3064 U8 3065 NumPhyEvents; /*0x0C */ 3066 U8 3067 Reserved2; /*0x0D */ 3068 U16 3069 Reserved3; /*0x0E */ 3070 MPI2_SASPHY2_PHY_EVENT 3071 PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /*0x10 */ 3072 } MPI2_CONFIG_PAGE_SAS_PHY_2, 3073 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_2, 3074 Mpi2SasPhyPage2_t, 3075 *pMpi2SasPhyPage2_t; 3076 3077 #define MPI2_SASPHY2_PAGEVERSION (0x00) 3078 3079 3080 /*SAS PHY Page 3 */ 3081 3082 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG { 3083 U8 PhyEventCode; /*0x00 */ 3084 U8 Reserved1; /*0x01 */ 3085 U16 Reserved2; /*0x02 */ 3086 U8 CounterType; /*0x04 */ 3087 U8 ThresholdWindow; /*0x05 */ 3088 U8 TimeUnits; /*0x06 */ 3089 U8 Reserved3; /*0x07 */ 3090 U32 EventThreshold; /*0x08 */ 3091 U16 ThresholdFlags; /*0x0C */ 3092 U16 Reserved4; /*0x0E */ 3093 } MPI2_SASPHY3_PHY_EVENT_CONFIG, 3094 *PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG, 3095 Mpi2SasPhy3PhyEventConfig_t, 3096 *pMpi2SasPhy3PhyEventConfig_t; 3097 3098 /*values for PhyEventCode field */ 3099 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 3100 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 3101 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 3102 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 3103 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 3104 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 3105 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 3106 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 3107 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 3108 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 3109 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 3110 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 3111 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 3112 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 3113 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 3114 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 3115 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 3116 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A) 3117 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B) 3118 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C) 3119 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D) 3120 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E) 3121 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 3122 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 3123 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 3124 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 3125 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 3126 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 3127 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 3128 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 3129 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 3130 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 3131 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 3132 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 3133 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) 3134 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) 3135 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2) 3136 3137 /*Following codes are product specific and in MPI v2.6 and later */ 3138 #define MPI2_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xD3) 3139 #define MPI2_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xD4) 3140 #define MPI2_SASPHY3_EVENT_CODE_LCCONN_TIME (0xD5) 3141 #define MPI2_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xD6) 3142 #define MPI2_SASPHY3_EVENT_CODE_SATA_TX_START (0xD7) 3143 #define MPI2_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xD8) 3144 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xD9) 3145 #define MPI2_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xDA) 3146 #define MPI2_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xDB) 3147 #define MPI2_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xDC) 3148 3149 3150 /*values for the CounterType field */ 3151 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 3152 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 3153 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 3154 3155 /*values for the TimeUnits field */ 3156 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 3157 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 3158 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 3159 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 3160 3161 /*values for the ThresholdFlags field */ 3162 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002) 3163 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 3164 3165 /* 3166 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3167 *one and check the value returned for NumPhyEvents at runtime. 3168 */ 3169 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX 3170 #define MPI2_SASPHY3_PHY_EVENT_MAX (1) 3171 #endif 3172 3173 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 { 3174 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3175 Header; /*0x00 */ 3176 U32 3177 Reserved1; /*0x08 */ 3178 U8 3179 NumPhyEvents; /*0x0C */ 3180 U8 3181 Reserved2; /*0x0D */ 3182 U16 3183 Reserved3; /*0x0E */ 3184 MPI2_SASPHY3_PHY_EVENT_CONFIG 3185 PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /*0x10 */ 3186 } MPI2_CONFIG_PAGE_SAS_PHY_3, 3187 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_3, 3188 Mpi2SasPhyPage3_t, *pMpi2SasPhyPage3_t; 3189 3190 #define MPI2_SASPHY3_PAGEVERSION (0x00) 3191 3192 3193 /*SAS PHY Page 4 */ 3194 3195 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 { 3196 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3197 Header; /*0x00 */ 3198 U16 3199 Reserved1; /*0x08 */ 3200 U8 3201 Reserved2; /*0x0A */ 3202 U8 3203 Flags; /*0x0B */ 3204 U8 3205 InitialFrame[28]; /*0x0C */ 3206 } MPI2_CONFIG_PAGE_SAS_PHY_4, 3207 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_4, 3208 Mpi2SasPhyPage4_t, *pMpi2SasPhyPage4_t; 3209 3210 #define MPI2_SASPHY4_PAGEVERSION (0x00) 3211 3212 /*values for the Flags field */ 3213 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02) 3214 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01) 3215 3216 3217 3218 3219 /**************************************************************************** 3220 * SAS Port Config Pages 3221 ****************************************************************************/ 3222 3223 /*SAS Port Page 0 */ 3224 3225 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 { 3226 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3227 Header; /*0x00 */ 3228 U8 3229 PortNumber; /*0x08 */ 3230 U8 3231 PhysicalPort; /*0x09 */ 3232 U8 3233 PortWidth; /*0x0A */ 3234 U8 3235 PhysicalPortWidth; /*0x0B */ 3236 U8 3237 ZoneGroup; /*0x0C */ 3238 U8 3239 Reserved1; /*0x0D */ 3240 U16 3241 Reserved2; /*0x0E */ 3242 U64 3243 SASAddress; /*0x10 */ 3244 U32 3245 DeviceInfo; /*0x18 */ 3246 U32 3247 Reserved3; /*0x1C */ 3248 U32 3249 Reserved4; /*0x20 */ 3250 } MPI2_CONFIG_PAGE_SAS_PORT_0, 3251 *PTR_MPI2_CONFIG_PAGE_SAS_PORT_0, 3252 Mpi2SasPortPage0_t, *pMpi2SasPortPage0_t; 3253 3254 #define MPI2_SASPORT0_PAGEVERSION (0x00) 3255 3256 /*see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */ 3257 3258 3259 /**************************************************************************** 3260 * SAS Enclosure Config Pages 3261 ****************************************************************************/ 3262 3263 /*SAS Enclosure Page 0 */ 3264 3265 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 { 3266 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3267 U32 Reserved1; /*0x08 */ 3268 U64 EnclosureLogicalID; /*0x0C */ 3269 U16 Flags; /*0x14 */ 3270 U16 EnclosureHandle; /*0x16 */ 3271 U16 NumSlots; /*0x18 */ 3272 U16 StartSlot; /*0x1A */ 3273 U8 ChassisSlot; /*0x1C */ 3274 U8 EnclosureLeve; /*0x1D */ 3275 U16 SEPDevHandle; /*0x1E */ 3276 U32 Reserved3; /*0x20 */ 3277 U32 Reserved4; /*0x24 */ 3278 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3279 *PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3280 Mpi2SasEnclosurePage0_t, *pMpi2SasEnclosurePage0_t, 3281 MPI26_CONFIG_PAGE_ENCLOSURE_0, 3282 *PTR_MPI26_CONFIG_PAGE_ENCLOSURE_0, 3283 Mpi26EnclosurePage0_t, *pMpi26EnclosurePage0_t; 3284 3285 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x04) 3286 3287 /*values for SAS Enclosure Page 0 Flags field */ 3288 #define MPI2_SAS_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020) 3289 #define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010) 3290 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 3291 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3292 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3293 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3294 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3295 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3296 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3297 3298 #define MPI26_ENCLOSURE0_PAGEVERSION (0x04) 3299 3300 /*Values for Enclosure Page 0 Flags field */ 3301 #define MPI26_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020) 3302 #define MPI26_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010) 3303 #define MPI26_ENCLS0_FLAGS_MNG_MASK (0x000F) 3304 #define MPI26_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3305 #define MPI26_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3306 #define MPI26_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3307 #define MPI26_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3308 #define MPI26_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3309 #define MPI26_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3310 3311 /**************************************************************************** 3312 * Log Config Page 3313 ****************************************************************************/ 3314 3315 /*Log Page 0 */ 3316 3317 /* 3318 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3319 *one and check the value returned for NumLogEntries at runtime. 3320 */ 3321 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES 3322 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1) 3323 #endif 3324 3325 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C) 3326 3327 typedef struct _MPI2_LOG_0_ENTRY { 3328 U64 TimeStamp; /*0x00 */ 3329 U32 Reserved1; /*0x08 */ 3330 U16 LogSequence; /*0x0C */ 3331 U16 LogEntryQualifier; /*0x0E */ 3332 U8 VP_ID; /*0x10 */ 3333 U8 VF_ID; /*0x11 */ 3334 U16 Reserved2; /*0x12 */ 3335 U8 3336 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/*0x14 */ 3337 } MPI2_LOG_0_ENTRY, *PTR_MPI2_LOG_0_ENTRY, 3338 Mpi2Log0Entry_t, *pMpi2Log0Entry_t; 3339 3340 /*values for Log Page 0 LogEntry LogEntryQualifier field */ 3341 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 3342 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 3343 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002) 3344 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000) 3345 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF) 3346 3347 typedef struct _MPI2_CONFIG_PAGE_LOG_0 { 3348 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3349 U32 Reserved1; /*0x08 */ 3350 U32 Reserved2; /*0x0C */ 3351 U16 NumLogEntries;/*0x10 */ 3352 U16 Reserved3; /*0x12 */ 3353 MPI2_LOG_0_ENTRY 3354 LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /*0x14 */ 3355 } MPI2_CONFIG_PAGE_LOG_0, *PTR_MPI2_CONFIG_PAGE_LOG_0, 3356 Mpi2LogPage0_t, *pMpi2LogPage0_t; 3357 3358 #define MPI2_LOG_0_PAGEVERSION (0x02) 3359 3360 3361 /**************************************************************************** 3362 * RAID Config Page 3363 ****************************************************************************/ 3364 3365 /*RAID Page 0 */ 3366 3367 /* 3368 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3369 *one and check the value returned for NumElements at runtime. 3370 */ 3371 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS 3372 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1) 3373 #endif 3374 3375 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT { 3376 U16 ElementFlags; /*0x00 */ 3377 U16 VolDevHandle; /*0x02 */ 3378 U8 HotSparePool; /*0x04 */ 3379 U8 PhysDiskNum; /*0x05 */ 3380 U16 PhysDiskDevHandle; /*0x06 */ 3381 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3382 *PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3383 Mpi2RaidConfig0ConfigElement_t, 3384 *pMpi2RaidConfig0ConfigElement_t; 3385 3386 /*values for the ElementFlags field */ 3387 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F) 3388 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000) 3389 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001) 3390 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002) 3391 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003) 3392 3393 3394 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 { 3395 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3396 U8 NumHotSpares; /*0x08 */ 3397 U8 NumPhysDisks; /*0x09 */ 3398 U8 NumVolumes; /*0x0A */ 3399 U8 ConfigNum; /*0x0B */ 3400 U32 Flags; /*0x0C */ 3401 U8 ConfigGUID[24]; /*0x10 */ 3402 U32 Reserved1; /*0x28 */ 3403 U8 NumElements; /*0x2C */ 3404 U8 Reserved2; /*0x2D */ 3405 U16 Reserved3; /*0x2E */ 3406 MPI2_RAIDCONFIG0_CONFIG_ELEMENT 3407 ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /*0x30 */ 3408 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3409 *PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3410 Mpi2RaidConfigurationPage0_t, 3411 *pMpi2RaidConfigurationPage0_t; 3412 3413 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00) 3414 3415 /*values for RAID Configuration Page 0 Flags field */ 3416 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001) 3417 3418 3419 /**************************************************************************** 3420 * Driver Persistent Mapping Config Pages 3421 ****************************************************************************/ 3422 3423 /*Driver Persistent Mapping Page 0 */ 3424 3425 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY { 3426 U64 PhysicalIdentifier; /*0x00 */ 3427 U16 MappingInformation; /*0x08 */ 3428 U16 DeviceIndex; /*0x0A */ 3429 U32 PhysicalBitsMapping; /*0x0C */ 3430 U32 Reserved1; /*0x10 */ 3431 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3432 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3433 Mpi2DriverMap0Entry_t, *pMpi2DriverMap0Entry_t; 3434 3435 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 { 3436 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3437 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /*0x08 */ 3438 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3439 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3440 Mpi2DriverMappingPage0_t, *pMpi2DriverMappingPage0_t; 3441 3442 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00) 3443 3444 /*values for Driver Persistent Mapping Page 0 MappingInformation field */ 3445 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0) 3446 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4) 3447 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F) 3448 3449 3450 /**************************************************************************** 3451 * Ethernet Config Pages 3452 ****************************************************************************/ 3453 3454 /*Ethernet Page 0 */ 3455 3456 /*IP address (union of IPv4 and IPv6) */ 3457 typedef union _MPI2_ETHERNET_IP_ADDR { 3458 U32 IPv4Addr; 3459 U32 IPv6Addr[4]; 3460 } MPI2_ETHERNET_IP_ADDR, *PTR_MPI2_ETHERNET_IP_ADDR, 3461 Mpi2EthernetIpAddr_t, *pMpi2EthernetIpAddr_t; 3462 3463 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32) 3464 3465 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 { 3466 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3467 U8 NumInterfaces; /*0x08 */ 3468 U8 Reserved0; /*0x09 */ 3469 U16 Reserved1; /*0x0A */ 3470 U32 Status; /*0x0C */ 3471 U8 MediaState; /*0x10 */ 3472 U8 Reserved2; /*0x11 */ 3473 U16 Reserved3; /*0x12 */ 3474 U8 MacAddress[6]; /*0x14 */ 3475 U8 Reserved4; /*0x1A */ 3476 U8 Reserved5; /*0x1B */ 3477 MPI2_ETHERNET_IP_ADDR IpAddress; /*0x1C */ 3478 MPI2_ETHERNET_IP_ADDR SubnetMask; /*0x2C */ 3479 MPI2_ETHERNET_IP_ADDR GatewayIpAddress;/*0x3C */ 3480 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /*0x4C */ 3481 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /*0x5C */ 3482 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /*0x6C */ 3483 U8 3484 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */ 3485 } MPI2_CONFIG_PAGE_ETHERNET_0, 3486 *PTR_MPI2_CONFIG_PAGE_ETHERNET_0, 3487 Mpi2EthernetPage0_t, *pMpi2EthernetPage0_t; 3488 3489 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00) 3490 3491 /*values for Ethernet Page 0 Status field */ 3492 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000) 3493 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000) 3494 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000) 3495 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100) 3496 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080) 3497 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040) 3498 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020) 3499 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010) 3500 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008) 3501 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004) 3502 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002) 3503 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001) 3504 3505 /*values for Ethernet Page 0 MediaState field */ 3506 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80) 3507 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00) 3508 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80) 3509 3510 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07) 3511 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00) 3512 #define MPI2_ETHPG0_MS_10MBIT (0x01) 3513 #define MPI2_ETHPG0_MS_100MBIT (0x02) 3514 #define MPI2_ETHPG0_MS_1GBIT (0x03) 3515 3516 3517 /*Ethernet Page 1 */ 3518 3519 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 { 3520 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3521 Header; /*0x00 */ 3522 U32 3523 Reserved0; /*0x08 */ 3524 U32 3525 Flags; /*0x0C */ 3526 U8 3527 MediaState; /*0x10 */ 3528 U8 3529 Reserved1; /*0x11 */ 3530 U16 3531 Reserved2; /*0x12 */ 3532 U8 3533 MacAddress[6]; /*0x14 */ 3534 U8 3535 Reserved3; /*0x1A */ 3536 U8 3537 Reserved4; /*0x1B */ 3538 MPI2_ETHERNET_IP_ADDR 3539 StaticIpAddress; /*0x1C */ 3540 MPI2_ETHERNET_IP_ADDR 3541 StaticSubnetMask; /*0x2C */ 3542 MPI2_ETHERNET_IP_ADDR 3543 StaticGatewayIpAddress; /*0x3C */ 3544 MPI2_ETHERNET_IP_ADDR 3545 StaticDNS1IpAddress; /*0x4C */ 3546 MPI2_ETHERNET_IP_ADDR 3547 StaticDNS2IpAddress; /*0x5C */ 3548 U32 3549 Reserved5; /*0x6C */ 3550 U32 3551 Reserved6; /*0x70 */ 3552 U32 3553 Reserved7; /*0x74 */ 3554 U32 3555 Reserved8; /*0x78 */ 3556 U8 3557 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */ 3558 } MPI2_CONFIG_PAGE_ETHERNET_1, 3559 *PTR_MPI2_CONFIG_PAGE_ETHERNET_1, 3560 Mpi2EthernetPage1_t, *pMpi2EthernetPage1_t; 3561 3562 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00) 3563 3564 /*values for Ethernet Page 1 Flags field */ 3565 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100) 3566 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080) 3567 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040) 3568 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020) 3569 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010) 3570 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008) 3571 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004) 3572 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002) 3573 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001) 3574 3575 /*values for Ethernet Page 1 MediaState field */ 3576 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80) 3577 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00) 3578 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80) 3579 3580 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07) 3581 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00) 3582 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01) 3583 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02) 3584 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03) 3585 3586 3587 /**************************************************************************** 3588 * Extended Manufacturing Config Pages 3589 ****************************************************************************/ 3590 3591 /* 3592 *Generic structure to use for product-specific extended manufacturing pages 3593 *(currently Extended Manufacturing Page 40 through Extended Manufacturing 3594 *Page 60). 3595 */ 3596 3597 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS { 3598 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3599 Header; /*0x00 */ 3600 U32 3601 ProductSpecificInfo; /*0x08 */ 3602 } MPI2_CONFIG_PAGE_EXT_MAN_PS, 3603 *PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS, 3604 Mpi2ExtManufacturingPagePS_t, 3605 *pMpi2ExtManufacturingPagePS_t; 3606 3607 /*PageVersion should be provided by product-specific code */ 3608 3609 3610 3611 /**************************************************************************** 3612 * values for fields used by several types of PCIe Config Pages 3613 ****************************************************************************/ 3614 3615 /*values for NegotiatedLinkRates fields */ 3616 #define MPI26_PCIE_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 3617 /*link rates used for Negotiated Physical Link Rate */ 3618 #define MPI26_PCIE_NEG_LINK_RATE_UNKNOWN (0x00) 3619 #define MPI26_PCIE_NEG_LINK_RATE_PHY_DISABLED (0x01) 3620 #define MPI26_PCIE_NEG_LINK_RATE_2_5 (0x02) 3621 #define MPI26_PCIE_NEG_LINK_RATE_5_0 (0x03) 3622 #define MPI26_PCIE_NEG_LINK_RATE_8_0 (0x04) 3623 #define MPI26_PCIE_NEG_LINK_RATE_16_0 (0x05) 3624 3625 3626 /**************************************************************************** 3627 * PCIe IO Unit Config Pages (MPI v2.6 and later) 3628 ****************************************************************************/ 3629 3630 /*PCIe IO Unit Page 0 */ 3631 3632 typedef struct _MPI26_PCIE_IO_UNIT0_PHY_DATA { 3633 U8 Link; /*0x00 */ 3634 U8 LinkFlags; /*0x01 */ 3635 U8 PhyFlags; /*0x02 */ 3636 U8 NegotiatedLinkRate; /*0x03 */ 3637 U32 ControllerPhyDeviceInfo;/*0x04 */ 3638 U16 AttachedDevHandle; /*0x08 */ 3639 U16 ControllerDevHandle; /*0x0A */ 3640 U32 EnumerationStatus; /*0x0C */ 3641 U32 Reserved1; /*0x10 */ 3642 } MPI26_PCIE_IO_UNIT0_PHY_DATA, 3643 *PTR_MPI26_PCIE_IO_UNIT0_PHY_DATA, 3644 Mpi26PCIeIOUnit0PhyData_t, *pMpi26PCIeIOUnit0PhyData_t; 3645 3646 /* 3647 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3648 *one and check the value returned for NumPhys at runtime. 3649 */ 3650 #ifndef MPI26_PCIE_IOUNIT0_PHY_MAX 3651 #define MPI26_PCIE_IOUNIT0_PHY_MAX (1) 3652 #endif 3653 3654 typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_0 { 3655 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3656 U32 Reserved1; /*0x08 */ 3657 U8 NumPhys; /*0x0C */ 3658 U8 InitStatus; /*0x0D */ 3659 U16 Reserved3; /*0x0E */ 3660 MPI26_PCIE_IO_UNIT0_PHY_DATA 3661 PhyData[MPI26_PCIE_IOUNIT0_PHY_MAX]; /*0x10 */ 3662 } MPI26_CONFIG_PAGE_PIOUNIT_0, 3663 *PTR_MPI26_CONFIG_PAGE_PIOUNIT_0, 3664 Mpi26PCIeIOUnitPage0_t, *pMpi26PCIeIOUnitPage0_t; 3665 3666 #define MPI26_PCIEIOUNITPAGE0_PAGEVERSION (0x00) 3667 3668 /*values for PCIe IO Unit Page 0 LinkFlags */ 3669 #define MPI26_PCIEIOUNIT0_LINKFLAGS_ENUMERATION_IN_PROGRESS (0x08) 3670 3671 /*values for PCIe IO Unit Page 0 PhyFlags */ 3672 #define MPI26_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 3673 3674 /*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3675 3676 /*see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo 3677 *values 3678 */ 3679 3680 /*values for PCIe IO Unit Page 0 EnumerationStatus */ 3681 #define MPI26_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED (0x40000000) 3682 #define MPI26_PCIEIOUNIT0_ES_MAX_DEVICES_EXCEEDED (0x20000000) 3683 3684 3685 /*PCIe IO Unit Page 1 */ 3686 3687 typedef struct _MPI26_PCIE_IO_UNIT1_PHY_DATA { 3688 U8 Link; /*0x00 */ 3689 U8 LinkFlags; /*0x01 */ 3690 U8 PhyFlags; /*0x02 */ 3691 U8 MaxMinLinkRate; /*0x03 */ 3692 U32 ControllerPhyDeviceInfo; /*0x04 */ 3693 U32 Reserved1; /*0x08 */ 3694 } MPI26_PCIE_IO_UNIT1_PHY_DATA, 3695 *PTR_MPI26_PCIE_IO_UNIT1_PHY_DATA, 3696 Mpi26PCIeIOUnit1PhyData_t, *pMpi26PCIeIOUnit1PhyData_t; 3697 3698 /*values for LinkFlags */ 3699 #define MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SRIS (0x00) 3700 #define MPI26_PCIEIOUNIT1_LINKFLAGS_EN_SRIS (0x01) 3701 3702 /* 3703 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3704 *one and check the value returned for NumPhys at runtime. 3705 */ 3706 #ifndef MPI26_PCIE_IOUNIT1_PHY_MAX 3707 #define MPI26_PCIE_IOUNIT1_PHY_MAX (1) 3708 #endif 3709 3710 typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_1 { 3711 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3712 U16 ControlFlags; /*0x08 */ 3713 U16 Reserved; /*0x0A */ 3714 U16 AdditionalControlFlags; /*0x0C */ 3715 U16 NVMeMaxQueueDepth; /*0x0E */ 3716 U8 NumPhys; /*0x10 */ 3717 U8 Reserved1; /*0x11 */ 3718 U16 Reserved2; /*0x12 */ 3719 MPI26_PCIE_IO_UNIT1_PHY_DATA 3720 PhyData[MPI26_PCIE_IOUNIT1_PHY_MAX];/*0x14 */ 3721 } MPI26_CONFIG_PAGE_PIOUNIT_1, 3722 *PTR_MPI26_CONFIG_PAGE_PIOUNIT_1, 3723 Mpi26PCIeIOUnitPage1_t, *pMpi26PCIeIOUnitPage1_t; 3724 3725 #define MPI26_PCIEIOUNITPAGE1_PAGEVERSION (0x00) 3726 3727 /*values for PCIe IO Unit Page 1 PhyFlags */ 3728 #define MPI26_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 3729 #define MPI26_PCIEIOUNIT1_PHYFLAGS_ENDPOINT_ONLY (0x01) 3730 3731 /*values for PCIe IO Unit Page 1 MaxMinLinkRate */ 3732 #define MPI26_PCIEIOUNIT1_MAX_RATE_MASK (0xF0) 3733 #define MPI26_PCIEIOUNIT1_MAX_RATE_SHIFT (4) 3734 #define MPI26_PCIEIOUNIT1_MAX_RATE_2_5 (0x20) 3735 #define MPI26_PCIEIOUNIT1_MAX_RATE_5_0 (0x30) 3736 #define MPI26_PCIEIOUNIT1_MAX_RATE_8_0 (0x40) 3737 #define MPI26_PCIEIOUNIT1_MAX_RATE_16_0 (0x50) 3738 3739 /*see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo 3740 *values 3741 */ 3742 3743 3744 /**************************************************************************** 3745 * PCIe Switch Config Pages (MPI v2.6 and later) 3746 ****************************************************************************/ 3747 3748 /*PCIe Switch Page 0 */ 3749 3750 typedef struct _MPI26_CONFIG_PAGE_PSWITCH_0 { 3751 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3752 U8 PhysicalPort; /*0x08 */ 3753 U8 Reserved1; /*0x09 */ 3754 U16 Reserved2; /*0x0A */ 3755 U16 DevHandle; /*0x0C */ 3756 U16 ParentDevHandle; /*0x0E */ 3757 U8 NumPorts; /*0x10 */ 3758 U8 PCIeLevel; /*0x11 */ 3759 U16 Reserved3; /*0x12 */ 3760 U32 Reserved4; /*0x14 */ 3761 U32 Reserved5; /*0x18 */ 3762 U32 Reserved6; /*0x1C */ 3763 } MPI26_CONFIG_PAGE_PSWITCH_0, *PTR_MPI26_CONFIG_PAGE_PSWITCH_0, 3764 Mpi26PCIeSwitchPage0_t, *pMpi26PCIeSwitchPage0_t; 3765 3766 #define MPI26_PCIESWITCH0_PAGEVERSION (0x00) 3767 3768 3769 /*PCIe Switch Page 1 */ 3770 3771 typedef struct _MPI26_CONFIG_PAGE_PSWITCH_1 { 3772 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3773 U8 PhysicalPort; /*0x08 */ 3774 U8 Reserved1; /*0x09 */ 3775 U16 Reserved2; /*0x0A */ 3776 U8 NumPorts; /*0x0C */ 3777 U8 PortNum; /*0x0D */ 3778 U16 AttachedDevHandle; /*0x0E */ 3779 U16 SwitchDevHandle; /*0x10 */ 3780 U8 NegotiatedPortWidth; /*0x12 */ 3781 U8 NegotiatedLinkRate; /*0x13 */ 3782 U32 Reserved4; /*0x14 */ 3783 U32 Reserved5; /*0x18 */ 3784 } MPI26_CONFIG_PAGE_PSWITCH_1, *PTR_MPI26_CONFIG_PAGE_PSWITCH_1, 3785 Mpi26PCIeSwitchPage1_t, *pMpi26PCIeSwitchPage1_t; 3786 3787 #define MPI26_PCIESWITCH1_PAGEVERSION (0x00) 3788 3789 /*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3790 3791 3792 /**************************************************************************** 3793 * PCIe Device Config Pages (MPI v2.6 and later) 3794 ****************************************************************************/ 3795 3796 /*PCIe Device Page 0 */ 3797 3798 typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_0 { 3799 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3800 U16 Slot; /*0x08 */ 3801 U16 EnclosureHandle; /*0x0A */ 3802 U64 WWID; /*0x0C */ 3803 U16 ParentDevHandle; /*0x14 */ 3804 U8 PortNum; /*0x16 */ 3805 U8 AccessStatus; /*0x17 */ 3806 U16 DevHandle; /*0x18 */ 3807 U8 PhysicalPort; /*0x1A */ 3808 U8 Reserved1; /*0x1B */ 3809 U32 DeviceInfo; /*0x1C */ 3810 U32 Flags; /*0x20 */ 3811 U8 SupportedLinkRates; /*0x24 */ 3812 U8 MaxPortWidth; /*0x25 */ 3813 U8 NegotiatedPortWidth; /*0x26 */ 3814 U8 NegotiatedLinkRate; /*0x27 */ 3815 U8 EnclosureLevel; /*0x28 */ 3816 U8 Reserved2; /*0x29 */ 3817 U16 Reserved3; /*0x2A */ 3818 U8 ConnectorName[4]; /*0x2C */ 3819 U32 Reserved4; /*0x30 */ 3820 U32 Reserved5; /*0x34 */ 3821 } MPI26_CONFIG_PAGE_PCIEDEV_0, *PTR_MPI26_CONFIG_PAGE_PCIEDEV_0, 3822 Mpi26PCIeDevicePage0_t, *pMpi26PCIeDevicePage0_t; 3823 3824 #define MPI26_PCIEDEVICE0_PAGEVERSION (0x01) 3825 3826 /*values for PCIe Device Page 0 AccessStatus field */ 3827 #define MPI26_PCIEDEV0_ASTATUS_NO_ERRORS (0x00) 3828 #define MPI26_PCIEDEV0_ASTATUS_NEEDS_INITIALIZATION (0x04) 3829 #define MPI26_PCIEDEV0_ASTATUS_CAPABILITY_FAILED (0x02) 3830 #define MPI26_PCIEDEV0_ASTATUS_DEVICE_BLOCKED (0x07) 3831 #define MPI26_PCIEDEV0_ASTATUS_MEMORY_SPACE_ACCESS_FAILED (0x08) 3832 #define MPI26_PCIEDEV0_ASTATUS_UNSUPPORTED_DEVICE (0x09) 3833 #define MPI26_PCIEDEV0_ASTATUS_MSIX_REQUIRED (0x0A) 3834 #define MPI26_PCIEDEV0_ASTATUS_UNKNOWN (0x10) 3835 3836 #define MPI26_PCIEDEV0_ASTATUS_NVME_READY_TIMEOUT (0x30) 3837 #define MPI26_PCIEDEV0_ASTATUS_NVME_DEVCFG_UNSUPPORTED (0x31) 3838 #define MPI26_PCIEDEV0_ASTATUS_NVME_IDENTIFY_FAILED (0x32) 3839 #define MPI26_PCIEDEV0_ASTATUS_NVME_QCONFIG_FAILED (0x33) 3840 #define MPI26_PCIEDEV0_ASTATUS_NVME_QCREATION_FAILED (0x34) 3841 #define MPI26_PCIEDEV0_ASTATUS_NVME_EVENTCFG_FAILED (0x35) 3842 #define MPI26_PCIEDEV0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED (0x36) 3843 #define MPI26_PCIEDEV0_ASTATUS_NVME_IDLE_TIMEOUT (0x37) 3844 #define MPI26_PCIEDEV0_ASTATUS_NVME_FAILURE_STATUS (0x38) 3845 3846 #define MPI26_PCIEDEV0_ASTATUS_INIT_FAIL_MAX (0x3F) 3847 3848 /*see mpi2_pci.h for the MPI26_PCIE_DEVINFO_ defines used for the DeviceInfo 3849 *field 3850 */ 3851 3852 /*values for PCIe Device Page 0 Flags field */ 3853 #define MPI26_PCIEDEV0_FLAGS_UNAUTHORIZED_DEVICE (0x8000) 3854 #define MPI26_PCIEDEV0_FLAGS_ENABLED_FAST_PATH (0x4000) 3855 #define MPI26_PCIEDEV0_FLAGS_FAST_PATH_CAPABLE (0x2000) 3856 #define MPI26_PCIEDEV0_FLAGS_ASYNCHRONOUS_NOTIFICATION (0x0400) 3857 #define MPI26_PCIEDEV0_FLAGS_ATA_SW_PRESERVATION (0x0200) 3858 #define MPI26_PCIEDEV0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 3859 #define MPI26_PCIEDEV0_FLAGS_ATA_48BIT_LBA_SUPPORTED (0x0080) 3860 #define MPI26_PCIEDEV0_FLAGS_ATA_SMART_SUPPORTED (0x0040) 3861 #define MPI26_PCIEDEV0_FLAGS_ATA_NCQ_SUPPORTED (0x0020) 3862 #define MPI26_PCIEDEV0_FLAGS_ATA_FUA_SUPPORTED (0x0010) 3863 #define MPI26_PCIEDEV0_FLAGS_ENCL_LEVEL_VALID (0x0002) 3864 #define MPI26_PCIEDEV0_FLAGS_DEVICE_PRESENT (0x0001) 3865 3866 /* values for PCIe Device Page 0 SupportedLinkRates field */ 3867 #define MPI26_PCIEDEV0_LINK_RATE_16_0_SUPPORTED (0x08) 3868 #define MPI26_PCIEDEV0_LINK_RATE_8_0_SUPPORTED (0x04) 3869 #define MPI26_PCIEDEV0_LINK_RATE_5_0_SUPPORTED (0x02) 3870 #define MPI26_PCIEDEV0_LINK_RATE_2_5_SUPPORTED (0x01) 3871 3872 /*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3873 3874 3875 /*PCIe Device Page 2 */ 3876 3877 typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_2 { 3878 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3879 U16 DevHandle; /*0x08 */ 3880 U8 ControllerResetTO; /* 0x0A */ 3881 U8 Reserved1; /* 0x0B */ 3882 U32 MaximumDataTransferSize; /*0x0C */ 3883 U32 Capabilities; /*0x10 */ 3884 U16 NOIOB; /* 0x14 */ 3885 U16 Reserved2; /* 0x16 */ 3886 } MPI26_CONFIG_PAGE_PCIEDEV_2, *PTR_MPI26_CONFIG_PAGE_PCIEDEV_2, 3887 Mpi26PCIeDevicePage2_t, *pMpi26PCIeDevicePage2_t; 3888 3889 #define MPI26_PCIEDEVICE2_PAGEVERSION (0x01) 3890 3891 /*defines for PCIe Device Page 2 Capabilities field */ 3892 #define MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN (0x00000008) 3893 #define MPI26_PCIEDEV2_CAP_SGL_FORMAT (0x00000004) 3894 #define MPI26_PCIEDEV2_CAP_BIT_BUCKET_SUPPORT (0x00000002) 3895 #define MPI26_PCIEDEV2_CAP_SGL_SUPPORT (0x00000001) 3896 3897 /* Defines for the NOIOB field */ 3898 #define MPI26_PCIEDEV2_NOIOB_UNSUPPORTED (0x0000) 3899 3900 /**************************************************************************** 3901 * PCIe Link Config Pages (MPI v2.6 and later) 3902 ****************************************************************************/ 3903 3904 /*PCIe Link Page 1 */ 3905 3906 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_1 { 3907 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3908 U8 Link; /*0x08 */ 3909 U8 Reserved1; /*0x09 */ 3910 U16 Reserved2; /*0x0A */ 3911 U32 CorrectableErrorCount; /*0x0C */ 3912 U16 NonFatalErrorCount; /*0x10 */ 3913 U16 Reserved3; /*0x12 */ 3914 U16 FatalErrorCount; /*0x14 */ 3915 U16 Reserved4; /*0x16 */ 3916 } MPI26_CONFIG_PAGE_PCIELINK_1, *PTR_MPI26_CONFIG_PAGE_PCIELINK_1, 3917 Mpi26PcieLinkPage1_t, *pMpi26PcieLinkPage1_t; 3918 3919 #define MPI26_PCIELINK1_PAGEVERSION (0x00) 3920 3921 /*PCIe Link Page 2 */ 3922 3923 typedef struct _MPI26_PCIELINK2_LINK_EVENT { 3924 U8 LinkEventCode; /*0x00 */ 3925 U8 Reserved1; /*0x01 */ 3926 U16 Reserved2; /*0x02 */ 3927 U32 LinkEventInfo; /*0x04 */ 3928 } MPI26_PCIELINK2_LINK_EVENT, *PTR_MPI26_PCIELINK2_LINK_EVENT, 3929 Mpi26PcieLink2LinkEvent_t, *pMpi26PcieLink2LinkEvent_t; 3930 3931 /*use MPI26_PCIELINK3_EVTCODE_ for the LinkEventCode field */ 3932 3933 3934 /* 3935 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3936 *one and check the value returned for NumLinkEvents at runtime. 3937 */ 3938 #ifndef MPI26_PCIELINK2_LINK_EVENT_MAX 3939 #define MPI26_PCIELINK2_LINK_EVENT_MAX (1) 3940 #endif 3941 3942 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_2 { 3943 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3944 U8 Link; /*0x08 */ 3945 U8 Reserved1; /*0x09 */ 3946 U16 Reserved2; /*0x0A */ 3947 U8 NumLinkEvents; /*0x0C */ 3948 U8 Reserved3; /*0x0D */ 3949 U16 Reserved4; /*0x0E */ 3950 MPI26_PCIELINK2_LINK_EVENT 3951 LinkEvent[MPI26_PCIELINK2_LINK_EVENT_MAX]; /*0x10 */ 3952 } MPI26_CONFIG_PAGE_PCIELINK_2, *PTR_MPI26_CONFIG_PAGE_PCIELINK_2, 3953 Mpi26PcieLinkPage2_t, *pMpi26PcieLinkPage2_t; 3954 3955 #define MPI26_PCIELINK2_PAGEVERSION (0x00) 3956 3957 /*PCIe Link Page 3 */ 3958 3959 typedef struct _MPI26_PCIELINK3_LINK_EVENT_CONFIG { 3960 U8 LinkEventCode; /*0x00 */ 3961 U8 Reserved1; /*0x01 */ 3962 U16 Reserved2; /*0x02 */ 3963 U8 CounterType; /*0x04 */ 3964 U8 ThresholdWindow; /*0x05 */ 3965 U8 TimeUnits; /*0x06 */ 3966 U8 Reserved3; /*0x07 */ 3967 U32 EventThreshold; /*0x08 */ 3968 U16 ThresholdFlags; /*0x0C */ 3969 U16 Reserved4; /*0x0E */ 3970 } MPI26_PCIELINK3_LINK_EVENT_CONFIG, *PTR_MPI26_PCIELINK3_LINK_EVENT_CONFIG, 3971 Mpi26PcieLink3LinkEventConfig_t, *pMpi26PcieLink3LinkEventConfig_t; 3972 3973 /*values for LinkEventCode field */ 3974 #define MPI26_PCIELINK3_EVTCODE_NO_EVENT (0x00) 3975 #define MPI26_PCIELINK3_EVTCODE_CORRECTABLE_ERROR_RECEIVED (0x01) 3976 #define MPI26_PCIELINK3_EVTCODE_NON_FATAL_ERROR_RECEIVED (0x02) 3977 #define MPI26_PCIELINK3_EVTCODE_FATAL_ERROR_RECEIVED (0x03) 3978 #define MPI26_PCIELINK3_EVTCODE_DATA_LINK_ERROR_DETECTED (0x04) 3979 #define MPI26_PCIELINK3_EVTCODE_TRANSACTION_LAYER_ERROR_DETECTED (0x05) 3980 #define MPI26_PCIELINK3_EVTCODE_TLP_ECRC_ERROR_DETECTED (0x06) 3981 #define MPI26_PCIELINK3_EVTCODE_POISONED_TLP (0x07) 3982 #define MPI26_PCIELINK3_EVTCODE_RECEIVED_NAK_DLLP (0x08) 3983 #define MPI26_PCIELINK3_EVTCODE_SENT_NAK_DLLP (0x09) 3984 #define MPI26_PCIELINK3_EVTCODE_LTSSM_RECOVERY_STATE (0x0A) 3985 #define MPI26_PCIELINK3_EVTCODE_LTSSM_RXL0S_STATE (0x0B) 3986 #define MPI26_PCIELINK3_EVTCODE_LTSSM_TXL0S_STATE (0x0C) 3987 #define MPI26_PCIELINK3_EVTCODE_LTSSM_L1_STATE (0x0D) 3988 #define MPI26_PCIELINK3_EVTCODE_LTSSM_DISABLED_STATE (0x0E) 3989 #define MPI26_PCIELINK3_EVTCODE_LTSSM_HOT_RESET_STATE (0x0F) 3990 #define MPI26_PCIELINK3_EVTCODE_SYSTEM_ERROR (0x10) 3991 #define MPI26_PCIELINK3_EVTCODE_DECODE_ERROR (0x11) 3992 #define MPI26_PCIELINK3_EVTCODE_DISPARITY_ERROR (0x12) 3993 3994 /*values for the CounterType field */ 3995 #define MPI26_PCIELINK3_COUNTER_TYPE_WRAPPING (0x00) 3996 #define MPI26_PCIELINK3_COUNTER_TYPE_SATURATING (0x01) 3997 #define MPI26_PCIELINK3_COUNTER_TYPE_PEAK_VALUE (0x02) 3998 3999 /*values for the TimeUnits field */ 4000 #define MPI26_PCIELINK3_TM_UNITS_10_MICROSECONDS (0x00) 4001 #define MPI26_PCIELINK3_TM_UNITS_100_MICROSECONDS (0x01) 4002 #define MPI26_PCIELINK3_TM_UNITS_1_MILLISECOND (0x02) 4003 #define MPI26_PCIELINK3_TM_UNITS_10_MILLISECONDS (0x03) 4004 4005 /*values for the ThresholdFlags field */ 4006 #define MPI26_PCIELINK3_TFLAGS_EVENT_NOTIFY (0x0001) 4007 4008 /* 4009 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 4010 *one and check the value returned for NumLinkEvents at runtime. 4011 */ 4012 #ifndef MPI26_PCIELINK3_LINK_EVENT_MAX 4013 #define MPI26_PCIELINK3_LINK_EVENT_MAX (1) 4014 #endif 4015 4016 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_3 { 4017 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 4018 U8 Link; /*0x08 */ 4019 U8 Reserved1; /*0x09 */ 4020 U16 Reserved2; /*0x0A */ 4021 U8 NumLinkEvents; /*0x0C */ 4022 U8 Reserved3; /*0x0D */ 4023 U16 Reserved4; /*0x0E */ 4024 MPI26_PCIELINK3_LINK_EVENT_CONFIG 4025 LinkEventConfig[MPI26_PCIELINK3_LINK_EVENT_MAX]; /*0x10 */ 4026 } MPI26_CONFIG_PAGE_PCIELINK_3, *PTR_MPI26_CONFIG_PAGE_PCIELINK_3, 4027 Mpi26PcieLinkPage3_t, *pMpi26PcieLinkPage3_t; 4028 4029 #define MPI26_PCIELINK3_PAGEVERSION (0x00) 4030 4031 4032 #endif 4033