1 /* 2 * Copyright 2000-2015 Avago Technologies. All rights reserved. 3 * 4 * 5 * Name: mpi2_cnfg.h 6 * Title: MPI Configuration messages and pages 7 * Creation Date: November 10, 2006 8 * 9 * mpi2_cnfg.h Version: 02.00.35 10 * 11 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 12 * prefix are for use only on MPI v2.5 products, and must not be used 13 * with MPI v2.0 products. Unless otherwise noted, names beginning with 14 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 15 * 16 * Version History 17 * --------------- 18 * 19 * Date Version Description 20 * -------- -------- ------------------------------------------------------ 21 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 22 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags. 23 * Added Manufacturing Page 11. 24 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE 25 * define. 26 * 06-26-07 02.00.02 Adding generic structure for product-specific 27 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS. 28 * Rework of BIOS Page 2 configuration page. 29 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the 30 * forms. 31 * Added configuration pages IOC Page 8 and Driver 32 * Persistent Mapping Page 0. 33 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated 34 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1, 35 * RAID Physical Disk Pages 0 and 1, RAID Configuration 36 * Page 0). 37 * Added new value for AccessStatus field of SAS Device 38 * Page 0 (_SATA_NEEDS_INITIALIZATION). 39 * 10-31-07 02.00.04 Added missing SEPDevHandle field to 40 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 41 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for 42 * NVDATA. 43 * Modified IOC Page 7 to use masks and added field for 44 * SASBroadcastPrimitiveMasks. 45 * Added MPI2_CONFIG_PAGE_BIOS_4. 46 * Added MPI2_CONFIG_PAGE_LOG_0. 47 * 02-29-08 02.00.06 Modified various names to make them 32-character unique. 48 * Added SAS Device IDs. 49 * Updated Integrated RAID configuration pages including 50 * Manufacturing Page 4, IOC Page 6, and RAID Configuration 51 * Page 0. 52 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA. 53 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION. 54 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING. 55 * Added missing MaxNumRoutedSasAddresses field to 56 * MPI2_CONFIG_PAGE_EXPANDER_0. 57 * Added SAS Port Page 0. 58 * Modified structure layout for 59 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0. 60 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use 61 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array. 62 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF 63 * to 0x000000FF. 64 * Added two new values for the Physical Disk Coercion Size 65 * bits in the Flags field of Manufacturing Page 4. 66 * Added product-specific Manufacturing pages 16 to 31. 67 * Modified Flags bits for controlling write cache on SATA 68 * drives in IO Unit Page 1. 69 * Added new bit to AdditionalControlFlags of SAS IO Unit 70 * Page 1 to control Invalid Topology Correction. 71 * Added additional defines for RAID Volume Page 0 72 * VolumeStatusFlags field. 73 * Modified meaning of RAID Volume Page 0 VolumeSettings 74 * define for auto-configure of hot-swap drives. 75 * Added SupportedPhysDisks field to RAID Volume Page 1 and 76 * added related defines. 77 * Added PhysDiskAttributes field (and related defines) to 78 * RAID Physical Disk Page 0. 79 * Added MPI2_SAS_PHYINFO_PHY_VACANT define. 80 * Added three new DiscoveryStatus bits for SAS IO Unit 81 * Page 0 and SAS Expander Page 0. 82 * Removed multiplexing information from SAS IO Unit pages. 83 * Added BootDeviceWaitTime field to SAS IO Unit Page 4. 84 * Removed Zone Address Resolved bit from PhyInfo and from 85 * Expander Page 0 Flags field. 86 * Added two new AccessStatus values to SAS Device Page 0 87 * for indicating routing problems. Added 3 reserved words 88 * to this page. 89 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3. 90 * Inserted missing reserved field into structure for IOC 91 * Page 6. 92 * Added more pending task bits to RAID Volume Page 0 93 * VolumeStatusFlags defines. 94 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define. 95 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0 96 * and SAS Expander Page 0 to flag a downstream initiator 97 * when in simplified routing mode. 98 * Removed SATA Init Failure defines for DiscoveryStatus 99 * fields of SAS IO Unit Page 0 and SAS Expander Page 0. 100 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define. 101 * Added PortGroups, DmaGroup, and ControlGroup fields to 102 * SAS Device Page 0. 103 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO 104 * Unit Page 6. 105 * Added expander reduced functionality data to SAS 106 * Expander Page 0. 107 * Added SAS PHY Page 2 and SAS PHY Page 3. 108 * 07-30-09 02.00.12 Added IO Unit Page 7. 109 * Added new device ids. 110 * Added SAS IO Unit Page 5. 111 * Added partial and slumber power management capable flags 112 * to SAS Device Page 0 Flags field. 113 * Added PhyInfo defines for power condition. 114 * Added Ethernet configuration pages. 115 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY. 116 * Added SAS PHY Page 4 structure and defines. 117 * 02-10-10 02.00.14 Modified the comments for the configuration page 118 * structures that contain an array of data. The host 119 * should use the "count" field in the page data (e.g. the 120 * NumPhys field) to determine the number of valid elements 121 * in the array. 122 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines. 123 * Added PowerManagementCapabilities to IO Unit Page 7. 124 * Added PortWidthModGroup field to 125 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS. 126 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines. 127 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines. 128 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines. 129 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT 130 * define. 131 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define. 132 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define. 133 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing) 134 * defines. 135 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to 136 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for 137 * the Pinout field. 138 * Added BoardTemperature and BoardTemperatureUnits fields 139 * to MPI2_CONFIG_PAGE_IO_UNIT_7. 140 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define 141 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure. 142 * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST. 143 * Added IO Unit Page 8, IO Unit Page 9, 144 * and IO Unit Page 10. 145 * Added SASNotifyPrimitiveMasks field to 146 * MPI2_CONFIG_PAGE_IOC_7. 147 * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec). 148 * 05-25-11 02.00.20 Cleaned up a few comments. 149 * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities 150 * for PCIe link as obsolete. 151 * Added SpinupFlags field containing a Disable Spin-up bit 152 * to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO 153 * Unit Page 4. 154 * 11-18-11 02.00.22 Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT. 155 * Added UEFIVersion field to BIOS Page 1 and defined new 156 * BiosOptions bits. 157 * Incorporating additions for MPI v2.5. 158 * 11-27-12 02.00.23 Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER. 159 * Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID. 160 * 12-20-12 02.00.24 Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as 161 * obsolete for MPI v2.5 and later. 162 * Added some defines for 12G SAS speeds. 163 * 04-09-13 02.00.25 Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK. 164 * Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to 165 * match the specification. 166 * 08-19-13 02.00.26 Added reserved words to MPI2_CONFIG_PAGE_IO_UNIT_7 for 167 * future use. 168 * 12-05-13 02.00.27 Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for 169 * MPI2_CONFIG_PAGE_MAN_7. 170 * Added EnclosureLevel and ConnectorName fields to 171 * MPI2_CONFIG_PAGE_SAS_DEV_0. 172 * Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for 173 * MPI2_CONFIG_PAGE_SAS_DEV_0. 174 * Added EnclosureLevel field to 175 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 176 * Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for 177 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 178 * 01-08-14 02.00.28 Added more defines for the BiosOptions field of 179 * MPI2_CONFIG_PAGE_BIOS_1. 180 * 06-13-14 02.00.29 Added SSUTimeout field to MPI2_CONFIG_PAGE_BIOS_1, and 181 * more defines for the BiosOptions field. 182 * 11-18-14 02.00.30 Updated copyright information. 183 * Added MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG. 184 * Added AdapterOrderAux fields to BIOS Page 3. 185 * 03-16-15 02.00.31 Updated for MPI v2.6. 186 * Added Flags field to IO Unit Page 7. 187 * Added new SAS Phy Event codes 188 * 05-25-15 02.00.33 Added more defines for the BiosOptions field of 189 * MPI2_CONFIG_PAGE_BIOS_1. 190 * 08-25-15 02.00.34 Bumped Header Version. 191 * 12-18-15 02.00.35 Added SATADeviceWaitTime to SAS IO Unit Page 4. 192 * -------------------------------------------------------------------------- 193 */ 194 195 #ifndef MPI2_CNFG_H 196 #define MPI2_CNFG_H 197 198 /***************************************************************************** 199 * Configuration Page Header and defines 200 *****************************************************************************/ 201 202 /*Config Page Header */ 203 typedef struct _MPI2_CONFIG_PAGE_HEADER { 204 U8 PageVersion; /*0x00 */ 205 U8 PageLength; /*0x01 */ 206 U8 PageNumber; /*0x02 */ 207 U8 PageType; /*0x03 */ 208 } MPI2_CONFIG_PAGE_HEADER, *PTR_MPI2_CONFIG_PAGE_HEADER, 209 Mpi2ConfigPageHeader_t, *pMpi2ConfigPageHeader_t; 210 211 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION { 212 MPI2_CONFIG_PAGE_HEADER Struct; 213 U8 Bytes[4]; 214 U16 Word16[2]; 215 U32 Word32; 216 } MPI2_CONFIG_PAGE_HEADER_UNION, *PTR_MPI2_CONFIG_PAGE_HEADER_UNION, 217 Mpi2ConfigPageHeaderUnion, *pMpi2ConfigPageHeaderUnion; 218 219 /*Extended Config Page Header */ 220 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER { 221 U8 PageVersion; /*0x00 */ 222 U8 Reserved1; /*0x01 */ 223 U8 PageNumber; /*0x02 */ 224 U8 PageType; /*0x03 */ 225 U16 ExtPageLength; /*0x04 */ 226 U8 ExtPageType; /*0x06 */ 227 U8 Reserved2; /*0x07 */ 228 } MPI2_CONFIG_EXTENDED_PAGE_HEADER, 229 *PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER, 230 Mpi2ConfigExtendedPageHeader_t, 231 *pMpi2ConfigExtendedPageHeader_t; 232 233 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION { 234 MPI2_CONFIG_PAGE_HEADER Struct; 235 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext; 236 U8 Bytes[8]; 237 U16 Word16[4]; 238 U32 Word32[2]; 239 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 240 *PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 241 Mpi2ConfigPageExtendedHeaderUnion, 242 *pMpi2ConfigPageExtendedHeaderUnion; 243 244 245 /*PageType field values */ 246 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 247 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 248 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 249 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0) 250 251 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00) 252 #define MPI2_CONFIG_PAGETYPE_IOC (0x01) 253 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02) 254 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 255 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09) 256 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 257 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F) 258 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F) 259 260 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF) 261 262 263 /*ExtPageType field values */ 264 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 265 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 266 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 267 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 268 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14) 269 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 270 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 271 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 272 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 273 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19) 274 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A) 275 276 277 /***************************************************************************** 278 * PageAddress defines 279 *****************************************************************************/ 280 281 /*RAID Volume PageAddress format */ 282 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000) 283 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 284 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000) 285 286 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF) 287 288 289 /*RAID Physical Disk PageAddress format */ 290 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000) 291 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000) 292 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000) 293 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000) 294 295 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 296 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF) 297 298 299 /*SAS Expander PageAddress format */ 300 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 301 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 302 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000) 303 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000) 304 305 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) 306 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) 307 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 308 309 310 /*SAS Device PageAddress format */ 311 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 312 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 313 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000) 314 315 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 316 317 318 /*SAS PHY PageAddress format */ 319 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 320 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 321 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000) 322 323 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 324 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 325 326 327 /*SAS Port PageAddress format */ 328 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000) 329 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 330 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 331 332 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF) 333 334 335 /*SAS Enclosure PageAddress format */ 336 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 337 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 338 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 339 340 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 341 342 343 /*RAID Configuration PageAddress format */ 344 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000) 345 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000) 346 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000) 347 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000) 348 349 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF) 350 351 352 /*Driver Persistent Mapping PageAddress format */ 353 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000) 354 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000) 355 356 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000) 357 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16) 358 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF) 359 360 361 /*Ethernet PageAddress format */ 362 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000) 363 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000) 364 365 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF) 366 367 368 /**************************************************************************** 369 * Configuration messages 370 ****************************************************************************/ 371 372 /*Configuration Request Message */ 373 typedef struct _MPI2_CONFIG_REQUEST { 374 U8 Action; /*0x00 */ 375 U8 SGLFlags; /*0x01 */ 376 U8 ChainOffset; /*0x02 */ 377 U8 Function; /*0x03 */ 378 U16 ExtPageLength; /*0x04 */ 379 U8 ExtPageType; /*0x06 */ 380 U8 MsgFlags; /*0x07 */ 381 U8 VP_ID; /*0x08 */ 382 U8 VF_ID; /*0x09 */ 383 U16 Reserved1; /*0x0A */ 384 U8 Reserved2; /*0x0C */ 385 U8 ProxyVF_ID; /*0x0D */ 386 U16 Reserved4; /*0x0E */ 387 U32 Reserved3; /*0x10 */ 388 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */ 389 U32 PageAddress; /*0x18 */ 390 MPI2_SGE_IO_UNION PageBufferSGE; /*0x1C */ 391 } MPI2_CONFIG_REQUEST, *PTR_MPI2_CONFIG_REQUEST, 392 Mpi2ConfigRequest_t, *pMpi2ConfigRequest_t; 393 394 /*values for the Action field */ 395 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00) 396 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 397 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 398 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03) 399 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 400 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 401 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 402 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07) 403 404 /*use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */ 405 406 407 /*Config Reply Message */ 408 typedef struct _MPI2_CONFIG_REPLY { 409 U8 Action; /*0x00 */ 410 U8 SGLFlags; /*0x01 */ 411 U8 MsgLength; /*0x02 */ 412 U8 Function; /*0x03 */ 413 U16 ExtPageLength; /*0x04 */ 414 U8 ExtPageType; /*0x06 */ 415 U8 MsgFlags; /*0x07 */ 416 U8 VP_ID; /*0x08 */ 417 U8 VF_ID; /*0x09 */ 418 U16 Reserved1; /*0x0A */ 419 U16 Reserved2; /*0x0C */ 420 U16 IOCStatus; /*0x0E */ 421 U32 IOCLogInfo; /*0x10 */ 422 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */ 423 } MPI2_CONFIG_REPLY, *PTR_MPI2_CONFIG_REPLY, 424 Mpi2ConfigReply_t, *pMpi2ConfigReply_t; 425 426 427 428 /***************************************************************************** 429 * 430 * C o n f i g u r a t i o n P a g e s 431 * 432 *****************************************************************************/ 433 434 /**************************************************************************** 435 * Manufacturing Config pages 436 ****************************************************************************/ 437 438 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000) 439 440 /*MPI v2.0 SAS products */ 441 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070) 442 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072) 443 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074) 444 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076) 445 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077) 446 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064) 447 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065) 448 449 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E) 450 451 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080) 452 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081) 453 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082) 454 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083) 455 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084) 456 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085) 457 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086) 458 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087) 459 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E) 460 461 /*MPI v2.5 SAS products */ 462 #define MPI25_MFGPAGE_DEVID_SAS3004 (0x0096) 463 #define MPI25_MFGPAGE_DEVID_SAS3008 (0x0097) 464 #define MPI25_MFGPAGE_DEVID_SAS3108_1 (0x0090) 465 #define MPI25_MFGPAGE_DEVID_SAS3108_2 (0x0091) 466 #define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094) 467 #define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095) 468 469 /* MPI v2.6 SAS Products */ 470 #define MPI26_MFGPAGE_DEVID_SAS3216 (0x00C9) 471 #define MPI26_MFGPAGE_DEVID_SAS3224 (0x00C4) 472 #define MPI26_MFGPAGE_DEVID_SAS3316_1 (0x00C5) 473 #define MPI26_MFGPAGE_DEVID_SAS3316_2 (0x00C6) 474 #define MPI26_MFGPAGE_DEVID_SAS3316_3 (0x00C7) 475 #define MPI26_MFGPAGE_DEVID_SAS3316_4 (0x00C8) 476 #define MPI26_MFGPAGE_DEVID_SAS3324_1 (0x00C0) 477 #define MPI26_MFGPAGE_DEVID_SAS3324_2 (0x00C1) 478 #define MPI26_MFGPAGE_DEVID_SAS3324_3 (0x00C2) 479 #define MPI26_MFGPAGE_DEVID_SAS3324_4 (0x00C3) 480 481 /*Manufacturing Page 0 */ 482 483 typedef struct _MPI2_CONFIG_PAGE_MAN_0 { 484 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 485 U8 ChipName[16]; /*0x04 */ 486 U8 ChipRevision[8]; /*0x14 */ 487 U8 BoardName[16]; /*0x1C */ 488 U8 BoardAssembly[16]; /*0x2C */ 489 U8 BoardTracerNumber[16]; /*0x3C */ 490 } MPI2_CONFIG_PAGE_MAN_0, 491 *PTR_MPI2_CONFIG_PAGE_MAN_0, 492 Mpi2ManufacturingPage0_t, 493 *pMpi2ManufacturingPage0_t; 494 495 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00) 496 497 498 /*Manufacturing Page 1 */ 499 500 typedef struct _MPI2_CONFIG_PAGE_MAN_1 { 501 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 502 U8 VPD[256]; /*0x04 */ 503 } MPI2_CONFIG_PAGE_MAN_1, 504 *PTR_MPI2_CONFIG_PAGE_MAN_1, 505 Mpi2ManufacturingPage1_t, 506 *pMpi2ManufacturingPage1_t; 507 508 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00) 509 510 511 typedef struct _MPI2_CHIP_REVISION_ID { 512 U16 DeviceID; /*0x00 */ 513 U8 PCIRevisionID; /*0x02 */ 514 U8 Reserved; /*0x03 */ 515 } MPI2_CHIP_REVISION_ID, *PTR_MPI2_CHIP_REVISION_ID, 516 Mpi2ChipRevisionId_t, *pMpi2ChipRevisionId_t; 517 518 519 /*Manufacturing Page 2 */ 520 521 /* 522 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 523 *one and check Header.PageLength at runtime. 524 */ 525 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS 526 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 527 #endif 528 529 typedef struct _MPI2_CONFIG_PAGE_MAN_2 { 530 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 531 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */ 532 U32 533 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/*0x08 */ 534 } MPI2_CONFIG_PAGE_MAN_2, 535 *PTR_MPI2_CONFIG_PAGE_MAN_2, 536 Mpi2ManufacturingPage2_t, 537 *pMpi2ManufacturingPage2_t; 538 539 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00) 540 541 542 /*Manufacturing Page 3 */ 543 544 /* 545 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 546 *one and check Header.PageLength at runtime. 547 */ 548 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS 549 #define MPI2_MAN_PAGE_3_INFO_WORDS (1) 550 #endif 551 552 typedef struct _MPI2_CONFIG_PAGE_MAN_3 { 553 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 554 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */ 555 U32 556 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/*0x08 */ 557 } MPI2_CONFIG_PAGE_MAN_3, 558 *PTR_MPI2_CONFIG_PAGE_MAN_3, 559 Mpi2ManufacturingPage3_t, 560 *pMpi2ManufacturingPage3_t; 561 562 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00) 563 564 565 /*Manufacturing Page 4 */ 566 567 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS { 568 U8 PowerSaveFlags; /*0x00 */ 569 U8 InternalOperationsSleepTime; /*0x01 */ 570 U8 InternalOperationsRunTime; /*0x02 */ 571 U8 HostIdleTime; /*0x03 */ 572 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 573 *PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 574 Mpi2ManPage4PwrSaveSettings_t, 575 *pMpi2ManPage4PwrSaveSettings_t; 576 577 /*defines for the PowerSaveFlags field */ 578 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03) 579 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00) 580 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01) 581 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02) 582 583 typedef struct _MPI2_CONFIG_PAGE_MAN_4 { 584 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 585 U32 Reserved1; /*0x04 */ 586 U32 Flags; /*0x08 */ 587 U8 InquirySize; /*0x0C */ 588 U8 Reserved2; /*0x0D */ 589 U16 Reserved3; /*0x0E */ 590 U8 InquiryData[56]; /*0x10 */ 591 U32 RAID0VolumeSettings; /*0x48 */ 592 U32 RAID1EVolumeSettings; /*0x4C */ 593 U32 RAID1VolumeSettings; /*0x50 */ 594 U32 RAID10VolumeSettings; /*0x54 */ 595 U32 Reserved4; /*0x58 */ 596 U32 Reserved5; /*0x5C */ 597 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /*0x60 */ 598 U8 MaxOCEDisks; /*0x64 */ 599 U8 ResyncRate; /*0x65 */ 600 U16 DataScrubDuration; /*0x66 */ 601 U8 MaxHotSpares; /*0x68 */ 602 U8 MaxPhysDisksPerVol; /*0x69 */ 603 U8 MaxPhysDisks; /*0x6A */ 604 U8 MaxVolumes; /*0x6B */ 605 } MPI2_CONFIG_PAGE_MAN_4, 606 *PTR_MPI2_CONFIG_PAGE_MAN_4, 607 Mpi2ManufacturingPage4_t, 608 *pMpi2ManufacturingPage4_t; 609 610 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A) 611 612 /*Manufacturing Page 4 Flags field */ 613 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000) 614 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000) 615 616 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000) 617 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000) 618 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000) 619 620 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00) 621 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000) 622 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400) 623 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800) 624 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00) 625 626 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300) 627 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000) 628 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100) 629 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200) 630 631 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080) 632 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040) 633 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020) 634 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010) 635 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008) 636 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004) 637 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002) 638 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001) 639 640 641 /*Manufacturing Page 5 */ 642 643 /* 644 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 645 *one and check the value returned for NumPhys at runtime. 646 */ 647 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES 648 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1) 649 #endif 650 651 typedef struct _MPI2_MANUFACTURING5_ENTRY { 652 U64 WWID; /*0x00 */ 653 U64 DeviceName; /*0x08 */ 654 } MPI2_MANUFACTURING5_ENTRY, 655 *PTR_MPI2_MANUFACTURING5_ENTRY, 656 Mpi2Manufacturing5Entry_t, 657 *pMpi2Manufacturing5Entry_t; 658 659 typedef struct _MPI2_CONFIG_PAGE_MAN_5 { 660 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 661 U8 NumPhys; /*0x04 */ 662 U8 Reserved1; /*0x05 */ 663 U16 Reserved2; /*0x06 */ 664 U32 Reserved3; /*0x08 */ 665 U32 Reserved4; /*0x0C */ 666 MPI2_MANUFACTURING5_ENTRY 667 Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/*0x08 */ 668 } MPI2_CONFIG_PAGE_MAN_5, 669 *PTR_MPI2_CONFIG_PAGE_MAN_5, 670 Mpi2ManufacturingPage5_t, 671 *pMpi2ManufacturingPage5_t; 672 673 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03) 674 675 676 /*Manufacturing Page 6 */ 677 678 typedef struct _MPI2_CONFIG_PAGE_MAN_6 { 679 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 680 U32 ProductSpecificInfo;/*0x04 */ 681 } MPI2_CONFIG_PAGE_MAN_6, 682 *PTR_MPI2_CONFIG_PAGE_MAN_6, 683 Mpi2ManufacturingPage6_t, 684 *pMpi2ManufacturingPage6_t; 685 686 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00) 687 688 689 /*Manufacturing Page 7 */ 690 691 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO { 692 U32 Pinout; /*0x00 */ 693 U8 Connector[16]; /*0x04 */ 694 U8 Location; /*0x14 */ 695 U8 ReceptacleID; /*0x15 */ 696 U16 Slot; /*0x16 */ 697 U32 Reserved2; /*0x18 */ 698 } MPI2_MANPAGE7_CONNECTOR_INFO, 699 *PTR_MPI2_MANPAGE7_CONNECTOR_INFO, 700 Mpi2ManPage7ConnectorInfo_t, 701 *pMpi2ManPage7ConnectorInfo_t; 702 703 /*defines for the Pinout field */ 704 #define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00) 705 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8) 706 707 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF) 708 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00) 709 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01) 710 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02) 711 #define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03) 712 #define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04) 713 #define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05) 714 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06) 715 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07) 716 #define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08) 717 #define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09) 718 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A) 719 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B) 720 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C) 721 #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D) 722 723 /*defines for the Location field */ 724 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01) 725 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02) 726 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04) 727 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08) 728 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10) 729 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 730 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 731 732 /* 733 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 734 *one and check the value returned for NumPhys at runtime. 735 */ 736 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX 737 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1) 738 #endif 739 740 typedef struct _MPI2_CONFIG_PAGE_MAN_7 { 741 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 742 U32 Reserved1; /*0x04 */ 743 U32 Reserved2; /*0x08 */ 744 U32 Flags; /*0x0C */ 745 U8 EnclosureName[16]; /*0x10 */ 746 U8 NumPhys; /*0x20 */ 747 U8 Reserved3; /*0x21 */ 748 U16 Reserved4; /*0x22 */ 749 MPI2_MANPAGE7_CONNECTOR_INFO 750 ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /*0x24 */ 751 } MPI2_CONFIG_PAGE_MAN_7, 752 *PTR_MPI2_CONFIG_PAGE_MAN_7, 753 Mpi2ManufacturingPage7_t, 754 *pMpi2ManufacturingPage7_t; 755 756 #define MPI2_MANUFACTURING7_PAGEVERSION (0x01) 757 758 /*defines for the Flags field */ 759 #define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL (0x00000008) 760 #define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER (0x00000002) 761 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 762 763 764 /* 765 *Generic structure to use for product-specific manufacturing pages 766 *(currently Manufacturing Page 8 through Manufacturing Page 31). 767 */ 768 769 typedef struct _MPI2_CONFIG_PAGE_MAN_PS { 770 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 771 U32 ProductSpecificInfo;/*0x04 */ 772 } MPI2_CONFIG_PAGE_MAN_PS, 773 *PTR_MPI2_CONFIG_PAGE_MAN_PS, 774 Mpi2ManufacturingPagePS_t, 775 *pMpi2ManufacturingPagePS_t; 776 777 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00) 778 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00) 779 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00) 780 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00) 781 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00) 782 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00) 783 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00) 784 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00) 785 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00) 786 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00) 787 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00) 788 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00) 789 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00) 790 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00) 791 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00) 792 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00) 793 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00) 794 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00) 795 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00) 796 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00) 797 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00) 798 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00) 799 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00) 800 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00) 801 802 803 /**************************************************************************** 804 * IO Unit Config Pages 805 ****************************************************************************/ 806 807 /*IO Unit Page 0 */ 808 809 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 { 810 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 811 U64 UniqueValue; /*0x04 */ 812 MPI2_VERSION_UNION NvdataVersionDefault; /*0x08 */ 813 MPI2_VERSION_UNION NvdataVersionPersistent; /*0x0A */ 814 } MPI2_CONFIG_PAGE_IO_UNIT_0, 815 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_0, 816 Mpi2IOUnitPage0_t, *pMpi2IOUnitPage0_t; 817 818 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02) 819 820 821 /*IO Unit Page 1 */ 822 823 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 { 824 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 825 U32 Flags; /*0x04 */ 826 } MPI2_CONFIG_PAGE_IO_UNIT_1, 827 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_1, 828 Mpi2IOUnitPage1_t, *pMpi2IOUnitPage1_t; 829 830 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04) 831 832 /*IO Unit Page 1 Flags defines */ 833 #define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK (0x00004000) 834 #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000) 835 #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000) 836 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800) 837 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600) 838 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9) 839 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000) 840 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200) 841 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400) 842 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 843 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040) 844 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020) 845 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 846 847 848 /*IO Unit Page 3 */ 849 850 /* 851 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 852 *one and check the value returned for GPIOCount at runtime. 853 */ 854 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX 855 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 856 #endif 857 858 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 { 859 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 860 U8 GPIOCount; /*0x04 */ 861 U8 Reserved1; /*0x05 */ 862 U16 Reserved2; /*0x06 */ 863 U16 864 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/*0x08 */ 865 } MPI2_CONFIG_PAGE_IO_UNIT_3, 866 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_3, 867 Mpi2IOUnitPage3_t, *pMpi2IOUnitPage3_t; 868 869 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01) 870 871 /*defines for IO Unit Page 3 GPIOVal field */ 872 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC) 873 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 874 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000) 875 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001) 876 877 878 /*IO Unit Page 5 */ 879 880 /* 881 *Upper layer code (drivers, utilities, etc.) should leave this define set to 882 *one and check the value returned for NumDmaEngines at runtime. 883 */ 884 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES 885 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1) 886 #endif 887 888 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 { 889 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 890 U64 891 RaidAcceleratorBufferBaseAddress; /*0x04 */ 892 U64 893 RaidAcceleratorBufferSize; /*0x0C */ 894 U64 895 RaidAcceleratorControlBaseAddress; /*0x14 */ 896 U8 RAControlSize; /*0x1C */ 897 U8 NumDmaEngines; /*0x1D */ 898 U8 RAMinControlSize; /*0x1E */ 899 U8 RAMaxControlSize; /*0x1F */ 900 U32 Reserved1; /*0x20 */ 901 U32 Reserved2; /*0x24 */ 902 U32 Reserved3; /*0x28 */ 903 U32 904 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /*0x2C */ 905 } MPI2_CONFIG_PAGE_IO_UNIT_5, 906 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_5, 907 Mpi2IOUnitPage5_t, *pMpi2IOUnitPage5_t; 908 909 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00) 910 911 /*defines for IO Unit Page 5 DmaEngineCapabilities field */ 912 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFFFF0000) 913 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16) 914 915 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008) 916 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004) 917 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002) 918 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001) 919 920 921 /*IO Unit Page 6 */ 922 923 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 { 924 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 925 U16 Flags; /*0x04 */ 926 U8 RAHostControlSize; /*0x06 */ 927 U8 Reserved0; /*0x07 */ 928 U64 929 RaidAcceleratorHostControlBaseAddress; /*0x08 */ 930 U32 Reserved1; /*0x10 */ 931 U32 Reserved2; /*0x14 */ 932 U32 Reserved3; /*0x18 */ 933 } MPI2_CONFIG_PAGE_IO_UNIT_6, 934 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_6, 935 Mpi2IOUnitPage6_t, *pMpi2IOUnitPage6_t; 936 937 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00) 938 939 /*defines for IO Unit Page 6 Flags field */ 940 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001) 941 942 943 /*IO Unit Page 7 */ 944 945 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 { 946 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 947 U8 CurrentPowerMode; /*0x04 */ 948 U8 PreviousPowerMode; /*0x05 */ 949 U8 PCIeWidth; /*0x06 */ 950 U8 PCIeSpeed; /*0x07 */ 951 U32 ProcessorState; /*0x08 */ 952 U32 953 PowerManagementCapabilities; /*0x0C */ 954 U16 IOCTemperature; /*0x10 */ 955 U8 956 IOCTemperatureUnits; /*0x12 */ 957 U8 IOCSpeed; /*0x13 */ 958 U16 BoardTemperature; /*0x14 */ 959 U8 960 BoardTemperatureUnits; /*0x16 */ 961 U8 Reserved3; /*0x17 */ 962 U32 BoardPowerRequirement; /*0x18 */ 963 U32 PCISlotPowerAllocation; /*0x1C */ 964 /* reserved prior to MPI v2.6 */ 965 U8 Flags; /* 0x20 */ 966 U8 Reserved6; /* 0x21 */ 967 U16 Reserved7; /* 0x22 */ 968 U32 Reserved8; /* 0x24 */ 969 } MPI2_CONFIG_PAGE_IO_UNIT_7, 970 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_7, 971 Mpi2IOUnitPage7_t, *pMpi2IOUnitPage7_t; 972 973 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x05) 974 975 /*defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */ 976 #define MPI25_IOUNITPAGE7_PM_INIT_MASK (0xC0) 977 #define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE (0x00) 978 #define MPI25_IOUNITPAGE7_PM_INIT_HOST (0x40) 979 #define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT (0x80) 980 #define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA (0xC0) 981 982 #define MPI25_IOUNITPAGE7_PM_MODE_MASK (0x07) 983 #define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE (0x00) 984 #define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN (0x01) 985 #define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER (0x04) 986 #define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER (0x05) 987 #define MPI25_IOUNITPAGE7_PM_MODE_STANDBY (0x06) 988 989 990 /*defines for IO Unit Page 7 PCIeWidth field */ 991 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01) 992 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02) 993 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04) 994 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08) 995 996 /*defines for IO Unit Page 7 PCIeSpeed field */ 997 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00) 998 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01) 999 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02) 1000 1001 /*defines for IO Unit Page 7 ProcessorState field */ 1002 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F) 1003 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0) 1004 1005 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00) 1006 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01) 1007 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02) 1008 1009 /*defines for IO Unit Page 7 PowerManagementCapabilities field */ 1010 #define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE (0x00400000) 1011 #define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE (0x00200000) 1012 #define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE (0x00100000) 1013 #define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE (0x00040000) 1014 #define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE (0x00020000) 1015 #define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE (0x00010000) 1016 #define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE (0x00004000) 1017 #define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE (0x00002000) 1018 #define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE (0x00001000) 1019 #define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED (0x00000400) 1020 #define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED (0x00000200) 1021 #define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED (0x00000100) 1022 #define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED (0x00000040) 1023 #define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED (0x00000020) 1024 #define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED (0x00000010) 1025 #define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE (0x00000008) 1026 #define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE (0x00000004) 1027 #define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE (0x00000002) 1028 #define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE (0x00000001) 1029 1030 /*obsolete names for the PowerManagementCapabilities bits (above) */ 1031 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400) 1032 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200) 1033 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100) 1034 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /*obsolete */ 1035 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /*obsolete */ 1036 1037 1038 /*defines for IO Unit Page 7 IOCTemperatureUnits field */ 1039 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00) 1040 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01) 1041 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02) 1042 1043 /*defines for IO Unit Page 7 IOCSpeed field */ 1044 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01) 1045 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02) 1046 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04) 1047 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08) 1048 1049 /*defines for IO Unit Page 7 BoardTemperatureUnits field */ 1050 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00) 1051 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01) 1052 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02) 1053 1054 /* defines for IO Unit Page 7 Flags field */ 1055 #define MPI2_IOUNITPAGE7_FLAG_CABLE_POWER_EXC (0x01) 1056 1057 /*IO Unit Page 8 */ 1058 1059 #define MPI2_IOUNIT8_NUM_THRESHOLDS (4) 1060 1061 typedef struct _MPI2_IOUNIT8_SENSOR { 1062 U16 Flags; /*0x00 */ 1063 U16 Reserved1; /*0x02 */ 1064 U16 1065 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /*0x04 */ 1066 U32 Reserved2; /*0x0C */ 1067 U32 Reserved3; /*0x10 */ 1068 U32 Reserved4; /*0x14 */ 1069 } MPI2_IOUNIT8_SENSOR, *PTR_MPI2_IOUNIT8_SENSOR, 1070 Mpi2IOUnit8Sensor_t, *pMpi2IOUnit8Sensor_t; 1071 1072 /*defines for IO Unit Page 8 Sensor Flags field */ 1073 #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008) 1074 #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004) 1075 #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002) 1076 #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001) 1077 1078 /* 1079 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1080 *one and check the value returned for NumSensors at runtime. 1081 */ 1082 #ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES 1083 #define MPI2_IOUNITPAGE8_SENSOR_ENTRIES (1) 1084 #endif 1085 1086 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 { 1087 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1088 U32 Reserved1; /*0x04 */ 1089 U32 Reserved2; /*0x08 */ 1090 U8 NumSensors; /*0x0C */ 1091 U8 PollingInterval; /*0x0D */ 1092 U16 Reserved3; /*0x0E */ 1093 MPI2_IOUNIT8_SENSOR 1094 Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/*0x10 */ 1095 } MPI2_CONFIG_PAGE_IO_UNIT_8, 1096 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_8, 1097 Mpi2IOUnitPage8_t, *pMpi2IOUnitPage8_t; 1098 1099 #define MPI2_IOUNITPAGE8_PAGEVERSION (0x00) 1100 1101 1102 /*IO Unit Page 9 */ 1103 1104 typedef struct _MPI2_IOUNIT9_SENSOR { 1105 U16 CurrentTemperature; /*0x00 */ 1106 U16 Reserved1; /*0x02 */ 1107 U8 Flags; /*0x04 */ 1108 U8 Reserved2; /*0x05 */ 1109 U16 Reserved3; /*0x06 */ 1110 U32 Reserved4; /*0x08 */ 1111 U32 Reserved5; /*0x0C */ 1112 } MPI2_IOUNIT9_SENSOR, *PTR_MPI2_IOUNIT9_SENSOR, 1113 Mpi2IOUnit9Sensor_t, *pMpi2IOUnit9Sensor_t; 1114 1115 /*defines for IO Unit Page 9 Sensor Flags field */ 1116 #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01) 1117 1118 /* 1119 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1120 *one and check the value returned for NumSensors at runtime. 1121 */ 1122 #ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES 1123 #define MPI2_IOUNITPAGE9_SENSOR_ENTRIES (1) 1124 #endif 1125 1126 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 { 1127 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1128 U32 Reserved1; /*0x04 */ 1129 U32 Reserved2; /*0x08 */ 1130 U8 NumSensors; /*0x0C */ 1131 U8 Reserved4; /*0x0D */ 1132 U16 Reserved3; /*0x0E */ 1133 MPI2_IOUNIT9_SENSOR 1134 Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/*0x10 */ 1135 } MPI2_CONFIG_PAGE_IO_UNIT_9, 1136 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_9, 1137 Mpi2IOUnitPage9_t, *pMpi2IOUnitPage9_t; 1138 1139 #define MPI2_IOUNITPAGE9_PAGEVERSION (0x00) 1140 1141 1142 /*IO Unit Page 10 */ 1143 1144 typedef struct _MPI2_IOUNIT10_FUNCTION { 1145 U8 CreditPercent; /*0x00 */ 1146 U8 Reserved1; /*0x01 */ 1147 U16 Reserved2; /*0x02 */ 1148 } MPI2_IOUNIT10_FUNCTION, 1149 *PTR_MPI2_IOUNIT10_FUNCTION, 1150 Mpi2IOUnit10Function_t, 1151 *pMpi2IOUnit10Function_t; 1152 1153 /* 1154 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1155 *one and check the value returned for NumFunctions at runtime. 1156 */ 1157 #ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES 1158 #define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES (1) 1159 #endif 1160 1161 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 { 1162 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1163 U8 NumFunctions; /*0x04 */ 1164 U8 Reserved1; /*0x05 */ 1165 U16 Reserved2; /*0x06 */ 1166 U32 Reserved3; /*0x08 */ 1167 U32 Reserved4; /*0x0C */ 1168 MPI2_IOUNIT10_FUNCTION 1169 Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];/*0x10 */ 1170 } MPI2_CONFIG_PAGE_IO_UNIT_10, 1171 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_10, 1172 Mpi2IOUnitPage10_t, *pMpi2IOUnitPage10_t; 1173 1174 #define MPI2_IOUNITPAGE10_PAGEVERSION (0x01) 1175 1176 1177 /* IO Unit Page 11 (for MPI v2.6 and later) */ 1178 1179 typedef struct _MPI26_IOUNIT11_SPINUP_GROUP { 1180 U8 MaxTargetSpinup; /* 0x00 */ 1181 U8 SpinupDelay; /* 0x01 */ 1182 U8 SpinupFlags; /* 0x02 */ 1183 U8 Reserved1; /* 0x03 */ 1184 } MPI26_IOUNIT11_SPINUP_GROUP, 1185 *PTR_MPI26_IOUNIT11_SPINUP_GROUP, 1186 Mpi26IOUnit11SpinupGroup_t, 1187 *pMpi26IOUnit11SpinupGroup_t; 1188 1189 /* defines for IO Unit Page 11 SpinupFlags */ 1190 #define MPI26_IOUNITPAGE11_SPINUP_DISABLE_FLAG (0x01) 1191 1192 1193 /* 1194 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1195 * four and check the value returned for NumPhys at runtime. 1196 */ 1197 #ifndef MPI26_IOUNITPAGE11_PHY_MAX 1198 #define MPI26_IOUNITPAGE11_PHY_MAX (4) 1199 #endif 1200 1201 typedef struct _MPI26_CONFIG_PAGE_IO_UNIT_11 { 1202 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1203 U32 Reserved1; /*0x04 */ 1204 MPI26_IOUNIT11_SPINUP_GROUP SpinupGroupParameters[4]; /*0x08 */ 1205 U32 Reserved2; /*0x18 */ 1206 U32 Reserved3; /*0x1C */ 1207 U32 Reserved4; /*0x20 */ 1208 U8 BootDeviceWaitTime; /*0x24 */ 1209 U8 Reserved5; /*0x25 */ 1210 U16 Reserved6; /*0x26 */ 1211 U8 NumPhys; /*0x28 */ 1212 U8 PEInitialSpinupDelay; /*0x29 */ 1213 U8 PEReplyDelay; /*0x2A */ 1214 U8 Flags; /*0x2B */ 1215 U8 PHY[MPI26_IOUNITPAGE11_PHY_MAX];/*0x2C */ 1216 } MPI26_CONFIG_PAGE_IO_UNIT_11, 1217 *PTR_MPI26_CONFIG_PAGE_IO_UNIT_11, 1218 Mpi26IOUnitPage11_t, 1219 *pMpi26IOUnitPage11_t; 1220 1221 #define MPI26_IOUNITPAGE11_PAGEVERSION (0x00) 1222 1223 /* defines for Flags field */ 1224 #define MPI26_IOUNITPAGE11_FLAGS_AUTO_PORTENABLE (0x01) 1225 1226 /* defines for PHY field */ 1227 #define MPI26_IOUNITPAGE11_PHY_SPINUP_GROUP_MASK (0x03) 1228 1229 1230 1231 1232 1233 1234 /**************************************************************************** 1235 * IOC Config Pages 1236 ****************************************************************************/ 1237 1238 /*IOC Page 0 */ 1239 1240 typedef struct _MPI2_CONFIG_PAGE_IOC_0 { 1241 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1242 U32 Reserved1; /*0x04 */ 1243 U32 Reserved2; /*0x08 */ 1244 U16 VendorID; /*0x0C */ 1245 U16 DeviceID; /*0x0E */ 1246 U8 RevisionID; /*0x10 */ 1247 U8 Reserved3; /*0x11 */ 1248 U16 Reserved4; /*0x12 */ 1249 U32 ClassCode; /*0x14 */ 1250 U16 SubsystemVendorID; /*0x18 */ 1251 U16 SubsystemID; /*0x1A */ 1252 } MPI2_CONFIG_PAGE_IOC_0, 1253 *PTR_MPI2_CONFIG_PAGE_IOC_0, 1254 Mpi2IOCPage0_t, *pMpi2IOCPage0_t; 1255 1256 #define MPI2_IOCPAGE0_PAGEVERSION (0x02) 1257 1258 1259 /*IOC Page 1 */ 1260 1261 typedef struct _MPI2_CONFIG_PAGE_IOC_1 { 1262 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1263 U32 Flags; /*0x04 */ 1264 U32 CoalescingTimeout; /*0x08 */ 1265 U8 CoalescingDepth; /*0x0C */ 1266 U8 PCISlotNum; /*0x0D */ 1267 U8 PCIBusNum; /*0x0E */ 1268 U8 PCIDomainSegment; /*0x0F */ 1269 U32 Reserved1; /*0x10 */ 1270 U32 Reserved2; /*0x14 */ 1271 } MPI2_CONFIG_PAGE_IOC_1, 1272 *PTR_MPI2_CONFIG_PAGE_IOC_1, 1273 Mpi2IOCPage1_t, *pMpi2IOCPage1_t; 1274 1275 #define MPI2_IOCPAGE1_PAGEVERSION (0x05) 1276 1277 /*defines for IOC Page 1 Flags field */ 1278 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001) 1279 1280 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 1281 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF) 1282 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF) 1283 1284 /*IOC Page 6 */ 1285 1286 typedef struct _MPI2_CONFIG_PAGE_IOC_6 { 1287 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1288 U32 1289 CapabilitiesFlags; /*0x04 */ 1290 U8 MaxDrivesRAID0; /*0x08 */ 1291 U8 MaxDrivesRAID1; /*0x09 */ 1292 U8 1293 MaxDrivesRAID1E; /*0x0A */ 1294 U8 1295 MaxDrivesRAID10; /*0x0B */ 1296 U8 MinDrivesRAID0; /*0x0C */ 1297 U8 MinDrivesRAID1; /*0x0D */ 1298 U8 1299 MinDrivesRAID1E; /*0x0E */ 1300 U8 1301 MinDrivesRAID10; /*0x0F */ 1302 U32 Reserved1; /*0x10 */ 1303 U8 1304 MaxGlobalHotSpares; /*0x14 */ 1305 U8 MaxPhysDisks; /*0x15 */ 1306 U8 MaxVolumes; /*0x16 */ 1307 U8 MaxConfigs; /*0x17 */ 1308 U8 MaxOCEDisks; /*0x18 */ 1309 U8 Reserved2; /*0x19 */ 1310 U16 Reserved3; /*0x1A */ 1311 U32 1312 SupportedStripeSizeMapRAID0; /*0x1C */ 1313 U32 1314 SupportedStripeSizeMapRAID1E; /*0x20 */ 1315 U32 1316 SupportedStripeSizeMapRAID10; /*0x24 */ 1317 U32 Reserved4; /*0x28 */ 1318 U32 Reserved5; /*0x2C */ 1319 U16 1320 DefaultMetadataSize; /*0x30 */ 1321 U16 Reserved6; /*0x32 */ 1322 U16 1323 MaxBadBlockTableEntries; /*0x34 */ 1324 U16 Reserved7; /*0x36 */ 1325 U32 1326 IRNvsramVersion; /*0x38 */ 1327 } MPI2_CONFIG_PAGE_IOC_6, 1328 *PTR_MPI2_CONFIG_PAGE_IOC_6, 1329 Mpi2IOCPage6_t, *pMpi2IOCPage6_t; 1330 1331 #define MPI2_IOCPAGE6_PAGEVERSION (0x05) 1332 1333 /*defines for IOC Page 6 CapabilitiesFlags */ 1334 #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT (0x00000020) 1335 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010) 1336 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008) 1337 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004) 1338 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002) 1339 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 1340 1341 1342 /*IOC Page 7 */ 1343 1344 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4) 1345 1346 typedef struct _MPI2_CONFIG_PAGE_IOC_7 { 1347 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1348 U32 Reserved1; /*0x04 */ 1349 U32 1350 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/*0x08 */ 1351 U16 SASBroadcastPrimitiveMasks; /*0x18 */ 1352 U16 SASNotifyPrimitiveMasks; /*0x1A */ 1353 U32 Reserved3; /*0x1C */ 1354 } MPI2_CONFIG_PAGE_IOC_7, 1355 *PTR_MPI2_CONFIG_PAGE_IOC_7, 1356 Mpi2IOCPage7_t, *pMpi2IOCPage7_t; 1357 1358 #define MPI2_IOCPAGE7_PAGEVERSION (0x02) 1359 1360 1361 /*IOC Page 8 */ 1362 1363 typedef struct _MPI2_CONFIG_PAGE_IOC_8 { 1364 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1365 U8 NumDevsPerEnclosure; /*0x04 */ 1366 U8 Reserved1; /*0x05 */ 1367 U16 Reserved2; /*0x06 */ 1368 U16 MaxPersistentEntries; /*0x08 */ 1369 U16 MaxNumPhysicalMappedIDs; /*0x0A */ 1370 U16 Flags; /*0x0C */ 1371 U16 Reserved3; /*0x0E */ 1372 U16 IRVolumeMappingFlags; /*0x10 */ 1373 U16 Reserved4; /*0x12 */ 1374 U32 Reserved5; /*0x14 */ 1375 } MPI2_CONFIG_PAGE_IOC_8, 1376 *PTR_MPI2_CONFIG_PAGE_IOC_8, 1377 Mpi2IOCPage8_t, *pMpi2IOCPage8_t; 1378 1379 #define MPI2_IOCPAGE8_PAGEVERSION (0x00) 1380 1381 /*defines for IOC Page 8 Flags field */ 1382 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020) 1383 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010) 1384 1385 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E) 1386 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000) 1387 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002) 1388 1389 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001) 1390 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000) 1391 1392 /*defines for IOC Page 8 IRVolumeMappingFlags */ 1393 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003) 1394 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000) 1395 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001) 1396 1397 1398 /**************************************************************************** 1399 * BIOS Config Pages 1400 ****************************************************************************/ 1401 1402 /*BIOS Page 1 */ 1403 1404 typedef struct _MPI2_CONFIG_PAGE_BIOS_1 { 1405 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1406 U32 BiosOptions; /*0x04 */ 1407 U32 IOCSettings; /*0x08 */ 1408 U8 SSUTimeout; /*0x0C */ 1409 U8 Reserved1; /*0x0D */ 1410 U16 Reserved2; /*0x0E */ 1411 U32 DeviceSettings; /*0x10 */ 1412 U16 NumberOfDevices; /*0x14 */ 1413 U16 UEFIVersion; /*0x16 */ 1414 U16 IOTimeoutBlockDevicesNonRM; /*0x18 */ 1415 U16 IOTimeoutSequential; /*0x1A */ 1416 U16 IOTimeoutOther; /*0x1C */ 1417 U16 IOTimeoutBlockDevicesRM; /*0x1E */ 1418 } MPI2_CONFIG_PAGE_BIOS_1, 1419 *PTR_MPI2_CONFIG_PAGE_BIOS_1, 1420 Mpi2BiosPage1_t, *pMpi2BiosPage1_t; 1421 1422 #define MPI2_BIOSPAGE1_PAGEVERSION (0x07) 1423 1424 /*values for BIOS Page 1 BiosOptions field */ 1425 #define MPI2_BIOSPAGE1_OPTIONS_BOOT_LIST_ADD_ALT_BOOT_DEVICE (0x00008000) 1426 #define MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG (0x00004000) 1427 1428 #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800) 1429 #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800) 1430 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL (0x00000000) 1431 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE (0x00000800) 1432 #define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID (0x00001000) 1433 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PSENS (0x00001800) 1434 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ESPHY (0x00002000) 1435 1436 #define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS (0x00000400) 1437 1438 #define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD (0x00000300) 1439 #define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD (0x00000000) 1440 #define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD (0x00000100) 1441 #define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD (0x00000200) 1442 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD (0x00000300) 1443 1444 #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0) 1445 #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000) 1446 1447 #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006) 1448 #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000) 1449 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002) 1450 #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004) 1451 1452 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1453 1454 /*values for BIOS Page 1 IOCSettings field */ 1455 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1456 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1457 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1458 1459 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1460 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1461 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1462 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1463 1464 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1465 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1466 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1467 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1468 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1469 1470 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1471 1472 /*values for BIOS Page 1 DeviceSettings field */ 1473 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 1474 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1475 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1476 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1477 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1478 1479 /*defines for BIOS Page 1 UEFIVersion field */ 1480 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK (0xFF00) 1481 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT (8) 1482 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK (0x00FF) 1483 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT (0) 1484 1485 1486 1487 /*BIOS Page 2 */ 1488 1489 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER { 1490 U32 Reserved1; /*0x00 */ 1491 U32 Reserved2; /*0x04 */ 1492 U32 Reserved3; /*0x08 */ 1493 U32 Reserved4; /*0x0C */ 1494 U32 Reserved5; /*0x10 */ 1495 U32 Reserved6; /*0x14 */ 1496 } MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1497 *PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1498 Mpi2BootDeviceAdapterOrder_t, 1499 *pMpi2BootDeviceAdapterOrder_t; 1500 1501 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID { 1502 U64 SASAddress; /*0x00 */ 1503 U8 LUN[8]; /*0x08 */ 1504 U32 Reserved1; /*0x10 */ 1505 U32 Reserved2; /*0x14 */ 1506 } MPI2_BOOT_DEVICE_SAS_WWID, 1507 *PTR_MPI2_BOOT_DEVICE_SAS_WWID, 1508 Mpi2BootDeviceSasWwid_t, 1509 *pMpi2BootDeviceSasWwid_t; 1510 1511 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT { 1512 U64 EnclosureLogicalID; /*0x00 */ 1513 U32 Reserved1; /*0x08 */ 1514 U32 Reserved2; /*0x0C */ 1515 U16 SlotNumber; /*0x10 */ 1516 U16 Reserved3; /*0x12 */ 1517 U32 Reserved4; /*0x14 */ 1518 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1519 *PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1520 Mpi2BootDeviceEnclosureSlot_t, 1521 *pMpi2BootDeviceEnclosureSlot_t; 1522 1523 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME { 1524 U64 DeviceName; /*0x00 */ 1525 U8 LUN[8]; /*0x08 */ 1526 U32 Reserved1; /*0x10 */ 1527 U32 Reserved2; /*0x14 */ 1528 } MPI2_BOOT_DEVICE_DEVICE_NAME, 1529 *PTR_MPI2_BOOT_DEVICE_DEVICE_NAME, 1530 Mpi2BootDeviceDeviceName_t, 1531 *pMpi2BootDeviceDeviceName_t; 1532 1533 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE { 1534 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1535 MPI2_BOOT_DEVICE_SAS_WWID SasWwid; 1536 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1537 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName; 1538 } MPI2_BIOSPAGE2_BOOT_DEVICE, 1539 *PTR_MPI2_BIOSPAGE2_BOOT_DEVICE, 1540 Mpi2BiosPage2BootDevice_t, 1541 *pMpi2BiosPage2BootDevice_t; 1542 1543 typedef struct _MPI2_CONFIG_PAGE_BIOS_2 { 1544 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1545 U32 Reserved1; /*0x04 */ 1546 U32 Reserved2; /*0x08 */ 1547 U32 Reserved3; /*0x0C */ 1548 U32 Reserved4; /*0x10 */ 1549 U32 Reserved5; /*0x14 */ 1550 U32 Reserved6; /*0x18 */ 1551 U8 ReqBootDeviceForm; /*0x1C */ 1552 U8 Reserved7; /*0x1D */ 1553 U16 Reserved8; /*0x1E */ 1554 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /*0x20 */ 1555 U8 ReqAltBootDeviceForm; /*0x38 */ 1556 U8 Reserved9; /*0x39 */ 1557 U16 Reserved10; /*0x3A */ 1558 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /*0x3C */ 1559 U8 CurrentBootDeviceForm; /*0x58 */ 1560 U8 Reserved11; /*0x59 */ 1561 U16 Reserved12; /*0x5A */ 1562 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /*0x58 */ 1563 } MPI2_CONFIG_PAGE_BIOS_2, *PTR_MPI2_CONFIG_PAGE_BIOS_2, 1564 Mpi2BiosPage2_t, *pMpi2BiosPage2_t; 1565 1566 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04) 1567 1568 /*values for BIOS Page 2 BootDeviceForm fields */ 1569 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F) 1570 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00) 1571 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05) 1572 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1573 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07) 1574 1575 1576 /*BIOS Page 3 */ 1577 1578 #define MPI2_BIOSPAGE3_NUM_ADAPTER (4) 1579 1580 typedef struct _MPI2_ADAPTER_INFO { 1581 U8 PciBusNumber; /*0x00 */ 1582 U8 PciDeviceAndFunctionNumber; /*0x01 */ 1583 U16 AdapterFlags; /*0x02 */ 1584 } MPI2_ADAPTER_INFO, *PTR_MPI2_ADAPTER_INFO, 1585 Mpi2AdapterInfo_t, *pMpi2AdapterInfo_t; 1586 1587 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 1588 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 1589 1590 typedef struct _MPI2_ADAPTER_ORDER_AUX { 1591 U64 WWID; /* 0x00 */ 1592 U32 Reserved1; /* 0x08 */ 1593 U32 Reserved2; /* 0x0C */ 1594 } MPI2_ADAPTER_ORDER_AUX, *PTR_MPI2_ADAPTER_ORDER_AUX, 1595 Mpi2AdapterOrderAux_t, *pMpi2AdapterOrderAux_t; 1596 1597 1598 typedef struct _MPI2_CONFIG_PAGE_BIOS_3 { 1599 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1600 U32 GlobalFlags; /*0x04 */ 1601 U32 BiosVersion; /*0x08 */ 1602 MPI2_ADAPTER_INFO AdapterOrder[MPI2_BIOSPAGE3_NUM_ADAPTER]; 1603 U32 Reserved1; /*0x1C */ 1604 MPI2_ADAPTER_ORDER_AUX AdapterOrderAux[MPI2_BIOSPAGE3_NUM_ADAPTER]; 1605 } MPI2_CONFIG_PAGE_BIOS_3, 1606 *PTR_MPI2_CONFIG_PAGE_BIOS_3, 1607 Mpi2BiosPage3_t, *pMpi2BiosPage3_t; 1608 1609 #define MPI2_BIOSPAGE3_PAGEVERSION (0x01) 1610 1611 /*values for BIOS Page 3 GlobalFlags */ 1612 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) 1613 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004) 1614 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010) 1615 1616 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 1617 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 1618 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020) 1619 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 1620 1621 1622 /*BIOS Page 4 */ 1623 1624 /* 1625 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1626 *one and check the value returned for NumPhys at runtime. 1627 */ 1628 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES 1629 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1) 1630 #endif 1631 1632 typedef struct _MPI2_BIOS4_ENTRY { 1633 U64 ReassignmentWWID; /*0x00 */ 1634 U64 ReassignmentDeviceName; /*0x08 */ 1635 } MPI2_BIOS4_ENTRY, *PTR_MPI2_BIOS4_ENTRY, 1636 Mpi2MBios4Entry_t, *pMpi2Bios4Entry_t; 1637 1638 typedef struct _MPI2_CONFIG_PAGE_BIOS_4 { 1639 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1640 U8 NumPhys; /*0x04 */ 1641 U8 Reserved1; /*0x05 */ 1642 U16 Reserved2; /*0x06 */ 1643 MPI2_BIOS4_ENTRY 1644 Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /*0x08 */ 1645 } MPI2_CONFIG_PAGE_BIOS_4, *PTR_MPI2_CONFIG_PAGE_BIOS_4, 1646 Mpi2BiosPage4_t, *pMpi2BiosPage4_t; 1647 1648 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01) 1649 1650 1651 /**************************************************************************** 1652 * RAID Volume Config Pages 1653 ****************************************************************************/ 1654 1655 /*RAID Volume Page 0 */ 1656 1657 typedef struct _MPI2_RAIDVOL0_PHYS_DISK { 1658 U8 RAIDSetNum; /*0x00 */ 1659 U8 PhysDiskMap; /*0x01 */ 1660 U8 PhysDiskNum; /*0x02 */ 1661 U8 Reserved; /*0x03 */ 1662 } MPI2_RAIDVOL0_PHYS_DISK, *PTR_MPI2_RAIDVOL0_PHYS_DISK, 1663 Mpi2RaidVol0PhysDisk_t, *pMpi2RaidVol0PhysDisk_t; 1664 1665 /*defines for the PhysDiskMap field */ 1666 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1667 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1668 1669 typedef struct _MPI2_RAIDVOL0_SETTINGS { 1670 U16 Settings; /*0x00 */ 1671 U8 HotSparePool; /*0x01 */ 1672 U8 Reserved; /*0x02 */ 1673 } MPI2_RAIDVOL0_SETTINGS, *PTR_MPI2_RAIDVOL0_SETTINGS, 1674 Mpi2RaidVol0Settings_t, 1675 *pMpi2RaidVol0Settings_t; 1676 1677 /*RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1678 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01) 1679 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02) 1680 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04) 1681 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08) 1682 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10) 1683 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20) 1684 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40) 1685 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80) 1686 1687 /*RAID Volume Page 0 VolumeSettings defines */ 1688 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008) 1689 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004) 1690 1691 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003) 1692 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000) 1693 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001) 1694 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002) 1695 1696 /* 1697 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1698 *one and check the value returned for NumPhysDisks at runtime. 1699 */ 1700 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX 1701 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 1702 #endif 1703 1704 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 { 1705 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1706 U16 DevHandle; /*0x04 */ 1707 U8 VolumeState; /*0x06 */ 1708 U8 VolumeType; /*0x07 */ 1709 U32 VolumeStatusFlags; /*0x08 */ 1710 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /*0x0C */ 1711 U64 MaxLBA; /*0x10 */ 1712 U32 StripeSize; /*0x18 */ 1713 U16 BlockSize; /*0x1C */ 1714 U16 Reserved1; /*0x1E */ 1715 U8 SupportedPhysDisks;/*0x20 */ 1716 U8 ResyncRate; /*0x21 */ 1717 U16 DataScrubDuration; /*0x22 */ 1718 U8 NumPhysDisks; /*0x24 */ 1719 U8 Reserved2; /*0x25 */ 1720 U8 Reserved3; /*0x26 */ 1721 U8 InactiveStatus; /*0x27 */ 1722 MPI2_RAIDVOL0_PHYS_DISK 1723 PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /*0x28 */ 1724 } MPI2_CONFIG_PAGE_RAID_VOL_0, 1725 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_0, 1726 Mpi2RaidVolPage0_t, *pMpi2RaidVolPage0_t; 1727 1728 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A) 1729 1730 /*values for RAID VolumeState */ 1731 #define MPI2_RAID_VOL_STATE_MISSING (0x00) 1732 #define MPI2_RAID_VOL_STATE_FAILED (0x01) 1733 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02) 1734 #define MPI2_RAID_VOL_STATE_ONLINE (0x03) 1735 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04) 1736 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05) 1737 1738 /*values for RAID VolumeType */ 1739 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00) 1740 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01) 1741 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02) 1742 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05) 1743 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF) 1744 1745 /*values for RAID Volume Page 0 VolumeStatusFlags field */ 1746 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000) 1747 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000) 1748 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000) 1749 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000) 1750 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000) 1751 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000) 1752 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000) 1753 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000) 1754 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000) 1755 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000) 1756 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080) 1757 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040) 1758 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020) 1759 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000) 1760 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010) 1761 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008) 1762 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004) 1763 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002) 1764 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001) 1765 1766 /*values for RAID Volume Page 0 SupportedPhysDisks field */ 1767 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08) 1768 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04) 1769 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02) 1770 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01) 1771 1772 /*values for RAID Volume Page 0 InactiveStatus field */ 1773 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 1774 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 1775 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 1776 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 1777 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 1778 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 1779 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 1780 1781 1782 /*RAID Volume Page 1 */ 1783 1784 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 { 1785 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1786 U16 DevHandle; /*0x04 */ 1787 U16 Reserved0; /*0x06 */ 1788 U8 GUID[24]; /*0x08 */ 1789 U8 Name[16]; /*0x20 */ 1790 U64 WWID; /*0x30 */ 1791 U32 Reserved1; /*0x38 */ 1792 U32 Reserved2; /*0x3C */ 1793 } MPI2_CONFIG_PAGE_RAID_VOL_1, 1794 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_1, 1795 Mpi2RaidVolPage1_t, *pMpi2RaidVolPage1_t; 1796 1797 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03) 1798 1799 1800 /**************************************************************************** 1801 * RAID Physical Disk Config Pages 1802 ****************************************************************************/ 1803 1804 /*RAID Physical Disk Page 0 */ 1805 1806 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS { 1807 U16 Reserved1; /*0x00 */ 1808 U8 HotSparePool; /*0x02 */ 1809 U8 Reserved2; /*0x03 */ 1810 } MPI2_RAIDPHYSDISK0_SETTINGS, 1811 *PTR_MPI2_RAIDPHYSDISK0_SETTINGS, 1812 Mpi2RaidPhysDisk0Settings_t, 1813 *pMpi2RaidPhysDisk0Settings_t; 1814 1815 /*use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */ 1816 1817 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA { 1818 U8 VendorID[8]; /*0x00 */ 1819 U8 ProductID[16]; /*0x08 */ 1820 U8 ProductRevLevel[4]; /*0x18 */ 1821 U8 SerialNum[32]; /*0x1C */ 1822 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1823 *PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1824 Mpi2RaidPhysDisk0InquiryData_t, 1825 *pMpi2RaidPhysDisk0InquiryData_t; 1826 1827 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 { 1828 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1829 U16 DevHandle; /*0x04 */ 1830 U8 Reserved1; /*0x06 */ 1831 U8 PhysDiskNum; /*0x07 */ 1832 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /*0x08 */ 1833 U32 Reserved2; /*0x0C */ 1834 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /*0x10 */ 1835 U32 Reserved3; /*0x4C */ 1836 U8 PhysDiskState; /*0x50 */ 1837 U8 OfflineReason; /*0x51 */ 1838 U8 IncompatibleReason; /*0x52 */ 1839 U8 PhysDiskAttributes; /*0x53 */ 1840 U32 PhysDiskStatusFlags;/*0x54 */ 1841 U64 DeviceMaxLBA; /*0x58 */ 1842 U64 HostMaxLBA; /*0x60 */ 1843 U64 CoercedMaxLBA; /*0x68 */ 1844 U16 BlockSize; /*0x70 */ 1845 U16 Reserved5; /*0x72 */ 1846 U32 Reserved6; /*0x74 */ 1847 } MPI2_CONFIG_PAGE_RD_PDISK_0, 1848 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_0, 1849 Mpi2RaidPhysDiskPage0_t, 1850 *pMpi2RaidPhysDiskPage0_t; 1851 1852 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05) 1853 1854 /*PhysDiskState defines */ 1855 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00) 1856 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01) 1857 #define MPI2_RAID_PD_STATE_OFFLINE (0x02) 1858 #define MPI2_RAID_PD_STATE_ONLINE (0x03) 1859 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04) 1860 #define MPI2_RAID_PD_STATE_DEGRADED (0x05) 1861 #define MPI2_RAID_PD_STATE_REBUILDING (0x06) 1862 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07) 1863 1864 /*OfflineReason defines */ 1865 #define MPI2_PHYSDISK0_ONLINE (0x00) 1866 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01) 1867 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03) 1868 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04) 1869 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05) 1870 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06) 1871 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF) 1872 1873 /*IncompatibleReason defines */ 1874 #define MPI2_PHYSDISK0_COMPATIBLE (0x00) 1875 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01) 1876 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02) 1877 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03) 1878 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04) 1879 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05) 1880 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06) 1881 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF) 1882 1883 /*PhysDiskAttributes defines */ 1884 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C) 1885 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08) 1886 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04) 1887 1888 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03) 1889 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02) 1890 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01) 1891 1892 /*PhysDiskStatusFlags defines */ 1893 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040) 1894 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020) 1895 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010) 1896 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000) 1897 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008) 1898 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004) 1899 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002) 1900 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001) 1901 1902 1903 /*RAID Physical Disk Page 1 */ 1904 1905 /* 1906 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1907 *one and check the value returned for NumPhysDiskPaths at runtime. 1908 */ 1909 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX 1910 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1) 1911 #endif 1912 1913 typedef struct _MPI2_RAIDPHYSDISK1_PATH { 1914 U16 DevHandle; /*0x00 */ 1915 U16 Reserved1; /*0x02 */ 1916 U64 WWID; /*0x04 */ 1917 U64 OwnerWWID; /*0x0C */ 1918 U8 OwnerIdentifier; /*0x14 */ 1919 U8 Reserved2; /*0x15 */ 1920 U16 Flags; /*0x16 */ 1921 } MPI2_RAIDPHYSDISK1_PATH, *PTR_MPI2_RAIDPHYSDISK1_PATH, 1922 Mpi2RaidPhysDisk1Path_t, 1923 *pMpi2RaidPhysDisk1Path_t; 1924 1925 /*RAID Physical Disk Page 1 Physical Disk Path Flags field defines */ 1926 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004) 1927 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 1928 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 1929 1930 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 { 1931 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1932 U8 NumPhysDiskPaths; /*0x04 */ 1933 U8 PhysDiskNum; /*0x05 */ 1934 U16 Reserved1; /*0x06 */ 1935 U32 Reserved2; /*0x08 */ 1936 MPI2_RAIDPHYSDISK1_PATH 1937 PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/*0x0C */ 1938 } MPI2_CONFIG_PAGE_RD_PDISK_1, 1939 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_1, 1940 Mpi2RaidPhysDiskPage1_t, 1941 *pMpi2RaidPhysDiskPage1_t; 1942 1943 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02) 1944 1945 1946 /**************************************************************************** 1947 * values for fields used by several types of SAS Config Pages 1948 ****************************************************************************/ 1949 1950 /*values for NegotiatedLinkRates fields */ 1951 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0) 1952 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4) 1953 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 1954 /*link rates used for Negotiated Physical and Logical Link Rate */ 1955 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 1956 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 1957 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 1958 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 1959 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 1960 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 1961 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 1962 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08) 1963 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09) 1964 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A) 1965 #define MPI25_SAS_NEG_LINK_RATE_12_0 (0x0B) 1966 1967 1968 /*values for AttachedPhyInfo fields */ 1969 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 1970 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 1971 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 1972 1973 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F) 1974 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 1975 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 1976 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 1977 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 1978 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 1979 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 1980 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 1981 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 1982 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 1983 1984 1985 /*values for PhyInfo fields */ 1986 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000) 1987 1988 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 1989 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27) 1990 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000) 1991 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000) 1992 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000) 1993 1994 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000) 1995 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000) 1996 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000) 1997 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 1998 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000) 1999 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 2000 2001 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000) 2002 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 2003 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 2004 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 2005 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 2006 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 2007 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 2008 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 2009 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 2010 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 2011 2012 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000) 2013 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 2014 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 2015 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 2016 2017 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 2018 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 2019 2020 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 2021 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000) 2022 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 2023 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020) 2024 2025 2026 /*values for SAS ProgrammedLinkRate fields */ 2027 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0) 2028 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 2029 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80) 2030 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90) 2031 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0) 2032 #define MPI25_SAS_PRATE_MAX_RATE_12_0 (0xB0) 2033 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F) 2034 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 2035 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08) 2036 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09) 2037 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A) 2038 #define MPI25_SAS_PRATE_MIN_RATE_12_0 (0x0B) 2039 2040 2041 /*values for SAS HwLinkRate fields */ 2042 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0) 2043 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80) 2044 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90) 2045 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0) 2046 #define MPI25_SAS_HWRATE_MAX_RATE_12_0 (0xB0) 2047 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F) 2048 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08) 2049 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09) 2050 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A) 2051 #define MPI25_SAS_HWRATE_MIN_RATE_12_0 (0x0B) 2052 2053 2054 2055 /**************************************************************************** 2056 * SAS IO Unit Config Pages 2057 ****************************************************************************/ 2058 2059 /*SAS IO Unit Page 0 */ 2060 2061 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA { 2062 U8 Port; /*0x00 */ 2063 U8 PortFlags; /*0x01 */ 2064 U8 PhyFlags; /*0x02 */ 2065 U8 NegotiatedLinkRate; /*0x03 */ 2066 U32 ControllerPhyDeviceInfo;/*0x04 */ 2067 U16 AttachedDevHandle; /*0x08 */ 2068 U16 ControllerDevHandle; /*0x0A */ 2069 U32 DiscoveryStatus; /*0x0C */ 2070 U32 Reserved; /*0x10 */ 2071 } MPI2_SAS_IO_UNIT0_PHY_DATA, 2072 *PTR_MPI2_SAS_IO_UNIT0_PHY_DATA, 2073 Mpi2SasIOUnit0PhyData_t, 2074 *pMpi2SasIOUnit0PhyData_t; 2075 2076 /* 2077 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2078 *one and check the value returned for NumPhys at runtime. 2079 */ 2080 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX 2081 #define MPI2_SAS_IOUNIT0_PHY_MAX (1) 2082 #endif 2083 2084 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 { 2085 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2086 U32 Reserved1;/*0x08 */ 2087 U8 NumPhys; /*0x0C */ 2088 U8 Reserved2;/*0x0D */ 2089 U16 Reserved3;/*0x0E */ 2090 MPI2_SAS_IO_UNIT0_PHY_DATA 2091 PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /*0x10 */ 2092 } MPI2_CONFIG_PAGE_SASIOUNIT_0, 2093 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0, 2094 Mpi2SasIOUnitPage0_t, *pMpi2SasIOUnitPage0_t; 2095 2096 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05) 2097 2098 /*values for SAS IO Unit Page 0 PortFlags */ 2099 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08) 2100 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) 2101 2102 /*values for SAS IO Unit Page 0 PhyFlags */ 2103 #define MPI2_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2104 #define MPI2_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2105 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) 2106 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 2107 2108 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2109 2110 /*see mpi2_sas.h for values for 2111 *SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 2112 2113 /*values for SAS IO Unit Page 0 DiscoveryStatus */ 2114 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2115 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2116 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000) 2117 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2118 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2119 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2120 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2121 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 2122 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2123 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 2124 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400) 2125 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 2126 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 2127 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 2128 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 2129 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2130 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010) 2131 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 2132 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2133 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001) 2134 2135 2136 /*SAS IO Unit Page 1 */ 2137 2138 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA { 2139 U8 Port; /*0x00 */ 2140 U8 PortFlags; /*0x01 */ 2141 U8 PhyFlags; /*0x02 */ 2142 U8 MaxMinLinkRate; /*0x03 */ 2143 U32 ControllerPhyDeviceInfo; /*0x04 */ 2144 U16 MaxTargetPortConnectTime; /*0x08 */ 2145 U16 Reserved1; /*0x0A */ 2146 } MPI2_SAS_IO_UNIT1_PHY_DATA, 2147 *PTR_MPI2_SAS_IO_UNIT1_PHY_DATA, 2148 Mpi2SasIOUnit1PhyData_t, 2149 *pMpi2SasIOUnit1PhyData_t; 2150 2151 /* 2152 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2153 *one and check the value returned for NumPhys at runtime. 2154 */ 2155 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX 2156 #define MPI2_SAS_IOUNIT1_PHY_MAX (1) 2157 #endif 2158 2159 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 { 2160 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2161 U16 2162 ControlFlags; /*0x08 */ 2163 U16 2164 SASNarrowMaxQueueDepth; /*0x0A */ 2165 U16 2166 AdditionalControlFlags; /*0x0C */ 2167 U16 2168 SASWideMaxQueueDepth; /*0x0E */ 2169 U8 2170 NumPhys; /*0x10 */ 2171 U8 2172 SATAMaxQDepth; /*0x11 */ 2173 U8 2174 ReportDeviceMissingDelay; /*0x12 */ 2175 U8 2176 IODeviceMissingDelay; /*0x13 */ 2177 MPI2_SAS_IO_UNIT1_PHY_DATA 2178 PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /*0x14 */ 2179 } MPI2_CONFIG_PAGE_SASIOUNIT_1, 2180 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1, 2181 Mpi2SasIOUnitPage1_t, *pMpi2SasIOUnitPage1_t; 2182 2183 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09) 2184 2185 /*values for SAS IO Unit Page 1 ControlFlags */ 2186 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 2187 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 2188 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) 2189 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 2190 2191 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 2192 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 2193 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0) 2194 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1) 2195 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2) 2196 2197 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 2198 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 2199 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 2200 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 2201 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 2202 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 2203 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 2204 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) 2205 2206 /*values for SAS IO Unit Page 1 AdditionalControlFlags */ 2207 #define MPI2_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100) 2208 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 2209 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 2210 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 2211 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 2212 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 2213 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 2214 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 2215 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 2216 2217 /*defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 2218 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 2219 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 2220 2221 /*values for SAS IO Unit Page 1 PortFlags */ 2222 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2223 2224 /*values for SAS IO Unit Page 1 PhyFlags */ 2225 #define MPI2_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2226 #define MPI2_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2227 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) 2228 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 2229 2230 /*values for SAS IO Unit Page 1 MaxMinLinkRate */ 2231 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) 2232 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) 2233 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) 2234 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) 2235 #define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0) 2236 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) 2237 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) 2238 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) 2239 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) 2240 #define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B) 2241 2242 /*see mpi2_sas.h for values for 2243 *SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 2244 2245 2246 /*SAS IO Unit Page 4 (for MPI v2.5 and earlier) */ 2247 2248 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP { 2249 U8 MaxTargetSpinup; /*0x00 */ 2250 U8 SpinupDelay; /*0x01 */ 2251 U8 SpinupFlags; /*0x02 */ 2252 U8 Reserved1; /*0x03 */ 2253 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, 2254 *PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP, 2255 Mpi2SasIOUnit4SpinupGroup_t, 2256 *pMpi2SasIOUnit4SpinupGroup_t; 2257 /*defines for SAS IO Unit Page 4 SpinupFlags */ 2258 #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01) 2259 2260 2261 /* 2262 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2263 *one and check the value returned for NumPhys at runtime. 2264 */ 2265 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX 2266 #define MPI2_SAS_IOUNIT4_PHY_MAX (4) 2267 #endif 2268 2269 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 { 2270 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header;/*0x00 */ 2271 MPI2_SAS_IOUNIT4_SPINUP_GROUP 2272 SpinupGroupParameters[4]; /*0x08 */ 2273 U32 2274 Reserved1; /*0x18 */ 2275 U32 2276 Reserved2; /*0x1C */ 2277 U32 2278 Reserved3; /*0x20 */ 2279 U8 2280 BootDeviceWaitTime; /*0x24 */ 2281 U8 2282 SATADeviceWaitTime; /*0x25 */ 2283 U16 2284 Reserved5; /*0x26 */ 2285 U8 2286 NumPhys; /*0x28 */ 2287 U8 2288 PEInitialSpinupDelay; /*0x29 */ 2289 U8 2290 PEReplyDelay; /*0x2A */ 2291 U8 2292 Flags; /*0x2B */ 2293 U8 2294 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /*0x2C */ 2295 } MPI2_CONFIG_PAGE_SASIOUNIT_4, 2296 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4, 2297 Mpi2SasIOUnitPage4_t, *pMpi2SasIOUnitPage4_t; 2298 2299 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02) 2300 2301 /*defines for Flags field */ 2302 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01) 2303 2304 /*defines for PHY field */ 2305 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03) 2306 2307 2308 /*SAS IO Unit Page 5 */ 2309 2310 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS { 2311 U8 ControlFlags; /*0x00 */ 2312 U8 PortWidthModGroup; /*0x01 */ 2313 U16 InactivityTimerExponent; /*0x02 */ 2314 U8 SATAPartialTimeout; /*0x04 */ 2315 U8 Reserved2; /*0x05 */ 2316 U8 SATASlumberTimeout; /*0x06 */ 2317 U8 Reserved3; /*0x07 */ 2318 U8 SASPartialTimeout; /*0x08 */ 2319 U8 Reserved4; /*0x09 */ 2320 U8 SASSlumberTimeout; /*0x0A */ 2321 U8 Reserved5; /*0x0B */ 2322 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2323 *PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2324 Mpi2SasIOUnit5PhyPmSettings_t, 2325 *pMpi2SasIOUnit5PhyPmSettings_t; 2326 2327 /*defines for ControlFlags field */ 2328 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08) 2329 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04) 2330 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02) 2331 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01) 2332 2333 /*defines for PortWidthModeGroup field */ 2334 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF) 2335 2336 /*defines for InactivityTimerExponent field */ 2337 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000) 2338 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12) 2339 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700) 2340 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8) 2341 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070) 2342 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4) 2343 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007) 2344 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0) 2345 2346 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7) 2347 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6) 2348 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5) 2349 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4) 2350 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3) 2351 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2) 2352 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1) 2353 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0) 2354 2355 /* 2356 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2357 *one and check the value returned for NumPhys at runtime. 2358 */ 2359 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX 2360 #define MPI2_SAS_IOUNIT5_PHY_MAX (1) 2361 #endif 2362 2363 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 { 2364 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2365 U8 NumPhys; /*0x08 */ 2366 U8 Reserved1;/*0x09 */ 2367 U16 Reserved2;/*0x0A */ 2368 U32 Reserved3;/*0x0C */ 2369 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS 2370 SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX];/*0x10 */ 2371 } MPI2_CONFIG_PAGE_SASIOUNIT_5, 2372 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5, 2373 Mpi2SasIOUnitPage5_t, *pMpi2SasIOUnitPage5_t; 2374 2375 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01) 2376 2377 2378 /*SAS IO Unit Page 6 */ 2379 2380 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS { 2381 U8 CurrentStatus; /*0x00 */ 2382 U8 CurrentModulation; /*0x01 */ 2383 U8 CurrentUtilization; /*0x02 */ 2384 U8 Reserved1; /*0x03 */ 2385 U32 Reserved2; /*0x04 */ 2386 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2387 *PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2388 Mpi2SasIOUnit6PortWidthModGroupStatus_t, 2389 *pMpi2SasIOUnit6PortWidthModGroupStatus_t; 2390 2391 /*defines for CurrentStatus field */ 2392 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00) 2393 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01) 2394 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02) 2395 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03) 2396 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04) 2397 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05) 2398 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06) 2399 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07) 2400 2401 /*defines for CurrentModulation field */ 2402 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00) 2403 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01) 2404 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02) 2405 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03) 2406 2407 /* 2408 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2409 *one and check the value returned for NumGroups at runtime. 2410 */ 2411 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX 2412 #define MPI2_SAS_IOUNIT6_GROUP_MAX (1) 2413 #endif 2414 2415 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 { 2416 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2417 U32 Reserved1; /*0x08 */ 2418 U32 Reserved2; /*0x0C */ 2419 U8 NumGroups; /*0x10 */ 2420 U8 Reserved3; /*0x11 */ 2421 U16 Reserved4; /*0x12 */ 2422 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 2423 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /*0x14 */ 2424 } MPI2_CONFIG_PAGE_SASIOUNIT_6, 2425 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6, 2426 Mpi2SasIOUnitPage6_t, *pMpi2SasIOUnitPage6_t; 2427 2428 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00) 2429 2430 2431 /*SAS IO Unit Page 7 */ 2432 2433 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS { 2434 U8 Flags; /*0x00 */ 2435 U8 Reserved1; /*0x01 */ 2436 U16 Reserved2; /*0x02 */ 2437 U8 Threshold75Pct; /*0x04 */ 2438 U8 Threshold50Pct; /*0x05 */ 2439 U8 Threshold25Pct; /*0x06 */ 2440 U8 Reserved3; /*0x07 */ 2441 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2442 *PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2443 Mpi2SasIOUnit7PortWidthModGroupSettings_t, 2444 *pMpi2SasIOUnit7PortWidthModGroupSettings_t; 2445 2446 /*defines for Flags field */ 2447 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01) 2448 2449 2450 /* 2451 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2452 *one and check the value returned for NumGroups at runtime. 2453 */ 2454 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX 2455 #define MPI2_SAS_IOUNIT7_GROUP_MAX (1) 2456 #endif 2457 2458 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 { 2459 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2460 U8 SamplingInterval; /*0x08 */ 2461 U8 WindowLength; /*0x09 */ 2462 U16 Reserved1; /*0x0A */ 2463 U32 Reserved2; /*0x0C */ 2464 U32 Reserved3; /*0x10 */ 2465 U8 NumGroups; /*0x14 */ 2466 U8 Reserved4; /*0x15 */ 2467 U16 Reserved5; /*0x16 */ 2468 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2469 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX];/*0x18 */ 2470 } MPI2_CONFIG_PAGE_SASIOUNIT_7, 2471 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7, 2472 Mpi2SasIOUnitPage7_t, *pMpi2SasIOUnitPage7_t; 2473 2474 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00) 2475 2476 2477 /*SAS IO Unit Page 8 */ 2478 2479 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 { 2480 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2481 Header; /*0x00 */ 2482 U32 2483 Reserved1; /*0x08 */ 2484 U32 2485 PowerManagementCapabilities; /*0x0C */ 2486 U8 2487 TxRxSleepStatus; /*0x10 */ 2488 U8 2489 Reserved2; /*0x11 */ 2490 U16 2491 Reserved3; /*0x12 */ 2492 } MPI2_CONFIG_PAGE_SASIOUNIT_8, 2493 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8, 2494 Mpi2SasIOUnitPage8_t, *pMpi2SasIOUnitPage8_t; 2495 2496 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00) 2497 2498 /*defines for PowerManagementCapabilities field */ 2499 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000) 2500 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800) 2501 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400) 2502 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200) 2503 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100) 2504 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010) 2505 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008) 2506 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004) 2507 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002) 2508 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001) 2509 2510 /*defines for TxRxSleepStatus field */ 2511 #define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED (0x00) 2512 #define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED (0x01) 2513 #define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE (0x02) 2514 #define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN (0x03) 2515 2516 2517 2518 /*SAS IO Unit Page 16 */ 2519 2520 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 { 2521 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2522 Header; /*0x00 */ 2523 U64 2524 TimeStamp; /*0x08 */ 2525 U32 2526 Reserved1; /*0x10 */ 2527 U32 2528 Reserved2; /*0x14 */ 2529 U32 2530 FastPathPendedRequests; /*0x18 */ 2531 U32 2532 FastPathUnPendedRequests; /*0x1C */ 2533 U32 2534 FastPathHostRequestStarts; /*0x20 */ 2535 U32 2536 FastPathFirmwareRequestStarts; /*0x24 */ 2537 U32 2538 FastPathHostCompletions; /*0x28 */ 2539 U32 2540 FastPathFirmwareCompletions; /*0x2C */ 2541 U32 2542 NonFastPathRequestStarts; /*0x30 */ 2543 U32 2544 NonFastPathHostCompletions; /*0x30 */ 2545 } MPI2_CONFIG_PAGE_SASIOUNIT16, 2546 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT16, 2547 Mpi2SasIOUnitPage16_t, *pMpi2SasIOUnitPage16_t; 2548 2549 #define MPI2_SASIOUNITPAGE16_PAGEVERSION (0x00) 2550 2551 2552 /**************************************************************************** 2553 * SAS Expander Config Pages 2554 ****************************************************************************/ 2555 2556 /*SAS Expander Page 0 */ 2557 2558 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 { 2559 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2560 Header; /*0x00 */ 2561 U8 2562 PhysicalPort; /*0x08 */ 2563 U8 2564 ReportGenLength; /*0x09 */ 2565 U16 2566 EnclosureHandle; /*0x0A */ 2567 U64 2568 SASAddress; /*0x0C */ 2569 U32 2570 DiscoveryStatus; /*0x14 */ 2571 U16 2572 DevHandle; /*0x18 */ 2573 U16 2574 ParentDevHandle; /*0x1A */ 2575 U16 2576 ExpanderChangeCount; /*0x1C */ 2577 U16 2578 ExpanderRouteIndexes; /*0x1E */ 2579 U8 2580 NumPhys; /*0x20 */ 2581 U8 2582 SASLevel; /*0x21 */ 2583 U16 2584 Flags; /*0x22 */ 2585 U16 2586 STPBusInactivityTimeLimit; /*0x24 */ 2587 U16 2588 STPMaxConnectTimeLimit; /*0x26 */ 2589 U16 2590 STP_SMP_NexusLossTime; /*0x28 */ 2591 U16 2592 MaxNumRoutedSasAddresses; /*0x2A */ 2593 U64 2594 ActiveZoneManagerSASAddress;/*0x2C */ 2595 U16 2596 ZoneLockInactivityLimit; /*0x34 */ 2597 U16 2598 Reserved1; /*0x36 */ 2599 U8 2600 TimeToReducedFunc; /*0x38 */ 2601 U8 2602 InitialTimeToReducedFunc; /*0x39 */ 2603 U8 2604 MaxReducedFuncTime; /*0x3A */ 2605 U8 2606 Reserved2; /*0x3B */ 2607 } MPI2_CONFIG_PAGE_EXPANDER_0, 2608 *PTR_MPI2_CONFIG_PAGE_EXPANDER_0, 2609 Mpi2ExpanderPage0_t, *pMpi2ExpanderPage0_t; 2610 2611 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06) 2612 2613 /*values for SAS Expander Page 0 DiscoveryStatus field */ 2614 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2615 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2616 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000) 2617 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2618 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2619 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2620 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2621 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000) 2622 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2623 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2624 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2625 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2626 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2627 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2628 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2629 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2630 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2631 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2632 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2633 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2634 2635 /*values for SAS Expander Page 0 Flags field */ 2636 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 2637 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 2638 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 2639 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 2640 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 2641 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 2642 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 2643 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 2644 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 2645 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 2646 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 2647 2648 2649 /*SAS Expander Page 1 */ 2650 2651 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 { 2652 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2653 Header; /*0x00 */ 2654 U8 2655 PhysicalPort; /*0x08 */ 2656 U8 2657 Reserved1; /*0x09 */ 2658 U16 2659 Reserved2; /*0x0A */ 2660 U8 2661 NumPhys; /*0x0C */ 2662 U8 2663 Phy; /*0x0D */ 2664 U16 2665 NumTableEntriesProgrammed; /*0x0E */ 2666 U8 2667 ProgrammedLinkRate; /*0x10 */ 2668 U8 2669 HwLinkRate; /*0x11 */ 2670 U16 2671 AttachedDevHandle; /*0x12 */ 2672 U32 2673 PhyInfo; /*0x14 */ 2674 U32 2675 AttachedDeviceInfo; /*0x18 */ 2676 U16 2677 ExpanderDevHandle; /*0x1C */ 2678 U8 2679 ChangeCount; /*0x1E */ 2680 U8 2681 NegotiatedLinkRate; /*0x1F */ 2682 U8 2683 PhyIdentifier; /*0x20 */ 2684 U8 2685 AttachedPhyIdentifier; /*0x21 */ 2686 U8 2687 Reserved3; /*0x22 */ 2688 U8 2689 DiscoveryInfo; /*0x23 */ 2690 U32 2691 AttachedPhyInfo; /*0x24 */ 2692 U8 2693 ZoneGroup; /*0x28 */ 2694 U8 2695 SelfConfigStatus; /*0x29 */ 2696 U16 2697 Reserved4; /*0x2A */ 2698 } MPI2_CONFIG_PAGE_EXPANDER_1, 2699 *PTR_MPI2_CONFIG_PAGE_EXPANDER_1, 2700 Mpi2ExpanderPage1_t, *pMpi2ExpanderPage1_t; 2701 2702 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02) 2703 2704 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2705 2706 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2707 2708 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2709 2710 /*see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines 2711 *used for the AttachedDeviceInfo field */ 2712 2713 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2714 2715 /*values for SAS Expander Page 1 DiscoveryInfo field */ 2716 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2717 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2718 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2719 2720 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2721 2722 2723 /**************************************************************************** 2724 * SAS Device Config Pages 2725 ****************************************************************************/ 2726 2727 /*SAS Device Page 0 */ 2728 2729 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 { 2730 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2731 Header; /*0x00 */ 2732 U16 2733 Slot; /*0x08 */ 2734 U16 2735 EnclosureHandle; /*0x0A */ 2736 U64 2737 SASAddress; /*0x0C */ 2738 U16 2739 ParentDevHandle; /*0x14 */ 2740 U8 2741 PhyNum; /*0x16 */ 2742 U8 2743 AccessStatus; /*0x17 */ 2744 U16 2745 DevHandle; /*0x18 */ 2746 U8 2747 AttachedPhyIdentifier; /*0x1A */ 2748 U8 2749 ZoneGroup; /*0x1B */ 2750 U32 2751 DeviceInfo; /*0x1C */ 2752 U16 2753 Flags; /*0x20 */ 2754 U8 2755 PhysicalPort; /*0x22 */ 2756 U8 2757 MaxPortConnections; /*0x23 */ 2758 U64 2759 DeviceName; /*0x24 */ 2760 U8 2761 PortGroups; /*0x2C */ 2762 U8 2763 DmaGroup; /*0x2D */ 2764 U8 2765 ControlGroup; /*0x2E */ 2766 U8 2767 EnclosureLevel; /*0x2F */ 2768 U32 2769 ConnectorName[4]; /*0x30 */ 2770 U32 2771 Reserved3; /*0x34 */ 2772 } MPI2_CONFIG_PAGE_SAS_DEV_0, 2773 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_0, 2774 Mpi2SasDevicePage0_t, 2775 *pMpi2SasDevicePage0_t; 2776 2777 #define MPI2_SASDEVICE0_PAGEVERSION (0x09) 2778 2779 /*values for SAS Device Page 0 AccessStatus field */ 2780 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2781 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2782 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2783 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2784 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2785 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05) 2786 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06) 2787 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07) 2788 /*specific values for SATA Init failures */ 2789 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2790 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2791 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2792 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2793 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2794 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2795 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2796 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2797 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2798 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2799 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2800 2801 /*see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2802 2803 /*values for SAS Device Page 0 Flags field */ 2804 #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000) 2805 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH (0x4000) 2806 #define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE (0x2000) 2807 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000) 2808 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800) 2809 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2810 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2811 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2812 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2813 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2814 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2815 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2816 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2817 #define MPI2_SAS_DEVICE0_FLAGS_PERSIST_CAPABLE (0x0004) 2818 #define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID (0x0002) 2819 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2820 2821 2822 /*SAS Device Page 1 */ 2823 2824 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 { 2825 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2826 Header; /*0x00 */ 2827 U32 2828 Reserved1; /*0x08 */ 2829 U64 2830 SASAddress; /*0x0C */ 2831 U32 2832 Reserved2; /*0x14 */ 2833 U16 2834 DevHandle; /*0x18 */ 2835 U16 2836 Reserved3; /*0x1A */ 2837 U8 2838 InitialRegDeviceFIS[20];/*0x1C */ 2839 } MPI2_CONFIG_PAGE_SAS_DEV_1, 2840 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_1, 2841 Mpi2SasDevicePage1_t, 2842 *pMpi2SasDevicePage1_t; 2843 2844 #define MPI2_SASDEVICE1_PAGEVERSION (0x01) 2845 2846 2847 /**************************************************************************** 2848 * SAS PHY Config Pages 2849 ****************************************************************************/ 2850 2851 /*SAS PHY Page 0 */ 2852 2853 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 { 2854 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2855 Header; /*0x00 */ 2856 U16 2857 OwnerDevHandle; /*0x08 */ 2858 U16 2859 Reserved1; /*0x0A */ 2860 U16 2861 AttachedDevHandle; /*0x0C */ 2862 U8 2863 AttachedPhyIdentifier; /*0x0E */ 2864 U8 2865 Reserved2; /*0x0F */ 2866 U32 2867 AttachedPhyInfo; /*0x10 */ 2868 U8 2869 ProgrammedLinkRate; /*0x14 */ 2870 U8 2871 HwLinkRate; /*0x15 */ 2872 U8 2873 ChangeCount; /*0x16 */ 2874 U8 2875 Flags; /*0x17 */ 2876 U32 2877 PhyInfo; /*0x18 */ 2878 U8 2879 NegotiatedLinkRate; /*0x1C */ 2880 U8 2881 Reserved3; /*0x1D */ 2882 U16 2883 Reserved4; /*0x1E */ 2884 } MPI2_CONFIG_PAGE_SAS_PHY_0, 2885 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_0, 2886 Mpi2SasPhyPage0_t, *pMpi2SasPhyPage0_t; 2887 2888 #define MPI2_SASPHY0_PAGEVERSION (0x03) 2889 2890 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2891 2892 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2893 2894 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2895 2896 /*values for SAS PHY Page 0 Flags field */ 2897 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 2898 2899 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2900 2901 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2902 2903 2904 /*SAS PHY Page 1 */ 2905 2906 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 { 2907 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2908 Header; /*0x00 */ 2909 U32 2910 Reserved1; /*0x08 */ 2911 U32 2912 InvalidDwordCount; /*0x0C */ 2913 U32 2914 RunningDisparityErrorCount; /*0x10 */ 2915 U32 2916 LossDwordSynchCount; /*0x14 */ 2917 U32 2918 PhyResetProblemCount; /*0x18 */ 2919 } MPI2_CONFIG_PAGE_SAS_PHY_1, 2920 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_1, 2921 Mpi2SasPhyPage1_t, *pMpi2SasPhyPage1_t; 2922 2923 #define MPI2_SASPHY1_PAGEVERSION (0x01) 2924 2925 2926 /*SAS PHY Page 2 */ 2927 2928 typedef struct _MPI2_SASPHY2_PHY_EVENT { 2929 U8 PhyEventCode; /*0x00 */ 2930 U8 Reserved1; /*0x01 */ 2931 U16 Reserved2; /*0x02 */ 2932 U32 PhyEventInfo; /*0x04 */ 2933 } MPI2_SASPHY2_PHY_EVENT, *PTR_MPI2_SASPHY2_PHY_EVENT, 2934 Mpi2SasPhy2PhyEvent_t, *pMpi2SasPhy2PhyEvent_t; 2935 2936 /*use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */ 2937 2938 2939 /* 2940 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2941 *one and check the value returned for NumPhyEvents at runtime. 2942 */ 2943 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX 2944 #define MPI2_SASPHY2_PHY_EVENT_MAX (1) 2945 #endif 2946 2947 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 { 2948 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2949 Header; /*0x00 */ 2950 U32 2951 Reserved1; /*0x08 */ 2952 U8 2953 NumPhyEvents; /*0x0C */ 2954 U8 2955 Reserved2; /*0x0D */ 2956 U16 2957 Reserved3; /*0x0E */ 2958 MPI2_SASPHY2_PHY_EVENT 2959 PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /*0x10 */ 2960 } MPI2_CONFIG_PAGE_SAS_PHY_2, 2961 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_2, 2962 Mpi2SasPhyPage2_t, 2963 *pMpi2SasPhyPage2_t; 2964 2965 #define MPI2_SASPHY2_PAGEVERSION (0x00) 2966 2967 2968 /*SAS PHY Page 3 */ 2969 2970 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG { 2971 U8 PhyEventCode; /*0x00 */ 2972 U8 Reserved1; /*0x01 */ 2973 U16 Reserved2; /*0x02 */ 2974 U8 CounterType; /*0x04 */ 2975 U8 ThresholdWindow; /*0x05 */ 2976 U8 TimeUnits; /*0x06 */ 2977 U8 Reserved3; /*0x07 */ 2978 U32 EventThreshold; /*0x08 */ 2979 U16 ThresholdFlags; /*0x0C */ 2980 U16 Reserved4; /*0x0E */ 2981 } MPI2_SASPHY3_PHY_EVENT_CONFIG, 2982 *PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG, 2983 Mpi2SasPhy3PhyEventConfig_t, 2984 *pMpi2SasPhy3PhyEventConfig_t; 2985 2986 /*values for PhyEventCode field */ 2987 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 2988 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 2989 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 2990 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 2991 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 2992 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 2993 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 2994 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 2995 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 2996 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 2997 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 2998 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 2999 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 3000 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 3001 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 3002 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 3003 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 3004 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A) 3005 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B) 3006 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C) 3007 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D) 3008 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E) 3009 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 3010 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 3011 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 3012 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 3013 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 3014 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 3015 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 3016 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 3017 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 3018 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 3019 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 3020 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 3021 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) 3022 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) 3023 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2) 3024 3025 /*Following codes are product specific and in MPI v2.6 and later */ 3026 #define MPI2_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xD3) 3027 #define MPI2_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xD4) 3028 #define MPI2_SASPHY3_EVENT_CODE_LCCONN_TIME (0xD5) 3029 #define MPI2_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xD6) 3030 #define MPI2_SASPHY3_EVENT_CODE_SATA_TX_START (0xD7) 3031 #define MPI2_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xD8) 3032 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xD9) 3033 #define MPI2_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xDA) 3034 #define MPI2_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xDB) 3035 #define MPI2_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xDC) 3036 3037 3038 /*values for the CounterType field */ 3039 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 3040 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 3041 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 3042 3043 /*values for the TimeUnits field */ 3044 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 3045 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 3046 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 3047 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 3048 3049 /*values for the ThresholdFlags field */ 3050 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002) 3051 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 3052 3053 /* 3054 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3055 *one and check the value returned for NumPhyEvents at runtime. 3056 */ 3057 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX 3058 #define MPI2_SASPHY3_PHY_EVENT_MAX (1) 3059 #endif 3060 3061 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 { 3062 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3063 Header; /*0x00 */ 3064 U32 3065 Reserved1; /*0x08 */ 3066 U8 3067 NumPhyEvents; /*0x0C */ 3068 U8 3069 Reserved2; /*0x0D */ 3070 U16 3071 Reserved3; /*0x0E */ 3072 MPI2_SASPHY3_PHY_EVENT_CONFIG 3073 PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /*0x10 */ 3074 } MPI2_CONFIG_PAGE_SAS_PHY_3, 3075 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_3, 3076 Mpi2SasPhyPage3_t, *pMpi2SasPhyPage3_t; 3077 3078 #define MPI2_SASPHY3_PAGEVERSION (0x00) 3079 3080 3081 /*SAS PHY Page 4 */ 3082 3083 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 { 3084 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3085 Header; /*0x00 */ 3086 U16 3087 Reserved1; /*0x08 */ 3088 U8 3089 Reserved2; /*0x0A */ 3090 U8 3091 Flags; /*0x0B */ 3092 U8 3093 InitialFrame[28]; /*0x0C */ 3094 } MPI2_CONFIG_PAGE_SAS_PHY_4, 3095 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_4, 3096 Mpi2SasPhyPage4_t, *pMpi2SasPhyPage4_t; 3097 3098 #define MPI2_SASPHY4_PAGEVERSION (0x00) 3099 3100 /*values for the Flags field */ 3101 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02) 3102 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01) 3103 3104 3105 3106 3107 /**************************************************************************** 3108 * SAS Port Config Pages 3109 ****************************************************************************/ 3110 3111 /*SAS Port Page 0 */ 3112 3113 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 { 3114 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3115 Header; /*0x00 */ 3116 U8 3117 PortNumber; /*0x08 */ 3118 U8 3119 PhysicalPort; /*0x09 */ 3120 U8 3121 PortWidth; /*0x0A */ 3122 U8 3123 PhysicalPortWidth; /*0x0B */ 3124 U8 3125 ZoneGroup; /*0x0C */ 3126 U8 3127 Reserved1; /*0x0D */ 3128 U16 3129 Reserved2; /*0x0E */ 3130 U64 3131 SASAddress; /*0x10 */ 3132 U32 3133 DeviceInfo; /*0x18 */ 3134 U32 3135 Reserved3; /*0x1C */ 3136 U32 3137 Reserved4; /*0x20 */ 3138 } MPI2_CONFIG_PAGE_SAS_PORT_0, 3139 *PTR_MPI2_CONFIG_PAGE_SAS_PORT_0, 3140 Mpi2SasPortPage0_t, *pMpi2SasPortPage0_t; 3141 3142 #define MPI2_SASPORT0_PAGEVERSION (0x00) 3143 3144 /*see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */ 3145 3146 3147 /**************************************************************************** 3148 * SAS Enclosure Config Pages 3149 ****************************************************************************/ 3150 3151 /*SAS Enclosure Page 0 */ 3152 3153 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 { 3154 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3155 Header; /*0x00 */ 3156 U32 3157 Reserved1; /*0x08 */ 3158 U64 3159 EnclosureLogicalID; /*0x0C */ 3160 U16 3161 Flags; /*0x14 */ 3162 U16 3163 EnclosureHandle; /*0x16 */ 3164 U16 3165 NumSlots; /*0x18 */ 3166 U16 3167 StartSlot; /*0x1A */ 3168 U8 3169 Reserved2; /*0x1C */ 3170 U8 3171 EnclosureLevel; /*0x1D */ 3172 U16 3173 SEPDevHandle; /*0x1E */ 3174 U32 3175 Reserved3; /*0x20 */ 3176 U32 3177 Reserved4; /*0x24 */ 3178 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3179 *PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3180 Mpi2SasEnclosurePage0_t, *pMpi2SasEnclosurePage0_t; 3181 3182 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x04) 3183 3184 /*values for SAS Enclosure Page 0 Flags field */ 3185 #define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010) 3186 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 3187 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3188 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3189 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3190 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3191 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3192 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3193 3194 3195 /**************************************************************************** 3196 * Log Config Page 3197 ****************************************************************************/ 3198 3199 /*Log Page 0 */ 3200 3201 /* 3202 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3203 *one and check the value returned for NumLogEntries at runtime. 3204 */ 3205 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES 3206 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1) 3207 #endif 3208 3209 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C) 3210 3211 typedef struct _MPI2_LOG_0_ENTRY { 3212 U64 TimeStamp; /*0x00 */ 3213 U32 Reserved1; /*0x08 */ 3214 U16 LogSequence; /*0x0C */ 3215 U16 LogEntryQualifier; /*0x0E */ 3216 U8 VP_ID; /*0x10 */ 3217 U8 VF_ID; /*0x11 */ 3218 U16 Reserved2; /*0x12 */ 3219 U8 3220 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/*0x14 */ 3221 } MPI2_LOG_0_ENTRY, *PTR_MPI2_LOG_0_ENTRY, 3222 Mpi2Log0Entry_t, *pMpi2Log0Entry_t; 3223 3224 /*values for Log Page 0 LogEntry LogEntryQualifier field */ 3225 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 3226 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 3227 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002) 3228 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000) 3229 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF) 3230 3231 typedef struct _MPI2_CONFIG_PAGE_LOG_0 { 3232 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3233 U32 Reserved1; /*0x08 */ 3234 U32 Reserved2; /*0x0C */ 3235 U16 NumLogEntries;/*0x10 */ 3236 U16 Reserved3; /*0x12 */ 3237 MPI2_LOG_0_ENTRY 3238 LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /*0x14 */ 3239 } MPI2_CONFIG_PAGE_LOG_0, *PTR_MPI2_CONFIG_PAGE_LOG_0, 3240 Mpi2LogPage0_t, *pMpi2LogPage0_t; 3241 3242 #define MPI2_LOG_0_PAGEVERSION (0x02) 3243 3244 3245 /**************************************************************************** 3246 * RAID Config Page 3247 ****************************************************************************/ 3248 3249 /*RAID Page 0 */ 3250 3251 /* 3252 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3253 *one and check the value returned for NumElements at runtime. 3254 */ 3255 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS 3256 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1) 3257 #endif 3258 3259 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT { 3260 U16 ElementFlags; /*0x00 */ 3261 U16 VolDevHandle; /*0x02 */ 3262 U8 HotSparePool; /*0x04 */ 3263 U8 PhysDiskNum; /*0x05 */ 3264 U16 PhysDiskDevHandle; /*0x06 */ 3265 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3266 *PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3267 Mpi2RaidConfig0ConfigElement_t, 3268 *pMpi2RaidConfig0ConfigElement_t; 3269 3270 /*values for the ElementFlags field */ 3271 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F) 3272 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000) 3273 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001) 3274 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002) 3275 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003) 3276 3277 3278 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 { 3279 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3280 U8 NumHotSpares; /*0x08 */ 3281 U8 NumPhysDisks; /*0x09 */ 3282 U8 NumVolumes; /*0x0A */ 3283 U8 ConfigNum; /*0x0B */ 3284 U32 Flags; /*0x0C */ 3285 U8 ConfigGUID[24]; /*0x10 */ 3286 U32 Reserved1; /*0x28 */ 3287 U8 NumElements; /*0x2C */ 3288 U8 Reserved2; /*0x2D */ 3289 U16 Reserved3; /*0x2E */ 3290 MPI2_RAIDCONFIG0_CONFIG_ELEMENT 3291 ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /*0x30 */ 3292 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3293 *PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3294 Mpi2RaidConfigurationPage0_t, 3295 *pMpi2RaidConfigurationPage0_t; 3296 3297 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00) 3298 3299 /*values for RAID Configuration Page 0 Flags field */ 3300 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001) 3301 3302 3303 /**************************************************************************** 3304 * Driver Persistent Mapping Config Pages 3305 ****************************************************************************/ 3306 3307 /*Driver Persistent Mapping Page 0 */ 3308 3309 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY { 3310 U64 PhysicalIdentifier; /*0x00 */ 3311 U16 MappingInformation; /*0x08 */ 3312 U16 DeviceIndex; /*0x0A */ 3313 U32 PhysicalBitsMapping; /*0x0C */ 3314 U32 Reserved1; /*0x10 */ 3315 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3316 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3317 Mpi2DriverMap0Entry_t, *pMpi2DriverMap0Entry_t; 3318 3319 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 { 3320 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3321 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /*0x08 */ 3322 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3323 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3324 Mpi2DriverMappingPage0_t, *pMpi2DriverMappingPage0_t; 3325 3326 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00) 3327 3328 /*values for Driver Persistent Mapping Page 0 MappingInformation field */ 3329 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0) 3330 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4) 3331 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F) 3332 3333 3334 /**************************************************************************** 3335 * Ethernet Config Pages 3336 ****************************************************************************/ 3337 3338 /*Ethernet Page 0 */ 3339 3340 /*IP address (union of IPv4 and IPv6) */ 3341 typedef union _MPI2_ETHERNET_IP_ADDR { 3342 U32 IPv4Addr; 3343 U32 IPv6Addr[4]; 3344 } MPI2_ETHERNET_IP_ADDR, *PTR_MPI2_ETHERNET_IP_ADDR, 3345 Mpi2EthernetIpAddr_t, *pMpi2EthernetIpAddr_t; 3346 3347 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32) 3348 3349 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 { 3350 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3351 U8 NumInterfaces; /*0x08 */ 3352 U8 Reserved0; /*0x09 */ 3353 U16 Reserved1; /*0x0A */ 3354 U32 Status; /*0x0C */ 3355 U8 MediaState; /*0x10 */ 3356 U8 Reserved2; /*0x11 */ 3357 U16 Reserved3; /*0x12 */ 3358 U8 MacAddress[6]; /*0x14 */ 3359 U8 Reserved4; /*0x1A */ 3360 U8 Reserved5; /*0x1B */ 3361 MPI2_ETHERNET_IP_ADDR IpAddress; /*0x1C */ 3362 MPI2_ETHERNET_IP_ADDR SubnetMask; /*0x2C */ 3363 MPI2_ETHERNET_IP_ADDR GatewayIpAddress;/*0x3C */ 3364 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /*0x4C */ 3365 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /*0x5C */ 3366 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /*0x6C */ 3367 U8 3368 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */ 3369 } MPI2_CONFIG_PAGE_ETHERNET_0, 3370 *PTR_MPI2_CONFIG_PAGE_ETHERNET_0, 3371 Mpi2EthernetPage0_t, *pMpi2EthernetPage0_t; 3372 3373 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00) 3374 3375 /*values for Ethernet Page 0 Status field */ 3376 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000) 3377 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000) 3378 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000) 3379 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100) 3380 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080) 3381 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040) 3382 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020) 3383 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010) 3384 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008) 3385 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004) 3386 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002) 3387 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001) 3388 3389 /*values for Ethernet Page 0 MediaState field */ 3390 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80) 3391 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00) 3392 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80) 3393 3394 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07) 3395 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00) 3396 #define MPI2_ETHPG0_MS_10MBIT (0x01) 3397 #define MPI2_ETHPG0_MS_100MBIT (0x02) 3398 #define MPI2_ETHPG0_MS_1GBIT (0x03) 3399 3400 3401 /*Ethernet Page 1 */ 3402 3403 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 { 3404 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3405 Header; /*0x00 */ 3406 U32 3407 Reserved0; /*0x08 */ 3408 U32 3409 Flags; /*0x0C */ 3410 U8 3411 MediaState; /*0x10 */ 3412 U8 3413 Reserved1; /*0x11 */ 3414 U16 3415 Reserved2; /*0x12 */ 3416 U8 3417 MacAddress[6]; /*0x14 */ 3418 U8 3419 Reserved3; /*0x1A */ 3420 U8 3421 Reserved4; /*0x1B */ 3422 MPI2_ETHERNET_IP_ADDR 3423 StaticIpAddress; /*0x1C */ 3424 MPI2_ETHERNET_IP_ADDR 3425 StaticSubnetMask; /*0x2C */ 3426 MPI2_ETHERNET_IP_ADDR 3427 StaticGatewayIpAddress; /*0x3C */ 3428 MPI2_ETHERNET_IP_ADDR 3429 StaticDNS1IpAddress; /*0x4C */ 3430 MPI2_ETHERNET_IP_ADDR 3431 StaticDNS2IpAddress; /*0x5C */ 3432 U32 3433 Reserved5; /*0x6C */ 3434 U32 3435 Reserved6; /*0x70 */ 3436 U32 3437 Reserved7; /*0x74 */ 3438 U32 3439 Reserved8; /*0x78 */ 3440 U8 3441 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */ 3442 } MPI2_CONFIG_PAGE_ETHERNET_1, 3443 *PTR_MPI2_CONFIG_PAGE_ETHERNET_1, 3444 Mpi2EthernetPage1_t, *pMpi2EthernetPage1_t; 3445 3446 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00) 3447 3448 /*values for Ethernet Page 1 Flags field */ 3449 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100) 3450 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080) 3451 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040) 3452 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020) 3453 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010) 3454 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008) 3455 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004) 3456 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002) 3457 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001) 3458 3459 /*values for Ethernet Page 1 MediaState field */ 3460 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80) 3461 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00) 3462 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80) 3463 3464 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07) 3465 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00) 3466 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01) 3467 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02) 3468 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03) 3469 3470 3471 /**************************************************************************** 3472 * Extended Manufacturing Config Pages 3473 ****************************************************************************/ 3474 3475 /* 3476 *Generic structure to use for product-specific extended manufacturing pages 3477 *(currently Extended Manufacturing Page 40 through Extended Manufacturing 3478 *Page 60). 3479 */ 3480 3481 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS { 3482 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3483 Header; /*0x00 */ 3484 U32 3485 ProductSpecificInfo; /*0x08 */ 3486 } MPI2_CONFIG_PAGE_EXT_MAN_PS, 3487 *PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS, 3488 Mpi2ExtManufacturingPagePS_t, 3489 *pMpi2ExtManufacturingPagePS_t; 3490 3491 /*PageVersion should be provided by product-specific code */ 3492 3493 #endif 3494