1 /* 2 * Copyright 2000-2015 Avago Technologies. All rights reserved. 3 * 4 * 5 * Name: mpi2_cnfg.h 6 * Title: MPI Configuration messages and pages 7 * Creation Date: November 10, 2006 8 * 9 * mpi2_cnfg.h Version: 02.00.33 10 * 11 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 12 * prefix are for use only on MPI v2.5 products, and must not be used 13 * with MPI v2.0 products. Unless otherwise noted, names beginning with 14 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 15 * 16 * Version History 17 * --------------- 18 * 19 * Date Version Description 20 * -------- -------- ------------------------------------------------------ 21 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 22 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags. 23 * Added Manufacturing Page 11. 24 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE 25 * define. 26 * 06-26-07 02.00.02 Adding generic structure for product-specific 27 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS. 28 * Rework of BIOS Page 2 configuration page. 29 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the 30 * forms. 31 * Added configuration pages IOC Page 8 and Driver 32 * Persistent Mapping Page 0. 33 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated 34 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1, 35 * RAID Physical Disk Pages 0 and 1, RAID Configuration 36 * Page 0). 37 * Added new value for AccessStatus field of SAS Device 38 * Page 0 (_SATA_NEEDS_INITIALIZATION). 39 * 10-31-07 02.00.04 Added missing SEPDevHandle field to 40 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 41 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for 42 * NVDATA. 43 * Modified IOC Page 7 to use masks and added field for 44 * SASBroadcastPrimitiveMasks. 45 * Added MPI2_CONFIG_PAGE_BIOS_4. 46 * Added MPI2_CONFIG_PAGE_LOG_0. 47 * 02-29-08 02.00.06 Modified various names to make them 32-character unique. 48 * Added SAS Device IDs. 49 * Updated Integrated RAID configuration pages including 50 * Manufacturing Page 4, IOC Page 6, and RAID Configuration 51 * Page 0. 52 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA. 53 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION. 54 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING. 55 * Added missing MaxNumRoutedSasAddresses field to 56 * MPI2_CONFIG_PAGE_EXPANDER_0. 57 * Added SAS Port Page 0. 58 * Modified structure layout for 59 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0. 60 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use 61 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array. 62 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF 63 * to 0x000000FF. 64 * Added two new values for the Physical Disk Coercion Size 65 * bits in the Flags field of Manufacturing Page 4. 66 * Added product-specific Manufacturing pages 16 to 31. 67 * Modified Flags bits for controlling write cache on SATA 68 * drives in IO Unit Page 1. 69 * Added new bit to AdditionalControlFlags of SAS IO Unit 70 * Page 1 to control Invalid Topology Correction. 71 * Added additional defines for RAID Volume Page 0 72 * VolumeStatusFlags field. 73 * Modified meaning of RAID Volume Page 0 VolumeSettings 74 * define for auto-configure of hot-swap drives. 75 * Added SupportedPhysDisks field to RAID Volume Page 1 and 76 * added related defines. 77 * Added PhysDiskAttributes field (and related defines) to 78 * RAID Physical Disk Page 0. 79 * Added MPI2_SAS_PHYINFO_PHY_VACANT define. 80 * Added three new DiscoveryStatus bits for SAS IO Unit 81 * Page 0 and SAS Expander Page 0. 82 * Removed multiplexing information from SAS IO Unit pages. 83 * Added BootDeviceWaitTime field to SAS IO Unit Page 4. 84 * Removed Zone Address Resolved bit from PhyInfo and from 85 * Expander Page 0 Flags field. 86 * Added two new AccessStatus values to SAS Device Page 0 87 * for indicating routing problems. Added 3 reserved words 88 * to this page. 89 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3. 90 * Inserted missing reserved field into structure for IOC 91 * Page 6. 92 * Added more pending task bits to RAID Volume Page 0 93 * VolumeStatusFlags defines. 94 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define. 95 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0 96 * and SAS Expander Page 0 to flag a downstream initiator 97 * when in simplified routing mode. 98 * Removed SATA Init Failure defines for DiscoveryStatus 99 * fields of SAS IO Unit Page 0 and SAS Expander Page 0. 100 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define. 101 * Added PortGroups, DmaGroup, and ControlGroup fields to 102 * SAS Device Page 0. 103 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO 104 * Unit Page 6. 105 * Added expander reduced functionality data to SAS 106 * Expander Page 0. 107 * Added SAS PHY Page 2 and SAS PHY Page 3. 108 * 07-30-09 02.00.12 Added IO Unit Page 7. 109 * Added new device ids. 110 * Added SAS IO Unit Page 5. 111 * Added partial and slumber power management capable flags 112 * to SAS Device Page 0 Flags field. 113 * Added PhyInfo defines for power condition. 114 * Added Ethernet configuration pages. 115 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY. 116 * Added SAS PHY Page 4 structure and defines. 117 * 02-10-10 02.00.14 Modified the comments for the configuration page 118 * structures that contain an array of data. The host 119 * should use the "count" field in the page data (e.g. the 120 * NumPhys field) to determine the number of valid elements 121 * in the array. 122 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines. 123 * Added PowerManagementCapabilities to IO Unit Page 7. 124 * Added PortWidthModGroup field to 125 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS. 126 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines. 127 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines. 128 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines. 129 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT 130 * define. 131 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define. 132 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define. 133 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing) 134 * defines. 135 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to 136 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for 137 * the Pinout field. 138 * Added BoardTemperature and BoardTemperatureUnits fields 139 * to MPI2_CONFIG_PAGE_IO_UNIT_7. 140 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define 141 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure. 142 * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST. 143 * Added IO Unit Page 8, IO Unit Page 9, 144 * and IO Unit Page 10. 145 * Added SASNotifyPrimitiveMasks field to 146 * MPI2_CONFIG_PAGE_IOC_7. 147 * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec). 148 * 05-25-11 02.00.20 Cleaned up a few comments. 149 * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities 150 * for PCIe link as obsolete. 151 * Added SpinupFlags field containing a Disable Spin-up bit 152 * to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO 153 * Unit Page 4. 154 * 11-18-11 02.00.22 Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT. 155 * Added UEFIVersion field to BIOS Page 1 and defined new 156 * BiosOptions bits. 157 * Incorporating additions for MPI v2.5. 158 * 11-27-12 02.00.23 Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER. 159 * Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID. 160 * 12-20-12 02.00.24 Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as 161 * obsolete for MPI v2.5 and later. 162 * Added some defines for 12G SAS speeds. 163 * 04-09-13 02.00.25 Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK. 164 * Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to 165 * match the specification. 166 * 08-19-13 02.00.26 Added reserved words to MPI2_CONFIG_PAGE_IO_UNIT_7 for 167 * future use. 168 * 12-05-13 02.00.27 Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for 169 * MPI2_CONFIG_PAGE_MAN_7. 170 * Added EnclosureLevel and ConnectorName fields to 171 * MPI2_CONFIG_PAGE_SAS_DEV_0. 172 * Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for 173 * MPI2_CONFIG_PAGE_SAS_DEV_0. 174 * Added EnclosureLevel field to 175 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 176 * Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for 177 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 178 * 01-08-14 02.00.28 Added more defines for the BiosOptions field of 179 * MPI2_CONFIG_PAGE_BIOS_1. 180 * 06-13-14 02.00.29 Added SSUTimeout field to MPI2_CONFIG_PAGE_BIOS_1, and 181 * more defines for the BiosOptions field. 182 * 11-18-14 02.00.30 Updated copyright information. 183 * Added MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG. 184 * Added AdapterOrderAux fields to BIOS Page 3. 185 * 03-16-15 02.00.31 Updated for MPI v2.6. 186 * Added new SAS Phy Event codes 187 * 05-25-15 02.00.33 Added more defines for the BiosOptions field of 188 * MPI2_CONFIG_PAGE_BIOS_1. 189 * -------------------------------------------------------------------------- 190 */ 191 192 #ifndef MPI2_CNFG_H 193 #define MPI2_CNFG_H 194 195 /***************************************************************************** 196 * Configuration Page Header and defines 197 *****************************************************************************/ 198 199 /*Config Page Header */ 200 typedef struct _MPI2_CONFIG_PAGE_HEADER { 201 U8 PageVersion; /*0x00 */ 202 U8 PageLength; /*0x01 */ 203 U8 PageNumber; /*0x02 */ 204 U8 PageType; /*0x03 */ 205 } MPI2_CONFIG_PAGE_HEADER, *PTR_MPI2_CONFIG_PAGE_HEADER, 206 Mpi2ConfigPageHeader_t, *pMpi2ConfigPageHeader_t; 207 208 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION { 209 MPI2_CONFIG_PAGE_HEADER Struct; 210 U8 Bytes[4]; 211 U16 Word16[2]; 212 U32 Word32; 213 } MPI2_CONFIG_PAGE_HEADER_UNION, *PTR_MPI2_CONFIG_PAGE_HEADER_UNION, 214 Mpi2ConfigPageHeaderUnion, *pMpi2ConfigPageHeaderUnion; 215 216 /*Extended Config Page Header */ 217 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER { 218 U8 PageVersion; /*0x00 */ 219 U8 Reserved1; /*0x01 */ 220 U8 PageNumber; /*0x02 */ 221 U8 PageType; /*0x03 */ 222 U16 ExtPageLength; /*0x04 */ 223 U8 ExtPageType; /*0x06 */ 224 U8 Reserved2; /*0x07 */ 225 } MPI2_CONFIG_EXTENDED_PAGE_HEADER, 226 *PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER, 227 Mpi2ConfigExtendedPageHeader_t, 228 *pMpi2ConfigExtendedPageHeader_t; 229 230 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION { 231 MPI2_CONFIG_PAGE_HEADER Struct; 232 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext; 233 U8 Bytes[8]; 234 U16 Word16[4]; 235 U32 Word32[2]; 236 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 237 *PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 238 Mpi2ConfigPageExtendedHeaderUnion, 239 *pMpi2ConfigPageExtendedHeaderUnion; 240 241 242 /*PageType field values */ 243 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 244 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 245 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 246 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0) 247 248 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00) 249 #define MPI2_CONFIG_PAGETYPE_IOC (0x01) 250 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02) 251 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 252 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09) 253 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 254 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F) 255 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F) 256 257 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF) 258 259 260 /*ExtPageType field values */ 261 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 262 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 263 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 264 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 265 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14) 266 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 267 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 268 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 269 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 270 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19) 271 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A) 272 273 274 /***************************************************************************** 275 * PageAddress defines 276 *****************************************************************************/ 277 278 /*RAID Volume PageAddress format */ 279 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000) 280 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 281 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000) 282 283 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF) 284 285 286 /*RAID Physical Disk PageAddress format */ 287 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000) 288 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000) 289 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000) 290 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000) 291 292 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 293 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF) 294 295 296 /*SAS Expander PageAddress format */ 297 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 298 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 299 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000) 300 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000) 301 302 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) 303 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) 304 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 305 306 307 /*SAS Device PageAddress format */ 308 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 309 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 310 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000) 311 312 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 313 314 315 /*SAS PHY PageAddress format */ 316 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 317 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 318 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000) 319 320 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 321 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 322 323 324 /*SAS Port PageAddress format */ 325 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000) 326 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 327 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 328 329 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF) 330 331 332 /*SAS Enclosure PageAddress format */ 333 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 334 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 335 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 336 337 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 338 339 340 /*RAID Configuration PageAddress format */ 341 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000) 342 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000) 343 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000) 344 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000) 345 346 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF) 347 348 349 /*Driver Persistent Mapping PageAddress format */ 350 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000) 351 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000) 352 353 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000) 354 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16) 355 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF) 356 357 358 /*Ethernet PageAddress format */ 359 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000) 360 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000) 361 362 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF) 363 364 365 /**************************************************************************** 366 * Configuration messages 367 ****************************************************************************/ 368 369 /*Configuration Request Message */ 370 typedef struct _MPI2_CONFIG_REQUEST { 371 U8 Action; /*0x00 */ 372 U8 SGLFlags; /*0x01 */ 373 U8 ChainOffset; /*0x02 */ 374 U8 Function; /*0x03 */ 375 U16 ExtPageLength; /*0x04 */ 376 U8 ExtPageType; /*0x06 */ 377 U8 MsgFlags; /*0x07 */ 378 U8 VP_ID; /*0x08 */ 379 U8 VF_ID; /*0x09 */ 380 U16 Reserved1; /*0x0A */ 381 U8 Reserved2; /*0x0C */ 382 U8 ProxyVF_ID; /*0x0D */ 383 U16 Reserved4; /*0x0E */ 384 U32 Reserved3; /*0x10 */ 385 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */ 386 U32 PageAddress; /*0x18 */ 387 MPI2_SGE_IO_UNION PageBufferSGE; /*0x1C */ 388 } MPI2_CONFIG_REQUEST, *PTR_MPI2_CONFIG_REQUEST, 389 Mpi2ConfigRequest_t, *pMpi2ConfigRequest_t; 390 391 /*values for the Action field */ 392 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00) 393 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 394 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 395 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03) 396 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 397 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 398 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 399 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07) 400 401 /*use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */ 402 403 404 /*Config Reply Message */ 405 typedef struct _MPI2_CONFIG_REPLY { 406 U8 Action; /*0x00 */ 407 U8 SGLFlags; /*0x01 */ 408 U8 MsgLength; /*0x02 */ 409 U8 Function; /*0x03 */ 410 U16 ExtPageLength; /*0x04 */ 411 U8 ExtPageType; /*0x06 */ 412 U8 MsgFlags; /*0x07 */ 413 U8 VP_ID; /*0x08 */ 414 U8 VF_ID; /*0x09 */ 415 U16 Reserved1; /*0x0A */ 416 U16 Reserved2; /*0x0C */ 417 U16 IOCStatus; /*0x0E */ 418 U32 IOCLogInfo; /*0x10 */ 419 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */ 420 } MPI2_CONFIG_REPLY, *PTR_MPI2_CONFIG_REPLY, 421 Mpi2ConfigReply_t, *pMpi2ConfigReply_t; 422 423 424 425 /***************************************************************************** 426 * 427 * C o n f i g u r a t i o n P a g e s 428 * 429 *****************************************************************************/ 430 431 /**************************************************************************** 432 * Manufacturing Config pages 433 ****************************************************************************/ 434 435 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000) 436 437 /*MPI v2.0 SAS products */ 438 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070) 439 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072) 440 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074) 441 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076) 442 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077) 443 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064) 444 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065) 445 446 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E) 447 448 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080) 449 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081) 450 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082) 451 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083) 452 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084) 453 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085) 454 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086) 455 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087) 456 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E) 457 458 /*MPI v2.5 SAS products */ 459 #define MPI25_MFGPAGE_DEVID_SAS3004 (0x0096) 460 #define MPI25_MFGPAGE_DEVID_SAS3008 (0x0097) 461 #define MPI25_MFGPAGE_DEVID_SAS3108_1 (0x0090) 462 #define MPI25_MFGPAGE_DEVID_SAS3108_2 (0x0091) 463 #define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094) 464 #define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095) 465 466 /* MPI v2.6 SAS Products */ 467 #define MPI26_MFGPAGE_DEVID_SAS3216 (0x00C9) 468 #define MPI26_MFGPAGE_DEVID_SAS3224 (0x00C4) 469 #define MPI26_MFGPAGE_DEVID_SAS3316_1 (0x00C5) 470 #define MPI26_MFGPAGE_DEVID_SAS3316_2 (0x00C6) 471 #define MPI26_MFGPAGE_DEVID_SAS3316_3 (0x00C7) 472 #define MPI26_MFGPAGE_DEVID_SAS3316_4 (0x00C8) 473 #define MPI26_MFGPAGE_DEVID_SAS3324_1 (0x00C0) 474 #define MPI26_MFGPAGE_DEVID_SAS3324_2 (0x00C1) 475 #define MPI26_MFGPAGE_DEVID_SAS3324_3 (0x00C2) 476 #define MPI26_MFGPAGE_DEVID_SAS3324_4 (0x00C3) 477 478 /*Manufacturing Page 0 */ 479 480 typedef struct _MPI2_CONFIG_PAGE_MAN_0 { 481 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 482 U8 ChipName[16]; /*0x04 */ 483 U8 ChipRevision[8]; /*0x14 */ 484 U8 BoardName[16]; /*0x1C */ 485 U8 BoardAssembly[16]; /*0x2C */ 486 U8 BoardTracerNumber[16]; /*0x3C */ 487 } MPI2_CONFIG_PAGE_MAN_0, 488 *PTR_MPI2_CONFIG_PAGE_MAN_0, 489 Mpi2ManufacturingPage0_t, 490 *pMpi2ManufacturingPage0_t; 491 492 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00) 493 494 495 /*Manufacturing Page 1 */ 496 497 typedef struct _MPI2_CONFIG_PAGE_MAN_1 { 498 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 499 U8 VPD[256]; /*0x04 */ 500 } MPI2_CONFIG_PAGE_MAN_1, 501 *PTR_MPI2_CONFIG_PAGE_MAN_1, 502 Mpi2ManufacturingPage1_t, 503 *pMpi2ManufacturingPage1_t; 504 505 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00) 506 507 508 typedef struct _MPI2_CHIP_REVISION_ID { 509 U16 DeviceID; /*0x00 */ 510 U8 PCIRevisionID; /*0x02 */ 511 U8 Reserved; /*0x03 */ 512 } MPI2_CHIP_REVISION_ID, *PTR_MPI2_CHIP_REVISION_ID, 513 Mpi2ChipRevisionId_t, *pMpi2ChipRevisionId_t; 514 515 516 /*Manufacturing Page 2 */ 517 518 /* 519 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 520 *one and check Header.PageLength at runtime. 521 */ 522 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS 523 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 524 #endif 525 526 typedef struct _MPI2_CONFIG_PAGE_MAN_2 { 527 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 528 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */ 529 U32 530 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/*0x08 */ 531 } MPI2_CONFIG_PAGE_MAN_2, 532 *PTR_MPI2_CONFIG_PAGE_MAN_2, 533 Mpi2ManufacturingPage2_t, 534 *pMpi2ManufacturingPage2_t; 535 536 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00) 537 538 539 /*Manufacturing Page 3 */ 540 541 /* 542 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 543 *one and check Header.PageLength at runtime. 544 */ 545 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS 546 #define MPI2_MAN_PAGE_3_INFO_WORDS (1) 547 #endif 548 549 typedef struct _MPI2_CONFIG_PAGE_MAN_3 { 550 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 551 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */ 552 U32 553 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/*0x08 */ 554 } MPI2_CONFIG_PAGE_MAN_3, 555 *PTR_MPI2_CONFIG_PAGE_MAN_3, 556 Mpi2ManufacturingPage3_t, 557 *pMpi2ManufacturingPage3_t; 558 559 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00) 560 561 562 /*Manufacturing Page 4 */ 563 564 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS { 565 U8 PowerSaveFlags; /*0x00 */ 566 U8 InternalOperationsSleepTime; /*0x01 */ 567 U8 InternalOperationsRunTime; /*0x02 */ 568 U8 HostIdleTime; /*0x03 */ 569 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 570 *PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 571 Mpi2ManPage4PwrSaveSettings_t, 572 *pMpi2ManPage4PwrSaveSettings_t; 573 574 /*defines for the PowerSaveFlags field */ 575 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03) 576 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00) 577 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01) 578 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02) 579 580 typedef struct _MPI2_CONFIG_PAGE_MAN_4 { 581 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 582 U32 Reserved1; /*0x04 */ 583 U32 Flags; /*0x08 */ 584 U8 InquirySize; /*0x0C */ 585 U8 Reserved2; /*0x0D */ 586 U16 Reserved3; /*0x0E */ 587 U8 InquiryData[56]; /*0x10 */ 588 U32 RAID0VolumeSettings; /*0x48 */ 589 U32 RAID1EVolumeSettings; /*0x4C */ 590 U32 RAID1VolumeSettings; /*0x50 */ 591 U32 RAID10VolumeSettings; /*0x54 */ 592 U32 Reserved4; /*0x58 */ 593 U32 Reserved5; /*0x5C */ 594 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /*0x60 */ 595 U8 MaxOCEDisks; /*0x64 */ 596 U8 ResyncRate; /*0x65 */ 597 U16 DataScrubDuration; /*0x66 */ 598 U8 MaxHotSpares; /*0x68 */ 599 U8 MaxPhysDisksPerVol; /*0x69 */ 600 U8 MaxPhysDisks; /*0x6A */ 601 U8 MaxVolumes; /*0x6B */ 602 } MPI2_CONFIG_PAGE_MAN_4, 603 *PTR_MPI2_CONFIG_PAGE_MAN_4, 604 Mpi2ManufacturingPage4_t, 605 *pMpi2ManufacturingPage4_t; 606 607 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A) 608 609 /*Manufacturing Page 4 Flags field */ 610 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000) 611 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000) 612 613 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000) 614 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000) 615 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000) 616 617 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00) 618 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000) 619 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400) 620 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800) 621 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00) 622 623 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300) 624 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000) 625 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100) 626 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200) 627 628 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080) 629 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040) 630 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020) 631 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010) 632 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008) 633 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004) 634 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002) 635 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001) 636 637 638 /*Manufacturing Page 5 */ 639 640 /* 641 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 642 *one and check the value returned for NumPhys at runtime. 643 */ 644 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES 645 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1) 646 #endif 647 648 typedef struct _MPI2_MANUFACTURING5_ENTRY { 649 U64 WWID; /*0x00 */ 650 U64 DeviceName; /*0x08 */ 651 } MPI2_MANUFACTURING5_ENTRY, 652 *PTR_MPI2_MANUFACTURING5_ENTRY, 653 Mpi2Manufacturing5Entry_t, 654 *pMpi2Manufacturing5Entry_t; 655 656 typedef struct _MPI2_CONFIG_PAGE_MAN_5 { 657 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 658 U8 NumPhys; /*0x04 */ 659 U8 Reserved1; /*0x05 */ 660 U16 Reserved2; /*0x06 */ 661 U32 Reserved3; /*0x08 */ 662 U32 Reserved4; /*0x0C */ 663 MPI2_MANUFACTURING5_ENTRY 664 Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/*0x08 */ 665 } MPI2_CONFIG_PAGE_MAN_5, 666 *PTR_MPI2_CONFIG_PAGE_MAN_5, 667 Mpi2ManufacturingPage5_t, 668 *pMpi2ManufacturingPage5_t; 669 670 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03) 671 672 673 /*Manufacturing Page 6 */ 674 675 typedef struct _MPI2_CONFIG_PAGE_MAN_6 { 676 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 677 U32 ProductSpecificInfo;/*0x04 */ 678 } MPI2_CONFIG_PAGE_MAN_6, 679 *PTR_MPI2_CONFIG_PAGE_MAN_6, 680 Mpi2ManufacturingPage6_t, 681 *pMpi2ManufacturingPage6_t; 682 683 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00) 684 685 686 /*Manufacturing Page 7 */ 687 688 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO { 689 U32 Pinout; /*0x00 */ 690 U8 Connector[16]; /*0x04 */ 691 U8 Location; /*0x14 */ 692 U8 ReceptacleID; /*0x15 */ 693 U16 Slot; /*0x16 */ 694 U32 Reserved2; /*0x18 */ 695 } MPI2_MANPAGE7_CONNECTOR_INFO, 696 *PTR_MPI2_MANPAGE7_CONNECTOR_INFO, 697 Mpi2ManPage7ConnectorInfo_t, 698 *pMpi2ManPage7ConnectorInfo_t; 699 700 /*defines for the Pinout field */ 701 #define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00) 702 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8) 703 704 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF) 705 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00) 706 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01) 707 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02) 708 #define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03) 709 #define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04) 710 #define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05) 711 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06) 712 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07) 713 #define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08) 714 #define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09) 715 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A) 716 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B) 717 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C) 718 #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D) 719 720 /*defines for the Location field */ 721 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01) 722 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02) 723 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04) 724 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08) 725 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10) 726 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 727 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 728 729 /* 730 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 731 *one and check the value returned for NumPhys at runtime. 732 */ 733 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX 734 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1) 735 #endif 736 737 typedef struct _MPI2_CONFIG_PAGE_MAN_7 { 738 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 739 U32 Reserved1; /*0x04 */ 740 U32 Reserved2; /*0x08 */ 741 U32 Flags; /*0x0C */ 742 U8 EnclosureName[16]; /*0x10 */ 743 U8 NumPhys; /*0x20 */ 744 U8 Reserved3; /*0x21 */ 745 U16 Reserved4; /*0x22 */ 746 MPI2_MANPAGE7_CONNECTOR_INFO 747 ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /*0x24 */ 748 } MPI2_CONFIG_PAGE_MAN_7, 749 *PTR_MPI2_CONFIG_PAGE_MAN_7, 750 Mpi2ManufacturingPage7_t, 751 *pMpi2ManufacturingPage7_t; 752 753 #define MPI2_MANUFACTURING7_PAGEVERSION (0x01) 754 755 /*defines for the Flags field */ 756 #define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL (0x00000008) 757 #define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER (0x00000002) 758 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 759 760 761 /* 762 *Generic structure to use for product-specific manufacturing pages 763 *(currently Manufacturing Page 8 through Manufacturing Page 31). 764 */ 765 766 typedef struct _MPI2_CONFIG_PAGE_MAN_PS { 767 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 768 U32 ProductSpecificInfo;/*0x04 */ 769 } MPI2_CONFIG_PAGE_MAN_PS, 770 *PTR_MPI2_CONFIG_PAGE_MAN_PS, 771 Mpi2ManufacturingPagePS_t, 772 *pMpi2ManufacturingPagePS_t; 773 774 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00) 775 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00) 776 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00) 777 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00) 778 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00) 779 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00) 780 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00) 781 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00) 782 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00) 783 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00) 784 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00) 785 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00) 786 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00) 787 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00) 788 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00) 789 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00) 790 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00) 791 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00) 792 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00) 793 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00) 794 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00) 795 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00) 796 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00) 797 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00) 798 799 800 /**************************************************************************** 801 * IO Unit Config Pages 802 ****************************************************************************/ 803 804 /*IO Unit Page 0 */ 805 806 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 { 807 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 808 U64 UniqueValue; /*0x04 */ 809 MPI2_VERSION_UNION NvdataVersionDefault; /*0x08 */ 810 MPI2_VERSION_UNION NvdataVersionPersistent; /*0x0A */ 811 } MPI2_CONFIG_PAGE_IO_UNIT_0, 812 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_0, 813 Mpi2IOUnitPage0_t, *pMpi2IOUnitPage0_t; 814 815 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02) 816 817 818 /*IO Unit Page 1 */ 819 820 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 { 821 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 822 U32 Flags; /*0x04 */ 823 } MPI2_CONFIG_PAGE_IO_UNIT_1, 824 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_1, 825 Mpi2IOUnitPage1_t, *pMpi2IOUnitPage1_t; 826 827 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04) 828 829 /*IO Unit Page 1 Flags defines */ 830 #define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK (0x00004000) 831 #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000) 832 #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000) 833 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800) 834 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600) 835 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9) 836 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000) 837 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200) 838 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400) 839 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 840 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040) 841 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020) 842 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 843 844 845 /*IO Unit Page 3 */ 846 847 /* 848 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 849 *one and check the value returned for GPIOCount at runtime. 850 */ 851 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX 852 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 853 #endif 854 855 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 { 856 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 857 U8 GPIOCount; /*0x04 */ 858 U8 Reserved1; /*0x05 */ 859 U16 Reserved2; /*0x06 */ 860 U16 861 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/*0x08 */ 862 } MPI2_CONFIG_PAGE_IO_UNIT_3, 863 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_3, 864 Mpi2IOUnitPage3_t, *pMpi2IOUnitPage3_t; 865 866 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01) 867 868 /*defines for IO Unit Page 3 GPIOVal field */ 869 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC) 870 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 871 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000) 872 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001) 873 874 875 /*IO Unit Page 5 */ 876 877 /* 878 *Upper layer code (drivers, utilities, etc.) should leave this define set to 879 *one and check the value returned for NumDmaEngines at runtime. 880 */ 881 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES 882 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1) 883 #endif 884 885 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 { 886 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 887 U64 888 RaidAcceleratorBufferBaseAddress; /*0x04 */ 889 U64 890 RaidAcceleratorBufferSize; /*0x0C */ 891 U64 892 RaidAcceleratorControlBaseAddress; /*0x14 */ 893 U8 RAControlSize; /*0x1C */ 894 U8 NumDmaEngines; /*0x1D */ 895 U8 RAMinControlSize; /*0x1E */ 896 U8 RAMaxControlSize; /*0x1F */ 897 U32 Reserved1; /*0x20 */ 898 U32 Reserved2; /*0x24 */ 899 U32 Reserved3; /*0x28 */ 900 U32 901 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /*0x2C */ 902 } MPI2_CONFIG_PAGE_IO_UNIT_5, 903 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_5, 904 Mpi2IOUnitPage5_t, *pMpi2IOUnitPage5_t; 905 906 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00) 907 908 /*defines for IO Unit Page 5 DmaEngineCapabilities field */ 909 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFFFF0000) 910 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16) 911 912 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008) 913 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004) 914 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002) 915 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001) 916 917 918 /*IO Unit Page 6 */ 919 920 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 { 921 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 922 U16 Flags; /*0x04 */ 923 U8 RAHostControlSize; /*0x06 */ 924 U8 Reserved0; /*0x07 */ 925 U64 926 RaidAcceleratorHostControlBaseAddress; /*0x08 */ 927 U32 Reserved1; /*0x10 */ 928 U32 Reserved2; /*0x14 */ 929 U32 Reserved3; /*0x18 */ 930 } MPI2_CONFIG_PAGE_IO_UNIT_6, 931 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_6, 932 Mpi2IOUnitPage6_t, *pMpi2IOUnitPage6_t; 933 934 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00) 935 936 /*defines for IO Unit Page 6 Flags field */ 937 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001) 938 939 940 /*IO Unit Page 7 */ 941 942 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 { 943 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 944 U8 CurrentPowerMode; /*0x04 */ 945 U8 PreviousPowerMode; /*0x05 */ 946 U8 PCIeWidth; /*0x06 */ 947 U8 PCIeSpeed; /*0x07 */ 948 U32 ProcessorState; /*0x08 */ 949 U32 950 PowerManagementCapabilities; /*0x0C */ 951 U16 IOCTemperature; /*0x10 */ 952 U8 953 IOCTemperatureUnits; /*0x12 */ 954 U8 IOCSpeed; /*0x13 */ 955 U16 BoardTemperature; /*0x14 */ 956 U8 957 BoardTemperatureUnits; /*0x16 */ 958 U8 Reserved3; /*0x17 */ 959 U32 BoardPowerRequirement; /*0x18 */ 960 U32 PCISlotPowerAllocation; /*0x1C */ 961 U32 Reserved6; /* 0x20 */ 962 U32 Reserved7; /* 0x24 */ 963 } MPI2_CONFIG_PAGE_IO_UNIT_7, 964 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_7, 965 Mpi2IOUnitPage7_t, *pMpi2IOUnitPage7_t; 966 967 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x04) 968 969 /*defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */ 970 #define MPI25_IOUNITPAGE7_PM_INIT_MASK (0xC0) 971 #define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE (0x00) 972 #define MPI25_IOUNITPAGE7_PM_INIT_HOST (0x40) 973 #define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT (0x80) 974 #define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA (0xC0) 975 976 #define MPI25_IOUNITPAGE7_PM_MODE_MASK (0x07) 977 #define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE (0x00) 978 #define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN (0x01) 979 #define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER (0x04) 980 #define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER (0x05) 981 #define MPI25_IOUNITPAGE7_PM_MODE_STANDBY (0x06) 982 983 984 /*defines for IO Unit Page 7 PCIeWidth field */ 985 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01) 986 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02) 987 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04) 988 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08) 989 990 /*defines for IO Unit Page 7 PCIeSpeed field */ 991 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00) 992 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01) 993 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02) 994 995 /*defines for IO Unit Page 7 ProcessorState field */ 996 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F) 997 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0) 998 999 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00) 1000 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01) 1001 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02) 1002 1003 /*defines for IO Unit Page 7 PowerManagementCapabilities field */ 1004 #define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE (0x00400000) 1005 #define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE (0x00200000) 1006 #define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE (0x00100000) 1007 #define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE (0x00040000) 1008 #define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE (0x00020000) 1009 #define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE (0x00010000) 1010 #define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE (0x00004000) 1011 #define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE (0x00002000) 1012 #define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE (0x00001000) 1013 #define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED (0x00000400) 1014 #define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED (0x00000200) 1015 #define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED (0x00000100) 1016 #define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED (0x00000040) 1017 #define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED (0x00000020) 1018 #define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED (0x00000010) 1019 #define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE (0x00000008) 1020 #define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE (0x00000004) 1021 #define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE (0x00000002) 1022 #define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE (0x00000001) 1023 1024 /*obsolete names for the PowerManagementCapabilities bits (above) */ 1025 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400) 1026 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200) 1027 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100) 1028 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /*obsolete */ 1029 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /*obsolete */ 1030 1031 1032 /*defines for IO Unit Page 7 IOCTemperatureUnits field */ 1033 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00) 1034 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01) 1035 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02) 1036 1037 /*defines for IO Unit Page 7 IOCSpeed field */ 1038 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01) 1039 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02) 1040 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04) 1041 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08) 1042 1043 /*defines for IO Unit Page 7 BoardTemperatureUnits field */ 1044 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00) 1045 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01) 1046 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02) 1047 1048 1049 /*IO Unit Page 8 */ 1050 1051 #define MPI2_IOUNIT8_NUM_THRESHOLDS (4) 1052 1053 typedef struct _MPI2_IOUNIT8_SENSOR { 1054 U16 Flags; /*0x00 */ 1055 U16 Reserved1; /*0x02 */ 1056 U16 1057 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /*0x04 */ 1058 U32 Reserved2; /*0x0C */ 1059 U32 Reserved3; /*0x10 */ 1060 U32 Reserved4; /*0x14 */ 1061 } MPI2_IOUNIT8_SENSOR, *PTR_MPI2_IOUNIT8_SENSOR, 1062 Mpi2IOUnit8Sensor_t, *pMpi2IOUnit8Sensor_t; 1063 1064 /*defines for IO Unit Page 8 Sensor Flags field */ 1065 #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008) 1066 #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004) 1067 #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002) 1068 #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001) 1069 1070 /* 1071 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1072 *one and check the value returned for NumSensors at runtime. 1073 */ 1074 #ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES 1075 #define MPI2_IOUNITPAGE8_SENSOR_ENTRIES (1) 1076 #endif 1077 1078 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 { 1079 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1080 U32 Reserved1; /*0x04 */ 1081 U32 Reserved2; /*0x08 */ 1082 U8 NumSensors; /*0x0C */ 1083 U8 PollingInterval; /*0x0D */ 1084 U16 Reserved3; /*0x0E */ 1085 MPI2_IOUNIT8_SENSOR 1086 Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/*0x10 */ 1087 } MPI2_CONFIG_PAGE_IO_UNIT_8, 1088 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_8, 1089 Mpi2IOUnitPage8_t, *pMpi2IOUnitPage8_t; 1090 1091 #define MPI2_IOUNITPAGE8_PAGEVERSION (0x00) 1092 1093 1094 /*IO Unit Page 9 */ 1095 1096 typedef struct _MPI2_IOUNIT9_SENSOR { 1097 U16 CurrentTemperature; /*0x00 */ 1098 U16 Reserved1; /*0x02 */ 1099 U8 Flags; /*0x04 */ 1100 U8 Reserved2; /*0x05 */ 1101 U16 Reserved3; /*0x06 */ 1102 U32 Reserved4; /*0x08 */ 1103 U32 Reserved5; /*0x0C */ 1104 } MPI2_IOUNIT9_SENSOR, *PTR_MPI2_IOUNIT9_SENSOR, 1105 Mpi2IOUnit9Sensor_t, *pMpi2IOUnit9Sensor_t; 1106 1107 /*defines for IO Unit Page 9 Sensor Flags field */ 1108 #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01) 1109 1110 /* 1111 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1112 *one and check the value returned for NumSensors at runtime. 1113 */ 1114 #ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES 1115 #define MPI2_IOUNITPAGE9_SENSOR_ENTRIES (1) 1116 #endif 1117 1118 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 { 1119 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1120 U32 Reserved1; /*0x04 */ 1121 U32 Reserved2; /*0x08 */ 1122 U8 NumSensors; /*0x0C */ 1123 U8 Reserved4; /*0x0D */ 1124 U16 Reserved3; /*0x0E */ 1125 MPI2_IOUNIT9_SENSOR 1126 Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/*0x10 */ 1127 } MPI2_CONFIG_PAGE_IO_UNIT_9, 1128 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_9, 1129 Mpi2IOUnitPage9_t, *pMpi2IOUnitPage9_t; 1130 1131 #define MPI2_IOUNITPAGE9_PAGEVERSION (0x00) 1132 1133 1134 /*IO Unit Page 10 */ 1135 1136 typedef struct _MPI2_IOUNIT10_FUNCTION { 1137 U8 CreditPercent; /*0x00 */ 1138 U8 Reserved1; /*0x01 */ 1139 U16 Reserved2; /*0x02 */ 1140 } MPI2_IOUNIT10_FUNCTION, 1141 *PTR_MPI2_IOUNIT10_FUNCTION, 1142 Mpi2IOUnit10Function_t, 1143 *pMpi2IOUnit10Function_t; 1144 1145 /* 1146 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1147 *one and check the value returned for NumFunctions at runtime. 1148 */ 1149 #ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES 1150 #define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES (1) 1151 #endif 1152 1153 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 { 1154 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1155 U8 NumFunctions; /*0x04 */ 1156 U8 Reserved1; /*0x05 */ 1157 U16 Reserved2; /*0x06 */ 1158 U32 Reserved3; /*0x08 */ 1159 U32 Reserved4; /*0x0C */ 1160 MPI2_IOUNIT10_FUNCTION 1161 Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];/*0x10 */ 1162 } MPI2_CONFIG_PAGE_IO_UNIT_10, 1163 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_10, 1164 Mpi2IOUnitPage10_t, *pMpi2IOUnitPage10_t; 1165 1166 #define MPI2_IOUNITPAGE10_PAGEVERSION (0x01) 1167 1168 1169 /* IO Unit Page 11 (for MPI v2.6 and later) */ 1170 1171 typedef struct _MPI26_IOUNIT11_SPINUP_GROUP { 1172 U8 MaxTargetSpinup; /* 0x00 */ 1173 U8 SpinupDelay; /* 0x01 */ 1174 U8 SpinupFlags; /* 0x02 */ 1175 U8 Reserved1; /* 0x03 */ 1176 } MPI26_IOUNIT11_SPINUP_GROUP, 1177 *PTR_MPI26_IOUNIT11_SPINUP_GROUP, 1178 Mpi26IOUnit11SpinupGroup_t, 1179 *pMpi26IOUnit11SpinupGroup_t; 1180 1181 /* defines for IO Unit Page 11 SpinupFlags */ 1182 #define MPI26_IOUNITPAGE11_SPINUP_DISABLE_FLAG (0x01) 1183 1184 1185 /* 1186 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1187 * four and check the value returned for NumPhys at runtime. 1188 */ 1189 #ifndef MPI26_IOUNITPAGE11_PHY_MAX 1190 #define MPI26_IOUNITPAGE11_PHY_MAX (4) 1191 #endif 1192 1193 typedef struct _MPI26_CONFIG_PAGE_IO_UNIT_11 { 1194 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1195 U32 Reserved1; /*0x04 */ 1196 MPI26_IOUNIT11_SPINUP_GROUP SpinupGroupParameters[4]; /*0x08 */ 1197 U32 Reserved2; /*0x18 */ 1198 U32 Reserved3; /*0x1C */ 1199 U32 Reserved4; /*0x20 */ 1200 U8 BootDeviceWaitTime; /*0x24 */ 1201 U8 Reserved5; /*0x25 */ 1202 U16 Reserved6; /*0x26 */ 1203 U8 NumPhys; /*0x28 */ 1204 U8 PEInitialSpinupDelay; /*0x29 */ 1205 U8 PEReplyDelay; /*0x2A */ 1206 U8 Flags; /*0x2B */ 1207 U8 PHY[MPI26_IOUNITPAGE11_PHY_MAX];/*0x2C */ 1208 } MPI26_CONFIG_PAGE_IO_UNIT_11, 1209 *PTR_MPI26_CONFIG_PAGE_IO_UNIT_11, 1210 Mpi26IOUnitPage11_t, 1211 *pMpi26IOUnitPage11_t; 1212 1213 #define MPI26_IOUNITPAGE11_PAGEVERSION (0x00) 1214 1215 /* defines for Flags field */ 1216 #define MPI26_IOUNITPAGE11_FLAGS_AUTO_PORTENABLE (0x01) 1217 1218 /* defines for PHY field */ 1219 #define MPI26_IOUNITPAGE11_PHY_SPINUP_GROUP_MASK (0x03) 1220 1221 1222 1223 1224 1225 1226 /**************************************************************************** 1227 * IOC Config Pages 1228 ****************************************************************************/ 1229 1230 /*IOC Page 0 */ 1231 1232 typedef struct _MPI2_CONFIG_PAGE_IOC_0 { 1233 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1234 U32 Reserved1; /*0x04 */ 1235 U32 Reserved2; /*0x08 */ 1236 U16 VendorID; /*0x0C */ 1237 U16 DeviceID; /*0x0E */ 1238 U8 RevisionID; /*0x10 */ 1239 U8 Reserved3; /*0x11 */ 1240 U16 Reserved4; /*0x12 */ 1241 U32 ClassCode; /*0x14 */ 1242 U16 SubsystemVendorID; /*0x18 */ 1243 U16 SubsystemID; /*0x1A */ 1244 } MPI2_CONFIG_PAGE_IOC_0, 1245 *PTR_MPI2_CONFIG_PAGE_IOC_0, 1246 Mpi2IOCPage0_t, *pMpi2IOCPage0_t; 1247 1248 #define MPI2_IOCPAGE0_PAGEVERSION (0x02) 1249 1250 1251 /*IOC Page 1 */ 1252 1253 typedef struct _MPI2_CONFIG_PAGE_IOC_1 { 1254 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1255 U32 Flags; /*0x04 */ 1256 U32 CoalescingTimeout; /*0x08 */ 1257 U8 CoalescingDepth; /*0x0C */ 1258 U8 PCISlotNum; /*0x0D */ 1259 U8 PCIBusNum; /*0x0E */ 1260 U8 PCIDomainSegment; /*0x0F */ 1261 U32 Reserved1; /*0x10 */ 1262 U32 Reserved2; /*0x14 */ 1263 } MPI2_CONFIG_PAGE_IOC_1, 1264 *PTR_MPI2_CONFIG_PAGE_IOC_1, 1265 Mpi2IOCPage1_t, *pMpi2IOCPage1_t; 1266 1267 #define MPI2_IOCPAGE1_PAGEVERSION (0x05) 1268 1269 /*defines for IOC Page 1 Flags field */ 1270 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001) 1271 1272 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 1273 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF) 1274 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF) 1275 1276 /*IOC Page 6 */ 1277 1278 typedef struct _MPI2_CONFIG_PAGE_IOC_6 { 1279 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1280 U32 1281 CapabilitiesFlags; /*0x04 */ 1282 U8 MaxDrivesRAID0; /*0x08 */ 1283 U8 MaxDrivesRAID1; /*0x09 */ 1284 U8 1285 MaxDrivesRAID1E; /*0x0A */ 1286 U8 1287 MaxDrivesRAID10; /*0x0B */ 1288 U8 MinDrivesRAID0; /*0x0C */ 1289 U8 MinDrivesRAID1; /*0x0D */ 1290 U8 1291 MinDrivesRAID1E; /*0x0E */ 1292 U8 1293 MinDrivesRAID10; /*0x0F */ 1294 U32 Reserved1; /*0x10 */ 1295 U8 1296 MaxGlobalHotSpares; /*0x14 */ 1297 U8 MaxPhysDisks; /*0x15 */ 1298 U8 MaxVolumes; /*0x16 */ 1299 U8 MaxConfigs; /*0x17 */ 1300 U8 MaxOCEDisks; /*0x18 */ 1301 U8 Reserved2; /*0x19 */ 1302 U16 Reserved3; /*0x1A */ 1303 U32 1304 SupportedStripeSizeMapRAID0; /*0x1C */ 1305 U32 1306 SupportedStripeSizeMapRAID1E; /*0x20 */ 1307 U32 1308 SupportedStripeSizeMapRAID10; /*0x24 */ 1309 U32 Reserved4; /*0x28 */ 1310 U32 Reserved5; /*0x2C */ 1311 U16 1312 DefaultMetadataSize; /*0x30 */ 1313 U16 Reserved6; /*0x32 */ 1314 U16 1315 MaxBadBlockTableEntries; /*0x34 */ 1316 U16 Reserved7; /*0x36 */ 1317 U32 1318 IRNvsramVersion; /*0x38 */ 1319 } MPI2_CONFIG_PAGE_IOC_6, 1320 *PTR_MPI2_CONFIG_PAGE_IOC_6, 1321 Mpi2IOCPage6_t, *pMpi2IOCPage6_t; 1322 1323 #define MPI2_IOCPAGE6_PAGEVERSION (0x05) 1324 1325 /*defines for IOC Page 6 CapabilitiesFlags */ 1326 #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT (0x00000020) 1327 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010) 1328 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008) 1329 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004) 1330 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002) 1331 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 1332 1333 1334 /*IOC Page 7 */ 1335 1336 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4) 1337 1338 typedef struct _MPI2_CONFIG_PAGE_IOC_7 { 1339 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1340 U32 Reserved1; /*0x04 */ 1341 U32 1342 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/*0x08 */ 1343 U16 SASBroadcastPrimitiveMasks; /*0x18 */ 1344 U16 SASNotifyPrimitiveMasks; /*0x1A */ 1345 U32 Reserved3; /*0x1C */ 1346 } MPI2_CONFIG_PAGE_IOC_7, 1347 *PTR_MPI2_CONFIG_PAGE_IOC_7, 1348 Mpi2IOCPage7_t, *pMpi2IOCPage7_t; 1349 1350 #define MPI2_IOCPAGE7_PAGEVERSION (0x02) 1351 1352 1353 /*IOC Page 8 */ 1354 1355 typedef struct _MPI2_CONFIG_PAGE_IOC_8 { 1356 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1357 U8 NumDevsPerEnclosure; /*0x04 */ 1358 U8 Reserved1; /*0x05 */ 1359 U16 Reserved2; /*0x06 */ 1360 U16 MaxPersistentEntries; /*0x08 */ 1361 U16 MaxNumPhysicalMappedIDs; /*0x0A */ 1362 U16 Flags; /*0x0C */ 1363 U16 Reserved3; /*0x0E */ 1364 U16 IRVolumeMappingFlags; /*0x10 */ 1365 U16 Reserved4; /*0x12 */ 1366 U32 Reserved5; /*0x14 */ 1367 } MPI2_CONFIG_PAGE_IOC_8, 1368 *PTR_MPI2_CONFIG_PAGE_IOC_8, 1369 Mpi2IOCPage8_t, *pMpi2IOCPage8_t; 1370 1371 #define MPI2_IOCPAGE8_PAGEVERSION (0x00) 1372 1373 /*defines for IOC Page 8 Flags field */ 1374 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020) 1375 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010) 1376 1377 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E) 1378 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000) 1379 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002) 1380 1381 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001) 1382 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000) 1383 1384 /*defines for IOC Page 8 IRVolumeMappingFlags */ 1385 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003) 1386 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000) 1387 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001) 1388 1389 1390 /**************************************************************************** 1391 * BIOS Config Pages 1392 ****************************************************************************/ 1393 1394 /*BIOS Page 1 */ 1395 1396 typedef struct _MPI2_CONFIG_PAGE_BIOS_1 { 1397 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1398 U32 BiosOptions; /*0x04 */ 1399 U32 IOCSettings; /*0x08 */ 1400 U8 SSUTimeout; /*0x0C */ 1401 U8 Reserved1; /*0x0D */ 1402 U16 Reserved2; /*0x0E */ 1403 U32 DeviceSettings; /*0x10 */ 1404 U16 NumberOfDevices; /*0x14 */ 1405 U16 UEFIVersion; /*0x16 */ 1406 U16 IOTimeoutBlockDevicesNonRM; /*0x18 */ 1407 U16 IOTimeoutSequential; /*0x1A */ 1408 U16 IOTimeoutOther; /*0x1C */ 1409 U16 IOTimeoutBlockDevicesRM; /*0x1E */ 1410 } MPI2_CONFIG_PAGE_BIOS_1, 1411 *PTR_MPI2_CONFIG_PAGE_BIOS_1, 1412 Mpi2BiosPage1_t, *pMpi2BiosPage1_t; 1413 1414 #define MPI2_BIOSPAGE1_PAGEVERSION (0x07) 1415 1416 /*values for BIOS Page 1 BiosOptions field */ 1417 #define MPI2_BIOSPAGE1_OPTIONS_BOOT_LIST_ADD_ALT_BOOT_DEVICE (0x00008000) 1418 #define MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG (0x00004000) 1419 1420 #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800) 1421 #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800) 1422 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL (0x00000000) 1423 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE (0x00000800) 1424 #define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID (0x00001000) 1425 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PSENS (0x00001800) 1426 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ESPHY (0x00002000) 1427 1428 #define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS (0x00000400) 1429 1430 #define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD (0x00000300) 1431 #define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD (0x00000000) 1432 #define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD (0x00000100) 1433 #define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD (0x00000200) 1434 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD (0x00000300) 1435 1436 #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0) 1437 #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000) 1438 1439 #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006) 1440 #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000) 1441 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002) 1442 #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004) 1443 1444 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1445 1446 /*values for BIOS Page 1 IOCSettings field */ 1447 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1448 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1449 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1450 1451 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1452 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1453 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1454 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1455 1456 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1457 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1458 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1459 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1460 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1461 1462 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1463 1464 /*values for BIOS Page 1 DeviceSettings field */ 1465 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 1466 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1467 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1468 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1469 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1470 1471 /*defines for BIOS Page 1 UEFIVersion field */ 1472 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK (0xFF00) 1473 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT (8) 1474 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK (0x00FF) 1475 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT (0) 1476 1477 1478 1479 /*BIOS Page 2 */ 1480 1481 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER { 1482 U32 Reserved1; /*0x00 */ 1483 U32 Reserved2; /*0x04 */ 1484 U32 Reserved3; /*0x08 */ 1485 U32 Reserved4; /*0x0C */ 1486 U32 Reserved5; /*0x10 */ 1487 U32 Reserved6; /*0x14 */ 1488 } MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1489 *PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1490 Mpi2BootDeviceAdapterOrder_t, 1491 *pMpi2BootDeviceAdapterOrder_t; 1492 1493 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID { 1494 U64 SASAddress; /*0x00 */ 1495 U8 LUN[8]; /*0x08 */ 1496 U32 Reserved1; /*0x10 */ 1497 U32 Reserved2; /*0x14 */ 1498 } MPI2_BOOT_DEVICE_SAS_WWID, 1499 *PTR_MPI2_BOOT_DEVICE_SAS_WWID, 1500 Mpi2BootDeviceSasWwid_t, 1501 *pMpi2BootDeviceSasWwid_t; 1502 1503 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT { 1504 U64 EnclosureLogicalID; /*0x00 */ 1505 U32 Reserved1; /*0x08 */ 1506 U32 Reserved2; /*0x0C */ 1507 U16 SlotNumber; /*0x10 */ 1508 U16 Reserved3; /*0x12 */ 1509 U32 Reserved4; /*0x14 */ 1510 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1511 *PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1512 Mpi2BootDeviceEnclosureSlot_t, 1513 *pMpi2BootDeviceEnclosureSlot_t; 1514 1515 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME { 1516 U64 DeviceName; /*0x00 */ 1517 U8 LUN[8]; /*0x08 */ 1518 U32 Reserved1; /*0x10 */ 1519 U32 Reserved2; /*0x14 */ 1520 } MPI2_BOOT_DEVICE_DEVICE_NAME, 1521 *PTR_MPI2_BOOT_DEVICE_DEVICE_NAME, 1522 Mpi2BootDeviceDeviceName_t, 1523 *pMpi2BootDeviceDeviceName_t; 1524 1525 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE { 1526 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1527 MPI2_BOOT_DEVICE_SAS_WWID SasWwid; 1528 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1529 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName; 1530 } MPI2_BIOSPAGE2_BOOT_DEVICE, 1531 *PTR_MPI2_BIOSPAGE2_BOOT_DEVICE, 1532 Mpi2BiosPage2BootDevice_t, 1533 *pMpi2BiosPage2BootDevice_t; 1534 1535 typedef struct _MPI2_CONFIG_PAGE_BIOS_2 { 1536 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1537 U32 Reserved1; /*0x04 */ 1538 U32 Reserved2; /*0x08 */ 1539 U32 Reserved3; /*0x0C */ 1540 U32 Reserved4; /*0x10 */ 1541 U32 Reserved5; /*0x14 */ 1542 U32 Reserved6; /*0x18 */ 1543 U8 ReqBootDeviceForm; /*0x1C */ 1544 U8 Reserved7; /*0x1D */ 1545 U16 Reserved8; /*0x1E */ 1546 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /*0x20 */ 1547 U8 ReqAltBootDeviceForm; /*0x38 */ 1548 U8 Reserved9; /*0x39 */ 1549 U16 Reserved10; /*0x3A */ 1550 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /*0x3C */ 1551 U8 CurrentBootDeviceForm; /*0x58 */ 1552 U8 Reserved11; /*0x59 */ 1553 U16 Reserved12; /*0x5A */ 1554 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /*0x58 */ 1555 } MPI2_CONFIG_PAGE_BIOS_2, *PTR_MPI2_CONFIG_PAGE_BIOS_2, 1556 Mpi2BiosPage2_t, *pMpi2BiosPage2_t; 1557 1558 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04) 1559 1560 /*values for BIOS Page 2 BootDeviceForm fields */ 1561 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F) 1562 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00) 1563 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05) 1564 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1565 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07) 1566 1567 1568 /*BIOS Page 3 */ 1569 1570 #define MPI2_BIOSPAGE3_NUM_ADAPTER (4) 1571 1572 typedef struct _MPI2_ADAPTER_INFO { 1573 U8 PciBusNumber; /*0x00 */ 1574 U8 PciDeviceAndFunctionNumber; /*0x01 */ 1575 U16 AdapterFlags; /*0x02 */ 1576 } MPI2_ADAPTER_INFO, *PTR_MPI2_ADAPTER_INFO, 1577 Mpi2AdapterInfo_t, *pMpi2AdapterInfo_t; 1578 1579 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 1580 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 1581 1582 typedef struct _MPI2_ADAPTER_ORDER_AUX { 1583 U64 WWID; /* 0x00 */ 1584 U32 Reserved1; /* 0x08 */ 1585 U32 Reserved2; /* 0x0C */ 1586 } MPI2_ADAPTER_ORDER_AUX, *PTR_MPI2_ADAPTER_ORDER_AUX, 1587 Mpi2AdapterOrderAux_t, *pMpi2AdapterOrderAux_t; 1588 1589 1590 typedef struct _MPI2_CONFIG_PAGE_BIOS_3 { 1591 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1592 U32 GlobalFlags; /*0x04 */ 1593 U32 BiosVersion; /*0x08 */ 1594 MPI2_ADAPTER_INFO AdapterOrder[MPI2_BIOSPAGE3_NUM_ADAPTER]; 1595 U32 Reserved1; /*0x1C */ 1596 MPI2_ADAPTER_ORDER_AUX AdapterOrderAux[MPI2_BIOSPAGE3_NUM_ADAPTER]; 1597 } MPI2_CONFIG_PAGE_BIOS_3, 1598 *PTR_MPI2_CONFIG_PAGE_BIOS_3, 1599 Mpi2BiosPage3_t, *pMpi2BiosPage3_t; 1600 1601 #define MPI2_BIOSPAGE3_PAGEVERSION (0x01) 1602 1603 /*values for BIOS Page 3 GlobalFlags */ 1604 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) 1605 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004) 1606 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010) 1607 1608 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 1609 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 1610 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020) 1611 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 1612 1613 1614 /*BIOS Page 4 */ 1615 1616 /* 1617 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1618 *one and check the value returned for NumPhys at runtime. 1619 */ 1620 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES 1621 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1) 1622 #endif 1623 1624 typedef struct _MPI2_BIOS4_ENTRY { 1625 U64 ReassignmentWWID; /*0x00 */ 1626 U64 ReassignmentDeviceName; /*0x08 */ 1627 } MPI2_BIOS4_ENTRY, *PTR_MPI2_BIOS4_ENTRY, 1628 Mpi2MBios4Entry_t, *pMpi2Bios4Entry_t; 1629 1630 typedef struct _MPI2_CONFIG_PAGE_BIOS_4 { 1631 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1632 U8 NumPhys; /*0x04 */ 1633 U8 Reserved1; /*0x05 */ 1634 U16 Reserved2; /*0x06 */ 1635 MPI2_BIOS4_ENTRY 1636 Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /*0x08 */ 1637 } MPI2_CONFIG_PAGE_BIOS_4, *PTR_MPI2_CONFIG_PAGE_BIOS_4, 1638 Mpi2BiosPage4_t, *pMpi2BiosPage4_t; 1639 1640 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01) 1641 1642 1643 /**************************************************************************** 1644 * RAID Volume Config Pages 1645 ****************************************************************************/ 1646 1647 /*RAID Volume Page 0 */ 1648 1649 typedef struct _MPI2_RAIDVOL0_PHYS_DISK { 1650 U8 RAIDSetNum; /*0x00 */ 1651 U8 PhysDiskMap; /*0x01 */ 1652 U8 PhysDiskNum; /*0x02 */ 1653 U8 Reserved; /*0x03 */ 1654 } MPI2_RAIDVOL0_PHYS_DISK, *PTR_MPI2_RAIDVOL0_PHYS_DISK, 1655 Mpi2RaidVol0PhysDisk_t, *pMpi2RaidVol0PhysDisk_t; 1656 1657 /*defines for the PhysDiskMap field */ 1658 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1659 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1660 1661 typedef struct _MPI2_RAIDVOL0_SETTINGS { 1662 U16 Settings; /*0x00 */ 1663 U8 HotSparePool; /*0x01 */ 1664 U8 Reserved; /*0x02 */ 1665 } MPI2_RAIDVOL0_SETTINGS, *PTR_MPI2_RAIDVOL0_SETTINGS, 1666 Mpi2RaidVol0Settings_t, 1667 *pMpi2RaidVol0Settings_t; 1668 1669 /*RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1670 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01) 1671 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02) 1672 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04) 1673 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08) 1674 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10) 1675 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20) 1676 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40) 1677 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80) 1678 1679 /*RAID Volume Page 0 VolumeSettings defines */ 1680 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008) 1681 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004) 1682 1683 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003) 1684 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000) 1685 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001) 1686 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002) 1687 1688 /* 1689 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1690 *one and check the value returned for NumPhysDisks at runtime. 1691 */ 1692 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX 1693 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 1694 #endif 1695 1696 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 { 1697 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1698 U16 DevHandle; /*0x04 */ 1699 U8 VolumeState; /*0x06 */ 1700 U8 VolumeType; /*0x07 */ 1701 U32 VolumeStatusFlags; /*0x08 */ 1702 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /*0x0C */ 1703 U64 MaxLBA; /*0x10 */ 1704 U32 StripeSize; /*0x18 */ 1705 U16 BlockSize; /*0x1C */ 1706 U16 Reserved1; /*0x1E */ 1707 U8 SupportedPhysDisks;/*0x20 */ 1708 U8 ResyncRate; /*0x21 */ 1709 U16 DataScrubDuration; /*0x22 */ 1710 U8 NumPhysDisks; /*0x24 */ 1711 U8 Reserved2; /*0x25 */ 1712 U8 Reserved3; /*0x26 */ 1713 U8 InactiveStatus; /*0x27 */ 1714 MPI2_RAIDVOL0_PHYS_DISK 1715 PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /*0x28 */ 1716 } MPI2_CONFIG_PAGE_RAID_VOL_0, 1717 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_0, 1718 Mpi2RaidVolPage0_t, *pMpi2RaidVolPage0_t; 1719 1720 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A) 1721 1722 /*values for RAID VolumeState */ 1723 #define MPI2_RAID_VOL_STATE_MISSING (0x00) 1724 #define MPI2_RAID_VOL_STATE_FAILED (0x01) 1725 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02) 1726 #define MPI2_RAID_VOL_STATE_ONLINE (0x03) 1727 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04) 1728 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05) 1729 1730 /*values for RAID VolumeType */ 1731 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00) 1732 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01) 1733 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02) 1734 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05) 1735 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF) 1736 1737 /*values for RAID Volume Page 0 VolumeStatusFlags field */ 1738 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000) 1739 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000) 1740 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000) 1741 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000) 1742 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000) 1743 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000) 1744 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000) 1745 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000) 1746 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000) 1747 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000) 1748 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080) 1749 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040) 1750 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020) 1751 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000) 1752 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010) 1753 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008) 1754 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004) 1755 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002) 1756 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001) 1757 1758 /*values for RAID Volume Page 0 SupportedPhysDisks field */ 1759 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08) 1760 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04) 1761 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02) 1762 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01) 1763 1764 /*values for RAID Volume Page 0 InactiveStatus field */ 1765 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 1766 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 1767 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 1768 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 1769 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 1770 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 1771 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 1772 1773 1774 /*RAID Volume Page 1 */ 1775 1776 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 { 1777 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1778 U16 DevHandle; /*0x04 */ 1779 U16 Reserved0; /*0x06 */ 1780 U8 GUID[24]; /*0x08 */ 1781 U8 Name[16]; /*0x20 */ 1782 U64 WWID; /*0x30 */ 1783 U32 Reserved1; /*0x38 */ 1784 U32 Reserved2; /*0x3C */ 1785 } MPI2_CONFIG_PAGE_RAID_VOL_1, 1786 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_1, 1787 Mpi2RaidVolPage1_t, *pMpi2RaidVolPage1_t; 1788 1789 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03) 1790 1791 1792 /**************************************************************************** 1793 * RAID Physical Disk Config Pages 1794 ****************************************************************************/ 1795 1796 /*RAID Physical Disk Page 0 */ 1797 1798 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS { 1799 U16 Reserved1; /*0x00 */ 1800 U8 HotSparePool; /*0x02 */ 1801 U8 Reserved2; /*0x03 */ 1802 } MPI2_RAIDPHYSDISK0_SETTINGS, 1803 *PTR_MPI2_RAIDPHYSDISK0_SETTINGS, 1804 Mpi2RaidPhysDisk0Settings_t, 1805 *pMpi2RaidPhysDisk0Settings_t; 1806 1807 /*use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */ 1808 1809 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA { 1810 U8 VendorID[8]; /*0x00 */ 1811 U8 ProductID[16]; /*0x08 */ 1812 U8 ProductRevLevel[4]; /*0x18 */ 1813 U8 SerialNum[32]; /*0x1C */ 1814 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1815 *PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1816 Mpi2RaidPhysDisk0InquiryData_t, 1817 *pMpi2RaidPhysDisk0InquiryData_t; 1818 1819 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 { 1820 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1821 U16 DevHandle; /*0x04 */ 1822 U8 Reserved1; /*0x06 */ 1823 U8 PhysDiskNum; /*0x07 */ 1824 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /*0x08 */ 1825 U32 Reserved2; /*0x0C */ 1826 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /*0x10 */ 1827 U32 Reserved3; /*0x4C */ 1828 U8 PhysDiskState; /*0x50 */ 1829 U8 OfflineReason; /*0x51 */ 1830 U8 IncompatibleReason; /*0x52 */ 1831 U8 PhysDiskAttributes; /*0x53 */ 1832 U32 PhysDiskStatusFlags;/*0x54 */ 1833 U64 DeviceMaxLBA; /*0x58 */ 1834 U64 HostMaxLBA; /*0x60 */ 1835 U64 CoercedMaxLBA; /*0x68 */ 1836 U16 BlockSize; /*0x70 */ 1837 U16 Reserved5; /*0x72 */ 1838 U32 Reserved6; /*0x74 */ 1839 } MPI2_CONFIG_PAGE_RD_PDISK_0, 1840 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_0, 1841 Mpi2RaidPhysDiskPage0_t, 1842 *pMpi2RaidPhysDiskPage0_t; 1843 1844 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05) 1845 1846 /*PhysDiskState defines */ 1847 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00) 1848 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01) 1849 #define MPI2_RAID_PD_STATE_OFFLINE (0x02) 1850 #define MPI2_RAID_PD_STATE_ONLINE (0x03) 1851 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04) 1852 #define MPI2_RAID_PD_STATE_DEGRADED (0x05) 1853 #define MPI2_RAID_PD_STATE_REBUILDING (0x06) 1854 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07) 1855 1856 /*OfflineReason defines */ 1857 #define MPI2_PHYSDISK0_ONLINE (0x00) 1858 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01) 1859 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03) 1860 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04) 1861 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05) 1862 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06) 1863 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF) 1864 1865 /*IncompatibleReason defines */ 1866 #define MPI2_PHYSDISK0_COMPATIBLE (0x00) 1867 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01) 1868 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02) 1869 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03) 1870 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04) 1871 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05) 1872 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06) 1873 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF) 1874 1875 /*PhysDiskAttributes defines */ 1876 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C) 1877 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08) 1878 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04) 1879 1880 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03) 1881 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02) 1882 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01) 1883 1884 /*PhysDiskStatusFlags defines */ 1885 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040) 1886 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020) 1887 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010) 1888 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000) 1889 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008) 1890 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004) 1891 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002) 1892 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001) 1893 1894 1895 /*RAID Physical Disk Page 1 */ 1896 1897 /* 1898 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1899 *one and check the value returned for NumPhysDiskPaths at runtime. 1900 */ 1901 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX 1902 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1) 1903 #endif 1904 1905 typedef struct _MPI2_RAIDPHYSDISK1_PATH { 1906 U16 DevHandle; /*0x00 */ 1907 U16 Reserved1; /*0x02 */ 1908 U64 WWID; /*0x04 */ 1909 U64 OwnerWWID; /*0x0C */ 1910 U8 OwnerIdentifier; /*0x14 */ 1911 U8 Reserved2; /*0x15 */ 1912 U16 Flags; /*0x16 */ 1913 } MPI2_RAIDPHYSDISK1_PATH, *PTR_MPI2_RAIDPHYSDISK1_PATH, 1914 Mpi2RaidPhysDisk1Path_t, 1915 *pMpi2RaidPhysDisk1Path_t; 1916 1917 /*RAID Physical Disk Page 1 Physical Disk Path Flags field defines */ 1918 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004) 1919 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 1920 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 1921 1922 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 { 1923 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1924 U8 NumPhysDiskPaths; /*0x04 */ 1925 U8 PhysDiskNum; /*0x05 */ 1926 U16 Reserved1; /*0x06 */ 1927 U32 Reserved2; /*0x08 */ 1928 MPI2_RAIDPHYSDISK1_PATH 1929 PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/*0x0C */ 1930 } MPI2_CONFIG_PAGE_RD_PDISK_1, 1931 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_1, 1932 Mpi2RaidPhysDiskPage1_t, 1933 *pMpi2RaidPhysDiskPage1_t; 1934 1935 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02) 1936 1937 1938 /**************************************************************************** 1939 * values for fields used by several types of SAS Config Pages 1940 ****************************************************************************/ 1941 1942 /*values for NegotiatedLinkRates fields */ 1943 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0) 1944 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4) 1945 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 1946 /*link rates used for Negotiated Physical and Logical Link Rate */ 1947 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 1948 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 1949 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 1950 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 1951 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 1952 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 1953 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 1954 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08) 1955 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09) 1956 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A) 1957 #define MPI25_SAS_NEG_LINK_RATE_12_0 (0x0B) 1958 1959 1960 /*values for AttachedPhyInfo fields */ 1961 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 1962 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 1963 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 1964 1965 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F) 1966 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 1967 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 1968 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 1969 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 1970 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 1971 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 1972 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 1973 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 1974 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 1975 1976 1977 /*values for PhyInfo fields */ 1978 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000) 1979 1980 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 1981 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27) 1982 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000) 1983 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000) 1984 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000) 1985 1986 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000) 1987 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000) 1988 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000) 1989 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 1990 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000) 1991 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 1992 1993 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000) 1994 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 1995 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 1996 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 1997 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 1998 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 1999 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 2000 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 2001 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 2002 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 2003 2004 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000) 2005 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 2006 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 2007 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 2008 2009 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 2010 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 2011 2012 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 2013 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000) 2014 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 2015 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020) 2016 2017 2018 /*values for SAS ProgrammedLinkRate fields */ 2019 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0) 2020 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 2021 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80) 2022 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90) 2023 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0) 2024 #define MPI25_SAS_PRATE_MAX_RATE_12_0 (0xB0) 2025 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F) 2026 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 2027 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08) 2028 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09) 2029 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A) 2030 #define MPI25_SAS_PRATE_MIN_RATE_12_0 (0x0B) 2031 2032 2033 /*values for SAS HwLinkRate fields */ 2034 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0) 2035 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80) 2036 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90) 2037 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0) 2038 #define MPI25_SAS_HWRATE_MAX_RATE_12_0 (0xB0) 2039 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F) 2040 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08) 2041 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09) 2042 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A) 2043 #define MPI25_SAS_HWRATE_MIN_RATE_12_0 (0x0B) 2044 2045 2046 2047 /**************************************************************************** 2048 * SAS IO Unit Config Pages 2049 ****************************************************************************/ 2050 2051 /*SAS IO Unit Page 0 */ 2052 2053 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA { 2054 U8 Port; /*0x00 */ 2055 U8 PortFlags; /*0x01 */ 2056 U8 PhyFlags; /*0x02 */ 2057 U8 NegotiatedLinkRate; /*0x03 */ 2058 U32 ControllerPhyDeviceInfo;/*0x04 */ 2059 U16 AttachedDevHandle; /*0x08 */ 2060 U16 ControllerDevHandle; /*0x0A */ 2061 U32 DiscoveryStatus; /*0x0C */ 2062 U32 Reserved; /*0x10 */ 2063 } MPI2_SAS_IO_UNIT0_PHY_DATA, 2064 *PTR_MPI2_SAS_IO_UNIT0_PHY_DATA, 2065 Mpi2SasIOUnit0PhyData_t, 2066 *pMpi2SasIOUnit0PhyData_t; 2067 2068 /* 2069 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2070 *one and check the value returned for NumPhys at runtime. 2071 */ 2072 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX 2073 #define MPI2_SAS_IOUNIT0_PHY_MAX (1) 2074 #endif 2075 2076 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 { 2077 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2078 U32 Reserved1;/*0x08 */ 2079 U8 NumPhys; /*0x0C */ 2080 U8 Reserved2;/*0x0D */ 2081 U16 Reserved3;/*0x0E */ 2082 MPI2_SAS_IO_UNIT0_PHY_DATA 2083 PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /*0x10 */ 2084 } MPI2_CONFIG_PAGE_SASIOUNIT_0, 2085 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0, 2086 Mpi2SasIOUnitPage0_t, *pMpi2SasIOUnitPage0_t; 2087 2088 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05) 2089 2090 /*values for SAS IO Unit Page 0 PortFlags */ 2091 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08) 2092 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) 2093 2094 /*values for SAS IO Unit Page 0 PhyFlags */ 2095 #define MPI2_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2096 #define MPI2_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2097 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) 2098 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 2099 2100 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2101 2102 /*see mpi2_sas.h for values for 2103 *SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 2104 2105 /*values for SAS IO Unit Page 0 DiscoveryStatus */ 2106 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2107 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2108 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000) 2109 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2110 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2111 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2112 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2113 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 2114 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2115 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 2116 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400) 2117 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 2118 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 2119 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 2120 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 2121 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2122 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010) 2123 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 2124 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2125 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001) 2126 2127 2128 /*SAS IO Unit Page 1 */ 2129 2130 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA { 2131 U8 Port; /*0x00 */ 2132 U8 PortFlags; /*0x01 */ 2133 U8 PhyFlags; /*0x02 */ 2134 U8 MaxMinLinkRate; /*0x03 */ 2135 U32 ControllerPhyDeviceInfo; /*0x04 */ 2136 U16 MaxTargetPortConnectTime; /*0x08 */ 2137 U16 Reserved1; /*0x0A */ 2138 } MPI2_SAS_IO_UNIT1_PHY_DATA, 2139 *PTR_MPI2_SAS_IO_UNIT1_PHY_DATA, 2140 Mpi2SasIOUnit1PhyData_t, 2141 *pMpi2SasIOUnit1PhyData_t; 2142 2143 /* 2144 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2145 *one and check the value returned for NumPhys at runtime. 2146 */ 2147 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX 2148 #define MPI2_SAS_IOUNIT1_PHY_MAX (1) 2149 #endif 2150 2151 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 { 2152 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2153 U16 2154 ControlFlags; /*0x08 */ 2155 U16 2156 SASNarrowMaxQueueDepth; /*0x0A */ 2157 U16 2158 AdditionalControlFlags; /*0x0C */ 2159 U16 2160 SASWideMaxQueueDepth; /*0x0E */ 2161 U8 2162 NumPhys; /*0x10 */ 2163 U8 2164 SATAMaxQDepth; /*0x11 */ 2165 U8 2166 ReportDeviceMissingDelay; /*0x12 */ 2167 U8 2168 IODeviceMissingDelay; /*0x13 */ 2169 MPI2_SAS_IO_UNIT1_PHY_DATA 2170 PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /*0x14 */ 2171 } MPI2_CONFIG_PAGE_SASIOUNIT_1, 2172 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1, 2173 Mpi2SasIOUnitPage1_t, *pMpi2SasIOUnitPage1_t; 2174 2175 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09) 2176 2177 /*values for SAS IO Unit Page 1 ControlFlags */ 2178 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 2179 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 2180 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) 2181 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 2182 2183 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 2184 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 2185 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0) 2186 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1) 2187 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2) 2188 2189 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 2190 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 2191 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 2192 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 2193 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 2194 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 2195 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 2196 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) 2197 2198 /*values for SAS IO Unit Page 1 AdditionalControlFlags */ 2199 #define MPI2_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100) 2200 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 2201 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 2202 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 2203 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 2204 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 2205 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 2206 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 2207 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 2208 2209 /*defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 2210 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 2211 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 2212 2213 /*values for SAS IO Unit Page 1 PortFlags */ 2214 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2215 2216 /*values for SAS IO Unit Page 1 PhyFlags */ 2217 #define MPI2_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2218 #define MPI2_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2219 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) 2220 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 2221 2222 /*values for SAS IO Unit Page 1 MaxMinLinkRate */ 2223 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) 2224 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) 2225 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) 2226 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) 2227 #define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0) 2228 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) 2229 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) 2230 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) 2231 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) 2232 #define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B) 2233 2234 /*see mpi2_sas.h for values for 2235 *SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 2236 2237 2238 /*SAS IO Unit Page 4 (for MPI v2.5 and earlier) */ 2239 2240 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP { 2241 U8 MaxTargetSpinup; /*0x00 */ 2242 U8 SpinupDelay; /*0x01 */ 2243 U8 SpinupFlags; /*0x02 */ 2244 U8 Reserved1; /*0x03 */ 2245 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, 2246 *PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP, 2247 Mpi2SasIOUnit4SpinupGroup_t, 2248 *pMpi2SasIOUnit4SpinupGroup_t; 2249 /*defines for SAS IO Unit Page 4 SpinupFlags */ 2250 #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01) 2251 2252 2253 /* 2254 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2255 *one and check the value returned for NumPhys at runtime. 2256 */ 2257 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX 2258 #define MPI2_SAS_IOUNIT4_PHY_MAX (4) 2259 #endif 2260 2261 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 { 2262 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header;/*0x00 */ 2263 MPI2_SAS_IOUNIT4_SPINUP_GROUP 2264 SpinupGroupParameters[4]; /*0x08 */ 2265 U32 2266 Reserved1; /*0x18 */ 2267 U32 2268 Reserved2; /*0x1C */ 2269 U32 2270 Reserved3; /*0x20 */ 2271 U8 2272 BootDeviceWaitTime; /*0x24 */ 2273 U8 2274 Reserved4; /*0x25 */ 2275 U16 2276 Reserved5; /*0x26 */ 2277 U8 2278 NumPhys; /*0x28 */ 2279 U8 2280 PEInitialSpinupDelay; /*0x29 */ 2281 U8 2282 PEReplyDelay; /*0x2A */ 2283 U8 2284 Flags; /*0x2B */ 2285 U8 2286 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /*0x2C */ 2287 } MPI2_CONFIG_PAGE_SASIOUNIT_4, 2288 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4, 2289 Mpi2SasIOUnitPage4_t, *pMpi2SasIOUnitPage4_t; 2290 2291 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02) 2292 2293 /*defines for Flags field */ 2294 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01) 2295 2296 /*defines for PHY field */ 2297 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03) 2298 2299 2300 /*SAS IO Unit Page 5 */ 2301 2302 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS { 2303 U8 ControlFlags; /*0x00 */ 2304 U8 PortWidthModGroup; /*0x01 */ 2305 U16 InactivityTimerExponent; /*0x02 */ 2306 U8 SATAPartialTimeout; /*0x04 */ 2307 U8 Reserved2; /*0x05 */ 2308 U8 SATASlumberTimeout; /*0x06 */ 2309 U8 Reserved3; /*0x07 */ 2310 U8 SASPartialTimeout; /*0x08 */ 2311 U8 Reserved4; /*0x09 */ 2312 U8 SASSlumberTimeout; /*0x0A */ 2313 U8 Reserved5; /*0x0B */ 2314 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2315 *PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2316 Mpi2SasIOUnit5PhyPmSettings_t, 2317 *pMpi2SasIOUnit5PhyPmSettings_t; 2318 2319 /*defines for ControlFlags field */ 2320 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08) 2321 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04) 2322 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02) 2323 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01) 2324 2325 /*defines for PortWidthModeGroup field */ 2326 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF) 2327 2328 /*defines for InactivityTimerExponent field */ 2329 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000) 2330 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12) 2331 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700) 2332 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8) 2333 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070) 2334 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4) 2335 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007) 2336 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0) 2337 2338 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7) 2339 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6) 2340 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5) 2341 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4) 2342 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3) 2343 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2) 2344 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1) 2345 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0) 2346 2347 /* 2348 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2349 *one and check the value returned for NumPhys at runtime. 2350 */ 2351 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX 2352 #define MPI2_SAS_IOUNIT5_PHY_MAX (1) 2353 #endif 2354 2355 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 { 2356 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2357 U8 NumPhys; /*0x08 */ 2358 U8 Reserved1;/*0x09 */ 2359 U16 Reserved2;/*0x0A */ 2360 U32 Reserved3;/*0x0C */ 2361 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS 2362 SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX];/*0x10 */ 2363 } MPI2_CONFIG_PAGE_SASIOUNIT_5, 2364 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5, 2365 Mpi2SasIOUnitPage5_t, *pMpi2SasIOUnitPage5_t; 2366 2367 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01) 2368 2369 2370 /*SAS IO Unit Page 6 */ 2371 2372 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS { 2373 U8 CurrentStatus; /*0x00 */ 2374 U8 CurrentModulation; /*0x01 */ 2375 U8 CurrentUtilization; /*0x02 */ 2376 U8 Reserved1; /*0x03 */ 2377 U32 Reserved2; /*0x04 */ 2378 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2379 *PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2380 Mpi2SasIOUnit6PortWidthModGroupStatus_t, 2381 *pMpi2SasIOUnit6PortWidthModGroupStatus_t; 2382 2383 /*defines for CurrentStatus field */ 2384 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00) 2385 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01) 2386 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02) 2387 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03) 2388 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04) 2389 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05) 2390 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06) 2391 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07) 2392 2393 /*defines for CurrentModulation field */ 2394 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00) 2395 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01) 2396 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02) 2397 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03) 2398 2399 /* 2400 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2401 *one and check the value returned for NumGroups at runtime. 2402 */ 2403 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX 2404 #define MPI2_SAS_IOUNIT6_GROUP_MAX (1) 2405 #endif 2406 2407 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 { 2408 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2409 U32 Reserved1; /*0x08 */ 2410 U32 Reserved2; /*0x0C */ 2411 U8 NumGroups; /*0x10 */ 2412 U8 Reserved3; /*0x11 */ 2413 U16 Reserved4; /*0x12 */ 2414 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 2415 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /*0x14 */ 2416 } MPI2_CONFIG_PAGE_SASIOUNIT_6, 2417 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6, 2418 Mpi2SasIOUnitPage6_t, *pMpi2SasIOUnitPage6_t; 2419 2420 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00) 2421 2422 2423 /*SAS IO Unit Page 7 */ 2424 2425 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS { 2426 U8 Flags; /*0x00 */ 2427 U8 Reserved1; /*0x01 */ 2428 U16 Reserved2; /*0x02 */ 2429 U8 Threshold75Pct; /*0x04 */ 2430 U8 Threshold50Pct; /*0x05 */ 2431 U8 Threshold25Pct; /*0x06 */ 2432 U8 Reserved3; /*0x07 */ 2433 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2434 *PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2435 Mpi2SasIOUnit7PortWidthModGroupSettings_t, 2436 *pMpi2SasIOUnit7PortWidthModGroupSettings_t; 2437 2438 /*defines for Flags field */ 2439 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01) 2440 2441 2442 /* 2443 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2444 *one and check the value returned for NumGroups at runtime. 2445 */ 2446 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX 2447 #define MPI2_SAS_IOUNIT7_GROUP_MAX (1) 2448 #endif 2449 2450 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 { 2451 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2452 U8 SamplingInterval; /*0x08 */ 2453 U8 WindowLength; /*0x09 */ 2454 U16 Reserved1; /*0x0A */ 2455 U32 Reserved2; /*0x0C */ 2456 U32 Reserved3; /*0x10 */ 2457 U8 NumGroups; /*0x14 */ 2458 U8 Reserved4; /*0x15 */ 2459 U16 Reserved5; /*0x16 */ 2460 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2461 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX];/*0x18 */ 2462 } MPI2_CONFIG_PAGE_SASIOUNIT_7, 2463 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7, 2464 Mpi2SasIOUnitPage7_t, *pMpi2SasIOUnitPage7_t; 2465 2466 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00) 2467 2468 2469 /*SAS IO Unit Page 8 */ 2470 2471 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 { 2472 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2473 Header; /*0x00 */ 2474 U32 2475 Reserved1; /*0x08 */ 2476 U32 2477 PowerManagementCapabilities; /*0x0C */ 2478 U8 2479 TxRxSleepStatus; /*0x10 */ 2480 U8 2481 Reserved2; /*0x11 */ 2482 U16 2483 Reserved3; /*0x12 */ 2484 } MPI2_CONFIG_PAGE_SASIOUNIT_8, 2485 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8, 2486 Mpi2SasIOUnitPage8_t, *pMpi2SasIOUnitPage8_t; 2487 2488 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00) 2489 2490 /*defines for PowerManagementCapabilities field */ 2491 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000) 2492 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800) 2493 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400) 2494 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200) 2495 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100) 2496 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010) 2497 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008) 2498 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004) 2499 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002) 2500 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001) 2501 2502 /*defines for TxRxSleepStatus field */ 2503 #define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED (0x00) 2504 #define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED (0x01) 2505 #define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE (0x02) 2506 #define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN (0x03) 2507 2508 2509 2510 /*SAS IO Unit Page 16 */ 2511 2512 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 { 2513 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2514 Header; /*0x00 */ 2515 U64 2516 TimeStamp; /*0x08 */ 2517 U32 2518 Reserved1; /*0x10 */ 2519 U32 2520 Reserved2; /*0x14 */ 2521 U32 2522 FastPathPendedRequests; /*0x18 */ 2523 U32 2524 FastPathUnPendedRequests; /*0x1C */ 2525 U32 2526 FastPathHostRequestStarts; /*0x20 */ 2527 U32 2528 FastPathFirmwareRequestStarts; /*0x24 */ 2529 U32 2530 FastPathHostCompletions; /*0x28 */ 2531 U32 2532 FastPathFirmwareCompletions; /*0x2C */ 2533 U32 2534 NonFastPathRequestStarts; /*0x30 */ 2535 U32 2536 NonFastPathHostCompletions; /*0x30 */ 2537 } MPI2_CONFIG_PAGE_SASIOUNIT16, 2538 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT16, 2539 Mpi2SasIOUnitPage16_t, *pMpi2SasIOUnitPage16_t; 2540 2541 #define MPI2_SASIOUNITPAGE16_PAGEVERSION (0x00) 2542 2543 2544 /**************************************************************************** 2545 * SAS Expander Config Pages 2546 ****************************************************************************/ 2547 2548 /*SAS Expander Page 0 */ 2549 2550 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 { 2551 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2552 Header; /*0x00 */ 2553 U8 2554 PhysicalPort; /*0x08 */ 2555 U8 2556 ReportGenLength; /*0x09 */ 2557 U16 2558 EnclosureHandle; /*0x0A */ 2559 U64 2560 SASAddress; /*0x0C */ 2561 U32 2562 DiscoveryStatus; /*0x14 */ 2563 U16 2564 DevHandle; /*0x18 */ 2565 U16 2566 ParentDevHandle; /*0x1A */ 2567 U16 2568 ExpanderChangeCount; /*0x1C */ 2569 U16 2570 ExpanderRouteIndexes; /*0x1E */ 2571 U8 2572 NumPhys; /*0x20 */ 2573 U8 2574 SASLevel; /*0x21 */ 2575 U16 2576 Flags; /*0x22 */ 2577 U16 2578 STPBusInactivityTimeLimit; /*0x24 */ 2579 U16 2580 STPMaxConnectTimeLimit; /*0x26 */ 2581 U16 2582 STP_SMP_NexusLossTime; /*0x28 */ 2583 U16 2584 MaxNumRoutedSasAddresses; /*0x2A */ 2585 U64 2586 ActiveZoneManagerSASAddress;/*0x2C */ 2587 U16 2588 ZoneLockInactivityLimit; /*0x34 */ 2589 U16 2590 Reserved1; /*0x36 */ 2591 U8 2592 TimeToReducedFunc; /*0x38 */ 2593 U8 2594 InitialTimeToReducedFunc; /*0x39 */ 2595 U8 2596 MaxReducedFuncTime; /*0x3A */ 2597 U8 2598 Reserved2; /*0x3B */ 2599 } MPI2_CONFIG_PAGE_EXPANDER_0, 2600 *PTR_MPI2_CONFIG_PAGE_EXPANDER_0, 2601 Mpi2ExpanderPage0_t, *pMpi2ExpanderPage0_t; 2602 2603 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06) 2604 2605 /*values for SAS Expander Page 0 DiscoveryStatus field */ 2606 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2607 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2608 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000) 2609 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2610 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2611 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2612 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2613 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000) 2614 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2615 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2616 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2617 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2618 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2619 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2620 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2621 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2622 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2623 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2624 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2625 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2626 2627 /*values for SAS Expander Page 0 Flags field */ 2628 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 2629 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 2630 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 2631 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 2632 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 2633 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 2634 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 2635 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 2636 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 2637 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 2638 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 2639 2640 2641 /*SAS Expander Page 1 */ 2642 2643 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 { 2644 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2645 Header; /*0x00 */ 2646 U8 2647 PhysicalPort; /*0x08 */ 2648 U8 2649 Reserved1; /*0x09 */ 2650 U16 2651 Reserved2; /*0x0A */ 2652 U8 2653 NumPhys; /*0x0C */ 2654 U8 2655 Phy; /*0x0D */ 2656 U16 2657 NumTableEntriesProgrammed; /*0x0E */ 2658 U8 2659 ProgrammedLinkRate; /*0x10 */ 2660 U8 2661 HwLinkRate; /*0x11 */ 2662 U16 2663 AttachedDevHandle; /*0x12 */ 2664 U32 2665 PhyInfo; /*0x14 */ 2666 U32 2667 AttachedDeviceInfo; /*0x18 */ 2668 U16 2669 ExpanderDevHandle; /*0x1C */ 2670 U8 2671 ChangeCount; /*0x1E */ 2672 U8 2673 NegotiatedLinkRate; /*0x1F */ 2674 U8 2675 PhyIdentifier; /*0x20 */ 2676 U8 2677 AttachedPhyIdentifier; /*0x21 */ 2678 U8 2679 Reserved3; /*0x22 */ 2680 U8 2681 DiscoveryInfo; /*0x23 */ 2682 U32 2683 AttachedPhyInfo; /*0x24 */ 2684 U8 2685 ZoneGroup; /*0x28 */ 2686 U8 2687 SelfConfigStatus; /*0x29 */ 2688 U16 2689 Reserved4; /*0x2A */ 2690 } MPI2_CONFIG_PAGE_EXPANDER_1, 2691 *PTR_MPI2_CONFIG_PAGE_EXPANDER_1, 2692 Mpi2ExpanderPage1_t, *pMpi2ExpanderPage1_t; 2693 2694 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02) 2695 2696 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2697 2698 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2699 2700 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2701 2702 /*see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines 2703 *used for the AttachedDeviceInfo field */ 2704 2705 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2706 2707 /*values for SAS Expander Page 1 DiscoveryInfo field */ 2708 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2709 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2710 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2711 2712 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2713 2714 2715 /**************************************************************************** 2716 * SAS Device Config Pages 2717 ****************************************************************************/ 2718 2719 /*SAS Device Page 0 */ 2720 2721 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 { 2722 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2723 Header; /*0x00 */ 2724 U16 2725 Slot; /*0x08 */ 2726 U16 2727 EnclosureHandle; /*0x0A */ 2728 U64 2729 SASAddress; /*0x0C */ 2730 U16 2731 ParentDevHandle; /*0x14 */ 2732 U8 2733 PhyNum; /*0x16 */ 2734 U8 2735 AccessStatus; /*0x17 */ 2736 U16 2737 DevHandle; /*0x18 */ 2738 U8 2739 AttachedPhyIdentifier; /*0x1A */ 2740 U8 2741 ZoneGroup; /*0x1B */ 2742 U32 2743 DeviceInfo; /*0x1C */ 2744 U16 2745 Flags; /*0x20 */ 2746 U8 2747 PhysicalPort; /*0x22 */ 2748 U8 2749 MaxPortConnections; /*0x23 */ 2750 U64 2751 DeviceName; /*0x24 */ 2752 U8 2753 PortGroups; /*0x2C */ 2754 U8 2755 DmaGroup; /*0x2D */ 2756 U8 2757 ControlGroup; /*0x2E */ 2758 U8 2759 EnclosureLevel; /*0x2F */ 2760 U32 2761 ConnectorName[4]; /*0x30 */ 2762 U32 2763 Reserved3; /*0x34 */ 2764 } MPI2_CONFIG_PAGE_SAS_DEV_0, 2765 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_0, 2766 Mpi2SasDevicePage0_t, 2767 *pMpi2SasDevicePage0_t; 2768 2769 #define MPI2_SASDEVICE0_PAGEVERSION (0x09) 2770 2771 /*values for SAS Device Page 0 AccessStatus field */ 2772 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2773 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2774 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2775 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2776 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2777 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05) 2778 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06) 2779 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07) 2780 /*specific values for SATA Init failures */ 2781 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2782 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2783 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2784 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2785 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2786 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2787 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2788 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2789 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2790 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2791 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2792 2793 /*see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2794 2795 /*values for SAS Device Page 0 Flags field */ 2796 #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000) 2797 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH (0x4000) 2798 #define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE (0x2000) 2799 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000) 2800 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800) 2801 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2802 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2803 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2804 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2805 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2806 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2807 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2808 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2809 #define MPI2_SAS_DEVICE0_FLAGS_PERSIST_CAPABLE (0x0004) 2810 #define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID (0x0002) 2811 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2812 2813 2814 /*SAS Device Page 1 */ 2815 2816 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 { 2817 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2818 Header; /*0x00 */ 2819 U32 2820 Reserved1; /*0x08 */ 2821 U64 2822 SASAddress; /*0x0C */ 2823 U32 2824 Reserved2; /*0x14 */ 2825 U16 2826 DevHandle; /*0x18 */ 2827 U16 2828 Reserved3; /*0x1A */ 2829 U8 2830 InitialRegDeviceFIS[20];/*0x1C */ 2831 } MPI2_CONFIG_PAGE_SAS_DEV_1, 2832 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_1, 2833 Mpi2SasDevicePage1_t, 2834 *pMpi2SasDevicePage1_t; 2835 2836 #define MPI2_SASDEVICE1_PAGEVERSION (0x01) 2837 2838 2839 /**************************************************************************** 2840 * SAS PHY Config Pages 2841 ****************************************************************************/ 2842 2843 /*SAS PHY Page 0 */ 2844 2845 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 { 2846 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2847 Header; /*0x00 */ 2848 U16 2849 OwnerDevHandle; /*0x08 */ 2850 U16 2851 Reserved1; /*0x0A */ 2852 U16 2853 AttachedDevHandle; /*0x0C */ 2854 U8 2855 AttachedPhyIdentifier; /*0x0E */ 2856 U8 2857 Reserved2; /*0x0F */ 2858 U32 2859 AttachedPhyInfo; /*0x10 */ 2860 U8 2861 ProgrammedLinkRate; /*0x14 */ 2862 U8 2863 HwLinkRate; /*0x15 */ 2864 U8 2865 ChangeCount; /*0x16 */ 2866 U8 2867 Flags; /*0x17 */ 2868 U32 2869 PhyInfo; /*0x18 */ 2870 U8 2871 NegotiatedLinkRate; /*0x1C */ 2872 U8 2873 Reserved3; /*0x1D */ 2874 U16 2875 Reserved4; /*0x1E */ 2876 } MPI2_CONFIG_PAGE_SAS_PHY_0, 2877 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_0, 2878 Mpi2SasPhyPage0_t, *pMpi2SasPhyPage0_t; 2879 2880 #define MPI2_SASPHY0_PAGEVERSION (0x03) 2881 2882 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2883 2884 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2885 2886 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2887 2888 /*values for SAS PHY Page 0 Flags field */ 2889 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 2890 2891 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2892 2893 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2894 2895 2896 /*SAS PHY Page 1 */ 2897 2898 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 { 2899 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2900 Header; /*0x00 */ 2901 U32 2902 Reserved1; /*0x08 */ 2903 U32 2904 InvalidDwordCount; /*0x0C */ 2905 U32 2906 RunningDisparityErrorCount; /*0x10 */ 2907 U32 2908 LossDwordSynchCount; /*0x14 */ 2909 U32 2910 PhyResetProblemCount; /*0x18 */ 2911 } MPI2_CONFIG_PAGE_SAS_PHY_1, 2912 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_1, 2913 Mpi2SasPhyPage1_t, *pMpi2SasPhyPage1_t; 2914 2915 #define MPI2_SASPHY1_PAGEVERSION (0x01) 2916 2917 2918 /*SAS PHY Page 2 */ 2919 2920 typedef struct _MPI2_SASPHY2_PHY_EVENT { 2921 U8 PhyEventCode; /*0x00 */ 2922 U8 Reserved1; /*0x01 */ 2923 U16 Reserved2; /*0x02 */ 2924 U32 PhyEventInfo; /*0x04 */ 2925 } MPI2_SASPHY2_PHY_EVENT, *PTR_MPI2_SASPHY2_PHY_EVENT, 2926 Mpi2SasPhy2PhyEvent_t, *pMpi2SasPhy2PhyEvent_t; 2927 2928 /*use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */ 2929 2930 2931 /* 2932 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2933 *one and check the value returned for NumPhyEvents at runtime. 2934 */ 2935 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX 2936 #define MPI2_SASPHY2_PHY_EVENT_MAX (1) 2937 #endif 2938 2939 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 { 2940 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2941 Header; /*0x00 */ 2942 U32 2943 Reserved1; /*0x08 */ 2944 U8 2945 NumPhyEvents; /*0x0C */ 2946 U8 2947 Reserved2; /*0x0D */ 2948 U16 2949 Reserved3; /*0x0E */ 2950 MPI2_SASPHY2_PHY_EVENT 2951 PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /*0x10 */ 2952 } MPI2_CONFIG_PAGE_SAS_PHY_2, 2953 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_2, 2954 Mpi2SasPhyPage2_t, 2955 *pMpi2SasPhyPage2_t; 2956 2957 #define MPI2_SASPHY2_PAGEVERSION (0x00) 2958 2959 2960 /*SAS PHY Page 3 */ 2961 2962 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG { 2963 U8 PhyEventCode; /*0x00 */ 2964 U8 Reserved1; /*0x01 */ 2965 U16 Reserved2; /*0x02 */ 2966 U8 CounterType; /*0x04 */ 2967 U8 ThresholdWindow; /*0x05 */ 2968 U8 TimeUnits; /*0x06 */ 2969 U8 Reserved3; /*0x07 */ 2970 U32 EventThreshold; /*0x08 */ 2971 U16 ThresholdFlags; /*0x0C */ 2972 U16 Reserved4; /*0x0E */ 2973 } MPI2_SASPHY3_PHY_EVENT_CONFIG, 2974 *PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG, 2975 Mpi2SasPhy3PhyEventConfig_t, 2976 *pMpi2SasPhy3PhyEventConfig_t; 2977 2978 /*values for PhyEventCode field */ 2979 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 2980 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 2981 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 2982 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 2983 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 2984 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 2985 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 2986 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 2987 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 2988 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 2989 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 2990 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 2991 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 2992 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 2993 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 2994 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 2995 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 2996 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A) 2997 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B) 2998 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C) 2999 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D) 3000 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E) 3001 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 3002 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 3003 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 3004 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 3005 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 3006 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 3007 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 3008 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 3009 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 3010 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 3011 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 3012 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 3013 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) 3014 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) 3015 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2) 3016 3017 /*Following codes are product specific and in MPI v2.6 and later */ 3018 #define MPI2_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xD3) 3019 #define MPI2_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xD4) 3020 #define MPI2_SASPHY3_EVENT_CODE_LCCONN_TIME (0xD5) 3021 #define MPI2_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xD6) 3022 #define MPI2_SASPHY3_EVENT_CODE_SATA_TX_START (0xD7) 3023 #define MPI2_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xD8) 3024 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xD9) 3025 #define MPI2_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xDA) 3026 #define MPI2_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xDB) 3027 #define MPI2_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xDC) 3028 3029 3030 /*values for the CounterType field */ 3031 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 3032 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 3033 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 3034 3035 /*values for the TimeUnits field */ 3036 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 3037 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 3038 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 3039 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 3040 3041 /*values for the ThresholdFlags field */ 3042 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002) 3043 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 3044 3045 /* 3046 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3047 *one and check the value returned for NumPhyEvents at runtime. 3048 */ 3049 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX 3050 #define MPI2_SASPHY3_PHY_EVENT_MAX (1) 3051 #endif 3052 3053 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 { 3054 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3055 Header; /*0x00 */ 3056 U32 3057 Reserved1; /*0x08 */ 3058 U8 3059 NumPhyEvents; /*0x0C */ 3060 U8 3061 Reserved2; /*0x0D */ 3062 U16 3063 Reserved3; /*0x0E */ 3064 MPI2_SASPHY3_PHY_EVENT_CONFIG 3065 PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /*0x10 */ 3066 } MPI2_CONFIG_PAGE_SAS_PHY_3, 3067 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_3, 3068 Mpi2SasPhyPage3_t, *pMpi2SasPhyPage3_t; 3069 3070 #define MPI2_SASPHY3_PAGEVERSION (0x00) 3071 3072 3073 /*SAS PHY Page 4 */ 3074 3075 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 { 3076 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3077 Header; /*0x00 */ 3078 U16 3079 Reserved1; /*0x08 */ 3080 U8 3081 Reserved2; /*0x0A */ 3082 U8 3083 Flags; /*0x0B */ 3084 U8 3085 InitialFrame[28]; /*0x0C */ 3086 } MPI2_CONFIG_PAGE_SAS_PHY_4, 3087 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_4, 3088 Mpi2SasPhyPage4_t, *pMpi2SasPhyPage4_t; 3089 3090 #define MPI2_SASPHY4_PAGEVERSION (0x00) 3091 3092 /*values for the Flags field */ 3093 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02) 3094 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01) 3095 3096 3097 3098 3099 /**************************************************************************** 3100 * SAS Port Config Pages 3101 ****************************************************************************/ 3102 3103 /*SAS Port Page 0 */ 3104 3105 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 { 3106 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3107 Header; /*0x00 */ 3108 U8 3109 PortNumber; /*0x08 */ 3110 U8 3111 PhysicalPort; /*0x09 */ 3112 U8 3113 PortWidth; /*0x0A */ 3114 U8 3115 PhysicalPortWidth; /*0x0B */ 3116 U8 3117 ZoneGroup; /*0x0C */ 3118 U8 3119 Reserved1; /*0x0D */ 3120 U16 3121 Reserved2; /*0x0E */ 3122 U64 3123 SASAddress; /*0x10 */ 3124 U32 3125 DeviceInfo; /*0x18 */ 3126 U32 3127 Reserved3; /*0x1C */ 3128 U32 3129 Reserved4; /*0x20 */ 3130 } MPI2_CONFIG_PAGE_SAS_PORT_0, 3131 *PTR_MPI2_CONFIG_PAGE_SAS_PORT_0, 3132 Mpi2SasPortPage0_t, *pMpi2SasPortPage0_t; 3133 3134 #define MPI2_SASPORT0_PAGEVERSION (0x00) 3135 3136 /*see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */ 3137 3138 3139 /**************************************************************************** 3140 * SAS Enclosure Config Pages 3141 ****************************************************************************/ 3142 3143 /*SAS Enclosure Page 0 */ 3144 3145 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 { 3146 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3147 Header; /*0x00 */ 3148 U32 3149 Reserved1; /*0x08 */ 3150 U64 3151 EnclosureLogicalID; /*0x0C */ 3152 U16 3153 Flags; /*0x14 */ 3154 U16 3155 EnclosureHandle; /*0x16 */ 3156 U16 3157 NumSlots; /*0x18 */ 3158 U16 3159 StartSlot; /*0x1A */ 3160 U8 3161 Reserved2; /*0x1C */ 3162 U8 3163 EnclosureLevel; /*0x1D */ 3164 U16 3165 SEPDevHandle; /*0x1E */ 3166 U32 3167 Reserved3; /*0x20 */ 3168 U32 3169 Reserved4; /*0x24 */ 3170 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3171 *PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3172 Mpi2SasEnclosurePage0_t, *pMpi2SasEnclosurePage0_t; 3173 3174 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x04) 3175 3176 /*values for SAS Enclosure Page 0 Flags field */ 3177 #define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010) 3178 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 3179 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3180 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3181 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3182 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3183 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3184 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3185 3186 3187 /**************************************************************************** 3188 * Log Config Page 3189 ****************************************************************************/ 3190 3191 /*Log Page 0 */ 3192 3193 /* 3194 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3195 *one and check the value returned for NumLogEntries at runtime. 3196 */ 3197 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES 3198 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1) 3199 #endif 3200 3201 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C) 3202 3203 typedef struct _MPI2_LOG_0_ENTRY { 3204 U64 TimeStamp; /*0x00 */ 3205 U32 Reserved1; /*0x08 */ 3206 U16 LogSequence; /*0x0C */ 3207 U16 LogEntryQualifier; /*0x0E */ 3208 U8 VP_ID; /*0x10 */ 3209 U8 VF_ID; /*0x11 */ 3210 U16 Reserved2; /*0x12 */ 3211 U8 3212 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/*0x14 */ 3213 } MPI2_LOG_0_ENTRY, *PTR_MPI2_LOG_0_ENTRY, 3214 Mpi2Log0Entry_t, *pMpi2Log0Entry_t; 3215 3216 /*values for Log Page 0 LogEntry LogEntryQualifier field */ 3217 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 3218 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 3219 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002) 3220 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000) 3221 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF) 3222 3223 typedef struct _MPI2_CONFIG_PAGE_LOG_0 { 3224 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3225 U32 Reserved1; /*0x08 */ 3226 U32 Reserved2; /*0x0C */ 3227 U16 NumLogEntries;/*0x10 */ 3228 U16 Reserved3; /*0x12 */ 3229 MPI2_LOG_0_ENTRY 3230 LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /*0x14 */ 3231 } MPI2_CONFIG_PAGE_LOG_0, *PTR_MPI2_CONFIG_PAGE_LOG_0, 3232 Mpi2LogPage0_t, *pMpi2LogPage0_t; 3233 3234 #define MPI2_LOG_0_PAGEVERSION (0x02) 3235 3236 3237 /**************************************************************************** 3238 * RAID Config Page 3239 ****************************************************************************/ 3240 3241 /*RAID Page 0 */ 3242 3243 /* 3244 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3245 *one and check the value returned for NumElements at runtime. 3246 */ 3247 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS 3248 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1) 3249 #endif 3250 3251 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT { 3252 U16 ElementFlags; /*0x00 */ 3253 U16 VolDevHandle; /*0x02 */ 3254 U8 HotSparePool; /*0x04 */ 3255 U8 PhysDiskNum; /*0x05 */ 3256 U16 PhysDiskDevHandle; /*0x06 */ 3257 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3258 *PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3259 Mpi2RaidConfig0ConfigElement_t, 3260 *pMpi2RaidConfig0ConfigElement_t; 3261 3262 /*values for the ElementFlags field */ 3263 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F) 3264 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000) 3265 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001) 3266 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002) 3267 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003) 3268 3269 3270 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 { 3271 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3272 U8 NumHotSpares; /*0x08 */ 3273 U8 NumPhysDisks; /*0x09 */ 3274 U8 NumVolumes; /*0x0A */ 3275 U8 ConfigNum; /*0x0B */ 3276 U32 Flags; /*0x0C */ 3277 U8 ConfigGUID[24]; /*0x10 */ 3278 U32 Reserved1; /*0x28 */ 3279 U8 NumElements; /*0x2C */ 3280 U8 Reserved2; /*0x2D */ 3281 U16 Reserved3; /*0x2E */ 3282 MPI2_RAIDCONFIG0_CONFIG_ELEMENT 3283 ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /*0x30 */ 3284 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3285 *PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3286 Mpi2RaidConfigurationPage0_t, 3287 *pMpi2RaidConfigurationPage0_t; 3288 3289 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00) 3290 3291 /*values for RAID Configuration Page 0 Flags field */ 3292 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001) 3293 3294 3295 /**************************************************************************** 3296 * Driver Persistent Mapping Config Pages 3297 ****************************************************************************/ 3298 3299 /*Driver Persistent Mapping Page 0 */ 3300 3301 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY { 3302 U64 PhysicalIdentifier; /*0x00 */ 3303 U16 MappingInformation; /*0x08 */ 3304 U16 DeviceIndex; /*0x0A */ 3305 U32 PhysicalBitsMapping; /*0x0C */ 3306 U32 Reserved1; /*0x10 */ 3307 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3308 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3309 Mpi2DriverMap0Entry_t, *pMpi2DriverMap0Entry_t; 3310 3311 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 { 3312 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3313 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /*0x08 */ 3314 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3315 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3316 Mpi2DriverMappingPage0_t, *pMpi2DriverMappingPage0_t; 3317 3318 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00) 3319 3320 /*values for Driver Persistent Mapping Page 0 MappingInformation field */ 3321 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0) 3322 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4) 3323 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F) 3324 3325 3326 /**************************************************************************** 3327 * Ethernet Config Pages 3328 ****************************************************************************/ 3329 3330 /*Ethernet Page 0 */ 3331 3332 /*IP address (union of IPv4 and IPv6) */ 3333 typedef union _MPI2_ETHERNET_IP_ADDR { 3334 U32 IPv4Addr; 3335 U32 IPv6Addr[4]; 3336 } MPI2_ETHERNET_IP_ADDR, *PTR_MPI2_ETHERNET_IP_ADDR, 3337 Mpi2EthernetIpAddr_t, *pMpi2EthernetIpAddr_t; 3338 3339 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32) 3340 3341 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 { 3342 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3343 U8 NumInterfaces; /*0x08 */ 3344 U8 Reserved0; /*0x09 */ 3345 U16 Reserved1; /*0x0A */ 3346 U32 Status; /*0x0C */ 3347 U8 MediaState; /*0x10 */ 3348 U8 Reserved2; /*0x11 */ 3349 U16 Reserved3; /*0x12 */ 3350 U8 MacAddress[6]; /*0x14 */ 3351 U8 Reserved4; /*0x1A */ 3352 U8 Reserved5; /*0x1B */ 3353 MPI2_ETHERNET_IP_ADDR IpAddress; /*0x1C */ 3354 MPI2_ETHERNET_IP_ADDR SubnetMask; /*0x2C */ 3355 MPI2_ETHERNET_IP_ADDR GatewayIpAddress;/*0x3C */ 3356 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /*0x4C */ 3357 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /*0x5C */ 3358 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /*0x6C */ 3359 U8 3360 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */ 3361 } MPI2_CONFIG_PAGE_ETHERNET_0, 3362 *PTR_MPI2_CONFIG_PAGE_ETHERNET_0, 3363 Mpi2EthernetPage0_t, *pMpi2EthernetPage0_t; 3364 3365 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00) 3366 3367 /*values for Ethernet Page 0 Status field */ 3368 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000) 3369 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000) 3370 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000) 3371 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100) 3372 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080) 3373 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040) 3374 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020) 3375 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010) 3376 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008) 3377 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004) 3378 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002) 3379 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001) 3380 3381 /*values for Ethernet Page 0 MediaState field */ 3382 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80) 3383 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00) 3384 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80) 3385 3386 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07) 3387 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00) 3388 #define MPI2_ETHPG0_MS_10MBIT (0x01) 3389 #define MPI2_ETHPG0_MS_100MBIT (0x02) 3390 #define MPI2_ETHPG0_MS_1GBIT (0x03) 3391 3392 3393 /*Ethernet Page 1 */ 3394 3395 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 { 3396 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3397 Header; /*0x00 */ 3398 U32 3399 Reserved0; /*0x08 */ 3400 U32 3401 Flags; /*0x0C */ 3402 U8 3403 MediaState; /*0x10 */ 3404 U8 3405 Reserved1; /*0x11 */ 3406 U16 3407 Reserved2; /*0x12 */ 3408 U8 3409 MacAddress[6]; /*0x14 */ 3410 U8 3411 Reserved3; /*0x1A */ 3412 U8 3413 Reserved4; /*0x1B */ 3414 MPI2_ETHERNET_IP_ADDR 3415 StaticIpAddress; /*0x1C */ 3416 MPI2_ETHERNET_IP_ADDR 3417 StaticSubnetMask; /*0x2C */ 3418 MPI2_ETHERNET_IP_ADDR 3419 StaticGatewayIpAddress; /*0x3C */ 3420 MPI2_ETHERNET_IP_ADDR 3421 StaticDNS1IpAddress; /*0x4C */ 3422 MPI2_ETHERNET_IP_ADDR 3423 StaticDNS2IpAddress; /*0x5C */ 3424 U32 3425 Reserved5; /*0x6C */ 3426 U32 3427 Reserved6; /*0x70 */ 3428 U32 3429 Reserved7; /*0x74 */ 3430 U32 3431 Reserved8; /*0x78 */ 3432 U8 3433 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */ 3434 } MPI2_CONFIG_PAGE_ETHERNET_1, 3435 *PTR_MPI2_CONFIG_PAGE_ETHERNET_1, 3436 Mpi2EthernetPage1_t, *pMpi2EthernetPage1_t; 3437 3438 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00) 3439 3440 /*values for Ethernet Page 1 Flags field */ 3441 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100) 3442 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080) 3443 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040) 3444 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020) 3445 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010) 3446 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008) 3447 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004) 3448 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002) 3449 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001) 3450 3451 /*values for Ethernet Page 1 MediaState field */ 3452 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80) 3453 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00) 3454 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80) 3455 3456 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07) 3457 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00) 3458 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01) 3459 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02) 3460 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03) 3461 3462 3463 /**************************************************************************** 3464 * Extended Manufacturing Config Pages 3465 ****************************************************************************/ 3466 3467 /* 3468 *Generic structure to use for product-specific extended manufacturing pages 3469 *(currently Extended Manufacturing Page 40 through Extended Manufacturing 3470 *Page 60). 3471 */ 3472 3473 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS { 3474 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3475 Header; /*0x00 */ 3476 U32 3477 ProductSpecificInfo; /*0x08 */ 3478 } MPI2_CONFIG_PAGE_EXT_MAN_PS, 3479 *PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS, 3480 Mpi2ExtManufacturingPagePS_t, 3481 *pMpi2ExtManufacturingPagePS_t; 3482 3483 /*PageVersion should be provided by product-specific code */ 3484 3485 #endif 3486