1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright 2000-2015 Avago Technologies. All rights reserved. 4 * 5 * 6 * Name: mpi2.h 7 * Title: MPI Message independent structures and definitions 8 * including System Interface Register Set and 9 * scatter/gather formats. 10 * Creation Date: June 21, 2006 11 * 12 * mpi2.h Version: 02.00.50 13 * 14 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 15 * prefix are for use only on MPI v2.5 products, and must not be used 16 * with MPI v2.0 products. Unless otherwise noted, names beginning with 17 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 18 * 19 * Version History 20 * --------------- 21 * 22 * Date Version Description 23 * -------- -------- ------------------------------------------------------ 24 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 25 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT. 26 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT. 27 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT. 28 * Moved ReplyPostHostIndex register to offset 0x6C of the 29 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for 30 * MPI2_REPLY_POST_HOST_INDEX_OFFSET. 31 * Added union of request descriptors. 32 * Added union of reply descriptors. 33 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT. 34 * Added define for MPI2_VERSION_02_00. 35 * Fixed the size of the FunctionDependent5 field in the 36 * MPI2_DEFAULT_REPLY structure. 37 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT. 38 * Removed the MPI-defined Fault Codes and extended the 39 * product specific codes up to 0xEFFF. 40 * Added a sixth key value for the WriteSequence register 41 * and changed the flush value to 0x0. 42 * Added message function codes for Diagnostic Buffer Post 43 * and Diagnsotic Release. 44 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED 45 * Moved MPI2_VERSION_UNION from mpi2_ioc.h. 46 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT. 47 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT. 48 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT. 49 * Added #defines for marking a reply descriptor as unused. 50 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT. 51 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT. 52 * Moved LUN field defines from mpi2_init.h. 53 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT. 54 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT. 55 * In all request and reply descriptors, replaced VF_ID 56 * field with MSIxIndex field. 57 * Removed DevHandle field from 58 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those 59 * bytes reserved. 60 * Added RAID Accelerator functionality. 61 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT. 62 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT. 63 * Added MSI-x index mask and shift for Reply Post Host 64 * Index register. 65 * Added function code for Host Based Discovery Action. 66 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT. 67 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL. 68 * Added defines for product-specific range of message 69 * function codes, 0xF0 to 0xFF. 70 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT. 71 * Added alternative defines for the SGE Direction bit. 72 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT. 73 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT. 74 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define. 75 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT. 76 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE. 77 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT. 78 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT. 79 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT. 80 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT. 81 * Incorporating additions for MPI v2.5. 82 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT. 83 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT. 84 * Added Hard Reset delay timings. 85 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT. 86 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT. 87 * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT. 88 * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT. 89 * Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET. 90 * 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT. 91 * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT. 92 * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT. 93 * 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT. 94 * 01-08-14 02.00.34 Bumped MPI2_HEADER_VERSION_UNIT 95 * 06-13-14 02.00.35 Bumped MPI2_HEADER_VERSION_UNIT. 96 * 11-18-14 02.00.36 Updated copyright information. 97 * Bumped MPI2_HEADER_VERSION_UNIT. 98 * 03-16-15 02.00.37 Bumped MPI2_HEADER_VERSION_UNIT. 99 * Added Scratchpad registers to 100 * MPI2_SYSTEM_INTERFACE_REGS. 101 * Added MPI2_DIAG_SBR_RELOAD. 102 * 03-19-15 02.00.38 Bumped MPI2_HEADER_VERSION_UNIT. 103 * 05-25-15 02.00.39 Bumped MPI2_HEADER_VERSION_UNIT. 104 * 08-25-15 02.00.40 Bumped MPI2_HEADER_VERSION_UNIT. 105 * 12-15-15 02.00.41 Bumped MPI_HEADER_VERSION_UNIT 106 * 01-01-16 02.00.42 Bumped MPI_HEADER_VERSION_UNIT 107 * 04-05-16 02.00.43 Modified MPI26_DIAG_BOOT_DEVICE_SELECT defines 108 * to be unique within first 32 characters. 109 * Removed AHCI support. 110 * Removed SOP support. 111 * Bumped MPI2_HEADER_VERSION_UNIT. 112 * 04-10-16 02.00.44 Bumped MPI2_HEADER_VERSION_UNIT. 113 * 07-06-16 02.00.45 Bumped MPI2_HEADER_VERSION_UNIT. 114 * 09-02-16 02.00.46 Bumped MPI2_HEADER_VERSION_UNIT. 115 * 11-23-16 02.00.47 Bumped MPI2_HEADER_VERSION_UNIT. 116 * 02-03-17 02.00.48 Bumped MPI2_HEADER_VERSION_UNIT. 117 * 06-13-17 02.00.49 Bumped MPI2_HEADER_VERSION_UNIT. 118 * 09-29-17 02.00.50 Bumped MPI2_HEADER_VERSION_UNIT. 119 * -------------------------------------------------------------------------- 120 */ 121 122 #ifndef MPI2_H 123 #define MPI2_H 124 125 /***************************************************************************** 126 * 127 * MPI Version Definitions 128 * 129 *****************************************************************************/ 130 131 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 132 #define MPI2_VERSION_MAJOR_SHIFT (8) 133 #define MPI2_VERSION_MINOR_MASK (0x00FF) 134 #define MPI2_VERSION_MINOR_SHIFT (0) 135 136 /*major version for all MPI v2.x */ 137 #define MPI2_VERSION_MAJOR (0x02) 138 139 /*minor version for MPI v2.0 compatible products */ 140 #define MPI2_VERSION_MINOR (0x00) 141 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 142 MPI2_VERSION_MINOR) 143 #define MPI2_VERSION_02_00 (0x0200) 144 145 /*minor version for MPI v2.5 compatible products */ 146 #define MPI25_VERSION_MINOR (0x05) 147 #define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 148 MPI25_VERSION_MINOR) 149 #define MPI2_VERSION_02_05 (0x0205) 150 151 /*minor version for MPI v2.6 compatible products */ 152 #define MPI26_VERSION_MINOR (0x06) 153 #define MPI26_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 154 MPI26_VERSION_MINOR) 155 #define MPI2_VERSION_02_06 (0x0206) 156 157 158 /* Unit and Dev versioning for this MPI header set */ 159 #define MPI2_HEADER_VERSION_UNIT (0x32) 160 #define MPI2_HEADER_VERSION_DEV (0x00) 161 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 162 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 163 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 164 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 165 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 166 MPI2_HEADER_VERSION_DEV) 167 168 /***************************************************************************** 169 * 170 * IOC State Definitions 171 * 172 *****************************************************************************/ 173 174 #define MPI2_IOC_STATE_RESET (0x00000000) 175 #define MPI2_IOC_STATE_READY (0x10000000) 176 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000) 177 #define MPI2_IOC_STATE_FAULT (0x40000000) 178 179 #define MPI2_IOC_STATE_MASK (0xF0000000) 180 #define MPI2_IOC_STATE_SHIFT (28) 181 182 /*Fault state range for prodcut specific codes */ 183 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000) 184 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF) 185 186 /***************************************************************************** 187 * 188 * System Interface Register Definitions 189 * 190 *****************************************************************************/ 191 192 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS { 193 U32 Doorbell; /*0x00 */ 194 U32 WriteSequence; /*0x04 */ 195 U32 HostDiagnostic; /*0x08 */ 196 U32 Reserved1; /*0x0C */ 197 U32 DiagRWData; /*0x10 */ 198 U32 DiagRWAddressLow; /*0x14 */ 199 U32 DiagRWAddressHigh; /*0x18 */ 200 U32 Reserved2[5]; /*0x1C */ 201 U32 HostInterruptStatus; /*0x30 */ 202 U32 HostInterruptMask; /*0x34 */ 203 U32 DCRData; /*0x38 */ 204 U32 DCRAddress; /*0x3C */ 205 U32 Reserved3[2]; /*0x40 */ 206 U32 ReplyFreeHostIndex; /*0x48 */ 207 U32 Reserved4[8]; /*0x4C */ 208 U32 ReplyPostHostIndex; /*0x6C */ 209 U32 Reserved5; /*0x70 */ 210 U32 HCBSize; /*0x74 */ 211 U32 HCBAddressLow; /*0x78 */ 212 U32 HCBAddressHigh; /*0x7C */ 213 U32 Reserved6[12]; /*0x80 */ 214 U32 Scratchpad[4]; /*0xB0 */ 215 U32 RequestDescriptorPostLow; /*0xC0 */ 216 U32 RequestDescriptorPostHigh; /*0xC4 */ 217 U32 AtomicRequestDescriptorPost;/*0xC8 */ 218 U32 Reserved7[13]; /*0xCC */ 219 } MPI2_SYSTEM_INTERFACE_REGS, 220 *PTR_MPI2_SYSTEM_INTERFACE_REGS, 221 Mpi2SystemInterfaceRegs_t, 222 *pMpi2SystemInterfaceRegs_t; 223 224 /* 225 *Defines for working with the Doorbell register. 226 */ 227 #define MPI2_DOORBELL_OFFSET (0x00000000) 228 229 /*IOC --> System values */ 230 #define MPI2_DOORBELL_USED (0x08000000) 231 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000) 232 #define MPI2_DOORBELL_WHO_INIT_SHIFT (24) 233 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF) 234 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF) 235 236 /*System --> IOC values */ 237 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000) 238 #define MPI2_DOORBELL_FUNCTION_SHIFT (24) 239 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000) 240 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16) 241 242 /* 243 *Defines for the WriteSequence register 244 */ 245 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 246 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F) 247 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 248 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 249 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 250 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 251 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 252 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 253 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 254 255 /* 256 *Defines for the HostDiagnostic register 257 */ 258 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008) 259 260 #define MPI2_DIAG_SBR_RELOAD (0x00002000) 261 262 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800) 263 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000) 264 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800) 265 266 /* Defines for V7A/V7R HostDiagnostic Register */ 267 #define MPI26_DIAG_BOOT_DEVICE_SEL_64FLASH (0x00000000) 268 #define MPI26_DIAG_BOOT_DEVICE_SEL_64HCDW (0x00000800) 269 #define MPI26_DIAG_BOOT_DEVICE_SEL_32FLASH (0x00001000) 270 #define MPI26_DIAG_BOOT_DEVICE_SEL_32HCDW (0x00001800) 271 272 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) 273 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200) 274 #define MPI2_DIAG_HCB_MODE (0x00000100) 275 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080) 276 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040) 277 #define MPI2_DIAG_RESET_HISTORY (0x00000020) 278 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010) 279 #define MPI2_DIAG_RESET_ADAPTER (0x00000004) 280 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002) 281 282 /* 283 *Offsets for DiagRWData and address 284 */ 285 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010) 286 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014) 287 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018) 288 289 /* 290 *Defines for the HostInterruptStatus register 291 */ 292 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030) 293 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000) 294 #define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS 295 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000) 296 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008) 297 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001) 298 #define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS 299 300 /* 301 *Defines for the HostInterruptMask register 302 */ 303 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034) 304 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000) 305 #define MPI2_HIM_REPLY_INT_MASK (0x00000008) 306 #define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK 307 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001) 308 #define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK 309 310 /* 311 *Offsets for DCRData and address 312 */ 313 #define MPI2_DCR_DATA_OFFSET (0x00000038) 314 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C) 315 316 /* 317 *Offset for the Reply Free Queue 318 */ 319 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048) 320 321 /* 322 *Defines for the Reply Descriptor Post Queue 323 */ 324 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 325 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF) 326 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000) 327 #define MPI2_RPHI_MSIX_INDEX_SHIFT (24) 328 #define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /*MPI v2.5 only*/ 329 330 331 /* 332 *Defines for the HCBSize and address 333 */ 334 #define MPI2_HCB_SIZE_OFFSET (0x00000074) 335 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000) 336 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001) 337 338 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078) 339 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C) 340 341 /* 342 *Offsets for the Scratchpad registers 343 */ 344 #define MPI26_SCRATCHPAD0_OFFSET (0x000000B0) 345 #define MPI26_SCRATCHPAD1_OFFSET (0x000000B4) 346 #define MPI26_SCRATCHPAD2_OFFSET (0x000000B8) 347 #define MPI26_SCRATCHPAD3_OFFSET (0x000000BC) 348 349 /* 350 *Offsets for the Request Descriptor Post Queue 351 */ 352 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0) 353 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4) 354 #define MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET (0x000000C8) 355 356 /*Hard Reset delay timings */ 357 #define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000) 358 #define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000) 359 #define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000) 360 361 /***************************************************************************** 362 * 363 * Message Descriptors 364 * 365 *****************************************************************************/ 366 367 /*Request Descriptors */ 368 369 /*Default Request Descriptor */ 370 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR { 371 U8 RequestFlags; /*0x00 */ 372 U8 MSIxIndex; /*0x01 */ 373 U16 SMID; /*0x02 */ 374 U16 LMID; /*0x04 */ 375 U16 DescriptorTypeDependent; /*0x06 */ 376 } MPI2_DEFAULT_REQUEST_DESCRIPTOR, 377 *PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 378 Mpi2DefaultRequestDescriptor_t, 379 *pMpi2DefaultRequestDescriptor_t; 380 381 /*defines for the RequestFlags field */ 382 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x1E) 383 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_RSHIFT (1) 384 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 385 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 386 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 387 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 388 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 389 #define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C) 390 #define MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED (0x10) 391 392 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 393 394 /*High Priority Request Descriptor */ 395 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR { 396 U8 RequestFlags; /*0x00 */ 397 U8 MSIxIndex; /*0x01 */ 398 U16 SMID; /*0x02 */ 399 U16 LMID; /*0x04 */ 400 U16 Reserved1; /*0x06 */ 401 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 402 *PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 403 Mpi2HighPriorityRequestDescriptor_t, 404 *pMpi2HighPriorityRequestDescriptor_t; 405 406 /*SCSI IO Request Descriptor */ 407 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR { 408 U8 RequestFlags; /*0x00 */ 409 U8 MSIxIndex; /*0x01 */ 410 U16 SMID; /*0x02 */ 411 U16 LMID; /*0x04 */ 412 U16 DevHandle; /*0x06 */ 413 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 414 *PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 415 Mpi2SCSIIORequestDescriptor_t, 416 *pMpi2SCSIIORequestDescriptor_t; 417 418 /*SCSI Target Request Descriptor */ 419 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR { 420 U8 RequestFlags; /*0x00 */ 421 U8 MSIxIndex; /*0x01 */ 422 U16 SMID; /*0x02 */ 423 U16 LMID; /*0x04 */ 424 U16 IoIndex; /*0x06 */ 425 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 426 *PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 427 Mpi2SCSITargetRequestDescriptor_t, 428 *pMpi2SCSITargetRequestDescriptor_t; 429 430 /*RAID Accelerator Request Descriptor */ 431 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR { 432 U8 RequestFlags; /*0x00 */ 433 U8 MSIxIndex; /*0x01 */ 434 U16 SMID; /*0x02 */ 435 U16 LMID; /*0x04 */ 436 U16 Reserved; /*0x06 */ 437 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 438 *PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 439 Mpi2RAIDAcceleratorRequestDescriptor_t, 440 *pMpi2RAIDAcceleratorRequestDescriptor_t; 441 442 /*Fast Path SCSI IO Request Descriptor */ 443 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR 444 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR, 445 *PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR, 446 Mpi25FastPathSCSIIORequestDescriptor_t, 447 *pMpi25FastPathSCSIIORequestDescriptor_t; 448 449 /*PCIe Encapsulated Request Descriptor */ 450 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR 451 MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR, 452 *PTR_MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR, 453 Mpi26PCIeEncapsulatedRequestDescriptor_t, 454 *pMpi26PCIeEncapsulatedRequestDescriptor_t; 455 456 /*union of Request Descriptors */ 457 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION { 458 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 459 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 460 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 461 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 462 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 463 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO; 464 MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR PCIeEncapsulated; 465 U64 Words; 466 } MPI2_REQUEST_DESCRIPTOR_UNION, 467 *PTR_MPI2_REQUEST_DESCRIPTOR_UNION, 468 Mpi2RequestDescriptorUnion_t, 469 *pMpi2RequestDescriptorUnion_t; 470 471 /*Atomic Request Descriptors */ 472 473 /* 474 * All Atomic Request Descriptors have the same format, so the following 475 * structure is used for all Atomic Request Descriptors: 476 * Atomic Default Request Descriptor 477 * Atomic High Priority Request Descriptor 478 * Atomic SCSI IO Request Descriptor 479 * Atomic SCSI Target Request Descriptor 480 * Atomic RAID Accelerator Request Descriptor 481 * Atomic Fast Path SCSI IO Request Descriptor 482 * Atomic PCIe Encapsulated Request Descriptor 483 */ 484 485 /*Atomic Request Descriptor */ 486 typedef struct _MPI26_ATOMIC_REQUEST_DESCRIPTOR { 487 U8 RequestFlags; /* 0x00 */ 488 U8 MSIxIndex; /* 0x01 */ 489 U16 SMID; /* 0x02 */ 490 } MPI26_ATOMIC_REQUEST_DESCRIPTOR, 491 *PTR_MPI26_ATOMIC_REQUEST_DESCRIPTOR, 492 Mpi26AtomicRequestDescriptor_t, 493 *pMpi26AtomicRequestDescriptor_t; 494 495 /*for the RequestFlags field, use the same 496 *defines as MPI2_DEFAULT_REQUEST_DESCRIPTOR 497 */ 498 499 /*Reply Descriptors */ 500 501 /*Default Reply Descriptor */ 502 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR { 503 U8 ReplyFlags; /*0x00 */ 504 U8 MSIxIndex; /*0x01 */ 505 U16 DescriptorTypeDependent1; /*0x02 */ 506 U32 DescriptorTypeDependent2; /*0x04 */ 507 } MPI2_DEFAULT_REPLY_DESCRIPTOR, 508 *PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 509 Mpi2DefaultReplyDescriptor_t, 510 *pMpi2DefaultReplyDescriptor_t; 511 512 /*defines for the ReplyFlags field */ 513 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 514 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 515 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 516 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 517 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 518 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 519 #define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06) 520 #define MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS (0x08) 521 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 522 523 /*values for marking a reply descriptor as unused */ 524 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 525 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 526 527 /*Address Reply Descriptor */ 528 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR { 529 U8 ReplyFlags; /*0x00 */ 530 U8 MSIxIndex; /*0x01 */ 531 U16 SMID; /*0x02 */ 532 U32 ReplyFrameAddress; /*0x04 */ 533 } MPI2_ADDRESS_REPLY_DESCRIPTOR, 534 *PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 535 Mpi2AddressReplyDescriptor_t, 536 *pMpi2AddressReplyDescriptor_t; 537 538 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00) 539 540 /*SCSI IO Success Reply Descriptor */ 541 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR { 542 U8 ReplyFlags; /*0x00 */ 543 U8 MSIxIndex; /*0x01 */ 544 U16 SMID; /*0x02 */ 545 U16 TaskTag; /*0x04 */ 546 U16 Reserved1; /*0x06 */ 547 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 548 *PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 549 Mpi2SCSIIOSuccessReplyDescriptor_t, 550 *pMpi2SCSIIOSuccessReplyDescriptor_t; 551 552 /*TargetAssist Success Reply Descriptor */ 553 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR { 554 U8 ReplyFlags; /*0x00 */ 555 U8 MSIxIndex; /*0x01 */ 556 U16 SMID; /*0x02 */ 557 U8 SequenceNumber; /*0x04 */ 558 U8 Reserved1; /*0x05 */ 559 U16 IoIndex; /*0x06 */ 560 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 561 *PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 562 Mpi2TargetAssistSuccessReplyDescriptor_t, 563 *pMpi2TargetAssistSuccessReplyDescriptor_t; 564 565 /*Target Command Buffer Reply Descriptor */ 566 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR { 567 U8 ReplyFlags; /*0x00 */ 568 U8 MSIxIndex; /*0x01 */ 569 U8 VP_ID; /*0x02 */ 570 U8 Flags; /*0x03 */ 571 U16 InitiatorDevHandle; /*0x04 */ 572 U16 IoIndex; /*0x06 */ 573 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 574 *PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 575 Mpi2TargetCommandBufferReplyDescriptor_t, 576 *pMpi2TargetCommandBufferReplyDescriptor_t; 577 578 /*defines for Flags field */ 579 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F) 580 581 /*RAID Accelerator Success Reply Descriptor */ 582 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR { 583 U8 ReplyFlags; /*0x00 */ 584 U8 MSIxIndex; /*0x01 */ 585 U16 SMID; /*0x02 */ 586 U32 Reserved; /*0x04 */ 587 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 588 *PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 589 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, 590 *pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 591 592 /*Fast Path SCSI IO Success Reply Descriptor */ 593 typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 594 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 595 *PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 596 Mpi25FastPathSCSIIOSuccessReplyDescriptor_t, 597 *pMpi25FastPathSCSIIOSuccessReplyDescriptor_t; 598 599 /*PCIe Encapsulated Success Reply Descriptor */ 600 typedef MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 601 MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR, 602 *PTR_MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR, 603 Mpi26PCIeEncapsulatedSuccessReplyDescriptor_t, 604 *pMpi26PCIeEncapsulatedSuccessReplyDescriptor_t; 605 606 /*union of Reply Descriptors */ 607 typedef union _MPI2_REPLY_DESCRIPTORS_UNION { 608 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 609 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 610 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 611 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 612 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 613 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 614 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess; 615 MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR 616 PCIeEncapsulatedSuccess; 617 U64 Words; 618 } MPI2_REPLY_DESCRIPTORS_UNION, 619 *PTR_MPI2_REPLY_DESCRIPTORS_UNION, 620 Mpi2ReplyDescriptorsUnion_t, 621 *pMpi2ReplyDescriptorsUnion_t; 622 623 /***************************************************************************** 624 * 625 * Message Functions 626 * 627 *****************************************************************************/ 628 629 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) 630 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) 631 #define MPI2_FUNCTION_IOC_INIT (0x02) 632 #define MPI2_FUNCTION_IOC_FACTS (0x03) 633 #define MPI2_FUNCTION_CONFIG (0x04) 634 #define MPI2_FUNCTION_PORT_FACTS (0x05) 635 #define MPI2_FUNCTION_PORT_ENABLE (0x06) 636 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) 637 #define MPI2_FUNCTION_EVENT_ACK (0x08) 638 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) 639 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) 640 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) 641 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) 642 #define MPI2_FUNCTION_FW_UPLOAD (0x12) 643 #define MPI2_FUNCTION_RAID_ACTION (0x15) 644 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) 645 #define MPI2_FUNCTION_TOOLBOX (0x17) 646 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) 647 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) 648 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) 649 #define MPI2_FUNCTION_IO_UNIT_CONTROL (0x1B) 650 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) 651 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) 652 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) 653 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) 654 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) 655 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) 656 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) 657 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) 658 #define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31) 659 #define MPI2_FUNCTION_NVME_ENCAPSULATED (0x33) 660 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) 661 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) 662 663 /*Doorbell functions */ 664 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 665 #define MPI2_FUNCTION_HANDSHAKE (0x42) 666 667 /***************************************************************************** 668 * 669 * IOC Status Values 670 * 671 *****************************************************************************/ 672 673 /*mask for IOCStatus status value */ 674 #define MPI2_IOCSTATUS_MASK (0x7FFF) 675 676 /**************************************************************************** 677 * Common IOCStatus values for all replies 678 ****************************************************************************/ 679 680 #define MPI2_IOCSTATUS_SUCCESS (0x0000) 681 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001) 682 #define MPI2_IOCSTATUS_BUSY (0x0002) 683 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003) 684 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004) 685 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005) 686 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 687 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007) 688 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008) 689 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) 690 #define MPI2_IOCSTATUS_INSUFFICIENT_POWER (0x000A) 691 692 /**************************************************************************** 693 * Config IOCStatus values 694 ****************************************************************************/ 695 696 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 697 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 698 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 699 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 700 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 701 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 702 703 /**************************************************************************** 704 * SCSI IO Reply 705 ****************************************************************************/ 706 707 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 708 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 709 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 710 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 711 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 712 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 713 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 714 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 715 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 716 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) 717 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) 718 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) 719 720 /**************************************************************************** 721 * For use by SCSI Initiator and SCSI Target end-to-end data protection 722 ****************************************************************************/ 723 724 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D) 725 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E) 726 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F) 727 728 /**************************************************************************** 729 * SCSI Target values 730 ****************************************************************************/ 731 732 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 733 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063) 734 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 735 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 736 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) 737 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D) 738 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E) 739 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F) 740 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 741 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 742 743 /**************************************************************************** 744 * Serial Attached SCSI values 745 ****************************************************************************/ 746 747 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 748 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 749 750 /**************************************************************************** 751 * Diagnostic Buffer Post / Diagnostic Release values 752 ****************************************************************************/ 753 754 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0) 755 756 /**************************************************************************** 757 * RAID Accelerator values 758 ****************************************************************************/ 759 760 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0) 761 762 /**************************************************************************** 763 * IOCStatus flag to indicate that log info is available 764 ****************************************************************************/ 765 766 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000) 767 768 /**************************************************************************** 769 * IOCLogInfo Types 770 ****************************************************************************/ 771 772 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000) 773 #define MPI2_IOCLOGINFO_TYPE_SHIFT (28) 774 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0) 775 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1) 776 #define MPI2_IOCLOGINFO_TYPE_FC (0x2) 777 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3) 778 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4) 779 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) 780 781 /***************************************************************************** 782 * 783 * Standard Message Structures 784 * 785 *****************************************************************************/ 786 787 /**************************************************************************** 788 *Request Message Header for all request messages 789 ****************************************************************************/ 790 791 typedef struct _MPI2_REQUEST_HEADER { 792 U16 FunctionDependent1; /*0x00 */ 793 U8 ChainOffset; /*0x02 */ 794 U8 Function; /*0x03 */ 795 U16 FunctionDependent2; /*0x04 */ 796 U8 FunctionDependent3; /*0x06 */ 797 U8 MsgFlags; /*0x07 */ 798 U8 VP_ID; /*0x08 */ 799 U8 VF_ID; /*0x09 */ 800 U16 Reserved1; /*0x0A */ 801 } MPI2_REQUEST_HEADER, *PTR_MPI2_REQUEST_HEADER, 802 MPI2RequestHeader_t, *pMPI2RequestHeader_t; 803 804 /**************************************************************************** 805 * Default Reply 806 ****************************************************************************/ 807 808 typedef struct _MPI2_DEFAULT_REPLY { 809 U16 FunctionDependent1; /*0x00 */ 810 U8 MsgLength; /*0x02 */ 811 U8 Function; /*0x03 */ 812 U16 FunctionDependent2; /*0x04 */ 813 U8 FunctionDependent3; /*0x06 */ 814 U8 MsgFlags; /*0x07 */ 815 U8 VP_ID; /*0x08 */ 816 U8 VF_ID; /*0x09 */ 817 U16 Reserved1; /*0x0A */ 818 U16 FunctionDependent5; /*0x0C */ 819 U16 IOCStatus; /*0x0E */ 820 U32 IOCLogInfo; /*0x10 */ 821 } MPI2_DEFAULT_REPLY, *PTR_MPI2_DEFAULT_REPLY, 822 MPI2DefaultReply_t, *pMPI2DefaultReply_t; 823 824 /*common version structure/union used in messages and configuration pages */ 825 826 typedef struct _MPI2_VERSION_STRUCT { 827 U8 Dev; /*0x00 */ 828 U8 Unit; /*0x01 */ 829 U8 Minor; /*0x02 */ 830 U8 Major; /*0x03 */ 831 } MPI2_VERSION_STRUCT; 832 833 typedef union _MPI2_VERSION_UNION { 834 MPI2_VERSION_STRUCT Struct; 835 U32 Word; 836 } MPI2_VERSION_UNION; 837 838 /*LUN field defines, common to many structures */ 839 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) 840 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) 841 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) 842 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) 843 #define MPI2_LUN_LEVEL_1_WORD (0xFF00) 844 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00) 845 846 /***************************************************************************** 847 * 848 * Fusion-MPT MPI Scatter Gather Elements 849 * 850 *****************************************************************************/ 851 852 /**************************************************************************** 853 * MPI Simple Element structures 854 ****************************************************************************/ 855 856 typedef struct _MPI2_SGE_SIMPLE32 { 857 U32 FlagsLength; 858 U32 Address; 859 } MPI2_SGE_SIMPLE32, *PTR_MPI2_SGE_SIMPLE32, 860 Mpi2SGESimple32_t, *pMpi2SGESimple32_t; 861 862 typedef struct _MPI2_SGE_SIMPLE64 { 863 U32 FlagsLength; 864 U64 Address; 865 } MPI2_SGE_SIMPLE64, *PTR_MPI2_SGE_SIMPLE64, 866 Mpi2SGESimple64_t, *pMpi2SGESimple64_t; 867 868 typedef struct _MPI2_SGE_SIMPLE_UNION { 869 U32 FlagsLength; 870 union { 871 U32 Address32; 872 U64 Address64; 873 } u; 874 } MPI2_SGE_SIMPLE_UNION, 875 *PTR_MPI2_SGE_SIMPLE_UNION, 876 Mpi2SGESimpleUnion_t, 877 *pMpi2SGESimpleUnion_t; 878 879 /**************************************************************************** 880 * MPI Chain Element structures - for MPI v2.0 products only 881 ****************************************************************************/ 882 883 typedef struct _MPI2_SGE_CHAIN32 { 884 U16 Length; 885 U8 NextChainOffset; 886 U8 Flags; 887 U32 Address; 888 } MPI2_SGE_CHAIN32, *PTR_MPI2_SGE_CHAIN32, 889 Mpi2SGEChain32_t, *pMpi2SGEChain32_t; 890 891 typedef struct _MPI2_SGE_CHAIN64 { 892 U16 Length; 893 U8 NextChainOffset; 894 U8 Flags; 895 U64 Address; 896 } MPI2_SGE_CHAIN64, *PTR_MPI2_SGE_CHAIN64, 897 Mpi2SGEChain64_t, *pMpi2SGEChain64_t; 898 899 typedef struct _MPI2_SGE_CHAIN_UNION { 900 U16 Length; 901 U8 NextChainOffset; 902 U8 Flags; 903 union { 904 U32 Address32; 905 U64 Address64; 906 } u; 907 } MPI2_SGE_CHAIN_UNION, 908 *PTR_MPI2_SGE_CHAIN_UNION, 909 Mpi2SGEChainUnion_t, 910 *pMpi2SGEChainUnion_t; 911 912 /**************************************************************************** 913 * MPI Transaction Context Element structures - for MPI v2.0 products only 914 ****************************************************************************/ 915 916 typedef struct _MPI2_SGE_TRANSACTION32 { 917 U8 Reserved; 918 U8 ContextSize; 919 U8 DetailsLength; 920 U8 Flags; 921 U32 TransactionContext[1]; 922 U32 TransactionDetails[1]; 923 } MPI2_SGE_TRANSACTION32, 924 *PTR_MPI2_SGE_TRANSACTION32, 925 Mpi2SGETransaction32_t, 926 *pMpi2SGETransaction32_t; 927 928 typedef struct _MPI2_SGE_TRANSACTION64 { 929 U8 Reserved; 930 U8 ContextSize; 931 U8 DetailsLength; 932 U8 Flags; 933 U32 TransactionContext[2]; 934 U32 TransactionDetails[1]; 935 } MPI2_SGE_TRANSACTION64, 936 *PTR_MPI2_SGE_TRANSACTION64, 937 Mpi2SGETransaction64_t, 938 *pMpi2SGETransaction64_t; 939 940 typedef struct _MPI2_SGE_TRANSACTION96 { 941 U8 Reserved; 942 U8 ContextSize; 943 U8 DetailsLength; 944 U8 Flags; 945 U32 TransactionContext[3]; 946 U32 TransactionDetails[1]; 947 } MPI2_SGE_TRANSACTION96, *PTR_MPI2_SGE_TRANSACTION96, 948 Mpi2SGETransaction96_t, *pMpi2SGETransaction96_t; 949 950 typedef struct _MPI2_SGE_TRANSACTION128 { 951 U8 Reserved; 952 U8 ContextSize; 953 U8 DetailsLength; 954 U8 Flags; 955 U32 TransactionContext[4]; 956 U32 TransactionDetails[1]; 957 } MPI2_SGE_TRANSACTION128, *PTR_MPI2_SGE_TRANSACTION128, 958 Mpi2SGETransaction_t128, *pMpi2SGETransaction_t128; 959 960 typedef struct _MPI2_SGE_TRANSACTION_UNION { 961 U8 Reserved; 962 U8 ContextSize; 963 U8 DetailsLength; 964 U8 Flags; 965 union { 966 U32 TransactionContext32[1]; 967 U32 TransactionContext64[2]; 968 U32 TransactionContext96[3]; 969 U32 TransactionContext128[4]; 970 } u; 971 U32 TransactionDetails[1]; 972 } MPI2_SGE_TRANSACTION_UNION, 973 *PTR_MPI2_SGE_TRANSACTION_UNION, 974 Mpi2SGETransactionUnion_t, 975 *pMpi2SGETransactionUnion_t; 976 977 /**************************************************************************** 978 * MPI SGE union for IO SGL's - for MPI v2.0 products only 979 ****************************************************************************/ 980 981 typedef struct _MPI2_MPI_SGE_IO_UNION { 982 union { 983 MPI2_SGE_SIMPLE_UNION Simple; 984 MPI2_SGE_CHAIN_UNION Chain; 985 } u; 986 } MPI2_MPI_SGE_IO_UNION, *PTR_MPI2_MPI_SGE_IO_UNION, 987 Mpi2MpiSGEIOUnion_t, *pMpi2MpiSGEIOUnion_t; 988 989 /**************************************************************************** 990 * MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only 991 ****************************************************************************/ 992 993 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION { 994 union { 995 MPI2_SGE_SIMPLE_UNION Simple; 996 MPI2_SGE_TRANSACTION_UNION Transaction; 997 } u; 998 } MPI2_SGE_TRANS_SIMPLE_UNION, 999 *PTR_MPI2_SGE_TRANS_SIMPLE_UNION, 1000 Mpi2SGETransSimpleUnion_t, 1001 *pMpi2SGETransSimpleUnion_t; 1002 1003 /**************************************************************************** 1004 * All MPI SGE types union 1005 ****************************************************************************/ 1006 1007 typedef struct _MPI2_MPI_SGE_UNION { 1008 union { 1009 MPI2_SGE_SIMPLE_UNION Simple; 1010 MPI2_SGE_CHAIN_UNION Chain; 1011 MPI2_SGE_TRANSACTION_UNION Transaction; 1012 } u; 1013 } MPI2_MPI_SGE_UNION, *PTR_MPI2_MPI_SGE_UNION, 1014 Mpi2MpiSgeUnion_t, *pMpi2MpiSgeUnion_t; 1015 1016 /**************************************************************************** 1017 * MPI SGE field definition and masks 1018 ****************************************************************************/ 1019 1020 /*Flags field bit definitions */ 1021 1022 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80) 1023 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40) 1024 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30) 1025 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08) 1026 #define MPI2_SGE_FLAGS_DIRECTION (0x04) 1027 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02) 1028 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01) 1029 1030 #define MPI2_SGE_FLAGS_SHIFT (24) 1031 1032 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF) 1033 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF) 1034 1035 /*Element Type */ 1036 1037 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) 1038 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10) 1039 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30) 1040 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30) 1041 1042 /*Address location */ 1043 1044 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00) 1045 1046 /*Direction */ 1047 1048 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00) 1049 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04) 1050 1051 #define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST) 1052 #define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC) 1053 1054 /*Address Size */ 1055 1056 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 1057 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 1058 1059 /*Context Size */ 1060 1061 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00) 1062 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02) 1063 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04) 1064 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06) 1065 1066 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000) 1067 #define MPI2_SGE_CHAIN_OFFSET_SHIFT (16) 1068 1069 /**************************************************************************** 1070 * MPI SGE operation Macros 1071 ****************************************************************************/ 1072 1073 /*SIMPLE FlagsLength manipulations... */ 1074 #define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT) 1075 #define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> \ 1076 MPI2_SGE_FLAGS_SHIFT) 1077 #define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK) 1078 #define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK) 1079 1080 #define MPI2_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_SGE_SET_FLAGS(f) | \ 1081 MPI2_SGE_LENGTH(l)) 1082 1083 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength) 1084 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength) 1085 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \ 1086 MPI2_SGE_SET_FLAGS_LENGTH(f, l)) 1087 1088 /*CAUTION - The following are READ-MODIFY-WRITE! */ 1089 #define MPI2_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \ 1090 MPI2_SGE_SET_FLAGS(f)) 1091 #define MPI2_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \ 1092 MPI2_SGE_LENGTH(l)) 1093 1094 #define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> \ 1095 MPI2_SGE_CHAIN_OFFSET_SHIFT) 1096 1097 /***************************************************************************** 1098 * 1099 * Fusion-MPT IEEE Scatter Gather Elements 1100 * 1101 *****************************************************************************/ 1102 1103 /**************************************************************************** 1104 * IEEE Simple Element structures 1105 ****************************************************************************/ 1106 1107 /*MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */ 1108 typedef struct _MPI2_IEEE_SGE_SIMPLE32 { 1109 U32 Address; 1110 U32 FlagsLength; 1111 } MPI2_IEEE_SGE_SIMPLE32, *PTR_MPI2_IEEE_SGE_SIMPLE32, 1112 Mpi2IeeeSgeSimple32_t, *pMpi2IeeeSgeSimple32_t; 1113 1114 typedef struct _MPI2_IEEE_SGE_SIMPLE64 { 1115 U64 Address; 1116 U32 Length; 1117 U16 Reserved1; 1118 U8 Reserved2; 1119 U8 Flags; 1120 } MPI2_IEEE_SGE_SIMPLE64, *PTR_MPI2_IEEE_SGE_SIMPLE64, 1121 Mpi2IeeeSgeSimple64_t, *pMpi2IeeeSgeSimple64_t; 1122 1123 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION { 1124 MPI2_IEEE_SGE_SIMPLE32 Simple32; 1125 MPI2_IEEE_SGE_SIMPLE64 Simple64; 1126 } MPI2_IEEE_SGE_SIMPLE_UNION, 1127 *PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 1128 Mpi2IeeeSgeSimpleUnion_t, 1129 *pMpi2IeeeSgeSimpleUnion_t; 1130 1131 /**************************************************************************** 1132 * IEEE Chain Element structures 1133 ****************************************************************************/ 1134 1135 /*MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */ 1136 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 1137 1138 /*MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */ 1139 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 1140 1141 typedef union _MPI2_IEEE_SGE_CHAIN_UNION { 1142 MPI2_IEEE_SGE_CHAIN32 Chain32; 1143 MPI2_IEEE_SGE_CHAIN64 Chain64; 1144 } MPI2_IEEE_SGE_CHAIN_UNION, 1145 *PTR_MPI2_IEEE_SGE_CHAIN_UNION, 1146 Mpi2IeeeSgeChainUnion_t, 1147 *pMpi2IeeeSgeChainUnion_t; 1148 1149 /*MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 and later */ 1150 typedef struct _MPI25_IEEE_SGE_CHAIN64 { 1151 U64 Address; 1152 U32 Length; 1153 U16 Reserved1; 1154 U8 NextChainOffset; 1155 U8 Flags; 1156 } MPI25_IEEE_SGE_CHAIN64, 1157 *PTR_MPI25_IEEE_SGE_CHAIN64, 1158 Mpi25IeeeSgeChain64_t, 1159 *pMpi25IeeeSgeChain64_t; 1160 1161 /**************************************************************************** 1162 * All IEEE SGE types union 1163 ****************************************************************************/ 1164 1165 /*MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */ 1166 typedef struct _MPI2_IEEE_SGE_UNION { 1167 union { 1168 MPI2_IEEE_SGE_SIMPLE_UNION Simple; 1169 MPI2_IEEE_SGE_CHAIN_UNION Chain; 1170 } u; 1171 } MPI2_IEEE_SGE_UNION, *PTR_MPI2_IEEE_SGE_UNION, 1172 Mpi2IeeeSgeUnion_t, *pMpi2IeeeSgeUnion_t; 1173 1174 /**************************************************************************** 1175 * IEEE SGE union for IO SGL's 1176 ****************************************************************************/ 1177 1178 typedef union _MPI25_SGE_IO_UNION { 1179 MPI2_IEEE_SGE_SIMPLE64 IeeeSimple; 1180 MPI25_IEEE_SGE_CHAIN64 IeeeChain; 1181 } MPI25_SGE_IO_UNION, *PTR_MPI25_SGE_IO_UNION, 1182 Mpi25SGEIOUnion_t, *pMpi25SGEIOUnion_t; 1183 1184 /**************************************************************************** 1185 * IEEE SGE field definitions and masks 1186 ****************************************************************************/ 1187 1188 /*Flags field bit definitions */ 1189 1190 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1191 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1192 1193 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1194 1195 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1196 1197 /*Element Type */ 1198 1199 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1200 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1201 1202 /*Next Segment Format */ 1203 1204 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C) 1205 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00) 1206 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08) 1207 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10) 1208 1209 /*Data Location Address Space */ 1210 1211 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1212 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1213 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1214 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1215 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1216 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03) 1217 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR \ 1218 (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) 1219 #define MPI26_IEEE_SGE_FLAGS_IOCCTL_ADDR (0x02) 1220 1221 /**************************************************************************** 1222 * IEEE SGE operation Macros 1223 ****************************************************************************/ 1224 1225 /*SIMPLE FlagsLength manipulations... */ 1226 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT) 1227 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) \ 1228 >> MPI2_IEEE32_SGE_FLAGS_SHIFT) 1229 #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK) 1230 1231 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) |\ 1232 MPI2_IEEE32_SGE_LENGTH(l)) 1233 1234 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) \ 1235 MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength) 1236 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) \ 1237 MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength) 1238 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \ 1239 MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l)) 1240 1241 /*CAUTION - The following are READ-MODIFY-WRITE! */ 1242 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \ 1243 MPI2_IEEE32_SGE_SET_FLAGS(f)) 1244 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \ 1245 MPI2_IEEE32_SGE_LENGTH(l)) 1246 1247 /***************************************************************************** 1248 * 1249 * Fusion-MPT MPI/IEEE Scatter Gather Unions 1250 * 1251 *****************************************************************************/ 1252 1253 typedef union _MPI2_SIMPLE_SGE_UNION { 1254 MPI2_SGE_SIMPLE_UNION MpiSimple; 1255 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1256 } MPI2_SIMPLE_SGE_UNION, *PTR_MPI2_SIMPLE_SGE_UNION, 1257 Mpi2SimpleSgeUntion_t, *pMpi2SimpleSgeUntion_t; 1258 1259 typedef union _MPI2_SGE_IO_UNION { 1260 MPI2_SGE_SIMPLE_UNION MpiSimple; 1261 MPI2_SGE_CHAIN_UNION MpiChain; 1262 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1263 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1264 } MPI2_SGE_IO_UNION, *PTR_MPI2_SGE_IO_UNION, 1265 Mpi2SGEIOUnion_t, *pMpi2SGEIOUnion_t; 1266 1267 /**************************************************************************** 1268 * 1269 * Values for SGLFlags field, used in many request messages with an SGL 1270 * 1271 ****************************************************************************/ 1272 1273 /*values for MPI SGL Data Location Address Space subfield */ 1274 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C) 1275 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00) 1276 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04) 1277 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) 1278 #define MPI26_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) 1279 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) 1280 /*values for SGL Type subfield */ 1281 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03) 1282 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00) 1283 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) 1284 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02) 1285 1286 #endif 1287