1 /* 2 * Copyright 2000-2015 Avago Technologies. All rights reserved. 3 * 4 * 5 * Name: mpi2.h 6 * Title: MPI Message independent structures and definitions 7 * including System Interface Register Set and 8 * scatter/gather formats. 9 * Creation Date: June 21, 2006 10 * 11 * mpi2.h Version: 02.00.39 12 * 13 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 14 * prefix are for use only on MPI v2.5 products, and must not be used 15 * with MPI v2.0 products. Unless otherwise noted, names beginning with 16 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 17 * 18 * Version History 19 * --------------- 20 * 21 * Date Version Description 22 * -------- -------- ------------------------------------------------------ 23 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 24 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT. 25 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT. 26 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT. 27 * Moved ReplyPostHostIndex register to offset 0x6C of the 28 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for 29 * MPI2_REPLY_POST_HOST_INDEX_OFFSET. 30 * Added union of request descriptors. 31 * Added union of reply descriptors. 32 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT. 33 * Added define for MPI2_VERSION_02_00. 34 * Fixed the size of the FunctionDependent5 field in the 35 * MPI2_DEFAULT_REPLY structure. 36 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT. 37 * Removed the MPI-defined Fault Codes and extended the 38 * product specific codes up to 0xEFFF. 39 * Added a sixth key value for the WriteSequence register 40 * and changed the flush value to 0x0. 41 * Added message function codes for Diagnostic Buffer Post 42 * and Diagnsotic Release. 43 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED 44 * Moved MPI2_VERSION_UNION from mpi2_ioc.h. 45 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT. 46 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT. 47 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT. 48 * Added #defines for marking a reply descriptor as unused. 49 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT. 50 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT. 51 * Moved LUN field defines from mpi2_init.h. 52 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT. 53 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT. 54 * In all request and reply descriptors, replaced VF_ID 55 * field with MSIxIndex field. 56 * Removed DevHandle field from 57 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those 58 * bytes reserved. 59 * Added RAID Accelerator functionality. 60 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT. 61 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT. 62 * Added MSI-x index mask and shift for Reply Post Host 63 * Index register. 64 * Added function code for Host Based Discovery Action. 65 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT. 66 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL. 67 * Added defines for product-specific range of message 68 * function codes, 0xF0 to 0xFF. 69 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT. 70 * Added alternative defines for the SGE Direction bit. 71 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT. 72 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT. 73 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define. 74 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT. 75 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE. 76 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT. 77 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT. 78 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT. 79 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT. 80 * Incorporating additions for MPI v2.5. 81 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT. 82 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT. 83 * Added Hard Reset delay timings. 84 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT. 85 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT. 86 * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT. 87 * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT. 88 * Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET. 89 * 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT. 90 * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT. 91 * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT. 92 * 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT. 93 * 01-08-14 02.00.34 Bumped MPI2_HEADER_VERSION_UNIT 94 * 06-13-14 02.00.35 Bumped MPI2_HEADER_VERSION_UNIT. 95 * 11-18-14 02.00.36 Updated copyright information. 96 * Bumped MPI2_HEADER_VERSION_UNIT. 97 * 03-16-15 02.00.37 Bumped MPI2_HEADER_VERSION_UNIT. 98 * Added Scratchpad registers to 99 * MPI2_SYSTEM_INTERFACE_REGS. 100 * Added MPI2_DIAG_SBR_RELOAD. 101 * 03-19-15 02.00.38 Bumped MPI2_HEADER_VERSION_UNIT. 102 * 05-25-15 02.00.39 Bumped MPI2_HEADER_VERSION_UNIT. 103 * -------------------------------------------------------------------------- 104 */ 105 106 #ifndef MPI2_H 107 #define MPI2_H 108 109 /***************************************************************************** 110 * 111 * MPI Version Definitions 112 * 113 *****************************************************************************/ 114 115 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 116 #define MPI2_VERSION_MAJOR_SHIFT (8) 117 #define MPI2_VERSION_MINOR_MASK (0x00FF) 118 #define MPI2_VERSION_MINOR_SHIFT (0) 119 120 /*major version for all MPI v2.x */ 121 #define MPI2_VERSION_MAJOR (0x02) 122 123 /*minor version for MPI v2.0 compatible products */ 124 #define MPI2_VERSION_MINOR (0x00) 125 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 126 MPI2_VERSION_MINOR) 127 #define MPI2_VERSION_02_00 (0x0200) 128 129 /*minor version for MPI v2.5 compatible products */ 130 #define MPI25_VERSION_MINOR (0x05) 131 #define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 132 MPI25_VERSION_MINOR) 133 #define MPI2_VERSION_02_05 (0x0205) 134 135 /*minor version for MPI v2.6 compatible products */ 136 #define MPI26_VERSION_MINOR (0x06) 137 #define MPI26_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 138 MPI26_VERSION_MINOR) 139 #define MPI2_VERSION_02_06 (0x0206) 140 141 /*Unit and Dev versioning for this MPI header set */ 142 #define MPI2_HEADER_VERSION_UNIT (0x27) 143 #define MPI2_HEADER_VERSION_DEV (0x00) 144 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 145 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 146 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 147 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 148 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 149 MPI2_HEADER_VERSION_DEV) 150 151 /***************************************************************************** 152 * 153 * IOC State Definitions 154 * 155 *****************************************************************************/ 156 157 #define MPI2_IOC_STATE_RESET (0x00000000) 158 #define MPI2_IOC_STATE_READY (0x10000000) 159 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000) 160 #define MPI2_IOC_STATE_FAULT (0x40000000) 161 162 #define MPI2_IOC_STATE_MASK (0xF0000000) 163 #define MPI2_IOC_STATE_SHIFT (28) 164 165 /*Fault state range for prodcut specific codes */ 166 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000) 167 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF) 168 169 /***************************************************************************** 170 * 171 * System Interface Register Definitions 172 * 173 *****************************************************************************/ 174 175 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS { 176 U32 Doorbell; /*0x00 */ 177 U32 WriteSequence; /*0x04 */ 178 U32 HostDiagnostic; /*0x08 */ 179 U32 Reserved1; /*0x0C */ 180 U32 DiagRWData; /*0x10 */ 181 U32 DiagRWAddressLow; /*0x14 */ 182 U32 DiagRWAddressHigh; /*0x18 */ 183 U32 Reserved2[5]; /*0x1C */ 184 U32 HostInterruptStatus; /*0x30 */ 185 U32 HostInterruptMask; /*0x34 */ 186 U32 DCRData; /*0x38 */ 187 U32 DCRAddress; /*0x3C */ 188 U32 Reserved3[2]; /*0x40 */ 189 U32 ReplyFreeHostIndex; /*0x48 */ 190 U32 Reserved4[8]; /*0x4C */ 191 U32 ReplyPostHostIndex; /*0x6C */ 192 U32 Reserved5; /*0x70 */ 193 U32 HCBSize; /*0x74 */ 194 U32 HCBAddressLow; /*0x78 */ 195 U32 HCBAddressHigh; /*0x7C */ 196 U32 Reserved6[12]; /*0x80 */ 197 U32 Scratchpad[4]; /*0xB0 */ 198 U32 RequestDescriptorPostLow; /*0xC0 */ 199 U32 RequestDescriptorPostHigh; /*0xC4 */ 200 U32 AtomicRequestDescriptorPost;/*0xC8 */ 201 U32 Reserved7[13]; /*0xCC */ 202 } MPI2_SYSTEM_INTERFACE_REGS, 203 *PTR_MPI2_SYSTEM_INTERFACE_REGS, 204 Mpi2SystemInterfaceRegs_t, 205 *pMpi2SystemInterfaceRegs_t; 206 207 /* 208 *Defines for working with the Doorbell register. 209 */ 210 #define MPI2_DOORBELL_OFFSET (0x00000000) 211 212 /*IOC --> System values */ 213 #define MPI2_DOORBELL_USED (0x08000000) 214 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000) 215 #define MPI2_DOORBELL_WHO_INIT_SHIFT (24) 216 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF) 217 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF) 218 219 /*System --> IOC values */ 220 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000) 221 #define MPI2_DOORBELL_FUNCTION_SHIFT (24) 222 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000) 223 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16) 224 225 /* 226 *Defines for the WriteSequence register 227 */ 228 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 229 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F) 230 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 231 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 232 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 233 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 234 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 235 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 236 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 237 238 /* 239 *Defines for the HostDiagnostic register 240 */ 241 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008) 242 243 #define MPI2_DIAG_SBR_RELOAD (0x00002000) 244 245 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800) 246 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000) 247 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800) 248 249 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) 250 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200) 251 #define MPI2_DIAG_HCB_MODE (0x00000100) 252 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080) 253 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040) 254 #define MPI2_DIAG_RESET_HISTORY (0x00000020) 255 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010) 256 #define MPI2_DIAG_RESET_ADAPTER (0x00000004) 257 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002) 258 259 /* 260 *Offsets for DiagRWData and address 261 */ 262 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010) 263 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014) 264 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018) 265 266 /* 267 *Defines for the HostInterruptStatus register 268 */ 269 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030) 270 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000) 271 #define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS 272 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000) 273 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008) 274 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001) 275 #define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS 276 277 /* 278 *Defines for the HostInterruptMask register 279 */ 280 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034) 281 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000) 282 #define MPI2_HIM_REPLY_INT_MASK (0x00000008) 283 #define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK 284 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001) 285 #define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK 286 287 /* 288 *Offsets for DCRData and address 289 */ 290 #define MPI2_DCR_DATA_OFFSET (0x00000038) 291 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C) 292 293 /* 294 *Offset for the Reply Free Queue 295 */ 296 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048) 297 298 /* 299 *Defines for the Reply Descriptor Post Queue 300 */ 301 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 302 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF) 303 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000) 304 #define MPI2_RPHI_MSIX_INDEX_SHIFT (24) 305 #define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /*MPI v2.5 only*/ 306 307 308 /* 309 *Defines for the HCBSize and address 310 */ 311 #define MPI2_HCB_SIZE_OFFSET (0x00000074) 312 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000) 313 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001) 314 315 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078) 316 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C) 317 318 /* 319 *Offsets for the Scratchpad registers 320 */ 321 #define MPI26_SCRATCHPAD0_OFFSET (0x000000B0) 322 #define MPI26_SCRATCHPAD1_OFFSET (0x000000B4) 323 #define MPI26_SCRATCHPAD2_OFFSET (0x000000B8) 324 #define MPI26_SCRATCHPAD3_OFFSET (0x000000BC) 325 326 /* 327 *Offsets for the Request Descriptor Post Queue 328 */ 329 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0) 330 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4) 331 #define MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET (0x000000C8) 332 333 /*Hard Reset delay timings */ 334 #define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000) 335 #define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000) 336 #define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000) 337 338 /***************************************************************************** 339 * 340 * Message Descriptors 341 * 342 *****************************************************************************/ 343 344 /*Request Descriptors */ 345 346 /*Default Request Descriptor */ 347 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR { 348 U8 RequestFlags; /*0x00 */ 349 U8 MSIxIndex; /*0x01 */ 350 U16 SMID; /*0x02 */ 351 U16 LMID; /*0x04 */ 352 U16 DescriptorTypeDependent; /*0x06 */ 353 } MPI2_DEFAULT_REQUEST_DESCRIPTOR, 354 *PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 355 Mpi2DefaultRequestDescriptor_t, 356 *pMpi2DefaultRequestDescriptor_t; 357 358 /*defines for the RequestFlags field */ 359 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x1E) 360 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_RSHIFT (1) 361 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 362 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 363 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 364 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 365 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 366 #define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C) 367 368 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 369 370 /*High Priority Request Descriptor */ 371 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR { 372 U8 RequestFlags; /*0x00 */ 373 U8 MSIxIndex; /*0x01 */ 374 U16 SMID; /*0x02 */ 375 U16 LMID; /*0x04 */ 376 U16 Reserved1; /*0x06 */ 377 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 378 *PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 379 Mpi2HighPriorityRequestDescriptor_t, 380 *pMpi2HighPriorityRequestDescriptor_t; 381 382 /*SCSI IO Request Descriptor */ 383 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR { 384 U8 RequestFlags; /*0x00 */ 385 U8 MSIxIndex; /*0x01 */ 386 U16 SMID; /*0x02 */ 387 U16 LMID; /*0x04 */ 388 U16 DevHandle; /*0x06 */ 389 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 390 *PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 391 Mpi2SCSIIORequestDescriptor_t, 392 *pMpi2SCSIIORequestDescriptor_t; 393 394 /*SCSI Target Request Descriptor */ 395 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR { 396 U8 RequestFlags; /*0x00 */ 397 U8 MSIxIndex; /*0x01 */ 398 U16 SMID; /*0x02 */ 399 U16 LMID; /*0x04 */ 400 U16 IoIndex; /*0x06 */ 401 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 402 *PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 403 Mpi2SCSITargetRequestDescriptor_t, 404 *pMpi2SCSITargetRequestDescriptor_t; 405 406 /*RAID Accelerator Request Descriptor */ 407 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR { 408 U8 RequestFlags; /*0x00 */ 409 U8 MSIxIndex; /*0x01 */ 410 U16 SMID; /*0x02 */ 411 U16 LMID; /*0x04 */ 412 U16 Reserved; /*0x06 */ 413 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 414 *PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 415 Mpi2RAIDAcceleratorRequestDescriptor_t, 416 *pMpi2RAIDAcceleratorRequestDescriptor_t; 417 418 /*Fast Path SCSI IO Request Descriptor */ 419 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR 420 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR, 421 *PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR, 422 Mpi25FastPathSCSIIORequestDescriptor_t, 423 *pMpi25FastPathSCSIIORequestDescriptor_t; 424 425 /*union of Request Descriptors */ 426 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION { 427 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 428 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 429 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 430 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 431 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 432 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO; 433 U64 Words; 434 } MPI2_REQUEST_DESCRIPTOR_UNION, 435 *PTR_MPI2_REQUEST_DESCRIPTOR_UNION, 436 Mpi2RequestDescriptorUnion_t, 437 *pMpi2RequestDescriptorUnion_t; 438 439 /*Atomic Request Descriptors */ 440 441 /* 442 * All Atomic Request Descriptors have the same format, so the following 443 * structure is used for all Atomic Request Descriptors: 444 * Atomic Default Request Descriptor 445 * Atomic High Priority Request Descriptor 446 * Atomic SCSI IO Request Descriptor 447 * Atomic SCSI Target Request Descriptor 448 * Atomic RAID Accelerator Request Descriptor 449 * Atomic Fast Path SCSI IO Request Descriptor 450 */ 451 452 /*Atomic Request Descriptor */ 453 typedef struct _MPI26_ATOMIC_REQUEST_DESCRIPTOR { 454 U8 RequestFlags; /* 0x00 */ 455 U8 MSIxIndex; /* 0x01 */ 456 U16 SMID; /* 0x02 */ 457 } MPI26_ATOMIC_REQUEST_DESCRIPTOR, 458 *PTR_MPI26_ATOMIC_REQUEST_DESCRIPTOR, 459 Mpi26AtomicRequestDescriptor_t, 460 *pMpi26AtomicRequestDescriptor_t; 461 462 /*for the RequestFlags field, use the same 463 *defines as MPI2_DEFAULT_REQUEST_DESCRIPTOR 464 */ 465 466 /*Reply Descriptors */ 467 468 /*Default Reply Descriptor */ 469 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR { 470 U8 ReplyFlags; /*0x00 */ 471 U8 MSIxIndex; /*0x01 */ 472 U16 DescriptorTypeDependent1; /*0x02 */ 473 U32 DescriptorTypeDependent2; /*0x04 */ 474 } MPI2_DEFAULT_REPLY_DESCRIPTOR, 475 *PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 476 Mpi2DefaultReplyDescriptor_t, 477 *pMpi2DefaultReplyDescriptor_t; 478 479 /*defines for the ReplyFlags field */ 480 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 481 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 482 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 483 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 484 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 485 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 486 #define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06) 487 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 488 489 /*values for marking a reply descriptor as unused */ 490 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 491 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 492 493 /*Address Reply Descriptor */ 494 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR { 495 U8 ReplyFlags; /*0x00 */ 496 U8 MSIxIndex; /*0x01 */ 497 U16 SMID; /*0x02 */ 498 U32 ReplyFrameAddress; /*0x04 */ 499 } MPI2_ADDRESS_REPLY_DESCRIPTOR, 500 *PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 501 Mpi2AddressReplyDescriptor_t, 502 *pMpi2AddressReplyDescriptor_t; 503 504 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00) 505 506 /*SCSI IO Success Reply Descriptor */ 507 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR { 508 U8 ReplyFlags; /*0x00 */ 509 U8 MSIxIndex; /*0x01 */ 510 U16 SMID; /*0x02 */ 511 U16 TaskTag; /*0x04 */ 512 U16 Reserved1; /*0x06 */ 513 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 514 *PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 515 Mpi2SCSIIOSuccessReplyDescriptor_t, 516 *pMpi2SCSIIOSuccessReplyDescriptor_t; 517 518 /*TargetAssist Success Reply Descriptor */ 519 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR { 520 U8 ReplyFlags; /*0x00 */ 521 U8 MSIxIndex; /*0x01 */ 522 U16 SMID; /*0x02 */ 523 U8 SequenceNumber; /*0x04 */ 524 U8 Reserved1; /*0x05 */ 525 U16 IoIndex; /*0x06 */ 526 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 527 *PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 528 Mpi2TargetAssistSuccessReplyDescriptor_t, 529 *pMpi2TargetAssistSuccessReplyDescriptor_t; 530 531 /*Target Command Buffer Reply Descriptor */ 532 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR { 533 U8 ReplyFlags; /*0x00 */ 534 U8 MSIxIndex; /*0x01 */ 535 U8 VP_ID; /*0x02 */ 536 U8 Flags; /*0x03 */ 537 U16 InitiatorDevHandle; /*0x04 */ 538 U16 IoIndex; /*0x06 */ 539 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 540 *PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 541 Mpi2TargetCommandBufferReplyDescriptor_t, 542 *pMpi2TargetCommandBufferReplyDescriptor_t; 543 544 /*defines for Flags field */ 545 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F) 546 547 /*RAID Accelerator Success Reply Descriptor */ 548 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR { 549 U8 ReplyFlags; /*0x00 */ 550 U8 MSIxIndex; /*0x01 */ 551 U16 SMID; /*0x02 */ 552 U32 Reserved; /*0x04 */ 553 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 554 *PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 555 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, 556 *pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 557 558 /*Fast Path SCSI IO Success Reply Descriptor */ 559 typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 560 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 561 *PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 562 Mpi25FastPathSCSIIOSuccessReplyDescriptor_t, 563 *pMpi25FastPathSCSIIOSuccessReplyDescriptor_t; 564 565 /*union of Reply Descriptors */ 566 typedef union _MPI2_REPLY_DESCRIPTORS_UNION { 567 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 568 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 569 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 570 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 571 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 572 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 573 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess; 574 U64 Words; 575 } MPI2_REPLY_DESCRIPTORS_UNION, 576 *PTR_MPI2_REPLY_DESCRIPTORS_UNION, 577 Mpi2ReplyDescriptorsUnion_t, 578 *pMpi2ReplyDescriptorsUnion_t; 579 580 /***************************************************************************** 581 * 582 * Message Functions 583 * 584 *****************************************************************************/ 585 586 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) 587 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) 588 #define MPI2_FUNCTION_IOC_INIT (0x02) 589 #define MPI2_FUNCTION_IOC_FACTS (0x03) 590 #define MPI2_FUNCTION_CONFIG (0x04) 591 #define MPI2_FUNCTION_PORT_FACTS (0x05) 592 #define MPI2_FUNCTION_PORT_ENABLE (0x06) 593 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) 594 #define MPI2_FUNCTION_EVENT_ACK (0x08) 595 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) 596 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) 597 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) 598 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) 599 #define MPI2_FUNCTION_FW_UPLOAD (0x12) 600 #define MPI2_FUNCTION_RAID_ACTION (0x15) 601 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) 602 #define MPI2_FUNCTION_TOOLBOX (0x17) 603 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) 604 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) 605 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) 606 #define MPI2_FUNCTION_IO_UNIT_CONTROL (0x1B) 607 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) 608 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) 609 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) 610 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) 611 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) 612 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) 613 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) 614 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) 615 #define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31) 616 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) 617 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) 618 619 /*Doorbell functions */ 620 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 621 #define MPI2_FUNCTION_HANDSHAKE (0x42) 622 623 /***************************************************************************** 624 * 625 * IOC Status Values 626 * 627 *****************************************************************************/ 628 629 /*mask for IOCStatus status value */ 630 #define MPI2_IOCSTATUS_MASK (0x7FFF) 631 632 /**************************************************************************** 633 * Common IOCStatus values for all replies 634 ****************************************************************************/ 635 636 #define MPI2_IOCSTATUS_SUCCESS (0x0000) 637 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001) 638 #define MPI2_IOCSTATUS_BUSY (0x0002) 639 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003) 640 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004) 641 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005) 642 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 643 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007) 644 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008) 645 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) 646 #define MPI2_IOCSTATUS_INSUFFICIENT_POWER (0x000A) 647 648 /**************************************************************************** 649 * Config IOCStatus values 650 ****************************************************************************/ 651 652 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 653 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 654 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 655 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 656 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 657 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 658 659 /**************************************************************************** 660 * SCSI IO Reply 661 ****************************************************************************/ 662 663 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 664 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 665 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 666 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 667 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 668 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 669 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 670 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 671 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 672 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) 673 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) 674 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) 675 676 /**************************************************************************** 677 * For use by SCSI Initiator and SCSI Target end-to-end data protection 678 ****************************************************************************/ 679 680 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D) 681 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E) 682 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F) 683 684 /**************************************************************************** 685 * SCSI Target values 686 ****************************************************************************/ 687 688 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 689 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063) 690 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 691 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 692 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) 693 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D) 694 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E) 695 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F) 696 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 697 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 698 699 /**************************************************************************** 700 * Serial Attached SCSI values 701 ****************************************************************************/ 702 703 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 704 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 705 706 /**************************************************************************** 707 * Diagnostic Buffer Post / Diagnostic Release values 708 ****************************************************************************/ 709 710 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0) 711 712 /**************************************************************************** 713 * RAID Accelerator values 714 ****************************************************************************/ 715 716 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0) 717 718 /**************************************************************************** 719 * IOCStatus flag to indicate that log info is available 720 ****************************************************************************/ 721 722 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000) 723 724 /**************************************************************************** 725 * IOCLogInfo Types 726 ****************************************************************************/ 727 728 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000) 729 #define MPI2_IOCLOGINFO_TYPE_SHIFT (28) 730 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0) 731 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1) 732 #define MPI2_IOCLOGINFO_TYPE_FC (0x2) 733 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3) 734 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4) 735 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) 736 737 /***************************************************************************** 738 * 739 * Standard Message Structures 740 * 741 *****************************************************************************/ 742 743 /**************************************************************************** 744 *Request Message Header for all request messages 745 ****************************************************************************/ 746 747 typedef struct _MPI2_REQUEST_HEADER { 748 U16 FunctionDependent1; /*0x00 */ 749 U8 ChainOffset; /*0x02 */ 750 U8 Function; /*0x03 */ 751 U16 FunctionDependent2; /*0x04 */ 752 U8 FunctionDependent3; /*0x06 */ 753 U8 MsgFlags; /*0x07 */ 754 U8 VP_ID; /*0x08 */ 755 U8 VF_ID; /*0x09 */ 756 U16 Reserved1; /*0x0A */ 757 } MPI2_REQUEST_HEADER, *PTR_MPI2_REQUEST_HEADER, 758 MPI2RequestHeader_t, *pMPI2RequestHeader_t; 759 760 /**************************************************************************** 761 * Default Reply 762 ****************************************************************************/ 763 764 typedef struct _MPI2_DEFAULT_REPLY { 765 U16 FunctionDependent1; /*0x00 */ 766 U8 MsgLength; /*0x02 */ 767 U8 Function; /*0x03 */ 768 U16 FunctionDependent2; /*0x04 */ 769 U8 FunctionDependent3; /*0x06 */ 770 U8 MsgFlags; /*0x07 */ 771 U8 VP_ID; /*0x08 */ 772 U8 VF_ID; /*0x09 */ 773 U16 Reserved1; /*0x0A */ 774 U16 FunctionDependent5; /*0x0C */ 775 U16 IOCStatus; /*0x0E */ 776 U32 IOCLogInfo; /*0x10 */ 777 } MPI2_DEFAULT_REPLY, *PTR_MPI2_DEFAULT_REPLY, 778 MPI2DefaultReply_t, *pMPI2DefaultReply_t; 779 780 /*common version structure/union used in messages and configuration pages */ 781 782 typedef struct _MPI2_VERSION_STRUCT { 783 U8 Dev; /*0x00 */ 784 U8 Unit; /*0x01 */ 785 U8 Minor; /*0x02 */ 786 U8 Major; /*0x03 */ 787 } MPI2_VERSION_STRUCT; 788 789 typedef union _MPI2_VERSION_UNION { 790 MPI2_VERSION_STRUCT Struct; 791 U32 Word; 792 } MPI2_VERSION_UNION; 793 794 /*LUN field defines, common to many structures */ 795 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) 796 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) 797 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) 798 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) 799 #define MPI2_LUN_LEVEL_1_WORD (0xFF00) 800 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00) 801 802 /***************************************************************************** 803 * 804 * Fusion-MPT MPI Scatter Gather Elements 805 * 806 *****************************************************************************/ 807 808 /**************************************************************************** 809 * MPI Simple Element structures 810 ****************************************************************************/ 811 812 typedef struct _MPI2_SGE_SIMPLE32 { 813 U32 FlagsLength; 814 U32 Address; 815 } MPI2_SGE_SIMPLE32, *PTR_MPI2_SGE_SIMPLE32, 816 Mpi2SGESimple32_t, *pMpi2SGESimple32_t; 817 818 typedef struct _MPI2_SGE_SIMPLE64 { 819 U32 FlagsLength; 820 U64 Address; 821 } MPI2_SGE_SIMPLE64, *PTR_MPI2_SGE_SIMPLE64, 822 Mpi2SGESimple64_t, *pMpi2SGESimple64_t; 823 824 typedef struct _MPI2_SGE_SIMPLE_UNION { 825 U32 FlagsLength; 826 union { 827 U32 Address32; 828 U64 Address64; 829 } u; 830 } MPI2_SGE_SIMPLE_UNION, 831 *PTR_MPI2_SGE_SIMPLE_UNION, 832 Mpi2SGESimpleUnion_t, 833 *pMpi2SGESimpleUnion_t; 834 835 /**************************************************************************** 836 * MPI Chain Element structures - for MPI v2.0 products only 837 ****************************************************************************/ 838 839 typedef struct _MPI2_SGE_CHAIN32 { 840 U16 Length; 841 U8 NextChainOffset; 842 U8 Flags; 843 U32 Address; 844 } MPI2_SGE_CHAIN32, *PTR_MPI2_SGE_CHAIN32, 845 Mpi2SGEChain32_t, *pMpi2SGEChain32_t; 846 847 typedef struct _MPI2_SGE_CHAIN64 { 848 U16 Length; 849 U8 NextChainOffset; 850 U8 Flags; 851 U64 Address; 852 } MPI2_SGE_CHAIN64, *PTR_MPI2_SGE_CHAIN64, 853 Mpi2SGEChain64_t, *pMpi2SGEChain64_t; 854 855 typedef struct _MPI2_SGE_CHAIN_UNION { 856 U16 Length; 857 U8 NextChainOffset; 858 U8 Flags; 859 union { 860 U32 Address32; 861 U64 Address64; 862 } u; 863 } MPI2_SGE_CHAIN_UNION, 864 *PTR_MPI2_SGE_CHAIN_UNION, 865 Mpi2SGEChainUnion_t, 866 *pMpi2SGEChainUnion_t; 867 868 /**************************************************************************** 869 * MPI Transaction Context Element structures - for MPI v2.0 products only 870 ****************************************************************************/ 871 872 typedef struct _MPI2_SGE_TRANSACTION32 { 873 U8 Reserved; 874 U8 ContextSize; 875 U8 DetailsLength; 876 U8 Flags; 877 U32 TransactionContext[1]; 878 U32 TransactionDetails[1]; 879 } MPI2_SGE_TRANSACTION32, 880 *PTR_MPI2_SGE_TRANSACTION32, 881 Mpi2SGETransaction32_t, 882 *pMpi2SGETransaction32_t; 883 884 typedef struct _MPI2_SGE_TRANSACTION64 { 885 U8 Reserved; 886 U8 ContextSize; 887 U8 DetailsLength; 888 U8 Flags; 889 U32 TransactionContext[2]; 890 U32 TransactionDetails[1]; 891 } MPI2_SGE_TRANSACTION64, 892 *PTR_MPI2_SGE_TRANSACTION64, 893 Mpi2SGETransaction64_t, 894 *pMpi2SGETransaction64_t; 895 896 typedef struct _MPI2_SGE_TRANSACTION96 { 897 U8 Reserved; 898 U8 ContextSize; 899 U8 DetailsLength; 900 U8 Flags; 901 U32 TransactionContext[3]; 902 U32 TransactionDetails[1]; 903 } MPI2_SGE_TRANSACTION96, *PTR_MPI2_SGE_TRANSACTION96, 904 Mpi2SGETransaction96_t, *pMpi2SGETransaction96_t; 905 906 typedef struct _MPI2_SGE_TRANSACTION128 { 907 U8 Reserved; 908 U8 ContextSize; 909 U8 DetailsLength; 910 U8 Flags; 911 U32 TransactionContext[4]; 912 U32 TransactionDetails[1]; 913 } MPI2_SGE_TRANSACTION128, *PTR_MPI2_SGE_TRANSACTION128, 914 Mpi2SGETransaction_t128, *pMpi2SGETransaction_t128; 915 916 typedef struct _MPI2_SGE_TRANSACTION_UNION { 917 U8 Reserved; 918 U8 ContextSize; 919 U8 DetailsLength; 920 U8 Flags; 921 union { 922 U32 TransactionContext32[1]; 923 U32 TransactionContext64[2]; 924 U32 TransactionContext96[3]; 925 U32 TransactionContext128[4]; 926 } u; 927 U32 TransactionDetails[1]; 928 } MPI2_SGE_TRANSACTION_UNION, 929 *PTR_MPI2_SGE_TRANSACTION_UNION, 930 Mpi2SGETransactionUnion_t, 931 *pMpi2SGETransactionUnion_t; 932 933 /**************************************************************************** 934 * MPI SGE union for IO SGL's - for MPI v2.0 products only 935 ****************************************************************************/ 936 937 typedef struct _MPI2_MPI_SGE_IO_UNION { 938 union { 939 MPI2_SGE_SIMPLE_UNION Simple; 940 MPI2_SGE_CHAIN_UNION Chain; 941 } u; 942 } MPI2_MPI_SGE_IO_UNION, *PTR_MPI2_MPI_SGE_IO_UNION, 943 Mpi2MpiSGEIOUnion_t, *pMpi2MpiSGEIOUnion_t; 944 945 /**************************************************************************** 946 * MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only 947 ****************************************************************************/ 948 949 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION { 950 union { 951 MPI2_SGE_SIMPLE_UNION Simple; 952 MPI2_SGE_TRANSACTION_UNION Transaction; 953 } u; 954 } MPI2_SGE_TRANS_SIMPLE_UNION, 955 *PTR_MPI2_SGE_TRANS_SIMPLE_UNION, 956 Mpi2SGETransSimpleUnion_t, 957 *pMpi2SGETransSimpleUnion_t; 958 959 /**************************************************************************** 960 * All MPI SGE types union 961 ****************************************************************************/ 962 963 typedef struct _MPI2_MPI_SGE_UNION { 964 union { 965 MPI2_SGE_SIMPLE_UNION Simple; 966 MPI2_SGE_CHAIN_UNION Chain; 967 MPI2_SGE_TRANSACTION_UNION Transaction; 968 } u; 969 } MPI2_MPI_SGE_UNION, *PTR_MPI2_MPI_SGE_UNION, 970 Mpi2MpiSgeUnion_t, *pMpi2MpiSgeUnion_t; 971 972 /**************************************************************************** 973 * MPI SGE field definition and masks 974 ****************************************************************************/ 975 976 /*Flags field bit definitions */ 977 978 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80) 979 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40) 980 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30) 981 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08) 982 #define MPI2_SGE_FLAGS_DIRECTION (0x04) 983 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02) 984 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01) 985 986 #define MPI2_SGE_FLAGS_SHIFT (24) 987 988 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF) 989 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF) 990 991 /*Element Type */ 992 993 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) 994 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10) 995 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30) 996 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30) 997 998 /*Address location */ 999 1000 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00) 1001 1002 /*Direction */ 1003 1004 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00) 1005 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04) 1006 1007 #define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST) 1008 #define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC) 1009 1010 /*Address Size */ 1011 1012 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 1013 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 1014 1015 /*Context Size */ 1016 1017 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00) 1018 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02) 1019 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04) 1020 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06) 1021 1022 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000) 1023 #define MPI2_SGE_CHAIN_OFFSET_SHIFT (16) 1024 1025 /**************************************************************************** 1026 * MPI SGE operation Macros 1027 ****************************************************************************/ 1028 1029 /*SIMPLE FlagsLength manipulations... */ 1030 #define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT) 1031 #define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> \ 1032 MPI2_SGE_FLAGS_SHIFT) 1033 #define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK) 1034 #define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK) 1035 1036 #define MPI2_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_SGE_SET_FLAGS(f) | \ 1037 MPI2_SGE_LENGTH(l)) 1038 1039 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength) 1040 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength) 1041 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \ 1042 MPI2_SGE_SET_FLAGS_LENGTH(f, l)) 1043 1044 /*CAUTION - The following are READ-MODIFY-WRITE! */ 1045 #define MPI2_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \ 1046 MPI2_SGE_SET_FLAGS(f)) 1047 #define MPI2_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \ 1048 MPI2_SGE_LENGTH(l)) 1049 1050 #define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> \ 1051 MPI2_SGE_CHAIN_OFFSET_SHIFT) 1052 1053 /***************************************************************************** 1054 * 1055 * Fusion-MPT IEEE Scatter Gather Elements 1056 * 1057 *****************************************************************************/ 1058 1059 /**************************************************************************** 1060 * IEEE Simple Element structures 1061 ****************************************************************************/ 1062 1063 /*MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */ 1064 typedef struct _MPI2_IEEE_SGE_SIMPLE32 { 1065 U32 Address; 1066 U32 FlagsLength; 1067 } MPI2_IEEE_SGE_SIMPLE32, *PTR_MPI2_IEEE_SGE_SIMPLE32, 1068 Mpi2IeeeSgeSimple32_t, *pMpi2IeeeSgeSimple32_t; 1069 1070 typedef struct _MPI2_IEEE_SGE_SIMPLE64 { 1071 U64 Address; 1072 U32 Length; 1073 U16 Reserved1; 1074 U8 Reserved2; 1075 U8 Flags; 1076 } MPI2_IEEE_SGE_SIMPLE64, *PTR_MPI2_IEEE_SGE_SIMPLE64, 1077 Mpi2IeeeSgeSimple64_t, *pMpi2IeeeSgeSimple64_t; 1078 1079 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION { 1080 MPI2_IEEE_SGE_SIMPLE32 Simple32; 1081 MPI2_IEEE_SGE_SIMPLE64 Simple64; 1082 } MPI2_IEEE_SGE_SIMPLE_UNION, 1083 *PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 1084 Mpi2IeeeSgeSimpleUnion_t, 1085 *pMpi2IeeeSgeSimpleUnion_t; 1086 1087 /**************************************************************************** 1088 * IEEE Chain Element structures 1089 ****************************************************************************/ 1090 1091 /*MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */ 1092 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 1093 1094 /*MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */ 1095 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 1096 1097 typedef union _MPI2_IEEE_SGE_CHAIN_UNION { 1098 MPI2_IEEE_SGE_CHAIN32 Chain32; 1099 MPI2_IEEE_SGE_CHAIN64 Chain64; 1100 } MPI2_IEEE_SGE_CHAIN_UNION, 1101 *PTR_MPI2_IEEE_SGE_CHAIN_UNION, 1102 Mpi2IeeeSgeChainUnion_t, 1103 *pMpi2IeeeSgeChainUnion_t; 1104 1105 /*MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 and later */ 1106 typedef struct _MPI25_IEEE_SGE_CHAIN64 { 1107 U64 Address; 1108 U32 Length; 1109 U16 Reserved1; 1110 U8 NextChainOffset; 1111 U8 Flags; 1112 } MPI25_IEEE_SGE_CHAIN64, 1113 *PTR_MPI25_IEEE_SGE_CHAIN64, 1114 Mpi25IeeeSgeChain64_t, 1115 *pMpi25IeeeSgeChain64_t; 1116 1117 /**************************************************************************** 1118 * All IEEE SGE types union 1119 ****************************************************************************/ 1120 1121 /*MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */ 1122 typedef struct _MPI2_IEEE_SGE_UNION { 1123 union { 1124 MPI2_IEEE_SGE_SIMPLE_UNION Simple; 1125 MPI2_IEEE_SGE_CHAIN_UNION Chain; 1126 } u; 1127 } MPI2_IEEE_SGE_UNION, *PTR_MPI2_IEEE_SGE_UNION, 1128 Mpi2IeeeSgeUnion_t, *pMpi2IeeeSgeUnion_t; 1129 1130 /**************************************************************************** 1131 * IEEE SGE union for IO SGL's 1132 ****************************************************************************/ 1133 1134 typedef union _MPI25_SGE_IO_UNION { 1135 MPI2_IEEE_SGE_SIMPLE64 IeeeSimple; 1136 MPI25_IEEE_SGE_CHAIN64 IeeeChain; 1137 } MPI25_SGE_IO_UNION, *PTR_MPI25_SGE_IO_UNION, 1138 Mpi25SGEIOUnion_t, *pMpi25SGEIOUnion_t; 1139 1140 /**************************************************************************** 1141 * IEEE SGE field definitions and masks 1142 ****************************************************************************/ 1143 1144 /*Flags field bit definitions */ 1145 1146 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1147 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1148 1149 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1150 1151 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1152 1153 /*Element Type */ 1154 1155 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1156 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1157 1158 /*Next Segment Format */ 1159 1160 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C) 1161 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00) 1162 1163 /*Data Location Address Space */ 1164 1165 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1166 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1167 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1168 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1169 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1170 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03) 1171 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR \ 1172 (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) 1173 #define MPI26_IEEE_SGE_FLAGS_IOCCTL_ADDR (0x02) 1174 1175 /**************************************************************************** 1176 * IEEE SGE operation Macros 1177 ****************************************************************************/ 1178 1179 /*SIMPLE FlagsLength manipulations... */ 1180 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT) 1181 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) \ 1182 >> MPI2_IEEE32_SGE_FLAGS_SHIFT) 1183 #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK) 1184 1185 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) |\ 1186 MPI2_IEEE32_SGE_LENGTH(l)) 1187 1188 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) \ 1189 MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength) 1190 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) \ 1191 MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength) 1192 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \ 1193 MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l)) 1194 1195 /*CAUTION - The following are READ-MODIFY-WRITE! */ 1196 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \ 1197 MPI2_IEEE32_SGE_SET_FLAGS(f)) 1198 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \ 1199 MPI2_IEEE32_SGE_LENGTH(l)) 1200 1201 /***************************************************************************** 1202 * 1203 * Fusion-MPT MPI/IEEE Scatter Gather Unions 1204 * 1205 *****************************************************************************/ 1206 1207 typedef union _MPI2_SIMPLE_SGE_UNION { 1208 MPI2_SGE_SIMPLE_UNION MpiSimple; 1209 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1210 } MPI2_SIMPLE_SGE_UNION, *PTR_MPI2_SIMPLE_SGE_UNION, 1211 Mpi2SimpleSgeUntion_t, *pMpi2SimpleSgeUntion_t; 1212 1213 typedef union _MPI2_SGE_IO_UNION { 1214 MPI2_SGE_SIMPLE_UNION MpiSimple; 1215 MPI2_SGE_CHAIN_UNION MpiChain; 1216 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1217 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1218 } MPI2_SGE_IO_UNION, *PTR_MPI2_SGE_IO_UNION, 1219 Mpi2SGEIOUnion_t, *pMpi2SGEIOUnion_t; 1220 1221 /**************************************************************************** 1222 * 1223 * Values for SGLFlags field, used in many request messages with an SGL 1224 * 1225 ****************************************************************************/ 1226 1227 /*values for MPI SGL Data Location Address Space subfield */ 1228 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C) 1229 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00) 1230 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04) 1231 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) 1232 #define MPI26_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) 1233 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) 1234 /*values for SGL Type subfield */ 1235 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03) 1236 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00) 1237 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) 1238 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02) 1239 1240 #endif 1241