1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for Broadcom MPI3 Storage Controllers 4 * 5 * Copyright (C) 2017-2023 Broadcom Inc. 6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com) 7 * 8 */ 9 10 #include "mpi3mr.h" 11 #include <linux/io-64-nonatomic-lo-hi.h> 12 13 static int 14 mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, u32 reset_reason); 15 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc); 16 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc, 17 struct mpi3_ioc_facts_data *facts_data); 18 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc, 19 struct mpi3mr_drv_cmd *drv_cmd); 20 21 static int poll_queues; 22 module_param(poll_queues, int, 0444); 23 MODULE_PARM_DESC(poll_queues, "Number of queues for io_uring poll mode. (Range 1 - 126)"); 24 25 #if defined(writeq) && defined(CONFIG_64BIT) 26 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr) 27 { 28 writeq(b, addr); 29 } 30 #else 31 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr) 32 { 33 __u64 data_out = b; 34 35 writel((u32)(data_out), addr); 36 writel((u32)(data_out >> 32), (addr + 4)); 37 } 38 #endif 39 40 static inline bool 41 mpi3mr_check_req_qfull(struct op_req_qinfo *op_req_q) 42 { 43 u16 pi, ci, max_entries; 44 bool is_qfull = false; 45 46 pi = op_req_q->pi; 47 ci = READ_ONCE(op_req_q->ci); 48 max_entries = op_req_q->num_requests; 49 50 if ((ci == (pi + 1)) || ((!ci) && (pi == (max_entries - 1)))) 51 is_qfull = true; 52 53 return is_qfull; 54 } 55 56 static void mpi3mr_sync_irqs(struct mpi3mr_ioc *mrioc) 57 { 58 u16 i, max_vectors; 59 60 max_vectors = mrioc->intr_info_count; 61 62 for (i = 0; i < max_vectors; i++) 63 synchronize_irq(pci_irq_vector(mrioc->pdev, i)); 64 } 65 66 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc) 67 { 68 mrioc->intr_enabled = 0; 69 mpi3mr_sync_irqs(mrioc); 70 } 71 72 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc) 73 { 74 mrioc->intr_enabled = 1; 75 } 76 77 static void mpi3mr_cleanup_isr(struct mpi3mr_ioc *mrioc) 78 { 79 u16 i; 80 81 mpi3mr_ioc_disable_intr(mrioc); 82 83 if (!mrioc->intr_info) 84 return; 85 86 for (i = 0; i < mrioc->intr_info_count; i++) 87 free_irq(pci_irq_vector(mrioc->pdev, i), 88 (mrioc->intr_info + i)); 89 90 kfree(mrioc->intr_info); 91 mrioc->intr_info = NULL; 92 mrioc->intr_info_count = 0; 93 mrioc->is_intr_info_set = false; 94 pci_free_irq_vectors(mrioc->pdev); 95 } 96 97 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length, 98 dma_addr_t dma_addr) 99 { 100 struct mpi3_sge_common *sgel = paddr; 101 102 sgel->flags = flags; 103 sgel->length = cpu_to_le32(length); 104 sgel->address = cpu_to_le64(dma_addr); 105 } 106 107 void mpi3mr_build_zero_len_sge(void *paddr) 108 { 109 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 110 111 mpi3mr_add_sg_single(paddr, sgl_flags, 0, -1); 112 } 113 114 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc, 115 dma_addr_t phys_addr) 116 { 117 if (!phys_addr) 118 return NULL; 119 120 if ((phys_addr < mrioc->reply_buf_dma) || 121 (phys_addr > mrioc->reply_buf_dma_max_address)) 122 return NULL; 123 124 return mrioc->reply_buf + (phys_addr - mrioc->reply_buf_dma); 125 } 126 127 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc, 128 dma_addr_t phys_addr) 129 { 130 if (!phys_addr) 131 return NULL; 132 133 return mrioc->sense_buf + (phys_addr - mrioc->sense_buf_dma); 134 } 135 136 static void mpi3mr_repost_reply_buf(struct mpi3mr_ioc *mrioc, 137 u64 reply_dma) 138 { 139 u32 old_idx = 0; 140 unsigned long flags; 141 142 spin_lock_irqsave(&mrioc->reply_free_queue_lock, flags); 143 old_idx = mrioc->reply_free_queue_host_index; 144 mrioc->reply_free_queue_host_index = ( 145 (mrioc->reply_free_queue_host_index == 146 (mrioc->reply_free_qsz - 1)) ? 0 : 147 (mrioc->reply_free_queue_host_index + 1)); 148 mrioc->reply_free_q[old_idx] = cpu_to_le64(reply_dma); 149 writel(mrioc->reply_free_queue_host_index, 150 &mrioc->sysif_regs->reply_free_host_index); 151 spin_unlock_irqrestore(&mrioc->reply_free_queue_lock, flags); 152 } 153 154 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc, 155 u64 sense_buf_dma) 156 { 157 u32 old_idx = 0; 158 unsigned long flags; 159 160 spin_lock_irqsave(&mrioc->sbq_lock, flags); 161 old_idx = mrioc->sbq_host_index; 162 mrioc->sbq_host_index = ((mrioc->sbq_host_index == 163 (mrioc->sense_buf_q_sz - 1)) ? 0 : 164 (mrioc->sbq_host_index + 1)); 165 mrioc->sense_buf_q[old_idx] = cpu_to_le64(sense_buf_dma); 166 writel(mrioc->sbq_host_index, 167 &mrioc->sysif_regs->sense_buffer_free_host_index); 168 spin_unlock_irqrestore(&mrioc->sbq_lock, flags); 169 } 170 171 static void mpi3mr_print_event_data(struct mpi3mr_ioc *mrioc, 172 struct mpi3_event_notification_reply *event_reply) 173 { 174 char *desc = NULL; 175 u16 event; 176 177 event = event_reply->event; 178 179 switch (event) { 180 case MPI3_EVENT_LOG_DATA: 181 desc = "Log Data"; 182 break; 183 case MPI3_EVENT_CHANGE: 184 desc = "Event Change"; 185 break; 186 case MPI3_EVENT_GPIO_INTERRUPT: 187 desc = "GPIO Interrupt"; 188 break; 189 case MPI3_EVENT_CABLE_MGMT: 190 desc = "Cable Management"; 191 break; 192 case MPI3_EVENT_ENERGY_PACK_CHANGE: 193 desc = "Energy Pack Change"; 194 break; 195 case MPI3_EVENT_DEVICE_ADDED: 196 { 197 struct mpi3_device_page0 *event_data = 198 (struct mpi3_device_page0 *)event_reply->event_data; 199 ioc_info(mrioc, "Device Added: dev=0x%04x Form=0x%x\n", 200 event_data->dev_handle, event_data->device_form); 201 return; 202 } 203 case MPI3_EVENT_DEVICE_INFO_CHANGED: 204 { 205 struct mpi3_device_page0 *event_data = 206 (struct mpi3_device_page0 *)event_reply->event_data; 207 ioc_info(mrioc, "Device Info Changed: dev=0x%04x Form=0x%x\n", 208 event_data->dev_handle, event_data->device_form); 209 return; 210 } 211 case MPI3_EVENT_DEVICE_STATUS_CHANGE: 212 { 213 struct mpi3_event_data_device_status_change *event_data = 214 (struct mpi3_event_data_device_status_change *)event_reply->event_data; 215 ioc_info(mrioc, "Device status Change: dev=0x%04x RC=0x%x\n", 216 event_data->dev_handle, event_data->reason_code); 217 return; 218 } 219 case MPI3_EVENT_SAS_DISCOVERY: 220 { 221 struct mpi3_event_data_sas_discovery *event_data = 222 (struct mpi3_event_data_sas_discovery *)event_reply->event_data; 223 ioc_info(mrioc, "SAS Discovery: (%s) status (0x%08x)\n", 224 (event_data->reason_code == MPI3_EVENT_SAS_DISC_RC_STARTED) ? 225 "start" : "stop", 226 le32_to_cpu(event_data->discovery_status)); 227 return; 228 } 229 case MPI3_EVENT_SAS_BROADCAST_PRIMITIVE: 230 desc = "SAS Broadcast Primitive"; 231 break; 232 case MPI3_EVENT_SAS_NOTIFY_PRIMITIVE: 233 desc = "SAS Notify Primitive"; 234 break; 235 case MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE: 236 desc = "SAS Init Device Status Change"; 237 break; 238 case MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW: 239 desc = "SAS Init Table Overflow"; 240 break; 241 case MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 242 desc = "SAS Topology Change List"; 243 break; 244 case MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE: 245 desc = "Enclosure Device Status Change"; 246 break; 247 case MPI3_EVENT_ENCL_DEVICE_ADDED: 248 desc = "Enclosure Added"; 249 break; 250 case MPI3_EVENT_HARD_RESET_RECEIVED: 251 desc = "Hard Reset Received"; 252 break; 253 case MPI3_EVENT_SAS_PHY_COUNTER: 254 desc = "SAS PHY Counter"; 255 break; 256 case MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR: 257 desc = "SAS Device Discovery Error"; 258 break; 259 case MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST: 260 desc = "PCIE Topology Change List"; 261 break; 262 case MPI3_EVENT_PCIE_ENUMERATION: 263 { 264 struct mpi3_event_data_pcie_enumeration *event_data = 265 (struct mpi3_event_data_pcie_enumeration *)event_reply->event_data; 266 ioc_info(mrioc, "PCIE Enumeration: (%s)", 267 (event_data->reason_code == 268 MPI3_EVENT_PCIE_ENUM_RC_STARTED) ? "start" : "stop"); 269 if (event_data->enumeration_status) 270 ioc_info(mrioc, "enumeration_status(0x%08x)\n", 271 le32_to_cpu(event_data->enumeration_status)); 272 return; 273 } 274 case MPI3_EVENT_PREPARE_FOR_RESET: 275 desc = "Prepare For Reset"; 276 break; 277 } 278 279 if (!desc) 280 return; 281 282 ioc_info(mrioc, "%s\n", desc); 283 } 284 285 static void mpi3mr_handle_events(struct mpi3mr_ioc *mrioc, 286 struct mpi3_default_reply *def_reply) 287 { 288 struct mpi3_event_notification_reply *event_reply = 289 (struct mpi3_event_notification_reply *)def_reply; 290 291 mrioc->change_count = le16_to_cpu(event_reply->ioc_change_count); 292 mpi3mr_print_event_data(mrioc, event_reply); 293 mpi3mr_os_handle_events(mrioc, event_reply); 294 } 295 296 static struct mpi3mr_drv_cmd * 297 mpi3mr_get_drv_cmd(struct mpi3mr_ioc *mrioc, u16 host_tag, 298 struct mpi3_default_reply *def_reply) 299 { 300 u16 idx; 301 302 switch (host_tag) { 303 case MPI3MR_HOSTTAG_INITCMDS: 304 return &mrioc->init_cmds; 305 case MPI3MR_HOSTTAG_CFG_CMDS: 306 return &mrioc->cfg_cmds; 307 case MPI3MR_HOSTTAG_BSG_CMDS: 308 return &mrioc->bsg_cmds; 309 case MPI3MR_HOSTTAG_BLK_TMS: 310 return &mrioc->host_tm_cmds; 311 case MPI3MR_HOSTTAG_PEL_ABORT: 312 return &mrioc->pel_abort_cmd; 313 case MPI3MR_HOSTTAG_PEL_WAIT: 314 return &mrioc->pel_cmds; 315 case MPI3MR_HOSTTAG_TRANSPORT_CMDS: 316 return &mrioc->transport_cmds; 317 case MPI3MR_HOSTTAG_INVALID: 318 if (def_reply && def_reply->function == 319 MPI3_FUNCTION_EVENT_NOTIFICATION) 320 mpi3mr_handle_events(mrioc, def_reply); 321 return NULL; 322 default: 323 break; 324 } 325 if (host_tag >= MPI3MR_HOSTTAG_DEVRMCMD_MIN && 326 host_tag <= MPI3MR_HOSTTAG_DEVRMCMD_MAX) { 327 idx = host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN; 328 return &mrioc->dev_rmhs_cmds[idx]; 329 } 330 331 if (host_tag >= MPI3MR_HOSTTAG_EVTACKCMD_MIN && 332 host_tag <= MPI3MR_HOSTTAG_EVTACKCMD_MAX) { 333 idx = host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN; 334 return &mrioc->evtack_cmds[idx]; 335 } 336 337 return NULL; 338 } 339 340 static void mpi3mr_process_admin_reply_desc(struct mpi3mr_ioc *mrioc, 341 struct mpi3_default_reply_descriptor *reply_desc, u64 *reply_dma) 342 { 343 u16 reply_desc_type, host_tag = 0; 344 u16 ioc_status = MPI3_IOCSTATUS_SUCCESS; 345 u32 ioc_loginfo = 0; 346 struct mpi3_status_reply_descriptor *status_desc; 347 struct mpi3_address_reply_descriptor *addr_desc; 348 struct mpi3_success_reply_descriptor *success_desc; 349 struct mpi3_default_reply *def_reply = NULL; 350 struct mpi3mr_drv_cmd *cmdptr = NULL; 351 struct mpi3_scsi_io_reply *scsi_reply; 352 u8 *sense_buf = NULL; 353 354 *reply_dma = 0; 355 reply_desc_type = le16_to_cpu(reply_desc->reply_flags) & 356 MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK; 357 switch (reply_desc_type) { 358 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS: 359 status_desc = (struct mpi3_status_reply_descriptor *)reply_desc; 360 host_tag = le16_to_cpu(status_desc->host_tag); 361 ioc_status = le16_to_cpu(status_desc->ioc_status); 362 if (ioc_status & 363 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL) 364 ioc_loginfo = le32_to_cpu(status_desc->ioc_log_info); 365 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK; 366 break; 367 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY: 368 addr_desc = (struct mpi3_address_reply_descriptor *)reply_desc; 369 *reply_dma = le64_to_cpu(addr_desc->reply_frame_address); 370 def_reply = mpi3mr_get_reply_virt_addr(mrioc, *reply_dma); 371 if (!def_reply) 372 goto out; 373 host_tag = le16_to_cpu(def_reply->host_tag); 374 ioc_status = le16_to_cpu(def_reply->ioc_status); 375 if (ioc_status & 376 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL) 377 ioc_loginfo = le32_to_cpu(def_reply->ioc_log_info); 378 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK; 379 if (def_reply->function == MPI3_FUNCTION_SCSI_IO) { 380 scsi_reply = (struct mpi3_scsi_io_reply *)def_reply; 381 sense_buf = mpi3mr_get_sensebuf_virt_addr(mrioc, 382 le64_to_cpu(scsi_reply->sense_data_buffer_address)); 383 } 384 break; 385 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS: 386 success_desc = (struct mpi3_success_reply_descriptor *)reply_desc; 387 host_tag = le16_to_cpu(success_desc->host_tag); 388 break; 389 default: 390 break; 391 } 392 393 cmdptr = mpi3mr_get_drv_cmd(mrioc, host_tag, def_reply); 394 if (cmdptr) { 395 if (cmdptr->state & MPI3MR_CMD_PENDING) { 396 cmdptr->state |= MPI3MR_CMD_COMPLETE; 397 cmdptr->ioc_loginfo = ioc_loginfo; 398 cmdptr->ioc_status = ioc_status; 399 cmdptr->state &= ~MPI3MR_CMD_PENDING; 400 if (def_reply) { 401 cmdptr->state |= MPI3MR_CMD_REPLY_VALID; 402 memcpy((u8 *)cmdptr->reply, (u8 *)def_reply, 403 mrioc->reply_sz); 404 } 405 if (sense_buf && cmdptr->sensebuf) { 406 cmdptr->is_sense = 1; 407 memcpy(cmdptr->sensebuf, sense_buf, 408 MPI3MR_SENSE_BUF_SZ); 409 } 410 if (cmdptr->is_waiting) { 411 complete(&cmdptr->done); 412 cmdptr->is_waiting = 0; 413 } else if (cmdptr->callback) 414 cmdptr->callback(mrioc, cmdptr); 415 } 416 } 417 out: 418 if (sense_buf) 419 mpi3mr_repost_sense_buf(mrioc, 420 le64_to_cpu(scsi_reply->sense_data_buffer_address)); 421 } 422 423 int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc) 424 { 425 u32 exp_phase = mrioc->admin_reply_ephase; 426 u32 admin_reply_ci = mrioc->admin_reply_ci; 427 u32 num_admin_replies = 0; 428 u64 reply_dma = 0; 429 struct mpi3_default_reply_descriptor *reply_desc; 430 431 if (!atomic_add_unless(&mrioc->admin_reply_q_in_use, 1, 1)) 432 return 0; 433 434 reply_desc = (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base + 435 admin_reply_ci; 436 437 if ((le16_to_cpu(reply_desc->reply_flags) & 438 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) { 439 atomic_dec(&mrioc->admin_reply_q_in_use); 440 return 0; 441 } 442 443 do { 444 if (mrioc->unrecoverable) 445 break; 446 447 mrioc->admin_req_ci = le16_to_cpu(reply_desc->request_queue_ci); 448 mpi3mr_process_admin_reply_desc(mrioc, reply_desc, &reply_dma); 449 if (reply_dma) 450 mpi3mr_repost_reply_buf(mrioc, reply_dma); 451 num_admin_replies++; 452 if (++admin_reply_ci == mrioc->num_admin_replies) { 453 admin_reply_ci = 0; 454 exp_phase ^= 1; 455 } 456 reply_desc = 457 (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base + 458 admin_reply_ci; 459 if ((le16_to_cpu(reply_desc->reply_flags) & 460 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) 461 break; 462 } while (1); 463 464 writel(admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci); 465 mrioc->admin_reply_ci = admin_reply_ci; 466 mrioc->admin_reply_ephase = exp_phase; 467 atomic_dec(&mrioc->admin_reply_q_in_use); 468 469 return num_admin_replies; 470 } 471 472 /** 473 * mpi3mr_get_reply_desc - get reply descriptor frame corresponding to 474 * queue's consumer index from operational reply descriptor queue. 475 * @op_reply_q: op_reply_qinfo object 476 * @reply_ci: operational reply descriptor's queue consumer index 477 * 478 * Returns reply descriptor frame address 479 */ 480 static inline struct mpi3_default_reply_descriptor * 481 mpi3mr_get_reply_desc(struct op_reply_qinfo *op_reply_q, u32 reply_ci) 482 { 483 void *segment_base_addr; 484 struct segments *segments = op_reply_q->q_segments; 485 struct mpi3_default_reply_descriptor *reply_desc = NULL; 486 487 segment_base_addr = 488 segments[reply_ci / op_reply_q->segment_qd].segment; 489 reply_desc = (struct mpi3_default_reply_descriptor *)segment_base_addr + 490 (reply_ci % op_reply_q->segment_qd); 491 return reply_desc; 492 } 493 494 /** 495 * mpi3mr_process_op_reply_q - Operational reply queue handler 496 * @mrioc: Adapter instance reference 497 * @op_reply_q: Operational reply queue info 498 * 499 * Checks the specific operational reply queue and drains the 500 * reply queue entries until the queue is empty and process the 501 * individual reply descriptors. 502 * 503 * Return: 0 if queue is already processed,or number of reply 504 * descriptors processed. 505 */ 506 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc, 507 struct op_reply_qinfo *op_reply_q) 508 { 509 struct op_req_qinfo *op_req_q; 510 u32 exp_phase; 511 u32 reply_ci; 512 u32 num_op_reply = 0; 513 u64 reply_dma = 0; 514 struct mpi3_default_reply_descriptor *reply_desc; 515 u16 req_q_idx = 0, reply_qidx; 516 517 reply_qidx = op_reply_q->qid - 1; 518 519 if (!atomic_add_unless(&op_reply_q->in_use, 1, 1)) 520 return 0; 521 522 exp_phase = op_reply_q->ephase; 523 reply_ci = op_reply_q->ci; 524 525 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci); 526 if ((le16_to_cpu(reply_desc->reply_flags) & 527 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) { 528 atomic_dec(&op_reply_q->in_use); 529 return 0; 530 } 531 532 do { 533 if (mrioc->unrecoverable) 534 break; 535 536 req_q_idx = le16_to_cpu(reply_desc->request_queue_id) - 1; 537 op_req_q = &mrioc->req_qinfo[req_q_idx]; 538 539 WRITE_ONCE(op_req_q->ci, le16_to_cpu(reply_desc->request_queue_ci)); 540 mpi3mr_process_op_reply_desc(mrioc, reply_desc, &reply_dma, 541 reply_qidx); 542 atomic_dec(&op_reply_q->pend_ios); 543 if (reply_dma) 544 mpi3mr_repost_reply_buf(mrioc, reply_dma); 545 num_op_reply++; 546 547 if (++reply_ci == op_reply_q->num_replies) { 548 reply_ci = 0; 549 exp_phase ^= 1; 550 } 551 552 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci); 553 554 if ((le16_to_cpu(reply_desc->reply_flags) & 555 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) 556 break; 557 #ifndef CONFIG_PREEMPT_RT 558 /* 559 * Exit completion loop to avoid CPU lockup 560 * Ensure remaining completion happens from threaded ISR. 561 */ 562 if (num_op_reply > mrioc->max_host_ios) { 563 op_reply_q->enable_irq_poll = true; 564 break; 565 } 566 #endif 567 } while (1); 568 569 writel(reply_ci, 570 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].consumer_index); 571 op_reply_q->ci = reply_ci; 572 op_reply_q->ephase = exp_phase; 573 574 atomic_dec(&op_reply_q->in_use); 575 return num_op_reply; 576 } 577 578 /** 579 * mpi3mr_blk_mq_poll - Operational reply queue handler 580 * @shost: SCSI Host reference 581 * @queue_num: Request queue number (w.r.t OS it is hardware context number) 582 * 583 * Checks the specific operational reply queue and drains the 584 * reply queue entries until the queue is empty and process the 585 * individual reply descriptors. 586 * 587 * Return: 0 if queue is already processed,or number of reply 588 * descriptors processed. 589 */ 590 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num) 591 { 592 int num_entries = 0; 593 struct mpi3mr_ioc *mrioc; 594 595 mrioc = (struct mpi3mr_ioc *)shost->hostdata; 596 597 if ((mrioc->reset_in_progress || mrioc->prepare_for_reset || 598 mrioc->unrecoverable)) 599 return 0; 600 601 num_entries = mpi3mr_process_op_reply_q(mrioc, 602 &mrioc->op_reply_qinfo[queue_num]); 603 604 return num_entries; 605 } 606 607 static irqreturn_t mpi3mr_isr_primary(int irq, void *privdata) 608 { 609 struct mpi3mr_intr_info *intr_info = privdata; 610 struct mpi3mr_ioc *mrioc; 611 u16 midx; 612 u32 num_admin_replies = 0, num_op_reply = 0; 613 614 if (!intr_info) 615 return IRQ_NONE; 616 617 mrioc = intr_info->mrioc; 618 619 if (!mrioc->intr_enabled) 620 return IRQ_NONE; 621 622 midx = intr_info->msix_index; 623 624 if (!midx) 625 num_admin_replies = mpi3mr_process_admin_reply_q(mrioc); 626 if (intr_info->op_reply_q) 627 num_op_reply = mpi3mr_process_op_reply_q(mrioc, 628 intr_info->op_reply_q); 629 630 if (num_admin_replies || num_op_reply) 631 return IRQ_HANDLED; 632 else 633 return IRQ_NONE; 634 } 635 636 #ifndef CONFIG_PREEMPT_RT 637 638 static irqreturn_t mpi3mr_isr(int irq, void *privdata) 639 { 640 struct mpi3mr_intr_info *intr_info = privdata; 641 int ret; 642 643 if (!intr_info) 644 return IRQ_NONE; 645 646 /* Call primary ISR routine */ 647 ret = mpi3mr_isr_primary(irq, privdata); 648 649 /* 650 * If more IOs are expected, schedule IRQ polling thread. 651 * Otherwise exit from ISR. 652 */ 653 if (!intr_info->op_reply_q) 654 return ret; 655 656 if (!intr_info->op_reply_q->enable_irq_poll || 657 !atomic_read(&intr_info->op_reply_q->pend_ios)) 658 return ret; 659 660 disable_irq_nosync(intr_info->os_irq); 661 662 return IRQ_WAKE_THREAD; 663 } 664 665 /** 666 * mpi3mr_isr_poll - Reply queue polling routine 667 * @irq: IRQ 668 * @privdata: Interrupt info 669 * 670 * poll for pending I/O completions in a loop until pending I/Os 671 * present or controller queue depth I/Os are processed. 672 * 673 * Return: IRQ_NONE or IRQ_HANDLED 674 */ 675 static irqreturn_t mpi3mr_isr_poll(int irq, void *privdata) 676 { 677 struct mpi3mr_intr_info *intr_info = privdata; 678 struct mpi3mr_ioc *mrioc; 679 u16 midx; 680 u32 num_op_reply = 0; 681 682 if (!intr_info || !intr_info->op_reply_q) 683 return IRQ_NONE; 684 685 mrioc = intr_info->mrioc; 686 midx = intr_info->msix_index; 687 688 /* Poll for pending IOs completions */ 689 do { 690 if (!mrioc->intr_enabled || mrioc->unrecoverable) 691 break; 692 693 if (!midx) 694 mpi3mr_process_admin_reply_q(mrioc); 695 if (intr_info->op_reply_q) 696 num_op_reply += 697 mpi3mr_process_op_reply_q(mrioc, 698 intr_info->op_reply_q); 699 700 usleep_range(MPI3MR_IRQ_POLL_SLEEP, 10 * MPI3MR_IRQ_POLL_SLEEP); 701 702 } while (atomic_read(&intr_info->op_reply_q->pend_ios) && 703 (num_op_reply < mrioc->max_host_ios)); 704 705 intr_info->op_reply_q->enable_irq_poll = false; 706 enable_irq(intr_info->os_irq); 707 708 return IRQ_HANDLED; 709 } 710 711 #endif 712 713 /** 714 * mpi3mr_request_irq - Request IRQ and register ISR 715 * @mrioc: Adapter instance reference 716 * @index: IRQ vector index 717 * 718 * Request threaded ISR with primary ISR and secondary 719 * 720 * Return: 0 on success and non zero on failures. 721 */ 722 static inline int mpi3mr_request_irq(struct mpi3mr_ioc *mrioc, u16 index) 723 { 724 struct pci_dev *pdev = mrioc->pdev; 725 struct mpi3mr_intr_info *intr_info = mrioc->intr_info + index; 726 int retval = 0; 727 728 intr_info->mrioc = mrioc; 729 intr_info->msix_index = index; 730 intr_info->op_reply_q = NULL; 731 732 snprintf(intr_info->name, MPI3MR_NAME_LENGTH, "%s%d-msix%d", 733 mrioc->driver_name, mrioc->id, index); 734 735 #ifndef CONFIG_PREEMPT_RT 736 retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr, 737 mpi3mr_isr_poll, IRQF_SHARED, intr_info->name, intr_info); 738 #else 739 retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr_primary, 740 NULL, IRQF_SHARED, intr_info->name, intr_info); 741 #endif 742 if (retval) { 743 ioc_err(mrioc, "%s: Unable to allocate interrupt %d!\n", 744 intr_info->name, pci_irq_vector(pdev, index)); 745 return retval; 746 } 747 748 intr_info->os_irq = pci_irq_vector(pdev, index); 749 return retval; 750 } 751 752 static void mpi3mr_calc_poll_queues(struct mpi3mr_ioc *mrioc, u16 max_vectors) 753 { 754 if (!mrioc->requested_poll_qcount) 755 return; 756 757 /* Reserved for Admin and Default Queue */ 758 if (max_vectors > 2 && 759 (mrioc->requested_poll_qcount < max_vectors - 2)) { 760 ioc_info(mrioc, 761 "enabled polled queues (%d) msix (%d)\n", 762 mrioc->requested_poll_qcount, max_vectors); 763 } else { 764 ioc_info(mrioc, 765 "disabled polled queues (%d) msix (%d) because of no resources for default queue\n", 766 mrioc->requested_poll_qcount, max_vectors); 767 mrioc->requested_poll_qcount = 0; 768 } 769 } 770 771 /** 772 * mpi3mr_setup_isr - Setup ISR for the controller 773 * @mrioc: Adapter instance reference 774 * @setup_one: Request one IRQ or more 775 * 776 * Allocate IRQ vectors and call mpi3mr_request_irq to setup ISR 777 * 778 * Return: 0 on success and non zero on failures. 779 */ 780 static int mpi3mr_setup_isr(struct mpi3mr_ioc *mrioc, u8 setup_one) 781 { 782 unsigned int irq_flags = PCI_IRQ_MSIX; 783 int max_vectors, min_vec; 784 int retval; 785 int i; 786 struct irq_affinity desc = { .pre_vectors = 1, .post_vectors = 1 }; 787 788 if (mrioc->is_intr_info_set) 789 return 0; 790 791 mpi3mr_cleanup_isr(mrioc); 792 793 if (setup_one || reset_devices) { 794 max_vectors = 1; 795 retval = pci_alloc_irq_vectors(mrioc->pdev, 796 1, max_vectors, irq_flags); 797 if (retval < 0) { 798 ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n", 799 retval); 800 goto out_failed; 801 } 802 } else { 803 max_vectors = 804 min_t(int, mrioc->cpu_count + 1 + 805 mrioc->requested_poll_qcount, mrioc->msix_count); 806 807 mpi3mr_calc_poll_queues(mrioc, max_vectors); 808 809 ioc_info(mrioc, 810 "MSI-X vectors supported: %d, no of cores: %d,", 811 mrioc->msix_count, mrioc->cpu_count); 812 ioc_info(mrioc, 813 "MSI-x vectors requested: %d poll_queues %d\n", 814 max_vectors, mrioc->requested_poll_qcount); 815 816 desc.post_vectors = mrioc->requested_poll_qcount; 817 min_vec = desc.pre_vectors + desc.post_vectors; 818 irq_flags |= PCI_IRQ_AFFINITY | PCI_IRQ_ALL_TYPES; 819 820 retval = pci_alloc_irq_vectors_affinity(mrioc->pdev, 821 min_vec, max_vectors, irq_flags, &desc); 822 823 if (retval < 0) { 824 ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n", 825 retval); 826 goto out_failed; 827 } 828 829 830 /* 831 * If only one MSI-x is allocated, then MSI-x 0 will be shared 832 * between Admin queue and operational queue 833 */ 834 if (retval == min_vec) 835 mrioc->op_reply_q_offset = 0; 836 else if (retval != (max_vectors)) { 837 ioc_info(mrioc, 838 "allocated vectors (%d) are less than configured (%d)\n", 839 retval, max_vectors); 840 } 841 842 max_vectors = retval; 843 mrioc->op_reply_q_offset = (max_vectors > 1) ? 1 : 0; 844 845 mpi3mr_calc_poll_queues(mrioc, max_vectors); 846 847 } 848 849 mrioc->intr_info = kzalloc(sizeof(struct mpi3mr_intr_info) * max_vectors, 850 GFP_KERNEL); 851 if (!mrioc->intr_info) { 852 retval = -ENOMEM; 853 pci_free_irq_vectors(mrioc->pdev); 854 goto out_failed; 855 } 856 for (i = 0; i < max_vectors; i++) { 857 retval = mpi3mr_request_irq(mrioc, i); 858 if (retval) { 859 mrioc->intr_info_count = i; 860 goto out_failed; 861 } 862 } 863 if (reset_devices || !setup_one) 864 mrioc->is_intr_info_set = true; 865 mrioc->intr_info_count = max_vectors; 866 mpi3mr_ioc_enable_intr(mrioc); 867 return 0; 868 869 out_failed: 870 mpi3mr_cleanup_isr(mrioc); 871 872 return retval; 873 } 874 875 static const struct { 876 enum mpi3mr_iocstate value; 877 char *name; 878 } mrioc_states[] = { 879 { MRIOC_STATE_READY, "ready" }, 880 { MRIOC_STATE_FAULT, "fault" }, 881 { MRIOC_STATE_RESET, "reset" }, 882 { MRIOC_STATE_BECOMING_READY, "becoming ready" }, 883 { MRIOC_STATE_RESET_REQUESTED, "reset requested" }, 884 { MRIOC_STATE_UNRECOVERABLE, "unrecoverable error" }, 885 }; 886 887 static const char *mpi3mr_iocstate_name(enum mpi3mr_iocstate mrioc_state) 888 { 889 int i; 890 char *name = NULL; 891 892 for (i = 0; i < ARRAY_SIZE(mrioc_states); i++) { 893 if (mrioc_states[i].value == mrioc_state) { 894 name = mrioc_states[i].name; 895 break; 896 } 897 } 898 return name; 899 } 900 901 /* Reset reason to name mapper structure*/ 902 static const struct { 903 enum mpi3mr_reset_reason value; 904 char *name; 905 } mpi3mr_reset_reason_codes[] = { 906 { MPI3MR_RESET_FROM_BRINGUP, "timeout in bringup" }, 907 { MPI3MR_RESET_FROM_FAULT_WATCH, "fault" }, 908 { MPI3MR_RESET_FROM_APP, "application invocation" }, 909 { MPI3MR_RESET_FROM_EH_HOS, "error handling" }, 910 { MPI3MR_RESET_FROM_TM_TIMEOUT, "TM timeout" }, 911 { MPI3MR_RESET_FROM_APP_TIMEOUT, "application command timeout" }, 912 { MPI3MR_RESET_FROM_MUR_FAILURE, "MUR failure" }, 913 { MPI3MR_RESET_FROM_CTLR_CLEANUP, "timeout in controller cleanup" }, 914 { MPI3MR_RESET_FROM_CIACTIV_FAULT, "component image activation fault" }, 915 { MPI3MR_RESET_FROM_PE_TIMEOUT, "port enable timeout" }, 916 { MPI3MR_RESET_FROM_TSU_TIMEOUT, "time stamp update timeout" }, 917 { MPI3MR_RESET_FROM_DELREQQ_TIMEOUT, "delete request queue timeout" }, 918 { MPI3MR_RESET_FROM_DELREPQ_TIMEOUT, "delete reply queue timeout" }, 919 { 920 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT, 921 "create request queue timeout" 922 }, 923 { 924 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT, 925 "create reply queue timeout" 926 }, 927 { MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT, "IOC facts timeout" }, 928 { MPI3MR_RESET_FROM_IOCINIT_TIMEOUT, "IOC init timeout" }, 929 { MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT, "event notify timeout" }, 930 { MPI3MR_RESET_FROM_EVTACK_TIMEOUT, "event acknowledgment timeout" }, 931 { 932 MPI3MR_RESET_FROM_CIACTVRST_TIMER, 933 "component image activation timeout" 934 }, 935 { 936 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT, 937 "get package version timeout" 938 }, 939 { MPI3MR_RESET_FROM_SYSFS, "sysfs invocation" }, 940 { MPI3MR_RESET_FROM_SYSFS_TIMEOUT, "sysfs TM timeout" }, 941 { MPI3MR_RESET_FROM_FIRMWARE, "firmware asynchronous reset" }, 942 { MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT, "configuration request timeout"}, 943 { MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT, "timeout of a SAS transport layer request" }, 944 }; 945 946 /** 947 * mpi3mr_reset_rc_name - get reset reason code name 948 * @reason_code: reset reason code value 949 * 950 * Map reset reason to an NULL terminated ASCII string 951 * 952 * Return: name corresponding to reset reason value or NULL. 953 */ 954 static const char *mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code) 955 { 956 int i; 957 char *name = NULL; 958 959 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_reason_codes); i++) { 960 if (mpi3mr_reset_reason_codes[i].value == reason_code) { 961 name = mpi3mr_reset_reason_codes[i].name; 962 break; 963 } 964 } 965 return name; 966 } 967 968 /* Reset type to name mapper structure*/ 969 static const struct { 970 u16 reset_type; 971 char *name; 972 } mpi3mr_reset_types[] = { 973 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, "soft" }, 974 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, "diag fault" }, 975 }; 976 977 /** 978 * mpi3mr_reset_type_name - get reset type name 979 * @reset_type: reset type value 980 * 981 * Map reset type to an NULL terminated ASCII string 982 * 983 * Return: name corresponding to reset type value or NULL. 984 */ 985 static const char *mpi3mr_reset_type_name(u16 reset_type) 986 { 987 int i; 988 char *name = NULL; 989 990 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_types); i++) { 991 if (mpi3mr_reset_types[i].reset_type == reset_type) { 992 name = mpi3mr_reset_types[i].name; 993 break; 994 } 995 } 996 return name; 997 } 998 999 /** 1000 * mpi3mr_print_fault_info - Display fault information 1001 * @mrioc: Adapter instance reference 1002 * 1003 * Display the controller fault information if there is a 1004 * controller fault. 1005 * 1006 * Return: Nothing. 1007 */ 1008 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc) 1009 { 1010 u32 ioc_status, code, code1, code2, code3; 1011 1012 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1013 1014 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) { 1015 code = readl(&mrioc->sysif_regs->fault); 1016 code1 = readl(&mrioc->sysif_regs->fault_info[0]); 1017 code2 = readl(&mrioc->sysif_regs->fault_info[1]); 1018 code3 = readl(&mrioc->sysif_regs->fault_info[2]); 1019 1020 ioc_info(mrioc, 1021 "fault code(0x%08X): Additional code: (0x%08X:0x%08X:0x%08X)\n", 1022 code, code1, code2, code3); 1023 } 1024 } 1025 1026 /** 1027 * mpi3mr_get_iocstate - Get IOC State 1028 * @mrioc: Adapter instance reference 1029 * 1030 * Return a proper IOC state enum based on the IOC status and 1031 * IOC configuration and unrcoverable state of the controller. 1032 * 1033 * Return: Current IOC state. 1034 */ 1035 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc) 1036 { 1037 u32 ioc_status, ioc_config; 1038 u8 ready, enabled; 1039 1040 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1041 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1042 1043 if (mrioc->unrecoverable) 1044 return MRIOC_STATE_UNRECOVERABLE; 1045 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) 1046 return MRIOC_STATE_FAULT; 1047 1048 ready = (ioc_status & MPI3_SYSIF_IOC_STATUS_READY); 1049 enabled = (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC); 1050 1051 if (ready && enabled) 1052 return MRIOC_STATE_READY; 1053 if ((!ready) && (!enabled)) 1054 return MRIOC_STATE_RESET; 1055 if ((!ready) && (enabled)) 1056 return MRIOC_STATE_BECOMING_READY; 1057 1058 return MRIOC_STATE_RESET_REQUESTED; 1059 } 1060 1061 /** 1062 * mpi3mr_clear_reset_history - clear reset history 1063 * @mrioc: Adapter instance reference 1064 * 1065 * Write the reset history bit in IOC status to clear the bit, 1066 * if it is already set. 1067 * 1068 * Return: Nothing. 1069 */ 1070 static inline void mpi3mr_clear_reset_history(struct mpi3mr_ioc *mrioc) 1071 { 1072 u32 ioc_status; 1073 1074 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1075 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) 1076 writel(ioc_status, &mrioc->sysif_regs->ioc_status); 1077 } 1078 1079 /** 1080 * mpi3mr_issue_and_process_mur - Message unit Reset handler 1081 * @mrioc: Adapter instance reference 1082 * @reset_reason: Reset reason code 1083 * 1084 * Issue Message unit Reset to the controller and wait for it to 1085 * be complete. 1086 * 1087 * Return: 0 on success, -1 on failure. 1088 */ 1089 static int mpi3mr_issue_and_process_mur(struct mpi3mr_ioc *mrioc, 1090 u32 reset_reason) 1091 { 1092 u32 ioc_config, timeout, ioc_status; 1093 int retval = -1; 1094 1095 ioc_info(mrioc, "Issuing Message unit Reset(MUR)\n"); 1096 if (mrioc->unrecoverable) { 1097 ioc_info(mrioc, "IOC is unrecoverable MUR not issued\n"); 1098 return retval; 1099 } 1100 mpi3mr_clear_reset_history(mrioc); 1101 writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]); 1102 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1103 ioc_config &= ~MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC; 1104 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); 1105 1106 timeout = MPI3MR_MUR_TIMEOUT * 10; 1107 do { 1108 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1109 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)) { 1110 mpi3mr_clear_reset_history(mrioc); 1111 break; 1112 } 1113 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) { 1114 mpi3mr_print_fault_info(mrioc); 1115 break; 1116 } 1117 msleep(100); 1118 } while (--timeout); 1119 1120 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1121 if (timeout && !((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) || 1122 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) || 1123 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC))) 1124 retval = 0; 1125 1126 ioc_info(mrioc, "Base IOC Sts/Config after %s MUR is (0x%x)/(0x%x)\n", 1127 (!retval) ? "successful" : "failed", ioc_status, ioc_config); 1128 return retval; 1129 } 1130 1131 /** 1132 * mpi3mr_revalidate_factsdata - validate IOCFacts parameters 1133 * during reset/resume 1134 * @mrioc: Adapter instance reference 1135 * 1136 * Return zero if the new IOCFacts parameters value is compatible with 1137 * older values else return -EPERM 1138 */ 1139 static int 1140 mpi3mr_revalidate_factsdata(struct mpi3mr_ioc *mrioc) 1141 { 1142 unsigned long *removepend_bitmap; 1143 1144 if (mrioc->facts.reply_sz > mrioc->reply_sz) { 1145 ioc_err(mrioc, 1146 "cannot increase reply size from %d to %d\n", 1147 mrioc->reply_sz, mrioc->facts.reply_sz); 1148 return -EPERM; 1149 } 1150 1151 if (mrioc->facts.max_op_reply_q < mrioc->num_op_reply_q) { 1152 ioc_err(mrioc, 1153 "cannot reduce number of operational reply queues from %d to %d\n", 1154 mrioc->num_op_reply_q, 1155 mrioc->facts.max_op_reply_q); 1156 return -EPERM; 1157 } 1158 1159 if (mrioc->facts.max_op_req_q < mrioc->num_op_req_q) { 1160 ioc_err(mrioc, 1161 "cannot reduce number of operational request queues from %d to %d\n", 1162 mrioc->num_op_req_q, mrioc->facts.max_op_req_q); 1163 return -EPERM; 1164 } 1165 1166 if ((mrioc->sas_transport_enabled) && (mrioc->facts.ioc_capabilities & 1167 MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED)) 1168 ioc_err(mrioc, 1169 "critical error: multipath capability is enabled at the\n" 1170 "\tcontroller while sas transport support is enabled at the\n" 1171 "\tdriver, please reboot the system or reload the driver\n"); 1172 1173 if (mrioc->facts.max_devhandle > mrioc->dev_handle_bitmap_bits) { 1174 removepend_bitmap = bitmap_zalloc(mrioc->facts.max_devhandle, 1175 GFP_KERNEL); 1176 if (!removepend_bitmap) { 1177 ioc_err(mrioc, 1178 "failed to increase removepend_bitmap bits from %d to %d\n", 1179 mrioc->dev_handle_bitmap_bits, 1180 mrioc->facts.max_devhandle); 1181 return -EPERM; 1182 } 1183 bitmap_free(mrioc->removepend_bitmap); 1184 mrioc->removepend_bitmap = removepend_bitmap; 1185 ioc_info(mrioc, 1186 "increased bits of dev_handle_bitmap from %d to %d\n", 1187 mrioc->dev_handle_bitmap_bits, 1188 mrioc->facts.max_devhandle); 1189 mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle; 1190 } 1191 1192 return 0; 1193 } 1194 1195 /** 1196 * mpi3mr_bring_ioc_ready - Bring controller to ready state 1197 * @mrioc: Adapter instance reference 1198 * 1199 * Set Enable IOC bit in IOC configuration register and wait for 1200 * the controller to become ready. 1201 * 1202 * Return: 0 on success, appropriate error on failure. 1203 */ 1204 static int mpi3mr_bring_ioc_ready(struct mpi3mr_ioc *mrioc) 1205 { 1206 u32 ioc_config, ioc_status, timeout, host_diagnostic; 1207 int retval = 0; 1208 enum mpi3mr_iocstate ioc_state; 1209 u64 base_info; 1210 1211 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1212 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1213 base_info = lo_hi_readq(&mrioc->sysif_regs->ioc_information); 1214 ioc_info(mrioc, "ioc_status(0x%08x), ioc_config(0x%08x), ioc_info(0x%016llx) at the bringup\n", 1215 ioc_status, ioc_config, base_info); 1216 1217 /*The timeout value is in 2sec unit, changing it to seconds*/ 1218 mrioc->ready_timeout = 1219 ((base_info & MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK) >> 1220 MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT) * 2; 1221 1222 ioc_info(mrioc, "ready timeout: %d seconds\n", mrioc->ready_timeout); 1223 1224 ioc_state = mpi3mr_get_iocstate(mrioc); 1225 ioc_info(mrioc, "controller is in %s state during detection\n", 1226 mpi3mr_iocstate_name(ioc_state)); 1227 1228 if (ioc_state == MRIOC_STATE_BECOMING_READY || 1229 ioc_state == MRIOC_STATE_RESET_REQUESTED) { 1230 timeout = mrioc->ready_timeout * 10; 1231 do { 1232 msleep(100); 1233 } while (--timeout); 1234 1235 if (!pci_device_is_present(mrioc->pdev)) { 1236 mrioc->unrecoverable = 1; 1237 ioc_err(mrioc, 1238 "controller is not present while waiting to reset\n"); 1239 retval = -1; 1240 goto out_device_not_present; 1241 } 1242 1243 ioc_state = mpi3mr_get_iocstate(mrioc); 1244 ioc_info(mrioc, 1245 "controller is in %s state after waiting to reset\n", 1246 mpi3mr_iocstate_name(ioc_state)); 1247 } 1248 1249 if (ioc_state == MRIOC_STATE_READY) { 1250 ioc_info(mrioc, "issuing message unit reset (MUR) to bring to reset state\n"); 1251 retval = mpi3mr_issue_and_process_mur(mrioc, 1252 MPI3MR_RESET_FROM_BRINGUP); 1253 ioc_state = mpi3mr_get_iocstate(mrioc); 1254 if (retval) 1255 ioc_err(mrioc, 1256 "message unit reset failed with error %d current state %s\n", 1257 retval, mpi3mr_iocstate_name(ioc_state)); 1258 } 1259 if (ioc_state != MRIOC_STATE_RESET) { 1260 if (ioc_state == MRIOC_STATE_FAULT) { 1261 timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10; 1262 mpi3mr_print_fault_info(mrioc); 1263 do { 1264 host_diagnostic = 1265 readl(&mrioc->sysif_regs->host_diagnostic); 1266 if (!(host_diagnostic & 1267 MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS)) 1268 break; 1269 if (!pci_device_is_present(mrioc->pdev)) { 1270 mrioc->unrecoverable = 1; 1271 ioc_err(mrioc, "controller is not present at the bringup\n"); 1272 goto out_device_not_present; 1273 } 1274 msleep(100); 1275 } while (--timeout); 1276 } 1277 mpi3mr_print_fault_info(mrioc); 1278 ioc_info(mrioc, "issuing soft reset to bring to reset state\n"); 1279 retval = mpi3mr_issue_reset(mrioc, 1280 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, 1281 MPI3MR_RESET_FROM_BRINGUP); 1282 if (retval) { 1283 ioc_err(mrioc, 1284 "soft reset failed with error %d\n", retval); 1285 goto out_failed; 1286 } 1287 } 1288 ioc_state = mpi3mr_get_iocstate(mrioc); 1289 if (ioc_state != MRIOC_STATE_RESET) { 1290 ioc_err(mrioc, 1291 "cannot bring controller to reset state, current state: %s\n", 1292 mpi3mr_iocstate_name(ioc_state)); 1293 goto out_failed; 1294 } 1295 mpi3mr_clear_reset_history(mrioc); 1296 retval = mpi3mr_setup_admin_qpair(mrioc); 1297 if (retval) { 1298 ioc_err(mrioc, "failed to setup admin queues: error %d\n", 1299 retval); 1300 goto out_failed; 1301 } 1302 1303 ioc_info(mrioc, "bringing controller to ready state\n"); 1304 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1305 ioc_config |= MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC; 1306 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); 1307 1308 timeout = mrioc->ready_timeout * 10; 1309 do { 1310 ioc_state = mpi3mr_get_iocstate(mrioc); 1311 if (ioc_state == MRIOC_STATE_READY) { 1312 ioc_info(mrioc, 1313 "successfully transitioned to %s state\n", 1314 mpi3mr_iocstate_name(ioc_state)); 1315 return 0; 1316 } 1317 if (!pci_device_is_present(mrioc->pdev)) { 1318 mrioc->unrecoverable = 1; 1319 ioc_err(mrioc, 1320 "controller is not present at the bringup\n"); 1321 retval = -1; 1322 goto out_device_not_present; 1323 } 1324 msleep(100); 1325 } while (--timeout); 1326 1327 out_failed: 1328 ioc_state = mpi3mr_get_iocstate(mrioc); 1329 ioc_err(mrioc, 1330 "failed to bring to ready state, current state: %s\n", 1331 mpi3mr_iocstate_name(ioc_state)); 1332 out_device_not_present: 1333 return retval; 1334 } 1335 1336 /** 1337 * mpi3mr_soft_reset_success - Check softreset is success or not 1338 * @ioc_status: IOC status register value 1339 * @ioc_config: IOC config register value 1340 * 1341 * Check whether the soft reset is successful or not based on 1342 * IOC status and IOC config register values. 1343 * 1344 * Return: True when the soft reset is success, false otherwise. 1345 */ 1346 static inline bool 1347 mpi3mr_soft_reset_success(u32 ioc_status, u32 ioc_config) 1348 { 1349 if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) || 1350 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC))) 1351 return true; 1352 return false; 1353 } 1354 1355 /** 1356 * mpi3mr_diagfault_success - Check diag fault is success or not 1357 * @mrioc: Adapter reference 1358 * @ioc_status: IOC status register value 1359 * 1360 * Check whether the controller hit diag reset fault code. 1361 * 1362 * Return: True when there is diag fault, false otherwise. 1363 */ 1364 static inline bool mpi3mr_diagfault_success(struct mpi3mr_ioc *mrioc, 1365 u32 ioc_status) 1366 { 1367 u32 fault; 1368 1369 if (!(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) 1370 return false; 1371 fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK; 1372 if (fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET) { 1373 mpi3mr_print_fault_info(mrioc); 1374 return true; 1375 } 1376 return false; 1377 } 1378 1379 /** 1380 * mpi3mr_set_diagsave - Set diag save bit for snapdump 1381 * @mrioc: Adapter reference 1382 * 1383 * Set diag save bit in IOC configuration register to enable 1384 * snapdump. 1385 * 1386 * Return: Nothing. 1387 */ 1388 static inline void mpi3mr_set_diagsave(struct mpi3mr_ioc *mrioc) 1389 { 1390 u32 ioc_config; 1391 1392 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1393 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE; 1394 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); 1395 } 1396 1397 /** 1398 * mpi3mr_issue_reset - Issue reset to the controller 1399 * @mrioc: Adapter reference 1400 * @reset_type: Reset type 1401 * @reset_reason: Reset reason code 1402 * 1403 * Unlock the host diagnostic registers and write the specific 1404 * reset type to that, wait for reset acknowledgment from the 1405 * controller, if the reset is not successful retry for the 1406 * predefined number of times. 1407 * 1408 * Return: 0 on success, non-zero on failure. 1409 */ 1410 static int mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, 1411 u32 reset_reason) 1412 { 1413 int retval = -1; 1414 u8 unlock_retry_count = 0; 1415 u32 host_diagnostic, ioc_status, ioc_config; 1416 u32 timeout = MPI3MR_RESET_ACK_TIMEOUT * 10; 1417 1418 if ((reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) && 1419 (reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT)) 1420 return retval; 1421 if (mrioc->unrecoverable) 1422 return retval; 1423 if (reset_reason == MPI3MR_RESET_FROM_FIRMWARE) { 1424 retval = 0; 1425 return retval; 1426 } 1427 1428 ioc_info(mrioc, "%s reset due to %s(0x%x)\n", 1429 mpi3mr_reset_type_name(reset_type), 1430 mpi3mr_reset_rc_name(reset_reason), reset_reason); 1431 1432 mpi3mr_clear_reset_history(mrioc); 1433 do { 1434 ioc_info(mrioc, 1435 "Write magic sequence to unlock host diag register (retry=%d)\n", 1436 ++unlock_retry_count); 1437 if (unlock_retry_count >= MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT) { 1438 ioc_err(mrioc, 1439 "%s reset failed due to unlock failure, host_diagnostic(0x%08x)\n", 1440 mpi3mr_reset_type_name(reset_type), 1441 host_diagnostic); 1442 mrioc->unrecoverable = 1; 1443 return retval; 1444 } 1445 1446 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH, 1447 &mrioc->sysif_regs->write_sequence); 1448 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST, 1449 &mrioc->sysif_regs->write_sequence); 1450 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND, 1451 &mrioc->sysif_regs->write_sequence); 1452 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD, 1453 &mrioc->sysif_regs->write_sequence); 1454 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH, 1455 &mrioc->sysif_regs->write_sequence); 1456 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH, 1457 &mrioc->sysif_regs->write_sequence); 1458 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH, 1459 &mrioc->sysif_regs->write_sequence); 1460 usleep_range(1000, 1100); 1461 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic); 1462 ioc_info(mrioc, 1463 "wrote magic sequence: retry_count(%d), host_diagnostic(0x%08x)\n", 1464 unlock_retry_count, host_diagnostic); 1465 } while (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE)); 1466 1467 writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]); 1468 writel(host_diagnostic | reset_type, 1469 &mrioc->sysif_regs->host_diagnostic); 1470 switch (reset_type) { 1471 case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET: 1472 do { 1473 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1474 ioc_config = 1475 readl(&mrioc->sysif_regs->ioc_configuration); 1476 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) 1477 && mpi3mr_soft_reset_success(ioc_status, ioc_config) 1478 ) { 1479 mpi3mr_clear_reset_history(mrioc); 1480 retval = 0; 1481 break; 1482 } 1483 msleep(100); 1484 } while (--timeout); 1485 mpi3mr_print_fault_info(mrioc); 1486 break; 1487 case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT: 1488 do { 1489 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1490 if (mpi3mr_diagfault_success(mrioc, ioc_status)) { 1491 retval = 0; 1492 break; 1493 } 1494 msleep(100); 1495 } while (--timeout); 1496 break; 1497 default: 1498 break; 1499 } 1500 1501 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND, 1502 &mrioc->sysif_regs->write_sequence); 1503 1504 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1505 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1506 ioc_info(mrioc, 1507 "ioc_status/ioc_onfig after %s reset is (0x%x)/(0x%x)\n", 1508 (!retval)?"successful":"failed", ioc_status, 1509 ioc_config); 1510 if (retval) 1511 mrioc->unrecoverable = 1; 1512 return retval; 1513 } 1514 1515 /** 1516 * mpi3mr_admin_request_post - Post request to admin queue 1517 * @mrioc: Adapter reference 1518 * @admin_req: MPI3 request 1519 * @admin_req_sz: Request size 1520 * @ignore_reset: Ignore reset in process 1521 * 1522 * Post the MPI3 request into admin request queue and 1523 * inform the controller, if the queue is full return 1524 * appropriate error. 1525 * 1526 * Return: 0 on success, non-zero on failure. 1527 */ 1528 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req, 1529 u16 admin_req_sz, u8 ignore_reset) 1530 { 1531 u16 areq_pi = 0, areq_ci = 0, max_entries = 0; 1532 int retval = 0; 1533 unsigned long flags; 1534 u8 *areq_entry; 1535 1536 if (mrioc->unrecoverable) { 1537 ioc_err(mrioc, "%s : Unrecoverable controller\n", __func__); 1538 return -EFAULT; 1539 } 1540 1541 spin_lock_irqsave(&mrioc->admin_req_lock, flags); 1542 areq_pi = mrioc->admin_req_pi; 1543 areq_ci = mrioc->admin_req_ci; 1544 max_entries = mrioc->num_admin_req; 1545 if ((areq_ci == (areq_pi + 1)) || ((!areq_ci) && 1546 (areq_pi == (max_entries - 1)))) { 1547 ioc_err(mrioc, "AdminReqQ full condition detected\n"); 1548 retval = -EAGAIN; 1549 goto out; 1550 } 1551 if (!ignore_reset && mrioc->reset_in_progress) { 1552 ioc_err(mrioc, "AdminReqQ submit reset in progress\n"); 1553 retval = -EAGAIN; 1554 goto out; 1555 } 1556 areq_entry = (u8 *)mrioc->admin_req_base + 1557 (areq_pi * MPI3MR_ADMIN_REQ_FRAME_SZ); 1558 memset(areq_entry, 0, MPI3MR_ADMIN_REQ_FRAME_SZ); 1559 memcpy(areq_entry, (u8 *)admin_req, admin_req_sz); 1560 1561 if (++areq_pi == max_entries) 1562 areq_pi = 0; 1563 mrioc->admin_req_pi = areq_pi; 1564 1565 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi); 1566 1567 out: 1568 spin_unlock_irqrestore(&mrioc->admin_req_lock, flags); 1569 1570 return retval; 1571 } 1572 1573 /** 1574 * mpi3mr_free_op_req_q_segments - free request memory segments 1575 * @mrioc: Adapter instance reference 1576 * @q_idx: operational request queue index 1577 * 1578 * Free memory segments allocated for operational request queue 1579 * 1580 * Return: Nothing. 1581 */ 1582 static void mpi3mr_free_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx) 1583 { 1584 u16 j; 1585 int size; 1586 struct segments *segments; 1587 1588 segments = mrioc->req_qinfo[q_idx].q_segments; 1589 if (!segments) 1590 return; 1591 1592 if (mrioc->enable_segqueue) { 1593 size = MPI3MR_OP_REQ_Q_SEG_SIZE; 1594 if (mrioc->req_qinfo[q_idx].q_segment_list) { 1595 dma_free_coherent(&mrioc->pdev->dev, 1596 MPI3MR_MAX_SEG_LIST_SIZE, 1597 mrioc->req_qinfo[q_idx].q_segment_list, 1598 mrioc->req_qinfo[q_idx].q_segment_list_dma); 1599 mrioc->req_qinfo[q_idx].q_segment_list = NULL; 1600 } 1601 } else 1602 size = mrioc->req_qinfo[q_idx].segment_qd * 1603 mrioc->facts.op_req_sz; 1604 1605 for (j = 0; j < mrioc->req_qinfo[q_idx].num_segments; j++) { 1606 if (!segments[j].segment) 1607 continue; 1608 dma_free_coherent(&mrioc->pdev->dev, 1609 size, segments[j].segment, segments[j].segment_dma); 1610 segments[j].segment = NULL; 1611 } 1612 kfree(mrioc->req_qinfo[q_idx].q_segments); 1613 mrioc->req_qinfo[q_idx].q_segments = NULL; 1614 mrioc->req_qinfo[q_idx].qid = 0; 1615 } 1616 1617 /** 1618 * mpi3mr_free_op_reply_q_segments - free reply memory segments 1619 * @mrioc: Adapter instance reference 1620 * @q_idx: operational reply queue index 1621 * 1622 * Free memory segments allocated for operational reply queue 1623 * 1624 * Return: Nothing. 1625 */ 1626 static void mpi3mr_free_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx) 1627 { 1628 u16 j; 1629 int size; 1630 struct segments *segments; 1631 1632 segments = mrioc->op_reply_qinfo[q_idx].q_segments; 1633 if (!segments) 1634 return; 1635 1636 if (mrioc->enable_segqueue) { 1637 size = MPI3MR_OP_REP_Q_SEG_SIZE; 1638 if (mrioc->op_reply_qinfo[q_idx].q_segment_list) { 1639 dma_free_coherent(&mrioc->pdev->dev, 1640 MPI3MR_MAX_SEG_LIST_SIZE, 1641 mrioc->op_reply_qinfo[q_idx].q_segment_list, 1642 mrioc->op_reply_qinfo[q_idx].q_segment_list_dma); 1643 mrioc->op_reply_qinfo[q_idx].q_segment_list = NULL; 1644 } 1645 } else 1646 size = mrioc->op_reply_qinfo[q_idx].segment_qd * 1647 mrioc->op_reply_desc_sz; 1648 1649 for (j = 0; j < mrioc->op_reply_qinfo[q_idx].num_segments; j++) { 1650 if (!segments[j].segment) 1651 continue; 1652 dma_free_coherent(&mrioc->pdev->dev, 1653 size, segments[j].segment, segments[j].segment_dma); 1654 segments[j].segment = NULL; 1655 } 1656 1657 kfree(mrioc->op_reply_qinfo[q_idx].q_segments); 1658 mrioc->op_reply_qinfo[q_idx].q_segments = NULL; 1659 mrioc->op_reply_qinfo[q_idx].qid = 0; 1660 } 1661 1662 /** 1663 * mpi3mr_delete_op_reply_q - delete operational reply queue 1664 * @mrioc: Adapter instance reference 1665 * @qidx: operational reply queue index 1666 * 1667 * Delete operatinal reply queue by issuing MPI request 1668 * through admin queue. 1669 * 1670 * Return: 0 on success, non-zero on failure. 1671 */ 1672 static int mpi3mr_delete_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx) 1673 { 1674 struct mpi3_delete_reply_queue_request delq_req; 1675 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx; 1676 int retval = 0; 1677 u16 reply_qid = 0, midx; 1678 1679 reply_qid = op_reply_q->qid; 1680 1681 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset); 1682 1683 if (!reply_qid) { 1684 retval = -1; 1685 ioc_err(mrioc, "Issue DelRepQ: called with invalid ReqQID\n"); 1686 goto out; 1687 } 1688 1689 (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount-- : 1690 mrioc->active_poll_qcount--; 1691 1692 memset(&delq_req, 0, sizeof(delq_req)); 1693 mutex_lock(&mrioc->init_cmds.mutex); 1694 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 1695 retval = -1; 1696 ioc_err(mrioc, "Issue DelRepQ: Init command is in use\n"); 1697 mutex_unlock(&mrioc->init_cmds.mutex); 1698 goto out; 1699 } 1700 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 1701 mrioc->init_cmds.is_waiting = 1; 1702 mrioc->init_cmds.callback = NULL; 1703 delq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 1704 delq_req.function = MPI3_FUNCTION_DELETE_REPLY_QUEUE; 1705 delq_req.queue_id = cpu_to_le16(reply_qid); 1706 1707 init_completion(&mrioc->init_cmds.done); 1708 retval = mpi3mr_admin_request_post(mrioc, &delq_req, sizeof(delq_req), 1709 1); 1710 if (retval) { 1711 ioc_err(mrioc, "Issue DelRepQ: Admin Post failed\n"); 1712 goto out_unlock; 1713 } 1714 wait_for_completion_timeout(&mrioc->init_cmds.done, 1715 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 1716 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 1717 ioc_err(mrioc, "delete reply queue timed out\n"); 1718 mpi3mr_check_rh_fault_ioc(mrioc, 1719 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT); 1720 retval = -1; 1721 goto out_unlock; 1722 } 1723 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 1724 != MPI3_IOCSTATUS_SUCCESS) { 1725 ioc_err(mrioc, 1726 "Issue DelRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 1727 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 1728 mrioc->init_cmds.ioc_loginfo); 1729 retval = -1; 1730 goto out_unlock; 1731 } 1732 mrioc->intr_info[midx].op_reply_q = NULL; 1733 1734 mpi3mr_free_op_reply_q_segments(mrioc, qidx); 1735 out_unlock: 1736 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 1737 mutex_unlock(&mrioc->init_cmds.mutex); 1738 out: 1739 1740 return retval; 1741 } 1742 1743 /** 1744 * mpi3mr_alloc_op_reply_q_segments -Alloc segmented reply pool 1745 * @mrioc: Adapter instance reference 1746 * @qidx: request queue index 1747 * 1748 * Allocate segmented memory pools for operational reply 1749 * queue. 1750 * 1751 * Return: 0 on success, non-zero on failure. 1752 */ 1753 static int mpi3mr_alloc_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx) 1754 { 1755 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx; 1756 int i, size; 1757 u64 *q_segment_list_entry = NULL; 1758 struct segments *segments; 1759 1760 if (mrioc->enable_segqueue) { 1761 op_reply_q->segment_qd = 1762 MPI3MR_OP_REP_Q_SEG_SIZE / mrioc->op_reply_desc_sz; 1763 1764 size = MPI3MR_OP_REP_Q_SEG_SIZE; 1765 1766 op_reply_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev, 1767 MPI3MR_MAX_SEG_LIST_SIZE, &op_reply_q->q_segment_list_dma, 1768 GFP_KERNEL); 1769 if (!op_reply_q->q_segment_list) 1770 return -ENOMEM; 1771 q_segment_list_entry = (u64 *)op_reply_q->q_segment_list; 1772 } else { 1773 op_reply_q->segment_qd = op_reply_q->num_replies; 1774 size = op_reply_q->num_replies * mrioc->op_reply_desc_sz; 1775 } 1776 1777 op_reply_q->num_segments = DIV_ROUND_UP(op_reply_q->num_replies, 1778 op_reply_q->segment_qd); 1779 1780 op_reply_q->q_segments = kcalloc(op_reply_q->num_segments, 1781 sizeof(struct segments), GFP_KERNEL); 1782 if (!op_reply_q->q_segments) 1783 return -ENOMEM; 1784 1785 segments = op_reply_q->q_segments; 1786 for (i = 0; i < op_reply_q->num_segments; i++) { 1787 segments[i].segment = 1788 dma_alloc_coherent(&mrioc->pdev->dev, 1789 size, &segments[i].segment_dma, GFP_KERNEL); 1790 if (!segments[i].segment) 1791 return -ENOMEM; 1792 if (mrioc->enable_segqueue) 1793 q_segment_list_entry[i] = 1794 (unsigned long)segments[i].segment_dma; 1795 } 1796 1797 return 0; 1798 } 1799 1800 /** 1801 * mpi3mr_alloc_op_req_q_segments - Alloc segmented req pool. 1802 * @mrioc: Adapter instance reference 1803 * @qidx: request queue index 1804 * 1805 * Allocate segmented memory pools for operational request 1806 * queue. 1807 * 1808 * Return: 0 on success, non-zero on failure. 1809 */ 1810 static int mpi3mr_alloc_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx) 1811 { 1812 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx; 1813 int i, size; 1814 u64 *q_segment_list_entry = NULL; 1815 struct segments *segments; 1816 1817 if (mrioc->enable_segqueue) { 1818 op_req_q->segment_qd = 1819 MPI3MR_OP_REQ_Q_SEG_SIZE / mrioc->facts.op_req_sz; 1820 1821 size = MPI3MR_OP_REQ_Q_SEG_SIZE; 1822 1823 op_req_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev, 1824 MPI3MR_MAX_SEG_LIST_SIZE, &op_req_q->q_segment_list_dma, 1825 GFP_KERNEL); 1826 if (!op_req_q->q_segment_list) 1827 return -ENOMEM; 1828 q_segment_list_entry = (u64 *)op_req_q->q_segment_list; 1829 1830 } else { 1831 op_req_q->segment_qd = op_req_q->num_requests; 1832 size = op_req_q->num_requests * mrioc->facts.op_req_sz; 1833 } 1834 1835 op_req_q->num_segments = DIV_ROUND_UP(op_req_q->num_requests, 1836 op_req_q->segment_qd); 1837 1838 op_req_q->q_segments = kcalloc(op_req_q->num_segments, 1839 sizeof(struct segments), GFP_KERNEL); 1840 if (!op_req_q->q_segments) 1841 return -ENOMEM; 1842 1843 segments = op_req_q->q_segments; 1844 for (i = 0; i < op_req_q->num_segments; i++) { 1845 segments[i].segment = 1846 dma_alloc_coherent(&mrioc->pdev->dev, 1847 size, &segments[i].segment_dma, GFP_KERNEL); 1848 if (!segments[i].segment) 1849 return -ENOMEM; 1850 if (mrioc->enable_segqueue) 1851 q_segment_list_entry[i] = 1852 (unsigned long)segments[i].segment_dma; 1853 } 1854 1855 return 0; 1856 } 1857 1858 /** 1859 * mpi3mr_create_op_reply_q - create operational reply queue 1860 * @mrioc: Adapter instance reference 1861 * @qidx: operational reply queue index 1862 * 1863 * Create operatinal reply queue by issuing MPI request 1864 * through admin queue. 1865 * 1866 * Return: 0 on success, non-zero on failure. 1867 */ 1868 static int mpi3mr_create_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx) 1869 { 1870 struct mpi3_create_reply_queue_request create_req; 1871 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx; 1872 int retval = 0; 1873 u16 reply_qid = 0, midx; 1874 1875 reply_qid = op_reply_q->qid; 1876 1877 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset); 1878 1879 if (reply_qid) { 1880 retval = -1; 1881 ioc_err(mrioc, "CreateRepQ: called for duplicate qid %d\n", 1882 reply_qid); 1883 1884 return retval; 1885 } 1886 1887 reply_qid = qidx + 1; 1888 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD; 1889 if (!mrioc->pdev->revision) 1890 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD4K; 1891 op_reply_q->ci = 0; 1892 op_reply_q->ephase = 1; 1893 atomic_set(&op_reply_q->pend_ios, 0); 1894 atomic_set(&op_reply_q->in_use, 0); 1895 op_reply_q->enable_irq_poll = false; 1896 1897 if (!op_reply_q->q_segments) { 1898 retval = mpi3mr_alloc_op_reply_q_segments(mrioc, qidx); 1899 if (retval) { 1900 mpi3mr_free_op_reply_q_segments(mrioc, qidx); 1901 goto out; 1902 } 1903 } 1904 1905 memset(&create_req, 0, sizeof(create_req)); 1906 mutex_lock(&mrioc->init_cmds.mutex); 1907 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 1908 retval = -1; 1909 ioc_err(mrioc, "CreateRepQ: Init command is in use\n"); 1910 goto out_unlock; 1911 } 1912 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 1913 mrioc->init_cmds.is_waiting = 1; 1914 mrioc->init_cmds.callback = NULL; 1915 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 1916 create_req.function = MPI3_FUNCTION_CREATE_REPLY_QUEUE; 1917 create_req.queue_id = cpu_to_le16(reply_qid); 1918 1919 if (midx < (mrioc->intr_info_count - mrioc->requested_poll_qcount)) 1920 op_reply_q->qtype = MPI3MR_DEFAULT_QUEUE; 1921 else 1922 op_reply_q->qtype = MPI3MR_POLL_QUEUE; 1923 1924 if (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) { 1925 create_req.flags = 1926 MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE; 1927 create_req.msix_index = 1928 cpu_to_le16(mrioc->intr_info[midx].msix_index); 1929 } else { 1930 create_req.msix_index = cpu_to_le16(mrioc->intr_info_count - 1); 1931 ioc_info(mrioc, "create reply queue(polled): for qid(%d), midx(%d)\n", 1932 reply_qid, midx); 1933 if (!mrioc->active_poll_qcount) 1934 disable_irq_nosync(pci_irq_vector(mrioc->pdev, 1935 mrioc->intr_info_count - 1)); 1936 } 1937 1938 if (mrioc->enable_segqueue) { 1939 create_req.flags |= 1940 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED; 1941 create_req.base_address = cpu_to_le64( 1942 op_reply_q->q_segment_list_dma); 1943 } else 1944 create_req.base_address = cpu_to_le64( 1945 op_reply_q->q_segments[0].segment_dma); 1946 1947 create_req.size = cpu_to_le16(op_reply_q->num_replies); 1948 1949 init_completion(&mrioc->init_cmds.done); 1950 retval = mpi3mr_admin_request_post(mrioc, &create_req, 1951 sizeof(create_req), 1); 1952 if (retval) { 1953 ioc_err(mrioc, "CreateRepQ: Admin Post failed\n"); 1954 goto out_unlock; 1955 } 1956 wait_for_completion_timeout(&mrioc->init_cmds.done, 1957 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 1958 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 1959 ioc_err(mrioc, "create reply queue timed out\n"); 1960 mpi3mr_check_rh_fault_ioc(mrioc, 1961 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT); 1962 retval = -1; 1963 goto out_unlock; 1964 } 1965 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 1966 != MPI3_IOCSTATUS_SUCCESS) { 1967 ioc_err(mrioc, 1968 "CreateRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 1969 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 1970 mrioc->init_cmds.ioc_loginfo); 1971 retval = -1; 1972 goto out_unlock; 1973 } 1974 op_reply_q->qid = reply_qid; 1975 if (midx < mrioc->intr_info_count) 1976 mrioc->intr_info[midx].op_reply_q = op_reply_q; 1977 1978 (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount++ : 1979 mrioc->active_poll_qcount++; 1980 1981 out_unlock: 1982 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 1983 mutex_unlock(&mrioc->init_cmds.mutex); 1984 out: 1985 1986 return retval; 1987 } 1988 1989 /** 1990 * mpi3mr_create_op_req_q - create operational request queue 1991 * @mrioc: Adapter instance reference 1992 * @idx: operational request queue index 1993 * @reply_qid: Reply queue ID 1994 * 1995 * Create operatinal request queue by issuing MPI request 1996 * through admin queue. 1997 * 1998 * Return: 0 on success, non-zero on failure. 1999 */ 2000 static int mpi3mr_create_op_req_q(struct mpi3mr_ioc *mrioc, u16 idx, 2001 u16 reply_qid) 2002 { 2003 struct mpi3_create_request_queue_request create_req; 2004 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + idx; 2005 int retval = 0; 2006 u16 req_qid = 0; 2007 2008 req_qid = op_req_q->qid; 2009 2010 if (req_qid) { 2011 retval = -1; 2012 ioc_err(mrioc, "CreateReqQ: called for duplicate qid %d\n", 2013 req_qid); 2014 2015 return retval; 2016 } 2017 req_qid = idx + 1; 2018 2019 op_req_q->num_requests = MPI3MR_OP_REQ_Q_QD; 2020 op_req_q->ci = 0; 2021 op_req_q->pi = 0; 2022 op_req_q->reply_qid = reply_qid; 2023 spin_lock_init(&op_req_q->q_lock); 2024 2025 if (!op_req_q->q_segments) { 2026 retval = mpi3mr_alloc_op_req_q_segments(mrioc, idx); 2027 if (retval) { 2028 mpi3mr_free_op_req_q_segments(mrioc, idx); 2029 goto out; 2030 } 2031 } 2032 2033 memset(&create_req, 0, sizeof(create_req)); 2034 mutex_lock(&mrioc->init_cmds.mutex); 2035 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 2036 retval = -1; 2037 ioc_err(mrioc, "CreateReqQ: Init command is in use\n"); 2038 goto out_unlock; 2039 } 2040 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 2041 mrioc->init_cmds.is_waiting = 1; 2042 mrioc->init_cmds.callback = NULL; 2043 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 2044 create_req.function = MPI3_FUNCTION_CREATE_REQUEST_QUEUE; 2045 create_req.queue_id = cpu_to_le16(req_qid); 2046 if (mrioc->enable_segqueue) { 2047 create_req.flags = 2048 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED; 2049 create_req.base_address = cpu_to_le64( 2050 op_req_q->q_segment_list_dma); 2051 } else 2052 create_req.base_address = cpu_to_le64( 2053 op_req_q->q_segments[0].segment_dma); 2054 create_req.reply_queue_id = cpu_to_le16(reply_qid); 2055 create_req.size = cpu_to_le16(op_req_q->num_requests); 2056 2057 init_completion(&mrioc->init_cmds.done); 2058 retval = mpi3mr_admin_request_post(mrioc, &create_req, 2059 sizeof(create_req), 1); 2060 if (retval) { 2061 ioc_err(mrioc, "CreateReqQ: Admin Post failed\n"); 2062 goto out_unlock; 2063 } 2064 wait_for_completion_timeout(&mrioc->init_cmds.done, 2065 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 2066 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2067 ioc_err(mrioc, "create request queue timed out\n"); 2068 mpi3mr_check_rh_fault_ioc(mrioc, 2069 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT); 2070 retval = -1; 2071 goto out_unlock; 2072 } 2073 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2074 != MPI3_IOCSTATUS_SUCCESS) { 2075 ioc_err(mrioc, 2076 "CreateReqQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 2077 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 2078 mrioc->init_cmds.ioc_loginfo); 2079 retval = -1; 2080 goto out_unlock; 2081 } 2082 op_req_q->qid = req_qid; 2083 2084 out_unlock: 2085 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2086 mutex_unlock(&mrioc->init_cmds.mutex); 2087 out: 2088 2089 return retval; 2090 } 2091 2092 /** 2093 * mpi3mr_create_op_queues - create operational queue pairs 2094 * @mrioc: Adapter instance reference 2095 * 2096 * Allocate memory for operational queue meta data and call 2097 * create request and reply queue functions. 2098 * 2099 * Return: 0 on success, non-zero on failures. 2100 */ 2101 static int mpi3mr_create_op_queues(struct mpi3mr_ioc *mrioc) 2102 { 2103 int retval = 0; 2104 u16 num_queues = 0, i = 0, msix_count_op_q = 1; 2105 2106 num_queues = min_t(int, mrioc->facts.max_op_reply_q, 2107 mrioc->facts.max_op_req_q); 2108 2109 msix_count_op_q = 2110 mrioc->intr_info_count - mrioc->op_reply_q_offset; 2111 if (!mrioc->num_queues) 2112 mrioc->num_queues = min_t(int, num_queues, msix_count_op_q); 2113 /* 2114 * During reset set the num_queues to the number of queues 2115 * that was set before the reset. 2116 */ 2117 num_queues = mrioc->num_op_reply_q ? 2118 mrioc->num_op_reply_q : mrioc->num_queues; 2119 ioc_info(mrioc, "trying to create %d operational queue pairs\n", 2120 num_queues); 2121 2122 if (!mrioc->req_qinfo) { 2123 mrioc->req_qinfo = kcalloc(num_queues, 2124 sizeof(struct op_req_qinfo), GFP_KERNEL); 2125 if (!mrioc->req_qinfo) { 2126 retval = -1; 2127 goto out_failed; 2128 } 2129 2130 mrioc->op_reply_qinfo = kzalloc(sizeof(struct op_reply_qinfo) * 2131 num_queues, GFP_KERNEL); 2132 if (!mrioc->op_reply_qinfo) { 2133 retval = -1; 2134 goto out_failed; 2135 } 2136 } 2137 2138 if (mrioc->enable_segqueue) 2139 ioc_info(mrioc, 2140 "allocating operational queues through segmented queues\n"); 2141 2142 for (i = 0; i < num_queues; i++) { 2143 if (mpi3mr_create_op_reply_q(mrioc, i)) { 2144 ioc_err(mrioc, "Cannot create OP RepQ %d\n", i); 2145 break; 2146 } 2147 if (mpi3mr_create_op_req_q(mrioc, i, 2148 mrioc->op_reply_qinfo[i].qid)) { 2149 ioc_err(mrioc, "Cannot create OP ReqQ %d\n", i); 2150 mpi3mr_delete_op_reply_q(mrioc, i); 2151 break; 2152 } 2153 } 2154 2155 if (i == 0) { 2156 /* Not even one queue is created successfully*/ 2157 retval = -1; 2158 goto out_failed; 2159 } 2160 mrioc->num_op_reply_q = mrioc->num_op_req_q = i; 2161 ioc_info(mrioc, 2162 "successfully created %d operational queue pairs(default/polled) queue = (%d/%d)\n", 2163 mrioc->num_op_reply_q, mrioc->default_qcount, 2164 mrioc->active_poll_qcount); 2165 2166 return retval; 2167 out_failed: 2168 kfree(mrioc->req_qinfo); 2169 mrioc->req_qinfo = NULL; 2170 2171 kfree(mrioc->op_reply_qinfo); 2172 mrioc->op_reply_qinfo = NULL; 2173 2174 return retval; 2175 } 2176 2177 /** 2178 * mpi3mr_op_request_post - Post request to operational queue 2179 * @mrioc: Adapter reference 2180 * @op_req_q: Operational request queue info 2181 * @req: MPI3 request 2182 * 2183 * Post the MPI3 request into operational request queue and 2184 * inform the controller, if the queue is full return 2185 * appropriate error. 2186 * 2187 * Return: 0 on success, non-zero on failure. 2188 */ 2189 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc, 2190 struct op_req_qinfo *op_req_q, u8 *req) 2191 { 2192 u16 pi = 0, max_entries, reply_qidx = 0, midx; 2193 int retval = 0; 2194 unsigned long flags; 2195 u8 *req_entry; 2196 void *segment_base_addr; 2197 u16 req_sz = mrioc->facts.op_req_sz; 2198 struct segments *segments = op_req_q->q_segments; 2199 2200 reply_qidx = op_req_q->reply_qid - 1; 2201 2202 if (mrioc->unrecoverable) 2203 return -EFAULT; 2204 2205 spin_lock_irqsave(&op_req_q->q_lock, flags); 2206 pi = op_req_q->pi; 2207 max_entries = op_req_q->num_requests; 2208 2209 if (mpi3mr_check_req_qfull(op_req_q)) { 2210 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX( 2211 reply_qidx, mrioc->op_reply_q_offset); 2212 mpi3mr_process_op_reply_q(mrioc, mrioc->intr_info[midx].op_reply_q); 2213 2214 if (mpi3mr_check_req_qfull(op_req_q)) { 2215 retval = -EAGAIN; 2216 goto out; 2217 } 2218 } 2219 2220 if (mrioc->reset_in_progress) { 2221 ioc_err(mrioc, "OpReqQ submit reset in progress\n"); 2222 retval = -EAGAIN; 2223 goto out; 2224 } 2225 2226 segment_base_addr = segments[pi / op_req_q->segment_qd].segment; 2227 req_entry = (u8 *)segment_base_addr + 2228 ((pi % op_req_q->segment_qd) * req_sz); 2229 2230 memset(req_entry, 0, req_sz); 2231 memcpy(req_entry, req, MPI3MR_ADMIN_REQ_FRAME_SZ); 2232 2233 if (++pi == max_entries) 2234 pi = 0; 2235 op_req_q->pi = pi; 2236 2237 #ifndef CONFIG_PREEMPT_RT 2238 if (atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios) 2239 > MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT) 2240 mrioc->op_reply_qinfo[reply_qidx].enable_irq_poll = true; 2241 #else 2242 atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios); 2243 #endif 2244 2245 writel(op_req_q->pi, 2246 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].producer_index); 2247 2248 out: 2249 spin_unlock_irqrestore(&op_req_q->q_lock, flags); 2250 return retval; 2251 } 2252 2253 /** 2254 * mpi3mr_check_rh_fault_ioc - check reset history and fault 2255 * controller 2256 * @mrioc: Adapter instance reference 2257 * @reason_code: reason code for the fault. 2258 * 2259 * This routine will save snapdump and fault the controller with 2260 * the given reason code if it is not already in the fault or 2261 * not asynchronosuly reset. This will be used to handle 2262 * initilaization time faults/resets/timeout as in those cases 2263 * immediate soft reset invocation is not required. 2264 * 2265 * Return: None. 2266 */ 2267 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code) 2268 { 2269 u32 ioc_status, host_diagnostic, timeout; 2270 2271 if (mrioc->unrecoverable) { 2272 ioc_err(mrioc, "controller is unrecoverable\n"); 2273 return; 2274 } 2275 2276 if (!pci_device_is_present(mrioc->pdev)) { 2277 mrioc->unrecoverable = 1; 2278 ioc_err(mrioc, "controller is not present\n"); 2279 return; 2280 } 2281 2282 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 2283 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) || 2284 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) { 2285 mpi3mr_print_fault_info(mrioc); 2286 return; 2287 } 2288 mpi3mr_set_diagsave(mrioc); 2289 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, 2290 reason_code); 2291 timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10; 2292 do { 2293 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic); 2294 if (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS)) 2295 break; 2296 msleep(100); 2297 } while (--timeout); 2298 } 2299 2300 /** 2301 * mpi3mr_sync_timestamp - Issue time stamp sync request 2302 * @mrioc: Adapter reference 2303 * 2304 * Issue IO unit control MPI request to synchornize firmware 2305 * timestamp with host time. 2306 * 2307 * Return: 0 on success, non-zero on failure. 2308 */ 2309 static int mpi3mr_sync_timestamp(struct mpi3mr_ioc *mrioc) 2310 { 2311 ktime_t current_time; 2312 struct mpi3_iounit_control_request iou_ctrl; 2313 int retval = 0; 2314 2315 memset(&iou_ctrl, 0, sizeof(iou_ctrl)); 2316 mutex_lock(&mrioc->init_cmds.mutex); 2317 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 2318 retval = -1; 2319 ioc_err(mrioc, "Issue IOUCTL time_stamp: command is in use\n"); 2320 mutex_unlock(&mrioc->init_cmds.mutex); 2321 goto out; 2322 } 2323 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 2324 mrioc->init_cmds.is_waiting = 1; 2325 mrioc->init_cmds.callback = NULL; 2326 iou_ctrl.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 2327 iou_ctrl.function = MPI3_FUNCTION_IO_UNIT_CONTROL; 2328 iou_ctrl.operation = MPI3_CTRL_OP_UPDATE_TIMESTAMP; 2329 current_time = ktime_get_real(); 2330 iou_ctrl.param64[0] = cpu_to_le64(ktime_to_ms(current_time)); 2331 2332 init_completion(&mrioc->init_cmds.done); 2333 retval = mpi3mr_admin_request_post(mrioc, &iou_ctrl, 2334 sizeof(iou_ctrl), 0); 2335 if (retval) { 2336 ioc_err(mrioc, "Issue IOUCTL time_stamp: Admin Post failed\n"); 2337 goto out_unlock; 2338 } 2339 2340 wait_for_completion_timeout(&mrioc->init_cmds.done, 2341 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 2342 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2343 ioc_err(mrioc, "Issue IOUCTL time_stamp: command timed out\n"); 2344 mrioc->init_cmds.is_waiting = 0; 2345 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET)) 2346 mpi3mr_soft_reset_handler(mrioc, 2347 MPI3MR_RESET_FROM_TSU_TIMEOUT, 1); 2348 retval = -1; 2349 goto out_unlock; 2350 } 2351 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2352 != MPI3_IOCSTATUS_SUCCESS) { 2353 ioc_err(mrioc, 2354 "Issue IOUCTL time_stamp: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 2355 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 2356 mrioc->init_cmds.ioc_loginfo); 2357 retval = -1; 2358 goto out_unlock; 2359 } 2360 2361 out_unlock: 2362 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2363 mutex_unlock(&mrioc->init_cmds.mutex); 2364 2365 out: 2366 return retval; 2367 } 2368 2369 /** 2370 * mpi3mr_print_pkg_ver - display controller fw package version 2371 * @mrioc: Adapter reference 2372 * 2373 * Retrieve firmware package version from the component image 2374 * header of the controller flash and display it. 2375 * 2376 * Return: 0 on success and non-zero on failure. 2377 */ 2378 static int mpi3mr_print_pkg_ver(struct mpi3mr_ioc *mrioc) 2379 { 2380 struct mpi3_ci_upload_request ci_upload; 2381 int retval = -1; 2382 void *data = NULL; 2383 dma_addr_t data_dma; 2384 struct mpi3_ci_manifest_mpi *manifest; 2385 u32 data_len = sizeof(struct mpi3_ci_manifest_mpi); 2386 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 2387 2388 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma, 2389 GFP_KERNEL); 2390 if (!data) 2391 return -ENOMEM; 2392 2393 memset(&ci_upload, 0, sizeof(ci_upload)); 2394 mutex_lock(&mrioc->init_cmds.mutex); 2395 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 2396 ioc_err(mrioc, "sending get package version failed due to command in use\n"); 2397 mutex_unlock(&mrioc->init_cmds.mutex); 2398 goto out; 2399 } 2400 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 2401 mrioc->init_cmds.is_waiting = 1; 2402 mrioc->init_cmds.callback = NULL; 2403 ci_upload.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 2404 ci_upload.function = MPI3_FUNCTION_CI_UPLOAD; 2405 ci_upload.msg_flags = MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY; 2406 ci_upload.signature1 = cpu_to_le32(MPI3_IMAGE_HEADER_SIGNATURE1_MANIFEST); 2407 ci_upload.image_offset = cpu_to_le32(MPI3_IMAGE_HEADER_SIZE); 2408 ci_upload.segment_size = cpu_to_le32(data_len); 2409 2410 mpi3mr_add_sg_single(&ci_upload.sgl, sgl_flags, data_len, 2411 data_dma); 2412 init_completion(&mrioc->init_cmds.done); 2413 retval = mpi3mr_admin_request_post(mrioc, &ci_upload, 2414 sizeof(ci_upload), 1); 2415 if (retval) { 2416 ioc_err(mrioc, "posting get package version failed\n"); 2417 goto out_unlock; 2418 } 2419 wait_for_completion_timeout(&mrioc->init_cmds.done, 2420 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 2421 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2422 ioc_err(mrioc, "get package version timed out\n"); 2423 mpi3mr_check_rh_fault_ioc(mrioc, 2424 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT); 2425 retval = -1; 2426 goto out_unlock; 2427 } 2428 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2429 == MPI3_IOCSTATUS_SUCCESS) { 2430 manifest = (struct mpi3_ci_manifest_mpi *) data; 2431 if (manifest->manifest_type == MPI3_CI_MANIFEST_TYPE_MPI) { 2432 ioc_info(mrioc, 2433 "firmware package version(%d.%d.%d.%d.%05d-%05d)\n", 2434 manifest->package_version.gen_major, 2435 manifest->package_version.gen_minor, 2436 manifest->package_version.phase_major, 2437 manifest->package_version.phase_minor, 2438 manifest->package_version.customer_id, 2439 manifest->package_version.build_num); 2440 } 2441 } 2442 retval = 0; 2443 out_unlock: 2444 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2445 mutex_unlock(&mrioc->init_cmds.mutex); 2446 2447 out: 2448 if (data) 2449 dma_free_coherent(&mrioc->pdev->dev, data_len, data, 2450 data_dma); 2451 return retval; 2452 } 2453 2454 /** 2455 * mpi3mr_watchdog_work - watchdog thread to monitor faults 2456 * @work: work struct 2457 * 2458 * Watch dog work periodically executed (1 second interval) to 2459 * monitor firmware fault and to issue periodic timer sync to 2460 * the firmware. 2461 * 2462 * Return: Nothing. 2463 */ 2464 static void mpi3mr_watchdog_work(struct work_struct *work) 2465 { 2466 struct mpi3mr_ioc *mrioc = 2467 container_of(work, struct mpi3mr_ioc, watchdog_work.work); 2468 unsigned long flags; 2469 enum mpi3mr_iocstate ioc_state; 2470 u32 fault, host_diagnostic, ioc_status; 2471 u32 reset_reason = MPI3MR_RESET_FROM_FAULT_WATCH; 2472 2473 if (mrioc->reset_in_progress) 2474 return; 2475 2476 if (!mrioc->unrecoverable && !pci_device_is_present(mrioc->pdev)) { 2477 ioc_err(mrioc, "watchdog could not detect the controller\n"); 2478 mrioc->unrecoverable = 1; 2479 } 2480 2481 if (mrioc->unrecoverable) { 2482 ioc_err(mrioc, 2483 "flush pending commands for unrecoverable controller\n"); 2484 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc); 2485 return; 2486 } 2487 2488 if (mrioc->ts_update_counter++ >= MPI3MR_TSUPDATE_INTERVAL) { 2489 mrioc->ts_update_counter = 0; 2490 mpi3mr_sync_timestamp(mrioc); 2491 } 2492 2493 if ((mrioc->prepare_for_reset) && 2494 ((mrioc->prepare_for_reset_timeout_counter++) >= 2495 MPI3MR_PREPARE_FOR_RESET_TIMEOUT)) { 2496 mpi3mr_soft_reset_handler(mrioc, 2497 MPI3MR_RESET_FROM_CIACTVRST_TIMER, 1); 2498 return; 2499 } 2500 2501 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 2502 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) { 2503 mpi3mr_soft_reset_handler(mrioc, MPI3MR_RESET_FROM_FIRMWARE, 0); 2504 return; 2505 } 2506 2507 /*Check for fault state every one second and issue Soft reset*/ 2508 ioc_state = mpi3mr_get_iocstate(mrioc); 2509 if (ioc_state != MRIOC_STATE_FAULT) 2510 goto schedule_work; 2511 2512 fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK; 2513 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic); 2514 if (host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS) { 2515 if (!mrioc->diagsave_timeout) { 2516 mpi3mr_print_fault_info(mrioc); 2517 ioc_warn(mrioc, "diag save in progress\n"); 2518 } 2519 if ((mrioc->diagsave_timeout++) <= MPI3_SYSIF_DIAG_SAVE_TIMEOUT) 2520 goto schedule_work; 2521 } 2522 2523 mpi3mr_print_fault_info(mrioc); 2524 mrioc->diagsave_timeout = 0; 2525 2526 switch (fault) { 2527 case MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED: 2528 case MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED: 2529 ioc_warn(mrioc, 2530 "controller requires system power cycle, marking controller as unrecoverable\n"); 2531 mrioc->unrecoverable = 1; 2532 goto schedule_work; 2533 case MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS: 2534 goto schedule_work; 2535 case MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET: 2536 reset_reason = MPI3MR_RESET_FROM_CIACTIV_FAULT; 2537 break; 2538 default: 2539 break; 2540 } 2541 mpi3mr_soft_reset_handler(mrioc, reset_reason, 0); 2542 return; 2543 2544 schedule_work: 2545 spin_lock_irqsave(&mrioc->watchdog_lock, flags); 2546 if (mrioc->watchdog_work_q) 2547 queue_delayed_work(mrioc->watchdog_work_q, 2548 &mrioc->watchdog_work, 2549 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL)); 2550 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags); 2551 return; 2552 } 2553 2554 /** 2555 * mpi3mr_start_watchdog - Start watchdog 2556 * @mrioc: Adapter instance reference 2557 * 2558 * Create and start the watchdog thread to monitor controller 2559 * faults. 2560 * 2561 * Return: Nothing. 2562 */ 2563 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc) 2564 { 2565 if (mrioc->watchdog_work_q) 2566 return; 2567 2568 INIT_DELAYED_WORK(&mrioc->watchdog_work, mpi3mr_watchdog_work); 2569 snprintf(mrioc->watchdog_work_q_name, 2570 sizeof(mrioc->watchdog_work_q_name), "watchdog_%s%d", mrioc->name, 2571 mrioc->id); 2572 mrioc->watchdog_work_q = 2573 create_singlethread_workqueue(mrioc->watchdog_work_q_name); 2574 if (!mrioc->watchdog_work_q) { 2575 ioc_err(mrioc, "%s: failed (line=%d)\n", __func__, __LINE__); 2576 return; 2577 } 2578 2579 if (mrioc->watchdog_work_q) 2580 queue_delayed_work(mrioc->watchdog_work_q, 2581 &mrioc->watchdog_work, 2582 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL)); 2583 } 2584 2585 /** 2586 * mpi3mr_stop_watchdog - Stop watchdog 2587 * @mrioc: Adapter instance reference 2588 * 2589 * Stop the watchdog thread created to monitor controller 2590 * faults. 2591 * 2592 * Return: Nothing. 2593 */ 2594 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc) 2595 { 2596 unsigned long flags; 2597 struct workqueue_struct *wq; 2598 2599 spin_lock_irqsave(&mrioc->watchdog_lock, flags); 2600 wq = mrioc->watchdog_work_q; 2601 mrioc->watchdog_work_q = NULL; 2602 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags); 2603 if (wq) { 2604 if (!cancel_delayed_work_sync(&mrioc->watchdog_work)) 2605 flush_workqueue(wq); 2606 destroy_workqueue(wq); 2607 } 2608 } 2609 2610 /** 2611 * mpi3mr_setup_admin_qpair - Setup admin queue pair 2612 * @mrioc: Adapter instance reference 2613 * 2614 * Allocate memory for admin queue pair if required and register 2615 * the admin queue with the controller. 2616 * 2617 * Return: 0 on success, non-zero on failures. 2618 */ 2619 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc) 2620 { 2621 int retval = 0; 2622 u32 num_admin_entries = 0; 2623 2624 mrioc->admin_req_q_sz = MPI3MR_ADMIN_REQ_Q_SIZE; 2625 mrioc->num_admin_req = mrioc->admin_req_q_sz / 2626 MPI3MR_ADMIN_REQ_FRAME_SZ; 2627 mrioc->admin_req_ci = mrioc->admin_req_pi = 0; 2628 2629 mrioc->admin_reply_q_sz = MPI3MR_ADMIN_REPLY_Q_SIZE; 2630 mrioc->num_admin_replies = mrioc->admin_reply_q_sz / 2631 MPI3MR_ADMIN_REPLY_FRAME_SZ; 2632 mrioc->admin_reply_ci = 0; 2633 mrioc->admin_reply_ephase = 1; 2634 atomic_set(&mrioc->admin_reply_q_in_use, 0); 2635 2636 if (!mrioc->admin_req_base) { 2637 mrioc->admin_req_base = dma_alloc_coherent(&mrioc->pdev->dev, 2638 mrioc->admin_req_q_sz, &mrioc->admin_req_dma, GFP_KERNEL); 2639 2640 if (!mrioc->admin_req_base) { 2641 retval = -1; 2642 goto out_failed; 2643 } 2644 2645 mrioc->admin_reply_base = dma_alloc_coherent(&mrioc->pdev->dev, 2646 mrioc->admin_reply_q_sz, &mrioc->admin_reply_dma, 2647 GFP_KERNEL); 2648 2649 if (!mrioc->admin_reply_base) { 2650 retval = -1; 2651 goto out_failed; 2652 } 2653 } 2654 2655 num_admin_entries = (mrioc->num_admin_replies << 16) | 2656 (mrioc->num_admin_req); 2657 writel(num_admin_entries, &mrioc->sysif_regs->admin_queue_num_entries); 2658 mpi3mr_writeq(mrioc->admin_req_dma, 2659 &mrioc->sysif_regs->admin_request_queue_address); 2660 mpi3mr_writeq(mrioc->admin_reply_dma, 2661 &mrioc->sysif_regs->admin_reply_queue_address); 2662 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi); 2663 writel(mrioc->admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci); 2664 return retval; 2665 2666 out_failed: 2667 2668 if (mrioc->admin_reply_base) { 2669 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz, 2670 mrioc->admin_reply_base, mrioc->admin_reply_dma); 2671 mrioc->admin_reply_base = NULL; 2672 } 2673 if (mrioc->admin_req_base) { 2674 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz, 2675 mrioc->admin_req_base, mrioc->admin_req_dma); 2676 mrioc->admin_req_base = NULL; 2677 } 2678 return retval; 2679 } 2680 2681 /** 2682 * mpi3mr_issue_iocfacts - Send IOC Facts 2683 * @mrioc: Adapter instance reference 2684 * @facts_data: Cached IOC facts data 2685 * 2686 * Issue IOC Facts MPI request through admin queue and wait for 2687 * the completion of it or time out. 2688 * 2689 * Return: 0 on success, non-zero on failures. 2690 */ 2691 static int mpi3mr_issue_iocfacts(struct mpi3mr_ioc *mrioc, 2692 struct mpi3_ioc_facts_data *facts_data) 2693 { 2694 struct mpi3_ioc_facts_request iocfacts_req; 2695 void *data = NULL; 2696 dma_addr_t data_dma; 2697 u32 data_len = sizeof(*facts_data); 2698 int retval = 0; 2699 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 2700 2701 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma, 2702 GFP_KERNEL); 2703 2704 if (!data) { 2705 retval = -1; 2706 goto out; 2707 } 2708 2709 memset(&iocfacts_req, 0, sizeof(iocfacts_req)); 2710 mutex_lock(&mrioc->init_cmds.mutex); 2711 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 2712 retval = -1; 2713 ioc_err(mrioc, "Issue IOCFacts: Init command is in use\n"); 2714 mutex_unlock(&mrioc->init_cmds.mutex); 2715 goto out; 2716 } 2717 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 2718 mrioc->init_cmds.is_waiting = 1; 2719 mrioc->init_cmds.callback = NULL; 2720 iocfacts_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 2721 iocfacts_req.function = MPI3_FUNCTION_IOC_FACTS; 2722 2723 mpi3mr_add_sg_single(&iocfacts_req.sgl, sgl_flags, data_len, 2724 data_dma); 2725 2726 init_completion(&mrioc->init_cmds.done); 2727 retval = mpi3mr_admin_request_post(mrioc, &iocfacts_req, 2728 sizeof(iocfacts_req), 1); 2729 if (retval) { 2730 ioc_err(mrioc, "Issue IOCFacts: Admin Post failed\n"); 2731 goto out_unlock; 2732 } 2733 wait_for_completion_timeout(&mrioc->init_cmds.done, 2734 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 2735 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2736 ioc_err(mrioc, "ioc_facts timed out\n"); 2737 mpi3mr_check_rh_fault_ioc(mrioc, 2738 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT); 2739 retval = -1; 2740 goto out_unlock; 2741 } 2742 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2743 != MPI3_IOCSTATUS_SUCCESS) { 2744 ioc_err(mrioc, 2745 "Issue IOCFacts: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 2746 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 2747 mrioc->init_cmds.ioc_loginfo); 2748 retval = -1; 2749 goto out_unlock; 2750 } 2751 memcpy(facts_data, (u8 *)data, data_len); 2752 mpi3mr_process_factsdata(mrioc, facts_data); 2753 out_unlock: 2754 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2755 mutex_unlock(&mrioc->init_cmds.mutex); 2756 2757 out: 2758 if (data) 2759 dma_free_coherent(&mrioc->pdev->dev, data_len, data, data_dma); 2760 2761 return retval; 2762 } 2763 2764 /** 2765 * mpi3mr_check_reset_dma_mask - Process IOC facts data 2766 * @mrioc: Adapter instance reference 2767 * 2768 * Check whether the new DMA mask requested through IOCFacts by 2769 * firmware needs to be set, if so set it . 2770 * 2771 * Return: 0 on success, non-zero on failure. 2772 */ 2773 static inline int mpi3mr_check_reset_dma_mask(struct mpi3mr_ioc *mrioc) 2774 { 2775 struct pci_dev *pdev = mrioc->pdev; 2776 int r; 2777 u64 facts_dma_mask = DMA_BIT_MASK(mrioc->facts.dma_mask); 2778 2779 if (!mrioc->facts.dma_mask || (mrioc->dma_mask <= facts_dma_mask)) 2780 return 0; 2781 2782 ioc_info(mrioc, "Changing DMA mask from 0x%016llx to 0x%016llx\n", 2783 mrioc->dma_mask, facts_dma_mask); 2784 2785 r = dma_set_mask_and_coherent(&pdev->dev, facts_dma_mask); 2786 if (r) { 2787 ioc_err(mrioc, "Setting DMA mask to 0x%016llx failed: %d\n", 2788 facts_dma_mask, r); 2789 return r; 2790 } 2791 mrioc->dma_mask = facts_dma_mask; 2792 return r; 2793 } 2794 2795 /** 2796 * mpi3mr_process_factsdata - Process IOC facts data 2797 * @mrioc: Adapter instance reference 2798 * @facts_data: Cached IOC facts data 2799 * 2800 * Convert IOC facts data into cpu endianness and cache it in 2801 * the driver . 2802 * 2803 * Return: Nothing. 2804 */ 2805 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc, 2806 struct mpi3_ioc_facts_data *facts_data) 2807 { 2808 u32 ioc_config, req_sz, facts_flags; 2809 2810 if ((le16_to_cpu(facts_data->ioc_facts_data_length)) != 2811 (sizeof(*facts_data) / 4)) { 2812 ioc_warn(mrioc, 2813 "IOCFactsdata length mismatch driver_sz(%zu) firmware_sz(%d)\n", 2814 sizeof(*facts_data), 2815 le16_to_cpu(facts_data->ioc_facts_data_length) * 4); 2816 } 2817 2818 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 2819 req_sz = 1 << ((ioc_config & MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ) >> 2820 MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT); 2821 if (le16_to_cpu(facts_data->ioc_request_frame_size) != (req_sz / 4)) { 2822 ioc_err(mrioc, 2823 "IOCFacts data reqFrameSize mismatch hw_size(%d) firmware_sz(%d)\n", 2824 req_sz / 4, le16_to_cpu(facts_data->ioc_request_frame_size)); 2825 } 2826 2827 memset(&mrioc->facts, 0, sizeof(mrioc->facts)); 2828 2829 facts_flags = le32_to_cpu(facts_data->flags); 2830 mrioc->facts.op_req_sz = req_sz; 2831 mrioc->op_reply_desc_sz = 1 << ((ioc_config & 2832 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ) >> 2833 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT); 2834 2835 mrioc->facts.ioc_num = facts_data->ioc_number; 2836 mrioc->facts.who_init = facts_data->who_init; 2837 mrioc->facts.max_msix_vectors = le16_to_cpu(facts_data->max_msix_vectors); 2838 mrioc->facts.personality = (facts_flags & 2839 MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK); 2840 mrioc->facts.dma_mask = (facts_flags & 2841 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK) >> 2842 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT; 2843 mrioc->facts.protocol_flags = facts_data->protocol_flags; 2844 mrioc->facts.mpi_version = le32_to_cpu(facts_data->mpi_version.word); 2845 mrioc->facts.max_reqs = le16_to_cpu(facts_data->max_outstanding_requests); 2846 mrioc->facts.product_id = le16_to_cpu(facts_data->product_id); 2847 mrioc->facts.reply_sz = le16_to_cpu(facts_data->reply_frame_size) * 4; 2848 mrioc->facts.exceptions = le16_to_cpu(facts_data->ioc_exceptions); 2849 mrioc->facts.max_perids = le16_to_cpu(facts_data->max_persistent_id); 2850 mrioc->facts.max_vds = le16_to_cpu(facts_data->max_vds); 2851 mrioc->facts.max_hpds = le16_to_cpu(facts_data->max_host_pds); 2852 mrioc->facts.max_advhpds = le16_to_cpu(facts_data->max_adv_host_pds); 2853 mrioc->facts.max_raid_pds = le16_to_cpu(facts_data->max_raid_pds); 2854 mrioc->facts.max_nvme = le16_to_cpu(facts_data->max_nvme); 2855 mrioc->facts.max_pcie_switches = 2856 le16_to_cpu(facts_data->max_pcie_switches); 2857 mrioc->facts.max_sasexpanders = 2858 le16_to_cpu(facts_data->max_sas_expanders); 2859 mrioc->facts.max_sasinitiators = 2860 le16_to_cpu(facts_data->max_sas_initiators); 2861 mrioc->facts.max_enclosures = le16_to_cpu(facts_data->max_enclosures); 2862 mrioc->facts.min_devhandle = le16_to_cpu(facts_data->min_dev_handle); 2863 mrioc->facts.max_devhandle = le16_to_cpu(facts_data->max_dev_handle); 2864 mrioc->facts.max_op_req_q = 2865 le16_to_cpu(facts_data->max_operational_request_queues); 2866 mrioc->facts.max_op_reply_q = 2867 le16_to_cpu(facts_data->max_operational_reply_queues); 2868 mrioc->facts.ioc_capabilities = 2869 le32_to_cpu(facts_data->ioc_capabilities); 2870 mrioc->facts.fw_ver.build_num = 2871 le16_to_cpu(facts_data->fw_version.build_num); 2872 mrioc->facts.fw_ver.cust_id = 2873 le16_to_cpu(facts_data->fw_version.customer_id); 2874 mrioc->facts.fw_ver.ph_minor = facts_data->fw_version.phase_minor; 2875 mrioc->facts.fw_ver.ph_major = facts_data->fw_version.phase_major; 2876 mrioc->facts.fw_ver.gen_minor = facts_data->fw_version.gen_minor; 2877 mrioc->facts.fw_ver.gen_major = facts_data->fw_version.gen_major; 2878 mrioc->msix_count = min_t(int, mrioc->msix_count, 2879 mrioc->facts.max_msix_vectors); 2880 mrioc->facts.sge_mod_mask = facts_data->sge_modifier_mask; 2881 mrioc->facts.sge_mod_value = facts_data->sge_modifier_value; 2882 mrioc->facts.sge_mod_shift = facts_data->sge_modifier_shift; 2883 mrioc->facts.shutdown_timeout = 2884 le16_to_cpu(facts_data->shutdown_timeout); 2885 2886 mrioc->facts.max_dev_per_tg = 2887 facts_data->max_devices_per_throttle_group; 2888 mrioc->facts.io_throttle_data_length = 2889 le16_to_cpu(facts_data->io_throttle_data_length); 2890 mrioc->facts.max_io_throttle_group = 2891 le16_to_cpu(facts_data->max_io_throttle_group); 2892 mrioc->facts.io_throttle_low = le16_to_cpu(facts_data->io_throttle_low); 2893 mrioc->facts.io_throttle_high = 2894 le16_to_cpu(facts_data->io_throttle_high); 2895 2896 /* Store in 512b block count */ 2897 if (mrioc->facts.io_throttle_data_length) 2898 mrioc->io_throttle_data_length = 2899 (mrioc->facts.io_throttle_data_length * 2 * 4); 2900 else 2901 /* set the length to 1MB + 1K to disable throttle */ 2902 mrioc->io_throttle_data_length = MPI3MR_MAX_SECTORS + 2; 2903 2904 mrioc->io_throttle_high = (mrioc->facts.io_throttle_high * 2 * 1024); 2905 mrioc->io_throttle_low = (mrioc->facts.io_throttle_low * 2 * 1024); 2906 2907 ioc_info(mrioc, "ioc_num(%d), maxopQ(%d), maxopRepQ(%d), maxdh(%d),", 2908 mrioc->facts.ioc_num, mrioc->facts.max_op_req_q, 2909 mrioc->facts.max_op_reply_q, mrioc->facts.max_devhandle); 2910 ioc_info(mrioc, 2911 "maxreqs(%d), mindh(%d) maxvectors(%d) maxperids(%d)\n", 2912 mrioc->facts.max_reqs, mrioc->facts.min_devhandle, 2913 mrioc->facts.max_msix_vectors, mrioc->facts.max_perids); 2914 ioc_info(mrioc, "SGEModMask 0x%x SGEModVal 0x%x SGEModShift 0x%x ", 2915 mrioc->facts.sge_mod_mask, mrioc->facts.sge_mod_value, 2916 mrioc->facts.sge_mod_shift); 2917 ioc_info(mrioc, "DMA mask %d InitialPE status 0x%x\n", 2918 mrioc->facts.dma_mask, (facts_flags & 2919 MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK)); 2920 ioc_info(mrioc, 2921 "max_dev_per_throttle_group(%d), max_throttle_groups(%d)\n", 2922 mrioc->facts.max_dev_per_tg, mrioc->facts.max_io_throttle_group); 2923 ioc_info(mrioc, 2924 "io_throttle_data_len(%dKiB), io_throttle_high(%dMiB), io_throttle_low(%dMiB)\n", 2925 mrioc->facts.io_throttle_data_length * 4, 2926 mrioc->facts.io_throttle_high, mrioc->facts.io_throttle_low); 2927 } 2928 2929 /** 2930 * mpi3mr_alloc_reply_sense_bufs - Send IOC Init 2931 * @mrioc: Adapter instance reference 2932 * 2933 * Allocate and initialize the reply free buffers, sense 2934 * buffers, reply free queue and sense buffer queue. 2935 * 2936 * Return: 0 on success, non-zero on failures. 2937 */ 2938 static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc) 2939 { 2940 int retval = 0; 2941 u32 sz, i; 2942 2943 if (mrioc->init_cmds.reply) 2944 return retval; 2945 2946 mrioc->init_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 2947 if (!mrioc->init_cmds.reply) 2948 goto out_failed; 2949 2950 mrioc->bsg_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 2951 if (!mrioc->bsg_cmds.reply) 2952 goto out_failed; 2953 2954 mrioc->transport_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 2955 if (!mrioc->transport_cmds.reply) 2956 goto out_failed; 2957 2958 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) { 2959 mrioc->dev_rmhs_cmds[i].reply = kzalloc(mrioc->reply_sz, 2960 GFP_KERNEL); 2961 if (!mrioc->dev_rmhs_cmds[i].reply) 2962 goto out_failed; 2963 } 2964 2965 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) { 2966 mrioc->evtack_cmds[i].reply = kzalloc(mrioc->reply_sz, 2967 GFP_KERNEL); 2968 if (!mrioc->evtack_cmds[i].reply) 2969 goto out_failed; 2970 } 2971 2972 mrioc->host_tm_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 2973 if (!mrioc->host_tm_cmds.reply) 2974 goto out_failed; 2975 2976 mrioc->pel_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 2977 if (!mrioc->pel_cmds.reply) 2978 goto out_failed; 2979 2980 mrioc->pel_abort_cmd.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 2981 if (!mrioc->pel_abort_cmd.reply) 2982 goto out_failed; 2983 2984 mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle; 2985 mrioc->removepend_bitmap = bitmap_zalloc(mrioc->dev_handle_bitmap_bits, 2986 GFP_KERNEL); 2987 if (!mrioc->removepend_bitmap) 2988 goto out_failed; 2989 2990 mrioc->devrem_bitmap = bitmap_zalloc(MPI3MR_NUM_DEVRMCMD, GFP_KERNEL); 2991 if (!mrioc->devrem_bitmap) 2992 goto out_failed; 2993 2994 mrioc->evtack_cmds_bitmap = bitmap_zalloc(MPI3MR_NUM_EVTACKCMD, 2995 GFP_KERNEL); 2996 if (!mrioc->evtack_cmds_bitmap) 2997 goto out_failed; 2998 2999 mrioc->num_reply_bufs = mrioc->facts.max_reqs + MPI3MR_NUM_EVT_REPLIES; 3000 mrioc->reply_free_qsz = mrioc->num_reply_bufs + 1; 3001 mrioc->num_sense_bufs = mrioc->facts.max_reqs / MPI3MR_SENSEBUF_FACTOR; 3002 mrioc->sense_buf_q_sz = mrioc->num_sense_bufs + 1; 3003 3004 /* reply buffer pool, 16 byte align */ 3005 sz = mrioc->num_reply_bufs * mrioc->reply_sz; 3006 mrioc->reply_buf_pool = dma_pool_create("reply_buf pool", 3007 &mrioc->pdev->dev, sz, 16, 0); 3008 if (!mrioc->reply_buf_pool) { 3009 ioc_err(mrioc, "reply buf pool: dma_pool_create failed\n"); 3010 goto out_failed; 3011 } 3012 3013 mrioc->reply_buf = dma_pool_zalloc(mrioc->reply_buf_pool, GFP_KERNEL, 3014 &mrioc->reply_buf_dma); 3015 if (!mrioc->reply_buf) 3016 goto out_failed; 3017 3018 mrioc->reply_buf_dma_max_address = mrioc->reply_buf_dma + sz; 3019 3020 /* reply free queue, 8 byte align */ 3021 sz = mrioc->reply_free_qsz * 8; 3022 mrioc->reply_free_q_pool = dma_pool_create("reply_free_q pool", 3023 &mrioc->pdev->dev, sz, 8, 0); 3024 if (!mrioc->reply_free_q_pool) { 3025 ioc_err(mrioc, "reply_free_q pool: dma_pool_create failed\n"); 3026 goto out_failed; 3027 } 3028 mrioc->reply_free_q = dma_pool_zalloc(mrioc->reply_free_q_pool, 3029 GFP_KERNEL, &mrioc->reply_free_q_dma); 3030 if (!mrioc->reply_free_q) 3031 goto out_failed; 3032 3033 /* sense buffer pool, 4 byte align */ 3034 sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ; 3035 mrioc->sense_buf_pool = dma_pool_create("sense_buf pool", 3036 &mrioc->pdev->dev, sz, 4, 0); 3037 if (!mrioc->sense_buf_pool) { 3038 ioc_err(mrioc, "sense_buf pool: dma_pool_create failed\n"); 3039 goto out_failed; 3040 } 3041 mrioc->sense_buf = dma_pool_zalloc(mrioc->sense_buf_pool, GFP_KERNEL, 3042 &mrioc->sense_buf_dma); 3043 if (!mrioc->sense_buf) 3044 goto out_failed; 3045 3046 /* sense buffer queue, 8 byte align */ 3047 sz = mrioc->sense_buf_q_sz * 8; 3048 mrioc->sense_buf_q_pool = dma_pool_create("sense_buf_q pool", 3049 &mrioc->pdev->dev, sz, 8, 0); 3050 if (!mrioc->sense_buf_q_pool) { 3051 ioc_err(mrioc, "sense_buf_q pool: dma_pool_create failed\n"); 3052 goto out_failed; 3053 } 3054 mrioc->sense_buf_q = dma_pool_zalloc(mrioc->sense_buf_q_pool, 3055 GFP_KERNEL, &mrioc->sense_buf_q_dma); 3056 if (!mrioc->sense_buf_q) 3057 goto out_failed; 3058 3059 return retval; 3060 3061 out_failed: 3062 retval = -1; 3063 return retval; 3064 } 3065 3066 /** 3067 * mpimr_initialize_reply_sbuf_queues - initialize reply sense 3068 * buffers 3069 * @mrioc: Adapter instance reference 3070 * 3071 * Helper function to initialize reply and sense buffers along 3072 * with some debug prints. 3073 * 3074 * Return: None. 3075 */ 3076 static void mpimr_initialize_reply_sbuf_queues(struct mpi3mr_ioc *mrioc) 3077 { 3078 u32 sz, i; 3079 dma_addr_t phy_addr; 3080 3081 sz = mrioc->num_reply_bufs * mrioc->reply_sz; 3082 ioc_info(mrioc, 3083 "reply buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n", 3084 mrioc->reply_buf, mrioc->num_reply_bufs, mrioc->reply_sz, 3085 (sz / 1024), (unsigned long long)mrioc->reply_buf_dma); 3086 sz = mrioc->reply_free_qsz * 8; 3087 ioc_info(mrioc, 3088 "reply_free_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n", 3089 mrioc->reply_free_q, mrioc->reply_free_qsz, 8, (sz / 1024), 3090 (unsigned long long)mrioc->reply_free_q_dma); 3091 sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ; 3092 ioc_info(mrioc, 3093 "sense_buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n", 3094 mrioc->sense_buf, mrioc->num_sense_bufs, MPI3MR_SENSE_BUF_SZ, 3095 (sz / 1024), (unsigned long long)mrioc->sense_buf_dma); 3096 sz = mrioc->sense_buf_q_sz * 8; 3097 ioc_info(mrioc, 3098 "sense_buf_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n", 3099 mrioc->sense_buf_q, mrioc->sense_buf_q_sz, 8, (sz / 1024), 3100 (unsigned long long)mrioc->sense_buf_q_dma); 3101 3102 /* initialize Reply buffer Queue */ 3103 for (i = 0, phy_addr = mrioc->reply_buf_dma; 3104 i < mrioc->num_reply_bufs; i++, phy_addr += mrioc->reply_sz) 3105 mrioc->reply_free_q[i] = cpu_to_le64(phy_addr); 3106 mrioc->reply_free_q[i] = cpu_to_le64(0); 3107 3108 /* initialize Sense Buffer Queue */ 3109 for (i = 0, phy_addr = mrioc->sense_buf_dma; 3110 i < mrioc->num_sense_bufs; i++, phy_addr += MPI3MR_SENSE_BUF_SZ) 3111 mrioc->sense_buf_q[i] = cpu_to_le64(phy_addr); 3112 mrioc->sense_buf_q[i] = cpu_to_le64(0); 3113 } 3114 3115 /** 3116 * mpi3mr_issue_iocinit - Send IOC Init 3117 * @mrioc: Adapter instance reference 3118 * 3119 * Issue IOC Init MPI request through admin queue and wait for 3120 * the completion of it or time out. 3121 * 3122 * Return: 0 on success, non-zero on failures. 3123 */ 3124 static int mpi3mr_issue_iocinit(struct mpi3mr_ioc *mrioc) 3125 { 3126 struct mpi3_ioc_init_request iocinit_req; 3127 struct mpi3_driver_info_layout *drv_info; 3128 dma_addr_t data_dma; 3129 u32 data_len = sizeof(*drv_info); 3130 int retval = 0; 3131 ktime_t current_time; 3132 3133 drv_info = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma, 3134 GFP_KERNEL); 3135 if (!drv_info) { 3136 retval = -1; 3137 goto out; 3138 } 3139 mpimr_initialize_reply_sbuf_queues(mrioc); 3140 3141 drv_info->information_length = cpu_to_le32(data_len); 3142 strscpy(drv_info->driver_signature, "Broadcom", sizeof(drv_info->driver_signature)); 3143 strscpy(drv_info->os_name, utsname()->sysname, sizeof(drv_info->os_name)); 3144 strscpy(drv_info->os_version, utsname()->release, sizeof(drv_info->os_version)); 3145 strscpy(drv_info->driver_name, MPI3MR_DRIVER_NAME, sizeof(drv_info->driver_name)); 3146 strscpy(drv_info->driver_version, MPI3MR_DRIVER_VERSION, sizeof(drv_info->driver_version)); 3147 strscpy(drv_info->driver_release_date, MPI3MR_DRIVER_RELDATE, 3148 sizeof(drv_info->driver_release_date)); 3149 drv_info->driver_capabilities = 0; 3150 memcpy((u8 *)&mrioc->driver_info, (u8 *)drv_info, 3151 sizeof(mrioc->driver_info)); 3152 3153 memset(&iocinit_req, 0, sizeof(iocinit_req)); 3154 mutex_lock(&mrioc->init_cmds.mutex); 3155 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 3156 retval = -1; 3157 ioc_err(mrioc, "Issue IOCInit: Init command is in use\n"); 3158 mutex_unlock(&mrioc->init_cmds.mutex); 3159 goto out; 3160 } 3161 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 3162 mrioc->init_cmds.is_waiting = 1; 3163 mrioc->init_cmds.callback = NULL; 3164 iocinit_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 3165 iocinit_req.function = MPI3_FUNCTION_IOC_INIT; 3166 iocinit_req.mpi_version.mpi3_version.dev = MPI3_VERSION_DEV; 3167 iocinit_req.mpi_version.mpi3_version.unit = MPI3_VERSION_UNIT; 3168 iocinit_req.mpi_version.mpi3_version.major = MPI3_VERSION_MAJOR; 3169 iocinit_req.mpi_version.mpi3_version.minor = MPI3_VERSION_MINOR; 3170 iocinit_req.who_init = MPI3_WHOINIT_HOST_DRIVER; 3171 iocinit_req.reply_free_queue_depth = cpu_to_le16(mrioc->reply_free_qsz); 3172 iocinit_req.reply_free_queue_address = 3173 cpu_to_le64(mrioc->reply_free_q_dma); 3174 iocinit_req.sense_buffer_length = cpu_to_le16(MPI3MR_SENSE_BUF_SZ); 3175 iocinit_req.sense_buffer_free_queue_depth = 3176 cpu_to_le16(mrioc->sense_buf_q_sz); 3177 iocinit_req.sense_buffer_free_queue_address = 3178 cpu_to_le64(mrioc->sense_buf_q_dma); 3179 iocinit_req.driver_information_address = cpu_to_le64(data_dma); 3180 3181 current_time = ktime_get_real(); 3182 iocinit_req.time_stamp = cpu_to_le64(ktime_to_ms(current_time)); 3183 3184 init_completion(&mrioc->init_cmds.done); 3185 retval = mpi3mr_admin_request_post(mrioc, &iocinit_req, 3186 sizeof(iocinit_req), 1); 3187 if (retval) { 3188 ioc_err(mrioc, "Issue IOCInit: Admin Post failed\n"); 3189 goto out_unlock; 3190 } 3191 wait_for_completion_timeout(&mrioc->init_cmds.done, 3192 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 3193 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 3194 mpi3mr_check_rh_fault_ioc(mrioc, 3195 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT); 3196 ioc_err(mrioc, "ioc_init timed out\n"); 3197 retval = -1; 3198 goto out_unlock; 3199 } 3200 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 3201 != MPI3_IOCSTATUS_SUCCESS) { 3202 ioc_err(mrioc, 3203 "Issue IOCInit: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 3204 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 3205 mrioc->init_cmds.ioc_loginfo); 3206 retval = -1; 3207 goto out_unlock; 3208 } 3209 3210 mrioc->reply_free_queue_host_index = mrioc->num_reply_bufs; 3211 writel(mrioc->reply_free_queue_host_index, 3212 &mrioc->sysif_regs->reply_free_host_index); 3213 3214 mrioc->sbq_host_index = mrioc->num_sense_bufs; 3215 writel(mrioc->sbq_host_index, 3216 &mrioc->sysif_regs->sense_buffer_free_host_index); 3217 out_unlock: 3218 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 3219 mutex_unlock(&mrioc->init_cmds.mutex); 3220 3221 out: 3222 if (drv_info) 3223 dma_free_coherent(&mrioc->pdev->dev, data_len, drv_info, 3224 data_dma); 3225 3226 return retval; 3227 } 3228 3229 /** 3230 * mpi3mr_unmask_events - Unmask events in event mask bitmap 3231 * @mrioc: Adapter instance reference 3232 * @event: MPI event ID 3233 * 3234 * Un mask the specific event by resetting the event_mask 3235 * bitmap. 3236 * 3237 * Return: 0 on success, non-zero on failures. 3238 */ 3239 static void mpi3mr_unmask_events(struct mpi3mr_ioc *mrioc, u16 event) 3240 { 3241 u32 desired_event; 3242 u8 word; 3243 3244 if (event >= 128) 3245 return; 3246 3247 desired_event = (1 << (event % 32)); 3248 word = event / 32; 3249 3250 mrioc->event_masks[word] &= ~desired_event; 3251 } 3252 3253 /** 3254 * mpi3mr_issue_event_notification - Send event notification 3255 * @mrioc: Adapter instance reference 3256 * 3257 * Issue event notification MPI request through admin queue and 3258 * wait for the completion of it or time out. 3259 * 3260 * Return: 0 on success, non-zero on failures. 3261 */ 3262 static int mpi3mr_issue_event_notification(struct mpi3mr_ioc *mrioc) 3263 { 3264 struct mpi3_event_notification_request evtnotify_req; 3265 int retval = 0; 3266 u8 i; 3267 3268 memset(&evtnotify_req, 0, sizeof(evtnotify_req)); 3269 mutex_lock(&mrioc->init_cmds.mutex); 3270 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 3271 retval = -1; 3272 ioc_err(mrioc, "Issue EvtNotify: Init command is in use\n"); 3273 mutex_unlock(&mrioc->init_cmds.mutex); 3274 goto out; 3275 } 3276 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 3277 mrioc->init_cmds.is_waiting = 1; 3278 mrioc->init_cmds.callback = NULL; 3279 evtnotify_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 3280 evtnotify_req.function = MPI3_FUNCTION_EVENT_NOTIFICATION; 3281 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 3282 evtnotify_req.event_masks[i] = 3283 cpu_to_le32(mrioc->event_masks[i]); 3284 init_completion(&mrioc->init_cmds.done); 3285 retval = mpi3mr_admin_request_post(mrioc, &evtnotify_req, 3286 sizeof(evtnotify_req), 1); 3287 if (retval) { 3288 ioc_err(mrioc, "Issue EvtNotify: Admin Post failed\n"); 3289 goto out_unlock; 3290 } 3291 wait_for_completion_timeout(&mrioc->init_cmds.done, 3292 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 3293 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 3294 ioc_err(mrioc, "event notification timed out\n"); 3295 mpi3mr_check_rh_fault_ioc(mrioc, 3296 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT); 3297 retval = -1; 3298 goto out_unlock; 3299 } 3300 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 3301 != MPI3_IOCSTATUS_SUCCESS) { 3302 ioc_err(mrioc, 3303 "Issue EvtNotify: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 3304 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 3305 mrioc->init_cmds.ioc_loginfo); 3306 retval = -1; 3307 goto out_unlock; 3308 } 3309 3310 out_unlock: 3311 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 3312 mutex_unlock(&mrioc->init_cmds.mutex); 3313 out: 3314 return retval; 3315 } 3316 3317 /** 3318 * mpi3mr_process_event_ack - Process event acknowledgment 3319 * @mrioc: Adapter instance reference 3320 * @event: MPI3 event ID 3321 * @event_ctx: event context 3322 * 3323 * Send event acknowledgment through admin queue and wait for 3324 * it to complete. 3325 * 3326 * Return: 0 on success, non-zero on failures. 3327 */ 3328 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event, 3329 u32 event_ctx) 3330 { 3331 struct mpi3_event_ack_request evtack_req; 3332 int retval = 0; 3333 3334 memset(&evtack_req, 0, sizeof(evtack_req)); 3335 mutex_lock(&mrioc->init_cmds.mutex); 3336 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 3337 retval = -1; 3338 ioc_err(mrioc, "Send EvtAck: Init command is in use\n"); 3339 mutex_unlock(&mrioc->init_cmds.mutex); 3340 goto out; 3341 } 3342 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 3343 mrioc->init_cmds.is_waiting = 1; 3344 mrioc->init_cmds.callback = NULL; 3345 evtack_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 3346 evtack_req.function = MPI3_FUNCTION_EVENT_ACK; 3347 evtack_req.event = event; 3348 evtack_req.event_context = cpu_to_le32(event_ctx); 3349 3350 init_completion(&mrioc->init_cmds.done); 3351 retval = mpi3mr_admin_request_post(mrioc, &evtack_req, 3352 sizeof(evtack_req), 1); 3353 if (retval) { 3354 ioc_err(mrioc, "Send EvtAck: Admin Post failed\n"); 3355 goto out_unlock; 3356 } 3357 wait_for_completion_timeout(&mrioc->init_cmds.done, 3358 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 3359 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 3360 ioc_err(mrioc, "Issue EvtNotify: command timed out\n"); 3361 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET)) 3362 mpi3mr_soft_reset_handler(mrioc, 3363 MPI3MR_RESET_FROM_EVTACK_TIMEOUT, 1); 3364 retval = -1; 3365 goto out_unlock; 3366 } 3367 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 3368 != MPI3_IOCSTATUS_SUCCESS) { 3369 ioc_err(mrioc, 3370 "Send EvtAck: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 3371 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 3372 mrioc->init_cmds.ioc_loginfo); 3373 retval = -1; 3374 goto out_unlock; 3375 } 3376 3377 out_unlock: 3378 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 3379 mutex_unlock(&mrioc->init_cmds.mutex); 3380 out: 3381 return retval; 3382 } 3383 3384 /** 3385 * mpi3mr_alloc_chain_bufs - Allocate chain buffers 3386 * @mrioc: Adapter instance reference 3387 * 3388 * Allocate chain buffers and set a bitmap to indicate free 3389 * chain buffers. Chain buffers are used to pass the SGE 3390 * information along with MPI3 SCSI IO requests for host I/O. 3391 * 3392 * Return: 0 on success, non-zero on failure 3393 */ 3394 static int mpi3mr_alloc_chain_bufs(struct mpi3mr_ioc *mrioc) 3395 { 3396 int retval = 0; 3397 u32 sz, i; 3398 u16 num_chains; 3399 3400 if (mrioc->chain_sgl_list) 3401 return retval; 3402 3403 num_chains = mrioc->max_host_ios / MPI3MR_CHAINBUF_FACTOR; 3404 3405 if (prot_mask & (SHOST_DIX_TYPE0_PROTECTION 3406 | SHOST_DIX_TYPE1_PROTECTION 3407 | SHOST_DIX_TYPE2_PROTECTION 3408 | SHOST_DIX_TYPE3_PROTECTION)) 3409 num_chains += (num_chains / MPI3MR_CHAINBUFDIX_FACTOR); 3410 3411 mrioc->chain_buf_count = num_chains; 3412 sz = sizeof(struct chain_element) * num_chains; 3413 mrioc->chain_sgl_list = kzalloc(sz, GFP_KERNEL); 3414 if (!mrioc->chain_sgl_list) 3415 goto out_failed; 3416 3417 sz = MPI3MR_PAGE_SIZE_4K; 3418 mrioc->chain_buf_pool = dma_pool_create("chain_buf pool", 3419 &mrioc->pdev->dev, sz, 16, 0); 3420 if (!mrioc->chain_buf_pool) { 3421 ioc_err(mrioc, "chain buf pool: dma_pool_create failed\n"); 3422 goto out_failed; 3423 } 3424 3425 for (i = 0; i < num_chains; i++) { 3426 mrioc->chain_sgl_list[i].addr = 3427 dma_pool_zalloc(mrioc->chain_buf_pool, GFP_KERNEL, 3428 &mrioc->chain_sgl_list[i].dma_addr); 3429 3430 if (!mrioc->chain_sgl_list[i].addr) 3431 goto out_failed; 3432 } 3433 mrioc->chain_bitmap = bitmap_zalloc(num_chains, GFP_KERNEL); 3434 if (!mrioc->chain_bitmap) 3435 goto out_failed; 3436 return retval; 3437 out_failed: 3438 retval = -1; 3439 return retval; 3440 } 3441 3442 /** 3443 * mpi3mr_port_enable_complete - Mark port enable complete 3444 * @mrioc: Adapter instance reference 3445 * @drv_cmd: Internal command tracker 3446 * 3447 * Call back for asynchronous port enable request sets the 3448 * driver command to indicate port enable request is complete. 3449 * 3450 * Return: Nothing 3451 */ 3452 static void mpi3mr_port_enable_complete(struct mpi3mr_ioc *mrioc, 3453 struct mpi3mr_drv_cmd *drv_cmd) 3454 { 3455 drv_cmd->callback = NULL; 3456 mrioc->scan_started = 0; 3457 if (drv_cmd->state & MPI3MR_CMD_RESET) 3458 mrioc->scan_failed = MPI3_IOCSTATUS_INTERNAL_ERROR; 3459 else 3460 mrioc->scan_failed = drv_cmd->ioc_status; 3461 drv_cmd->state = MPI3MR_CMD_NOTUSED; 3462 } 3463 3464 /** 3465 * mpi3mr_issue_port_enable - Issue Port Enable 3466 * @mrioc: Adapter instance reference 3467 * @async: Flag to wait for completion or not 3468 * 3469 * Issue Port Enable MPI request through admin queue and if the 3470 * async flag is not set wait for the completion of the port 3471 * enable or time out. 3472 * 3473 * Return: 0 on success, non-zero on failures. 3474 */ 3475 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async) 3476 { 3477 struct mpi3_port_enable_request pe_req; 3478 int retval = 0; 3479 u32 pe_timeout = MPI3MR_PORTENABLE_TIMEOUT; 3480 3481 memset(&pe_req, 0, sizeof(pe_req)); 3482 mutex_lock(&mrioc->init_cmds.mutex); 3483 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 3484 retval = -1; 3485 ioc_err(mrioc, "Issue PortEnable: Init command is in use\n"); 3486 mutex_unlock(&mrioc->init_cmds.mutex); 3487 goto out; 3488 } 3489 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 3490 if (async) { 3491 mrioc->init_cmds.is_waiting = 0; 3492 mrioc->init_cmds.callback = mpi3mr_port_enable_complete; 3493 } else { 3494 mrioc->init_cmds.is_waiting = 1; 3495 mrioc->init_cmds.callback = NULL; 3496 init_completion(&mrioc->init_cmds.done); 3497 } 3498 pe_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 3499 pe_req.function = MPI3_FUNCTION_PORT_ENABLE; 3500 3501 retval = mpi3mr_admin_request_post(mrioc, &pe_req, sizeof(pe_req), 1); 3502 if (retval) { 3503 ioc_err(mrioc, "Issue PortEnable: Admin Post failed\n"); 3504 goto out_unlock; 3505 } 3506 if (async) { 3507 mutex_unlock(&mrioc->init_cmds.mutex); 3508 goto out; 3509 } 3510 3511 wait_for_completion_timeout(&mrioc->init_cmds.done, (pe_timeout * HZ)); 3512 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 3513 ioc_err(mrioc, "port enable timed out\n"); 3514 retval = -1; 3515 mpi3mr_check_rh_fault_ioc(mrioc, MPI3MR_RESET_FROM_PE_TIMEOUT); 3516 goto out_unlock; 3517 } 3518 mpi3mr_port_enable_complete(mrioc, &mrioc->init_cmds); 3519 3520 out_unlock: 3521 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 3522 mutex_unlock(&mrioc->init_cmds.mutex); 3523 out: 3524 return retval; 3525 } 3526 3527 /* Protocol type to name mapper structure */ 3528 static const struct { 3529 u8 protocol; 3530 char *name; 3531 } mpi3mr_protocols[] = { 3532 { MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR, "Initiator" }, 3533 { MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET, "Target" }, 3534 { MPI3_IOCFACTS_PROTOCOL_NVME, "NVMe attachment" }, 3535 }; 3536 3537 /* Capability to name mapper structure*/ 3538 static const struct { 3539 u32 capability; 3540 char *name; 3541 } mpi3mr_capabilities[] = { 3542 { MPI3_IOCFACTS_CAPABILITY_RAID_CAPABLE, "RAID" }, 3543 { MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED, "MultiPath" }, 3544 }; 3545 3546 /** 3547 * mpi3mr_print_ioc_info - Display controller information 3548 * @mrioc: Adapter instance reference 3549 * 3550 * Display controller personalit, capability, supported 3551 * protocols etc. 3552 * 3553 * Return: Nothing 3554 */ 3555 static void 3556 mpi3mr_print_ioc_info(struct mpi3mr_ioc *mrioc) 3557 { 3558 int i = 0, bytes_written = 0; 3559 char personality[16]; 3560 char protocol[50] = {0}; 3561 char capabilities[100] = {0}; 3562 struct mpi3mr_compimg_ver *fwver = &mrioc->facts.fw_ver; 3563 3564 switch (mrioc->facts.personality) { 3565 case MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA: 3566 strncpy(personality, "Enhanced HBA", sizeof(personality)); 3567 break; 3568 case MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR: 3569 strncpy(personality, "RAID", sizeof(personality)); 3570 break; 3571 default: 3572 strncpy(personality, "Unknown", sizeof(personality)); 3573 break; 3574 } 3575 3576 ioc_info(mrioc, "Running in %s Personality", personality); 3577 3578 ioc_info(mrioc, "FW version(%d.%d.%d.%d.%d.%d)\n", 3579 fwver->gen_major, fwver->gen_minor, fwver->ph_major, 3580 fwver->ph_minor, fwver->cust_id, fwver->build_num); 3581 3582 for (i = 0; i < ARRAY_SIZE(mpi3mr_protocols); i++) { 3583 if (mrioc->facts.protocol_flags & 3584 mpi3mr_protocols[i].protocol) { 3585 bytes_written += scnprintf(protocol + bytes_written, 3586 sizeof(protocol) - bytes_written, "%s%s", 3587 bytes_written ? "," : "", 3588 mpi3mr_protocols[i].name); 3589 } 3590 } 3591 3592 bytes_written = 0; 3593 for (i = 0; i < ARRAY_SIZE(mpi3mr_capabilities); i++) { 3594 if (mrioc->facts.protocol_flags & 3595 mpi3mr_capabilities[i].capability) { 3596 bytes_written += scnprintf(capabilities + bytes_written, 3597 sizeof(capabilities) - bytes_written, "%s%s", 3598 bytes_written ? "," : "", 3599 mpi3mr_capabilities[i].name); 3600 } 3601 } 3602 3603 ioc_info(mrioc, "Protocol=(%s), Capabilities=(%s)\n", 3604 protocol, capabilities); 3605 } 3606 3607 /** 3608 * mpi3mr_cleanup_resources - Free PCI resources 3609 * @mrioc: Adapter instance reference 3610 * 3611 * Unmap PCI device memory and disable PCI device. 3612 * 3613 * Return: 0 on success and non-zero on failure. 3614 */ 3615 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc) 3616 { 3617 struct pci_dev *pdev = mrioc->pdev; 3618 3619 mpi3mr_cleanup_isr(mrioc); 3620 3621 if (mrioc->sysif_regs) { 3622 iounmap((void __iomem *)mrioc->sysif_regs); 3623 mrioc->sysif_regs = NULL; 3624 } 3625 3626 if (pci_is_enabled(pdev)) { 3627 if (mrioc->bars) 3628 pci_release_selected_regions(pdev, mrioc->bars); 3629 pci_disable_device(pdev); 3630 } 3631 } 3632 3633 /** 3634 * mpi3mr_setup_resources - Enable PCI resources 3635 * @mrioc: Adapter instance reference 3636 * 3637 * Enable PCI device memory, MSI-x registers and set DMA mask. 3638 * 3639 * Return: 0 on success and non-zero on failure. 3640 */ 3641 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc) 3642 { 3643 struct pci_dev *pdev = mrioc->pdev; 3644 u32 memap_sz = 0; 3645 int i, retval = 0, capb = 0; 3646 u16 message_control; 3647 u64 dma_mask = mrioc->dma_mask ? mrioc->dma_mask : 3648 ((sizeof(dma_addr_t) > 4) ? DMA_BIT_MASK(64) : DMA_BIT_MASK(32)); 3649 3650 if (pci_enable_device_mem(pdev)) { 3651 ioc_err(mrioc, "pci_enable_device_mem: failed\n"); 3652 retval = -ENODEV; 3653 goto out_failed; 3654 } 3655 3656 capb = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 3657 if (!capb) { 3658 ioc_err(mrioc, "Unable to find MSI-X Capabilities\n"); 3659 retval = -ENODEV; 3660 goto out_failed; 3661 } 3662 mrioc->bars = pci_select_bars(pdev, IORESOURCE_MEM); 3663 3664 if (pci_request_selected_regions(pdev, mrioc->bars, 3665 mrioc->driver_name)) { 3666 ioc_err(mrioc, "pci_request_selected_regions: failed\n"); 3667 retval = -ENODEV; 3668 goto out_failed; 3669 } 3670 3671 for (i = 0; (i < DEVICE_COUNT_RESOURCE); i++) { 3672 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) { 3673 mrioc->sysif_regs_phys = pci_resource_start(pdev, i); 3674 memap_sz = pci_resource_len(pdev, i); 3675 mrioc->sysif_regs = 3676 ioremap(mrioc->sysif_regs_phys, memap_sz); 3677 break; 3678 } 3679 } 3680 3681 pci_set_master(pdev); 3682 3683 retval = dma_set_mask_and_coherent(&pdev->dev, dma_mask); 3684 if (retval) { 3685 if (dma_mask != DMA_BIT_MASK(32)) { 3686 ioc_warn(mrioc, "Setting 64 bit DMA mask failed\n"); 3687 dma_mask = DMA_BIT_MASK(32); 3688 retval = dma_set_mask_and_coherent(&pdev->dev, 3689 dma_mask); 3690 } 3691 if (retval) { 3692 mrioc->dma_mask = 0; 3693 ioc_err(mrioc, "Setting 32 bit DMA mask also failed\n"); 3694 goto out_failed; 3695 } 3696 } 3697 mrioc->dma_mask = dma_mask; 3698 3699 if (!mrioc->sysif_regs) { 3700 ioc_err(mrioc, 3701 "Unable to map adapter memory or resource not found\n"); 3702 retval = -EINVAL; 3703 goto out_failed; 3704 } 3705 3706 pci_read_config_word(pdev, capb + 2, &message_control); 3707 mrioc->msix_count = (message_control & 0x3FF) + 1; 3708 3709 pci_save_state(pdev); 3710 3711 pci_set_drvdata(pdev, mrioc->shost); 3712 3713 mpi3mr_ioc_disable_intr(mrioc); 3714 3715 ioc_info(mrioc, "iomem(0x%016llx), mapped(0x%p), size(%d)\n", 3716 (unsigned long long)mrioc->sysif_regs_phys, 3717 mrioc->sysif_regs, memap_sz); 3718 ioc_info(mrioc, "Number of MSI-X vectors found in capabilities: (%d)\n", 3719 mrioc->msix_count); 3720 3721 if (!reset_devices && poll_queues > 0) 3722 mrioc->requested_poll_qcount = min_t(int, poll_queues, 3723 mrioc->msix_count - 2); 3724 return retval; 3725 3726 out_failed: 3727 mpi3mr_cleanup_resources(mrioc); 3728 return retval; 3729 } 3730 3731 /** 3732 * mpi3mr_enable_events - Enable required events 3733 * @mrioc: Adapter instance reference 3734 * 3735 * This routine unmasks the events required by the driver by 3736 * sennding appropriate event mask bitmapt through an event 3737 * notification request. 3738 * 3739 * Return: 0 on success and non-zero on failure. 3740 */ 3741 static int mpi3mr_enable_events(struct mpi3mr_ioc *mrioc) 3742 { 3743 int retval = 0; 3744 u32 i; 3745 3746 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 3747 mrioc->event_masks[i] = -1; 3748 3749 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_ADDED); 3750 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_INFO_CHANGED); 3751 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_STATUS_CHANGE); 3752 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE); 3753 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_ADDED); 3754 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST); 3755 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DISCOVERY); 3756 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR); 3757 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_BROADCAST_PRIMITIVE); 3758 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST); 3759 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_ENUMERATION); 3760 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PREPARE_FOR_RESET); 3761 mpi3mr_unmask_events(mrioc, MPI3_EVENT_CABLE_MGMT); 3762 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENERGY_PACK_CHANGE); 3763 3764 retval = mpi3mr_issue_event_notification(mrioc); 3765 if (retval) 3766 ioc_err(mrioc, "failed to issue event notification %d\n", 3767 retval); 3768 return retval; 3769 } 3770 3771 /** 3772 * mpi3mr_init_ioc - Initialize the controller 3773 * @mrioc: Adapter instance reference 3774 * 3775 * This the controller initialization routine, executed either 3776 * after soft reset or from pci probe callback. 3777 * Setup the required resources, memory map the controller 3778 * registers, create admin and operational reply queue pairs, 3779 * allocate required memory for reply pool, sense buffer pool, 3780 * issue IOC init request to the firmware, unmask the events and 3781 * issue port enable to discover SAS/SATA/NVMe devies and RAID 3782 * volumes. 3783 * 3784 * Return: 0 on success and non-zero on failure. 3785 */ 3786 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc) 3787 { 3788 int retval = 0; 3789 u8 retry = 0; 3790 struct mpi3_ioc_facts_data facts_data; 3791 u32 sz; 3792 3793 retry_init: 3794 retval = mpi3mr_bring_ioc_ready(mrioc); 3795 if (retval) { 3796 ioc_err(mrioc, "Failed to bring ioc ready: error %d\n", 3797 retval); 3798 goto out_failed_noretry; 3799 } 3800 3801 retval = mpi3mr_setup_isr(mrioc, 1); 3802 if (retval) { 3803 ioc_err(mrioc, "Failed to setup ISR error %d\n", 3804 retval); 3805 goto out_failed_noretry; 3806 } 3807 3808 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data); 3809 if (retval) { 3810 ioc_err(mrioc, "Failed to Issue IOC Facts %d\n", 3811 retval); 3812 goto out_failed; 3813 } 3814 3815 mrioc->max_host_ios = mrioc->facts.max_reqs - MPI3MR_INTERNAL_CMDS_RESVD; 3816 3817 mrioc->num_io_throttle_group = mrioc->facts.max_io_throttle_group; 3818 atomic_set(&mrioc->pend_large_data_sz, 0); 3819 3820 if (reset_devices) 3821 mrioc->max_host_ios = min_t(int, mrioc->max_host_ios, 3822 MPI3MR_HOST_IOS_KDUMP); 3823 3824 if (!(mrioc->facts.ioc_capabilities & 3825 MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED)) { 3826 mrioc->sas_transport_enabled = 1; 3827 mrioc->scsi_device_channel = 1; 3828 mrioc->shost->max_channel = 1; 3829 mrioc->shost->transportt = mpi3mr_transport_template; 3830 } 3831 3832 mrioc->reply_sz = mrioc->facts.reply_sz; 3833 3834 retval = mpi3mr_check_reset_dma_mask(mrioc); 3835 if (retval) { 3836 ioc_err(mrioc, "Resetting dma mask failed %d\n", 3837 retval); 3838 goto out_failed_noretry; 3839 } 3840 3841 mpi3mr_print_ioc_info(mrioc); 3842 3843 if (!mrioc->cfg_page) { 3844 dprint_init(mrioc, "allocating config page buffers\n"); 3845 mrioc->cfg_page_sz = MPI3MR_DEFAULT_CFG_PAGE_SZ; 3846 mrioc->cfg_page = dma_alloc_coherent(&mrioc->pdev->dev, 3847 mrioc->cfg_page_sz, &mrioc->cfg_page_dma, GFP_KERNEL); 3848 if (!mrioc->cfg_page) { 3849 retval = -1; 3850 goto out_failed_noretry; 3851 } 3852 } 3853 3854 if (!mrioc->init_cmds.reply) { 3855 retval = mpi3mr_alloc_reply_sense_bufs(mrioc); 3856 if (retval) { 3857 ioc_err(mrioc, 3858 "%s :Failed to allocated reply sense buffers %d\n", 3859 __func__, retval); 3860 goto out_failed_noretry; 3861 } 3862 } 3863 3864 if (!mrioc->chain_sgl_list) { 3865 retval = mpi3mr_alloc_chain_bufs(mrioc); 3866 if (retval) { 3867 ioc_err(mrioc, "Failed to allocated chain buffers %d\n", 3868 retval); 3869 goto out_failed_noretry; 3870 } 3871 } 3872 3873 retval = mpi3mr_issue_iocinit(mrioc); 3874 if (retval) { 3875 ioc_err(mrioc, "Failed to Issue IOC Init %d\n", 3876 retval); 3877 goto out_failed; 3878 } 3879 3880 retval = mpi3mr_print_pkg_ver(mrioc); 3881 if (retval) { 3882 ioc_err(mrioc, "failed to get package version\n"); 3883 goto out_failed; 3884 } 3885 3886 retval = mpi3mr_setup_isr(mrioc, 0); 3887 if (retval) { 3888 ioc_err(mrioc, "Failed to re-setup ISR, error %d\n", 3889 retval); 3890 goto out_failed_noretry; 3891 } 3892 3893 retval = mpi3mr_create_op_queues(mrioc); 3894 if (retval) { 3895 ioc_err(mrioc, "Failed to create OpQueues error %d\n", 3896 retval); 3897 goto out_failed; 3898 } 3899 3900 if (!mrioc->pel_seqnum_virt) { 3901 dprint_init(mrioc, "allocating memory for pel_seqnum_virt\n"); 3902 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq); 3903 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev, 3904 mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma, 3905 GFP_KERNEL); 3906 if (!mrioc->pel_seqnum_virt) { 3907 retval = -ENOMEM; 3908 goto out_failed_noretry; 3909 } 3910 } 3911 3912 if (!mrioc->throttle_groups && mrioc->num_io_throttle_group) { 3913 dprint_init(mrioc, "allocating memory for throttle groups\n"); 3914 sz = sizeof(struct mpi3mr_throttle_group_info); 3915 mrioc->throttle_groups = kcalloc(mrioc->num_io_throttle_group, sz, GFP_KERNEL); 3916 if (!mrioc->throttle_groups) { 3917 retval = -1; 3918 goto out_failed_noretry; 3919 } 3920 } 3921 3922 retval = mpi3mr_enable_events(mrioc); 3923 if (retval) { 3924 ioc_err(mrioc, "failed to enable events %d\n", 3925 retval); 3926 goto out_failed; 3927 } 3928 3929 ioc_info(mrioc, "controller initialization completed successfully\n"); 3930 return retval; 3931 out_failed: 3932 if (retry < 2) { 3933 retry++; 3934 ioc_warn(mrioc, "retrying controller initialization, retry_count:%d\n", 3935 retry); 3936 mpi3mr_memset_buffers(mrioc); 3937 goto retry_init; 3938 } 3939 retval = -1; 3940 out_failed_noretry: 3941 ioc_err(mrioc, "controller initialization failed\n"); 3942 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, 3943 MPI3MR_RESET_FROM_CTLR_CLEANUP); 3944 mrioc->unrecoverable = 1; 3945 return retval; 3946 } 3947 3948 /** 3949 * mpi3mr_reinit_ioc - Re-Initialize the controller 3950 * @mrioc: Adapter instance reference 3951 * @is_resume: Called from resume or reset path 3952 * 3953 * This the controller re-initialization routine, executed from 3954 * the soft reset handler or resume callback. Creates 3955 * operational reply queue pairs, allocate required memory for 3956 * reply pool, sense buffer pool, issue IOC init request to the 3957 * firmware, unmask the events and issue port enable to discover 3958 * SAS/SATA/NVMe devices and RAID volumes. 3959 * 3960 * Return: 0 on success and non-zero on failure. 3961 */ 3962 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume) 3963 { 3964 int retval = 0; 3965 u8 retry = 0; 3966 struct mpi3_ioc_facts_data facts_data; 3967 u32 pe_timeout, ioc_status; 3968 3969 retry_init: 3970 pe_timeout = 3971 (MPI3MR_PORTENABLE_TIMEOUT / MPI3MR_PORTENABLE_POLL_INTERVAL); 3972 3973 dprint_reset(mrioc, "bringing up the controller to ready state\n"); 3974 retval = mpi3mr_bring_ioc_ready(mrioc); 3975 if (retval) { 3976 ioc_err(mrioc, "failed to bring to ready state\n"); 3977 goto out_failed_noretry; 3978 } 3979 3980 if (is_resume) { 3981 dprint_reset(mrioc, "setting up single ISR\n"); 3982 retval = mpi3mr_setup_isr(mrioc, 1); 3983 if (retval) { 3984 ioc_err(mrioc, "failed to setup ISR\n"); 3985 goto out_failed_noretry; 3986 } 3987 } else 3988 mpi3mr_ioc_enable_intr(mrioc); 3989 3990 dprint_reset(mrioc, "getting ioc_facts\n"); 3991 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data); 3992 if (retval) { 3993 ioc_err(mrioc, "failed to get ioc_facts\n"); 3994 goto out_failed; 3995 } 3996 3997 dprint_reset(mrioc, "validating ioc_facts\n"); 3998 retval = mpi3mr_revalidate_factsdata(mrioc); 3999 if (retval) { 4000 ioc_err(mrioc, "failed to revalidate ioc_facts data\n"); 4001 goto out_failed_noretry; 4002 } 4003 4004 mpi3mr_print_ioc_info(mrioc); 4005 4006 dprint_reset(mrioc, "sending ioc_init\n"); 4007 retval = mpi3mr_issue_iocinit(mrioc); 4008 if (retval) { 4009 ioc_err(mrioc, "failed to send ioc_init\n"); 4010 goto out_failed; 4011 } 4012 4013 dprint_reset(mrioc, "getting package version\n"); 4014 retval = mpi3mr_print_pkg_ver(mrioc); 4015 if (retval) { 4016 ioc_err(mrioc, "failed to get package version\n"); 4017 goto out_failed; 4018 } 4019 4020 if (is_resume) { 4021 dprint_reset(mrioc, "setting up multiple ISR\n"); 4022 retval = mpi3mr_setup_isr(mrioc, 0); 4023 if (retval) { 4024 ioc_err(mrioc, "failed to re-setup ISR\n"); 4025 goto out_failed_noretry; 4026 } 4027 } 4028 4029 dprint_reset(mrioc, "creating operational queue pairs\n"); 4030 retval = mpi3mr_create_op_queues(mrioc); 4031 if (retval) { 4032 ioc_err(mrioc, "failed to create operational queue pairs\n"); 4033 goto out_failed; 4034 } 4035 4036 if (!mrioc->pel_seqnum_virt) { 4037 dprint_reset(mrioc, "allocating memory for pel_seqnum_virt\n"); 4038 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq); 4039 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev, 4040 mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma, 4041 GFP_KERNEL); 4042 if (!mrioc->pel_seqnum_virt) { 4043 retval = -ENOMEM; 4044 goto out_failed_noretry; 4045 } 4046 } 4047 4048 if (mrioc->shost->nr_hw_queues > mrioc->num_op_reply_q) { 4049 ioc_err(mrioc, 4050 "cannot create minimum number of operational queues expected:%d created:%d\n", 4051 mrioc->shost->nr_hw_queues, mrioc->num_op_reply_q); 4052 retval = -1; 4053 goto out_failed_noretry; 4054 } 4055 4056 dprint_reset(mrioc, "enabling events\n"); 4057 retval = mpi3mr_enable_events(mrioc); 4058 if (retval) { 4059 ioc_err(mrioc, "failed to enable events\n"); 4060 goto out_failed; 4061 } 4062 4063 mrioc->device_refresh_on = 1; 4064 mpi3mr_add_event_wait_for_device_refresh(mrioc); 4065 4066 ioc_info(mrioc, "sending port enable\n"); 4067 retval = mpi3mr_issue_port_enable(mrioc, 1); 4068 if (retval) { 4069 ioc_err(mrioc, "failed to issue port enable\n"); 4070 goto out_failed; 4071 } 4072 do { 4073 ssleep(MPI3MR_PORTENABLE_POLL_INTERVAL); 4074 if (mrioc->init_cmds.state == MPI3MR_CMD_NOTUSED) 4075 break; 4076 if (!pci_device_is_present(mrioc->pdev)) 4077 mrioc->unrecoverable = 1; 4078 if (mrioc->unrecoverable) { 4079 retval = -1; 4080 goto out_failed_noretry; 4081 } 4082 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 4083 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) || 4084 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) { 4085 mpi3mr_print_fault_info(mrioc); 4086 mrioc->init_cmds.is_waiting = 0; 4087 mrioc->init_cmds.callback = NULL; 4088 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 4089 goto out_failed; 4090 } 4091 } while (--pe_timeout); 4092 4093 if (!pe_timeout) { 4094 ioc_err(mrioc, "port enable timed out\n"); 4095 mpi3mr_check_rh_fault_ioc(mrioc, 4096 MPI3MR_RESET_FROM_PE_TIMEOUT); 4097 mrioc->init_cmds.is_waiting = 0; 4098 mrioc->init_cmds.callback = NULL; 4099 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 4100 goto out_failed; 4101 } else if (mrioc->scan_failed) { 4102 ioc_err(mrioc, 4103 "port enable failed with status=0x%04x\n", 4104 mrioc->scan_failed); 4105 } else 4106 ioc_info(mrioc, "port enable completed successfully\n"); 4107 4108 ioc_info(mrioc, "controller %s completed successfully\n", 4109 (is_resume)?"resume":"re-initialization"); 4110 return retval; 4111 out_failed: 4112 if (retry < 2) { 4113 retry++; 4114 ioc_warn(mrioc, "retrying controller %s, retry_count:%d\n", 4115 (is_resume)?"resume":"re-initialization", retry); 4116 mpi3mr_memset_buffers(mrioc); 4117 goto retry_init; 4118 } 4119 retval = -1; 4120 out_failed_noretry: 4121 ioc_err(mrioc, "controller %s is failed\n", 4122 (is_resume)?"resume":"re-initialization"); 4123 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, 4124 MPI3MR_RESET_FROM_CTLR_CLEANUP); 4125 mrioc->unrecoverable = 1; 4126 return retval; 4127 } 4128 4129 /** 4130 * mpi3mr_memset_op_reply_q_buffers - memset the operational reply queue's 4131 * segments 4132 * @mrioc: Adapter instance reference 4133 * @qidx: Operational reply queue index 4134 * 4135 * Return: Nothing. 4136 */ 4137 static void mpi3mr_memset_op_reply_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx) 4138 { 4139 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx; 4140 struct segments *segments; 4141 int i, size; 4142 4143 if (!op_reply_q->q_segments) 4144 return; 4145 4146 size = op_reply_q->segment_qd * mrioc->op_reply_desc_sz; 4147 segments = op_reply_q->q_segments; 4148 for (i = 0; i < op_reply_q->num_segments; i++) 4149 memset(segments[i].segment, 0, size); 4150 } 4151 4152 /** 4153 * mpi3mr_memset_op_req_q_buffers - memset the operational request queue's 4154 * segments 4155 * @mrioc: Adapter instance reference 4156 * @qidx: Operational request queue index 4157 * 4158 * Return: Nothing. 4159 */ 4160 static void mpi3mr_memset_op_req_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx) 4161 { 4162 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx; 4163 struct segments *segments; 4164 int i, size; 4165 4166 if (!op_req_q->q_segments) 4167 return; 4168 4169 size = op_req_q->segment_qd * mrioc->facts.op_req_sz; 4170 segments = op_req_q->q_segments; 4171 for (i = 0; i < op_req_q->num_segments; i++) 4172 memset(segments[i].segment, 0, size); 4173 } 4174 4175 /** 4176 * mpi3mr_memset_buffers - memset memory for a controller 4177 * @mrioc: Adapter instance reference 4178 * 4179 * clear all the memory allocated for a controller, typically 4180 * called post reset to reuse the memory allocated during the 4181 * controller init. 4182 * 4183 * Return: Nothing. 4184 */ 4185 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc) 4186 { 4187 u16 i; 4188 struct mpi3mr_throttle_group_info *tg; 4189 4190 mrioc->change_count = 0; 4191 mrioc->active_poll_qcount = 0; 4192 mrioc->default_qcount = 0; 4193 if (mrioc->admin_req_base) 4194 memset(mrioc->admin_req_base, 0, mrioc->admin_req_q_sz); 4195 if (mrioc->admin_reply_base) 4196 memset(mrioc->admin_reply_base, 0, mrioc->admin_reply_q_sz); 4197 atomic_set(&mrioc->admin_reply_q_in_use, 0); 4198 4199 if (mrioc->init_cmds.reply) { 4200 memset(mrioc->init_cmds.reply, 0, sizeof(*mrioc->init_cmds.reply)); 4201 memset(mrioc->bsg_cmds.reply, 0, 4202 sizeof(*mrioc->bsg_cmds.reply)); 4203 memset(mrioc->host_tm_cmds.reply, 0, 4204 sizeof(*mrioc->host_tm_cmds.reply)); 4205 memset(mrioc->pel_cmds.reply, 0, 4206 sizeof(*mrioc->pel_cmds.reply)); 4207 memset(mrioc->pel_abort_cmd.reply, 0, 4208 sizeof(*mrioc->pel_abort_cmd.reply)); 4209 memset(mrioc->transport_cmds.reply, 0, 4210 sizeof(*mrioc->transport_cmds.reply)); 4211 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) 4212 memset(mrioc->dev_rmhs_cmds[i].reply, 0, 4213 sizeof(*mrioc->dev_rmhs_cmds[i].reply)); 4214 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) 4215 memset(mrioc->evtack_cmds[i].reply, 0, 4216 sizeof(*mrioc->evtack_cmds[i].reply)); 4217 bitmap_clear(mrioc->removepend_bitmap, 0, 4218 mrioc->dev_handle_bitmap_bits); 4219 bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD); 4220 bitmap_clear(mrioc->evtack_cmds_bitmap, 0, 4221 MPI3MR_NUM_EVTACKCMD); 4222 } 4223 4224 for (i = 0; i < mrioc->num_queues; i++) { 4225 mrioc->op_reply_qinfo[i].qid = 0; 4226 mrioc->op_reply_qinfo[i].ci = 0; 4227 mrioc->op_reply_qinfo[i].num_replies = 0; 4228 mrioc->op_reply_qinfo[i].ephase = 0; 4229 atomic_set(&mrioc->op_reply_qinfo[i].pend_ios, 0); 4230 atomic_set(&mrioc->op_reply_qinfo[i].in_use, 0); 4231 mpi3mr_memset_op_reply_q_buffers(mrioc, i); 4232 4233 mrioc->req_qinfo[i].ci = 0; 4234 mrioc->req_qinfo[i].pi = 0; 4235 mrioc->req_qinfo[i].num_requests = 0; 4236 mrioc->req_qinfo[i].qid = 0; 4237 mrioc->req_qinfo[i].reply_qid = 0; 4238 spin_lock_init(&mrioc->req_qinfo[i].q_lock); 4239 mpi3mr_memset_op_req_q_buffers(mrioc, i); 4240 } 4241 4242 atomic_set(&mrioc->pend_large_data_sz, 0); 4243 if (mrioc->throttle_groups) { 4244 tg = mrioc->throttle_groups; 4245 for (i = 0; i < mrioc->num_io_throttle_group; i++, tg++) { 4246 tg->id = 0; 4247 tg->fw_qd = 0; 4248 tg->modified_qd = 0; 4249 tg->io_divert = 0; 4250 tg->need_qd_reduction = 0; 4251 tg->high = 0; 4252 tg->low = 0; 4253 tg->qd_reduction = 0; 4254 atomic_set(&tg->pend_large_data_sz, 0); 4255 } 4256 } 4257 } 4258 4259 /** 4260 * mpi3mr_free_mem - Free memory allocated for a controller 4261 * @mrioc: Adapter instance reference 4262 * 4263 * Free all the memory allocated for a controller. 4264 * 4265 * Return: Nothing. 4266 */ 4267 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc) 4268 { 4269 u16 i; 4270 struct mpi3mr_intr_info *intr_info; 4271 4272 mpi3mr_free_enclosure_list(mrioc); 4273 4274 if (mrioc->sense_buf_pool) { 4275 if (mrioc->sense_buf) 4276 dma_pool_free(mrioc->sense_buf_pool, mrioc->sense_buf, 4277 mrioc->sense_buf_dma); 4278 dma_pool_destroy(mrioc->sense_buf_pool); 4279 mrioc->sense_buf = NULL; 4280 mrioc->sense_buf_pool = NULL; 4281 } 4282 if (mrioc->sense_buf_q_pool) { 4283 if (mrioc->sense_buf_q) 4284 dma_pool_free(mrioc->sense_buf_q_pool, 4285 mrioc->sense_buf_q, mrioc->sense_buf_q_dma); 4286 dma_pool_destroy(mrioc->sense_buf_q_pool); 4287 mrioc->sense_buf_q = NULL; 4288 mrioc->sense_buf_q_pool = NULL; 4289 } 4290 4291 if (mrioc->reply_buf_pool) { 4292 if (mrioc->reply_buf) 4293 dma_pool_free(mrioc->reply_buf_pool, mrioc->reply_buf, 4294 mrioc->reply_buf_dma); 4295 dma_pool_destroy(mrioc->reply_buf_pool); 4296 mrioc->reply_buf = NULL; 4297 mrioc->reply_buf_pool = NULL; 4298 } 4299 if (mrioc->reply_free_q_pool) { 4300 if (mrioc->reply_free_q) 4301 dma_pool_free(mrioc->reply_free_q_pool, 4302 mrioc->reply_free_q, mrioc->reply_free_q_dma); 4303 dma_pool_destroy(mrioc->reply_free_q_pool); 4304 mrioc->reply_free_q = NULL; 4305 mrioc->reply_free_q_pool = NULL; 4306 } 4307 4308 for (i = 0; i < mrioc->num_op_req_q; i++) 4309 mpi3mr_free_op_req_q_segments(mrioc, i); 4310 4311 for (i = 0; i < mrioc->num_op_reply_q; i++) 4312 mpi3mr_free_op_reply_q_segments(mrioc, i); 4313 4314 for (i = 0; i < mrioc->intr_info_count; i++) { 4315 intr_info = mrioc->intr_info + i; 4316 intr_info->op_reply_q = NULL; 4317 } 4318 4319 kfree(mrioc->req_qinfo); 4320 mrioc->req_qinfo = NULL; 4321 mrioc->num_op_req_q = 0; 4322 4323 kfree(mrioc->op_reply_qinfo); 4324 mrioc->op_reply_qinfo = NULL; 4325 mrioc->num_op_reply_q = 0; 4326 4327 kfree(mrioc->init_cmds.reply); 4328 mrioc->init_cmds.reply = NULL; 4329 4330 kfree(mrioc->bsg_cmds.reply); 4331 mrioc->bsg_cmds.reply = NULL; 4332 4333 kfree(mrioc->host_tm_cmds.reply); 4334 mrioc->host_tm_cmds.reply = NULL; 4335 4336 kfree(mrioc->pel_cmds.reply); 4337 mrioc->pel_cmds.reply = NULL; 4338 4339 kfree(mrioc->pel_abort_cmd.reply); 4340 mrioc->pel_abort_cmd.reply = NULL; 4341 4342 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) { 4343 kfree(mrioc->evtack_cmds[i].reply); 4344 mrioc->evtack_cmds[i].reply = NULL; 4345 } 4346 4347 bitmap_free(mrioc->removepend_bitmap); 4348 mrioc->removepend_bitmap = NULL; 4349 4350 bitmap_free(mrioc->devrem_bitmap); 4351 mrioc->devrem_bitmap = NULL; 4352 4353 bitmap_free(mrioc->evtack_cmds_bitmap); 4354 mrioc->evtack_cmds_bitmap = NULL; 4355 4356 bitmap_free(mrioc->chain_bitmap); 4357 mrioc->chain_bitmap = NULL; 4358 4359 kfree(mrioc->transport_cmds.reply); 4360 mrioc->transport_cmds.reply = NULL; 4361 4362 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) { 4363 kfree(mrioc->dev_rmhs_cmds[i].reply); 4364 mrioc->dev_rmhs_cmds[i].reply = NULL; 4365 } 4366 4367 if (mrioc->chain_buf_pool) { 4368 for (i = 0; i < mrioc->chain_buf_count; i++) { 4369 if (mrioc->chain_sgl_list[i].addr) { 4370 dma_pool_free(mrioc->chain_buf_pool, 4371 mrioc->chain_sgl_list[i].addr, 4372 mrioc->chain_sgl_list[i].dma_addr); 4373 mrioc->chain_sgl_list[i].addr = NULL; 4374 } 4375 } 4376 dma_pool_destroy(mrioc->chain_buf_pool); 4377 mrioc->chain_buf_pool = NULL; 4378 } 4379 4380 kfree(mrioc->chain_sgl_list); 4381 mrioc->chain_sgl_list = NULL; 4382 4383 if (mrioc->admin_reply_base) { 4384 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz, 4385 mrioc->admin_reply_base, mrioc->admin_reply_dma); 4386 mrioc->admin_reply_base = NULL; 4387 } 4388 if (mrioc->admin_req_base) { 4389 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz, 4390 mrioc->admin_req_base, mrioc->admin_req_dma); 4391 mrioc->admin_req_base = NULL; 4392 } 4393 if (mrioc->cfg_page) { 4394 dma_free_coherent(&mrioc->pdev->dev, mrioc->cfg_page_sz, 4395 mrioc->cfg_page, mrioc->cfg_page_dma); 4396 mrioc->cfg_page = NULL; 4397 } 4398 if (mrioc->pel_seqnum_virt) { 4399 dma_free_coherent(&mrioc->pdev->dev, mrioc->pel_seqnum_sz, 4400 mrioc->pel_seqnum_virt, mrioc->pel_seqnum_dma); 4401 mrioc->pel_seqnum_virt = NULL; 4402 } 4403 4404 kfree(mrioc->throttle_groups); 4405 mrioc->throttle_groups = NULL; 4406 4407 kfree(mrioc->logdata_buf); 4408 mrioc->logdata_buf = NULL; 4409 4410 } 4411 4412 /** 4413 * mpi3mr_issue_ioc_shutdown - shutdown controller 4414 * @mrioc: Adapter instance reference 4415 * 4416 * Send shutodwn notification to the controller and wait for the 4417 * shutdown_timeout for it to be completed. 4418 * 4419 * Return: Nothing. 4420 */ 4421 static void mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc *mrioc) 4422 { 4423 u32 ioc_config, ioc_status; 4424 u8 retval = 1; 4425 u32 timeout = MPI3MR_DEFAULT_SHUTDOWN_TIME * 10; 4426 4427 ioc_info(mrioc, "Issuing shutdown Notification\n"); 4428 if (mrioc->unrecoverable) { 4429 ioc_warn(mrioc, 4430 "IOC is unrecoverable shutdown is not issued\n"); 4431 return; 4432 } 4433 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 4434 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK) 4435 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) { 4436 ioc_info(mrioc, "shutdown already in progress\n"); 4437 return; 4438 } 4439 4440 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 4441 ioc_config |= MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL; 4442 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ; 4443 4444 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); 4445 4446 if (mrioc->facts.shutdown_timeout) 4447 timeout = mrioc->facts.shutdown_timeout * 10; 4448 4449 do { 4450 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 4451 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK) 4452 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE) { 4453 retval = 0; 4454 break; 4455 } 4456 msleep(100); 4457 } while (--timeout); 4458 4459 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 4460 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 4461 4462 if (retval) { 4463 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK) 4464 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) 4465 ioc_warn(mrioc, 4466 "shutdown still in progress after timeout\n"); 4467 } 4468 4469 ioc_info(mrioc, 4470 "Base IOC Sts/Config after %s shutdown is (0x%x)/(0x%x)\n", 4471 (!retval) ? "successful" : "failed", ioc_status, 4472 ioc_config); 4473 } 4474 4475 /** 4476 * mpi3mr_cleanup_ioc - Cleanup controller 4477 * @mrioc: Adapter instance reference 4478 * 4479 * controller cleanup handler, Message unit reset or soft reset 4480 * and shutdown notification is issued to the controller. 4481 * 4482 * Return: Nothing. 4483 */ 4484 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc) 4485 { 4486 enum mpi3mr_iocstate ioc_state; 4487 4488 dprint_exit(mrioc, "cleaning up the controller\n"); 4489 mpi3mr_ioc_disable_intr(mrioc); 4490 4491 ioc_state = mpi3mr_get_iocstate(mrioc); 4492 4493 if ((!mrioc->unrecoverable) && (!mrioc->reset_in_progress) && 4494 (ioc_state == MRIOC_STATE_READY)) { 4495 if (mpi3mr_issue_and_process_mur(mrioc, 4496 MPI3MR_RESET_FROM_CTLR_CLEANUP)) 4497 mpi3mr_issue_reset(mrioc, 4498 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, 4499 MPI3MR_RESET_FROM_MUR_FAILURE); 4500 mpi3mr_issue_ioc_shutdown(mrioc); 4501 } 4502 dprint_exit(mrioc, "controller cleanup completed\n"); 4503 } 4504 4505 /** 4506 * mpi3mr_drv_cmd_comp_reset - Flush a internal driver command 4507 * @mrioc: Adapter instance reference 4508 * @cmdptr: Internal command tracker 4509 * 4510 * Complete an internal driver commands with state indicating it 4511 * is completed due to reset. 4512 * 4513 * Return: Nothing. 4514 */ 4515 static inline void mpi3mr_drv_cmd_comp_reset(struct mpi3mr_ioc *mrioc, 4516 struct mpi3mr_drv_cmd *cmdptr) 4517 { 4518 if (cmdptr->state & MPI3MR_CMD_PENDING) { 4519 cmdptr->state |= MPI3MR_CMD_RESET; 4520 cmdptr->state &= ~MPI3MR_CMD_PENDING; 4521 if (cmdptr->is_waiting) { 4522 complete(&cmdptr->done); 4523 cmdptr->is_waiting = 0; 4524 } else if (cmdptr->callback) 4525 cmdptr->callback(mrioc, cmdptr); 4526 } 4527 } 4528 4529 /** 4530 * mpi3mr_flush_drv_cmds - Flush internaldriver commands 4531 * @mrioc: Adapter instance reference 4532 * 4533 * Flush all internal driver commands post reset 4534 * 4535 * Return: Nothing. 4536 */ 4537 void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc) 4538 { 4539 struct mpi3mr_drv_cmd *cmdptr; 4540 u8 i; 4541 4542 cmdptr = &mrioc->init_cmds; 4543 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4544 4545 cmdptr = &mrioc->cfg_cmds; 4546 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4547 4548 cmdptr = &mrioc->bsg_cmds; 4549 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4550 cmdptr = &mrioc->host_tm_cmds; 4551 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4552 4553 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) { 4554 cmdptr = &mrioc->dev_rmhs_cmds[i]; 4555 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4556 } 4557 4558 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) { 4559 cmdptr = &mrioc->evtack_cmds[i]; 4560 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4561 } 4562 4563 cmdptr = &mrioc->pel_cmds; 4564 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4565 4566 cmdptr = &mrioc->pel_abort_cmd; 4567 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4568 4569 cmdptr = &mrioc->transport_cmds; 4570 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4571 } 4572 4573 /** 4574 * mpi3mr_pel_wait_post - Issue PEL Wait 4575 * @mrioc: Adapter instance reference 4576 * @drv_cmd: Internal command tracker 4577 * 4578 * Issue PEL Wait MPI request through admin queue and return. 4579 * 4580 * Return: Nothing. 4581 */ 4582 static void mpi3mr_pel_wait_post(struct mpi3mr_ioc *mrioc, 4583 struct mpi3mr_drv_cmd *drv_cmd) 4584 { 4585 struct mpi3_pel_req_action_wait pel_wait; 4586 4587 mrioc->pel_abort_requested = false; 4588 4589 memset(&pel_wait, 0, sizeof(pel_wait)); 4590 drv_cmd->state = MPI3MR_CMD_PENDING; 4591 drv_cmd->is_waiting = 0; 4592 drv_cmd->callback = mpi3mr_pel_wait_complete; 4593 drv_cmd->ioc_status = 0; 4594 drv_cmd->ioc_loginfo = 0; 4595 pel_wait.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT); 4596 pel_wait.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG; 4597 pel_wait.action = MPI3_PEL_ACTION_WAIT; 4598 pel_wait.starting_sequence_number = cpu_to_le32(mrioc->pel_newest_seqnum); 4599 pel_wait.locale = cpu_to_le16(mrioc->pel_locale); 4600 pel_wait.class = cpu_to_le16(mrioc->pel_class); 4601 pel_wait.wait_time = MPI3_PEL_WAITTIME_INFINITE_WAIT; 4602 dprint_bsg_info(mrioc, "sending pel_wait seqnum(%d), class(%d), locale(0x%08x)\n", 4603 mrioc->pel_newest_seqnum, mrioc->pel_class, mrioc->pel_locale); 4604 4605 if (mpi3mr_admin_request_post(mrioc, &pel_wait, sizeof(pel_wait), 0)) { 4606 dprint_bsg_err(mrioc, 4607 "Issuing PELWait: Admin post failed\n"); 4608 drv_cmd->state = MPI3MR_CMD_NOTUSED; 4609 drv_cmd->callback = NULL; 4610 drv_cmd->retry_count = 0; 4611 mrioc->pel_enabled = false; 4612 } 4613 } 4614 4615 /** 4616 * mpi3mr_pel_get_seqnum_post - Issue PEL Get Sequence number 4617 * @mrioc: Adapter instance reference 4618 * @drv_cmd: Internal command tracker 4619 * 4620 * Issue PEL get sequence number MPI request through admin queue 4621 * and return. 4622 * 4623 * Return: 0 on success, non-zero on failure. 4624 */ 4625 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc, 4626 struct mpi3mr_drv_cmd *drv_cmd) 4627 { 4628 struct mpi3_pel_req_action_get_sequence_numbers pel_getseq_req; 4629 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 4630 int retval = 0; 4631 4632 memset(&pel_getseq_req, 0, sizeof(pel_getseq_req)); 4633 mrioc->pel_cmds.state = MPI3MR_CMD_PENDING; 4634 mrioc->pel_cmds.is_waiting = 0; 4635 mrioc->pel_cmds.ioc_status = 0; 4636 mrioc->pel_cmds.ioc_loginfo = 0; 4637 mrioc->pel_cmds.callback = mpi3mr_pel_get_seqnum_complete; 4638 pel_getseq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT); 4639 pel_getseq_req.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG; 4640 pel_getseq_req.action = MPI3_PEL_ACTION_GET_SEQNUM; 4641 mpi3mr_add_sg_single(&pel_getseq_req.sgl, sgl_flags, 4642 mrioc->pel_seqnum_sz, mrioc->pel_seqnum_dma); 4643 4644 retval = mpi3mr_admin_request_post(mrioc, &pel_getseq_req, 4645 sizeof(pel_getseq_req), 0); 4646 if (retval) { 4647 if (drv_cmd) { 4648 drv_cmd->state = MPI3MR_CMD_NOTUSED; 4649 drv_cmd->callback = NULL; 4650 drv_cmd->retry_count = 0; 4651 } 4652 mrioc->pel_enabled = false; 4653 } 4654 4655 return retval; 4656 } 4657 4658 /** 4659 * mpi3mr_pel_wait_complete - PELWait Completion callback 4660 * @mrioc: Adapter instance reference 4661 * @drv_cmd: Internal command tracker 4662 * 4663 * This is a callback handler for the PELWait request and 4664 * firmware completes a PELWait request when it is aborted or a 4665 * new PEL entry is available. This sends AEN to the application 4666 * and if the PELwait completion is not due to PELAbort then 4667 * this will send a request for new PEL Sequence number 4668 * 4669 * Return: Nothing. 4670 */ 4671 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc, 4672 struct mpi3mr_drv_cmd *drv_cmd) 4673 { 4674 struct mpi3_pel_reply *pel_reply = NULL; 4675 u16 ioc_status, pe_log_status; 4676 bool do_retry = false; 4677 4678 if (drv_cmd->state & MPI3MR_CMD_RESET) 4679 goto cleanup_drv_cmd; 4680 4681 ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK; 4682 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 4683 ioc_err(mrioc, "%s: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 4684 __func__, ioc_status, drv_cmd->ioc_loginfo); 4685 dprint_bsg_err(mrioc, 4686 "pel_wait: failed with ioc_status(0x%04x), log_info(0x%08x)\n", 4687 ioc_status, drv_cmd->ioc_loginfo); 4688 do_retry = true; 4689 } 4690 4691 if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID) 4692 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply; 4693 4694 if (!pel_reply) { 4695 dprint_bsg_err(mrioc, 4696 "pel_wait: failed due to no reply\n"); 4697 goto out_failed; 4698 } 4699 4700 pe_log_status = le16_to_cpu(pel_reply->pe_log_status); 4701 if ((pe_log_status != MPI3_PEL_STATUS_SUCCESS) && 4702 (pe_log_status != MPI3_PEL_STATUS_ABORTED)) { 4703 ioc_err(mrioc, "%s: Failed pe_log_status(0x%04x)\n", 4704 __func__, pe_log_status); 4705 dprint_bsg_err(mrioc, 4706 "pel_wait: failed due to pel_log_status(0x%04x)\n", 4707 pe_log_status); 4708 do_retry = true; 4709 } 4710 4711 if (do_retry) { 4712 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) { 4713 drv_cmd->retry_count++; 4714 dprint_bsg_err(mrioc, "pel_wait: retrying(%d)\n", 4715 drv_cmd->retry_count); 4716 mpi3mr_pel_wait_post(mrioc, drv_cmd); 4717 return; 4718 } 4719 dprint_bsg_err(mrioc, 4720 "pel_wait: failed after all retries(%d)\n", 4721 drv_cmd->retry_count); 4722 goto out_failed; 4723 } 4724 atomic64_inc(&event_counter); 4725 if (!mrioc->pel_abort_requested) { 4726 mrioc->pel_cmds.retry_count = 0; 4727 mpi3mr_pel_get_seqnum_post(mrioc, &mrioc->pel_cmds); 4728 } 4729 4730 return; 4731 out_failed: 4732 mrioc->pel_enabled = false; 4733 cleanup_drv_cmd: 4734 drv_cmd->state = MPI3MR_CMD_NOTUSED; 4735 drv_cmd->callback = NULL; 4736 drv_cmd->retry_count = 0; 4737 } 4738 4739 /** 4740 * mpi3mr_pel_get_seqnum_complete - PELGetSeqNum Completion callback 4741 * @mrioc: Adapter instance reference 4742 * @drv_cmd: Internal command tracker 4743 * 4744 * This is a callback handler for the PEL get sequence number 4745 * request and a new PEL wait request will be issued to the 4746 * firmware from this 4747 * 4748 * Return: Nothing. 4749 */ 4750 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc, 4751 struct mpi3mr_drv_cmd *drv_cmd) 4752 { 4753 struct mpi3_pel_reply *pel_reply = NULL; 4754 struct mpi3_pel_seq *pel_seqnum_virt; 4755 u16 ioc_status; 4756 bool do_retry = false; 4757 4758 pel_seqnum_virt = (struct mpi3_pel_seq *)mrioc->pel_seqnum_virt; 4759 4760 if (drv_cmd->state & MPI3MR_CMD_RESET) 4761 goto cleanup_drv_cmd; 4762 4763 ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK; 4764 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 4765 dprint_bsg_err(mrioc, 4766 "pel_get_seqnum: failed with ioc_status(0x%04x), log_info(0x%08x)\n", 4767 ioc_status, drv_cmd->ioc_loginfo); 4768 do_retry = true; 4769 } 4770 4771 if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID) 4772 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply; 4773 if (!pel_reply) { 4774 dprint_bsg_err(mrioc, 4775 "pel_get_seqnum: failed due to no reply\n"); 4776 goto out_failed; 4777 } 4778 4779 if (le16_to_cpu(pel_reply->pe_log_status) != MPI3_PEL_STATUS_SUCCESS) { 4780 dprint_bsg_err(mrioc, 4781 "pel_get_seqnum: failed due to pel_log_status(0x%04x)\n", 4782 le16_to_cpu(pel_reply->pe_log_status)); 4783 do_retry = true; 4784 } 4785 4786 if (do_retry) { 4787 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) { 4788 drv_cmd->retry_count++; 4789 dprint_bsg_err(mrioc, 4790 "pel_get_seqnum: retrying(%d)\n", 4791 drv_cmd->retry_count); 4792 mpi3mr_pel_get_seqnum_post(mrioc, drv_cmd); 4793 return; 4794 } 4795 4796 dprint_bsg_err(mrioc, 4797 "pel_get_seqnum: failed after all retries(%d)\n", 4798 drv_cmd->retry_count); 4799 goto out_failed; 4800 } 4801 mrioc->pel_newest_seqnum = le32_to_cpu(pel_seqnum_virt->newest) + 1; 4802 drv_cmd->retry_count = 0; 4803 mpi3mr_pel_wait_post(mrioc, drv_cmd); 4804 4805 return; 4806 out_failed: 4807 mrioc->pel_enabled = false; 4808 cleanup_drv_cmd: 4809 drv_cmd->state = MPI3MR_CMD_NOTUSED; 4810 drv_cmd->callback = NULL; 4811 drv_cmd->retry_count = 0; 4812 } 4813 4814 /** 4815 * mpi3mr_soft_reset_handler - Reset the controller 4816 * @mrioc: Adapter instance reference 4817 * @reset_reason: Reset reason code 4818 * @snapdump: Flag to generate snapdump in firmware or not 4819 * 4820 * This is an handler for recovering controller by issuing soft 4821 * reset are diag fault reset. This is a blocking function and 4822 * when one reset is executed if any other resets they will be 4823 * blocked. All BSG requests will be blocked during the reset. If 4824 * controller reset is successful then the controller will be 4825 * reinitalized, otherwise the controller will be marked as not 4826 * recoverable 4827 * 4828 * In snapdump bit is set, the controller is issued with diag 4829 * fault reset so that the firmware can create a snap dump and 4830 * post that the firmware will result in F000 fault and the 4831 * driver will issue soft reset to recover from that. 4832 * 4833 * Return: 0 on success, non-zero on failure. 4834 */ 4835 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, 4836 u32 reset_reason, u8 snapdump) 4837 { 4838 int retval = 0, i; 4839 unsigned long flags; 4840 u32 host_diagnostic, timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10; 4841 4842 /* Block the reset handler until diag save in progress*/ 4843 dprint_reset(mrioc, 4844 "soft_reset_handler: check and block on diagsave_timeout(%d)\n", 4845 mrioc->diagsave_timeout); 4846 while (mrioc->diagsave_timeout) 4847 ssleep(1); 4848 /* 4849 * Block new resets until the currently executing one is finished and 4850 * return the status of the existing reset for all blocked resets 4851 */ 4852 dprint_reset(mrioc, "soft_reset_handler: acquiring reset_mutex\n"); 4853 if (!mutex_trylock(&mrioc->reset_mutex)) { 4854 ioc_info(mrioc, 4855 "controller reset triggered by %s is blocked due to another reset in progress\n", 4856 mpi3mr_reset_rc_name(reset_reason)); 4857 do { 4858 ssleep(1); 4859 } while (mrioc->reset_in_progress == 1); 4860 ioc_info(mrioc, 4861 "returning previous reset result(%d) for the reset triggered by %s\n", 4862 mrioc->prev_reset_result, 4863 mpi3mr_reset_rc_name(reset_reason)); 4864 return mrioc->prev_reset_result; 4865 } 4866 ioc_info(mrioc, "controller reset is triggered by %s\n", 4867 mpi3mr_reset_rc_name(reset_reason)); 4868 4869 mrioc->device_refresh_on = 0; 4870 mrioc->reset_in_progress = 1; 4871 mrioc->stop_bsgs = 1; 4872 mrioc->prev_reset_result = -1; 4873 4874 if ((!snapdump) && (reset_reason != MPI3MR_RESET_FROM_FAULT_WATCH) && 4875 (reset_reason != MPI3MR_RESET_FROM_FIRMWARE) && 4876 (reset_reason != MPI3MR_RESET_FROM_CIACTIV_FAULT)) { 4877 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 4878 mrioc->event_masks[i] = -1; 4879 4880 dprint_reset(mrioc, "soft_reset_handler: masking events\n"); 4881 mpi3mr_issue_event_notification(mrioc); 4882 } 4883 4884 mpi3mr_wait_for_host_io(mrioc, MPI3MR_RESET_HOST_IOWAIT_TIMEOUT); 4885 4886 mpi3mr_ioc_disable_intr(mrioc); 4887 4888 if (snapdump) { 4889 mpi3mr_set_diagsave(mrioc); 4890 retval = mpi3mr_issue_reset(mrioc, 4891 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason); 4892 if (!retval) { 4893 do { 4894 host_diagnostic = 4895 readl(&mrioc->sysif_regs->host_diagnostic); 4896 if (!(host_diagnostic & 4897 MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS)) 4898 break; 4899 msleep(100); 4900 } while (--timeout); 4901 } 4902 } 4903 4904 retval = mpi3mr_issue_reset(mrioc, 4905 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, reset_reason); 4906 if (retval) { 4907 ioc_err(mrioc, "Failed to issue soft reset to the ioc\n"); 4908 goto out; 4909 } 4910 if (mrioc->num_io_throttle_group != 4911 mrioc->facts.max_io_throttle_group) { 4912 ioc_err(mrioc, 4913 "max io throttle group doesn't match old(%d), new(%d)\n", 4914 mrioc->num_io_throttle_group, 4915 mrioc->facts.max_io_throttle_group); 4916 retval = -EPERM; 4917 goto out; 4918 } 4919 4920 mpi3mr_flush_delayed_cmd_lists(mrioc); 4921 mpi3mr_flush_drv_cmds(mrioc); 4922 bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD); 4923 bitmap_clear(mrioc->removepend_bitmap, 0, 4924 mrioc->dev_handle_bitmap_bits); 4925 bitmap_clear(mrioc->evtack_cmds_bitmap, 0, MPI3MR_NUM_EVTACKCMD); 4926 mpi3mr_flush_host_io(mrioc); 4927 mpi3mr_cleanup_fwevt_list(mrioc); 4928 mpi3mr_invalidate_devhandles(mrioc); 4929 mpi3mr_free_enclosure_list(mrioc); 4930 4931 if (mrioc->prepare_for_reset) { 4932 mrioc->prepare_for_reset = 0; 4933 mrioc->prepare_for_reset_timeout_counter = 0; 4934 } 4935 mpi3mr_memset_buffers(mrioc); 4936 retval = mpi3mr_reinit_ioc(mrioc, 0); 4937 if (retval) { 4938 pr_err(IOCNAME "reinit after soft reset failed: reason %d\n", 4939 mrioc->name, reset_reason); 4940 goto out; 4941 } 4942 ssleep(MPI3MR_RESET_TOPOLOGY_SETTLE_TIME); 4943 4944 out: 4945 if (!retval) { 4946 mrioc->diagsave_timeout = 0; 4947 mrioc->reset_in_progress = 0; 4948 mrioc->pel_abort_requested = 0; 4949 if (mrioc->pel_enabled) { 4950 mrioc->pel_cmds.retry_count = 0; 4951 mpi3mr_pel_wait_post(mrioc, &mrioc->pel_cmds); 4952 } 4953 4954 mrioc->device_refresh_on = 0; 4955 4956 mrioc->ts_update_counter = 0; 4957 spin_lock_irqsave(&mrioc->watchdog_lock, flags); 4958 if (mrioc->watchdog_work_q) 4959 queue_delayed_work(mrioc->watchdog_work_q, 4960 &mrioc->watchdog_work, 4961 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL)); 4962 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags); 4963 mrioc->stop_bsgs = 0; 4964 if (mrioc->pel_enabled) 4965 atomic64_inc(&event_counter); 4966 } else { 4967 mpi3mr_issue_reset(mrioc, 4968 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason); 4969 mrioc->device_refresh_on = 0; 4970 mrioc->unrecoverable = 1; 4971 mrioc->reset_in_progress = 0; 4972 retval = -1; 4973 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc); 4974 } 4975 mrioc->prev_reset_result = retval; 4976 mutex_unlock(&mrioc->reset_mutex); 4977 ioc_info(mrioc, "controller reset is %s\n", 4978 ((retval == 0) ? "successful" : "failed")); 4979 return retval; 4980 } 4981 4982 4983 /** 4984 * mpi3mr_free_config_dma_memory - free memory for config page 4985 * @mrioc: Adapter instance reference 4986 * @mem_desc: memory descriptor structure 4987 * 4988 * Check whether the size of the buffer specified by the memory 4989 * descriptor is greater than the default page size if so then 4990 * free the memory pointed by the descriptor. 4991 * 4992 * Return: Nothing. 4993 */ 4994 static void mpi3mr_free_config_dma_memory(struct mpi3mr_ioc *mrioc, 4995 struct dma_memory_desc *mem_desc) 4996 { 4997 if ((mem_desc->size > mrioc->cfg_page_sz) && mem_desc->addr) { 4998 dma_free_coherent(&mrioc->pdev->dev, mem_desc->size, 4999 mem_desc->addr, mem_desc->dma_addr); 5000 mem_desc->addr = NULL; 5001 } 5002 } 5003 5004 /** 5005 * mpi3mr_alloc_config_dma_memory - Alloc memory for config page 5006 * @mrioc: Adapter instance reference 5007 * @mem_desc: Memory descriptor to hold dma memory info 5008 * 5009 * This function allocates new dmaable memory or provides the 5010 * default config page dmaable memory based on the memory size 5011 * described by the descriptor. 5012 * 5013 * Return: 0 on success, non-zero on failure. 5014 */ 5015 static int mpi3mr_alloc_config_dma_memory(struct mpi3mr_ioc *mrioc, 5016 struct dma_memory_desc *mem_desc) 5017 { 5018 if (mem_desc->size > mrioc->cfg_page_sz) { 5019 mem_desc->addr = dma_alloc_coherent(&mrioc->pdev->dev, 5020 mem_desc->size, &mem_desc->dma_addr, GFP_KERNEL); 5021 if (!mem_desc->addr) 5022 return -ENOMEM; 5023 } else { 5024 mem_desc->addr = mrioc->cfg_page; 5025 mem_desc->dma_addr = mrioc->cfg_page_dma; 5026 memset(mem_desc->addr, 0, mrioc->cfg_page_sz); 5027 } 5028 return 0; 5029 } 5030 5031 /** 5032 * mpi3mr_post_cfg_req - Issue config requests and wait 5033 * @mrioc: Adapter instance reference 5034 * @cfg_req: Configuration request 5035 * @timeout: Timeout in seconds 5036 * @ioc_status: Pointer to return ioc status 5037 * 5038 * A generic function for posting MPI3 configuration request to 5039 * the firmware. This blocks for the completion of request for 5040 * timeout seconds and if the request times out this function 5041 * faults the controller with proper reason code. 5042 * 5043 * On successful completion of the request this function returns 5044 * appropriate ioc status from the firmware back to the caller. 5045 * 5046 * Return: 0 on success, non-zero on failure. 5047 */ 5048 static int mpi3mr_post_cfg_req(struct mpi3mr_ioc *mrioc, 5049 struct mpi3_config_request *cfg_req, int timeout, u16 *ioc_status) 5050 { 5051 int retval = 0; 5052 5053 mutex_lock(&mrioc->cfg_cmds.mutex); 5054 if (mrioc->cfg_cmds.state & MPI3MR_CMD_PENDING) { 5055 retval = -1; 5056 ioc_err(mrioc, "sending config request failed due to command in use\n"); 5057 mutex_unlock(&mrioc->cfg_cmds.mutex); 5058 goto out; 5059 } 5060 mrioc->cfg_cmds.state = MPI3MR_CMD_PENDING; 5061 mrioc->cfg_cmds.is_waiting = 1; 5062 mrioc->cfg_cmds.callback = NULL; 5063 mrioc->cfg_cmds.ioc_status = 0; 5064 mrioc->cfg_cmds.ioc_loginfo = 0; 5065 5066 cfg_req->host_tag = cpu_to_le16(MPI3MR_HOSTTAG_CFG_CMDS); 5067 cfg_req->function = MPI3_FUNCTION_CONFIG; 5068 5069 init_completion(&mrioc->cfg_cmds.done); 5070 dprint_cfg_info(mrioc, "posting config request\n"); 5071 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO) 5072 dprint_dump(cfg_req, sizeof(struct mpi3_config_request), 5073 "mpi3_cfg_req"); 5074 retval = mpi3mr_admin_request_post(mrioc, cfg_req, sizeof(*cfg_req), 1); 5075 if (retval) { 5076 ioc_err(mrioc, "posting config request failed\n"); 5077 goto out_unlock; 5078 } 5079 wait_for_completion_timeout(&mrioc->cfg_cmds.done, (timeout * HZ)); 5080 if (!(mrioc->cfg_cmds.state & MPI3MR_CMD_COMPLETE)) { 5081 mpi3mr_check_rh_fault_ioc(mrioc, 5082 MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT); 5083 ioc_err(mrioc, "config request timed out\n"); 5084 retval = -1; 5085 goto out_unlock; 5086 } 5087 *ioc_status = mrioc->cfg_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK; 5088 if ((*ioc_status) != MPI3_IOCSTATUS_SUCCESS) 5089 dprint_cfg_err(mrioc, 5090 "cfg_page request returned with ioc_status(0x%04x), log_info(0x%08x)\n", 5091 *ioc_status, mrioc->cfg_cmds.ioc_loginfo); 5092 5093 out_unlock: 5094 mrioc->cfg_cmds.state = MPI3MR_CMD_NOTUSED; 5095 mutex_unlock(&mrioc->cfg_cmds.mutex); 5096 5097 out: 5098 return retval; 5099 } 5100 5101 /** 5102 * mpi3mr_process_cfg_req - config page request processor 5103 * @mrioc: Adapter instance reference 5104 * @cfg_req: Configuration request 5105 * @cfg_hdr: Configuration page header 5106 * @timeout: Timeout in seconds 5107 * @ioc_status: Pointer to return ioc status 5108 * @cfg_buf: Memory pointer to copy config page or header 5109 * @cfg_buf_sz: Size of the memory to get config page or header 5110 * 5111 * This is handler for config page read, write and config page 5112 * header read operations. 5113 * 5114 * This function expects the cfg_req to be populated with page 5115 * type, page number, action for the header read and with page 5116 * address for all other operations. 5117 * 5118 * The cfg_hdr can be passed as null for reading required header 5119 * details for read/write pages the cfg_hdr should point valid 5120 * configuration page header. 5121 * 5122 * This allocates dmaable memory based on the size of the config 5123 * buffer and set the SGE of the cfg_req. 5124 * 5125 * For write actions, the config page data has to be passed in 5126 * the cfg_buf and size of the data has to be mentioned in the 5127 * cfg_buf_sz. 5128 * 5129 * For read/header actions, on successful completion of the 5130 * request with successful ioc_status the data will be copied 5131 * into the cfg_buf limited to a minimum of actual page size and 5132 * cfg_buf_sz 5133 * 5134 * 5135 * Return: 0 on success, non-zero on failure. 5136 */ 5137 static int mpi3mr_process_cfg_req(struct mpi3mr_ioc *mrioc, 5138 struct mpi3_config_request *cfg_req, 5139 struct mpi3_config_page_header *cfg_hdr, int timeout, u16 *ioc_status, 5140 void *cfg_buf, u32 cfg_buf_sz) 5141 { 5142 struct dma_memory_desc mem_desc; 5143 int retval = -1; 5144 u8 invalid_action = 0; 5145 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 5146 5147 memset(&mem_desc, 0, sizeof(struct dma_memory_desc)); 5148 5149 if (cfg_req->action == MPI3_CONFIG_ACTION_PAGE_HEADER) 5150 mem_desc.size = sizeof(struct mpi3_config_page_header); 5151 else { 5152 if (!cfg_hdr) { 5153 ioc_err(mrioc, "null config header passed for config action(%d), page_type(0x%02x), page_num(%d)\n", 5154 cfg_req->action, cfg_req->page_type, 5155 cfg_req->page_number); 5156 goto out; 5157 } 5158 switch (cfg_hdr->page_attribute & MPI3_CONFIG_PAGEATTR_MASK) { 5159 case MPI3_CONFIG_PAGEATTR_READ_ONLY: 5160 if (cfg_req->action 5161 != MPI3_CONFIG_ACTION_READ_CURRENT) 5162 invalid_action = 1; 5163 break; 5164 case MPI3_CONFIG_PAGEATTR_CHANGEABLE: 5165 if ((cfg_req->action == 5166 MPI3_CONFIG_ACTION_READ_PERSISTENT) || 5167 (cfg_req->action == 5168 MPI3_CONFIG_ACTION_WRITE_PERSISTENT)) 5169 invalid_action = 1; 5170 break; 5171 case MPI3_CONFIG_PAGEATTR_PERSISTENT: 5172 default: 5173 break; 5174 } 5175 if (invalid_action) { 5176 ioc_err(mrioc, 5177 "config action(%d) is not allowed for page_type(0x%02x), page_num(%d) with page_attribute(0x%02x)\n", 5178 cfg_req->action, cfg_req->page_type, 5179 cfg_req->page_number, cfg_hdr->page_attribute); 5180 goto out; 5181 } 5182 mem_desc.size = le16_to_cpu(cfg_hdr->page_length) * 4; 5183 cfg_req->page_length = cfg_hdr->page_length; 5184 cfg_req->page_version = cfg_hdr->page_version; 5185 } 5186 if (mpi3mr_alloc_config_dma_memory(mrioc, &mem_desc)) 5187 goto out; 5188 5189 mpi3mr_add_sg_single(&cfg_req->sgl, sgl_flags, mem_desc.size, 5190 mem_desc.dma_addr); 5191 5192 if ((cfg_req->action == MPI3_CONFIG_ACTION_WRITE_PERSISTENT) || 5193 (cfg_req->action == MPI3_CONFIG_ACTION_WRITE_CURRENT)) { 5194 memcpy(mem_desc.addr, cfg_buf, min_t(u16, mem_desc.size, 5195 cfg_buf_sz)); 5196 dprint_cfg_info(mrioc, "config buffer to be written\n"); 5197 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO) 5198 dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf"); 5199 } 5200 5201 if (mpi3mr_post_cfg_req(mrioc, cfg_req, timeout, ioc_status)) 5202 goto out; 5203 5204 retval = 0; 5205 if ((*ioc_status == MPI3_IOCSTATUS_SUCCESS) && 5206 (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_PERSISTENT) && 5207 (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_CURRENT)) { 5208 memcpy(cfg_buf, mem_desc.addr, min_t(u16, mem_desc.size, 5209 cfg_buf_sz)); 5210 dprint_cfg_info(mrioc, "config buffer read\n"); 5211 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO) 5212 dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf"); 5213 } 5214 5215 out: 5216 mpi3mr_free_config_dma_memory(mrioc, &mem_desc); 5217 return retval; 5218 } 5219 5220 /** 5221 * mpi3mr_cfg_get_dev_pg0 - Read current device page0 5222 * @mrioc: Adapter instance reference 5223 * @ioc_status: Pointer to return ioc status 5224 * @dev_pg0: Pointer to return device page 0 5225 * @pg_sz: Size of the memory allocated to the page pointer 5226 * @form: The form to be used for addressing the page 5227 * @form_spec: Form specific information like device handle 5228 * 5229 * This is handler for config page read for a specific device 5230 * page0. The ioc_status has the controller returned ioc_status. 5231 * This routine doesn't check ioc_status to decide whether the 5232 * page read is success or not and it is the callers 5233 * responsibility. 5234 * 5235 * Return: 0 on success, non-zero on failure. 5236 */ 5237 int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 5238 struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec) 5239 { 5240 struct mpi3_config_page_header cfg_hdr; 5241 struct mpi3_config_request cfg_req; 5242 u32 page_address; 5243 5244 memset(dev_pg0, 0, pg_sz); 5245 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5246 memset(&cfg_req, 0, sizeof(cfg_req)); 5247 5248 cfg_req.function = MPI3_FUNCTION_CONFIG; 5249 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5250 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DEVICE; 5251 cfg_req.page_number = 0; 5252 cfg_req.page_address = 0; 5253 5254 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5255 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5256 ioc_err(mrioc, "device page0 header read failed\n"); 5257 goto out_failed; 5258 } 5259 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5260 ioc_err(mrioc, "device page0 header read failed with ioc_status(0x%04x)\n", 5261 *ioc_status); 5262 goto out_failed; 5263 } 5264 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5265 page_address = ((form & MPI3_DEVICE_PGAD_FORM_MASK) | 5266 (form_spec & MPI3_DEVICE_PGAD_HANDLE_MASK)); 5267 cfg_req.page_address = cpu_to_le32(page_address); 5268 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5269 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, dev_pg0, pg_sz)) { 5270 ioc_err(mrioc, "device page0 read failed\n"); 5271 goto out_failed; 5272 } 5273 return 0; 5274 out_failed: 5275 return -1; 5276 } 5277 5278 5279 /** 5280 * mpi3mr_cfg_get_sas_phy_pg0 - Read current SAS Phy page0 5281 * @mrioc: Adapter instance reference 5282 * @ioc_status: Pointer to return ioc status 5283 * @phy_pg0: Pointer to return SAS Phy page 0 5284 * @pg_sz: Size of the memory allocated to the page pointer 5285 * @form: The form to be used for addressing the page 5286 * @form_spec: Form specific information like phy number 5287 * 5288 * This is handler for config page read for a specific SAS Phy 5289 * page0. The ioc_status has the controller returned ioc_status. 5290 * This routine doesn't check ioc_status to decide whether the 5291 * page read is success or not and it is the callers 5292 * responsibility. 5293 * 5294 * Return: 0 on success, non-zero on failure. 5295 */ 5296 int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 5297 struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form, 5298 u32 form_spec) 5299 { 5300 struct mpi3_config_page_header cfg_hdr; 5301 struct mpi3_config_request cfg_req; 5302 u32 page_address; 5303 5304 memset(phy_pg0, 0, pg_sz); 5305 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5306 memset(&cfg_req, 0, sizeof(cfg_req)); 5307 5308 cfg_req.function = MPI3_FUNCTION_CONFIG; 5309 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5310 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY; 5311 cfg_req.page_number = 0; 5312 cfg_req.page_address = 0; 5313 5314 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5315 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5316 ioc_err(mrioc, "sas phy page0 header read failed\n"); 5317 goto out_failed; 5318 } 5319 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5320 ioc_err(mrioc, "sas phy page0 header read failed with ioc_status(0x%04x)\n", 5321 *ioc_status); 5322 goto out_failed; 5323 } 5324 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5325 page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) | 5326 (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK)); 5327 cfg_req.page_address = cpu_to_le32(page_address); 5328 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5329 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg0, pg_sz)) { 5330 ioc_err(mrioc, "sas phy page0 read failed\n"); 5331 goto out_failed; 5332 } 5333 return 0; 5334 out_failed: 5335 return -1; 5336 } 5337 5338 /** 5339 * mpi3mr_cfg_get_sas_phy_pg1 - Read current SAS Phy page1 5340 * @mrioc: Adapter instance reference 5341 * @ioc_status: Pointer to return ioc status 5342 * @phy_pg1: Pointer to return SAS Phy page 1 5343 * @pg_sz: Size of the memory allocated to the page pointer 5344 * @form: The form to be used for addressing the page 5345 * @form_spec: Form specific information like phy number 5346 * 5347 * This is handler for config page read for a specific SAS Phy 5348 * page1. The ioc_status has the controller returned ioc_status. 5349 * This routine doesn't check ioc_status to decide whether the 5350 * page read is success or not and it is the callers 5351 * responsibility. 5352 * 5353 * Return: 0 on success, non-zero on failure. 5354 */ 5355 int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 5356 struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form, 5357 u32 form_spec) 5358 { 5359 struct mpi3_config_page_header cfg_hdr; 5360 struct mpi3_config_request cfg_req; 5361 u32 page_address; 5362 5363 memset(phy_pg1, 0, pg_sz); 5364 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5365 memset(&cfg_req, 0, sizeof(cfg_req)); 5366 5367 cfg_req.function = MPI3_FUNCTION_CONFIG; 5368 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5369 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY; 5370 cfg_req.page_number = 1; 5371 cfg_req.page_address = 0; 5372 5373 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5374 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5375 ioc_err(mrioc, "sas phy page1 header read failed\n"); 5376 goto out_failed; 5377 } 5378 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5379 ioc_err(mrioc, "sas phy page1 header read failed with ioc_status(0x%04x)\n", 5380 *ioc_status); 5381 goto out_failed; 5382 } 5383 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5384 page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) | 5385 (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK)); 5386 cfg_req.page_address = cpu_to_le32(page_address); 5387 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5388 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg1, pg_sz)) { 5389 ioc_err(mrioc, "sas phy page1 read failed\n"); 5390 goto out_failed; 5391 } 5392 return 0; 5393 out_failed: 5394 return -1; 5395 } 5396 5397 5398 /** 5399 * mpi3mr_cfg_get_sas_exp_pg0 - Read current SAS Expander page0 5400 * @mrioc: Adapter instance reference 5401 * @ioc_status: Pointer to return ioc status 5402 * @exp_pg0: Pointer to return SAS Expander page 0 5403 * @pg_sz: Size of the memory allocated to the page pointer 5404 * @form: The form to be used for addressing the page 5405 * @form_spec: Form specific information like device handle 5406 * 5407 * This is handler for config page read for a specific SAS 5408 * Expander page0. The ioc_status has the controller returned 5409 * ioc_status. This routine doesn't check ioc_status to decide 5410 * whether the page read is success or not and it is the callers 5411 * responsibility. 5412 * 5413 * Return: 0 on success, non-zero on failure. 5414 */ 5415 int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 5416 struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form, 5417 u32 form_spec) 5418 { 5419 struct mpi3_config_page_header cfg_hdr; 5420 struct mpi3_config_request cfg_req; 5421 u32 page_address; 5422 5423 memset(exp_pg0, 0, pg_sz); 5424 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5425 memset(&cfg_req, 0, sizeof(cfg_req)); 5426 5427 cfg_req.function = MPI3_FUNCTION_CONFIG; 5428 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5429 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER; 5430 cfg_req.page_number = 0; 5431 cfg_req.page_address = 0; 5432 5433 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5434 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5435 ioc_err(mrioc, "expander page0 header read failed\n"); 5436 goto out_failed; 5437 } 5438 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5439 ioc_err(mrioc, "expander page0 header read failed with ioc_status(0x%04x)\n", 5440 *ioc_status); 5441 goto out_failed; 5442 } 5443 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5444 page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) | 5445 (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK | 5446 MPI3_SAS_EXPAND_PGAD_HANDLE_MASK))); 5447 cfg_req.page_address = cpu_to_le32(page_address); 5448 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5449 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg0, pg_sz)) { 5450 ioc_err(mrioc, "expander page0 read failed\n"); 5451 goto out_failed; 5452 } 5453 return 0; 5454 out_failed: 5455 return -1; 5456 } 5457 5458 /** 5459 * mpi3mr_cfg_get_sas_exp_pg1 - Read current SAS Expander page1 5460 * @mrioc: Adapter instance reference 5461 * @ioc_status: Pointer to return ioc status 5462 * @exp_pg1: Pointer to return SAS Expander page 1 5463 * @pg_sz: Size of the memory allocated to the page pointer 5464 * @form: The form to be used for addressing the page 5465 * @form_spec: Form specific information like phy number 5466 * 5467 * This is handler for config page read for a specific SAS 5468 * Expander page1. The ioc_status has the controller returned 5469 * ioc_status. This routine doesn't check ioc_status to decide 5470 * whether the page read is success or not and it is the callers 5471 * responsibility. 5472 * 5473 * Return: 0 on success, non-zero on failure. 5474 */ 5475 int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 5476 struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form, 5477 u32 form_spec) 5478 { 5479 struct mpi3_config_page_header cfg_hdr; 5480 struct mpi3_config_request cfg_req; 5481 u32 page_address; 5482 5483 memset(exp_pg1, 0, pg_sz); 5484 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5485 memset(&cfg_req, 0, sizeof(cfg_req)); 5486 5487 cfg_req.function = MPI3_FUNCTION_CONFIG; 5488 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5489 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER; 5490 cfg_req.page_number = 1; 5491 cfg_req.page_address = 0; 5492 5493 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5494 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5495 ioc_err(mrioc, "expander page1 header read failed\n"); 5496 goto out_failed; 5497 } 5498 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5499 ioc_err(mrioc, "expander page1 header read failed with ioc_status(0x%04x)\n", 5500 *ioc_status); 5501 goto out_failed; 5502 } 5503 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5504 page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) | 5505 (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK | 5506 MPI3_SAS_EXPAND_PGAD_HANDLE_MASK))); 5507 cfg_req.page_address = cpu_to_le32(page_address); 5508 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5509 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg1, pg_sz)) { 5510 ioc_err(mrioc, "expander page1 read failed\n"); 5511 goto out_failed; 5512 } 5513 return 0; 5514 out_failed: 5515 return -1; 5516 } 5517 5518 /** 5519 * mpi3mr_cfg_get_enclosure_pg0 - Read current Enclosure page0 5520 * @mrioc: Adapter instance reference 5521 * @ioc_status: Pointer to return ioc status 5522 * @encl_pg0: Pointer to return Enclosure page 0 5523 * @pg_sz: Size of the memory allocated to the page pointer 5524 * @form: The form to be used for addressing the page 5525 * @form_spec: Form specific information like device handle 5526 * 5527 * This is handler for config page read for a specific Enclosure 5528 * page0. The ioc_status has the controller returned ioc_status. 5529 * This routine doesn't check ioc_status to decide whether the 5530 * page read is success or not and it is the callers 5531 * responsibility. 5532 * 5533 * Return: 0 on success, non-zero on failure. 5534 */ 5535 int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 5536 struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form, 5537 u32 form_spec) 5538 { 5539 struct mpi3_config_page_header cfg_hdr; 5540 struct mpi3_config_request cfg_req; 5541 u32 page_address; 5542 5543 memset(encl_pg0, 0, pg_sz); 5544 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5545 memset(&cfg_req, 0, sizeof(cfg_req)); 5546 5547 cfg_req.function = MPI3_FUNCTION_CONFIG; 5548 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5549 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_ENCLOSURE; 5550 cfg_req.page_number = 0; 5551 cfg_req.page_address = 0; 5552 5553 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5554 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5555 ioc_err(mrioc, "enclosure page0 header read failed\n"); 5556 goto out_failed; 5557 } 5558 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5559 ioc_err(mrioc, "enclosure page0 header read failed with ioc_status(0x%04x)\n", 5560 *ioc_status); 5561 goto out_failed; 5562 } 5563 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5564 page_address = ((form & MPI3_ENCLOS_PGAD_FORM_MASK) | 5565 (form_spec & MPI3_ENCLOS_PGAD_HANDLE_MASK)); 5566 cfg_req.page_address = cpu_to_le32(page_address); 5567 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5568 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, encl_pg0, pg_sz)) { 5569 ioc_err(mrioc, "enclosure page0 read failed\n"); 5570 goto out_failed; 5571 } 5572 return 0; 5573 out_failed: 5574 return -1; 5575 } 5576 5577 5578 /** 5579 * mpi3mr_cfg_get_sas_io_unit_pg0 - Read current SASIOUnit page0 5580 * @mrioc: Adapter instance reference 5581 * @sas_io_unit_pg0: Pointer to return SAS IO Unit page 0 5582 * @pg_sz: Size of the memory allocated to the page pointer 5583 * 5584 * This is handler for config page read for the SAS IO Unit 5585 * page0. This routine checks ioc_status to decide whether the 5586 * page read is success or not. 5587 * 5588 * Return: 0 on success, non-zero on failure. 5589 */ 5590 int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc, 5591 struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz) 5592 { 5593 struct mpi3_config_page_header cfg_hdr; 5594 struct mpi3_config_request cfg_req; 5595 u16 ioc_status = 0; 5596 5597 memset(sas_io_unit_pg0, 0, pg_sz); 5598 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5599 memset(&cfg_req, 0, sizeof(cfg_req)); 5600 5601 cfg_req.function = MPI3_FUNCTION_CONFIG; 5602 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5603 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT; 5604 cfg_req.page_number = 0; 5605 cfg_req.page_address = 0; 5606 5607 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5608 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5609 ioc_err(mrioc, "sas io unit page0 header read failed\n"); 5610 goto out_failed; 5611 } 5612 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5613 ioc_err(mrioc, "sas io unit page0 header read failed with ioc_status(0x%04x)\n", 5614 ioc_status); 5615 goto out_failed; 5616 } 5617 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5618 5619 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5620 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg0, pg_sz)) { 5621 ioc_err(mrioc, "sas io unit page0 read failed\n"); 5622 goto out_failed; 5623 } 5624 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5625 ioc_err(mrioc, "sas io unit page0 read failed with ioc_status(0x%04x)\n", 5626 ioc_status); 5627 goto out_failed; 5628 } 5629 return 0; 5630 out_failed: 5631 return -1; 5632 } 5633 5634 /** 5635 * mpi3mr_cfg_get_sas_io_unit_pg1 - Read current SASIOUnit page1 5636 * @mrioc: Adapter instance reference 5637 * @sas_io_unit_pg1: Pointer to return SAS IO Unit page 1 5638 * @pg_sz: Size of the memory allocated to the page pointer 5639 * 5640 * This is handler for config page read for the SAS IO Unit 5641 * page1. This routine checks ioc_status to decide whether the 5642 * page read is success or not. 5643 * 5644 * Return: 0 on success, non-zero on failure. 5645 */ 5646 int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc, 5647 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz) 5648 { 5649 struct mpi3_config_page_header cfg_hdr; 5650 struct mpi3_config_request cfg_req; 5651 u16 ioc_status = 0; 5652 5653 memset(sas_io_unit_pg1, 0, pg_sz); 5654 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5655 memset(&cfg_req, 0, sizeof(cfg_req)); 5656 5657 cfg_req.function = MPI3_FUNCTION_CONFIG; 5658 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5659 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT; 5660 cfg_req.page_number = 1; 5661 cfg_req.page_address = 0; 5662 5663 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5664 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5665 ioc_err(mrioc, "sas io unit page1 header read failed\n"); 5666 goto out_failed; 5667 } 5668 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5669 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n", 5670 ioc_status); 5671 goto out_failed; 5672 } 5673 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5674 5675 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5676 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) { 5677 ioc_err(mrioc, "sas io unit page1 read failed\n"); 5678 goto out_failed; 5679 } 5680 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5681 ioc_err(mrioc, "sas io unit page1 read failed with ioc_status(0x%04x)\n", 5682 ioc_status); 5683 goto out_failed; 5684 } 5685 return 0; 5686 out_failed: 5687 return -1; 5688 } 5689 5690 /** 5691 * mpi3mr_cfg_set_sas_io_unit_pg1 - Write SASIOUnit page1 5692 * @mrioc: Adapter instance reference 5693 * @sas_io_unit_pg1: Pointer to the SAS IO Unit page 1 to write 5694 * @pg_sz: Size of the memory allocated to the page pointer 5695 * 5696 * This is handler for config page write for the SAS IO Unit 5697 * page1. This routine checks ioc_status to decide whether the 5698 * page read is success or not. This will modify both current 5699 * and persistent page. 5700 * 5701 * Return: 0 on success, non-zero on failure. 5702 */ 5703 int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc, 5704 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz) 5705 { 5706 struct mpi3_config_page_header cfg_hdr; 5707 struct mpi3_config_request cfg_req; 5708 u16 ioc_status = 0; 5709 5710 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5711 memset(&cfg_req, 0, sizeof(cfg_req)); 5712 5713 cfg_req.function = MPI3_FUNCTION_CONFIG; 5714 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5715 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT; 5716 cfg_req.page_number = 1; 5717 cfg_req.page_address = 0; 5718 5719 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5720 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5721 ioc_err(mrioc, "sas io unit page1 header read failed\n"); 5722 goto out_failed; 5723 } 5724 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5725 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n", 5726 ioc_status); 5727 goto out_failed; 5728 } 5729 cfg_req.action = MPI3_CONFIG_ACTION_WRITE_CURRENT; 5730 5731 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5732 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) { 5733 ioc_err(mrioc, "sas io unit page1 write current failed\n"); 5734 goto out_failed; 5735 } 5736 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5737 ioc_err(mrioc, "sas io unit page1 write current failed with ioc_status(0x%04x)\n", 5738 ioc_status); 5739 goto out_failed; 5740 } 5741 5742 cfg_req.action = MPI3_CONFIG_ACTION_WRITE_PERSISTENT; 5743 5744 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5745 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) { 5746 ioc_err(mrioc, "sas io unit page1 write persistent failed\n"); 5747 goto out_failed; 5748 } 5749 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5750 ioc_err(mrioc, "sas io unit page1 write persistent failed with ioc_status(0x%04x)\n", 5751 ioc_status); 5752 goto out_failed; 5753 } 5754 return 0; 5755 out_failed: 5756 return -1; 5757 } 5758 5759 /** 5760 * mpi3mr_cfg_get_driver_pg1 - Read current Driver page1 5761 * @mrioc: Adapter instance reference 5762 * @driver_pg1: Pointer to return Driver page 1 5763 * @pg_sz: Size of the memory allocated to the page pointer 5764 * 5765 * This is handler for config page read for the Driver page1. 5766 * This routine checks ioc_status to decide whether the page 5767 * read is success or not. 5768 * 5769 * Return: 0 on success, non-zero on failure. 5770 */ 5771 int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc, 5772 struct mpi3_driver_page1 *driver_pg1, u16 pg_sz) 5773 { 5774 struct mpi3_config_page_header cfg_hdr; 5775 struct mpi3_config_request cfg_req; 5776 u16 ioc_status = 0; 5777 5778 memset(driver_pg1, 0, pg_sz); 5779 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5780 memset(&cfg_req, 0, sizeof(cfg_req)); 5781 5782 cfg_req.function = MPI3_FUNCTION_CONFIG; 5783 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5784 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DRIVER; 5785 cfg_req.page_number = 1; 5786 cfg_req.page_address = 0; 5787 5788 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5789 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5790 ioc_err(mrioc, "driver page1 header read failed\n"); 5791 goto out_failed; 5792 } 5793 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5794 ioc_err(mrioc, "driver page1 header read failed with ioc_status(0x%04x)\n", 5795 ioc_status); 5796 goto out_failed; 5797 } 5798 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5799 5800 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5801 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, driver_pg1, pg_sz)) { 5802 ioc_err(mrioc, "driver page1 read failed\n"); 5803 goto out_failed; 5804 } 5805 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5806 ioc_err(mrioc, "driver page1 read failed with ioc_status(0x%04x)\n", 5807 ioc_status); 5808 goto out_failed; 5809 } 5810 return 0; 5811 out_failed: 5812 return -1; 5813 } 5814